waashk/dblp huggingface dataset:
layout-driven area-constrained timing optimization by net buffering. with the advent of deep sub-micron technologies, interconnect loads and delays are becoming significant, and layout-driven synthesis has become the need of the day. however, given the tight constraints imposed by the layout (e.g., area availability, congestion), only those synthesis transforms can be made layout-driven that are local and layout-friendly. examples of such transforms are net buffering, gate resizing, and gate replication.in this paper, we address the problem of minimizing the delay of a mapped, roughly placed, and globally-routed design by buffer insertion and/or deletion without violating the local area constraints imposed by the layout and without overloading any buffer/cell pins. we believe this is the one of the most fundamental problems in layout-driven buffer optimization. to the best of our knowledge, no technique has been published to date that solves this problem. the concept of local (or block) area constraints we use in this paper is more powerful than that of the total design area traditionally-used in logic synthesis.our main contributions are the following: 1. we propose an exact, layout-driven net buffering algorithm to minimize the delay of an extended net under the area constraint of each block in the design. 2. we propose a simple yet effective scheme for applying the single-net algorithm to an entire design. 3. we apply our technique successfully on three real, large, industrial designs. the largest design (172k gates and 211k nets) could be optimized in about 20 minutes. the technique is remarkably effective when the available area in the design is small: it generates 6-9 times better delay improvements than the unconstrained delay minimization technique [8] modified to handle area constraints. over an entire range of available areas, it gives about 115% better delay improvements.
wta: waveform-based timing analysis for deep submicron circuits. existing static timing analyzers make several assumptions about circuits, implicitly trading off accuracy for speed. in this paper we examine the validity of these assumptions, notably the slope approximation to waveforms, single-input transitions, and the choice of a propagating signal based on a single voltage-time point. we provide data on static cmos gates that show delays obtained in this way can be optimistic by more than 30%. we propose a new approach, waveform-based timing analysis that employs a state-of-the-art circuit simulator as the underlying delay modeler. we show that such an approach can achieve more accurate delays than slope-based timing analyzers at a computation cost that still allows iterations between design modification and delay analysis.
oscillator-ac: restoring rigour to linearized small-signal analysis of oscillators. standard small-signal analysis methods for circuits break down for oscillators because small input perturbations result in arbitrarily large output changes, thus invalidating fundamental assumptions for small-signal analysis. in this paper, we propose a novel oscillator-ac (oac) approach remedying this situation, thus restoring validity and rigour to small-signal analysis of oscillators. our approach centers around a novel, general equation formulation for circuits that we term the gempde. a key feature of our approach is to solve for bivariate frequency variables with the help of novel augmenting phase condition equations. our gempde-based small-signal analysis provides both amplitude and frequency characteristics in a unified manner and is applicable to any kind of oscillator described by differential equations. we obtain speedups of 1-2 orders of magnitude over the transient simulation approach commonly used today by designers for oscillator perturbation analysis. we also demonstrate and explain how our linearization approach captures the inherently nonlinear phenomenon of injection locking in oscillators.
code placement with selective cache activity minimization for embedded real-time software design. many embedded system designs usually impose (hard)read-time constraints on tasks. thus, computing a tight upper boundof the worst case execution time (wcet) of a software is a criticallyimportant, but difficult task. the difficulty arises particularlywhen the code is executed on processors with cache-based memorysystems. in this paper, we propose a new code placement techniqueunder cache activity consideration for real-time software design.specifically, unlike the previous approaches which have triedto minimize total cache misses, which is not necessarily the bestway to meet all timing constraints of tasks, we minimizes the cachemisses in a selective way for tasks according to the degree of tightness(or urgency) of their timing constraints. based on a concept ofselective cache activity minimization, we propose a new approachwhich solves the code placement problem in two steps: (step 1) wetransform the code placement problem into so called an interval selectionproblem, which then we formulate into a 0-1 integer linearprogramming (ilp); (step 2) we apply an efficient approximationalgorithm, called code-map, to solve the exact code placementformulation obtained in step.
performance optimization under rise and fall parameters. typically, cell parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. the performance optimization algorithms, however, assume a single value for each parameter. no work has been done to study the impact of separate rise and fall values on the complexity of optimization. in this paper, we take the first step towards understanding this impact. we pick two problems that have polynomial-time complexities if a single value for each cell parameter is assumed. the first problem is that of buffer insertion on a fixed topology net to maximize the required time at the source of the net. the second is the gate resizing problem (and the more general technology mapping problem) for minimizing the circuit delay under the simplest, load-independent delay model. we show that under separate rise and fall parameters, both these problems become np-complete. to the best of our knowledge, this is the first such result showing the effect of rise and fall parameters on the complexity of performance optimization problems. we then address the important question of devising a good practical algorithm for local fanout optimization.
on the global fanout optimization problem. fanout optimization is a fundamental problem in timing optimization. most of the research has focussed on the fanout optimization problem for a single net (or the local fanout optimization problem lfo). the real goal, however, is to optimize the delay through the entire circuit by fanout optimization. this is the global fanout optimization (gfo) problem. touati claims in his thesis [6] that visiting nets of the network in a reverse topological order (from primary outputs to inputs), applying the optimum lfo algorithm to each net, computing the new required time at the source and propagating the delay changes to the fanins yields a provably optimum solution to the gfo problem. this result implies that gfo is solvable in polynomial time if lfo is. in this paper, we show that that is not the case. we prove that gfo is np-complete even if there are a constant number of buffering choices at each net. we analyze touati's result and point out the flaw in his argument. we then present sufficient conditions for the optimality of the reverse topological algorithm.
delay and bus current evaluation in cmos logic circuits. an accurate and fast analytical technique for computing the delay and the maximum supply current in a cmos inverter is presented. it accounts for the effects of input slope, output load, transistor size, and short-circuit current. the accuracy is within 10% of the hspice level-3 model and the speed is more than three orders of magnitude faster than hspice. an extension of this technique is shown for the calculation of the delay and the maximum supply current of a chain of inverters, without recourse to integration. an efficient method for computing the total current waveform of the chain is also presented. the relative speed of computing the current waveform exceeds two orders of magnitude compared to hspice
code partitioning for synthesis of embedded applications with phantom. in a large class of embedded systems, dynamic multitasking using traditional os techniques is infeasible because of memory and processing overheads or lack of operating systems availability for the target embedded processor. serializing compilers have been proposed as an alternative solution, enabling a designer to develop multitasking applications without the need of os support. a serializing compiler is a source-to-source translator that takes a posix compliant multitasking c program as input and generates an equivalent, embedded processor independent, single-threaded ansi c program, to be compiled using the embedded processor-specific tool chain. such serializing compilers work by partitioning each task into blocks of code and synthesizing a scheduler that dynamically switches among these blocks. the quality of the compiled code in terms of multitasking overhead and task latency is highly dependent on the partitioning algorithm. in this work, we give our solution to the partitioning problem in the context of serializing compilers. we show that it is possible to provide the designer with a set of pareto-optimal solutions that trade off multitasking overhead for task latency.
soi transistor model for fast transient simulation. progress in semiconductor process technology has made soitransistors one of the most promising candidates for high performanceand low power designs. with smaller diffusion capacitances,soi transistors switch significantly faster than theirtraditional bulk mos counterparts and consume less power perswitching. however, design and simulation of soi mos circuits ismore challenging due to more complex behavior of an soi transistorinvolving floating body effects, delay dependence on history oftransistor switching, bipolar effect and others. this paper isdevoted to developing a fast table model of soi transistors, suitablefor use in fast transistor level simulators. we propose usingbody charge instead of body potential as an independent variableof the model to improve convergence of circuit simulation integrationalgorithm. soi transistor has one additional terminal comparedwith the bulk mosfet and hence requires larger tables tomodel. we propose a novel transformation to reduce number oftable dimensions and as a result to make the size of the tables reasonable.the paper also presents efficient implementation of oursoi transistor table model using piece-wise polynomial approximation,nonuniform grid discretization, and splitting the transistormodel into the model of its equilibrium and non equilibrium states.the effectiveness of the proposed model is demonstrated byemploying it in a fast transistor level simulator to simulate highperformance industrial soi microprocessor circuits.
performance-driven simultaneous place and route for island-style fpgas. abstract: sequential place and route tools for fpgas are inherently weak at addressing both wirability and timing optimizations. this is primarily due to the difficulty of accurately predicting wirability and delay during placement. a new performance-driven simultaneous placement/routing technique has been developed for island-style fpga designs. on a set of industrial designs for xilinx 4000-series fpgas, our scheme produces 100% routed designs with 8%-15% improvement in delay when compared to the xilinx xact5.0 place and route system.
power estimation techniques for integrated circuits. with the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (vlsi) circuits is becoming a critical concern. accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. recently, a variety of power estimation techniques have been proposed, most of which are based on: 1) the use of simplified delay models, and 2) modeling the long-term behavior of logic signals with probabilities. the array of available techniques differ in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. in this tutorial, i will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, i will try to explain the different assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.
module placement on bsg-structure and ic layout applications. a new method of packing the rectangles (modules) is presented with applications to ic layout design. it is based on the bounded-sliceline grid (bsg) structure. the bsg dissects the plane into rooms associated with binary relations ``right-to''and ``above'' such that any two rooms are uniquely in either relation. a packing is obtained through an assignment of modules on the bsg, followed by physical realization bsg-pack. a simulated annealing searches for a good packing of all packings by changing the assignments. experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with a quite good quality in area efficiency. a wide adaptability is demonstrated specific to ic layout design. remarkable examples are: the chip is not necessarily rectangle, l-shaped modules and modules which are allowed to partially overlap each other can be handled.
channel-driven global routing with consistent placement (extended abstract). a global router with its consistent placer is proposed which aims to control wire-densities of channels. the routing order of nets and their routes are decided according to the channel which is predicted to have the maximum wire-density. the placer distributes the nets evenly with respect to the virtual length (half perimeter of the bounding box). interesting features included are the interactive dynamic test to decide the form of predicting functions and the admissible region to consider the routing resources in placement stage. experiments reveal some interesting phenomena that smaller maximum wire-density is attained in spite of comparable total wire-density and that smaller maximum wire-length in spite of larger total wire-length.
amplification of ultrawideband signals. one of the main implementation challenges in the ultrawide-band(uwb) radio is the design of efficient amplifiers. the difficultyin amplifying an uwb signal stems from its bandwidth beinga large fraction of the amplifier gain-bandwidth product. this paperdescribes a methodology and the tradeoffs associated with thedesign of uwb amplifiers. the amplifiers are designed to minimizea new performance metric, which we refer to as the effectivenoise figure (nf). the effective nf measures the degradationcaused by the amplifier in the achievable receiver performance afterthe digital decoding process, which is ultimately the most relevantmeasure of performance.
reachability analysis using partitioned-robdds. in this paper, we address the problem of finite state machine (fsm) traversal, a key step in most sequential verification and synthesis algorithms. we propose the use of partitioned-robdds to reduce the memory explosion problem associated with symbolic state space exploration techniques. in our technique, the reachable state set is represented as a partitioned-robdd different partitions of the boolean space are allowed to have different variable orderings and only one partition needs to be in memory at any given time. we show the effectiveness of our approach on a set of iscas89 benchmark circuits. our techniques result in a significant reduction in total memory utilization. for a given memory limit, partitioned-robdd based method can complete traversal for many circuits for which monolithic robdds fail. for circuits where both partitioned-robdds as well as monolithic-robdds cannot complete traversal, partitioned-robdds can reach a significantly larger set of states.
static timing analysis for self resetting circuits. static timing analysis techniques are widely used to verify the timing behavior of large digital designs implemented predominantly in conventional static cmos. these techniques, however, are not sufficient to completely verify the dynamic circuit families now finding favor in high-performance designs. in this paper, we describe an approach that extends static timing analysis to a high-performance dynamic cmos logic family called self-resetting cmos. due to the circuit structure employed in srcmos, designs naturally decompose into a hierarchy of gates and macros; timing analysis must address and preferably exploit this hierarchy. at the gate level, three categories of constraints on pulse timing arise from considering the effects of pulse width, overlap, and collisions. timing analysis is performed at the macro level, by a) performing timing tests at macro boundaries and b) using macro-level delay models. we define various macro-level timing tests which ensure that fundamental gate-level timing constraints are satisfied. we extend the standard delay model to handle leading and trailing edges of signal pulses, across-chip variations, tracking of signals, and slow and fast operating conditions. we have developed an srcmos timing analyzer based on this approach; the analyzer was implemented as extensions to a standard static timing analysis program, thus facilitating its integration into an existing design system and methodology.
configuring multiple scan chains for minimum test time. the high test time for serial scan designs can be reduced by the use of multiple scan chains. the problem of optimally constructing multiple scan chains so as to minimize the overall test time is considered. rather than following the traditional practice of using equal length chains, the chains are allowed to be of different lengths; this can lead to lower test times. the main idea of this approach is to assign those scan elements that are more frequently accessed to shorter scan chains. given a design with n scan elements, and given that k scan chains are to be used for applying tests, an algorithm of complexity o(kn2) is presented for configuring the chains such that the overall test application time is minimized. by analyzing a range of circuit topologies, test time reductions as large as 40% over equal length chain configurations are demonstrated
low power logic synthesis for xor based circuits. an abundance of research efforts in low power logic synthesis have so far been focused on and/or or nand/nor based logic. a typical approach is to first generate an initial multi- level and/or or nand/nor representation of a boolean function. next, the representation is optimized in terms of power. however, there are major classes of circuits such as arithmetic functions which have sizable and/or representations but have very compact and/xor representations. for these functions and/or based optimization approach often yields poor results. in this paper, we put forth a paradigm for low power logic synthesis based on and/xor representations of boolean functions. specifically, we propose transforming a boolean function into a fixed polarity reed muller form that allows us to efficiently synthesize xor trees and and trees with provably minimum switching activity. preliminary experimental results show that we attain good power savings with negligible area overhead and often area reduction when compared to conventional and/xor based synthesis methods and the berkeley sis system.
a methodology for the computation of an upper bound on nose current spectrum of cmos switching activity. currents injected by cmos digital circuit blocks into the powergrid and into the substrate of a system-on-a-chip may affect reliabilityand performance of other sensitive circuit blocks. to verify thecorrect operation of the system, an upper bound for the spectrum ofthe noise current has to be provided with respect to all possible transitionsof the circuit inputs. the number of input transitions is exponentialin the number of circuit inputs. in this paper, we present anovel approach for the computation of the upper bound that avoidsthe untractable exhaustive exploration of the entire space. its computationalcomplexity is indeed linear in the number of gates. ourapproach requires cmos standard cell libraries to be characterizedfor injected noise current. in this paper, we also present an approachfor this characterization of cmos standard cells. experimental resultshave proven the accuracy of both the algorithm and the noisecurrent models used for the library characterization.
the care and feeding of your statistical static timer. the integrated circuit fabrication process has inevitable imperfections and fluctuations that had resulted in ever-growing systematic and random variations in the electrical parameters of active and passive devices fabricated as stated in s. nassif (2001). the impact of such variations on various aspects of chip performance has been the subject of numerous recent papers, and techniques for analyzing and dealing with such variability roadly labeled design for manufacturability (dfm) - are emerging from research laboratories to practical implementation and deployment, and several service companies are actively engaged in implementing and promoting dfm techniques amongst semiconductor design and manufacturing organizations.
efficient verification of hazard-freedom in gate-level timed asynchronous circuits. this paper presents an efficient method for verifying hazard freedomin timed asynchronous circuits. timed circuits are a classof asynchronous circuits that utilize explicit timing informationfor optimization throughout the entire design process. in asynchronouscircuits, correct operation requires that there are no hazardsin the circuit implementation. therefore, when designing anasynchronous circuit, each internal node and output of the circuitmust be verified for hazard-freedom to ensure correct operation.current verification algorithms for timed asynchronous circuits requirean explicit state exploration often resulting in state explosionfor even modest sized examples. the goal of this work isto abstract the behavior of internal nodes and utilize this informationto make a conservative determination of hazard-freedom foreach node in the circuit. experimental results indicate that thisapproach is substantially more efficient than existing timing verificationtools. these results also indicate that this method scaleswell for large examples. it is capable of analyzing circuits in lessthan a second that could not be previously analyzed. while thismethod is conservative in that some false hazards may be reported,our results indicate that the number of false hazards is small.
high-level area and power estimation for vlsi circuits. this paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multi-level implementation of the combinational logic. the proposed area model is based on transforming the given multi-output boolean function description into an equivalent single-output function. the model is empirical, and results demonstrating its feasibility and utility are presented. also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. high-level power estimates based on the total capacitance estimates and average activity estimates are also presented.