waashk/dblp huggingface dataset:
valid clocking in wavepipelined circuits. an analysis of valid clock rates in wavepipelined circuits using a technique called timed boolean functions is presented. it is shown that the valid intervals for the clock period can be disconnected. thus, it is insufficient to known only the minimum valid clock period in guaranteeing proper operation of pipelined circuits. analytic expressions for the valid clock intervals in terms of both topological delay and two-vector longest and shortest delays are provided. also uncertainties arising from manufacturing are taken into account. some potential difficulties in computing the exact valid clock intervals are illustrated by demonstrating discontinuity and nonmonotonicity of the harmonic number h(&tau;) (the number of valid simultaneous data waves allowed) as a function of the clock period &tau;
leakage power modeling and reduction with data retention. in this paper, we study leakage power reduction using power gating in the forms of the virtual power/ground rails clamp (vrc) and multi-threshold cmos (mtcmos) techniques. we apply power gating to two circuit types: memory-based units and datapath components. using a microarchitecture-level power simulator, as well as power and timing models derived from detailed circuit designs, we further study leakage power modeling and reduction at the system level for modern high-performance vliw processors. we show that the leakage power can be over 40% of the total power for such processors. moreover, we propose time-out scheduling of vrc to reduce power up to 85.65% for l2 cache. this power savings results in close to 1/3 total power dissipation for the vliw processors we study.
statistical based link insertion for robust clock network design. we present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. monte carlo simulations show that the robustness of the final clock network can be significantly improved with a small increase in wire length.
capturing time-of-flight delay for transient analysis based on scattering parameter macromodel. the delay associated with transmission line networks consists of the exponentially charging time and a pure propagation delay. this propagation delay, so called time-of-flight delay, is particularly evident in long lines. when the time-of-flight is comparable to the input rise-time, it is difficult to capture the time-of-flight with a finite sum of exponentials. therefore the time-of-flight must be captured explicitly from the transfer function of the circuit. in this paper, we give a precise definition of the time-of-flight together with some basic properties, and present an efficient method to capture the time-of-flight for general interconnect networks. based on our scattering parameter macromodel, we can easily capture the time-of-flight during the network reduction while using lower order model to evaluate the charging delay. by capturing the time-of-flight delay, the accuracy of system responses can be greatly improved without significantly increasing computing time.
on the interaction between power-aware fpga cad algorithms. as field-programmable gate array (fpga) power consumptioncontinues to increase, lower power fpga circuitry, architectures,and computer-aided design (cad) tools need to be developed.before designing low-power fpga circuitry, architectures, orcad tools, we must first determine where the biggest savings (interms of energy dissipation) are to be made and whether thesesavings are cumulative. in this paper, we focus on fpga cadtools. specifically, we describe a new power-aware cad flow forfpgas that was developed to answer the above questions.estimating energy using very detailed post-route power and delaymodels, we determine the energy savings obtained by our power-awaretechnology mapping, clustering, placement, and routingalgorithms and investigate how the savings behave when thealgorithms are applied concurrently. the individual savings of thepower-aware technology-mapping, clustering, placement, androuting algorithms were 7.6%, 12.6%, 3.0%, and 2.6%respectively. the majority of the overall savings were achievedduring the technology mapping and clustering stages of the power-awarefpga cad flow. in addition, the savings were mostlycumulative when the individual power-aware cad algorithmswere applied concurrently with an overall energy reduction of 22.6%.
partitioning and reduction of rc interconnect networks based on scattering parameter macromodels. this paper presents a linear time algorithm to reduce a large rc interconnect network into subnetworks which are approximated with lower order equivalent rc circuits. the number of rc elements can be reduced between 50% and 90%. instead of increasing approximation order for a network with large number of ports which will result in inefficiency at best and ill-conditioned matrices at worst, we partition the original network into several subnetworks, each of which is approximated by lower order model. the reduced circuits are guaranteed to be stable. the experiment results show that the number of circuit elements in a reduced network is o(n) for typical clock networks, where n is the number of external ports. the simulation time can be reduced by two to three orders of magnitude while the response of the reduced circuits is within five percent of that of the original circuits.
the design and optimization of soc test solutions. we propose an integrated technique for extensive optimization of the final test solution for system-on-chip using simulated annealing. the produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. we have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.
actif: a high-level power estimation tool for analog continuous-time-filters. a tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time ota-c filter when given only high-level input parameters such as dynamic range and signal swing. when used in combination with estimators for other building blocks (adc's, dac's, mixers,...) a truly high-level analog system exploration becomes feasible such as needed for architectural exploration of telecom systems. in literature only fundamental relations exist for analog filters, that predict the power with an error of orders of magnitude, which makes them hard to use in real system design. actif combines existing filter synthesis methods with new behavioral models for transconductance stages in a novel way to obtain an optimized high-level yet accurate power estimation. to verify the presented approach, two recently published design examples are compared with the results from actif.
instruction selection using binate covering for code size optimization. we address the problem of instruction selection in code generation for embedded dsp microprocessors. such processors have highly irregular data-paths, and conventional code generation methods typically result in inefficient code. instruction selection can be formulated as directed acyclic graph (dag) covering. conventional methods for instruction selection use heuristics that break up the dag into a forest of trees and then cover them independently. this breakup can result in suboptimal solutions for the original dag. alternatively, the dag covering problem can be formulated as a binate covering problem, and solved exactly or heuristically using branch-and-bound methods. we show that optimal instruction selection on a dag in the case of accumulator-based architectures requires a partial scheduling of nodes in the dag, and we augment the binate covering formulation to minimize spills and reloads. we show how the irregular data transfer costs of typical dsp data-paths can be modeled in the binate covering formulation.
full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flop insertion. in this paper, we study the full-chip interconnect power modeling.we show that repeater insertion is no longer sufficient toachieve the target frequencies specified by itrs, and develop concurrentrepeater and ff insertion schemes. considering structuralinterconnects, layer assignment and concurrent repeater andff insertion for delay specification, we develop a cycle-accuratemicroarchitecture-level interconnect power simulation. the simulationreduces the over-estimation by up to 2:46x compared topower estimation based on purely stochastic interconnects and fixedswitching factor. furthermore, we show that interconnect pipelininghas a lower ipc but can improve throughput by up to 2.03x.this indicates that the traditional design flow optimizing ipc andclock frequency separately may no longer be valid.
backend cad flows for "restrictive design rules". to meet challenges of deep-subwavelength technologies (particularly 130 nm and following), lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and rets like altpsm. for emerging technologies (65 nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the design-silicon flow. this has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. we have been exploring how design might take advantage of these restrictions, and present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of opc/ret algorithms and the accuracy of models of manufactured products. we also believe that the underlying technology, including simulation and analysis, may be applicable to a variety of approaches to design for manufacturability (dfm).
cad computation for manufacturability: can we save vlsi technology from itself? every 18 to 24 months, the areal density of vlsi doubles and the predicted date for the end of cmos scaling is pushed out approximately 18 to 24 months. this rate of growth has been controlled mainly by the increasing capabilities of lithographic patterning. however, the rate of improvement of lithography systems in key physical parameters such as illumination wavelength has begun to slow. to make up the shortfall, lithography has increasingly turned to using cad tools to transform the geometric shapes in designs into shapes on photomasks which have been compensated for systematic pattern-distorting effects. as the requirements for this compensation grow, however, it becomes increasingly difficult to hide in post-tapeout data preparation, and must be considered in back-end design tools and methodologies. we describe a number of the challenges to lithographic patterning, highlighting the factors that limit "physical scaling" and introduce the layout-to-mask shape transformations that compensate for these limitations. we describe the implementation of these transformations in general-purpose and specialized cad tools, pointing out challenges like growth of computation effort. finally, we describe how limitations of post-tapeout compensation drive the need for "litho-aware" physical design tools, showing examples in cell design, place-and-route, and layout migration.
register assignment through resource classification for asip microcode generation. application specific instruction-set processors (asips) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design specifications, accommodation of design errors, and product evolution. however, code generation for asips is a complex problem and new techniques are needed for its success. the register assignment task can be a critical phase, since often in asips, the number and functionality of available registers is limited, as the designer has opted for simplicity, speed, and low area. intelligent use of register files is critical to the program execution time, program memory usage and data memory usage. this paper describes a methodology utilizing register classes as a basis for assignment for a particular style of asip architectures. the approach gives preference to special purpose registers which are the scarce resources. this naturally leads to the objectives of high speed and low program memory usage. the approach has been implemented in a system called codesyn and used on custom asip architectures.
circuit simulation of nanotechnology devices with non-monotonic i-v characteristics. as research begins to explore potential nanotechnologiesfor future post-cmos integrated systems, modeling andsimulation environments must be developed that canaccommodate the corresponding problem complexity and non-traditionaldevice characteristics. this paper describes a circuit-levelsimulator that can accommodate an important class ofnanotechnology devices that are characterized by non-monotonici-v characteristics. employing adaptively controlledexplicit integration method (aces) and piecewise linear (pwl)device models, the proposed approach effectively overcomesthe convergence problems and multiple equilibrium pointsolution problems caused by the negative differentialresistance (ndr) regions in such device i-v functions.importantly, the aces approach can address the circuit sizeproblem when partitioning is included, and providecompatibility with simple i-v device model tables, therebyavoiding the need for analytical device models that rarely areavailable for nanotechnology devices.
system level design with spade: an m-jpeg case study. in this paper we present and evaluate the spade (system level performance analysis and design space exploration) methodology through an illustrative case study. spade is a method and tool for architecture exploration of heterogeneous signal processing systems. in this case study we start from an m-jpeg application and use spade to evaluate alternative multi-processor architectures for implementing this application. spade follows the y-chart paradigm for system level design; application and architecture are modeled separately and mapped onto each other in an explicit design step. spade permits architectures to be modeled at an abstract level using a library of generic building blocks, thereby reducing the cost of model construction and simulation. the case study shows that spade supports efficient exploration of candidate architectures; models can be easily constructed, modified and simulated in order to quickly evaluate alternative system implementations.
optimal wire sizing and buffer insertion for low power and a generalized delay model. we present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. our algorithms are able to minimize dynamic power dissipation subject to given timing constraints. in addition, we compute the complete power-delay tradeoff curve for added flexibility. we extend our algorithm to take into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. the effectiveness of these methods is demonstrated experimentally.
power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. the soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistors switching. to ensure the design quality of power delivery, extensive transient power grid simulations need to be performed during design process. however, the traditional circuit simulation engines are not scaled as well as the complexity of power delivery, as a result, it often takes a long runtime and huge memory requirement to simulate a medium size power grid circuit. in this paper, we develop and present a new efficient transient simulation algorithm for power distribution. the proposed algorithm, tlm-adi (transmission-line-modeling alternating-direction-implicit), first models the power delivery structure as transmission line mesh structure, then solves the transient mna matrices by the alternating-direction-implicit method. the proposed algorithm, with linear runtime and memory requirement, is also unconditionally stable which ensures that the time-step is not limited by any stability requirement. extensive experimental results show that the proposed algorithm is not only orders of magnitude faster than spice but also extremely memory saving and accurate.
flip-flop insertion with shifted-phase clocks for fpga power reduction. although the lut (look-up table) size of fpgas has been optimized for general applications, complicated designs may contain a large number of cascaded luts between flip-flops. this results in unwanted glitch propagation along the luts, and wastes power. this paper proposes a flip-flop insertion, we propose insertion of new flip-flops between adjacent existing flip-flops to minimize glitch propagation and power loss. each new flip-flop is timed by a phase-shifted clock with the phase calculated from the delays of luts and routing paths. this is different from traditional retiming methods that use the original clock or an 180-degree clock for the new flip-flops, and thus alters the original pipeline structure and synchronization. we start from a post-layout design, retiming its clock frequency and timing behavior. multiple flip-flop insertion is an np-complete problem because each new flip-flop affects the delays in the design. we have devised a glitch generation and propagation model for lut-based fpgas that take account of path delays while supporting reasonable complexity. we propose effective heuristics for flip-flop insertion and clock phase selection. full-chip measurements, including all the overheads associated with the inserted flip-flops, show that our approach shows up to 38% of the total dynamic power. we have analyzed our scheme, showing the mechanics of clock assignment and glitch minimization, and the sources of power reduction.
efficient instruction encoding for automatic instruction set design of configurable asips. application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. a common approach used in the design of such instructions is to convert application-specific operation patterns into new complex instructions. however, processors with a fixed instruction bitwidth cannot accommodate all the potentially interesting operation patterns, due to the limited code space afforded by the fixed instruction bitwidth. we present a novel instruction set synthesis technique that employs an efficient instruction encoding method to achieve maximal performance improvement. we build a library of complex instructions with various encoding alternatives and select the best set of complex instructions while satisfying the instruction bitwidth constraint. we formulate the problem using integer linear programming and also present an effective heuristic algorithm. experimental results using our technique generate instruction sets that show improvements of up to 38% over the native instruction set for several realistic benchmark applications running on a typical embedded risc processor.
challenges in power-ground integrity. with the advance of semiconductor manufacturing, eda, and vlsi design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. this trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to ir-drop, l di/dt noise, or lc resonance. therefore, power-ground integrity becomes a serious challenge in designing future high-performance circuits. in this paper, we will introduce power-ground integrity, addressing its importance, verification methodology, and problem solution.
an efficient statistical analysis methodology and its application to high-density drams. in this work, a new approach for the statistical worst case of full-chip circuit performance and parametric yield prediction, using both the modified-principal component analysis (mpca) and the gradient method (gm), is proposed and verified. this method enables designers not only to predict the standard deviations of circuit performances but also track the circuit performances associated with the process shift by measuring e-tests. this new method is validated experimentally during the development and production of high density drams. our contributions to statistical circuit design are as follows: 1) a method for directly generating a parametrized model associated with electrical test data 2) the first application to high density drams using the true statistical method
a novel framework for multilevel routing considering routability and performance. we propose in this paper a novel framework for multilevel routing considering both routability and performance. the two-stage multilevel framework consists of coarsening followed by uncoarsening. unlike the previous multilevel routing, we integrate global routing, detailed routing, and resource estimation together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. further, the exact routing information obtained at each level makes our framework more flexible in dealing with various routing objectives (such as crosstalk, power, etc). experimental results show that our approach obtains significantly better routing solutions than previous works. for example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the previous multilevel routing, the three-level routing, and the hierarchical routing can complete routing for only 3, 0, 3 circuits, respectively. in particular, the number of routing layers used by our router is even smaller. we also have performed experiments on timing-driven routing. the results are also very promising.
a min-cost flow based detailed router for fpgas. routing for fpgas has been a very challenging problem dueto the limitation of routing resources. although the fpgarouting problem has been researched extensively, most algorithms route one net at a time, and it can cause the net-ordering problem.in this paper, we present a detailed routing algorithm forfpgas based on min-cost flow computations. using themin-cost flow approach, our algorithm routes all the netsconnected to a common logic module simultaneously. ateach stage of the network flow computation, we guaranteeoptimal result in terms of routability and delay cost. for further improvement, we adopt an iterative re nement scheme based on the lagrangian relaxation technique. the lagrangian relaxation approach transforms the routing problem into a sequence of lagrangian subproblems. at each iteration of the algorithm, lagrangian subproblems are solvedby our min-cost flow based routing algorithm. any violationof congestion constraints is reflected in the value of corresponding lagrangian multiplier. the lagrangian multipliers are incorporated into the cost of each routing rosource nodeand guide the router.because our min-cost flow based algorithm minimizes costfunction while it maximizes the flow, our algorithm findscongestion-free routing solutions with minimum total delay.comparison with vpr router shows that our router usesless or equal number of routing tracks with smaller criticalpath delay as well as total routing delay.