waashk/dblp huggingface dataset:
hybrid cmos-sttram non-volatile fpga: design challenges and optimization approaches. research efforts to develop a novel memory technology that combines the desired traits of non-volatility, high endurance, high speed and low power have resulted in the emergence of spin torque transfer-ram (sttram) as a promising next generation universal memory. however, the prospect of developing a non-volatile fpga framework with sttram exploiting its high integration density remains largely unexplored. in this paper, we propose a novel cmos-sttram hybrid fpga framework; identify the key design challenges; and propose optimization techniques at circuit, architecture and application mapping levels. simulation results show that a sttram based optimized fpga framework achieves an average improvement of 48.38% in area, 22.28% in delay and 16.1% in dynamic power for iscas benchmark circuits over a conventional cmos based fpga design.
power supply signal calibration techniques for improving detection resolution to hardware trojans. chip design and fabrication is becoming increasingly vulnerable to malicious activities and alternations with globalization. an adversary can introduce a trojan designed to disable and/or destroy a system at some future time (time bomb) or the trojan may serve to leak confidential information covertly to the adversary. this paper proposes a taxonomy for trojan classification and then describes a statistical approach for detecting hardware trojans that is based on the analysis of an ics power supply transient signals. a key component to improving the resolution of power analysis techniques to trojans is calibrating for process and test environment (pe) variations. the main focus of this research is on the evaluation of four signal calibration techniques, each designed to reduce the adverse impact of pe variations on our statistical trojan detection method.
fault tolerant placement and defect reconfiguration for nano-fpgas. when manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. until now, the most pervasive methods used to address reliability, involve injecting spare resources. however, these methods use predetermined spare placement that is not optimized for each netlist. this is the first work (to the best of our knowledge) that addresses the problem of fault tolerance for nano-fpgas at the placement stage; fault tolerant placements are generated that are amenable to fast defect reconfiguration through replacement of defective logic elements with spares. we propose a simulated-annealing based placement algorithm that produces placements with the objective of maximizing the chances of successful recovery from faults in logic elements within the circuit's timing constraints. in addition, our study of the fault reconfiguration problem shows it is np-complete, and we propose a fast scheme for achieving a good reconfiguration solution for a random or clustered fault map. experimental results show that these techniques can increase the probability of successful fault reconfiguration by 55% (compared to a uniform spare distribution scheme), without significantly degrading the circuit performance.
path-ro: a novel on-chip critical path delay measurement under process variations. as technology scales to 45nm and below, process variations will present significant impact on path delay. this trend makes the deviation between simulated path delay and actual path delay in a manufactured chip more significant. in this paper, we propose a new on-chip path delay measurement structure called path-based ring oscillator (path-ro). the proposed method creates an oscillator from a targeted path for which it is used to measure path delay on-chip under the impact of process variations. to alleviate accuracy degradation caused by the architecture itself, a high-accuracy calibration process is presented. through experimental results on path-ros inserted in itc'99 b19 benchmark, we obtain path delay distribution under different process variations. the accuracy and efficiency of path delay measurement using path-ro are also verified by comparing the results obtained from post-layout hspice simulations.
steel: a technique for stress-enhanced standard cell library design. mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in mosfet channels, which results in enhanced carrier transport. new fabrication steps strive to increase carrier mobility which, consequently, increases both ion and ioff in cmos devices. however, most stress-enhancement techniques are dependent on layout parameters and their effects can be exploited within standard cell library design. in this work, we propose a new standard cell library design methodology that shares vdd and vss source/drain connections across standard cell boundaries. such sharing allows for increased channel stress in both the corresponding device as well as its neighboring devices. using an industrial 65nm process and standard cell library, we show that our standard cell design methodology can be seamlessly integrated into current, state-of-the-art digital ic design flows. the new shared source/drain technique improves critical path delay by 11% on average over a number of benchmarks for only a ~35% increase in leakage. further-more, stress-enhanced standard cell libraries offer a superior power/delay tradeoff compared to dual-vth across a wide range of operating points with reduced manufacturing costs. specifically, our stress-enhanced library (with a single vth) consumes ~2.5x less leakage than its dual-vth counterpart.
to sat or not to sat: ashenhurst decomposition in a large scale. functional decomposition is a fundamental operation in logic synthesis. prior bdd-based approaches to functional decomposition suffer from the memory explosion problem and do not scale well to large boolean functions. variable partitioning has to be specified a priori and often restricted to a few bound-set variables. moreover, non-disjoint decomposition requires substantial sophistication. this paper shows that, when ashenhurst decomposition (the simplest and preferable functional decomposition) is considered, both single and multiple-output decomposition can be formulated with satisfiability solving, craig interpolation, and functional dependency. variable partitioning can be automated and integrated into the decomposition process without the bound-set size restriction. the computation naturally extends to nondisjoint decomposition. experimental results show that the proposed method can effectively decompose functions with up to 300 input variables.
race analysis for systemc using model checking. systemc is a system-level modeling language that offers a wide range of features to describe concurrent systems at different levels of abstraction. the systemc standard permits simulators to implement a deterministic scheduling policy, which often hides concurrency-related design flaws. we present a novel compiler for systemc that integrates a formal and scalable race analysis. this analysis combines both classic static analysis and model checking techniques. the outcome of the analysis is not only valuable to diagnose the effect of race conditions, but can also be used to improve simulation performance dramatically. our compiler produces a simulator that uses the race analysis information at runtime to perform partial-order reduction, thereby eliminating context switches that do not affect the result of the simulation. experimental results show simulation speedups of one order of magnitude and better.
obstacle-avoiding rectilinear steiner tree construction. in today's vlsi designs, there can be many blockages in a routing region. the obstacle-avoiding rectilinear steiner minimum tree (oarsmt) problem has become an important problem in the physical design stage of vlsi circuits. this problem has attracted a lot of attentions in research and several approaches have been proposed to solve this problem effectively. in this paper, we will present a heuristic maze routing based approach to solve this oarsmt problem. it is commonly believed that maze routing based approaches can only handle small scale problems and there is a lack of an effective multi-terminal variant to handle multi-pin nets in practice. we will show in this paper that maze routing based approaches can also handle large scale oarsmt problems effectively. our approach is based on the searching process as in maze routing and can handle multi-pin nets very well in both solution quality, running time and memory space usage. we have compared our results with those of the previous works and can show that we can out-perform the best previous results on this problem [15] by giving an oarsmt with 2.01% less wire length on average and can make a 27.04% improvement in wire length in comparison with a lower bound of the optimal solution on average, while the running times are all very short and comparable to those in [15]. besides, due to the flexibility of maze routing, we can handle different kinds of obstacles with different convex or concave rectilinear shapes directly without a need to partition each blockage into a set of rectangular sub-blockages, which will increase the size of the problem.
impulse sensitivity function analysis of periodic circuits. this paper describes an efficient method to characterize the impulse sensitivity function (isf) of a periodic circuit via periodic ac (pac) analysis. the paper extends the application of isf from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. recognizing that the generalized isf is a subset of a time-varying impulse response, the isf is efficiently computed based on periodic time-varying system analysis techniques. compared to the previous isf characterization method based on transient simulations, a speedup of ~5x is achieved.
constrained aggressor set selection for maximum coupling noise. in this paper, we consider the problem of selecting a set of aggressor nets that maximize crosstalk induced noise or delay pushout on a coupled victim net, under given logical constraints. we formulate the problem mathematically, and propose efficient lagrangian relaxation and network flow based approaches that guarantee an optimal solution. we also formulate and solve this problem while considering the noise susceptibility of the victim's receiving gate. experimental results show that the proposed approaches are run-time efficient by factors of up to 800x in comparison to an exhaustive search approach, and reduce timing pessimism by up to 36%.
using test data to improve ic quality and yield. the complexity of interactions in today's manufacturing processes makes test structures and experiments inadequate as sole drivers of yield-learning and design-for-manufacturing [dfm]. they must be driven by product impact. product-impact-oriented test-based learning provides insight into the nature of model-hardware mismatches and variability that exist on and impact real products. that insight can be used to drive both parametric and defect-oriented process actions and dfm.
layout decomposition for double patterning lithography. in double patterning lithography (dpl) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. however, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. in such cases, dpl requires that a layout feature be split into two parts. we address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. we evaluate our technique on both real-world and artificially generated testcases in 45nm technology. experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. there are no design rule violations in the final decomposed layout.
fbt: filled buffer technique to reduce code size for vliw processors. vliw processors provide higher performance and better efficiency etc. than risc processors in specific domains like multimedia applications etc. a disadvantage is the bloated code size of the compiled application code. therefore, reducing the application code size is a design key issue for vliw processors. in this paper we adapt a hardware-supported approach called "deflate" [12] which has been used before in data compression. it can significantly reduce the code size compared to state-of-the-art approaches for vliw processors as we will show within this work. in fact, we enhance the "deflate" algorithm by using a new technique called filled buffer technique which can be applied to any lempel-ziv family algorithms to improve compression ratio in average by more than 13% compared to the sole "deflate" algorithm. using our filled buffer technique in conjunction with "v2f" [15] improves the compression ratio by 10%. we have conducted evaluations using a representative set of benchmarks (from mediabench and mibench) and have applied our scheme to two vliw processors, namely tms320c62x and tms320c64x. we achieved allover compression ratios as low as 44% using the "deflate" algorithm (61% and 56% in average for tms320c62x and tms320c64x, respectively).
performance optimization of elastic systems using buffer resizing and buffer insertion. buffer resizing and buffer insertion are two transformation techniques for the performance optimization of elastic systems. different approaches for each technique have already been proposed in the literature. both techniques increase the storage capacity and can potentially contribute to improve the throughput of the system. each technique offers a different trade-off between area cost and latency. this paper presents a method that combines both techniques to achieve the maximum possible throughput while minimizing the cost of the implementation. the provided method is based on mixed integer linear programming. a set of experiments is designed to show the feasibility of the approach.
a low-overhead fault tolerance scheme for tsv-based 3d network on chip links. three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. through silicon vias (tsvs) provide a promising area- and power-efficient way to support communication between different stack layers. unfortunately, low tsv yield significantly impacts design of three-dimensional die stacks with a large number of tsvs. this paper presents a defecttolerance technique for tsvs-based multi-bit links through an efficient and effective use of redundancy. this technique is ideally suited for three-dimensional network-on-chip (noc) links. simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a noc switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of vlsi design and test flows.
robust reconfigurable filter design using analytic variability quantification techniques. in this paper, we develop a variability-aware design methodology for reconfigurable filters used in multi-standard wireless systems. to model the impact of statistical circuit component variations on the predicted manufacturing yield, we implement several different analytic variability quantification techniques based on a double-sided implementation of the first and second order reliability methods (form and sorm), which provide several orders of magnitude improvement in computational complexity over statistical sampling methods. leveraging these efficient analytic variability quantification techniques, we employ an optimization approach using sequential quadratic programming to simultaneously determine the fixed and tunable/switchable circuit element values in an arbitrary-order canonical filter to improve the overall robustness of the filter design when statistical variations are present. the results indicate that reconfigurable filters and impedance matching networks designed using the proposed methodology meet the specified performance requirements with a 26% average absolute yield improvement over circuits designed using deterministic techniques.
context-sensitive static transistor-level ir analysis. with advances in semiconductor process technology, chip power density has dramatically increased, making power grid integrity a critical concern at all stages of the design process. given the inherent difficulty of capturing worst-case ir drops for all logic gates with dynamic vectors, a static flow is essential for verifying grid integrity on complex chip designs, especially microprocessors. a novel static transistor-level ir drop analysis flow which significantly reduces the conservatism of other static flows is presented. the key feature of this flow is a fast nand decision diagram (ndd) algorithm, a lightweight variant of a boolean decision diagram (bdd) with the capacity to effectively process device transition exclusions in a per logical-device, context-sensitive fashion, thereby radically reducing the conservatism typical of static analysis.
advancing supercomputer performance through interconnection topology synthesis. in today's many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. in this paper, we propose a design flow to discover the best topology in terms of the communication latency and physical constraints. first a set of representative candidate topologies are generated for the interconnection networks among computing chips; then an efficient multi-commodity flow algorithm is devised to evaluate the performance. the experiments show that the best topologies identified by our algorithm can achieve better average latency compared to the existing networks.
fastroute3.0: a fast and high quality global router based on virtual capacity. as an easily implemented approach, ripup and reroute has been employed by most of today's global routers, which iteratively applies maze routing to refine solution quality. but traditional maze routing is susceptible to get stuck at local optimal results. in this work, we will present a fast and high quality global router fastroute3.0, with the new technique named virtual capacity. virtual capacity is proposed to guide the global router at maze routing stage to achieve higher quality results in terms of overflow and runtime. during maze routing stage, virtual capacity works as a substitute for the real edge capacity in calculating the maze routing cost. there are two sub techniques included: (1) virtual capacity initialization, (2) virtual capacity update. before the maze routing stage, fastroute3.0 initializes the virtual capacity by subtracting the predicted overflow generated by adaptive congestion estimation (ace) from the real edge capacity. and in the following maze routing iterations, we further reduce the virtual capacity by the amount of existing overflow (edge usage minus real edge capacity) for the edges that are still congested. to avoid excessive "pushing-away" of routing wires, the virtual capacity is increased by a fixed percentage of the existing overflow if edge usage is smaller than real edge capacity. experimental results show that fastroute3.0 is highly proficient dealing with ispd98, ispd07 and ispd08 benchmark suites. the results outperform published ripup and reroute based academic global routers in both routability and runtime. in particular, (1) fastroute3.0 completes routing all the ispd98 benchmarks. (2) for ispd07 and ispd08 global routing contest benchmarks, it generates 12 out of 16 congestion free solutions. (3) the total runtime is enhanced greatly.
a new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage. obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for dfm-aware nanometer ic design. in this paper, tcad device simulations are utilized to quantify the accuracy of a standard equivalent gate length extraction approach for non-rectangular transistors. it is verified that threshold voltage and current density are non-uniform along the channel width due to narrow-width related edge effects, leading to significant inaccuracy in the sub-threshold region. a new egl extraction method utilizing location-dependent weighting factors and convex parameter extraction techniques is proposed to account for the current density non-uniformity. preliminary results verified by tcad simulations indicate that the accuracy of leakage current estimation for non-rectangular transistors can be significantly improved. the method is readily applicable to calibration with real silicon data.
parameterized transient thermal behavioral modeling for chip multiprocessors. in this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for high-performance chip-multiprocessor (cmp) design. we propose a new approach, called parthermpof, to build the parameterized thermal performance models from the given architecture thermal and power information. the new method can include a number of parameters such as the locations of thermal sensors in a heat sink, different components (heat sink, heat spread, core, cache, etc.), thermal conductivity of heat sink materials, etc. the method consists of two steps: first, response surface method based on low-order polynomials is applied to build the parameterized models at each time point for all the given sampling nodes in the parameter space. second, an improved generalized pencil-of-function (gpof) method is employed to build the transfer-function based behavioral models for each time-varying coefficient of the polynomials generated in the first step. experimental results on a practical quad-core microprocessor show that the generated parameterized thermal model matchs the given data very well. parthermpof is very suitable for design space exploration and optimization where both time and system parameters need to be considered.