waashk/dblp huggingface dataset:
novel wire density driven full-chip routing for cmp variation control. as nanometer technology advances, the post-cmp dielectric thickness variation control becomes crucial for manufacturing closure. to improve cmp quality, dummy feature filling is typically performed by foundries after the routing stage. however, filling dummy features may greatly degrade the interconnect performance and lead to explosion of mask data. it is thus desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. in this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. to fully consider wire distribution, the router applies a novel two-pass, top-down planarity-driven routing framework, which employs a new density critical area analysis based on voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental delaunay triangulation. experimental results show that our methods can achieve more balanced wire distribution than state-of-the-art works.
fastroute: a step to integrate global routing into placement. because of the increasing dominance of interconnect issues in advanced ic technology, placement has become a critical step in the ic design flow. to get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. however, previous global routers are computationally expensive. it is impractical to perform global routing repeatedly during placement. in this paper, we present an extremely fast and high-quality global router called fastroute. in traditional global routing approaches, congestion is not considered during steiner tree construction. so they have to rely on the time-consuming maze routing technique to eliminate routing congestion. different from traditional approaches, we proposed a congestion-driven steiner tree topology generation technique and an edge shifting technique to determine the good steiner tree topologies and steiner node positions. based on the congestion-driven steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. we also proposed a new cost function based on logistic function to direct the maze routing. experimental results show that fastroute generates less congested solutions in 132x and 64x faster runtimes than the state-of-the-art academic global routers labyrinth [1] and chi dispersion router [2], respectively. it is even faster than the highly-efficient congestion estimator fadglor [3]. the promising results make it possible to incorporate global routing directly into placement process without much runtime penalty. this could dramatically improve the placement solution quality. we believe this work will fundamentally change the way the eda community look at and make use of global routing in the whole design flow.
eco timing optimization using spare cells. we introduce in this paper a new problem of eco timing optimization using spare-cell rewiring and present the first work for this problem. spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. the spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost. for the addressed problem, we present a framework of buffer insertion and gate sizing to handle it. in this framework, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming (dcp), for the eco timing optimization with spare cells. without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. the whole framework is integrated into a commercial design flow. experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of eco paths.
algorithms for mis vector generation and pruning. ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. the main reason to omit this effect is the run time penalty and potential over-conservatism. run times are directly proportional to the vector sizes. efficient algorithms are presented that prune the multiple input switching (mis) vector set to a worst-case covering using a boolean logic abstraction of the gate. this non-physical representation reduces the vector size to approximately n vectors for an n-input gate. this is effectively the same vector set size as the optimal single input switching vector set. there are no errors for 88% the simulations using a monty-carlo coverage on a 90nm static library, and the magnitude of the errors are less than 5% on average.
skew aware polarity assignment in clock tree. in modern sequential vlsi designs, clock tree plays an important role in synchronizing different components in a chip. to reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. althogh peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. as a result, a timing-aware signal polarities assigning technique is necessary. in this paper, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. the experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skew produced by three algorithms (partition, mst, matching) [5] are 235%, 272%, and 283%, respectively. moreover, our algorithm is as efficient as the three algorithms of [5] in reducing peak current and power/ground noises.
high-level synthesis challenges and solutions for a dynamically reconfigurable processor. a dynamically reconfigurable processor (drp) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. our drp architecture has a stand alone finite state machine and that switches "contexts" consisting of many operational and storage units in processing elements (pes) and wires between them. utilizing the resources not only in two spatial dimensions but also vertically (time-multiplexed) under accurate timing and area constraints imposes challenges for a high-level synthesizer for the drp. we describe a c-based behavioral synthesis method which features data path generation with clock speed optimization. this is achieved by including the overhead of selectors in the scheduling algorithm, and considering a wire delay at each pe level. a new technique is introduced to achieve high area efficiency. it works by effectively allocating multiple steps into the context. from the original highlevel synthesizer for application-specific integrated circuits, some of the basic rules such as operator and register sharing were completely changed due to the coarse grained and multi-context architecture. experimental results show that the generated data paths are highly parallelized and well balanced between contexts. the delay controllability enables the highest throughput point to be found more easily.
an efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. during the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. in this paper, we introduce several important properties of the surge current during the power mode transition for the distributed sleep transistor network (dstn) designs. based on these properties, we propose an accurate estimation of surge current and provide an efficient schedule on the dstn structure. our experiment achieved significantly better results than previous works---on average, 332 times wake-up time reduction and 35.48% less energy loss during the power mode transition.
decomposing image computation for symbolic reachability analysis using control flow information. the main challenge in bdd-based symbolic reachability analysis is represented by the sizes of the intermediate decision diagrams obtained during image computations. methods proposed to mitigate this problem fall broadly into two categories: search strategies that depart from breadth-first search, and efficient techniques for image computation. in this paper we present an algorithm that belongs to the latter category. it exploits define-use information along executable paths extracted from the control-flow graph of the model being analyzed; this information enables an effective constraining of the transition relation and a decomposition of the image computation process that often leads to much smaller intermediate bdds. our experiments confirm that this reduction in the size of the representation of state sets translates in significant decreases in cpu and memory requirements.
temperature aware microprocessor floorplanning considering application dependent power load. this paper studies microprocessor floorplanning considering thermal and throughput optimization. we first develop a stochastic heat diffusion model taking into account the application dependent power load for thermal analysis. then, we design the floorplanning algorithm based on this model. experimental results show that, compared with the deterministic heat diffusion model, our model obtains up to 3.2&deg;c reduction of the on-chip peak temperature, 1.25% reduction of the area, and 1.125x better cpi (cycles per instruction) performance, respectively. compared with temperature aware floorplanning in the hotspot tool set that ignores interconnect pipelining, our algorithm is up to 27x faster, reduces the peak temperature by up to 3&deg;c, and also reduces cpi significantly with a negligible area overhead.
increasing data-bandwidth to instruction-set extensions through register clustering. the conflicting requirements of performance and flexibility in today's embedded system market are forcing system designers to use more and more of the so called configurable or customizable processor cores. such processors tend to meet the demanding performance constraints by accommodating application specific instruction-set extensions (ises) which have, naturally, become a vital component of current processor customization flows. one major bottleneck in maximizing ise performance is the limitation on the data-bandwidth between the general purpose register(gpr) file and the ises. for improved performance, it is desirable to have a large data-bandwidth from the gprs to ises. however, the tight area constraints of modern embedded processors often restrict the gpr i/o of ises to save port area of the register files. this paper presents a novel approach to increase the gpr i/o of ises without significantly increasing the size of the gpr files. this is achieved by applying the concept of register clustering, common in many vliw architectures, to single-issue processors with high performance ises. such clustering often causes extra register moves in compiled code. this work also presents an algorithm to minimize such register moves. the benchmark results presented in this paper show that our solution can significantly reduce the area overhead of many-port gpr files without sacrificing the performance improvements through ises.
boxrouter 2.0: architecture and implementation of a hybrid and robust global router. in this paper, we present boxrouter 2.0, a hybrid and robust global router with discussion on its architecture and implementation. as high performance vlsi design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. hence, we propose boxrouter 2.0 which has strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. boxrouter 2.0 is improved over [1], but can perform multi-layer routing with 2d global routing and layer assignment. our 2d global routing is equipped with two ideas: robust negotiation-based a* search for routing stability, and topology-aware wire ripup for flexibility. after 2d global routing, 2d-to-3d mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. experimental results show that boxrouter 2.0 has better routability with comparable wirelength than other routers on ispd07 benchmark, and it can complete (no overflow) ispd98 benchmark for the first time in the literature with the shortest wirelength.
scalable exploration of functional dependency by interpolation and incremental sat solving. functional dependency is concerned with rewriting a boolean function f as a function h over a set of base functions {g1, ..., gn}, i.e. f = h(g1, ..., gn). it plays an important role in many aspects of electronic design automation (eda), ranging from logic synthesis to formal verification. prior approaches to the exploration of functional dependency are based on binary decision diagrams (bdds), which may not be easily scalable to large designs. this paper proposes a novel reformulation that extensively exploits the capability of modern satisfiability (sat) solvers. thereby, functional dependency is detected effectively through incremental sat solving, and the dependency function h, if it exists, is obtained through craig interpolation. the main strengths of the proposed approach include: (1) fast detection of functional dependency with modest memory consumption and thus scalable to large designs, (2) a full capacity to handle a large set of base functions and thus discovering dependency whenever exists, and (3) potential application to large-scale logic optimization and verification reduction. experimental results show the proposed method is far superior to prior work and scales well in dealing with the largest iscas89 and itc99 benchmark circuits with up to 200k gates.
approximation algorithm for the temperature-aware scheduling problem. the paper addresses the problem of performance optimization for a set of periodic tasks with discrete voltage/frequency states under thermal constraints. we prove that the problem is np-hard, and present a pseudo-polynomial optimal algorithm and a fully polynomial time approximation technique (fptas) for the problem. the fptas technique is able to generate solutions in polynomial time that are guaranteed to be within a designer specified quality bound (qb) (say within 1% of the optimal). we evaluate our techniques by experimentation with multimedia and synthetic benchmarks mapped on the 70nm cmos technology processor. the experimental results demonstrate our techniques are able to match optimal solutions when qb is set at 5%, can generate solutions that are quite close to optimal (< 5%) even when qb is set at higher values (50%), and executes in few seconds (with qb > 25%) for large task sets with 120 nodes (while the optimal solution takes several hundred seconds). we also analyze the effect of different thermal parameters, such as the initial temperature, the final temperature and the thermal resistance.
performance and power evaluation of a 3d cmos/nanomaterial reconfigurable architecture. in this paper, we introduce a novel reconfigurable architecture, named 3d nfpga, which utilizes 3d integration techniques and new nanoscale materials synergistically. the proposed architecture is based on cmos-nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into cmos fabrication process. using unique features of fpgas and a novel 3d stacking method enabled by the application of nanomaterials, 3d nfpga obtains a 4.5x footprint reduction compared to traditional cmos-based 2d fpgas. with a customized design automation flow, we evaluate the performance and power of 3d nfpga driven by the 20 largest mcnc benchmarks. results demonstrate that 3d nfpga is able to provide a performance gain of 2.6x with a small power overhead comparing to the cmos 2d fpga architecture.
cachecompress: a novel approach for test data compression with cache for ip embedded cores. in this paper, we propose a novel test data compression technique named cachecompress, which combines selective encoding and dynamic dictionary based encoding. depending on the number of specified bits, a test data word is either encoded in a single code word or as a lookup in the dictionary. explicit dictionary initialization is not required since the content of the dictionary is updated during testing. the dictionary itself only contains the most recently used patterns, thus it exhibits a behaviour similar to a cache. experiments show that our technique achieves higher compression ratio than other recent compression schemes while the dictionary size has been dramatically reduced.
run-time adaptive on-chip communication scheme. during run-time varying workloads and/or constraints in embedded systems require run-time adaptivity to provide a high degree of efficiency during any operation mode/scenario. design time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. we are presenting the first approach of an adaptive on-chip communication scheme. it provides an adaptive routing/path allocation algorithm to meet a required level of qos (guaranteed bandwidth). in our architecture adaptive runtime links are established by re-assigning buffer blocks on-demand. this adaptive buffer allocation scheme increases the buffer utilization and decreases the overall buffer use on an average of 42% in our case study analysis compared to a fixed buffer assignment strategy. the area overhead introduced by the adaptive scheme can be traded-off against the flexibility in order to select an available path and on-demand buffer allocation. we demonstrate the advantage by using various real world digital media applications and compare our approach to the state-of-the-art static on-chip communication schemes.
a self-adjusting clock tree architecture to cope with temperature variations. ensuring resilience against environmental variations is becoming one of the great challenges of chip design. in this paper, we propose a self adjusting clock tree architecture, sacta, to improve chip performance and reliability in the presence of on-chip temperature variations. sacta performs temperature dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. we present an automatic temperature adjustable skew buffer design, which enables the adaptive feature of sacta. furthermore, we propose an efficient and general optimization framework to determine the configuration of these special delay elements. experimental results show that a pipeline supported by sacta is able to prevent thermal induced timing violations within a significantly larger range of operating temperatures (enhancing the violation-free range by as much as 45&deg;c).
device-circuit co-optimization for mixed-mode circuit design via geometric programming. modern processing technologies offer a number of types of devices such as high-vt, low-vt, thick-oxide, etc. in addition to the nominal transistor in order to meet system performance and functional needs. while designers have leveraged these devices for mixed-signal design, a design framework is needed to guide designers in selecting the best set of devices. the same framework can enable device manufacturers decide which new devices to include in the suite of device offerings. this paper presents a design methodology that can quickly guide a designer in selecting the best set of devices for a given application, specifications, and circuit structure. the equation-based optimization framework based on geometric programming (gp) extends upon previous efforts that optimize sizing, biasing, and supply voltages. the paper first shows that convex piecewise-linear function fitting can effectively model for optimization all the types of devices offered by a 90nm cmos technology. additionally, we show the potential to model and include experimental devices such as a schottky tunneling source mosfet. second, the paper applies the model to an example circuit, a track-and-hold amplifier. the optimization and subsequent simulation illustrate the importance and amount of benefit from applying device selection.
estimation of delay test quality and its application to test generation. as a method to evaluate delay test quality of test patterns, sdqm (statistical delay quality model) has been proposed for transition faults. in order to derive better test quality by sdqm, the following two things are important: for each transition fault, (1) to find out the accurate length of the longest sensitizable paths along which the fault is activated and propagated, and (2) to generate a test pattern that detects the fault through as long paths as possible. in this paper, we propose a method to calculate the length of the potentially sensitizable longest path for detection of a transition fault. in addition, we develop a procedure to extract path information that helps high quality transition atpg. experimental results show that the proposed method not only derives more accurate sdql (statistical delay quality level) but also enhances the test quality of generated test patterns.
3d-staf: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. thermal issues are a primary concern in the three-dimensional (3d) integrated circuit (ic) design. temperature, area, and wire length must be simultaneously optimized during 3d floorplanning, significantly increasing optimization complexity. most existing floorplanners use combinatorial stochastic optimization techniques, hampering performance and scalability when used for 3d floorplanning. in this work, we propose and evaluate a scalable, temperature-aware, force-directed floorplanner called 3d-staf. force-directed techniques, although efficient at reacting to physical information such as temperature gradients, must eventually eliminate overlap. this can cause significant displacement when used for heterogeneous blocks. to smooth the transition from an unconstrained 3d placement to a legalized, layer-assigned floorplan, we propose a three-stage force-directed optimization flow combined with new legalization techniques that eliminate white spaces and block overlapping during multi-layer floorplanning. a temperature-dependent leakage model is used within 3d-staf to permit optimization based on the feedback loop connecting thermal profile and leakage power consumption. 3d-staf has good performance that scales well for large problem instances. compared to recently published 3d floorplanning work, 3d-staf improves the area by 6%, wire length by 16%, via count by 22%, peak temperature by 6% while running nearly 4x faster on average.