waashk/dblp huggingface dataset:
a fast wavelet collocation method for high-speed vlsi circuit simulation. this paper presents a fast wavelet collocation method (fwcm) for high- speed circuit simulation. the fwcm has the following properties: (1) it works in the time domain, so that the circuit nonlinearity can be handled, and the accuracy of the result can be well controlled, unlike the method working in the frequency domain where the numerical error may get uncontrolled during the inverse laplace transform; (2) the wavelet property of localization in both time and frequency domains makes a uniform approximation possible, which is generally not found in the time marching methods; (3) it is very effective in treating the singularities often developed in high-speed ics due to the property of the wavelets; (4) calculation of derivatives at all collocation points is optimal and takes o(n\log n), where n is the number of collocation points; (5) an adaptive scheme exists; and (6) it has an o(h^4) convergence rate while the most existing methods only have an o(h^2) convergence rate, where h is the step length. numerical experiments further demonstrated the promising features of fwcm in high-speed ic simulation.
cost-effective radiation hardening technique for combinational logic. a radiation hardening technique for combinational logic circuits is described. the key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. the technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to spice). a full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.
an optimal algorithm for river routing with crosstalk constraints. with the increasing density of vlsi circuits, the interconnection wires are getting packed even closer. this has increased the effect of interaction between these wires on circuit performance and hence, the importance of controlling crosstalk. in this paper, we consider river routing with crosstalk constraints. given the positions of the pins in a single-layer routing channel and the maximum tolerable crosstalk between each pair of nets, we give a polynomial time algorithm to decide whether there is a feasible river routing solution and produce one with minimum crosstalk whenever the problem is feasible.
an exact gate decomposition algorithm for low-power technology mapping. with the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in ic designs. in technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. in the literature, only heuristic algorithms are given for the low-power gate decomposition problem. in this paper, we prove many properties an optimal decomposition tree must have. based on these optimality properties, we design an efficient exact algorithm to solve the low-power gate decomposition problem. moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics.
improving the efficiency of static timing analysis with false paths. we improve the efficiency of static timing analysis when false paths are considered. the efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. however, when false paths are dealt in timing analysis, a large number of tags need to be created and propagated, and thus deteriorated the efficiency. in this paper, we minimize the number of the tags through a biclique covering approach, which iteratively removes a tag if the false path information in the tag is covered by the union of other tags. the produced tags remove the false path timing and guarantee to cover the true path timings. since the minimum biclique covering of the general bipartite graph is np complete, we use a minimal degree ordering approach to perform the biclique covering minimization. the experimental results show significant reduction on the number of tags.
thermal characterization and optimization in platform fpgas. increasing power densities in field programmable gate arrays (fpgas) have made them susceptible to thermal problems. the advent of platform fpgas has further exacerbated the problems by increasing the power density variations on the fpga fabric. therefore, we need to characterize the die temperature of platform fpgas. in this paper, we first estimate the temperature distribution within a virtex-4 fpga by feeding the block power numbers in an architecture-level temperature simulator calibrated to reflect a real fpga package. we analyze the impact of different hard-wired blocks on the temperature profile, and observe that they introduce intra-die variation in temperature of up to 20&deg;c. next, we evaluate the influence of placement on temperature. our experiments indicate a decrease in peak temperature by changing the placement of hard blocks, especially the high-speed transceivers. we further propose an iterative placement technique to reduce the peak temperature, and apply it on real designs. finally, we propose alternate organizations of the hard blocks in the fpga fabric to reduce temperature.
optimal sizing of high-speed clock networks based on distributed rc and lossy transmission line models. we have proposed an efficient measure to reduce the clock skew by assigning the clock network with variable branch widths. this measure has long been used for ``h'''' clock tree. this paper formulates the optimal sizing of a general clock network as an optimization problem which minimizes the clock skew in a feasible set of widths. this feasible set of branch widths is decided by the process technology and routing resources. the skew minimization problem is turned into a least-squares estimation problem, and a modified gauss-marquardt''s method is then used to determine the optimal widths of clock branches. this optimization method combines the best features of the methods based on taylor series and methods based on gradients. an efficient algorithm is also proposed that assigns the good initial widths especially for a clock tree which let the later optimization process converge much more quickly. our method is very flexible and can handle the general clock network including loops. the clock network can exhibit distributed rc and lossy transmission line behaviors. the method employs a scattering-parameters based delay macromodel to evaluate the timing of the clock network during the optimization process. the major objective of our sizing method is to minimize the skew, but as a by-product that the largest path delay is also reduced.
a new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. low power design techniques such as voltage scaling, dual-vth etc. can have a large negative impact on parametric yield. in this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. the principal idea is to (a) isolate and predict the set of possible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. this allows us to operate the circuit at reduced supply voltage while achieving the required yield. simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. application of the proposed methodology to pipelined design is also investigated.
improving the robustness of a surface integral formulation for wideband impendance extraction of 3d structures. in order for parasitic extraction of high-speed integrated circuit interconnect to be sufficiently efficient, and fit with model-order reduction techniques, a robust wideband surface integral formulation is essential. one recently developed surface integral formulation has shown promise, but was plagued with numerical difficulties of poorly understood origin. in this paper we show that one of that formulation's difficulties was related to the inaccuracy in the approach to evaluate integrals over discretization panels, and we present an accurate approach based on an adapted piecewise quadrature scheme. we also show that the condition number of the original system of integral equations can be reduced by differentiating one of the integral equations. computational results on a ring and a spiral inductor are used to show that the new quadrature scheme and the differentiated integral formulation improve accuracy and accelerate the convergence of iterative solution methods.
trunk decomposition based global routing optimization. we present global routing optimization methods which are not based on rip-up and re-route framework. in particular, the routing optimization is based on trunk decomposition [13] of the global routing. in this framework, the route of a net is decomposed into sets of wiring segments. by viewing a wiring segment as an "atomic object" of perturbation, we can efficiently evaluate the effect of routing tree perturbation. we propose two complementary routing optimization methods, namely segment partitioning and segment migration. these targeted optimizers can improve congestion related routing objectives by quickly shuffling wiring segments across different routing channels. our routing approach produces better results compared to rip-up and re-route method based router labyrinth [14] with average total overflow reduction of more than 88% while taking only 61% of runtime required by ripup and reroute phase of labyrinth. when applied to the output of labyrinth, the approach, on average, reduces the total overflow by more than 97% with complete overflow elimination for four circuits, while requiring additional runtime of just 33%. on a larger benchmark suite, the total overflow reduction of more than 86% is obtained, with complete overflow elimination for eight circuits, while requiring only 19% additional runtime.
generator-based verification. to prove system correctness, assumptions made in verifying a blockmust be cleared by verifying that the block's environment guaranteesthem. conversely, guarantees enforced by a block may be usedas assumptions for its environment. block level interface specificationsthus serve as both assumptions and guarantees in compositionalverification. traditionally, such specifications have beenrepresented as monitors or checkers. in this paper, we propose analternative representation using generators. novel algorithms arepresented for simulation and formal verification. we argue that forsimulation, representation as a generator can be more efficient thanas a checker - both asymptotically and practically. we also identifya subset of generators that can be efficiently handled using formaltechniques. experimental results are given for some benchmarkexamples and industrial case studies.
on the use of bloom filters for defect maps in nanocomputing. while the exact manufacturing process for nanoscale computing devices is uncertain, it is abundantly clear that future technology nodes will see an increase in defect rates. therefore, it is of paramount importance to construct new architectures and design methodologies that can tolerate large numbers of defects. defect maps are a necessity in the future design flows, and research on their practical construction is essential. in this work, we study the use of bloom filters as a data structure for defect maps. we show that bloom filters provide the right tradeoff between accuracy and space-efficiency. in particular, they can help simplify the nanosystem design flow by embedding defect information within the nanosystem delivered by the manufacturers. we develop a novel nanoscale memory design that uses this concept. it does not rely on a voting strategy, and utilizes the device redundancy more effectively than existing approaches.
a hierarchical modeling framework for on-chip communication architectures. the communication sub-system of complex ic systems is increasingly critical for achieving system performance. given this, it is important that the on-chip communication architecture should be included in any quantitative evaluation of system design during design space exploration. while there are several mature methodologies for the modeling and evaluation of architectures of processing elements, there is relatively little work done in modeling of an extensive range of on-chip communication architectures, and integrating this into a single modeling and simulation environment combining processing element and on-chip communication architectures. this paper describes a modeling framework with accompanying simulation tools that attempts to fill this gap. based on an analysis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or variants of existing ones with relatively little incremental effort. we demonstrate this through three case studies including two commercial on-chip bus systems and an on-chip packet switching network. here we show that through careful analysis and construction it is possible for the modeling environment to support the common features of these architectures as part of the library and permit instantiation of the individual architectures as variants of the library design. as part of this methodology we also show how different levels of abstraction of the model can be supported and viewed as different variants that can be used in an accuracy versus simulation time trade-off.
verification of analog/mixed-signal circuits using labeled hybrid petri nets. system on a chip design results in the integration of digital, analog, and mixed-signal circuits on the same substrate which further complicates the already difficult validation problem. this paper presents a new model, labeled hybrid petri nets (lhpns), that is developed to be capable of modeling such a heterogeneous set of components. this paper also describes a compiler from vhdl-ams to lhpns. to support formal verification, this paper presents an efficient zone-based state space exploration algorithm for lhpns. this algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. finally, this paper describes the application of this algorithm to a couple of analog/mixed-signal circuit examples.
the effects of energy management on reliability in real-time embedded systems. the slack time in real-time systems can be used by recovery schemes to increase system reliability as well as by frequency and voltage scaling techniques to save energy. moreover, the rate of transient faults (i.e., soft errors caused, for example, by cosmic ray radiations) also depends on system operating frequency and supply voltage. thus, there is an interesting trade-off between system reliability and energy consumption. this work first investigates the effects of frequency and voltage scaling on the fault rate and proposes two fault rate models based on previously published data. then, the effects of energy management on reliability are studied. our analysis results show that, energy management through frequency and voltage scaling could dramatically reduce system reliability, and ignoring the effects of energy management on the fault rate is too optimistic and may lead to unsatisfied system reliability.
an accurate sparse matrix based framework for statistical static timing analysis. statistical static timing analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. to be useful, however, it is important that the error introduced in ssta be significantly smaller than the manufacturing variations being modeled. achieving such accuracy requires careful attention to the delay models and to the algorithms applied. in this paper, we propose a new sparse-matrix based framework for accurate path-based ssta, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the iscas89 benchmarks. our sparse-matrix based formulation has the following advantages: (a) it places no restrictions on process parameter distributions; (b) it embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) it takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. our experimental results are very promising.
color permutation: an iterative algorithm for memory packing. it is predicted that 70% of the silicon real-estate will be occupied by memories in future system-on-chips. the minimization of on-chip memory hence becomes increasingly important for cost, performance and energy consumption. in this paper, we present a reasonably fast algorithm based on iterative improvement, which packs a large number of memory blocks into a minimum-size address space. the efficiency of the algorithm is achieved by two new techniques. first, in order to evaluate each solution in linear time, we propose a new algorithm based on the acyclic orientation of the memory conflict graph. second, we propose a novel representation of the solution which effectively compresses the potentially infinite solution space to a finite value of n!, where n is the number of vertices in th memory conflict graph. furthermore, if a near-optimal solution is satisfactory, this value can be dramatically reduced to &chi;!, where &chi;! is the chromatic number of the memory conflict graph. experiments show that consistent improvement over scalar method by 30% can be achieved.
information theoretic approach to address delay and reliability in long on-chip interconnects. with shrinking feature size and growing integration density in the deep sub-micron technologies, the global buses are fast becoming the "weakest-links" in vlsi design. they have large delays and are error-prone. especially, in system-on-chip (soc) designs, where parallel interconnects run over large distances, the effects of crosstalk are detrimental to the overall system performance due to the large delays and un-reliability involved. this paper presents an information theoretic approach to address delay and reliability in long interconnects. a framework to calculate the capacity of a physical wire is laid out herein. the results for 8-bit wide buses of varying lengths in 0.1&mu;m technology are also presented. the wires are modeled based on their calculated parasitic (r, l, c) values and the coupling (c, l) parameters. using this model, results are obtained for the data transfer capacity of long interconnects. it is seen that for wide buses, the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. using communication-theory, these "good" signals arriving early can be used to predict/correct the "few" signals arriving late. further, results show that for every bus configuration, there exists an optimal frequency of transmission that will result in the maximum data transfer rate. also, this optimal frequency is higher than the pessimistic worst case delay based clock design.
fastsies: a fast stochastic integral equation solver for modeling the rough surface effect. in this paper we describe several novel sparsification techniques used in a fast stochastic integral equation solver to compute the mean value and the variance of capacitance of 3d interconnects with random surface roughness. with the combination of these numerical techniques, the computational cost has been reduced from o(n/sup 4/) to o(nlog/sup 2/(n)), where n is the number of panels used for the discretization of nominal smooth surfaces. numerical experiments show that the proposed numerical techniques are accurate and efficient.
designing application-specific networks on chips with floorplan information. with increasing communication demands of processor and memory cores in systems on chips (socs), scalable networks on chips (nocs) are needed to interconnect the cores. for the use of nocs to be feasible in today's industrial designs, a custom-tailored, application-specific noc that satisfies the design objectives and constraints of the targeted application domain is required. in this work, we present a design methodology that automates the synthesis of such application-specific noc architectures. we present a floorplan aware design method that considers the wiring complexity of the noc during the topology synthesis process. this leads to detecting timing violations on the noc links early in the design cycle and to have accurate power estimations of the interconnect. we incorporate mechanisms to prevent deadlocks during routing, which is critical for proper operation of nocs. we integrate the noc synthesis method with an existing design flow, automating noc synthesis, generation, simulation and physical design processes. we also present ways to ensure design convergence across the levels. experiments on several soc benchmarks are presented, which show that the synthesized topologies provide a large reduction in network power consumption (2.78x on average) and improvement in performance (1.59x on average) over the best mesh and mesh-based custom topologies. an actual layout of a multimedia soc with the noc designed using our methodology is presented, which shows that the designed noc supports the required frequency of operation (close to 900 mhz) without any timing violations. we could design the noc from input specifications to layout in 4 hours, a process that usually takes several weeks.
on channel segmentation design for row-based fpgas. the channel segmentation design problem for row-based field-programmable gate arrays (fpgas) is to design a segmented channel to maximize the probability of successful routing. an algorithm which takes an arbitrary net distribution and an integer k (specifying the maximum number of segments allowed in routing a net) as inputs, and automatically generates a segmented channel which is most suitable for k-segment channel routing is presented. the algorithm was tested extensively over various net distributions. an algorithm for segmented channel routing based on reducing the problem to the maximum independent set problem for undirected graphs is also presented
leakage power dependent temperature estimation to predict thermal runaway in finfet circuits. in this work we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. we target 28n m finfet based circuits as they are more prone to thermal runaway compared to bulk-mosfets. we generate thermal models for logic cells to self-consistently determine the temperature map of a circuit block. our proposed condition for thermal runaway shows the design trade off between the primary input (pi) activity of a circuit block, sub-threshold leakage at the room temperature and the thermal resistance of the package. we show that in finfet circuits, thermal runaway can occur at the itrs specified sub-threshold leakage (150na/&mu;m, highperformance) for a nominal pi activity of 0.5 and typical package thermal resistance.