waashk/dblp huggingface dataset:
formal derivation of optimal active shielding for low-power on-chip buses. passive shielding has been used to reduce capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between the bus lines. active shielding is another shielding technique, in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. this work formally derives the optimal active shielding logic function for minimum power dissipation. it is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (/spl gamma/ = c/sub c//c/sub g/). optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. a sub-optimal active shielding architecture with simpler hardware is also proposed. simulation results show that using the sub-optimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit.
serial-link bus: a low-power on-chip bus architecture. as technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. this paper proposes reducing the number of bus lines of the conventional parallel-line bus (plb) architecture by multiplexing each m-bits onto a single line. this bus architecture, the serial-link bus (slb), transforms an n-bit conventional plb into an n/m-line (serial link) bus. the advantage of slbs is that they have fewer lines, and if the bus width is kept the same, slbs will have a larger line pitch. increasing the line width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line width increases. also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. thus, an optimum degree of multiplexing mopt and an optimum width to pitch ratio ηopt exist, which minimizes the bus energy dissipation and maximizes the bus throughput per unit area. the optimum degree of multiplexing and optimum width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. hspice simulations show that for the same throughput per unit area as conventional parallel-line data buses, the slb architecture reduces the energy dissipation by up to 31% for a 64-bit bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology.
cache optimization for embedded processor cores: an analytical approach. embedded microprocessor cores are increasingly beingused in embedded and mobile devices. the softwarerunning on these embedded microprocessor cores is often apriori known, thus, there is an opportunity for customizingthe cache subsystem for improved performance. in thiswork, we propose an efficient algorithm to directly computecache parameters satisfying desired performance criteria.our approach avoids simulation and exhaustiveexploration, and, instead, relies on an exact algorithmicapproach. we demonstrate the feasibility of our algorithmby applying it to a large number of embedded systembenchmarks.
a design for testability technique for rtl circuits using control/data flow extraction. in this paper, we present a technique for extracting functional (control/data flow) information from register transfer level (rtl) controller/data path circuits and illustrate its use in design for hierarchical testability of these circuits. this testing procedure and design for testability (dft) technique is general enough to handle rtl control flow intensive circuits like protocol handlers as well as data flow intensive circuits like digital filters. it makes the combined controller-data path highly testable and does not require any external behavioral information. this scheme has the advantages of low area/delay/power overheads (average of 3.2%, 0.9% and 4.1%, respectively, for benchmarks), high fault coverage (over 99% for most cases), very low test generation times (because it is independent of bit-width), and the advantage of at-speed testing. experiments show a 2-to-4 (1-to-3) orders of magnitude test generation time advantage over an efficient gate-level sequential test generator (combinational test generator that assumes full scan).
fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring. a new method for the testing and fault detection of analog integrated circuits is presented. time-domain testing followed by spectral analysis of the power-supply current is used to detect both dc and ac faults. spectral analysis is applied since the tolerances on the circuit parameters make a direct comparison of waveforms impossible. for the fault detection a probabilistic decision rule is proposed based on a multivariate statistical analysis. since no extra testing pin is needed and the on-line calculation effort is small, the method can be used for wafer-probe testing as well as final production testing. in addition, a methodology for the selection of the input stimulus is presented that improves the test-ability. examples demonstrate the efficiency and the effectiveness of the algorithms.
interface and cache power exploration for core-based embedded system design. minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-on-a-chip, since interdependencies of design characteristics like power, performance, and area for various system parts (cores) become increasingly influential. in this scenario, interfaces play a key role since they allow one to control/exploit these interdependencies with the aim to meet design constraints like power. in this paper, we present the first comprehensive approach to explore this impact. we consider a whole system comprising a cpu, caches, a main memory and interfaces between those cores and demonstrate the high impact that an adequate adaptation between core parameters and interface parameters in terms of power consumption has. we especially found that cache parameters and bus configurations of cache buses have a significant impact in this respect. in addition, we made the important observation that optimizing for performance no longer implies that power is optimized as well in deep submicron technologies. instead, we found out that especially for newer technologies, the relative interface power contribution increases, leading to scenarios where we obtain a real power/performance tradeoff. in summary, our explorations unveiled not yet investigated interdependencies that represent the first step towards future efforts to optimize/adapt interfaces and caches in core-based systems for low power designs.
system-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip. in this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (soc) architecture to find all pareto-optimal configurations. these configurations represent the range of meaningful power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application mapped onto the soc architecture. our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. we have successfully incorporated our technique into the parameterized soc tuning environment (platune) and applied it to a number of applications.
test generation for bridging faults in cmos ics based on current monitoring versus signal propagation. bridge-type defects play a dominant role in state-of-the-art cmos technologies. this paper describes a combined functional and overcurrent-based test generation approach for cmos circuits, which is optionally based on layout information. comparative results for benchmark circuits are given to demonstrate the feasibility of voltage-based versus iddq-based testing.
false-noise analysis using logic implications. cross-coupled noise analysis has become a critical concern in today's vlsi designs. typically, noise analysis makes an assumption that all aggressing nets can simultaneously switch in the same direction. this creates a worst-case noise pulse on the victim net that often leads to false noise violations. in this paper, we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. we propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using robdd representations and a newly proposed laterial propagation method. we then show that the problem of finding the worst case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits and then extend our approach to timed implications. the proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. we demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this paper, underscoring the need for false-noise analysis.
delay noise pessimism reduction by logic correlations. high-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (sta) methods consider crosstalk-induced delay variation. current noise-aware sta methods compute noise-induced delay uncertainty for each net independently and annotate appropriate delay changes of nets onto data paths and associated clock paths to determine timing violations. since delay changes in individual nets contribute cumulatively to delay changes of paths, even small amounts of pessimism in noise computation of nets can add up to produce large timing violations for paths, which may be unrealistic. unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. in this paper, we propose a method to reduce pessimism in noise-aware sta by considering signal correlations of all nets associated with an entire timing path simultaneously, in a path-based approach. we first present an exact algorithm based on the branch-and-bound technique and then extend it with several heuristic techniques so that very large industrial designs can be analyzed efficiently. these techniques, which are implemented in an industrial crosstalk noise analysis tool, show as much as 75% reduction in the computed path delay variations.
negative thinking by incremental problem solving: application to unate covering. we introduce a new technique to solve exactly a discrete optimization problem, based on the paradigm of "negative" thinking. the motivation is that when searching the space of solutions, often a good solution is reached quickly and then improved only a few times before the optimum is found: hence most of the solution space is explored to certify optimality, but it does not yield any improvement of the cost function. so it is quite natural for an algorithm to be "skeptical" about the chance to improve the current best solution. for illustration we have applied our approach to the unate covering problem. we designed a procedure, raiser, implementing a negative thinking search, which is incorporated into a common branch-and-bound procedure. raiser is invoked at a node of the search tree which is deep enough to justify negative thinking. raiser tries to detect a hard core of the matrix corresponding to the node by augmenting an independent set of rows in order to increase incrementally the cost of the minimum solutions covering the matrix. eventually either raiser prunes the subtree rooted at the node (having found a lower bound equal or greater than the current best solution) or returns a new solution that becomes the current best one. experiments show that our program, aura, outperforms both espresso and our enhancement of espresso using coudert's limit lower bound. it is always faster and in the most difficult examples either has a running time better by up to two orders of magnitude, or the other programs fail to finish due to timeout or spaceout. the package scherzo is faster on some examples and loses on others, due to a less powerful pruning strategy of the search space, partially mitigated by a more effective computation of the maximal independent set.
a fast and robust exact algorithm for face embedding. we present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all faces of minimum length. increasing dimensions of the boolean space are explored; for a given dimension constraints are satisfied one at a time. the following features help to reduce the nodes of the solution space that must be explored: candidate cubes instead of candidate codes are generated, cubes yielding symmetric solutions are not generated, a smaller sufficient set of solutions (producing basic sections) is explored, necessary conditions help discard unsuitable candidate cubes, early detection that a partial solution cannot be extended to be a global solution prunes infeasible portions of the search tree. we have implemented a prototype package minsk based on the previous ideas and run experiments to evaluate it. the experiments show that minsk is faster and solves more problems than any available algorithm. moreover, minsk is a robust algorithm, while most of the proposed alternatives are not. besides most problems of the complete mcnc benchmark suite, other solved examples include an important set of decoder plas coming from the design of microprocessor instruction sets.
the impact of the nanoscale on computing systems. nanoscale technologies provide both challenges and opportunities. we show that the issues and potential solutions facing designers are technology independent and arise mainly from shrinking device sizes and an increase in the number of devices available. we explore how it is possible to use some of the devices that will be available to help ease design complexity as well as overcome process related challenges such as limited layout freedom, increased defect densities, timing constraints, and power dissipation.
factoring logic functions using graph partitioning. algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the boolean equations with no regard to physical properties and the dependent stage where mapping to a physical cell library is done. the independent stage includes logic operations like decomposition, extraction, factoring, substitution and elimination. these operations are done with some kind of division (boolean, algebraic), with the goal being to obtain a logically equivalent factored form which minimizes the number of literals.in this paper, we present an algorithm for factoring that uses graph partitioning rather than division. central to our approach is to combine this with the use of special classes of boolean functions, such as read-once functions, to devise new combinatorial algorithms for logic minimization. our method has been implemented in the sis environment, and an empirical evaluation indicates that we usually get significantly better results than algebraic factoring and are quite competitive with boolean factoring but with lower computation costs.
robust optimization based backtrace method for analog circuits. in this paper, we propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. the proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem (bvp), with constraints on the output state and the input. this error constraint minimizes large spurious deviations in the input signal and the corvergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. as an additional attractive advantage, this formulation preserves the core iteration structure of a spice-like simulator without modifications, greatly easing implementation.
on adaptive diagnostic test generation. adaptive diagnosis, a paradigm for diagnosis, is defined. a system based on this paradigm, for i_{ddq} measurement based diagnosis of bridging faults, is reported. experimental evaluation of the system shows it to be substantially superior to existing systems, especially for larger circuits.
storage assignment during high-level synthesis for configurable architectures. modern, high performance configurable architectures integrate on-chip, distributed block ram modules to provide ample data storage. synthesizing applications to these complex systems requires an effective and efficient approach to conduct data partitioning and storage assignment. in this paper, we present a data and iteration space partitioning solution that focuses on minimizing remote memory accesses or, equivalently, maximizing the local computation. using the same code but different data partitionings, we can achieve faster clock frequencies, without increasing the number of cycles, by simply minimizing global memory accesses. other optimization techniques like scalar replacement, prefetching and buffer insertion can further minimize remote accesses and lead to average 4.8/spl times/ speedup in overall runtime.
design of heterogeneous ics for mobile and personal communication systems. mobile and personal communication systems form key market areas for the electronics industry of the nineties. stringent requirements in terms of flexibility, performance and power dissipation, are driving the development of integrated circuits into the direction of heterogeneous single-chip solutions. new ic architectures are emerging which contain the core of a powerful programmable processor, complemented with dedicated hardware, memory and interface structures. in this tutorial we will discuss the real-life design of a heterogeneous ic for an industrial telecom application: a reconfigurable mobile terminal for satellite communication. based on this practical design experience, we will subsequently discuss a methodology for the design of heterogeneous ics. design steps that will be addressed include: system specification and refinement, data path and communication synthesis, and code generation for embedded processor cores.
direct transistor-level layout for digital blocks. we present a complete transistor-level layout flow, from logic netlist to final shapes, for blocks of combinational logic up to a few thousand transistors in size. the direct transistor-level attack easily accommodates the demands for careful custom sizing necessary in high-speed design, and is also significantly denser than a comparable cell-based layout. the key algorithmic innovations are (a) early identification of essential diffusion-merged mos device groups called clusters, but (b) deferred binding of clusters to a specific shape-level layout until the very end of a multi-phase placement strategy. a global placer arranges uncommitted clusters; a detailed placer optimizes clusters at shape level for density and for overall routability. a commercial router completes the flow. experiments comparing to a commercial standard cell-level layout flow show that, when flattened to transistors, our tool consistently achieves 100% routed layouts that average 23% less area.
efficient thermal placement of standard cells in 3d ics using a force directed approach. as the technology node progresses, thermal problems arebecoming more prominent especially in the developingtechnology of three-dimensional (3d) integrated circuits. thethermal placement method presented in this paper uses an iterativeforce-directed approach in which thermal forces direct cells awayfrom areas of high temperature. finite element analysis (fea) isused to calculate temperatures efficiently during each iteration.benchmark circuits produce thermal placements with both lowertemperatures and thermal gradients while wirelength is minimally affected.
addressing the timing closure problem by integrating logic optimization and placement. timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. in such a situation, logic synthesis and layout synthesis are iterated until the estimates match. the number of such iterations is becoming larger as technology scales. timing closure problems occur mainly due to the difficulty in accurately predicting interconnect delay during logic synthesis.in this paper, we present an algorithm that integrates logic synthesis and global placement to address the timing closure problem. we introduce technology independent algorithms as well as technology dependent algorithms. our technology independent algorithms are based on the notion of "wire-planning". all these algorithms interleave their logic operations with local and incremental/full global placement, in order to maintain a consistent placement while the algorithm is run. we show that by integrating logic synthesis and placement, we avoid the need to predict interconnect delay during logic synthesis. we demonstrate that our scheme significantly enhances the predictability of wire delays, thereby solving the timing closure problem. this is the main result of our paper. our results also show that our algorithms result in a significant reduction in total circuit delay. in addition, our technology independent algorithms result in a significant circuit area reduction.
new methods for speeding up computation of newton updates in harmonic balance. a new adaptive approach to solving large dimension harmonic balance (hb) problems is presented. the method is based on adjusting the order of the equation system according to the degree of nonlinearity of each node in the circuit. a block-diagonal preconditioner is used to construct an algorithm for order reducing during the iterative hb process.
counterexample-guided choice of projections in approximate symbolic model checking. bdd-based symbolic techniques of approximate reachability analysis based on decomposing the circuit into a collection of overlapping sub-machines (also referred to as overlapping projections) have been recently proposed. computing a superset of the reachable states in this fashion is susceptible to false negatives. searching for real counterexamples in such an approximate space is liable to failure. in this paper, the "hybridization effect" induced by the choice of projections is identified as the cause for the failure. a heuristic based on hamming distance is proposed to improve the choice of projections, that reduces the hybridization effect and facilitates either a genuine counterexample or proof of the property. the ideas are evaluated on a real large design example from the pci interface unit in the magic chip of the stanford flash multiprocessor.