waashk/dblp huggingface dataset:
a framework for testing core-based systems-on-a-chip. available techniques for testing core-based systems-on-a-chip (socs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions. in this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for socs. first, we develop a common ground for addressing issues such as core test requirements, core access and test hardware additions. for this purpose, we introduce finite-state automata for modeling tests, transparency modes and test hardware behavior. in many cases, the tests repeat a basic set of test actions for different test data which can again be modeled using finite-state automata. while earlier work can derive a single symbolic test for a module in a register-transfer level (rtl) circuit as a finite-state automation, this work extends the methodology to the system level, and, additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time. this problem is known to be a bottleneck in testability analysis not only at the system level, but also at the rtl. experimental results show that the system-level average area overhead for making socs testable with our method is only 4.4%, while achieving an average test application time reduction of 78.5% over recent approaches. at the same time, it provides 100% test coverage of the precomputed test sets/sequences of the embedded cores.
high-density reachability analysis. we address the problem of reachability analysis for large finite state systems. symbolic techniques have revolutionized reachability analysis but still have limitations in traversing large systems. we present techniques to improve the symbolic breadth-first traversal and compute a lower bound on the reachable states. we identify the problem as one of density during traversal and our techniques seek to improve the same. our results show a marked improvement on the existing breadth-first traversal methods.
multi-domain clock skew scheduling. the application of general clock skew scheduling is practicallylimited due to the difficulties in implementing a wide spectrum ofdedicated clock delays in a reliable manner. this results in a significantlimitation of the optimization potential. as an alternative,the application of multiple clocking domains with dedicatedphase shifts that are implemented by reliable, possibly expensivedesign structures can overcome these limitations and substantiallyincrease the implementable optimization potential of clock adjustments.in this paper we present an algorithm for constrained clockskew scheduling which computes for a given number of clockingdomains the optimal phase shifts for the domains and the assignmentof the individual registers to the domains. for the within-domainlatency values, the algorithm can assume a zero-skew clockdelivery or apply a user-provided upper bound. our experimentsdemonstrate that a constrained clock skew schedule using a fewclocking domains combined with small within-domain latency canreliably implement the full sequential optimization potential to dateonly possible with an unconstrained clock schedule.
modeling of ballistic carbon nanotube field effect transistors for efficient circuit simulation. carbon nanotube field-effect transistors (cnfets) arebeing extensively studied as possible successors to cmos.novel device structures have been fabricated and devicesimulators have been developed to estimate theirperformance in a sub 10nm transistor era. this paperpresents a novel method of circuit-compatible modeling ofcnfets in their ultimate performance limit. the model sodeveloped has been used to simulate arithmetic and logicblocks using hspice.
a circuit model for carbon nanotube interconnects: comparative study with cu interconnects for scaled technologies. semiconducting carbon nanotubes (cnt) have gained immense popularity as possible successors to silicon as the channel material for ultra high performance field effect transistors. on the other hand, their metallic counterparts have often been regarded as ideal interconnects for the future technology generations. owing to their high current densities and increased reliability, metallic-single walled cnts (swcnts) have been subjects of fundamental research both in theory as well as experiments. metallic cnts have been modeled for rf applications in (burke, 2003) using an lc model. we present an efficient circuit compatible rlc model for metallic sw cnts, and analyze the impact of sw cnts on the performance of ultra scaled digital vlsi design.
compactest-ii: a method to generate compact two-pattern test sets for combinational logic circuits. the problem of generating small (compact) test sets for single transition and cmos stuck-open faults in combinational logic circuits is considered. in addition, it is proposed that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. specifically, the problem of generating small and comprehensive test sets is addressed by considering the cmos stuck-open and the single transition fault models together. a dynamic test compaction technique for two-pattern tests is proposed. the technique exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. experimental results for iscas-85 combinational circuits and fully scanned versions of iscas-89 sequential circuits are presented to illustrate the efficacy of the proposed test compaction technique
true crosstalk aware incremental placement with noise map. crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. existing works to fix crosstalk noise are mostly done at the routing or post routing stage, which may be too late. since placement determines the overall routing congestion, which correlates with the coupling capacitance, which in turn correlates with the crosstalk noise, placement shall be a good level to do early noise mitigation. the only existing work for the crosstalk aware placement (to our best knowledge) is by lou and chen (2004), which uses the coupling capacitance map to guide placement. however, crosstalk is determined not only by the coupling capacitance, but also by many other factors, such as the driver resistance of the victim net and the coupling location (near source vs near sink coupling) (cong et al., 2001). we introduce a concept of noise map which takes those factors into account. guided by this accurate noise map explicitly, we propose an incremental placement technique to mitigate noise without disturbing the global placement order. our incremental placement has two key steps, namely noise aware cell inflation and local refinement. experimental results on industrial circuits show that our approach is able to reduce the number of top noise nets by 25% and improve the timing (300ps on the worst slack), with no wire length penalty or cpu overhead. our incremental approach is also able to maintain the placement stability.
a trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices. in this paper we present an approach to the nonlinear model reduction based on representing the nonlinear system with a piecewise-linear system and then reducing each of the pieces with a krylov projection. however, rather than approximating the individual components as piecewise-linear and then composing hundreds of components to make a system with exponentially many different linear regions, we instead generate a small set of linearizations about the state trajectory which is the response to a 'training input'. computational results and performance data are presented for a nonlinear circuit and a micromachined fixed-fixed beam example. these examples demonstrate that the macromodels obtained with the proposed reduction algorithm are significantly more accurate than models obtained with linear or the recently developed quadratic reduction techniques. finally, it is shown that the proposed technique is computationally inexpensive, and that the models can be constructed 'on-the-fly', to accelerate simulation of the system response.
leopard: a logical effort-based fanout optimizer for area and delay. we present leopard, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. our algorithm minimizes area under required timing and input capacitance constraints by finding the tree topology and assigning different gains to each buffer to minimize the total buffer area. experimental results show that the new algorithm achieves significant buffer area improvement compared to previous approaches.
co-synthesis of heterogeneous multiprocessor systems using arbitrated communication. we describe the first co-design technique aimed at heterogenous systems employing arbitrated communication. arbitrated system design is especially difficult because communication scheduling is directly tied to task allocation. the method provides a complete co-design&mdash;i.e. generation of a hardware configuration along with an allocation and schedule&mdash;for the execution of hard real-time data-dependent tasks. by using an actual scheduling analysis in the inner co-design loop, the method is readily able to address realistic system effects including various communication models like arbitration, as in pci-based systems.
metrics, techniques and recent developments in mixed-signal testing. this paper presents a tutorial on mixed-signal testing. our focus is on testing the analog portion of the mixed-signal device, as the digital portion is handled in the usual way. we begin by first outlining the role of test in a manufacturing environment, and its impact on product cost and quality. we look at the impact of manufacturing defects on the behavior of digital and analog circuits. subsequently, we argue that analog circuits require very different test methods than those presently used to test digital circuits. we then describe four common analog test methods and their measurement setups. we also describe how analog testing can be accomplished using digital sampling techniques. finally, we close this tutorial with a brief description of several developments presently underway on the design of testable mixed-signal circuits.
verification of delta-sigma converters using adaptive regression modeling. a new verification technique for &delta;&sigma; analog-to-digital converters (adc) is proposed. the adc is partitioned into functional blocks, and adaptive regression models for each partition are constructed using transistor-level simulation data. non-idealities in circuit behavior are captured by the adaptive regression technique from the collected data. the algorithms have been implemented in a simulation program arsim (adaptive regression simulator), which performs data sampling, model building, and simulation. experimental results using arsim are shown on a second-order &delta;&sigma; modulator, and they demonstrate the effectiveness of our technique as a fast and accurate approach for verifying &delta;&sigma; converters.
battery-aware power management based on markovian decision processes. this paper is concerned with the problem of maximizing capacity utilization of the battery power source in a portable electronic system under latency and loss rate constraints. first, a detailed stochastic model of a power-managed, battery-powered electronic system is presented. the model, which is based on the theories of continuous-time markovian decision processes and stochastic networks, captures two important characteristics of today's rechargeable battery cells, i.e., the current rate-capacity characteristic and the relaxation-induced recovery. next, the battery-aware dynamic power management problem is formulated as a policy optimization problem and solved exactly by using a linear programming approach. experimental results show that the proposed method outperforms existing heuristic methods for battery management by as much as 17% in terms of the average energy delivered per unit weight of battery cells.
hardware synthesis from guarded atomic actions with performance specifications. we present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. the methodology is based on rule composition, and relies on the fact that a rule derived by the composition of two rules behaves as if the two rules were scheduled simultaneously. rule composition is a well understood transformation in the trs theoretical framework; however, previous rule composition approaches resulted in an explosion of the number of rules during synthesis, making them impractical for realistic designs. we avoid this problem through composition of conditional actions which generates one rule instead of 2/sup n/ rules when we combine n rules. we then show how this conditional composition of rules can be compiled into an efficient hardware structure which introduces new but derived interfaces in modules. we demonstrate the approach via a small circuit example (gcd) and then show its impact on the methodology to implement pipelined processors in bluespec. many ways of dealing with branches in pipelined processors or bypassing values can be expressed simply as different schedules. the results show improvements in performance over previous rule-based synthesis approaches as well as the ease of performance-related architectural exploration. in a somewhat surprising result, we show that simply by specifying a different schedule, one can automatically transform a single-issue processor pipeline into a superscalar pipeline.
cellular wave computers and cnn technology - a soc architecture with xk processors and sensor arrays. cellular wave computers and cellular nonlinear network (cnn) technology are discussed in this paper. it is a system-on-chip (soc) architecture with xk processors and sensor arrays. the architectural lessons from the trends in manufacturing billion component devices when crossing the threshold of 100 nm feature size will determine the architecture, the elementary instructions, and the type of algorithms needed, hence also the complexity of the solution.
power-delay modeling of dynamic cmos gates for circuit optimization. we present an accurate analytical expression to compute power and delay of domino cmos circuits from a detailed description of internal capacitor switching and discharging currents. the expression obtained accounts for the main effects in complex sub-micron gates like velocity saturation effects, body effect, device sizes and coupling capacitors. the energy-delay product is also evaluated and analyzed. results are compared to hspice simulations (level 50) for a 0.18&mu;m cmos technology.
design of dna origami. the generation of arbitrary patterns and shapes at very small scales is at the heart of our effort to miniaturize circuits and is fundamental to the development of nanotechnology. here i review a recently developed method for folding long single strands of dna into arbitrary two-dimensional shapes using a raster fill technique - 'scaffolded dna origami'. shapes up to 100 nanometers in diameter can be approximated with a resolution of 6 nanometers and decorated with patterns of roughly 200 binary pixels at the same resolution. experimentally verified by the creation of a dozen shapes and patterns, the method is easy, high yield, and lends itself well to automated design and manufacture. so far, cad tools for scaffolded dna origami are simple, require hand-design of the folding path, and are restricted to two dimensional designs. if the method gains wide acceptance, better cad tools will be required.
power estimation tool for sub-micron cmos vlsi circuits. accurate and fast time-domain current waveform simulation is important for the design of reliable cmos vlsi circuits. a detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by spice level 3 at peak values and 5% at the average current is presented. the current model accounts for short-channel effects, input risetimes, short-circuit and dynamic current, and circuit topology. moreover, the model produces piecewise linear current waveforms and can be incorporated in any switch-level simulator. using the models in an event driven simulator, a 3-4 orders of magnitude speedup relative to spice level 3 has been achieved. the results for current waveform accuracy are better than those obtained for previously published methods and in particular for complex cmos circuits
thermal simulation techniques for nanoscale transistors. thermal simulations are important for advanced electronic systems at multiple length scales. a major challenge involves electrothermal phenomena within nanoscale transistors, which exhibit nearly ballistic transport both for electrons and phonons. the thermal device behavior can influence both the mobility and the leakage currents. we discuss recent advances in modeling coupled electron-phonon transport in future nanoscale transistors. the solution techniques involve solving the boltzmann transport equation (bte) for both electrons and phonons. we present a practical method for coupling an electron monte carlo simulation with an analytic "split-flux" form of the phonon bte. we use this approach to model self-heating in a 20 nm quasi-ballistic n+/n/n+ silicon diode, and to investigate the role of hot electron and hot phonon transport.
convexfit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. convex optimization has gained popularity due to its capability to reach global optimum in a reasonable amount of time. convexity is often ensured by fitting the table data into analytically convex forms such as posynomials. however, fitting the look-up tables into the posynomial forms with minimum error itself may not be a convex optimization problem and hence excessive fitting errors may be introduced. in this paper, we propose to directly adjust the look-up table values into a numerically convex look-up table without explicit analytical form. we show that numerically "convexifying" the table data with minimum perturbation can be formulated as a convex semidefinite optimization problem and hence optimality can be reached in polynomial time. without an explicit form limitation, we find that the fitting error is significantly reduced while the convexity is still ensured. as a result, convex optimization algorithms can still be applied. furthermore, we also develop a "smoothing" algorithm to make the table data smooth and convex to facilitate the optimization process. results from extensive experiments on industrial cell libraries demonstrate that our method reduces 30/spl times/ fitting error over a well-developed posynomial fitting algorithm. its application to circuit tuning is also presented.
automatic test generation for linear digital systems with bi-level search using matrix transform methods. a hierarchial testing approach for linear state variable digital systems based on matrix manipulation and constrained low-level test generation is reported. feast (functional extractor and sequential test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. crest (constrained sequential test generator) operates at the low level description of the individual modules, and generates test sets satisfying constraints imposed by the high-level modules and their interconnection structure. the approach was found to perform better than automatic test generation at the gate level using existing algorithms for several large circuits
sat based solutions for consistency problems in formal property specifications for open systems. formal property verification is increasingly being adopted by designers for module level validation. the behavior of a module is typically expressed in terms of the behavioral guarantee of the module under assumptions on its environment. expressing such assume-guarantee properties correctly in a formal language is a nontrivial task and errors in the specification are not uncommon. in this paper we examine the main forms of specification errors for open systems, and present sat based algorithms for verifying the specification against such errors.
double-gate soi devices for low-power and high-performance applications. double-gate (dg) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk cmos. among the various types of dg devices, quasi-planar soi finfets are easier to manufacture compared to planar double-gate devices. dg devices with independent gates (separate contacts to back and front gates) have recently been developed. dg devices with symmetric and asymmetric gates have also been demonstrated. such device options have direct implications at the circuit level. independent control of front and back gate in dg devices can be effectively used to improve performance and reduce power in sub-50nm circuits. independent gate control can be used to merge parallel transistors in noncritical paths. this results in reduction in the effective switching capacitance and hence power dissipation. we show a variety of circuits in logic and memory that can benefit from independent gate operation of dg devices. as examples, we show the benefit of independent gate operation in circuits such as dynamic logic circuits, schmitt triggers, sense amplifiers, and sram cells. in addition to independent gate option, we also investigate the usefulness of asymmetric devices and the impact of width quantization and process variations on circuit design.
making fourier-envelope simulation robust. fourier-envelope algorithms are an important component of the mixed-signal/rf verification toolbox. in this paper, we address the unpredictability and lack of robustness that has been reported for these algorithms. we show that the problem stems from fast oscillations in envelopes that are expected to be slowly varying. we demonstrate that this is related to the fact that the envelope equations are always stiff, whether or not the underlying system is. we show that careful choice of envelope initial conditions is necessary to obtain useful solutions, and propose two techniques for finding good initial conditions. applying these, and solving the envelope equations with stiffly-stable numerical methods, we improve the robustness and reliability of fourier-envelope methods. we illustrate the new methods with a direct-downconversion mixer circuit.
a bipartition-codec architecture to reduce power in pipelined circuits. this paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. we treat each output value of a pipelined circuit as one state of a fsm. if the output of a pipelined circuit transit mainly among few states, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states of high activity is small and the other that contains the remainder of low activity is big. consequently, the state transitions will be confined to the small block in most of the time. then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. the encoder minimizes the number of bit changes during state transitions thus the switching which propagates into decoder is reduced considerably. we present experimental results on several mcnc benchmarks and get up to 63.7% power savings by using our new architecture.