waashk/dblp huggingface dataset:
addressing shared resource contention in multicore processors via scheduling. contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past. previous solutions focused primarily on hardware techniques and software page coloring to mitigate this problem. our goal is to investigate how and to what extent contention for shared resource can be mitigated via thread scheduling. scheduling is an attractive tool, because it does not require extra hardware and is relatively easy to integrate into the system. our study is the first to provide a comprehensive analysis of contention-mitigating techniques that use only scheduling. the most difficult part of the problem is to find a classification scheme for threads, which would determine how they affect each other when competing for shared resources. we provide a comprehensive analysis of such classification schemes using a newly proposed methodology that enables to evaluate these schemes separately from the scheduling algorithm itself and to compare them to the optimal. as a result of this analysis we discovered a classification scheme that addresses not only contention for cache space, but contention for other shared resources, such as the memory controller, memory bus and prefetching hardware. to show the applicability of our analysis we design a new scheduling algorithm, which we prototype at user level, and demonstrate that it performs within 2\% of the optimal. we also conclude that the highest impact of contention-aware scheduling techniques is not in improving performance of a workload as a whole but in improving quality of service or performance isolation for individual applications.
paralog: enabling and accelerating online parallel monitoring of multithreaded applications. instruction-grain lifeguards monitor the events of a running application at the level of individual instructions in order to identify and help mitigate application bugs and security exploits. because such lifeguards impose a 10-100x slowdown on existing platforms, previous studies have proposed hardware designs to accelerate lifeguard processing. however, these accelerators are either tailored to a specific class of lifeguards or suitable only for monitoring singlethreaded programs. we present paralog, the first design of a system enabling fast online parallel monitoring of multithreaded parallel applications. paralog supports a broad class of software-defined lifeguards. we show how three existing accelerators can be enhanced to support online multithreaded monitoring, dramatically reducing lifeguard overheads. we identify and solve several challenges in monitoring parallel applications and/or parallelizing these accelerators, including (i) enforcing inter-thread data dependences, (ii) dealing with inter-thread effects that are not reflected in coherence traffic, (iii) dealing with unmonitored operating system activity, and (iv) ensuring lifeguards can access shared metadata with negligible synchronization overheads. we present our system design for both sequentially consistent and total store ordering processors. we implement and evaluate our design on a 16 core simulated cmp, using benchmarks from splash-2 and parsec and two lifeguards: a data-flow tracking lifeguard and a memory-access checker lifeguard. our results show that (i) our parallel accelerators improve performance by 2-9x and 1.13-3.4x for our two lifeguards, respectively, (ii) we are 5-126x faster than the time-slicing approach required by existing techniques, and (iii) our average overheads for applications with eight threads are 51% and 28% for the two lifeguards, respectively.
characterizing processor thermal behavior. temperature is a dominant factor in the performance, reliability, and leakage power consumption of modern processors. as a result, increasing numbers of researchers evaluate thermal characteristics in their proposals. in this paper, we measure a real processor focusing on its thermal characterization executing diverse workloads. our results show that in real designs, thermal transients operate at larger scales than their performance and power counterparts. conventional thermal simulation methodologies based on profile-based simulation or statistical sampling, such as simpoint, tend to explore very limited execution spans. short simulation times can lead to reduced matchings between performance and thermal phases. to illustrate these issues we characterize and classify from a thermal standpoint spec00 and spec06 applications, which are traditionally used in the evaluation of architectural proposals. this paper concludes with a list of recommendations regarding thermal modeling considerations based on our experimental insights.
orthrus: efficient software integrity protection on multi-cores. this paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. recent studies show that a large class of software attacks can be detected by running multiple versions of a program simultaneously and checking the consistency of their behaviors. however, execution of multiple replicas incurs significant overheads on today's computing platforms, especially with fine-grained comparisons necessary for high security. orthrus exploits similarities in automatically generated replicas to enable simultaneous execution of those replicas with minimal overheads; the architecture reduces memory and bandwidth overheads by compressing multiple memory spaces together, and additional power consumption and silicon area by eliminating redundant computations. utilizing the hardware architecture, orthrus implements a fine-grained memory layout diversification with the llvm compiler and can detect corruptions in both pointers and critical data. experiments indicate that the orthrus architecture incurs minimal overheads and provides a protection against a broad range of attacks.
dynamically replicated memory: building reliable systems from nanoscale resistive memories. dram is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. resistive memories, such as phase-change memory (pcm), already scale well beyond dram and are a promising dram replacement. unfortunately, pcm is write-limited, and current approaches to managing writes must de- commission pages of pcm when the first bit fails. this paper presents dynamically replicated memory (drm), the first hardware and operating system interface designed for pcm that allows continued operation through graceful degradation when hard faults occur. drm reuses memory pages that con- tain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. no changes are required to the processor cores, the cache hierarchy, or the operating sys- tem's page tables. by changing the memory controller, the tlbs, and the operating system to be drm-aware, we can improve the lifetime of pcm by up to 40x over conventional error-detection techniques.
micro-pages: increasing dram efficiency with locality-aware data placement. power consumption and dram latencies are serious concerns in modern chip-multiprocessor (cmp or multi-core) based compute systems. the management of the dram row buffer can significantly impact both power consumption and latency. modern dram systems read data from cell arrays and populate a row buffer as large as 8 kb on a memory request. but only a small fraction of these bits are ever returned back to the cpu. this ends up wasting energy and time to read (and subsequently write back) bits which are used rarely. traditionally, an open-page policy has been used for uni-processor systems and it has worked well because of spatial and temporal locality in the access stream. in future multi-core processors, the possibly independent access streams of each core are interleaved, thus destroying the available locality and significantly under-utilizing the contents of the row buffer. in this work, we attempt to improve row-buffer utilization for future multi-core systems. the schemes presented here are motivated by our observations that a large number of accesses within heavily accessed os pages are to small, contiguous "chunks" of cache blocks. thus, the co-location of chunks (from different os pages) in a row-buffer will improve the overall utilization of the row buffer contents, and consequently reduce memory energy consumption and access time. such co-location can be achieved in many ways, notably involving a reduction in os page size and software or hardware assisted migration of data within dram. we explore these mechanisms and discuss the trade-offs involved along with energy and performance improvements from each scheme. on average, for applications with room for improvement, our best performing scheme increases performance by 9% (max. 18%) and reduces memory energy consumption by 15% (max. 70%).
conmem: detecting severe concurrency bugs through an effect-oriented approach. multicore technology is making concurrent programs increasingly pervasive. unfortunately, it is difficult to deliver reliable concurrent programs, because of the huge and non-deterministic interleaving space. in reality, without the resources to thoroughly check the interleaving space, critical concurrency bugs can slip into production runs and cause failures in the field. approaches to making the best use of the limited resources and exposing severe concurrency bugs before software release would be desirable. unlike previous work that focuses on bugs caused by specific interleavings (e.g., races and atomicity-violations), this paper targets concurrency bugs that result in one type of severe effects: program crashes. our study of the error-propagation process of realworld concurrency bugs reveals a common pattern (50% in our non-deadlock concurrency bug set) that is highly correlated with program crashes. we call this pattern concurrency-memory bugs: buggy interleavings directly cause memory bugs (null-pointer-dereference, dangling-pointer, buffer-overflow, uninitialized-read) on shared memory objects. guided by this study, we built conmem to monitor program execution, analyze memory accesses and synchronizations, and predicatively detect these common and severe concurrency-memory bugs. we also built a validator conmem-v to automatically prune false positives by enforcing potential bug-triggering interleavings. we evaluated conmem using 7 open-source programs with 9 real-world severe concurrency bugs. conmem detects more tested bugs (8 out of 9 bugs) than a lock-set-based race detector and an unserializable-interleaving detector that detect 4 and 5 bugs respectively, with a false positive rate about one tenth of the compared tools. conmem-v further prunes out all the false positives. conmem has reasonable overhead suitable for development usage.
coredet: a compiler and runtime system for deterministic multithreaded execution. the behavior of a multithreaded program does not depend only on its inputs. scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in the execution of multithreaded programs. this severely complicates many tasks, including debugging, testing, and automatic replication. in this work, we avoid these complications by eliminating their root cause: we develop a compiler and runtime system that runs arbitrary multithreaded c/c++ posix threads programs deterministically. a trivial non-performant approach to providing determinism is simply deterministically serializing execution. instead, we present a compiler and runtime infrastructure that ensures determinism but resorts to serialization rarely, for handling interthread communication and synchronization. we develop two basic approaches, both of which are largely dynamic with performance improved by some static compiler optimizations. first, an ownership-based approach detects interthread communication via an evolving table that tracks ownership of memory regions by threads. second, a buffering approach uses versioned memory and employs a deterministic commit protocol to make changes visible to other threads. while buffering has larger single-threaded overhead than ownership, it tends to scale better (serializing less often). a hybrid system sometimes performs and scales better than either approach individually. our implementation is based on the llvm compiler infrastructure. it needs neither programmer annotations nor special hardware. our empirical evaluation uses the parsec and splash2 benchmarks and shows that our approach scales comparably to nondeterministic execution.
a power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. we present an all-optical approach to constructing data networks on chip that combines the following key features: (1) wavelength-based routing, where the route followed by a packet depends solely on the wavelength of its carrier signal, and not on information either contained in the packet or traveling along with it. (2) oblivious routing, by which the wavelength (and thus the route) employed to connect a source-destination pair is invariant for that pair, and does not depend on ongoing transmissions by other nodes, thereby simplifying design and operation. and (3) passive optical wavelength routers, whose routing pattern is set at design time, which allows for area and power optimizations not generally available to solutions that use dynamic routing. compared to prior proposals, our evaluation shows that our solution is significantly more power efficient at a similar level of performance.
specifying and dynamically verifying address translation-aware memory consistency. computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (at) systems. detecting bugs and faults requires a clear specification of correct behavior. to address this need, we develop a framework for at-aware memory consistency models. we expand and divide memory consistency into the physical address memory consistency (pamc) model that defines the behavior of operations on physical addresses and the virtual address memory consistency (vamc) model that defines the behavior of operations on virtual addresses. as part of this expansion, we show what at features are required to bridge the gap between pamc and vamc. based on our at-aware memory consistency specifications, we design efficient dynamic verification hardware that can detect violations of vamc and thus detect the effects of design bugs and runtime faults, including most at related bugs in published errata.
fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. cores in a chip-multiprocessor (cmp) system share multiple hardware resources in the memory subsystem. if resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. previous research proposed separate fairness mechanisms in each individual resource. such resource-based fairness mechanisms implemented independently in each resource can make contradictory decisions, leading to low fairness and loss of performance. therefore, a coordinated mechanism that provides fairness in the entire shared memory system is desirable. this paper proposes a new approach that provides fairness in the entire shared memory system, thereby eliminating the need for and complexity of developing fairness mechanisms for each individual resource. our technique, fairness via source throttling (fst), estimates the unfairness in the entire shared memory system. if the estimated unfairness is above a threshold set by system software, fst throttles down cores causing unfairness by limiting the number of requests they can inject into the system and the frequency at which they do. as such, our source-based fairness control ensures fairness decisions are made in tandem in the entire memory system. fst also enforces thread priorities/weights, and enables system software to enforce different fairness objectives and fairness-performance tradeoffs in the memory system. our evaluations show that fst provides the best system fairness and performance compared to four systems with no fairness control and with state-of-the-art fairness mechanisms implemented in both shared caches and memory controllers.
butterfly analysis: adapting dataflow analysis to dynamic parallel monitoring. online program monitoring is an effective technique for detecting bugs and security attacks in running applications. extending these tools to monitor parallel programs is challenging because the tools must account for inter-thread dependences and relaxed memory consistency models. existing tools assume sequential consistency and often slow down the monitored program by orders of magnitude. in this paper, we present a novel approach that avoids these pitfalls by not relying on strong consistency models or detailed inter-thread dependence tracking. instead, we only assume that events in the distant past on all threads have become visible; we make no assumptions on (and avoid the overheads of tracking) the relative ordering of more recent events on other threads. to overcome the potential state explosion of considering all the possible orderings among recent events, we adapt two techniques from static dataflow analysis, reaching definitions and reaching expressions, to this new domain of dynamic parallel monitoring. significant modifications to these techniques are proposed to ensure the correctness and efficiency of our approach. we show how our adapted analysis can be used in two popular memory and security tools. we prove that our approach does not miss errors, and sacrifices precision only due to the lack of a relative ordering among recent events. moreover, our simulation study on a collection of splash-2 and parsec 2.0 benchmarks running a memory-checking tool on a hardware-assisted logging platform demonstrates the potential benefits in trading off a very low false positive rate for (i) reduced overhead and (ii) the ability to run on relaxed consistency models.
shoestring: probabilistic soft error reliability on the cheap. aggressive technology scaling provides designers with an ever increasing budget of cheaper and faster transistors. unfortunately, this trend is accompanied by a decline in individual device reliability as transistors become increasingly susceptible to soft errors. we are quickly approaching a new era where resilience to soft errors is no longer a luxury that can be reserved for just processors in high-reliability, mission-critical domains. even processors used in mainstream computing will soon require protection. however, due to tighter profit margins, reliable operation for these devices must come at little or no cost. this paper presents shoestring, a minimally invasive software solution that provides high soft error coverage with very little overhead, enabling its deployment even in commodity processors with "shoestring" reliability budgets. leveraging intelligent analysis at compile time, and exploiting low-cost, symptom-based error detection, shoestring is able to focus its efforts on protecting statistically-vulnerable portions of program code. shoestring effectively applies instruction duplication to protect only those segments of code that, when subjected to a soft error, are likely to result in user-visible faults without first exhibiting symptomatic behavior. shoestring is able to recover from an additional 33.9% of soft errors that are undetected by a symptom-only approach, achieving an overall user-visible failure rate of 1.6%. this reliability improvement comes at a modest performance overhead of 15.8%.
dynamic filtering: multi-purpose architecture support for language runtime systems. this paper introduces a new abstraction to accelerate the read-barriers and write-barriers used by language runtime systems. we exploit the fact that, dynamically, many barrier executions perform checks but no real work -- e.g., in generational garbage collection (gc), frequent checks are needed to detect the creation of inter-generational references, even though such references occur rarely in many workloads. we introduce a form of dynamic filtering that identifies redundant checks by (i) recording checks that have recently been executed, and (ii) detecting when a barrier is repeating one of these checks. we show how this technique can be applied to a variety of algorithms for gc, transactional memory, and language-based security. by supporting dynamic filtering in the instruction set, we show that the fast-paths of these barriers can be streamlined, reducing the impact on the quality of surrounding code. we show how we accelerate the barriers used for generational gc and transactional memory in the bartok research compiler. with a 2048-entry filter, dynamic filtering eliminates almost all the overhead of the gc write-barriers. dynamic filtering eliminates around half the overhead of stm over a non-synchronized baseline -- even when used with an stm that is already designed for low overhead, and which employs static analyses to avoid redundant operations.
flexible architectural support for fine-grain scheduling. to make efficient use of cmps with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. however, managing tasks of a few thousand instructions is particularly challenging, as the runtime must ensure load balance without compromising locality and introducing small overheads. software-only schedulers can implement various scheduling algorithms that match the characteristics of different applications and programming models, but suffer significant overheads as they synchronize and communicate task information over the deep cache hierarchy of a large-scale cmp. to reduce these costs, hardware-only schedulers like carbon, which implement task queuing and scheduling in hardware, have been proposed. however, a hardware-only solution fixes the scheduling algorithm and leaves no room for other uses of the custom hardware. this paper presents a combined hardware-software approach to build fine-grain schedulers that retain the flexibility of software schedulers while being as fast and scalable as hardware ones. we propose asynchronous direct messages (adm), a simple architectural extension that provides direct exchange of asynchronous, short messages between threads in the cmp without going through the memory hierarchy. adm is sufficient to implement a family of novel, software-mostly schedulers that rely on low-overhead messaging to efficiently coordinate scheduling and transfer task information. these schedulers match and often exceed the performance and scalability of carbon when using the same scheduling algorithm. when the adm runtime tailors its scheduling algorithm to application characteristics, it outperforms carbon by up to 70%.