waashk/dblp huggingface dataset:
combining speech retrieval results with generalized additive models. efficient and intelligent music information retrieval is a very important topic of the 21st century. with the ultimate goal of building personal music information retrieval systems, this paper studies the problem of identifying "similar" artists using both lyrics and acoustic data. in this paper, we present a clustering algorithm that integrates features from both sources to perform bimodal learning. the algorithm is tested on a data set consisting of 570 songs from 53 albums of 41 artists using artist similarity provided by all music guide. experimental results show that the accuracy of artist similarity classifiers can be significantly improved and that artist similarity can be efficiently identified.
distributed word clustering for large scale class-based language modeling in machine translation. for group-oriented applications, designing secure and efficient group key management schemes is a major problem. we present a group key management scheme for dynamic peer networks, which supports join, leave, merge and partition events. in the scheme, the numbers of rounds and messages are close to the lower bounds of those for dynamic group key management, and the length of messages and computation costs are less than those of the existing schemes. furthermore, this scheme provides forward secrecy, backward secrecy and key independence
extraction of entailed semantic relations through syntax-based comma resolution. aimed at the overvoltage trouble of electric equipments in 500 kv gis substation caused by lightning strikes to overhead line, four protection solutions were proposed. through atp simulation, the protection margins and economy of the protective devices such as transformer, reactor, cvt and gis-inlet were estimated. it is concluded that installation of a set of outdoor type surge arrester at line inlet and a set of indoor type one at main transformers may effectively reduce the lightning overvoltage based on chaos fractal theory, fractal dimension and kolmogorov entropy of voltage wave at transformer were calculated and compared, and the positive correlation between the protection margin and kolmogorov entropy was proved. it is proposed that protection solution may be determined using chaos characteristics of voltage wave, it is satisfactory when potection point p is not less than the reference point pi, namely, pgespi.
evaluating a crosslinguistic grammar resource: a case study of wambaya. this paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. in this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. in order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. experimental results for iscas circuits show that the method efficiently evaluates the upper bounds of switching gates
applying morphology generation models to machine translation. most tracking algorithms are based on the maximum a posteriori (map) solution of a probabilistic framework called hidden markov model, where the distribution of the object state at current time instance is estimated based on current and previous observations. however this approach is prone to errors caused by temporal distractions such as occlusion, background clutter and multi-object confusion. in this paper we propose a multiple object tracking algorithm that seeks the optimal state sequence which maximizes the joint state-observation probability. we name this algorithm trajectory tracking since it estimates the state sequence or "trajectory" instead of the current state. the algorithm is capable of tracking multiple objects whose number is unknown and varies during tracking. we introduce an observation model which is composed of the original image, the foreground mask given by background subtraction and the object detection map generated by an object detector the image provides the object appearance information. the foreground mask enables the likelihood computation to consider the multi-object configuration in its entirety. the detection map consists of pixel-wise object detection scores, which drives the tracking algorithm to perform joint inference on both the number of objects and their configurations efficiently.
combining multiple resources to improve smt-based paraphrasing model. we examine a knowledge representation architecture to support context interchange mediation. for autonomous receivers and sources sharing a common subject domain, the mediator's reasoning engine can devise query plans integrating multiple sources and resolving semantic heterogeneity. receiver applications obtain the data they need in the form they need it without imposing changes on sources. the kr architecture includes: 1) data models for each source and receiver, 2) subject domain ontologies, containing abstract subject matter conceptualizations that would be known to experienced practitioners in the industry, and 3) context models for each source and receiver that explain how each source or receiver data model implements the abstract concepts from a subject domain ontology. examples drawn from the fixed income securities industry illustrate problems and solutions enabled by the proposed architecture.
hedge classification in biomedical texts with a weakly supervised selection of keywords. route flap damping is a mechanism generally used in network routing protocols. its goal is to limit the global impact of unstable routes by temporarily suppressing routes with rapid changes over short time periods. although route damping is a clearly defined and simple procedure at each router, its effect in a large network setting is not well understood. we show that the current damping design leads to the intended behavior only under persistent route flapping. when the number of flaps is small, the global routing dynamics deviates significantly from the expected behavior with a longer convergence delay. previous work observed that a single route flap can falsely trigger route suppression due to path exploration. however our simulations show that this false suppression only accounts for 30% of the convergence delay after a single route flap. our study reveals previously unknown interactions between reuse timers at different routers. route suppression and reuse at different routers are triggered at different times and thus affect the number of updates received by other routers. in turn, this impacts other routers' damping behavior. we propose to use root cause notification to eliminate both false suppression and undesirable timer interaction
exploiting feature hierarchy for transfer learning in named entity recognition. summary form only given. facola (face coder based on location and attention) is proposed for potential applications such as compression of face pictures used in ic and id cards. the face locator locates a face in an image using template matching and eigenface techniques. the attention detector detects high attention and low attention in the located face according to their different frequency characteristics. for high attention, usually high quality or lossless coding is required. the dct is not suitable for such a case because it will not lead to an efficient compaction of the image energy and variable length coding (vlc) cannot be done efficiently. so a dpcm coder with three directional predictors is presented instead of the dct. the prediction difference is quantized and the entropy coded dpcm coder supports lossless and lossy compression. the dct coder is adopted for low attention and non-face area compression using different quantization factors
name translation in statistical machine translation - learning when to transliterate. soft-core microprocessors mapped onto field-programmable gate arrays (fpgas) represent an increasingly common embedded software implementation option. modern fpga soft-cores are parameterized to support application-specific customization, wherein pre-defined units, such as a multiplication unit or floating-point unit, may be included in the microprocessor architecture to speed up software execution at the expense of increased size. we introduce a methodology for fast application-specific customization of a parameterized fpga soft core, using synthesis and execution to obtain size and performance data in order to create a tool that can be used across a variety of tool platforms and fpga devices. as synthesizing a soft core takes tens of minutes, developing heuristics that execute in an acceptable time of an hour or two, yet find near-optimal results, is a challenge. we consider two approaches, one using a traditional cad approach that does an initial characterization using synthesis to create an abstract problem model and then explores the solution space using a knapsack algorithm, and the other using a synthesis-in-the-loop exploration approach. we compare approaches for a variety of design constraints, on 11 eembc benchmarks, using an actual xilinx soft-core processor, and for two different commercial xilinx fpga devices. our results show that the approaches can generate a customized configuration exhibiting roughly 2x speedups over a base soft core, reaching within 4% of optimal in about 1.5 hours, including complete synthesis of the soft-core onto the fpga, compared to over 11 hours for exhaustive search. our results also show that including synthesis-in-the-loop, compared to a traditional cad approach, improved speedups by an average of 20% when size constraints were tight. the approaches may also be applicable to soft-core processors targeted to asics in addition to fpgas
refining event extraction through cross-document inference. "the marauder's map" is a magical map in j. k. rowling's fantasy series, "harry potter and the prisoner of azkaban". it shows all moving objects within the boundary of the "hogwarts school of witchcraft and wizardry". in this paper, we introduce a similar attack to location privacy in wireless networks. our system, namely the digital marauder's map, can reveal the locations of wifi-enabled mobile devices within the coverage area of a single high-gain antenna. the digital marauder's map is built solely with off-the-shelf wireless equipments, and features a mobile design that can be quickly deployed to a new location and instantly used without training. we present a comprehensive set of theoretical analysis and experimental results which demonstrate the coverage and localization accuracy of the digital marauder's map.
learning effective multimodal dialogue strategies from wizard-of-oz data: bootstrapping and evaluation. this paper summarizes a methodology for reliability prediction of new products where field data are sparse, and the allowed number & length of experiments are limited. the methodology relies on estimating a set where the unknown parameters are most likely to be found, calculation of an upper bound for the reliability metric of interest conditioned that the parameters reside in the estimated set, and tightening the bounds via design of experiments. models of failure propagation, failure acceleration, system operations, and time/cycle to failure at various levels of fidelity & expert elicited information may be incorporated to enhance the accuracy of the predictions. the application of the model is illustrated through numerical studies.
pdt 2.0 requirements on a query language. the v-detector generation algorithm is a kind of negative selection algorithm (nsa) inspired by biological immune system (bis). in this paper, v-detector generation algorithm is simply introduced. the problem that v-detector generation algorithm can not meet the change of parameters in significant level is also pointed out. this problem will cause instable algorithm performance. in the meantime, it will cause the algorithm failed under the circumstance of some parameter values. this paper analyzed the reason that caused the problem theoretically and the relevant solution is proposed. the experiment results showed that the proposed solution solved the problem existed in original algorithm successfully and make the performance more stable and reliable. the improved algorithm can really adapt to different values of significant level and obtain better detection performance.
forest-based translation. this paper describes a new approach to invariant object recognition. in this approach, an object is represented by a set of key points called landmarks. all possible translation, scaling, and rotation of the object are placed into an equivalent class and associated to a single point in a complex projective space called the shape space. object recognition is then achieved by distance calculations in this shape space. this approach is invariant to object translation, scaling, and rotation, and is computationally simple. our experimental results also indicate that it is insensitive to noise and moderate occlusions
randomized language models via perfect hash functions. data management in very large distributed systems (vlds) is considered. a replication strategy that can offer a tradeoff between cost and quality of service is discussed. imperfect replicated data, called quasi-copies, are considered in conjunction with the notion of file stashing. stashing a file means placing copies of that file in several nodes of a computer network to augment the availability of the file, i.e. to be able to access the file when the file server that holds it is no longer reachable. the stash propagation problem of how to efficiently propagate updates to the stashed copies throughout the system is studied
selecting query term alternations for web search by exploiting query contexts. we propose a client-server graphics design framework and implement a room design system using corba. we have integrated technologies used in distributed computation (java and corba) and computer graphics (vrml). to support multiuser collaborative design, we propose a supplier-consumer communication approach and implement it using the event service in corba. our system can be applied in electronic commerce to improve the existing systems by allowing customers to select furniture and to visualize the whole furnished room in 3d
improving parsing and pp attachment performance with sense information. with the advance of hardware and software technology, modern phased array radars are now built with commercial off-the-shelf (cots) components, and it opens up a new era in real-time resource scheduling of digital signal processing. this paper targets the essential issues in building a component-oriented signal processor (sp), which is one of the two major modules in modern phased array radars. we propose a simple but effective task allocation policy and a real-time scheduling algorithm to address the design objectives of sps. we are able to bound the number of processing units needed for a component-oriented sp in the design time, while everything was done empirically in the past. a series of experiments were done to demonstrate the strength of our methodology
a logical basis for the d combinator and normal form in ccg. how to manage trust is regarded as a main problem of security issues in p2p overlay networks. reputation-based trust management is regarded as a promising way to solve the problem. however, in p2p systems, obtaining reputation evidence for building trust relationships is not an easy job. we tackle this problem by employing a scheme for the distribution of reputation evidence, which is based on the swarm intelligence paradigm. our simulations show that it performs very well in p2p environment. we hope that this method will help move the reputation based trust management closer to fulfilling its promise in p2p networks
finding contradictions in text. accuracy of statistical face recognition is determined by face's distributed feature. applying statistical recognition to faces without obvious distributed feature is meaningless. but such faces can be classified by subtle differences between local features. so local feature based face recognition by obtaining local feature and its dimension is proposed in this paper. experiments show that, the algorithm is satisfactory
pivot approach for extracting paraphrase patterns from bilingual corpora. as an important part of requirement management, managing requirement change plays a key role in controlling project schedule and costs at early stage. effective requirement impact analysis would give proper assessment on the effect of certain requirement changes on the whole system, and provide useful information for making trade-off decisions on future system design and implementation. in this paper a quantitative approach to concern impact analysis at requirement level has been proposed with the application of pagerank algorithm, which is a successful link based web page sorting algorithm. at first, separation of concerns is applied during deriving formal requirement specification from textual requirement statements. next, concerns are specified and concern relationship graph is established. finally, pagerank algorithm is utilized on concern relationship graph for assessing the impact of concern changes. our approach has been applied to hallway section in light control system and validation of analysis result has been stated.
enriching morphologically poor languages for statistical machine translation. microarray image technology is a powerful tool for monitoring the expression of thousands of genes simultaneously. each microarray experiment produces immense amounts of image data, and efficient storage and transmission requires compression that utilizes the microarray image's structure and unique analysis goals. we have developed a progressive compression scheme for microarray images which can be either lossy or lossless. our scheme has a coded data structure that allows fast decoding and reprocessing of image subsets, and includes summary statistics and image segmentation information. since visual fidelity is not the end goal for microarray images, we introduce a new measure of distortion for lossy compression: the sensitivity of microarray information extraction to compression loss. we find that a lossy compression ratio of 8:1 for cdna microarrays minimally affects downstream processing. the average lossless compression ratio is 1.83:1 for cdna images and 2.43:1 for inkjet images, comparable to state-of-the-art lossless schemas, yet with added flexibility and information.
trainable generation of big-five personality styles through data-driven parameter estimation. h.264/avc is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. we propose an efficient processing order for the deblocking filter, and present the vlsi architecture according to the order. making good use of data dependence between neighboring 4&times;4 blocks, our design reduces the requirement of on-chip sram bandwidth and increases the throughput of the filter processing. the architecture has been described in verilog hdl, simulated with vcs and synthesized using 0.25 &mu;m cmos cells library by synopsys design compiler. the circuit costs about 24k logic gates (not including a 32&times;64 sram and two 32&times;96 srams) when the working frequency is set to 100 mhz. this design can support real-time deblocking of hdtv (1280&times;720, 60 fps) h.264/avc video. this architecture is valuable for the hardware design of an h.264/avc codec.
when specialists and generalists work together: overcoming domain dependence in sentiment tagging. this paper presents an efficient survivability hierarchy analysis method for networked information system. in the hierarchical model, the top level is the survivability of system; the second is the survivability of essential service; the third is the survivability of atomic module; the lowest one is vulnerability. with the help of attack graph, the survivability (3r+a) is quantified according the records of the qos before and after attack. key words: survivability, hierarchical model
a tree sequence alignment-based tree-to-tree translation model. validation is one of the most complex and expensive tasks in current application specific instruction set processors (asip) design process. many existing approaches employ a multiple-level approach to efficiently design and verify asip design. this paper presents a novel extended timed petri net model called hdpn-hardware design based-on petri net to model systems at multiple levels, and introduces a verification scheme based on hdpn to satisfy the requirement of design space exploration (dse). this paper focuses on formal modeling and verification asip architecture. and a dlx pipelined processor is presented to demonstrate the validity and usage of this method.
joint word segmentation and pos tagging using a single perceptron. in open multi-agent systems (mas), interaction between agents is uncertain. trust plays an important role in deciding with whom to interact and how to interact with it. current trust models have solved the problem of how to quantify, deduce and evaluate trust, but there are still challenges. this paper presents fire+ trust model using utility loss of issue to evaluate trust values. with the representation of matrix, it efficiently increases the rating information. also by introducing d-s theory and wma, it can handle uncertain information and dishonest witness finely. meanwhile, our approach introduces the concept of information-amount to derive each issue 's weight so as to gain the whole trust value of the target agent. it also takes witness reliability into account. experiments show that fire+ is more effective than others.
an entity-mention model for coreference resolution with inductive logic programming. dynamic random access memory (dram) has been used in main memory design for decades. however, dram consumes an increasing power budget and faces difficulties in scaling down for small feature size cmos processing technologies. compared to conventional dram, emerging phase change random access memory (pram) demonstrates superior power efficiency and processing scalability as vlsi technologies and integration density continue to advance. nevertheless, using nano-scale fabrication technologies will unavoidably introduce design parameter variability in the manufacturing stage. in the past, the impact of process variation (pv) on conventional transistor-based storage cells and combinational logic has been studied extensively. however, the implication of pv on non-volatile memory design using emerging phase change techniques has not been well understood. in this paper, we take the first step toward characterizing the effect of process variation on pram and explore pv-aware design techniques. we show that process variation increases the pram programming power by 96% and degrades pram endurance by 50x. our proposed circuit and two microarchtiecture techniques with system-level support reduce pram power by 44%, 59% and 57% and improve pram endurance by 27x, 277x and 268x, relative to pv-affected pram design. moreover, we show that the synergy of the proposed cross-layer approaches, which achieve an average 63% power savings and 13050x endurance improvement over the conventional case, provide an attractive design solution to mitigate the deleterious impact of pv for non-volatile memory in the upcoming nano-scale processing technology era.