waashk/dblp huggingface dataset:
smoothed form of nonlinear phase macromodel for oscillators. this paper proposes an improvement to the well-known oscillator nonlinear phase macromodel based on floquet theory. a smoothed form of the nonlinear phase macromodel is derived by eliminating highly oscillatory terms in the macromodel, resulting in a significant speed-up in transient simulation. for an lc oscillator under sinusoidal excitation the new macromodel is equivalent to the adler model. numerical experiments confirm a considerable decrease of computational efforts. it is further shown that the new macromodel allows one to perform phase noise analysis of locked oscillators under arbitrary periodic injection.
power supply noise aware workload assignment for multi-core systems. as the industry moves from single- to multi-core processors, the challenges of how to reliably design and analyze power delivery for such systems also arise. we study various workload assignments to cores and their impact on the global power grid noise. we develop metrics to estimate the amount of noise propagated from core to core and propose a power supply noise aware workload assignment method. in our experiments, we show that performance loss can be significant if workload assignment is not properly made.
boolean factoring and decomposition of logic networks. this paper presents new methods for restructuring logic networks based on fast boolean techniques. the basis for these are 1) a cut-based view of a logic network, 2) exploiting the uniqueness and speed of disjoint-support decompositions, 3) a new heuristic for speeding these up, 4) extending these to general decompositions, and 5) limiting local transformations to functions with 16 or less inputs so that fast truth table manipulations can be used in all operations. boolean methods lessen the structural bias of algebraic methods, while still allowing for high speed and multiple iterations. experimental results on k-lut networks show an average additional reduction of 5.4% in lut count, while preserving delay, compared to heavily optimized versions of the same networks.
efficient and accurate eye diagram prediction for high speed signaling. this paper introduces an accumulative prediction method to predict the eye diagram for high speed signaling systems. we use the step responses of pull-up and pull-down to extract the worst-case eye diagram, including the eye height and jitter. furthermore, the method produces the input patterns of the worst-case intersymbol interference. the algorithm handles signals of either symmetric or asymmetric rise/fall time. experimental results demonstrate the accuracy and efficiency of the proposed method.
linear constraint graph for floorplan optimization with soft blocks. in this paper, we propose the linear constraint graph (lcg) as an efficient general floorplan representation. for n blocks, an lcg has at most 2n+3 vertices and at most 6n+2 edges. operations with direct geometric meanings are developed to perturb the lcgs. we apply the lcgs to the floorplan optimization with soft blocks to leverage its advantage in terms of the sizes of the graphs, which will improve the efficiency of solving a complex mathematical program in the inner loop of the optimization that decide the block shapes without introducing overlaps to the non-slicing floorplans. experimental results confirm that the lcgs are effective and efficient.
on capture power-aware test data compression for scan-based testing. large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. with given test cubes in scan-based testing, the "don't-care" bits can be exploited for test data compression and/or test power reduction. prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. in this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.
system-level power estimation using an on-chip bus performance monitoring unit. in this paper we propose an on-chip bus pmu which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity information exchanged on the on-chip bus. it can easily be customized for different on-chip and off-chip memory devices, and is not dependent on a specific cpu core. we model memory devices using energy state machines, describe them in xml, and use that description automatic synthesis of the pmu. we compare the short-term accuracy of the proposed pmu with a cycle-accurate system-level power estimator, and assess its long-term accuracy with a real hardware prototype. experimental results show that the the power estimation deviates less than 5% from real measurements.
texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. with increasing interest in sophisticated graphics capabilities in mobile systems, energy consumption of graphics hardware is becoming a major design concern in addition to the traditional performance enhancement criteria. among the different steps in the graphics processing pipeline, we have observed that memory accesses during texture mapping -- a highly memory intensive phase - contribute 30-40% of the energy consumed in typical embedded graphics processors. this makes the texture mapping subsystem an attractive candidate for energy optimization. we argue that a standard cache hierarchy, commonly used by researchers and commercial graphics processors for texture mapping, is wasteful of energy, and propose the texture filter memory, an energy efficient architecture that exploits locality and the relatively high degree of predictability in texture memory access patterns. our architecture consumes 75% lesser energy for texturing in a fixed function pipeline, incurring no performance overhead and a small area overhead over conventional texture mapping hardware.
nanolithography and cad challenges for 32nm/22nm and beyond. the semiconductor industry is stuck at 193nm lithography as the main workhorse for manufacturing integrated circuits of 45nm and most likely 32nm nodes. on one hand, many novel approaches are being developed to extend the 193nm lithography, including immersion, double patterning, and exotic resolution enhancement techniques. on the other hand, next generation lithography, in particular, extreme ultra violet lithography (euvl) is projected by itrs as the main contender for technology nodes at or below 22nm, though significant challenges still exist from both technology and economy aspects. this tutorial will cover key nanolithography and cad challenges with possible solutions for 32nm/22nm (and beyond?), from the underlying hardware/equipment perspectives (for double patterning, euv, and so on), to the computational lithography aspects (extreme ret, inverse lithography, pixelated mask, etc.), and to the key eda issues on nanolithofriendly layouts (e.g., double patterning compliance layout, and so on).
game-theoretic timing analysis. estimating the worst-case execution time (wcet) of tasks is a key step in the design of reliable real-time software and systems. in this paper, we present a new, game-theoretic approach to estimating wcet based on performing directed measurements on the target platform. we model the estimation problem as a game between our algorithm (player) and the environment of the program (adversary), where the player seeks to find the longest path through the program while the adversary sets environment parameters to thwart the player. we present both theoretical and experimental results demonstrating the utility of our approach. on the theoretical side, we prove that our algorithm can converge to find the longest path with high probability. experimental results indicate that our approach is competitive with an existing technique based on static analysis and integer programming. moreover, the approach can be easily applied to even complex hardware/software platforms.
minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing. in this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running. the technique dynamically adjusts the supply voltage level and clock frequency of the design by exploiting slacks that are present in various stages of the pipeline. the key enabler is the utilization of soft-edge flip-flops to allow time borrowing between consecutive stages of the pipeline in order to provide the timing-critical stages with more time to complete their computations resulting in lower error probability. this raises the effective throughput of the pipeline for a fixed energy consumption level, or alternatively, lowers the energy consumption for the same effective throughput. we formulate the problem of optimally selecting the transparency window sizes of the soft-edge flip-flops and the frequency level of the pipeline circuit at different voltage levels so as to optimize the energy cost of the achieved throughput. experimental results show the efficacy of the problem formulation and solution technique.
sram dynamic stability: theory, variability and analysis. technology scaling in sub-100nm regime has significantly shrunk the sram stability margins in data retention, read and write operations. conventional static noise margins (snms) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art srams with shrinking access time and/or advanced dynamic read-write-assist circuits. using the insights gained from rigorous nonlinear system theory, we define the much needed sram dynamic noise margins (dnms). the newly defined dnms not only capture key sram nonlinear dynamical characteristics but also provide valuable design insights. furthermore, we show how system theory can be exploited to develop cad algorithms that can analyze sram dynamic stability characteristics three orders of magnitude faster than a brute-force approach while maintaining spice-level accuracy. we also demonstrate a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to three orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations.
routing for chip-package-board co-design considering differential pairs. nanometer effects have complicated the designs of chips as well as packages and printed circuit boards (pcb's). in order to improve the performance, convergence, and signal integrity of the design, chip-package-board co-design is strongly recommended by industry. in this paper, we present the first routing algorithm in the literature for chip-package-board co-design with differential-pair considerations. our algorithm is based on linear programming and integer linear programming and guarantees to find an optimal solution for the addressed problem. it first creates globalrouting paths among chips, packages, and a pcb. without loss of the solution optimality, our routing formulation can reduce the numbers of integer variables (constraints) by 95% (99%) on average. then, any-angle routing is applied to complete the routing. experimental results based on five real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all differential-pair constraints, under reasonable cpu times, whereas recent related work results in much inferior solution quality.
proactive temperature balancing for low cost thermal management in mpsocs. designing thermal management strategies that reduce the impact of hot spots and on-die temperature variations at low performance cost is a very significant challenge for multiprocessor system-on-chips (mpsocs). in this work, we present a proactive mpsoc thermal management approach, which predicts the future temperature and adjusts the job allocation on the mpsoc to minimize the impact of thermal hot spots and temperature variations without degrading performance. in addition, we implement and compare several reactive and proactive management strategies, and demonstrate that our proactive temperature-aware mpsoc job allocation technique is able to dramatically reduce the adverse effects of temperature at very low performance cost. we show experimental results using a simulator as well as an implementation on an ultrasparc t1 system.
mute-aes: a multiprocessor architecture to prevent power analysis based side channel attack of the aes algorithm. side channel attack based upon the analysis of power traces is an effective way of obtaining the encryption key from secure processors. power traces can be used to detect bitflips which betray the secure key. balancing the bitflips with opposite bitflips have been proposed, by the use of opposite logic. this is an expensive solution, where the balancing processor continues to balance even when encryption is not carried out in the processor. we propose, for the first time, a multiprocessor algorithmic balancing technique to prevent power analysis of a processor executing an aes cryptographic program, a popular encryption standard for embedded systems. our technique uses a dual processor architecture where two processors execute the same program in parallel, but with complementary intermediate data, thus balancing the bitflips. the second processor works in conjunction with the first processor for balancing only when the aes encryption is performed, and both processors carry out independent tasks when no encryption is being performed. accessing the encryption key or the input data by the first processor begins the obfuscation by the second processor. to stop the encryption by the second processor, we use a novel signature detection technique, which detects the end of the encryption automatically. the multiprocessor balancing approach (muteaes) proposed here reduces performance by 0.42% and increases the size of the hardware by 2x (though reduces to 0.1% when no encryption is being performed). we show that differential power analysis (dpa) fails when our technique is applied to aes. we further illustrate, that by the use of this balancing strategy, the adversary is left with noise from the power profile with little useful information.
double patterning technology friendly detailed routing. double patterning technology (dpt) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of extreme ultra violet lithography. however, it should hurdle two challenges before being introduced to mass production, layout decomposition and overlay error. in this paper, we present the first detailed routing algorithm for dpt to improve layout decomposability and robustness against overlay error, by minimizing indecomposable wirelength and the number of stitches. experimental results show that the proposed approach improves the quality of layout significantly in terms of decomposability and the number of stitches with 3.6x speedup, compared with a current industrial dpt design flow.
a framework for predictive dynamic temperature management of microprocessor systems. the sustained push for performance, transistor count and instruction level parallelism has reached a point where ic thermal issues are at the forefront of design constraints. many of the current systems deploy dynamic voltage and frequency scaling (dvfs) to address thermal emergencies. dvfs has certain limitations in terms of response lag, scalability and being reactive. on the other hand, several hardware based control theoretic schemes have been proposed to deliver optimal performance, but such schemes come at high cost and lack flexibility and scalability. in this paper, we present an alternative thermal monitoring and management system that utilizes software and hardware components, based on virtual machine concept. the proposed scheme delivers targeted, localized, and preemptive thermal management at low cost, adapts well to a multitasking environment, while delivering maximum performance under thermal stress.
automated abstraction by incremental refinement in interpolant-based model checking. this paper addresses the field of unbounded model checking (umc) based on sat engines, where craig interpolants have recently gained wide acceptance as an automated abstraction technique. we start from the observation that interpolants can be quite effective on large verification instances. as they operate on sat-generated refutation proofs, interpolants are very good at automatically abstract facts that are not significant for proofs. in this work, we push forward the new idea of generating abstractions without resorting to sat proofs, and to accept (reject) abstractions whenever they (do not) fulfill given adequacy constraints. we propose an integrated approach smoothly combining the capabilities of interpolation with abstraction and over-approximation techniques, that do not directly derive from sat refutation proofs. the driving idea of this combination is to incrementally generate, by refinement, an abstract (over-approximate) image, built up from equivalences, implications, ternary and localization abstraction, then (eventually) from sat refutation proofs. experimental results, derived from the verification of hard problems, show the robustness of our approach.
pyramids: an efficient computational geometry-based approach for timing-driven placement. the purpose of global placement is to find non-overlapping locations for cells, typically while minimizing a wirelength objective. because of this objective, however, when more timing information about the design is known, some cells will inevitably be sub-optimally placed from a timing perspective. in this paper, we present two new techniques to incrementally improve placements by moving cells to their optimal timing locations. we call our approach pyramids, since it uses pyramid-shaped delay surfaces to solve for the optimal location, rather than running a more expensive linear programming solver. we show how to apply these techniques to timing-driven detailed placement and also for more accurate latestage incremental timing correction. experimental results validate the effectiveness of pyramids by showing significantly improved timing after an industrial placement algorithm. furthermore, compared to the linear programming solvers, the speedup of pyramids solver is 373x vs. clp and 448x vs. glpk.
embedded software verification: challenges and solutions. embedded software are becoming more and more pervasive in our lives, and many application domains have very high reliability requirements. ensuring high software quality while still maintaining software productivity is a challenging task. in order to address this challenge, more formal analysis and automated verification techniques are needed in addition to standard software testing. in this tutorial, we will showcase the important ideas and techniques of software formal verification, including static program analysis, program modeling and (bounded) model checking, and predicate abstraction refinement. we will emphasize some of the key techniques that have been successfully adopted by recent, industrial-strength software verification tools. in this tutorial, we will focus on detecting bugs in sequential programs written in c/c++ for portable devices as well as for general purpose platforms. the tutorial will be tailored to the iccad audience by emphasizing the use of decision procedures such as bdds, presburger arithmetic, bit-vector arithmetic, sat and smt solvers. many of these techniques have been used in the context of analyzing, optimizing, and verifying ic designs. by attending this tutorial, the audience will get a better understanding of the challenges and potential solutions of embedded software verification.
mixed-signal simulation challenges and solutions. the design of complex mixed-signal system-on-a-chip (soc) designer poses challenging requirements on the simulation design environment. the simulation platform has to include simulations at the behavioral, gate and transistor-level which have traditionally been done in separate environments. as the scaling trend continues, the designer needs additional accuracy and capacity, new capabilities such as efficient statistical simulation that takes into account layout dependent effects. in this panel we have representatives from the cad and design community discussing the challenges and current solutions available to the mixed-signal simulation challenge.
a succinct memory model for automated design debugging. in today's complex soc designs, verification and debugging are becoming ever more crucial and increasingly time-consuming tasks. the prevalence of embedded memories adds to the difficulty of the problem by exponentially increasing the statespace of the design. in this work, a novel memory model for design debugging is presented. it models memory succinctly by avoiding an explicit representation for each memory bit. the method uses the simulation of the erroneous design to guide the debugging process. this results in a parameterizable formal encoding that grows linearly with the erroneous trace length, significantly reducing the memory requirements of the debugging problem. in addition, the proposed model is extended to handle an arbitrary initial memory configuration, as well as non-cycle accurate output traces where only a final expected memory state is available for comparison. experiments on industrial designs show a 96% average reduction in memory usage along with a noticeable performance improvement compared to previous work.
placement based multiplier rewiring for cell-based designs. we present an algorithm for improving the performance of carry-save-adder (csa) style multipliers. based on placement information, the algorithm exploits the arithmetic equivalence in the csa multipliers and rewires to improve the slack of the multiplier.
decoupling capacitance allocation for timing with statistical noise model and timing analysis. this paper presents an allocation method of decoupling capacitance that explicitly considers timing. we have found and focused that decap does not necessarily improve a gate delay at all the switching timing within a cycle, and devised an efficient sensitivity calculation of timing to decap for decap allocation. the proposed method, which is based on a statistical noise modeling and timing analysis, accelerates the sensitivity calculation with an approximation and adjoint sensitivity analysis. experimental results show that the decap allocation based on the sensitivity analysis efficiently optimizes the worst-case circuit delay within a given decap budget. compared to the maximum decap placement, the delay improvement due to decap increases by 5% even while the total amount of decap is reduced to 40%.
statistical path selection for at-speed test. process variations make at-speed testing significantly more difficult. they cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. due to parametric variations, different paths can be critical in different parts of the process space, and the union of such paths must be tested to obtain good process space coverage. this paper proposes a novel branch-and-bound algorithm that elegantly and efficiently solves the hitherto open problem of statistical path tracing. the resulting paths are used for at-speed structural testing. a new test quality metric (tqm) is proposed and paths which maximize this metric are selected. after chip timing has been performed, the path selection procedure is extremely efficient. path selection for a multi-million gate chip design can be completed in a matter of seconds.