waashk/dblp huggingface dataset:
transition-aware decoupling-capacitor allocation in power noise reduction. dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. decoupling capacitor (decap) allocation is one of the most effective way in reducing serious dynamic power noises (hotspots). to allocate decap before placement, we observed that not only locations but also rising time of functional cells are required to accurately predict power noises. compared to a previous work which only takes neighborhood relation into consideration, our method is more efficient in reducing hotspots. furthermore, to reduce the hotspots after placement, instead of only using the empty space as proposed in the previous work, we move out cells in the area with serious power noise area (hot area). the obtained empty space can be used to accommodate decaps to further reduce the hotspots. the experimental result shows, compared to the previous work [1], our estimation function to allocate decap before placement is 23% better in reducing power noises. moreover, compared to a method which fills decaps to all remaining empty space, our cell move algorithm can almost eliminate all the remaining hot grid nodes and hot cells. in summary, compared to the original circuits (without decap), about 60% of hotspots can be removed using our prediction function before placement, and most of the remaining hotspots are removed by our cell moving step after placement.
lightweight secure pufs. to ensure security and robustness of the next generation of physically unclonable functions (pufs), we have developed a new methodology for puf design. our approach employs integration of three key principles: (i) inclusion of multiple delay lines for creation of each response bit; (ii) transformations and combination of the challenge bits; and (iii) combination of the outputs from multiple delay lines; to create modular, easy to parameterize, secure and reliable puf structures. statistical analysis of the new structure and its comparison with existing pufs indicates a significantly lower predictability, and higher resilience against circuit faults, reverse engineering and other security attacks.
system-level thermal aware design of applications with uncertain execution time. the paper introduces the problem of system-level thermal aware design of applications with uncertain run time on an embedded processor equipped with dynamic voltage/frequency scaling features. the problem takes as inputs a task sequence, cycle time distribution of each task, and processor thermal model. the solution specifies a voltage/frequency assignment to the tasks such that the expected latency is minimized subject to the probability that the peak temperature constraint is not violated is no less than a designer specified value. we prove that the problem is at least np-hard, and present optimal and (1 + &epsilon;) fully polynomial time approximation scheme as solutions. to the best of our knowledge, this paper is the first work that addresses the stochastic version of the system-level thermal-aware design problem. we evaluate the effectiveness of our techniques by experimenting with realistic and synthetic benchmarks.
reliable system design: models, metrics and design techniques. design of reliable systems meeting stringent quality, reliability, and availability requirements is becoming increasingly difficult in advanced technologies. the current design paradigm, which assumes that no gate or interconnect will ever operate incorrectly within the lifetime of a product, must change to cope with this situation. future systems must be designed with built-in mechanisms for failure tolerance, prediction, detection and recovery during normal system operation. this tutorial will focus on models and metrics for designing reliable systems, algorithms and tools for modeling and evaluating such systems, will discuss a broad spectrum of techniques for building such systems with support for concurrent error detection, failure prediction, error correction, recovery, and self-repair. complex interplay between power, performance and reliability requirements in future systems, and associated constraints will also be discussed.
simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. this work aims to analyze and establish the relations between the three important design parameters in power gated circuits: (i) the maximum current flowing from/to power/ground (ii) the wakeup (sleep to active mode transition) time delay and (iii) the number of sleep transistors. with the understanding of relations between the parameters, we propose solutions to the two problems: (1) finding logic clusters and their wakeup schedule to minimize the sleep transistor overhead under the constraints of wakeup time and peak current and (2) finding logic clusters and their wakeup schedule to minimize the wakeup time under the constraints of peak current and the number of sleep transistors. from an experimentation using iscas benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 65% ~ 77% reduced number of sleep transistors and 30% ~ 36% reduced wakeup time delay, compared to the results by the previous work.
on efficient monte carlo-based statistical static timing analysis of digital circuits. the monte-carlo (mc) technique is a well-known solution for statistical analysis. in contrast to probabilistic (non-monte carlo) statistical static timing analysis (ssta) techniques, which are typically derived from simple statistical or timing models, the mc-based ssta technique encompasses complicated timing and process variation models. however, a precise analysis that involves a traditional mc-based technique requires many timing simulation runs (1000s). in this paper, the behavior of the critical delay of digital circuits is investigated by using a legendre polynomial-based anova decomposition. the analysis verifies that the variance of the critical delay is mainly due to the pairwise interactions among the principal components (pcs) of the process parameters. based on this fact, recent progress on the mc-based ssta, through latin hypercube sampling (lhs), is also studied. it is shown that this technique is prone to inefficient critical delay variance and quantile estimating. inspired by the decomposition observations, an efficient algorithm is proposed which produces optimally low l2-discrepancy quasi-mc (qmc) samples which significantly improve the precision of critical delay statistical estimations, compared with that of the mc, lhs, and traditional qmc techniques.
characterization and modeling of graphene field-effect devices. the novel electronic properties of graphene, including a linear energy dispersion relation and purely two-dimensional structure, have led to intense research into possible applications of this material in nanoscale devices. in this paper, we review the unique electronic properties of graphene that give it the potential for high-frequency electronic applications. we then present the latest results on the current-voltage characteristics of top-gated graphene fets. these devices show unique characteristics related to the ambipolar nature of the graphene channel. in addition, the devices show very high saturation velocities, suggesting the possibility for superior high frequency performance. our initial devices have transconductances as high as 150 &mu;s/&mu;m despite low on-off current ratios, making the devices very suitable for analog/rf applications.
challenges at 45nm and beyond. design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. in this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and cad challenges in 45nm, what cad challenges still exist and how the cad community can help.
area-i/o flip-chip routing for chip-package co-design. the area-i/o flip-chip package provides a high chip-density solution to the demand of more i/o's in vlsi designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. in this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple re-distribution layer (rdl) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. our router adopts a two-stage technique of global routing followed by rdl routing. the global routing assigns each block port to a unique bump pad via an i/o pad and decides the rdl routing among i/o pads and bump pads. based on the minimum-cost maximum-flow algorithm, we can guarantee 100% rdl routing completion after the assignment and the optimal solution with the minimum wirelength. the rdl routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable cpu times, while related works cannot.
linear analysis of random process variability. this paper describes an alternate method to monte carlo for calculating circuit node voltage and branch current variances due to random process variability. recent results show that the complex models traditionally used to describe random process variations of a transistor can be replaced by a single independent current noise source with a variance dependent on the transistor's size and operating points. as a result, each transistor affected by random process variability can be modeled as a deterministic device in parallel with a current noise source. by replacing all the transistors in a circuit with this model, the spatial voltage variances of circuit nodes can be calculated through linear small-signal analysis. the idea is presented in this paper and a tool implemented for berkeley spice is described. the results of the variability spice tool match the results from monte carlo run in spectre, with an accuracy determined by the accuracy of the random process variability model. for example, the standard deviations computed by the tool are within a 5.0% accuracy of those calculated through measured silicon data which has a fitting error of 5.4%. the monte carlo method computes node variances in a time proportional to the number of circuit nodes and the number of iterations, whereas the computation time required by the variability tool is only a function of the number of circuit nodes. for large analog designs this results in a significant speed-up in the amount of time required to calculate circuit node variances.
integrated code and data placement in two-dimensional mesh based chip multiprocessors. as transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (cmps) are becoming a promising alternative to remain on the current performance trajectory for both high-end systems and embedded systems. since future technologies offer the promise of being able to integrate billions of transistors on a chip, the prospects of having hundreds to thousands of processors on a single chip along with an underlying memory hierarchy and an interconnection system is entirely feasible. this paper proposes a compiler directed integrated code and data placement scheme for two-dimensional mesh based cmp architectures. the proposed approach uses a code-data affinity graph (cdag) to represent the relationship between loop iterations and array data and then assigns the sets of loop iterations to processing cores and sets of data blocks to on-chip memories. during the mapping process, the on-chip memory capacity and load imbalance across different cores and the topology of the noc are taken into account. in this paper, we present two variants of our approach: depth-first placement (dfp) and breadth-first placement (bfp), and compare them to three alternate code/data mapping schemes. the experimental evaluation shows that our cdag based placement schemes are very successful in practice, achieving average performance improvements of 19.9% (dfp) and 16.8% (bfp), and average energy improvements of 29.7% (dfp) and 27.8% (bfp).
integrated circuit design with nem relays. to overcome the energy-efficiency limitations imposed by finite sub-threshold slope in cmos transistors, this paper explores the design of integrated circuits based on nanoelectro-mechanical (nem) relays. a dynamical verilog-a model of the nem relay is described and correlated to device measurements. using this model we explore nem relay design strategies for digital logic and i/o that can significantly improve the energy efficiency of the whole vlsi system. by exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that nem relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over cmos adders with ns-range delays and with no area penalty. by applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. similar improvements in high-speed i/o energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.
overlay aware interconnect and timing variation modeling for double patterning technology. as double patterning technology (dpt) becomes the only solution for 32-nm lithography process, we need to investigate how dpt affects the performance of a chip. in this paper, we present an efficient modeling of timing variation with overlay which is inevitable for dpt. our work makes it possible to analyze timing with overlay variables. since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional rc extraction flow. to verify our work, we use identical interconnects having different positions and different layout decompositions. experimental result shows that the delay has a variation from 7.8% to 9.1% depending on their locations. the well decomposed structure shows only 2.7% delay variation.
multigrid on gpu: tackling power grid analysis on parallel simt platforms. the challenging task of analyzing on-chip power (ground) distribution networks with multi-million node complexity and beyond is key to today's large chip designs. for the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (simt) based graphics processing unit (gpu) platforms to tackle power grid analysis with promising performance. several key enablers including gpu-specific algorithm design, circuit topology transformation, workload partitioning, performance tuning are embodied in our gpu-accelerated hybrid multigrid algorithm, gpuhmd, and its implementation. in particular, a proper interplay between algorithm design and simt architecture consideration is shown to be essential to achieve good runtime performance. different from the standard cpu based cad development, care must be taken to balance between computing and memory access, reduce random memory access patterns and simplify flow control to achieve efficiency on the gpu platform. extensive experiments on industrial and synthetic benchmarks have shown that the proposed gpuhmd engine can achieve 100x runtime speedup over a state-of-the-art direct solver and be more than 15x faster than the cpu based multigrid implementation. the dc analysis of a 1.6 million-node industrial power grid benchmark can be accurately solved in three seconds with less than 50mb memory on a commodity gpu. it is observed that the proposed approach scales favorably with the circuit complexity, at a rate about one second per million nodes.
delay-optimal simultaneous technology mapping and placement with applications to timing optimization. technology mapping and placement have significant impact on the delays in standard cell based very large scale integrated (vlsi) circuits. traditionally, these steps are applied separately to optimize delays, possibly since efficient algorithms that allow the simultaneous exploration of the mapping and placement solution spaces are unknown. in this paper, we present an exact polynomial time algorithm for delay-optimal placement of a tree and extend the same to simultaneous technology mapping and placement for optimal delay in the tree. we extend the algorithm by employing lagrangian relaxation technique, which assesses the timing criticality of paths beyond a tree, to optimize the delays in directed acyclic graphs (dags). experimental results on benchmark circuits in a 70 nm technology show that our algorithms improve timing significantly with remarkably less run-times compared to a competitive approach of iterative conventional timing driven mapping and multi-level placement.
algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. we propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay under area constraints by simultaneously considering the benefits and costs of all transforms (as opposed to considering them sequentially after applying each transform). the circuit transforms we employ include, but are not limited to, incremental placement, two types of buffer insertion, cell resizing and cell replication. the problem is modeled as a min-cost network flow problem, in which nodes represent circuit transform options. by carefully determining the structure of the network graph and the cost of each arc, a set of near-optimal transform options can be obtained as those whose corresponding nodes in the network graph have the min-cost flow passing through them. we also tie the transform selection network graph to a detailed placement network graph with td arc costs for cell movements. this enables our algorithms to incorporate considerations of detailed placement cost for each synthesis transform along with the basic cost of applying the transform in the circuit. we have tested our algorithms on three sets of benchmarks under 3--10% area increase constraints, and obtained up to 48% and an average of 27.8% timing improvement. our average improvement is relatively 40% better (8.2% better by an absolute measure) than applying the same set of transforms in a good sequential order that is used in many current techniques. considering only synthesis transforms (no replacement), our technique is relatively 50% better than the sequential approach.
roadnoc: runtime observability for an adaptive network on chip architecture. hard-to-predict system behavior and/or reliability issues resulting from migrating to new technology nodes requires considering runtime adaptivity in future on-chip systems. runtime observability is a prerequisite for runtime adaptivity as it is providing necessary system information gathered on-the-fly. we are presenting the first comprehensive runtime observability infrastructure for an adaptive network on chip architecture which is flexible (e.g. in choosing the routing path), hardly intrusive, and requires little additional overhead (around 0.7% of the total link bandwidth). the hardware overhead is negligible, too, and is in fact less than the hardware savings due to resource multiplexing capabilities that are achieved through runtime observability/adaptivity. as an example, our on-demand buffer assignment scheme increases the buffer utilization and decreases the overall buffer requirements by an average of 42% (the buffer area amounts to about 60% of the entire router area [19]) in our case study analysis compared to a fixed buffer assignment scheme [7]. our runtime observability on an average also increases the connection success rate by 62% compared to the case without runtime observability for the applications from the e3s benchmark suite [6]. we show the advantages obtained through runtime observability and compare with state-of-the art communication-centric designs.
a novel sequential circuit optimization with clock gating logic. to save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. we observe that the clock-gating conditions and the next-state function of a flip-flop (ff) are correlated and can be used for sequential optimization. we show that the implementation of the next-state function of any ff can be just an inverter if the clock signal is appropriately gated. by exploiting the flexibility between the clock-gating conditions and the next-state function, we propose an iterative optimization technique to minimize the overall timing.
verification of arithmetic datapaths using polynomial function models and congruence solving. this paper addresses the problem of solving finite word-length (bit-vector) arithmetic with applications to equivalence verification of arithmetic datapaths. arithmetic datapath designs perform a sequence of add, mult, shift, compare, concatenate, extract, etc., operations over bit-vectors. we show that such arithmetic operations can be modeled, as constraints, using a system of polynomial functions of the type f: z2n1 x z2n2 x &middot;&middot;&middot; x z2nd &rarr; z2m. this enables the use of modulo-arithmetic based decision procedures for solving such problems in one unified domain. we devise a decision procedure using newton's p-adic iteration to solve such arithmetic with composite moduli, while properly accounting for the word-sizes of the operands. we describe our implementation and show how the basic p-adic approach can be improved upon. experiments are performed over some communication and signal processing designs that perform non-linear and polynomial arithmetic over word-level inputs. results demonstrate the potential and limitations of our approach, when compared against sat-based approaches.
deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. the analog placement algorithm plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. plantage is based on a hierarchically bounded enumeration of basic building blocks, using b*-trees. the practically relevant solution space is thereby enumerated quasi-complete. the sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. the result of plantage is the pareto front of placements with respect to different aspect ratios. the whole approach is deterministic, in contrast to existing analog placement algorithms.
importance sampled circuit learning ensembles for robust analog ic design. this paper presents iscles, a novel and robust analog design method that promises to scale with moore's law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. iscles consists of: (1) a boosting algorithm developed specifically for circuit assembly; (2) an iscles-specific library of possible digital-sized circuit blocks; and (3) a recently-developed multi-topology sizing technique to automatically determine each block's topology and device sizes. iscles is demonstrated on design of a sinusoidal function generator and a flash a/d converter, showing promise to robustly scale with shrinking process geometries.