waashk/dblp huggingface dataset:
variation-aware task allocation and scheduling for mpsoc. as technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. as a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable [1]. in this paper, we propose a variation-aware task allocation and scheduling algorithm for multiprocessor system-on-chip (mpsoc) architectures to mitigate the impact of parameter variations. a new design metric, called performance yield and defined as the probability of the assigned schedule meeting the predefined performance constraints, is used to guide the task allocation and scheduling procedure. an efficient yield computation method for task scheduling complements and significantly improves the effectiveness of the proposed variation-aware scheduling algorithm. experimental results show that our variation-aware scheduler achieves significant yield improvements. on average, 45% and 34% yield improvements over worst-case and nominal-case deterministic schedulers, respectively, can be obtained across the benchmarks by using the proposed variation-aware scheduler.
methodology for low power test pattern generation using activity threshold control logic. this paper proposes a new technique of power-aware test pattern generation, wherein the test mode power constraints are specified using pseudo hardware logic functions (referred to as power constraint circuits) that augment the target circuit fed to the atpg tool. the novelty of this approach is three-fold: (i) the atpg tool only sees the enhanced circuit. this influences the generation of the test cubes themselves, as against post-processing of these cubes for a given pattern. (ii) pattern generation can be driven to minimize test power according to a programmable switching activity threshold, and hence, is scalable. (iii) the same constraint circuit can also be effectively used for pattern filtering to isolate patterns which cause high switching activity. additionally, the proposed method does not require any changes to the pattern generation tool or process. this paper describes the methodology, together with techniques for realizing the hardware circuit and specifying thresholds. experimental results on various benchmark circuits (including an industrial design) are presented to show the effectiveness of this approach.
exploiting sti stress for performance. starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. an intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. in this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit sti stress for performance improvement. we perform process simulation of a production 65nm sti technology to generate mobility and delay impact models for sti stress. based on these models, we are able to perform sti stress-aware delay analysis of critical paths using spice. we then present our timing-driven optimization of sti stress in standard cell designs, using detailed placement perturbation to optimize pmos performance and active-layer fill insertion to optimize nmos performance. we assess our optimization on small designs implemented with a 65nm production cell library and a standard synthesis, place and route flow. our timing-driven optimization of sti stress impacts can improve clock frequency by between 7% to 11%. the frequency improvement through exploitation of sti stress comes at practically zero cost in terms of design area and wirelength.
fast exact toffoli network synthesis of reversible logic. the research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. hence synthesis of reversible logic has become a very important research area in the last years. in this paper exact algorithms for the synthesis of generalized toffoli networks are considered. we present an improvement of an existing synthesis approach that is based on boolean satisfiability. furthermore, the principle limits of the original and the improved approach are shown. then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude.
architectural power models for sram and cam structures based on hybrid analytical/empirical techniques. the need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. embedded and high-performance microprocessors incorporate large on-chip cache and similar sram-based or cam-based structures, and these components can consume a significant fraction of the total chip power. thus an accurate power modeling method for such structures is important in early architecture design studies. we present a unified architecture-level power modeling methodology for array structures which is highly-accurate, parameterizable, and technology scalable. we demonstrate the applicability of the model to different memory structures (srams and cams) and include leakage-variability in advanced technologies. the power modeling approach is validated against hspice power simulation results, and we show power estimation accuracy within 5% of detailed circuit simulations.
analog placement with common centroid constraints. in order to reduce parasitic mismatch in analog circuits, some groups of devices are required to share a common centroid while being placed. devices are split into smaller ones and placed with a common center point. we will address this problem of handling common centroid constraint in placement. a new representation called center-based corner block list (c-cbl) is proposed which is a natural extension of corner block list (cbl) [1] to represent a common centroid placement of a set of device pairs. c-cbl is complete and non-redundant in representing any common centroid mosaic packings with pairs of blocks to be matched. to address the same problem with an additional constraint that devices are required to be placed uniformly to average out the parasitic errors, a grid-based approach is proposed. experimental results show that both approaches are fast and promising, and have high scalability that even large data sets can be handled effectively.
high-performance routing at the nanometer scale. in this work we describe significant improvements to core routing technologies and outperform the best results from the ispd '07 global routing contest, as well as previous literature, in terms of route completion, runtime and total wirelength. in particular, our router, fgr, improves upon wirelengths produced by boxrouter and maizerouter in march 2007 by 9.9% and 8.4%, respectively. additionally, we reveal the mathematical basis of negotiated-congestion routing, offer comprehensive analysis of existing routing techniques and discuss several applications at the nanometer scale.
combinational and sequential mapping with priority cuts. an algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into k-input lookup-tables (k-luts). the new algorithm avoids the hurdle of computing all k-input cuts while preserving the quality of the results, in terms of area and depth. the memory and runtime of the proposed algorithm are linear in circuit size and quite affordable even for large industrial designs. for example, computing a good quality 6-lut mapping of an aig with im nodes takes 150mb of ram and 1 minute on a typical laptop. an extension of the algorithm allows for sequential mapping, which searches the combined space of all possible mappings and retimings. this leads to an 18--22% improvement in depth with a 3--5% lut count penalty, compared to combinational mapping followed by retiming.
extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-d planar soc single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-d integration. among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. it has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result upto 80% of the final product cost. in this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. in order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.
stochastic extended krylov subspace method for variational analysis of on-chip power grid networks. in this paper, we propose a novel stochastic method for analyzing the voltage drop variations of on-chip power grid networks with log-normal leakage current variations. the new method, called stoeks, applies hermite polynomial chaos (pc) to represent the random variables in both power grid networks and input leakage currents. but different from the existing hermit pc based stochastic simulation method, extended krylov subspace method (eks) is employed to compute variational responses using the augmented matrices consisting of the coefficients of hermite polynomials. our contribution lies in the combination of the statistical spectrum method with the extended krylov subspace method to fast solve the variational circuit equations for the first time. experimental results show that the proposed method is about two-order magnitude faster than the existing her-mite pc based simulation method and more order of magnitudes faster than monte carlo methods with marginal errors. stoeks also can analyze much larger circuits than the exiting hermit pc based methods.
efficient decoupling capacitance budgeting considering operation and process variations. this paper solves the variation-aware on-chip decoupling capacitance (decap) budgeting problem. unlike previous work assuming the worst-case current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlation between clock cycles and logic-induced correlation between ports. the models also considers current variation due to process variation with spatial correlation. we then propose an iterative alternative programming algorithm to solve the decap budgeting problem under the stochastic current model. experiments using industrial examples show that compared with the baseline model which assumes maximum currents at all ports and under the same decap area constraint, the model considering temporal correlation reduces the noise by up to 5x, and the model considering both temporal and logic-induced correlations reduces the noise by up to 17x. compared with the model using deterministic process parameters, considering process variation (leff variation in this paper) reduces the mean noise by up to 4x and the 3&sigma; noise by up to 13x. while the existing stochastic optimization has been used mainly for process variation purpose, this paper to the best of our knowledge is the first in-depth study on stochastic optimization taking into account both operation and process variations for power network design. we convincingly show that considering operation variation is highly beneficial for power integrity optimization and this should be researched for optimizing signal and thermal integrity as well.
the fast methodology for high-speed soc/computer simulation. this paper describes the fast methodology that enables a single fpga to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic socs, embedded systems and standard desktop/laptop/server computer systems. the methodology partitions a simulator into (i) a functional model that simulates the functionality of the computer system and (ii) a predictive model that predicts performance and other metrics. the partitioning is crafted to map most of the parallel work onto a hardware-based predictive model, eliminating much of the complexity and difficulty of simulating parallel constructs on a sequential platform. fast conventions and libraries have been designed to make creating, modifying, using and measuring such simulators straightforward. we describe a prototype fast system: a full-system, rtl-level cycle-accurate-capable computer system simulator that executes the x86 isa, boots unmodified linux and executes unmodified x86 applications. the prototype runs two to three orders of magnitude faster than the fastest intel and amd rtl-level cycle-accurate x86 software-based simulators and about six to seven times faster than rtl simulation.
a nonlinear cell macromodel for digital applications. current source models have emerged as a promising technique for reducing digital cell netlists to a simpler electrical model for use in timing and other applications. the multiport current source model (mcsm) is one of the most general models in this class, which has been shown to handle multiple electrical effects including multiple-input switching (mis) events in timing. however, this new model is hampered by two major problems: port characterization runtime and accuracy across a range of complicated cells which are deployed in advanced microprocessor design such as complex combinational cells, muxes, and sequentials. in this paper we demonstrate a significant leap in modeling accuracy and characterization runtime over the mcsm model which effectively eliminates these remaining issues. the quality of the new approach is conclusively demonstrated on a comprehensive 45nm cell library currently in use. the new approach accurately models both complex combinational as well as, for the first time, sequential cells, and puts mcsms on the path for next generation gate level electrical analysis.
minimizing leakage power in sequential circuits by using mixed flip-flops. dual vt has been widely used to control leakage, while, at the same time, satisfying circuit performance. however, current approaches target the combinational circuits even though sequential elements, such as flip-flops and latches, contribute an appreciable proportion of the total leakage. the use of dual vt flip-flops is limited to circuits of large timing slack, because introducing high vt flip-flops in place of low vt ones yields abrupt change in timing. we propose mixed vt flip-flops, which are designed by using both low and high vt, but in different transistors. compared to low vt flip-flop, the mixed vt flip-flops exhibit increased delay, but either on setup time or on clock-to-q delay but not on both, while their leakage is greatly reduced. we extend the conventional sensitivity-based dual vt allocation algorithm to incorporate mixed vt flip-flops together with dual vt combinational gates. experimental results show that an average leakage saving of 31% is achieved, compared to the use of dual vt on combinational subcircuits alone. the leakage of the flip-flops themselves is cut by 57% on average.
practical method for obtaining a feasible integer solution in hierarchical layout optimization. layout optimization is a powerful technique for design migration, circuit performance tuning and design for manufacturing. in this paper, we study the problem of layout optimization for the hierarchical circuits in modern vlsi designs which essentially can be formulated as the integer linear programming(ilp) problem. existing approaches are either unable to handle hierarchy, inefficient or failing to provide the feasible integer solutions for large scale hierarchical layouts. we present a practical method, irls algorithm (iteratively rounding and lp solving) which consists of a proper rounding strategy based on the careful analysis of hierarchical layout constraints, to obtain a feasible integer solution in the constraint-based layout modification process, thus enabling efficient optimization for large scale hierarchical layouts, and specifically avoiding the need to use the general ilp solvers. experimental results demonstrate the efficiency and effectiveness of the irls algorithm. compared with the general ilp/milp solver, the irls algorithm can obtain decent results with much less runtime (speed-up ranging from 4,000x to 360,000x). compared with the two-step approach[2] on legalizing a set of large scale industry circuit layouts, the irls algorithm can provide much better solution (satisfying all abutment/alignment constraints that the two-step approach fails to meet).
impedance extraction for 3-d structures with multiple dielectrics using preconditioned boundary element method. in this paper, we present the first bem impedance extraction algorithm for multiple dielectrics. the effect of multiple dielectrics is significant and efficient modeling is challenging. however, previous bem algorithms, including fastimp and fastpep, assume uniform dielectric, thus causing considerable errors. the new algorithm introduces a circuit formulation which makes it possible to utilizes either multilayer green's function or equivalent charge method to extract impedance in multiple dielectrics. the novelty of the formulation is the reduction of the number of unknowns and the application of the hierarchical data structure. the hierarchical data structure permits efficient sparsification transformation and preconditioners to accelerate the linear equation solver. experimental results demonstrate that the new algorithm is accurate and efficient. for uniform dielectric problems, the new algorithm is one magnitude faster than fastimp, while its results differ from fastimp within 2%. for multiple dielectrics problems, its relative error with respect to hfss is below 3%.
stimulus generation for constrained random simulation. constrained random simulation is the main workhorse in today's hardware verification flows. it requires the random generation of input stimuli that obey a set of declaratively specified input constraints, which are then applied to validate given design properties by simulation. the efficiency of the overall flow depends critically on (1) the performance of the constraint solver and (2) the distribution of the generated solutions. in this paper we discuss the overall problem of efficient constraint solving for stimulus generation for mixed boolean/integer variable domains and propose a new hybrid solver based on markov-chain monte carlo methods with good performance and distribution.
operation chaining asynchronous pipelined circuits. we define operation chaining (op-chaining) as an optimization problem to determine the optimal pipeline depth for balancing performance against energy demands in pipelined asynchronous designs. since there are no clock period requirements, asynchronous pipeline stages can have non-uniform latencies. we exploit this fact to coalesce several stages together thereby saving power and area due to the elimination of control-path resources from the pipeline. the trade-off is potentially reduced pipeline parallelism. in this paper, we formally define this optimization as a graph covering problem, which finds sub-graphs that will be synthesized as an opchained pipeline stage. we then define the solution space for provably correct solutions and present an algorithm to efficiently search this space. the search technique partitions the graph based on post-dominator relationships to find sub-graphs that are potential op-chain candidates. we use knowledge of the global critical path (gcp) [13] to evaluate the performance impact of accepting a candidate sub-graph and formulate a heuristic cost function to model this trade-off. the algorithm has a quadratic-time complexity in the size of the dataflow graph. we have implemented this algorithm within an automated asynchronous synthesis toolchain [12]. experimental evidence from applying the algorithm on several media processing kernels reveals that the average energy-delay and energy-delay-area products improve by about 1.4x and 1.8x respectively, with a maximum improvement of 5x and 18x.
a novel intensity based optical proximity correction algorithm with speedup in lithography simulation. it is important to reduce the optical proximity correction (opc) runtime while maintaining a good result quality. in this paper, we obtain a better formula, which theoretically speeds up the widely used method, optimal coherent approximations (oca's), by a factor of 2x. we speed up the opc algorithm further by making it intensity based (ib-opc), because it requires much less intensity simulations than the conventional edge placement error (epe) based opc algorithms. in addition, the ib-opc algorithm, which uses the efficiently computed sensitivity information, converges faster than the epe based opc. our ib-opc experimental results show a runtime speedup of up to 15x with a comparable result quality as of the epe based opc.
low-overhead design technique for calibration of maximum frequency at multiple operating points. determination of maximum operating frequencies (fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a dynamic voltage and frequency scaling (dvfs) system, the adaptation hardware actually applies the correct operating frequency corresponding to a scaled supply and (b) to sort chips in different voltage-frequency (v-fmax)bins, so that chips at different bins can be used for different applications. existing speed binning approach requires extensive delay testing at all operating points with all possible frequencies, which increases test cost and test time significantly. in this paper, we propose a low-overhead solution for characterizing fmax of a circuit at different operating voltages that can eliminate the complex and expensive fmax calibration at multiple voltage points. the basic idea is to choose a small set of representative paths in a circuit based on their voltage sensitivity and dynamically configuring them into ring oscillator to compute the fmax. the proposed calibration mechanism is all-digital, robust to process variations, reasonably accurate (average 2.8% error) and incorporates minimal hardware overhead (average 1.7% delay, 3.5% area and 0.28% power overhead).
a robust finite-point based gate model considering process variations. this paper proposes a robust gate model based on a finite-point modeling scheme. with current source model (csm) framework, a robust, finite-point gate model is constructed. the new model depends on the selective points of i-v curves of gates. thus, it implicitly incorporates the variation related parameters into finite points. in addition, to provide good accuracy on output waveform, the new model creates the input and output capacitance elements as nonlinear dependency on input/output waveform and process variation parameters. experimental results show that the generated gate model has less than 3.7% error at mean, less than 6.2% error at variance and less than 5.8% at 90% percentile for cumulative density functions (cdfs).