waashk/dblp huggingface dataset:
localized watermarking: methodology and application to operation scheduling. this paper addresses the copyright protection problem of integrated circuits designed with blocks which are originated from multiple design sources. the process consists of two phases. first, a compact signature is generated from every block independently and made public. utilizing such signatures, a design can be decomposed into its original building blocks, regardless of multiple hierarchies. then, a map of all the blocks can be built, thus allowing to reconstruct the original copyright dependencies. the proposed methodology can be used by foundries to verify that designs submitted for fabrication contain blocks traceable to a legal source of intellectual property. the verification process is also useful to intellectual property providers and integrators, as it reduces the likelihood of infringement, thus ultimately minimizing the risk of litigation.
optimal p/n width ratio selection for standard cell libraries. the effectiveness of logic synthesis to satisfy increasingly tight timing constraints in deep-submicron high-performance circuits heavily depends on the range and variety of logic gates available in the standard cell library. primarily, research in the design of high-performance standard cell libraries has been focused on drive strength selection of various logic gates. since cmos logic circuit delays not only depend on the drive strength of each gate but also on its p/n width ratio, it is crucial to provide good p/n width ratios for cach cell. the main contribution of this paper is the development of a theoretical framework through which library designers can determine &ldquo;optimal&rdquo; p/n width ratio for each logic gate in their high-performance standard cell library. this theoretical framework utilizes new gate delay models that explicitly represent the dependence of delay on p/n width ratio and load. these delay models yield highly accurate delay for cmos gates in a 0.12&mgr;m leff deep-submicron technology.
a novel net weighting algorithm for timing-driven placement. net weighting for timing-driven placement has been very popular in industry and academia. it has various advantages such as low complexity, high flexibility and ease of implementation. existing net weighting algorithms, however, are often ad-hoc. there is generally no known good net weighting algorithms. in this paper, we present a novel net weighting algorithm based on the concept of path-counting, and apply it in timing-driven fpga placement application. theoretically this is the first ever known accurate, all-path counting algorithm. experimental data shows that compared with the weighting algorithm used in state-of-the-art fpga placement package vpr[1], this new algorithm can achieve the longest path delay reduction of up to 38.8%, 15.6% on average with no runtime overhead and only a 4.1% increase in total wirelength.
silca: fast-yet-accurate time-domain simulation of vlsi circuits with strong parasitic coupling effects. we propose a new circuit analysis method, namelysemi-implicit linear-centric analysis (silca), for efficientspice-accurate transient simulation of deep-submicron vlsicircuits with strong parasitic coupling effects introduced byinterconnect lines, common substrate, power/ground networks, etc.silca is based on two linear-centric techniques. first, a new semi-implicititerative numerical integration scheme is developed, whichapplies dynamic time step control accounting for stiff systems andmeanwhile keeps constant equivalent conductance forcapacitor/inductor companion models. its convergence and stabilityproperties are characterized. second, to achieve constant linearizedconductance for nonlinear devices during nonlinear iterationprocess, a successive variable chord method is introduced as analternative of the newton-raphson method and the rank-one updatetechnique is implemented for fast lu factorization. with thesetechniques, silca reduces the number and cost of required lufactorizations dramatically. experimental results on substrate andpower/ground networks have demonstrated that silca yieldsspice-like accuracy with an over 80x reduction in lufactorization cost, and an about 20x overall cpu time speedup overspice3 for circuits with tens of thousands elements, and theefficiency increases further with the size of a circuit.
partial scan delay fault testing of asynchronous circuits. asynchronous circuits operate correctly only under timing assumptions. hence testing those circuits for delay faults is crucial. this paper describes a three-step method to detect possible delay faults in a sequential asynchronous circuit. the delays that are to be tested must be provided by the synthesis system. by using this information a set of paths in the circuit that must be tested is identified (step 1). for these paths the circuit is made acyclic by inserting at least one scan latch in every cycle (step 2). then test patterns are generated for these paths (step 3). these test patterns consist of setup and initialization vectors and the final test vector. we provide effective procedures to solve both the initialization and the test pattern generation problem. the latter problem is solved by reduction to a classical problem of stuck-at test pattern generation for a related combinational circuit. finally, a heuristic is proposed to determine which state variables must become part of a scan chain, or for which input variables the positive and negative phase must be driven independently in test mode. experimental results shows that a high level of path delay fault testability can be achieved with partial scan.
fault simulation of interconnect opens in digital cmos circuits. we describe a highly accurate but efficient fault simulator for interconnect opens, based on characterizing the standard cell library with spice; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can affect the voltage of an open, into account; and considering the oscillation and sequential behavior potential of opens. a novel test technique based on controlling the die surface voltage is also described. we present our simulation results of iscas85 layouts using stuck-at and iddq test sets.
efficient computation of small abstraction refinements. in the abstraction refinement approach to model checking, the discovery of spurious counterexamples in the current abstract model triggers its refinement. the proof - produced by a sat solver - that the abstract counterexamples cannot be concretized can be used to identify the circuit elements or predicates that should be added to the model. it is common, however, for the refinements thus computed to be highly redundant. a costly minimization phase is therefore often needed to prevent excessive growth of the abstract model. in this work we show how to modify the search strategy of a sat solver so that it generates refinements that are close to minimal, thus greatly reducing the time required for their minimization.
automated data dependency size estimation with a partially fixed execution ordering. for data dominated applications, the system level design trajectory should first focus on finding a good data transfer and storage solution. since no realization details are available at this level, estimates are needed to guide the designer. this paper presents an algorithm for automated estimation of strict upper and lower bounds on the individual data dependency sizes in high level application code given a partially fixed execution ordering. previous work has either not taken execution ordering into account at all, resulting in large overestimates, or required a fully specified ordering which is usually not available at this high level. the usefulness of the methodology is illustrated on representative application demonstrators.
multi-level logic optimization by implication analysis. this paper proposes a new approach to multi-level logic optimization based on atpg (automatic test pattern generation). previous atpg-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. we show that the atpg-based method presented here allows (in principle) the transformation of a given combinational network c into an arbitrary, structurally different but functionally equivalent combinational network c'. furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. by identifying indirect implications between signals in the circuit, transformations can be derived which are &ldquo;good&rdquo; candidates for the minimization of the circuit. in particular, it is shown that recursive learning can derive &ldquo;good&rdquo; boolean divisors justifying the effort to attempt a boolean division. for 9 out of 10 iscas-85 benchmark circuits our tool hannibal obtains smaller circuits than the well-known synthesis system sis.
concurrent d-algorithm on reconfigurable hardware. in this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. the approach is based on automatically designing a circuit which implements the d-algorithm, an automatic test pattern generation (atpg) algorithm, specialized for the combinational circuit. our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, loading the state of the circuit after backup. in this paper, we show the feasibility of this approach in terms of speed, and how it compares with software based techniques.
fast methods for simulation of biomolecule electrostatics. computer simulation is an important tool for improving our understanding of biomolecule electrostatics, in part to aid in drug design. however, the numerical techniques used in these simulation tools do not exploit fast solver approaches widely used in analyzing integrated circuit interconnects. in this paper we describe one popular formulation used to analyze biomolecule electrostatics, present an integral formulation of the problem, and apply the precorrected-fft method to accelerate the solution of the integral equations.
a methodology for verifying memory access protocols in behavioral synthesis. memory is one of the most important components to be optimized in the several phases of the synthesis process. in behavioral synthesis, a memory is viewed as an abstract construct which hides the detail implementations of the memory. consequently, for a vendor's memory, behavioral synthesis should create a clean model of the memory wrapper which abstracts the properties of the memory that are required to interface to the rest of the circuit. however, this wrapping process invariably demands the verification problem of the memory access protocols in order to be safely used in behavioral synthesis environment. in this paper, we propose a systematic methodology of verifying the correctness of the memory wrapper. specifically, we analyze the complexity of the problem, and derive an effective solution which is not only practically efficient but also highly reliable. for designers who use memories as design components in behavioral synthesis, automating our solution shortens the verification time significantly in contrast of simulating memory accesses in the context of full design, which is a quite complex and time-consuming process, especially for designs with many memory access operations.
hardware/software co-synthesis with memory hierarchies. this paper introduces the first hardware/software co-synthesis algorithm of distributed real-time systems that optimize the memory hierarchy along with the rest of the architecture. memory hierarchies (caches) are essential for modern embedded cores to obtain high performance. they also represent a significant portion of the cost, size and power consumption of many embedded systems. our algorithm synthesizes a set of real-time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. unlike previous work in co-synthesis, our algorithm not only synthesizes the hardware and software portions of the applications, but also the memory hierarchies. it chooses cache sizes and allocates tasks to caches as part of co-synthesis. the algorithm is built upon a task-level performance model for memory hierarchies. experimental results, including examples from the literature and results on real-life examples such as an mpeg-2 encoder, show that our algorithm is efficient, and compared with existing algorithms, it can reduce the overall cost of the synthesized system.
regularity driven logic synthesis. we present a new and innovative logic synthesis approach using regularity information of a design to selectively apply transformations and globally guide the synthesis process.since traditional logic synthesis applies transformations without consideration of global design characteristics such as regularity and dataflow, it destroys a substantial amount of regular structures. in addition, due to the non-incremental nature of most logic transformations, synthesis relies vastly on the computationally expensive concept of trial and error application of transformations, a time-consuming process in the synthesis of large designs.the proposed approach addresses both shortcomings of traditional logic synthesis and describes a mechanism to speed up logic synthesis and preserve regularity. it selectively applies transformations to places with similar characteristics and to the same stage of a regular structure, introducing a notion of dataflow-aware synthesis.preservation of regular structures has tremendous advantages to the following physical design stages. it yields high-density layouts, shorter wiring length and improved delay. in addition, the layout becomes more predictable at an earlier design stage.
embedded tutorial: formal equivalence checking between system-level models and rtl. a rigorous system-level model (slm) for a hardware design project is extremely important, often critical. such a functional model not only defines the architect's ideas but also builds a precise foundation for both hardware designers and verification engineers. the key uses of slms are: architecture validation; performance modeling and architectural trade-off; platforms for software development and verification; and functional reference model. in this tutorial, we discuss how to formally verify sequential equivalence between slms and rtl, for both timed and untimed models. first, we provide a formal definition of the sequential equivalence. then we discuss various formal verification technology that enables such practice in real designs.
design/process learning from electrical test. modern design-for-test (dft) practices not only simplify test generation but also make it much easier to diagnose problems uncovered in electrical test. in fact, many diagnostics steps can be automated enough to enable batch processing of large quantities of fail data captured during production test. hidden in these fail data is very valuable information about the product design, manufacturing process, and interactions between the two. the embedded tutorial provides an overview of some of the analysis methods that are being used and/or prototyped in the industry, as well as the underlying data sharing between the design and manufacturing areas that is required for and enabled by the analyses.
optimization and control of and for low-power, high-speed cmos design. it is essential to control vdd and vth for low-power, high-speed cmos design. in this paper, it is shown that these two parameters can be controlled by designers as objectives of design optimization to find better trade-offs between power and speed. quantitative analysis of trade-offs between power and speed is presented. some of the popular circuit techniques and design examples to control vdd and vth are introduced. a simple theory to compute optimum multiple vdd's and vth's is described. scaling scenarios of variable and/or multiple vdd's and vth's is discussed to show future technology directions.
verifying hardware in its software context. we describe a method for verifying hardware whose correct behavior depends upon its software interface. it is presumed that the hardware is presented as a synchronous rtl model whereas the software is presented as an asynchronous abstraction. our methodology incorporates partial order reduction on the software side, and localization reduction, to deal with the computational complexity of the verification. the partial order reduction is implemented as a constraint on the transition relation of a synchronous transformation of the software model. the reduced transformed model then may be verified using a verification algorithm whose scope is purely synchronous models, without modification. thus, independent of the interface verification problem, this gives a general method for combining partial order reduction with symbolic model-checking.
performance optimization of latency insensitive systems through buffer queue sizing of communication channels. this paper proposes for latency insensitive systems a performanceoptimization technique called channel buffer queue sizing, whichis performed after relay station insertion in the physical designstage. it can be shown that proper queue sizing can reduce or evencompletely avoid the performance loss due to imbalanced relaystations insertion in reconvergent paths. moreover, the problemof queue sizing and placement of the additional buffers for maximumperformance is formulated and studied to properly allocateavailable chip areas in the layout to communication channels. analgorithm based on mixed integer linear programming is proposed.experimental results show that queue sizing is effective in improvingthe performance of latency insensitive systems even under tightarea constraints. moreover, the proposed algorithm is sufficientlyefficient in obtaining the optimal solution for systems of practicalsizes.
samba-bus: a high performance bus architecture for system-on-chips. a high performance communication architecture, samba-bus, isproposed in this paper. in samba-bus, multiple compatible bustransactions can be performed simultaneously with only a singlebus access grant from the bus arbiter. experimental results showthat, compared with a traditional bus architecture, the samba-busarchitecture can have up to 3.5 times improvement in the effectivebandwidth, and up to 15 times reduction in the average communicationlatency. in addition, the performance of samba-bus architectureis affected only slightly by arbitration latency, because bustransactions can be performed without waiting for the bus accessgrant from the arbiter. this feature is desirable in soc designs withlarge numbers of modules and long communication delay betweenmodules and the bus arbiter.
congestion aware layout driven logic synthesis. in this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. in addition, we employ partitioning and clustering algorithms to achieve faster turn around times.with the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. while this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.in our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. in addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.
projection-based performance modeling for inter/intra-die variations. large-scale process fluctuations in nano-scale ic technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. fitting such models requires significantly more simulation samples and solving much larger linear equations. in this paper, we propose a novel projection-based extraction approach, probe, to efficiently create quadratic response surface models and capture both inter-die and intra-die variations with affordable computation cost. probe applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. in addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. several circuit examples from both digital and analog circuit modeling applications demonstrate that probe can generate accurate response surface models while achieving up to 12/spl times/ speedup compared with the traditional methods.
prop: a recursive paradigm for area-efficient and performance oriented partitioning of large fpga netlists. in this paper, we introduce a new recursive partitioning paradigm prop which combines (p)artitioning, (r)eplication, (o)ptimization, to be followed by another recursion of (p)artitioning, etc. we measure the quality of partitions in terms of total device cost, logic and terminal utilization, and critical path delay. traditionally, the minimum lower bound into which a given netlist can be partitioned is determined by disregarding the logic interconnect while distributing the logic nodes into a minimum number of devices. prop paradigm challenges this assumption by demonstrating feasible partitions of some large netlists such that the number of device partitions is smaller than minimum lower bounds postulated initially. overall, we report consistent reductions in the total number of partitions for a wide range of combinational and sequential circuit benchmarks while, on the average, reducing critical path delay as well.
a hybrid approach to nonlinear macromodel generation for time-varying analog circuits. modeling frequency-dependent nonlinear characteristics of complexanalog blocks and subsystems is critical for enabling efficientverification of mixed-signal system designs. recent progress hasbeen made for constructing such macromodels, however, their accuracyand/or efficiency can break down for certain problems, particularlythose with high-q filtering. in this paper we explore a novelhybrid approach for generating accurate analog macromodels fortime-varying weakly nonlinear circuits. the combined benefits ofnonlinear padé approximations and pruning by exploitation of thesystem's internal structure allows us to construct nonlinear circuitmodels that are accurate for wide input frequency ranges, and therebycapable of modeling systems with sharp frequency selectivity.such components are widely encountered in analog signal processingand rf applications. the efficacy of the proposed approach isdemonstrated by the modeling of large time-varying nonlinear circuitsthat are commonly found in these application areas.