waashk/dblp huggingface dataset:
the design and synthesis of a synchronous and distributed mac protocol for wireless network-on-chip. to bridge the widening gap between computation requirements and communication efficiency faced by gigascale heterogeneous socs in the upcoming ubiquitous era, a new on-chip communication system, dubbed wireless network-on-chip (wnoc), is introduced by using the recently developed cmos proximity wireless interconnection technology. in this paper, a synchronous and distributed medium access control (sd-mac) protocol is designed and implemented. tailored for wnoc, sd-mac employs a binary countdown approach to resolve channel contention between rf nodes. the receiver_select_sender mechanism and hidden terminal elimination scheme are proposed to increase the throughput and channel utilization of the system. our simulation study shows the promising performance of sd-mac in terms of throughput, latency, and network utilization. as a major component of simple and compact rf node design, a mac unit implements the proposed sdmac that guarantees correct operation of synchronized frames while keeping overhead low. the synthesis results demonstrate several attractive features such as high speed, low power consumption, nice scalability and low area cost.
data locality enhancement for cmps. as chip multiprocessors (cmps) are being increasingly used in embedded computing, optimizing data locality considering interprocessor interactions is becoming critical. to address this problem, this paper proposes a new abstraction called the interprocessor data reuse vector, which captures the reuse distance (in terms of loop iterations) between successive accesses to a given data element from different processors. based on this reuse vector, we then present a data locality optimization scheme. a unique characteristic of this scheme is that it allows application of different transformations to different processors of the cmp if this helps improve locality of data shared across processors. we automated our approach within an optimizing compiler and collected statistics using eight application codes. our results indicate that the proposed code restructuring is very effective in practice (about 9% savings in performance over a standard data locality optimizer).
an incremental learning framework for estimating signal controllability in unit-level verification. unit-level verification is a critical step to the success of full-chip functional verification for microprocessor designs. in the unit-level verification, a unit is first embedded in a complex software that emulates the behavior of surrounding units, and then a sequence of stimuli is applied to measure the functional coverage. in order to generate such a sequence, designers need to comprehend the relationship between boundaries at the unit under verification and at the inputs to the emulation software. however, figuring out this relationship can be very difficult. therefore, this paper proposes an incremental learning framework that incorporates an ordered-binary-decision-forest(obdf) algorithm, to automate estimating the controllability of unit-level signals and to provide full-chip level information for designers to govern these signals. mathematical analysis shows that the proposed obdf algorithm has lower model complexity and lower error variance than the previous algorithms. meanwhile, a commercial microprocessor core is also applied to demonstrate that controllability of input signals on the load/store unit in the microprocessor core can be estimated automatically and information about how to govern these signals can also be extracted successfully.
adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. the well-known pelgrom model [14] has demonstrated that the variation between two devices on the same die due to random mismatch is inversely proportional to the square root of the device area: &sigma; ~ 1/sqrt(area). based on the pelgrom model, analog devices are sized to be large enough to average out random variations. importantly, with cmos scaling, variations due to random doping fluctuations are making it exceedingly difficult to control device mismatches by sizing alone; namely, the devices have to be made so large that the benefits of cmos scaling are not realized for analog and rf circuits. in this paper we propose a novel post-silicon tuning methodology to reduce random mismatches for analog circuits in sub-90nm cmos. a novel dynamic programming algorithm is incorporated into a fast monte carlo simulation flow for statistical analysis and optimization of the proposed tunable analog circuits. we apply the proposed post-silicon tuning methodology to several commonly-used analog circuit blocks. we demonstrate that with the post-silicon tuning, device mismatch exponentially decreases as area increases: &sigma; ~ exp(---&alpha;&middot;area).
a novel soc design methodology combining adaptive software and reconfigurable hardware. reconfigurable hardware is becoming a prominent component in a large variety of soc designs. reconfigurability allows for efficient hardware acceleration and virtually unlimited adaptability. on the other hand, overheads associated with reconfiguration and interfaces with the software component need to be evaluated carefully during the exploration phase. the aim of this paper is to identify the best trade-off considering application-specific features in software, which can lend itself to software-based acceleration and lead to a revision of the view that certain computationally intensive tasks can only be accelerated through hardware. in order to validate the effectiveness of our proposed techniques, we built an extensive development and experimental setup, bringing together the mlton-based programming environment and physical mapping of the software and hardware onto a real dynamically reconfigurable soc system.
clustering based pruning for statistical criticality computation under process variations. we present a new linear time technique to compute criticality information in a timing graph by dividing it into "zones". errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuit-level cutsets. our clustering algorithm gives a 150x speedup compared to a pairwise pruning strategy in addition to ordering edges in a cutset to reduce errors due to clark's max formulation. the clustering based pruning strategy coupled with a localized sampling technique reduces errors to within 5% of monte carlo simulations with large speedups in runtime.
timing variation-aware high-level synthesis. the timing closure problem is one of the most important problems in the design automation. however, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. this work addresses a new problem of high-level synthesis (hls) that effectively takes into account the timing variation. specifically, the work addresses the following four problem: (1) how can the statistical static timing analysis (ssta) used in logic synthesis be modified and applied to the delay and yield computation in hls? (2) how does the resource binding affect yield? (3) how does the scheduling affect yield? (4) how can scheduling and resource binding tasks be combined together to efficiently solve the problem with the objective of minimizing latency under yield constraint?
variation-aware performance verification using at-speed structural test and statistical timing. meeting the tight performance specifications mandated by the customer is critical for contract manufactured asics. to address this, at speed test has been employed to detect subtle delay failures in manufacturing. however, the increasing process spread in advanced nanometer asics poses considerable challenges to predicting hardware performance from timing models. performance verification in the presence of process variation is difficult because the critical path is no longer unique. different paths become frequency limiting in different process corners. in this paper, we present a novel variation-aware method based on statistical timing to select critical paths for structural test. node criticalities are computed to determine the probabilities of different circuit nodes being on the critical path across process variation. moreover, path delays are projected into different process corners using their linear delay function forms. experimental results for three multimillion gate asics demonstrate the effectiveness of our methods.
principle hessian direction based parameter reduction with process variation. as cmos technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. in this paper, we propose a principle hessian direction (phd) based parameter reduction approach. this new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. compared with the existing principle component analysis (pca) method, this performance based property provides us a significantly smaller set of parameters after reduction. the experimental results also support our conclusions. in all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.
unified adaptivity optimization of clock and logic signals. vlsi design is increasingly sensitive to variations which often degrade the parametric yield. post-silicon tuning techniques can compensate for specific variations on the die and thus significantly improve the yield. previous works on adaptivity optimization for post-silicon tuning focus on either logic signal tuning or clock signal tuning. this paper proposes the first unified adaptivity optimization on logical and clock signal tuning, which enables us to significantly save resource. in addition, it does not need any assumption on variation distributions. our unified optimization is based on a novel linear programming formulation which can be efficiently solved by an advanced robust linear programming technique. due to the discrete nature of the problem, the continuous solution obtained from linear programming is then efficiently discretized. this procedure involves binary search accelerated dynamic programming, batch based optimization, and latin hypercube sampling based fast simulation. our experimental results demonstrate that up to 50% area cost reduction can be obtained by the unified optimization compared to optimization on logic or clock alone. in addition, the proposed discretization approach significantly outperforms the alternatives in terms of solution quality and runtime.
estimation of statistical variation in temporal nbti degradation and its impact on lifetime circuit performance. negative bias temperature instability (nbti) in mosfets is one of the major reliability concerns in sub-100nm technologies. so far, studies of nbti and its impact on circuit performance have assumed an average behavior of the degradation process. however, in very short channel devices, finite number of si-h bonds in the channel can induce a statistical random variation of the degradation process. this results in significant random vt variations in pmos transistor. the nbti induced variation depends on operating temperature and the effective stress period for the specific device. in this paper, we analyze the impact of stochastic temporal nbti variations and propose a compact circuit level vt model. using the proposed model, we show how temporal vt variations can affect the lifetime performance of different circuit topologies including 6t sram cell and random combinational logic circuits.
checking equivalence of quantum circuits and states. among the post-cmos technologies currently under investigation, quantum computing (qc) holds a special place. qc offers not only extremely small size and low power, but also exponential speed-ups for important simulation and optimization problems. it also poses new cad problems that are similar to, but more challenging, than the related problems in classical (non-quantum) cad, such as determining if two states or circuits are functionally equivalent. while differences in classical states are easy to detect, quantum states, which are represented by complex-valued vectors, exhibit subtle differences leading to several notions of equivalence. this provides flexibility in optimizing quantum circuits, but leads to difficult new equivalence-checking issues for simulation and synthesis. we identify several different equivalence-checking problems and present algorithms for practical benchmarks, including quantum communication and search circuits, which are shown to be very fast and robust for hundreds of qubits.
mapping model with inter-array memory sharing for multidimensional signal processing. the storage requirements in data-intensive signal processing systems (including applications in video and image processing, artificial vision, medical imaging, real-time 3-d rendering, advanced audio and speech coding) have an important impact on both the system performance and the essential design parameters -- the overall power consumption and chip area. this is due to the significant amount of data that must be stored during the execution of the algorithmic specification, as well as due to the amount of data transfers to/from large, energy-consuming, off-chip data memories. this paper addresses the problem of efficiently mapping the multidimensional signals from the algorithmic specification of the system into the physical memory. different from all the previous mapping models that aim to optimize the memory sharing between the elements of a same array, creating separate windows in the physical memory for distinct arrays, this proposed mapping model is the first one to exploit the possibility of memory sharing between different arrays. as a consequence, this signal-to-memory mapping approach yields significant savings in the amount of data storage resulted after mapping.
device and architecture concurrent optimization for fpga transient soft error rate. late cmos scaling reduces device reliability, and existing work has studied the permanent ser (soft error rate) for configuration memory in fpga extensively. in this paper, we show that continuous cmos scaling dramatically increases the significance of fpga chip-level transient soft errors in circuit elements other than configuration memory, and transient ser can no longer be ignored. we then develop an efficient, yet accurate, transient ser evaluation method, called trace based methodology, considering logic, electrical and latch-window maskings. by collecting traces on logic probability and sensitivity and re-using these traces for different device settings, we finally perform device and architecture concurrent optimization considering hundreds of device and architecture combinations. compared to the commonly used fpga architecture and device settings, device and architecture concurrent optimization can reduce the transient ser by 2.8x and reduce the product of energy, delay and transient ser by 1.8x.
a general model for performance optimization of sequential systems. retiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. for retiming and c-slow retiming, different models that provide exact solutions have already been proposed. an exact model for recycling was yet unknown. this paper presents a general formulation that covers the combination of the three schemes for performance optimization. it provides an exact model based on integer linear programming that resorts to the structural theory of marked graphs. a set of experiments has been designed to show the benefits in performance obtained by combining retiming and recycling. the results also show the applicability of the method in large circuits.
yield-driven near-threshold sram design. voltage scaling is desirable in sram to reduce energy consumption. however, commercial sram is prone to functional failures when vdd is scaled. several sram designs scale vdd to 200--300mv to minimize energy per access, but these designs do not consider sram robustness, limiting them to small arrays and sensor type applications. we examine the effects on area and energy for a differential 6t, single-ended 6t with power rail collapsing and an 8t bitcell as vdd is scaled and the bitcells are sized appropriately to maintain robustness. sram robustness is examined using importance sampling to reduce simulation runtime. at high voltages, the differential 6t bitcell is the smallest for the same failure rate, but the 8t bitcell is smaller when vdd is scaled below 450mv. for vdd below vth, bitcells must be sized greatly to retain robustness and large arrays become impractical. the differential 6t and 8t designs have the lowest dynamic energy consumption, and the single-ended 6t design has the lowest leakage. the supply voltage for minimum energy operation depends on cache configuration and can be well above vth for large caches with low dynamic activity.
multi-layer interconnect performance corners for variation-aware timing analysis. parasitic interconnect corner methods are known to be inaccurate. this paper explains the sources of their errors and shows that errors in excess of 22% can occur in the predicted corner delays of a multi-layer stage in the presence of process variations. it is shown that exhaustive corner search methods are infeasible in practice as they have an exponential complexity in terms of required spice simulations with respect to the number of layers a stage is routed through. this exponential complexity is reduced to a linear one with a new simulation-based search method with the aid of stage delay properties. the ideas behind the simulation-based methodology are shown to be expandable to an analytical-based multi-layer performance corner location methodology. the simulated best/worst case delays based on these analytical corners produce errors below 4% as compared to the exhaustive search simulation based method.
an efficient algorithm for time separation of events in concurrent systems. the time separation of events (tse) problem is that of finding the maximum and minimum separation between the times of occurrence of two events in a concurrent system. it has applications in the performance analysis, optimization and verification of concurrent digital systems. this paper introduces an efficient polynomial-time algorithm to give exact bounds on tse's for choice-free concurrent systems, whose operational semantics obey the max-causality rule. a choice-free concurrent system is modeled as a strongly-connected marked graph, where delays on operations are modeled as bounded intervals with unspecified distributions. while previous approaches handle acyclic systems only, or else require graph unfolding until a steady-state behavior is reached, the proposed approach directly identifies and evaluates the asymptotic steady-state behavior of a cyclic system via a graph-theoretical approach. as a result, the method has significantly lower computational complexity than previously-proposed solutions. a prototype cad tool has been developed to demonstrate the feasibility and efficacy of our method. a set of experiments have been performed on the tool as well as two existing tools, with noticeable improvement on runtime and accuracy for several examples.
efficient placement of distributed on-chip decoupling capacitors in nanoscale ics. decoupling capacitors are widely used to reduce power supply noise. on-chip decoupling capacitors have traditionally been allocated into the white space available on the die based on an unsystematic or ad hoc approach. in this way, large decoupling capacitors are often placed at a significant distance from the current load, compromising the signal integrity of the system. this issue of power delivery cannot be alleviated by simply increasing the size of the on-chip decoupling capacitors. to be effective, the on-chip decoupling capacitors should be placed physically close to the current loads. the area occupied by the on-chip decoupling capacitor, however, is directly proportional to the magnitude of the capacitor. the minimum impedance between the on-chip decoupling capacitor and the current load is therefore fundamentally affected by the magnitude of the capacitor. a distributed on-chip decoupling capacitor network is proposed in this paper. a system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. in a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. related simulation results for typical values of on-chip parasitic resistance are also presented. an analytic solution is shown to provide accurate distributed system. the worst case error is 0.003% as compared to spice. techniques presented in this paper are applicable not only for current technologies, but also provide an efficient placement of the on-chip decoupling capacitors in future technology generations.
victim alignment in crosstalk aware timing analysis. modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (sta) and involves the "victim-aggressor alignment" problem. as delay-noise depends strongly on the skew between the victim-aggressor input transitions', it is not possible to apriori identify the victim input transition that results in the latest arrival time at the victim. several approaches that heuristically search for the worst-case victim-aggressor alignment have been proposed in literature. in this paper we present an analytical result that obviates the need to search for the worst-case victim input transition, thereby simplifying the victim-aggressor alignment problem significantly. using the properties of standard nonlinear cmos drivers, we show that regardless of the switching of the aggressors, the worst-case victim input transition is the one that switches at the latest point in its timing window. although this result has been empirically observed in the industry, to the best of our knowledge, this is the first work that provides a rigorous analysis and shows that the result holds for both linear and non-linear drivers. we also show that limiting the alignment of the victim to only the latest victim input transition can significantly reduce the runtime of existing heuristic techniques with no loss of accuracy.
efficient path delay test generation based on stuck-at test generation using checker circuitry. this paper proposes an approach to non-robust and functionally sensitizable path delay test generation through stuck-at test generation. in this approach, to generate two-pattern tests for path delay faults in a combinational circuit, checker circuitry is constructed which is composed of logic gates corresponding to the mandatory assignments for detecting the faults. this checker circuitry allows us to use any existing combinational stuck-at test generation tool. since today's stuck-at test generation tools reach a mature level, the proposed approach can efficiently solve the path delay test generation problem for combinational circuits. experimental results show that the approach can speed up path delay test generation and can improve fault efficiency. this paper also discusses how a scan circuit and the issues of over-testing and test power are handled in the proposed test generation framework.