waashk/dblp huggingface dataset:
hardware-software trade-offs in a direct rambus implementation of the rampage memory hierarchy. the rampage memory hierarchy is an alternative to the traditional division between cache and main memory: main memory is moved up a level and dram is used as a paging device. the idea behind rampage is to reduce hardware complexity, if at the cost of software complexity, with a view to allowing more flexible memory system design. this paper investigates some issues in choosing between rampage and a conventionalcache architecture, with a view to illustrating trade-offs which can be made in choosing whether to place complexity in the memory system in hardware or in software. performance results in this paper are based on a simple rambus implementation of dram, with performance characteristics of direct rambus, which should be available in 1999. this paper explores the conditions under which it becomes feasible to perform a context switch on a miss in the rampage model, and the conditions under which rampage is a win over a conventional cache architecture: as the cpu-dram speed gap grows, rampage becomes more viable.
tags and type checking in lisp: hardware and software approaches. one of the major factors that distinguishes lisp from many other languages (pascal, c, fortran, etc.) is the need for run-time type checking. run-time type checking is implemented by adding to each data object a tag that encodes type information. tags must be compared for type compatibility, removed when using the data, and inserted when new data items are created. this tag manipulation, together with other work related to dynamic type checking and generic operations, constitutes a significant component of the execution time of lisp programs. this has led both to the development of lisp machines that support tag checking in hardware and to the avoidance of type checking by users running on stock hardware. to understand the role and necessity of special-purpose hardware for tag handling, we first measure the cost of type checking operations for a group of lisp programs. we then examine hardware and software implementations of tag operations and estimate the cost of tag handling with the different tag implementation schemes. the data shows that minimal levels of support provide most of the benefits, and that tag operations can be relatively inexpensive, even when no special hardware support is present.
firmware structure and architectural support for monitors, vertical migration and user microprogramming. this paper describes firmware and hardware support necessary for constructing easy-to-understand and high performance operating systems including language translators and interpreters. basic principles are one-to-one correspondence between logical hierarchy and physical hierarchy, and vertical migration. implementation of monitors in firmware and architectural support for it are discussed, and a sample system is shown. architectural support for user microprogramming is then discussed and an example is shown. after a total system firmware structure is discussed, an experiment of vertical migration is described. it is shown that a proper selection of modules for migration is extremely important. it is suggested that the direction shown in this paper is one of future directions of computer systems.
a real-time support processor for ada tasking. task synchronization in ada causes excessive run-time overhead due to the complex semantics of the rendezvous. to demonstrate that the speed can be increased by two orders of magnitude by using special purpose hardware, a single chip vlsi support processor has been designed. by providing predictable and uniformly low overhead for the entire semantics of a rendezvous, the powerful real-time constructs of ada can be used freely without performance degradation. the key to high performance is the set of primitive operations implemented in hardware. each operation is complex enough to replace a considerable amount of code was designed to execute with a minimum of communication overhead. task control blocks are stored on-chip as well as headers for entry, delay and ready queues. all necessary scheduling is integrated in the operations. delays are handled completely on-chip using an internal real-time clock. a multilevel design strategy, based on silicon compilation, made it possible to run actual ada programs on a functional emulator of the chip and use the results to verify the detailed design. a high degree of parallelism and pipelining together with an elaborate internal addressing scheme has reduced the number of clock cycles needed to perform each operation. using 2 &mgr;m cmos, the processor can run at 20 mhz. a complex rendezvous, including the calling sequence and all necessary scheduling, can be performed in less than 15 &mgr;s.
integer multiplication and division on the hp precision architecture. in recent years, many architectural design efforts have focused on maximizing performance for frequently executed, simple instructions. the authors describe how a small set of primitive instructions combined with what is considered careful frequency analysis and clever programming allows the hewlett-packard (hp) precision architecture integer multiplication and division implementation to provide adequate performance at little or no hardware cost.
schedule-independent storage mapping for loops. this paper studies the relationship between storage requirements and performance. storage-related dependences inhibit optimizations for locality and parallelism. techniques such as renaming and array expansion can eliminate all storage-related dependences, but do so at the expense of increased storage. this paper introduces the universal occupancy vector (uov) for loops with a regular stencil of dependences. the uov provides a schedule-independent storage reuse pattern that introduces no further dependences (other than those implied by true flow dependences). ov-mapped code requires less storage than full array expansion and only slightly more storage than schedule-dependent minimal storage.we show that determine if a vector is a uov is npcomplete. however, an easily constructed but possibly nonminimal uov can be used. we also present a branch and bound algorithm which finds the minimal uov, while still maintaining a legal uov at all times.our experimental results show that the use of ov-mapped storage, coupled with tiling for locality, achieves better performance than tiling after array expansion, and accommodates larger problem sizes than untilable, storage-optimized code. f'urthermore, storage mapping based on the uov introduces negligible runtime overhead.
sentinel scheduling for vliw and superscalar processors. speculative execution is an important source of parallelism for vliw and superscalar processors. a serious challenge with compiler-controlled speculative execution is to accurately detect and report all program execution errors at the time of occurrence. in this paper, a set of architectural features and compile-time scheduling support referred to as sentinel scheduling is introduced. sentinel scheduling provides an effective framework for compiler-controlled speculative execution that accurately detects and reports all exceptions. sentinel scheduling also supports speculative execution of store instructions by providing a store buffer which allows probationary entries. experimental results show that sentinel scheduling is highly effective for a wide range of vliw and superscalar processors.
dependance based prefetching for linked data structures. we introduce a dynamic scheme that captures the accesspat-terns of linked data structures and can be used to predict future accesses with high accuracy. our technique exploits the dependence relationships that exist between loads that produce addresses and loads that consume these addresses. by identzj+ing producer-consumer pairs, we construct a compact internal representation for the associated structure and its traversal. to achieve a prefetching eflect, a small prefetch engine speculatively traverses this representation ahead of the executing program. dependence-based prefetching achieves speedups of up to 25% on a suite of pointer-intensive programs.
coding guidelines for pipelined processors. this paper is a tutorial for assembly language programmers of pipelined processors. it describes the general characteristics of pipelined processors and presents a collection of coding guidelines for them. these guidelines are particularly significant to compiler developers who determine object code patterns.
timestamp snooping: an approach for extending smps. symmetric multiprocessor (smp) servers provide superior performance for the commercial workloads that dominate the internet. our simulation results show that over one-third of cache misses by these applications result in cache-to-cache transfers, where the data is found in another processor's cache rather than in memory. smps are optimized for this case by using snooping protocols that broadcast address transactions to all processors. conversely, directory-based shared-memory systems must indirectly locate the owner and sharers through a directory, resulting in larger average miss latencies.this paper proposes timestamp snooping, a technique that allows smps to i) utilize high-speed switched interconnection networks and ii) exploit physical locality by delivering address transactions to processors and memories without regard to order. traditional snooping requires physical ordering of transactions. timestamp snooping works by processing address transactions in a logical order. logical time is maintained by adding a few bits per address transaction and having network switches perform a handshake to ensure on-time delivery. processors and memories then reorder transactions based on their timestamps to establish a total order.we evaluate timestamp snooping with commercial workloads on a 16-processor sparc system using the simics full-system simulator. we simulate both an indirect (butterfly) and a direct (torus) network design. for oltp, dss, web serving, web searching, and one scientific application, timestamp snooping with the butterfly network runs 6-28% faster than directories, at a cost of 13-43% more link traffic. similarly, with the torus network, timestamp snooping runs 6-29% faster for 17-37% more link traffic. thus, timestamp snooping is worth considering when buying more interconnect bandwidth is easier than reducing interconnect latency.
secure program execution via dynamic information flow tracking. we present a simple architectural mechanism called dynamic information flow tracking that can significantly improve the security of computing systems with negligible performance overhead. dynamic information flow tracking protects programs against malicious software attacks by identifying spurious information flows from untrusted i/o and restricting the usage of the spurious information.every security attack to take control of a program needs to transfer the program's control to malevolent code. in our approach, the operating system identifies a set of input channels as spurious, and the processor tracks all information flows from those inputs. a broad range of attacks are effectively defeated by checking the use of the spurious values as instructions and pointers.our protection is transparent to users or application programmers; the executables can be used without any modification. also, our scheme only incurs, on average, a memory overhead of 1.4% and a performance overhead of 1.1%.
speculative synchronization: applying thread-level speculation to explicitly parallel applications. barriers, locks, and flags are synchronizing operations widely used programmers and parallelizing compilers to produce race-free parallel programs. often times, these operations are placed suboptimally, either because of conservative assumptions about the program, or merely for code simplicity.we propose speculative synchronization, which applies the philosophy behind thread-level speculation (tls) to explicitly parallel applications. speculative threads execute past active barriers, busy locks, and unset flags instead of waiting. the proposed hardware checks for conflicting accesses and, if a violation is detected, offending speculative thread is rolled back to the synchronization point and restarted on the fly. tls's principle of always keeping a safe thread is key to our proposal: in any speculative barrier, lock, or flag, the existence of one or more safe threads at all times guarantees forward progress, even in the presence of access conflicts or speculative buffer overflow. our proposal requires simple hardware and no programming effort. furthermore, it can coexist with conventional synchronization at run time.we use simulations to evaluate 5 compiler- and hand-parallelized applications. our results show a reduction in the time lost to synchronization of 34% on average, and a reduction in overall program execution time of 7.4% on average.
slipstream processors: improving both performance and fault tolerance. processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. we propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. the shortened program is run concurrently with the full program on a chip multiprocessor simultaneous multithreaded processor, with two key advantages:1) improved single-program performance. the shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. the full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. the two programs combined run faster than the original program alone. detailed simulations of an example implementation show an average improvement of 7% for the spec95 integer benchmarks.2) fault tolerance. the shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.
superoptimizer - a look at the smallest program. given an instruction set, the superoptimizer finds the shortest program to compute a function. startling programs have been generated, many of them engaging in convoluted bit-fiddling bearing little resemblance to the source programs which defined the functions. the key idea in the superoptimizer is a probabilistic test that makes exhaustive searches practical for programs of useful size. the search space is defined by the processor's instruction set, which may include the whole set, but it is typically restricted to a subset. by constraining the instructions and observing the effect on the output program, one can gain insight into the design of instruction sets. in addition, superoptimized programs may be used by peephole optimizers to improve the quality of generated code, or by assembly language programmers to improve manually written code.
empirical analysis of the mesa instruction set. this paper describes recent work to refine the instruction set of the mesa processor. mesa [8] is a high level systems implementation language developed at xerox parc during the middle 1970's. typical systems written in mesa are large collections of programs running on single-user machines. for this reason, a major design goal of the project has been to generate compact object programs. the computers that execute mesa programs are implementations of a stack architecture [5]. the instructions of an object program are organized into a stream of eight bit bytes. the exact complement into of instructions in the architecture has changed as the language and machine micro architecture have evolved. in sections 3 and 4, we give a short history of the mesa instruction set and discuss the motivation for our most recent analysis of it. in section 5, we discuss the tools and techniques used in this analysis. section 6 shows the results of this analysis as applied to a large sample of approximately 2.5 million instruction bytes. sections 7 and 8 give advice to others who might be contemplating similar analyses.
communication scheduling. the high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect between functional units and register files. communication scheduling enables scheduling to these emerging architectures, including those that use shared buses and register file ports. scheduling to these shared interconnect architectures is difficult because it requires simultaneously allocating functional units to operations and buses and register file ports to the communications between operations. prior vliw scheduling algorithms are limited to clustered register file architectures with no shared buses or register file ports. communication scheduling extends the range of target architectures by making each communication explicit and decomposing it into three components: a write stub, zero or more copy operations, and a read stub. communication scheduling allows media processing kernels to achieve 98% of the performance of a central register file architecture on a distributed register file architecture with only 9% of the area, 6% of the power consumption, and 37% of the access delay, and 120% of the performance of a clustered register file architecture on a distributed register file architecture with 56% of the area and 50% of the power consumption.
performance and architectural evaluation of the psi machine. we evaluated a prolog machine psi (personal sequential inference machine) for the purpose of improving and redesigning it. in this evaluation, we measured the execution speed and the dynamic characteristics of cache memory, register file, and branching hardware introduced for high-speed execution of prolog programs.execution speed of the psi firmware interpreter was found to be comparable to that of the dec-10 prolog compiled code on the dec-2060. it was also found that psi was faster than dec for executing programs containing much unification and backtracking that require runtime processing.with the cache memory, the hit ratio for application programs was found higher than 96%; this demonstrates that the prolog execution has much memory access locality. the memory access frequency and the appearance ratio between read and write command were also investigated.concerning the register file, use rate of each dedicated access mode was measured and effect of each mode was discussed. in the branching function we confirmed a high appearance rate of conditional branches and multi-way branches based on tag values.
contrasting characteristics and cache performance of technical and multi-user commercial workloads. experience has shown that many widely used benchmarks are poor predictors of the performance of systems running commercial applications. research into this anomaly has long been hampered by a lack of address traces from representative multi-user commercial workloads. this paper presents research, using traces of industry-standard commercial benchmarks, which examines the characteristic differences between technical and commercial workloads and illustrates how those differences affect cache performance.commercial and technical environments differ in their respective branch behavior, operating system activity, i/o, and dispatching characteristics. a wide range of uniprocessor instruction and data cache geometries were studied. the instruction cache results for commercial workloads demonstrate that instruction cache performance can no longer be neglected because these workloads have much larger code working sets than technical applications. for database workloads, a breakdown of kernel and user behavior reveals that the application component can exhibit behavior similar to the operating system and therefore, can experience miss rates equally high. this paper also indicates that &ldquo;dispatching&rdquo; or process switching characteristics must be considered when designing level-two caches. the data presented shows that increasing the associativity of second-level caches can reduce miss rates significantly. overall, the results of this research should help system designers choose a cache configuration that will perform well in commercial markets.
surpassing the tlb performance of superpages with less operating system support. many commercial microprocessor architectures have added translation lookaside buffer (tlb) support for superpages. superpages differ from segments because their size must be a power of two multiple of the base page size and they must be aligned in both virtual and physical address spaces. very large superpages (e.g., 1mb) are clearly useful for mapping special structures, such as kernel data or frame buffers. this paper considers the architectural and operating system support required to exploit medium-sized superpages (e.g., 64kb, i.e., sixteen times a 4kb base page size). first, we show that superpages improve tlb performance only after invasive operating system modifications that introduce considerable overhead.we then propose two subblock tlb designs as alternate ways to improve tlb performance. analogous to a subblock cache, a complete-subblock tlb associates a tag with a superpage-sized region but has valid bits, physical page number, attributes, etc., for each possible base page mapping. a partial-subblock tlb entry is much smaller than a complete-subblock tlb entry, because it shares physical page number and attribute fields across base page mappings. a drawback of a partial-subblock tlb is that base page mappings can share a tlb entry only if they map to consecutive physical pages and have the same attributes. we propose a physical memory allocation algorithm, page reservation, that makes this sharing more likely. when page reservation is used, experimental results show partial-subblock tlbs perform better than superpage tlbs, while requiring simpler operating system changes. if operating system changes are inappropriate, however, complete-subblock tlbs perform best.
an analysis of a mesa instruction set using dynamic instruction frequencies. the mesa architecture is implemented on a variety of processors, and dynamic instruction frequency data for two programs is used to analyze the architecture in an implementation independent fashion. the mesa compiler allocates variables in an order based upon their static frequency of use, and measurements are provided that show that these static predictions predict run time usage as well. we provide an evaluation of the advantages and costs of mesa's compact byte encoding, its reliance upon an evaluation stack, and its use of memory. the mesa language has evolved over time in a hardware environment oriented around 16-bit quantities with growing use of and accommodations to 32-bit quantities. the cost of emulating 32-bit data paths on a 16-bit machine is identified for a program that heavily exploits longer values. several potential areas for improving the execution speed of a mesa processor with special purpose hardware are identified.