waashk/dblp huggingface dataset:
extraction of circuit models for substrate cross-talk. an increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. this paper proposes a boundary element method (bem) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification.in contrast with standard be methods, we propose a green's function which is specific to the domain and the problem. this allows minimal discretization and a direct extraction of circuit models for the cross-talk. the extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. the complete extraction process has a linear time complexity and a constant memory usage. the method is fully implemented and integrated in an existing layout-to-circuit extractor.
a new surface integral formulation for wideband impedance extraction of 3-d structures. detailed electromagnetic analysis of three-dimensional structures in multi-layereddielectric media is critical for automatic generation of equivalentcircuit models for the interconnects and packages in rf or mixed signalintegrated circuits. in this paper we present a new wideband surface integralformulation that can be readily combined with the well-establishedlayered green's function techniques. in discretizing the formulation, wehave used the well-known rwg linear basis function to reduce the numberof unknowns. using a so-called loop-star basis transformation andthe frequency normalization, the accuracy at low frequencies has beenimproved substantially. several numerical examples are used to validatethe accuracy and robustness of this new formulation.
maze router without a grid map. it is pointed out that maze routers provide powerful and flexible routing algorithms, but require storage of information for every routing grid and layer. the number of these grids is often so large that routing programs either run out of memory or become very slow due to excessive paging. a data organization which, with certain modifications to the algorithm, reduces and possibly eliminates the entire grid map is presented. the router has been coded with a special data structure library
retiming with non-zero clock skew, variable register, and interconnect delay. a retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. these delay components are incorporated into retiming by assigning register electrical characteristics (recs) to each edge in the graph representation of the synchronous circuit. a matrix (called the sequential adjacency matrix or sam) is presented that contains all path delays. timing constraints for each data path are derived from this matrix. vertex lags are assigned ranges rather than single values as in standard retiming algorithms. the approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. the algorithm is demonstrated on modified mcnc benchmark circuits and both increased clock frequencies and elimination of all race conditions are observed.
eda and the network. digital computer networks are playing an increasingly important role in the evaluation, distribution, integration and management of eda systems. tools, libraries, design data, and a variety of both design and manufacturing services are accessible today via networks. networks are also playing a central role in the integration of system design teams, teams that involve a variety of both business and technical disciplines as well as widely distributed geographical locations. throughout the history of eda, the architectures used to integrate and distribute computation and interaction have played a central role in the overall design methodology and so have had a major, indirect impact on the choice of the most effective tools, algorithms, and data structures. in this paper, a number of the factors involved in the choice of a suitable architecture for eda integration are reviewed and a number of ongoing developments and challenges are presented.
an automated technique for topology and route generation of application specific on-chip interconnection networks. network-on-chip (noc) has been proposed as a solution to the communication challenges of system-on-chip (soc) design in nanoscale technologies. application specific soc design offers the opportunity for incorporating custom noc architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. custom noc design in nanoscale technologies must address performance requirements, power consumption and physical layout considerations. this paper presents a novel three phase technique that i) generates a performance aware layout of the soc, ii) maps the cores of the soc to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. we present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks.
improving soft-error tolerance of fpga configuration bits. soft errors that change configuration bits of an sram based fpga modify the functionality of the design. the proliferation of fpga devices in various critical applications makes it important to increase their immunity to soft errors. in this work, we propose the use of an asymmetric sram (asram) structure that is optimized for soft error immunity and leakage when storing a preferred value. the key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. consequently, the use of asram cell optimized for storing a zero (asram-0) reduces the failure in time by 25% as compared to the original design. we also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.
detailed layer assignment for mcm routing. a routing environment mode, called the k-mcm model, is developed to take into account the unique features of a multilayer multichip module (mcm) such as the availability of segmented vias, and the presence of two active or terminal-bearing layers. a detailed layer assignment problem is formulated on the k-mcm model. a fast heuristic algorithm for the layer assignment problem is proposed and experimental results on twelve test examples with net counts up to 842 are presented
performance analysis of carbon nanotube interconnects for vlsi applications. the work in this paper analyses the applicability of carbon nanotube (cnt) bundles as interconnects for vlsi circuits, while taking into account the practical limitations in this technology. a model is developed to calculate equivalent circuit parameters for a cnt-bundle interconnect based on interconnect geometry. using this model, the performance of cnt-bundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. it is shown that cnt bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. the technological requirements necessary to make cnt bundles viable as future interconnects are also laid out.
timing driven gate duplication: complexity issues and algorithms. this paper addresses the issue of timing driven gate duplication for delay optimization. gate duplication has been used extensively for cutset minimization but the usefulness in minimizing the circuit delay has not been addressed. this paper studies the complexity issues in timing driven gate duplication and proposes an algorithm for solving the so called global gate duplication problem. delay improvements over highly optimized results from sis have been reported.
achieving design closure through delay relaxation parameter. current design automation methodologies are becoming incapableof achieving design closure especially in the presence of deep submicroneffects. this paper addresses the issue of design closure from ahigh level point of view. a new metric called delay relaxation parameter(drp) for rtl (register transfer level) designs is proposed. drpessentially captures the degree of delay relaxation that the design cantolerate without violating the clock constraint. this metric when optimizedresults in quicker design flow. algorithms to optimize drp areformulated and their optimality are investigated. experimental resultsare conducted using a state of the art design flow with synopsys designcompiler followed by cadence place and route. our approachof optimizing drp resulted in lesser design iterations and faster designclosure as compared to designs generated through synopsys behavioralcompiler and a representative academic design flow.
predictability: definition, ananlysis and optimization. predictability is the quantified from of accuracy. we propose a predictability driven design methodology. the novelty lies in defining and using the idea of predictability. in order to illustrate the basic concepts we focus on the low power binding problem. the binding problem for low power was solved in [3], [5], but in the presence of in-accuracies, their claims of optimality are imprecise. our experiments show that these inaccuracies could be as high as 33%. our methodology could improve this unpredictability to as low as 11% with minimal power penalty (7% on average).
a general framework for probabilistic low-power design space exploration considering process variation. increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. this work presents a convex optimization based approach to select supply and threshold voltages to minimize power dissipation in generic multi-vdd/vth cmos designs while considering process variation. we use this probabilistic approach to compare the optimization of different statistical parameters of power dissipation (e.g., mean or high percentile points), and quantify the impact of rising process variations on these power minimization techniques.
binding, allocation and floorplanning in low power high-level synthesis. this work is a contribution to high level synthesis for lowpower systems.while device feature size decreases, interconnectpower becomes a dominating factor.thus it is importantthat accurate physical information is used during high-level synthesis.we propose a new power optimisation algorithm for rt-levelnetlists.the optimisation performs simultaneously slicing-treestructure-based floorplanning and functional unit binding andallocation.since floorplanning, binding and allocation can use theinformation generated by the other step, the algorithm can greatlyoptimise the interconnect power.compared to interconnect unawarepower optimised circuits, it shows that interconnect powercan be reduced by an average of 41.2%, while reducing overallpower by 24.1% on an average.the functional unit power remainsnearly unchanged.these optimisations are not achieved atthe expense of area.
dynamic fault-tolerance and metrics for battery powered, failure-prone systems. emerging vlsi technologies and platforms are giving rise tosystems with inherently high potential for runtime failure.such failures range from intermittent electrical and mechanicalfailures at the system level, to device failures at the chip level.techniques to provide reliable computation in the presence offailures must do so while maintaining high performance, withan eye toward energy efficiency. when possible, they shouldmaximize battery lifetime in the face of battery discharge non-linearities. this paper introduces the concept of adaptive fault-tolerance management for failure-prone systems, and a classification of local algorithms for achieving system-wide reliability.in order to judge the efficacy of the proposed algorithmsfor dynamic fault-tolerance management, a set of metrics, forcharacterizing system behavior in terms of energy efficiency,reliability, computation performance and battery lifetime, ispresented. for an example platform employed in a realistic evaluation scenario, it is shown that system configurations with the best performance and lifetime are not necessarilythose with the best combination of performance, reliability,battery lifetime and average power consumption.
digital rf processor (drp/spl trade/) for cellular phones. rf circuits for multi-ghz frequencies have recently migrated to low-cost digital deep-submicron cmos processes. unfortunately, this process environment, which is optimized only for digital logic and sram memory, is extremely unfriendly for conventional analog and hf designs. we present fundamental techniques recently developed that transform the rf and analog circuit design complexity to digital domain for a wireless rf transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. all-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct hf sampling techniques allow great flexibility in reconfigurable radio design. digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. software layers are defined to enable these architectures to develop an efficient software defined radio. vhdl hardware description language is universally used throughout this soc. the ideas presented have been used in texas instruments to develop two generations of commercial digital rf processors: a single-chip bluetooth radio and a single-chip gsm radio.
analog performance space exploration by fourier-motzkin elimination with application to hierarchical sizing. analog performance space exploration identifies the range of feasible performance values of a given circuit topology. it is an extremely challenging task of great importance to topology selection and hierarchical sizing. in this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. to this end, fundamental circuit design knowledge is described by constraint functions. based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. practical application results demonstrate the efficiency and usefulness of the new method.
initial sizing of analog integrated circuits by centering within topology-given implicit specification. we present a novel technique to automatically calculate an initialsizing of analog circuits that conforms to good design practice.the method is purely (dc) simulation-based and does not needsymbolic design equations or user design knowledge. it identifiesthe space of feasible design parameters based on implicit specifications, which arise from the circuit topology. a sizing centeredwithin this space is obtained by iteratively solving a maximum volume ellipsoid problem on approximations to the feasible parameter space. the result is well-suited as initial sizing because it safely satisfies all implicit specifications. experimental results demonstrate the efficiency and reliability of our method.
new decompilation techniques for binary-level co-processor generation. existing asips (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded applications while consuming less power than high-performance gigahertz microprocessors. however, existing approaches place restrictions on software languages and compilers. binary-level co-processor generation has previously been proposed as a complementary approach to reduce impact on tool restrictions, supporting all languages and compilers, at the cost of some decrease in performance. in a binary-level approach, decompilation recovers much of the high-level information, like loops and arrays, needed for effective synthesis, and in many cases yields hardware similar to that of a compiler-based approach. however, previous binary-level approaches have not considered the effects of software compiler optimizations on the resulting hardware. in this paper, we introduce two new decompilation techniques, strength promotion and loop rerolling, and show that they are necessary to synthesize an efficient custom hardware coprocessor from a binary in the presence of software compiler optimizations. in addition, unlike previous approaches, we show the robustness of binary-level co-processor generation by achieving order of magnitude speedups for binaries generated for three different instruction sets, mips, arm, and microblaze, using two different levels of compiler optimizations.
hardware/software partitioning of software binaries. partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. the advent of single-chip microprocessor/fpga platforms makes such partitioning even more attractive. previous partitioning approaches have partitioned sequential program source code, such as c or c++. we introduce a new approach that partitions at the software binary level. although source code partitioning is preferable from a purely technical viewpoint, binary-level partitioning provides several very practical benefits for commercial acceptance. we demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned on a single-chip microprocessor/fpga device.
verification of integer multipliers on the arithmetic bit level. one of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. in this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. we propose a boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. experimental results show the promise of our approach.
record & play: a structural fixed point iteration for sequential circuit verification. this paper proposes a technique for sequential logic equivalence checking by a structural fixed point iteration. verification is performed by expanding the circuit into an iterative circuit array and by proving equivalence of each time frame by well-known combinational verification techniques. these exploit structural similarity between designs by local circuit transformations. starting from the initial state, for each time frame the performed circuit transformations are stored (recorded) in an instruction queue. in subsequent time frames the instruction queue is re-used (played) and updated when necessary. at some point the instruction queue does not need to be modified any more and is valid in all subsequent time frames. thus, a fixed point is reached and machine equivalence is proved by induction. experimental results show the great promise of this approach to verify circuits after resynthesis and retiming.
test register insertion with minimum hardware cost. implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. such a scheme is implemented by test registers, for instance bilbos and cbilbos, which are inserted into the circuit structure at appropriate places. an algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the iscas'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs is obtained for all the circuits within a few minutes of computing time. the algorithm can also be applied to the minimum feedback vertex set problem in partial scan design, and an optimal solution is found for all the benchmark circuits. the resulting self-testable circuits are analyzed. it is found that often cbilbos lead to a minimum hardware overhead and also simplify test scheduling and test control.
design-manufacturing interface for 0.13 micron and below. over the years, the increase in ic functionality has been achieved by a continuous drive towards smaller feature sizes. due to the decreasing dimensions of semiconductor structures, the sensitivity to critical design and manufacturing parameters has risen dramatically. vertical integration techniques and multi-level interconnect, which are becoming more common in modern technologies, have driven up the number of critical processing steps to several hundreds. these trends are expected to continue for the next several decades. the .13 micron technology is around the corner, as well as 300mm wafers. the increase in ic functionality has come with a skyrocketing capital spending (more than $2 billion per fabrication facility). moreover, the product life cycles for leading edge ic's have become very short (less than 2 years).
impulse response fault model and fault extraction for functional level analog circuit diagnosis. in this paper, a functional fault model for analog circuit diagnosis is proposed. a faulty module is modeled as a fault-free module in serial or in parallel with a fault module. to extract such a fault module, we adopt an iterative deconvolution technique to deconvolute the impulse response of the fault module from the faulty response. the test results show that with such a fault model and fault extraction technique the diagnostic resolution is improved significantly due to the separation of the fault and the system function. moreover, such a fault model allows single-module fault tables to be applied to the diagnosis of a multi-module system.
metrology for analog module testing using analog testability bus. in this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. for the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the cut. the test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. with the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.
fast analysis and optimization of power/ground networks. this paper presents an efficient method for optimizing power/ground (p/g) networks. it proposes a structured skeleton that is intermediate to the conventional method that uses full meshes (which are hard to analyze efficiently), and tree-structured p/g networks (which provide poor performance). as an example, we consider a p/g network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. a fast and efficient event-driven p/g network simulator is proposed, which hierarchically simulates the p/g network with an adaptation of prima to handle non-zero initial conditions. an adjoint network that incorporates the variable topology of the original p/g network, as elements switch in and out of the network, is constructed to calculate the transient adjoint sensitivity over multiple intervals. these are used to drive a sensitivity-based heuristic optimization method. experimental results show that this procedure can be used to efficiently optimize large networks.