waashk/dblp huggingface dataset:
mc-sim: an efficient simulation tool for mpsoc designs. the ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (noc) communication frameworks onto a single chip has greatly increased the design space available for system-on-chip (soc) designers. efficient and accurate performance estimation tools are needed to assist the designer in making design decisions. in this paper, we present mc-sim, a heterogeneous multi-core simulator framework which is capable of accurately simulating a variety of processor, memory, noc configurations and application specific coprocessors. we also describe a methodology to automatically generate fast, cycle-true behavioral, c-based simulators for coprocessors using a high-level synthesis tool and integrate them with mc-sim, thus augmenting it with the capacity to simulate coprocessors. our c-based simulators provide on an average 45x improvement in simulation speed over that of rtl descriptions. we have used this framework to simulate a number of real-life applications such as the mpeg4 decoder and litho-simulation, and experimented with a number of design choices. our simulator framework is able to accurately model the performance of these applications (only 7% off the actual implementation) and allows us to explore the design space rapidly and achieve interesting design implementations
including inductance in static timing analysis. in this paper analytical expressions are derived for effective load capacitances of rlc interconnects to accurately estimate both the propagation delay and transition time at the output of a cmos gate. the new effective capacitance calculation technique poses no extra complexity as compared to the rc based approaches but can accommodate inductance. these new expressions are derived based on a generalized driving point admittance. the generalized driving point admittance takes inductance into consideration and hence accounts for the inductive shielding that in some cases can even exceed the resistive shielding in current technologies. another improvement in the new effective capacitance calculation method is the utilization of a more general waveform shape that accounts for the non-monotonic behavior due to inductance effects. it is shown throughout the paper that two effective capacitances are required for accurate estimation of the propagation delay and rise time with an rlc interconnect load. simulation results show that the error in propagation delays and rise times when neglecting inductance can be over 60% as compared to an rlc model in realistic interconnects. on the other hand, simulations show that the propagation delay and rise time maximum errors associated with the proposed approach are less than 10% as compared to spice.
frequency-aware ppv: a robust phase macromodel for accurate oscillator noise analysis. perturbation projection vector (ppv) is an established technique for oscillator phase noise analysis; however, the ppv method significantly loses accuracy when circuits have large time constants, resulting in over-estimation of oscillator phase noise. in this paper, we show the problem of the ppv phase equation that it ignores the dynamics of oscillator frequency responses, and propose an improved ppv technique: frequency-aware ppv (fw-ppv). using the fw-ppv technique, we derive analytical phase noise equations, which work accurately for all oscillators, especially for oscillators with large time constants. we apply the proposed technique on real oscillator circuits, and compare the results to cadence spectre rf. simulation results show that our method has better accuracy than previous approaches.
sparse and passive reduction of massively coupled large multiport interconnects. the large number of ports in an interconnect structure is a critical limiting factor when applying model-order reduction. this is due to the fact that the size of the reduced model grows rapidly with increasing the number of ports, leading to large and dense circuit matrices. to address this problem, a novel method based on transverse partitioning and waveform relaxation is proposed for passive model-order reduction of massively coupled large multiport interconnects. the new method effectively replaces the tightly coupled multiport reduced model with decoupled 2-port subcircuits. in addition to preserving the advantages of model-order reduction, the computational complexity of the new method grows only linearly with the number of lines.
the analysis of cyclic circuits with boolean satisfiability. the accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. and yet simple examples suggest that this need not be so. in previous work, we advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). we proposed a synthesis methodology and demonstrated that it produces significant improvements in area and in delay. the analysis method that we used to validate cyclic circuits was based on binary decision diagrams. in this paper, we propose a much more efficient technique for analysis based on boolean satisfiability (sat).
a fast band-matching technique for interconnect inductance modeling. sparsification of the inverse of inductance matrix l has been widely used to facilitate the interconnect simulation. the band-matching proposed in [5] was proven to be stable and optimal. however, the technique in [5] exhibits a cubic computation complexity. in this paper, we reveal additional relationship between the entries in band-matching inductance matrices. we propose a fast technique that can calculate the entries in the band-matching approximation, in linear computational time. experiments show accurate results for proposed method with orders of magnitude improvement in computational time.
an efficient algorithm for statistical circuit optimization using lagrangian relaxation. due to the technology scaling down, process variation has become a crucial challenge on both interconnect delay and reliability. to handle the process variation, statistical optimization has emerged as a popular technique for yield improvement. as a relatively new technique, second-order conic programming (socp) has recently attracted very much attention in the literature for statistical circuit optimization. however, we observe significant limitations of socp in its flexibility, accuracy, and scalability for statistical circuit optimization, especially when interconnects are considered. we thus present in this paper an effective and efficient alternative for multi-constrained statistical circuit optimization by both gate and wire sizing using lagrangian relaxation (lr). compared with socp, experimental results show that our lr-based algorithm can achieve much better solution quality by reducing 21% area and obtain 560x speed-up over socp.
modeling, optimization and control of rotary traveling-wave oscillator. rotary traveling-wave oscillator (rtwo) is a recently proposed transmission-line approach for multi-gigahertz rate clock generation. rtwo has the characteristics of both conventional lc tank oscillator and ring oscillator. thus, it is difficult to be analyzed by a general-purpose method. this paper presents a systematic and efficient method for rtwo modeling and optimization. equations for frequency, power dissipation, die area, loop gain and phase noise are formulated in posynomial forms. the resulting optimization problem is relaxed to be a geometric programming (gp) and can be efficiently solved with a convex optimization solver. a novel scheme to control the rotation direction is also suggested for skew control. experimental results show that our method can rapidly compute the globally optimal trade-off and reduce the power by up to 85% for a 11.8 ghz rtwo design. compared to a recently reported low-power methodology, the proposed design scheme can save about 50% of die area and achieve lower power dissipation as well as faster rise/fall time.
on the numbers of variables to represent sparse logic functions. in an incompletely specified function f, don't care values can be chosen to minimize the number of variables to represent f. it is shown that, in incompletely specified functions with k 0's and k 1's, the probability that f can be represented with only p = 2[log2(k + 1)] variables is greater than e-1 = 0.36788. in the case of multiple-output functions, where only the outputs for k input combinations are specified, most functions can be represented with at most p = 2[log2(k+1)] -1 variables. experimental data is shown to support this. because of this property, an ip address table can be realized with a small amount of memory.
voltage island-driven floorplanning. energy efficiency has become one of the most important issues to be addressed in today's system-on-a-chip (soc) designs. one way to lower the power consumption is to reduce the supply voltage. multi-supply voltage (msv) is thus introduced to provide higher flexibility in controlling the power and performance trade-off. in region-based msv, circuits are partitioned into "voltage islands" where each island occupies a contiguous physical space and operates at one supply voltage. these tasks of island partitioning and voltage level assignments should be done simultaneously in the floorplanning process in order to take those important physical information into consideration. in this paper, we consider this core-based voltage island driven floorplanning problem including islands with power down mode, and propose a method to solve it. given a candidate floorplan solution represented by a normalized polish expression, we are able to obtain optimal voltage assignment and island partitioning (including islands with power down mode) simultaneously to minimize the total power consumption. simulated annealing is used as the basic searching engine. by using this approach, we can achieve significant power savings (up to 50%) for all data sets, without any significant increase in area and wire length. our floorplanner can also be extended to minimize the number of level shifters between different voltage islands and to simplify the power routing step by placing the islands in proximity to the corresponding power pins.
on the decreasing significance of large standard cells in technology mapping. technology scaling reduces gate delays while wire delays may increase. our work studies the interaction of this phenomenon with technology mapping and its impact on modern eda flows. in particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65nm and below. experiments with 130nm, 90nm, 65nm, and 45nm industrial cmos technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65nm and 45nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.
enhancing design robustness with reliability-aware resynthesis and logic simulation. while circuit density and power efficiency increase with each major advance in ic technology, reliability with respect to soft errors tends to decrease. current solutions to this problem such as tmr require high area and power overhead. in this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. the key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. we describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. a key feature of these techniques is fast, on-the-fly estimation of soft error rate (ser) using our reliability evaluator anser. this tool is compared against prior ser evaluators and found to run orders of magnitude faster. we show empirically that our reliability-driven synthesis methods can reduce ser by 29--40% with only 5--13% area overhead.
network flow-based power optimization under timing constraints in msv-driven floorplanning. power consumption has become a crucial problem in modern circuit design. multiple supply voltage (msv) design is introduced to provide higher flexibility in controlling the power and performance tradeoff. one important requirement of msv design is that timing constraints of the circuit must be satisfied after voltage assignment of the cells. in this paper, we will show that the voltage assignment task on a given netlist can be formulated as a convex cost dual network flow problem and can be solved optimally in polynomial time using a cost-scaling algorithm when the delay choices of each module are continuous in the real or integer domain. we can make use of this approach to obtain a feasible voltage assignment solution in the general cases with power consumption approximating the minimum one. furthermore, we will propose a framework to optimize power consumption and physical layout of a circuit simultaneously during the floorplanning stage, by embedding this cost-scaling solver into a simulated annealing based floorplanner. this is effective in practice due to the short running time of the solver. we compared our approach with the latest work [9] on the same problem, and the experimental results show that, using our framework, significant improvement on power saving (18% less power cost on average) can be achieved in much less running time (7x faster on average) for all the test cases, which confirms the effectiveness of our approach.
an ilp algorithm for post-floorplanning voltage-island generation considering power-network planning. power optimization is a crucial concern for modern circuit designs. multiple supply voltages (msv's) provide an effective technique for the power optimization. this paper addresses the voltage-island generation problem for msv designs at the post-floorplanning stage. we first present a general formulation of this problem that considers level-shifter planning and power-network routing resources. without loss of solution quality, we propose an economical graph-based representation that needs only a linear number of nodes to the block number to model the block adjacency in a floorplan for the voltage-island generation. in contrast, previous works need a quadratic number of nodes. to tackle the addressed problem, we employ an ilp formulation which consists of (1) level-shifter aware wirelength estimation to capture the timing overhead, (2) voltage-island-clustering inequalities to avoid complicated constraint transformations, and (3) inequalities to capture the power-network routing-resource usage. compared with previous works, our algorithm can produce better voltage islands in terms of power-network routing resources. experimental results show that our algorithm can effectively reduce the power-network routing resource by up to 19.46% with a reasonable overhead of 4.03% more power consumption and using reasonable running time.
archer: a history-driven global routing algorithm. global routing is an important step in the physical design process. in this paper, we propose a new global routing algorithm archer, which resolves some of the most common problems with the state-of-the-art global routers. it is known that concurrent global routing algorithms are typically too expensive to be applied on today's large designs, which may contain up to a million nets. on the other hand, iterative rip-up and reroute (rnr) based algorithms are susceptible to getting stuck in local optimal solutions. in this paper, we propose an rnr-based global routing algorithm that guides the routing iterations out of local optima through effective usage of congestion histories. we also focus on the problem of how to enable a smooth trade-off between seemingly conflicting objectives of overflow and wirelength minimization. furthermore, we propose a lagrangian relaxation based bounded-length min-cost topology improvement algorithm that enables steiner trees to change dynamically for the purpose of congestion optimization. our experiments show that archer obtains congestion-free solutions for all circuits in the standard ispd98 benchmarks, which is the best result published so far. furthermore, it produces better results than the best results reported in the ispd-07 global routing contest in terms of routability. compared to fastroute [18, 19], which is the state-of-the-art rnr-based global routing algorithm, archer improves routability by 30%, and reduces the wirelengths by 32% on the average on ispd07 benchmarks.
bounding l2 gain system error generated by approximations of the nonlinear vector field. typical nonlinear model order reduction approaches need to address two issues: reducing the order of the model, and approximating the vector field. in this paper we focus exclusively on the second issue, and present results characterizing the repercussions at the system level of vector field approximations. the error assessment problem is formulated as the l2 gain upper bounding problem of a scaled feedback interconnection. applying the small gain theorem in the proposed setup, we prove that the l2 gain of the error system is upper bounded by the l2 gain of the vector field approximation error, provided it is small. in addition, the paper also presents a numerical procedure, based on the iqc/lmi approach, to perform the error estimation task with less conservatism. a numerical example is given in this paper to demonstrate the practical implications of the presented results.
sensitivity analysis for oscillators. this paper presents an analysis for calculating sensitivities of an oscillator's periodic steady-state and perturbation projection vector to design, process, or environmental parameters. a general continuous-time formulation is described. applications of the oscillator sensitivity analysis in design optimization and macromodeling are demonstrated through examples.
what can brain researchers learn from computer engineers and vice versa? the human brain is a network containing a hundred billion neurons, each communicating with several thousand others. as the wiring for neuronal communication draws on limited space and energy resources, evolution had to optimize their use. this principle of minimizing wiring costs, similar to that in computer design, explains many features of brain architecture, including placement and shape of many neurons. however, the shape of some neurons and their synaptic properties remained unexplained. this led us to the principle of maximization of brain's ability to store information. combination of the two principles provides a systematic view of brain architecture, necessary to explain brain function. it would be interesting to see whether advances in understanding brain function will make impact on computer design. the acm portal is published by the association for computing machinery. copyright © 2010 acm, inc. terms of usage privacy policy code of ethics contact us useful downloads: adobe acrobat quicktime windows media player real player
parallel domain decomposition for simulation of large-scale power grids. this paper presents fully parallel domain decomposition (dd) techniques for efficient simulation of large-scale linear circuits such as power grids. dd techniques that use non-overlapping and overlapping partitioning of power grids are described in this paper. simulation results show that with the proposed parallel dd framework, existing linear circuit simulators can be extended to handle large-scale power grids. results for circuits with more than four million nodes indicate that parallel dd with lu factorization is most suitable for power grid simulation. however, for densely connected power grids, parallel dd with additive schwarz preconditioning offers maximum scalability and best performance.
analysis and optimization of power-gated ics with multiple power gating configurations. power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. disconnecting gated blocks causes changes in densities of currents flowing through a grid. even in dc conditions, current densities in some grid branches may increase for some gating configurations to the extent of violating electromigration (em) constraints. the existing dc methods for grid sizing optimize the grid area under voltage drop (ir) and em constraints for one configuration of circuit blocks connected to the grid. we show that these methods cannot be directly applied for optimizing power-gated grids. we analyze the effects of em and ir voltage drop in power grids with multiple power gating configurations. based on our analyses, we develop a grid sizing algorithm to satisfy all reliability constraints for all feasible gating configurations. our experimental results indicate that a grid initially sized for all blocks present may be modified to fulfill em and ir constraints for multiple gating schedules with only a small area increase.
exploiting hierarchy and structure to efficiently solve graph coloring as sat. many important eda problems can be formulated as graph coloring, which is a class of the constraint satisfaction problem (csp). this paper makes three contributions. first, we define new encodings for representing csps as equivalent boolean satisfiability (sat) problems: 1) a generalization of the log encoding by using ite trees to select the domain values of a csp variable, so that only conflict clauses are required; and 2) a simplified direct encoding, derived from the direct encoding (where each domain value of a csp variable is indexed by a unique boolean variable) by omitting one of the boolean variables and the at-least-one clause. second, we propose the use of hierarchical encodings that combine several simple encodings to index the domain values of csp variables, in order to produce sat formulas that depend on fewer boolean variables and are easier to solve. third, we study schemes for static ordering of the boolean variables in a conjunctive normal form (cnf) representation of a csp, based on the structure of the csp graph, such that the resulting variable order is used for the decisions made by a sat solver when evaluating the cnf. we compare 12 previously known sat encodings for csp with the two new encodings, as well as with 10 hybrid encodings. with symmetry-breaking constraints enforced, static variable ordering produced up to 2 orders of magnitude speedup. additionally exploiting hierarchical encodings resulted in another order of magnitude speedup.
simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. dual vt assignment and input vector control are two tightly coupled leakage reduction techniques. we study how to apply them effectively to a circuit to minimize the static leakage power. we argue that simply combining them in a serial fashion will not reach their full potential in leakage reduction. to show this, we propose a heuristic algorithm that integrates them into a single optimization loop by assigning the value for primary inputs and vt for logic gates simultaneously. our algorithm leverages the fact that both input vector and threshold voltage vt have great impact on a gate's leakage at standby mode and avoids to assign a gate both low vt and input vector that results high leakage. the selection of input vector and the assignment of vt are integrated seamlessly through the concepts of leakage observability, worst leakage state, and path factor. the proposed algorithm has a low run time complexity and achieves an average 15% leakage reduction on all the iscas and mcnc benchmarks over the serial combination of input vector selection and dual vt assignment.