waashk/dblp huggingface dataset:
coherence decoupling: making use of incoherence. this paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a speculative cache lookup (scl) protocol and a safe, backing coherence protocol. the scl protocol produces a speculative load value, typically from an invalid cache line, permitting the processor to compute with incoherent data. in parallel, the coherence protocol obtains the necessary coherence permissions and the correct value. eventually, the speculative use of the incoherent data can be verified against the coherent data. thus, coherence decoupling can greatly reduce --- if not eliminate --- the effects of false sharing. furthermore, coherence decoupling can also reduce latencies incurred by true sharing. scl protocols reduce those latencies by speculatively writing updates into invalid lines, thereby increasing the accuracy of speculation, without complicating the simple, underlying coherence protocol that guarantees correctness.the performance benefits of coherence decoupling are evaluated using a full-system simulator and a mix of commercial and scientific benchmarks. our results show that 40% to 90% of all coherence misses can be speculated correctly, and therefore their latencies partially or fully hidden. this capability results in performance improvements ranging from 3% to over 16%, in most cases where the latencies of coherence misses have an effect on performance.
where is time spent in message-passing and shared-memory programs? message passing and shared memory are two techniques parallel programs use for coordination and communication. this paper studies the strengths and weaknesses of these two mechanisms by comparing equivalent, well-written message-passing and shared-memory programs running on similar hardware. to ensure that our measurements are comparable, we produced two carefully tuned versions of each program and measured them on closely-related simulators of a message-passing and a shared-memory machine, both of which are based on same underlying hardware assumptions.we examined the behavior and performance of each program carefully. although the cost of computation in each pair of programs was similar, synchronization and communication differed greatly. we found that message-passing's advantage over shared-memory is not clear-cut. three of the four shared-memory programs ran at roughly the same speed as their message-passing equivalent, even though their communication patterns were different.
a look at several memory management units, tlb-refill mechanisms, and page table organizations. virtual memory is a staple in modem systems, though there is little agreement on how its functionality is to be implemented on either the hardware or software side of the interface. the myriad of design choices and incompatible hardware mechanisms suggests potential performance problems, especially since increasing numbers of systems (even embedded systems) are using memory management. a comparative study of the implementation choices in virtual memory should therefore aid system-level designers.this paper compares several virtual memory designs, including combinations of hierarchical and inverted page tables on hardware-managed and software-managed translation lookaside buffers (tlbs). the simulations show that systems are fairly sensitive to tlb size; that interrupts already account for a large portion of memory-management overhead and can become a significant factor as processors execute more concurrent instructions; and that if one includes the cache misses inflicted on applications by the vm system, the total vm overhead is roughly twice what was thought (10--20% rather than 5--10%).
reducing network latency using subpages in a global memory environment. new high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. because pages are the fundamental transfer and access units in remote memory systems, page size is a key performance factor. recently, page sizes of modern processors have been increasing in order to provide more tlb coverage and amortize disk access costs. unfortunately, for high-speed networks, small transfers are needed to provide low latency. this trend in page size is thus at odds with the use of network memory on high-speed networks.this paper studies the use of subpages as a means of reducing transfer size and latency in a remote-memory environment. using trace-driven simulation, we show how and why subpages reduce latency and improve performance of programs using network memory. our results show that memory-intensive applications execute up to 1.8 times faster when executing with 1k-byte subpages, when compared to the same applications using full 8k-byte pages in the global memory system. those same applications using 1k-byte subpages execute up to 4 times faster than they would using the disk for backing store. using a prototype implementation on the dec alpha and an2 network, we demonstrate how subpages can reduce remote-memory fault time; e.g., our prototype is able to satisfy a fault on a 1k subpage stored in remote memory in 0.5 milliseconds, one third the time of a full page.
utlb: a mechanism for address translation on network interfaces. an important aspect of a high-speed network system is the ability to transfer data directly between the network interface and application buffers. such a direct data path requires the network interface to "know" the virtual-to-physical address translation of a user buffer, i.e., the physical memory location of the buffer. this paper presents an efficient address translation architecture, user-managed tlb (utlb), which eliminates system calls and device interrupts from the common communication path. utlb also supports application-specific policies to pin and unpin application memory. we report micro-benchmark results for an implementation on myrinet pc clusters. a trace-driven analysis is used to compare the utlb approach with the interrupt-based approach. it is also used to study the effects of utlb cache size, associativity, and prefetching. our results show that the utlb approach delivers robust performance with relatively small translation cache sizes.
some requirements for architectural support of software debugging. architectural support of high-level, symbolic debugging is described at three levels of abstraction: the user's view of desired debugging functionality, the debugger implementor's view of architectural requirements that support the functionality, and the computer architect's view of architectural features or attributes that implement the requirements. references are made where possible to computing systems that meet the requirements. the paper is written from the viewpoint of debugger implementors, and is addressed primarily to computer architects.
analysis of branch prediction via data compression. branch prediction is an important mechanism in modern microprocessor design. the focus of research in this area has been on designing new branch prediction schemes. in contrast, very few studies address the theoretical basis behind these prediction schemes. knowing this theoretical basis helps us to evaluate how good a prediction scheme is and how much we can expect to improve its accuracy.in this paper, we apply techniques from data compression to establish a theoretical basis for branch prediction, and to illustrate alternatives for further improvement. to establish a theoretical basis, we first introduce a conceptual model to characterize each component in a branch prediction process. then we show that current "two-level" or correlation based predictors are, in fact, simplifications of an optimal predictor in data compression, prediction by partial matching (ppm).if the information provided to the predictor remains the same, it is unlikely that significant improvements can be expected (asymptotically) from two-level predictors, since ppm is optimal. however, there are a rich set of predictors available from data compression, several of which can still yield some improvement in cases where resources are limited. to illustrate this, we conduct trace-driven simulation running the instruction benchmark suite and the spec cint95 benchmarks. the results show that ppm can outperform a two-level predictor for modest sized branch target buffers.
the rio file cache: surviving operating system crashes. one of the fundamental limits to high-performance, high-reliability file systems is memory's vulnerability to system crashes. because memory is viewed as unsafe, systems periodically write data back to disk. the extra disk traffic lowers performance, and the delay period before data is safe lowers reliability. the goal of the rio (ram i/o) file cache is to make ordinary main memory safe for persistent storage by enabling memory to survive operating system crashes. reliable memory enables a system to achieve the best of both worlds: reliability equivalent to a write-through file cache, where every write is instantly safe, and performance equivalent to a pure write-back cache, with no reliability-induced writes to disk. to achieve reliability, we protect memory during a crash and restore it during a reboot (a "warm" reboot). extensive crash tests show that even without protection, warm reboot enables memory to achieve reliability close to that of a write-through file system. adding protection makes memory even safer than a write-through file system while adding essentially no overhead. by eliminating reliability-induced disk writes, rio performs 4-22 times as fast as a write-through file system, 2-14 times as fast as a standard unix file system, and 1-3 times as fast as an optimized system that risks losing 30 seconds of data and metadata.
an overview of the mesa processor architecture. this paper provides an overview of the architecture of the mesa processor, an architecture which was designed to support the mesa programming system [4]. mesa is a high level systems programming language and associated tools designed to support the development of large information processing applications (on the order of one million source lines). since the start of development in 1971, the processor architecture, the programming language, and the operating system have been designed as a unit, so that proper tradeoffs among these components could be made.
software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. tracing garbage collectors traverse references from live program variables, transitively tracing out the closure of live objects. memory accesses incurred during tracing are essentially random: a given object may contain references to any other object. since application heaps are typically much larger than hardware caches, tracing results in many cache misses. technology trends will make cache misses more important, so tracing is a prime target for prefetching.simulation of java benchmarks running with the boehm-de-mers-weiser mark-sweep garbage collector for a projected hardware platform reveal high tracing overhead (up to 65% of elapsed time), and that cache misses are a problem. applying boehm's default prefetching strategy yields improvements in execution time (16% on average with incremental/generational collection for gc-intensive benchmarks), but analysis shows that his strategy suffers from significant timing problems: prefetches that occur too early or too late relative to their matching loads. this analysis drives development of a new prefetching strategy that yields up to three times the performance improvement of boehm's strategy for gc-intensive benchmark (27% average speedup), and achieves performance close to that of perfect timing ie, few misses for tracing accesses) on some benchmarks. validating these simulation results with live runs on current hardware produces average speedup of 6% for the new strategy on gc-intensive benchmarks with a gc configuration that tightly controls heap growth. in contrast, boehm's default prefetching strategy is ineffective on this platform.
systematic protection mechanism design. this work describes an attempt to systematically design a hardware resource protection mechanism when given the requirements of a particular language as a target. the design process is formalized as a structured walk through the multidimensional computer design space towards a hypothetical class of optimal machines. each step in this walk involves a change in the distribution of work between the compiler and run-time system but no change in the source language semantics. the starting point for this walk is the result of a semantic analysis of the language to be implemented; typically, this produces a very high level machine where the compiler, if any, is trivial. the walk ends when no changes result in a net improvement. this does not guarantee that the result is even locally optimal, since the changes tried depend on the ingenuity and persistence of the designer. this design approach has been used to arrive at a practical, general purpose protection mechanism oriented towards the needs of the ada language (preliminary version). this architecture was evaluated by comparing it with the pdp-11/45. for the purpose of this comparison, the protection mechanism was incorporated into a partially specified pdp-11 like instruction set. the number of bits making up the processor state and the number of operations involved in address computation were evaluated. on this basis, the result appears to be competitive and worth further investigation.
a unified vector/scalar floating-point architecture. in this paper we present a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. the goal of this architecture is to yield improved scalar performance while broadening the range of vectorizable applications. for example, reduction operations and recurrences can be expressed in vector form in this architecture. this approach results in greater overall performance for most applications than does the approach of emphasizing peak vector performance. the hardware required to support the enhanced vector capability is insignificant, but allows the execution of two operations per cycle for vectorized code. moreover, the size of the unified vector/scalar register file required for peak performance is an order of magnitude smaller than traditional vector register files, allowing efficient on-chip vlsi implementation. the results of simulations of the livermore loops and linpack using this architecture are presented.
using meta-level compilation to check flash protocol code. building systems such as os kernels and embedded software is difficult. an important source of this difficulty is the numerous rules they must obey: interrupts cannot be disabled for "too long," global variables must be protected by locks, user pointers passed to os code must be checked for safety before use, etc. a single violation can crash the system, yet typically these invariants are unchecked, existing only on paper or in the implementor's mind.this paper is a case study in how system implementors can use a new programming methodology, metalevel compilation (mc), to easily check such invariants. it focuses on using mc to check for errors in the code used to manage cache coherence on the flash shared memory multiprocessor. the only real practical method known for verifying such code is testing and simulation. we show that simple, system-specific checkers can dramatically improve this situation by statically pinpointing errors in the program source. these checkers can be written by implementors themselves and, by exploiting the system-specific information this allows, can detect errors unreachable with other methods. the checkers in this paper found 34 bugs in flash code despite the care used in building it and the years of testing it has undergone. many of these errors fall in the worst category of systems bugs: those that show up sporadically only after days of continuous use. the case study is interesting because it shows that the mc approach finds serious errors in well-tested, non-toy systems code. further, the code to find such bugs is usually 10-100 lines long, written in a few hours, and exactly locates errors that, if discovered during testing, would require several days of investigation by an experienced implementor.the paper presents 8 checkers we wrote, their application to five different protocol implementations, and a discussion of the errors that we found.
available instruction-level parallelism for superscalar and superpipelined machines. superscalar machines can issue several instructions per cycle. superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latency of any functional unit. in this paper these two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism. a parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism for a series of benchmarks. results of these simulations in the presence of various compiler optimizations are presented. the average degree of superpipelining metric is introduced. our simulations suggest that this metric is already high for many machines. these machines already exploit all of the instruction-level parallelism available in many non-numeric applications, even without parallel instruction issue or higher degrees of pipelining.
how many addressing modes are enough? programs naturally require a variety of memory-addressing modes. it isn't necessary to provide them in hardware, however, if a compiler can synthesize them from a few primitive modes. this not only simplifies the hardware, but also permits the compiler to use its understanding of the program to economize on the modes which it uses. we present some compilation techniques that allow the compiler to deal effectively with a single addressing mode in a target risc processor. we also give measurements to show the benefits of such techniques, and to support our assertion that a single addressing mode is adequate for a general purpose processor, provided that mode incorporates both a pointer and an offset.
energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with zebranet. over the past decade, mobile computing and wireless communication have become increasingly important drivers of many new computing applications. the field of wireless sensor networks particularly focuses on applications involving autonomous use of compute, sensing, and wireless communication devices for both scientific and commercial purposes. this paper examines the research decisions and design tradeoffs that arise when applying wireless peer-to-peer networking techniques in a mobile sensor network designed to support wildlife tracking for biology research.the zebranet system includes custom tracking collars (nodes) carried by animals under study across a large, wild area; the collars operate as a peer-to-peer network to deliver logged data back to researchers. the collars include global positioning system (gps), flash memory, wireless transceivers, and a small cpu; essentially each node is a small, wireless computing device. since there is no cellular service or broadcast communication covering the region where animals are studied, ad hoc, peer-to-peer routing is needed. although numerous ad hoc protocols exist, additional challenges arise because the researchers themselves are mobile and thus there is no fixed base station towards which to aim data. overall, our goal is to use the least energy, storage, and other resources necessary to maintain a reliable system with a very high `data homing' success rate. we plan to deploy a 30-node zebranet system at the mpala research centre in central kenya. more broadly, we believe that the domain-centric protocols and energy tradeoffs presented here for zebranet will have general applicability in other wireless and sensor applications.
accelerating multi-media processing by implementing memoing in multiplication and division units. this paper proposes a technique that enables performing multi-cycle (multiplication, division, square-root &hellip;) computations in a single cycle. the technique is based on the notion of memoing: saving the input and output of previous calculations and using the output if the input is encountered again. this technique is especially suitable for multi-media (mm) processing. in mm applications the local entropy of the data tends to be low which results in repeated operations on the same datum.the inputs and outputs of assembly level operations are stored in cache-like lookup tables and accessed in parallel to the conventional computation. a successful lookup gives the result of a multi-cycle computation in a single cycle, and a failed lookup doesn't necessitate a penalty in computation time.results of simulations have shown that on the average, for a modestly sized memo-table, about 40% of the floating point multiplications and 50% of the floating point divisions, in multi-media applications, can be avoided by using the values within the memo-table, leading to an average computational speedup of more than 20%.
heart: an operating system nucleus machine implemented by firmware. this paper discusses the role of microprogramming in operating system design and shows several things: (1) advantages of the efficiency which may be gained from microcoded operating system primitives, (2) selecting the most appropriste primitives for implementation, and (3) an analysis of the tradeoffs among software, firmware, and hardware. the authors propose a practical approach of enhancing computer architecture level, from a view point of functional hierarchy of operating systems. in order to prove the advantages of this approach, we have designed and implemented an experimental abstract machine for an operating system nucleus. this research is an experimental design, and evaluation on its operating system nucleus machine,called heart. heart is a set of primitive and universal functions, and works as a nucleus of a multiprogrammed operating system. the research results of our approach are the followings: first, to clarify the properties of operating system nucleus, taking functional hierarchy of operating system into consideration. second, to show the design of operating system nucleus based on novel concepts. third, to confirm the possibility of implimenting operating system nucleus machine. finally, we give a performance evaluation on microcoded heart and the effectiveness of enhancing computer architecture level based on the properties of operating systems.
pipelining and performance in the vax 8800 processor. the vax 8800 family (models 8800, 8700, 8550), currently the fastest computers in the vax product line, achieve their speed through a combination of fast cycle time and deep pipelining. rather than pipeline highly variable vax instructions as such, the 8800 design pipelines uniform microinstructions whose addresses are generated by instruction unit hardware. this design approach helps achieve a fast cycle time, which is the prime determinan of performance. some preliminary measurements of cycles per average instruction are reported.