waashk/dblp huggingface dataset:
a more reliable reduction algorithm for behavioral model extraction. in this paper we are concerned with developing more reliable model reduction algorithms. we have focused on less common, but real, examples that fail to be effectively reduced by almost all of the currently popular model reduction methods. the failure of these popular methods is due to the fact that they all separately examine controllability and observability. we then present a new method based on several modifications and extensions of the recently developed aisiad algorithm. the modified aisaid method is demonstrated on a wide variety of examples, including electrical interconnect, micromachined devices, and heat flow to show that the method is reliable. our modified aisaid method is either nearly equivalent or far superior to any of the other reduction methods suitable for large scale problems.
on mask layout partitioning for electron projection lithography. electron projection lithography (epl) is a leading candidate for next generation lithography (ngl) in vlsi production. the membrane mask used in epl is divided into sub-fields by struts for structural support. a layout must be partitioned into these sub-fields on mask and then stitched back together by the epl tool on wafer. to minimize possible stitching errors, partitioning of a mask layout should minimize cuts of layout features in the overlapping area between two adjacent sub-fields. this paper presents the first formulation of the mask layout partitioning problem for epl as a graph problem. the graph formulation is optimally solved with a shortest path approach. two other techniques are also presented to speed up computation. experimental runs on data from a real industry design show excellent results.
a video driver system designed using a top-down, constraint-driven methodology. to accelerate the design cycle for analog and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. the key idea of the proposed methodology is hierarchically propagating constraints from performance specifications to layout. consequently, it is essential to provide the necessary tools and techniques enabling the efficient constraint propagation. to illustrate the applicability of the proposed methodology to the design of larger systems, we present in this paper the complete design flow for a video driver system. critical advantages of the methodology illustrated with this design example include avoiding costly low level re-designs and getting working silicon parts from the first run. following our approach, a jitter constraint is imposed at the system level and then is propagated hierarchically to the circuit blocks and layout, using behavioral modeling and simulation. experimental results are presented from working fabricated parts.
damocles: an observer-based approach to design tracking. the first phase of damocles, which involves developing a data management system subset of an entire design tracking system using the observer approach, is described. the designer is provided with a cockpit data management view of the project, without changing the way in which design groups do data management. the observer approach creates a cockpit view for the designer without changing the current point-task view. the cockpit view presents a designer with a design state perspective consisting of an object-oriented view of design data, tool flow and methodology information, history and audit trail information, etc. the designer can use the cockpit view to get the larger picture about project progress as and when the designer chooses. this view is extracted from the traditional designer environment by damocles while the designer is working through the point-task view
power analysis of embedded software: a first step towards software power minimization. embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. power constraints are increasingly becoming the critical component of the design specification of these systems. at present, however, power analysis tools can only be applied at the lower levels of the design&mdash;the circuit or gate level. it is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. this paper describes the first systematic attempt to model this power cost. a power analysis technique is developed that has been applied to two commercial microprocessors&mdash;intel 486dx2 and fujitsu sparclite 934. this technique can be employed to evaluate the power cost of embedded software and also be used to search the design space in software power optimization.
efficient iterative time preconditioners for harmonic balance rf circuit simulation. efficient iterative time preconditioners for krylov-basedharmonic balance circuit simulators are proposed.some numerical experiments assess theirperformance relative to the well-known block-diagonalfrequency preconditioner and the previouslyproposed time preconditioners.
a simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. technology mapping algorithms for lut (look up table) based fpgas have been proposed to transfer a boolean network into logic-blocks. however, since those algorithms take no layout information into account, they do not always lead to excellent results. in this paper, a simultaneous technology mapping, placement and global routing algorithm for fpgas, maple, is presented. mapleis an extended version of a simultaneous placement and global routing algorithm for fpgas, which is based on recursive partition of layout regions and block sets. maple inherits its basic processes and executes the technology mapping simultaneously in each recursive process. therefore, the mapping can be done with the placement and global routing information. experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.
adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. many approaches to analog performance parameter macro modeling have been investigated by the research community. these models are typically derived from discrete data obtained from circuit simulation using numerous input combinations of component sizes for a given circuit topology. the simulations are computationally intensive, therefore it is advantageous to reduce the number of simulations necessary to build an accurate macro model. we present a new algorithm for adaptively sampling multi-dimensional black box functions based on duchon pseudo-cubic splines. the splines readily and accurately model high dimensional functions based on discrete unstructured data and require no tuning of parameters as seen in many other interpolation methods. the adaptive sampler, in conjunction with pseudo-cubic splines, is used to accurately model various analog performance parameters for an operational amplifier topology using fewer sample points than traditional gridded and quasi-random sampling methodologies.
a deductive technique for diagnosis of bridging faults. a deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. for defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-and/or behavior. a path-trace procedure starting from failing outputs deduces potential lines associated with the bridge and eliminates certain faults. the information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. the intersection graph implicitly represents all candidate faults, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. the above procedures are performed dynamically and a reduced intersection graph is maintained to reduce memory and simulation time. no dictionary or fault simulation is required. results are provided for all large iscas89 benchmark circuits. for the largest benchmark circuit, the procedure reduces the space of all bridging faults, which is of the order of 10^9 to a few hundred faults on the average in about 30 seconds of execution time.
practical techniques to reduce skew and its variations in buffered clock networks. clock skew is becoming increasingly difficult to control due to variations. link based non-tree clock distribution is a cost-effective technique for reducing clock skew variations. however, previous works based on this technique were limited to unbuffered clock networks and neglected spatial correlations in the experimental validation. in this work, we overcome these shortcomings and make the link based non-tree approach feasible for realistic designs. the short circuit risk and multi-driver delay issues in buffered non-tree clock networks are investigated. our approach is validated with spice based monte carlo simulations, considering spatial correlations among variations. the experimental results show that our approach can reduce the maximal skew by 47%, improve the skew yield from 15% to 73% on average with a decrease on the total wire and buffer capacitance.
subtract: a program for the efficient evaluation of substrate parasitics in integrated circuits. algorithms for the efficient evaluation of substrate parasitics in mixed-signal integrated circuits have been developed and incorporated in an extraction tool for substrate parasitics, subtract. using a preprocessed, polynomial- based boundary element method, subtract enables the parasitic extraction process to be completely technology independent, allowing for fast evaluation. additionally, techniques to accelerate the iterative solution of the resulting impedance matrix have been developed and employed to further improve the speed advantages that this method offers. the preprocessed boundary element method is more efficient than finite-difference schemes and orders of magnitude faster than general boundary element methods using a direct evaluation of green's function. results of employing subtract to the design and verification of a mixed-signal a/d converter ic are described.
logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. this paper presents new logic synthesis techniques for generating multilevel circuits with concurrent error detection based on a parity-check code scheme that can detect all errors caused by single stuck-at faults. these synthesis techniques fully automate the design process and allow for a better quality result than previous methods thereby reducing the cost of concurrent error detection. an algorithm is described for selecting a good parity-check code for encoding the outputs of a circuit. once the code has been chosen, a new procedure called structure-constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. the implementation that is generated is path fault secure and when augmented by a checker forms a self-checking circuit. results indicate that self-checking multilevel circuits can be generated which require significantly less area than using duplication.
ust/dme: a clock tree router for general skew constraints. in this paper, we propose new approaches for solving the useful-skew tree (ust) routing problem [17]: clock routing subject to general skew constraints. the clock layout synthesis engine of our ust algorithms is based on the deferred-merge embedding (dme) paradigm for zero-skew tree [5; 1] and bounded-skew tree [8; 2] routings; hence, the names ust/dme and greedy-ust/dme for our algorithms. they simultaneously perform skew scheduling and tree routing such that each local skew range is incrementally refined to a skew value that minimizes the wirelength during the bottom-up merging phase of dme. the resulting skew schedule is not only feasible, but is also best for routing in terms of wirelength. the experimental results show very encouraging improvement over the previous bst/dme algorithm on three iscas89 benchmarks under general skew constraints in terms of total wirelength.
jitter-tolerant clock routing in two-phase synchronous systems. due to process, manufacturing and system operating conditions in a real environment, clock jitter is inevitable. in the presence of jitter, zero or near-zero skew are not really safe for reliable clock operations. appropriate skew or useful skew can serve as a safety margin to guard against clock jitter. in two-phase clocking, the nonoverlapping interval of two-phase clocks provides an additional degree of freedom to improve either the clock tree cost or jitter-tolerance. we construct a two-phase jitter-tolerant useful-skew tree (jt-ust) such that the susceptibility to clock jitter and the clock tree cost is minimized. following the deferred-merge embedding (dme) framework, we use a simulated annealing approach to explore the routing topologies and embeddings. experimental results have shown 63% to 100% reduction of jitter-prone sink pairs over previous clock routing methods while having very comparable clock tree costs.
physics-based compact modeling for nonclassical cmos. physics-based compact modeling, as opposed to the conventional empirical approach, is emphasized for nanoscale nonclassical cmos. ufdg, a physics-based compact model for generic double-gate mosfets with ultra-thin bodies, is overviewed, and its applications to double- and (multiple) independent-gate finfet device and circuit design are demonstrated.
efficiency improvements for force-directed scheduling. force-directed scheduling is a technique which schedules operations under time constraints in order to achieve schedules with a minimum number of resources. the worst case time complexity of the algorithm is cubic in the number of operations. this is due to the computation of the changes in the distribution functions needed for the force calculations. an incremental way to compute the changes in the distribution functions, based on gradual time-frame reduction, is presented. this reduces the time complexity of the algorithm to quadratic in the number of operations, without any loss in effectiveness or generality of the algorithm. implementations show a substantial cpu-time reduction of force-directed scheduling, which is illustrated by means of some industrially relevant examples
predicting the performance of synchronous discrete event simulation systems. in this paper we propose a model to predict the performance of synchronous discrete event simulation. the model considers parameters including the number of active objects per cycle, event execution granularity and communication cost. we derive a single formula that predicts the performance of synchronous simulation.we have benchmarked several vhdl circuits on sgi origin 2000. the benchmark results show that the prediction model explains more than 90% of parallel simulation execution time. we also measure the effect of computation granularity over performance. the benchmark results show that although higher granularity can have better speedup because of dominance of computation over communication, the computational granularity cannot overshadow the inherent synchronization cost. this model can be used to predict the speed-up expected for synchronous simulation, and to decide whether it is worthwhile to use synchronous simulation before actually implementing it.
relaxation-based harmonic balance technique for semiconductor device simulation. harmonic and intermodulation distortion effects play an important role in numerous analog applications, particularly in such areas as wireless communication systems. in this paper, we present a two-dimensional harmonic balance semiconductor device simulator which accurately models these nonlinear effects at the physical (drift-diffusion) level. the simulator is based on stanford university's pisces code, and supports the full range of physical models and features present in the time-domain version of the program. a modified block gauss-seidel-newton nonlinear relaxation scheme is developed to efficiently handle the extremely large size of two-dimensional harmonic balance semiconductor device simulation problems.
a yield improvement methodology using pre- and post-silicon statistical clock scheduling. in deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. in this paper, we propose a comprehensive clock scheduling methodology that improves timing and yield through both pre-silicon clock scheduling and post-silicon clock tuning. first, an optimal clock scheduling algorithm has been developed to allocate the slack for each path according to its timing uncertainty. to balance the skew that can be caused by process variations, programmable delay elements are inserted at the clock inputs of a small set of flip-flops on the timing critical paths. a delay-fault testing scheme combined with linear programming is used to identify and eliminate timing violations in the manufactured chips. experimental results show that our methodology achieves substantial yield improvement over a traditional clock scheduling algorithm in many of the iscas89 benchmark circuits, and obtain an average yield improvement of 13.6%.
a search-based bump-and-refit approach to incremental routing for eco applications in fpgas. incremental physical cad is encountered frequently in the so-called engineering change order (eco) process in which design changes are made typically late in the design process in order to correct logical and/or technological problems in the circuit. as far as routing is concerned, in order to capitalize on the enormous resources and time already spent on routing the circuit, and to meet time-to-market requirements, it is desirable to re-route only the eco-affected portion of the circuit, while minimizing any routing changes in the much larger unaffected part of the circuit. incremental re-routing also needs to be fast and to effectively use available routing resources. in this paper, we develop a complete incremental routing methodology for fpgas using a novel approach called bump and refit (b&r); b&r was initially proposed in [4] in the much simpler context of extending some nets by a segment (for the purpose of fault tolerance) for fpgas with simple i-to-i switchboxes. here we significantly extend this concept to global and detailed incremental routing for fpgas with complex switchboxes such as those in lucent's orca and xilinx's virtex series. we also introduce new concepts such as b&r cost estimation during global routing, and determination of the optimal subnet set to bump for each bumped net, which we obtain using an efficient dynamic programming formulation. the basic b&r idea in our algorithms is to re-arrange some portions of some existing nets on other tracks within their current channels to find valid routings for the incrementally changed circuit without requiring any extra routing resources (i.e., completely unused tracks), and with little effect on the electrical properties of existing nets.we have developed optimal and near-optimal algorithms (called subsec_b&r and subnet_b&r, respectively) to find incremental routing solutions using the b&r paradigm in complex fpgas. we implemented these algorithms for lucent's orca-2c fpga, and compared our algorithms to two recent incremental routing techniques, standard and rip-up&reroute, and to lucent's a_par routing tool. experimental results show that our incremental routers perform very well for eco applications. firstly, b&r is 10 to 20 times faster than complete re-routing using a_par. further, the b&r incremental routers are nearly 27% faster and the new nets have nearly 10% smaller lengths than in previous incremental techniques. also, the b&r routers do not change either the lengths or topologies of existing nets, a significant advantage in eco applications, in contrast to rip-up&reroute which increases the length of ripped up nets by an average of 8.75% to 13.6%.
weighted control scheduling. this paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. such a weighted metric is crucial for control dependent scheduling to accommodate practical architectural goals. in contrast to most weighting mechanisms, a nonbayesian probabilistic measure is used to avoid assumptions of branch independence. the underlying scheduling model allows general fsm-based models for operations, captures several forms of speculative execution and scales well with increasing control complexity.
improved use of the carry-save representation for the synthesis of complex arithmetic circuits. the increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimisations. the goal is to achieve automatically the handcrafted results which escape classic logic optimisations. some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - especially in arithmetic computations which are originally described at the bit level in high-level languages such as c. we therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized in high-quality arithmetic circuits, close, to those that an expert designer would conceive. on typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. in many cases, our algorithm also manages to reduce the cell area by up to 10-20%.
bus encoding to prevent crosstalk delay. the propagation delay across long on-chip buses is increasingly becoming a limiting factor in high-speed designs. crosstalk between adjacent wires on the bus may create a significant portion of this delay. placing a shield wire between each signal wire alleviates the crosstalk problem but doubles the area used by the bus, an unacceptable consequence when the bus is routed using scarce top-level metal resources. instead, we propose to employ data encoding to eliminate crosstalk delay within a bus. this paper presents a rigorous analysis of the theory behind "self-shielding codes", and gives the fundamental theoretical limits on the performance of codes with and without memory. specifically, we find that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding.
hierarchical timing analysis using conditional delays. we present a novel method to perform timing analysis of hierarchical circuits. it is based on the representation of circuit modules by conditional delay matrices (cdms) which combine module delays with event propagation conditions. the cdm model is independent of module complexity and allows automatic identification of false paths. we exploit hierarchy information to perform efficient delay computation. the effectiveness of the method is demonstrated on a high-level model of the iscas-85 circuit c6288, which is difficult to analyze using traditional approaches. the method has been implemented in a symbolic timing analysis program called cat. the application of cat to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.