waashk/dblp huggingface dataset:
power-switch routing for coarse-grain mtcmos technologies. multi-threshold cmos (mtcmos) is an effective power-gating technique to reduce ic's leakage power consumption by turning off idle devices with mtcmos switches. however, few existing literatures have discussed the algorithms required in mtcmos's back-end tools. in this paper, we propose a switch-routing framework which serially connects the mtcmos switches without violating the manhattan-distance constraint. the proposed switch-routing framework can simultaneously maximize the number of mtcmos switches covered by its trunk path and minimize the total path length. the experimental result based on four industrial mtcmos designs demonstrates the effectiveness and efficiency of the proposed framework compared to a solution provided by an eda vendor and an advanced tsp solver.
parallel multi-level analytical global placement on graphics processing units. gpu platforms are becoming increasingly attractive for implementing accelerators because they feature a larger number of cores with improved programmability. in this paper, we describe our implementation of a state-of-the-art academic multi-level analytical placer mpl [8] on nvidia's massively parallel gt200 series platforms. we detail our efforts on performance tuning and optimizations. when compared to software implementation on intel's recent generation xeon cpu, the speed of the global placement part of mpl is 15x faster on average using a tesla c1060 card, with comparable wl. (less than 1% wl degradation on average)
on soft error rate analysis of scaled cmos designs - a statistical perspective. this paper re-examines the soft error effect caused by cosmic radiation in sub 90nm technologies. considering the impact of process variation, a number of statistical natures of transient faults are found more sophisticated than their static ones. we apply the state-of-the-art statistical learning algorithm to tackle the complexity of these natures and build compact yet accurate generation and propagation models for transient fault distributions. a statistical analysis framework for soft error rate (ser) is also proposed on the basis of these models. experimental results show that the proposed framework can obtain improved ser estimation compared to the static approaches.
consistency-based characterization for ic trojan detection. a trojan attack maliciously modifies, alters, or embeds unplanned components inside the exploited chips. given the original chip specifications, and process and simulation models, the goal of trojan detection is to identify the malicious components. this paper introduces a new trojan detection method based on nonintrusive external ic quiescent current measurements. we define a new metric called consistency. based on the consistency metric and properties of the objective function, we present a robust estimation method that estimates the gate properties while simultaneously detecting the trojans. experimental evaluations on standard benchmark designs show the validity of the metric, and demonstrate the effectiveness of the new trojan detection.
deltasyn: an efficient logic difference optimizer for eco synthesis. during the ic design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. however, designers are left either to manually process such modifications by hand or to restart the design process from scratch---a very costly option. in order to address this issue, we present deltasyn, a method for generating a highly optimized logic difference between a modified high-level specification and an implemented design. deltasyn has the ability to locate boundaries in implemented logic within which changes can be confined. deltasyn demarcates the boundary in two phases. the first phase employs fast functional and structural analysis techniques to identify equivalent signals forming the input-side boundary of the changes. the second phase locates the outputside boundary of the changes through a novel dynamic algorithm that detects matching logic downstream from the changes required by the eco. experiments on industrial designs show that together these techniques successfully implement ecos while preserving an average of 97% of the existing logic. unlike previous approaches, the use of bitparallel logic simulation and fast sat solvers enables high performance and scalability. deltasyn can process and verify a typical eco for a design of around 10k gates in about 200 seconds or less.
an elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. we propose a new and efficient statistical-simulation-based test methodology for optimally selecting repair elements at beginning-of-life (bol) to improve the end-of-life (eol) functionality of memory designs. this is achieved by identifying the best bol test/repair corner that maximizes eol yield, thereby exploiting redundancy to optimize eol operability with minimal bol yield loss. the statistical approach makes it possible to identify such corners with tremendous savings in terms of test time and hardware. to estimate yields and search for the best repair corner the approach relies on fast conditional importance sampling statistical simulations. the methodology is versatile and can handle complex aging effects with asymmetrical distributions. results are demonstrated on state-of-the-art dual-supply memory designs subject to statistical negative bias temperature instability (nbti) effects, and hardware results are shown to match predicted model trends.
fast and reliable passivity assessment and enforcement with extended hamiltonian pencil. passivity is an important property for a macro-model generated from measured or simulated data. existence of purely imaginary eigenvalues of a hamiltonian matrix provides useful information in assessing and correcting the passivity of a system. since direct computation of eigenvalues is very expensive for large-scale systems, several authors have proposed to solve iteratively for a subset of the eigenvalues based on heuristic sampling along the imaginary axis. however, completeness is not guaranteed in such methods and thus potential risk of missing important eigenvalues is difficult to avoid. in this paper we are aiming at finding all eigenvalues efficiently to avoid both the high cost and the potential risk of missing important eigenvalues. the idea of the proposed method is to convert the hamiltonian matrix to an equivalent sparse form, termed the "extended hamiltonian pencil", and solve for its eigenvalues efficiently using a special eigensolver. experiments on several realistic systems demonstrate an 80x speed-up compared with standard direct eigensolvers.
timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. double patterning lithography (dpl) is a likely resolution enhancement technique for ic production in 32nm and below technology nodes. however, dpl gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation. in this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using dpl. our first contribution is a dpl-aware approach to timing modeling, based on detailed analysis of cell layouts. our second contribution is an ilp-based maximization of 'alternate' mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure "double patterning correctness" after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable eco impact. with a 45nm library and open-source design testcases, our timing-aware recoloring and placement optimizations together achieve up to 232ps (resp. 36.22ns) reduction in worst (resp. total) negative slack, and 78% (resp. 65%) reduction in worst (resp. total) negative slack variation.
post-fabrication measurement-driven oxide breakdown reliability prediction and management. oxide breakdown has become an increasingly pressing reliability issue in modern vlsi design with ultra-thin oxides. the conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. in this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. the estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second.
bist design optimization for large-scale embedded memory cores. built-in self test (bist) is a crucial technique for testing embedded memory cores in a system-on-chip (soc). however, there is not much published work on bist design optimization for multiple memory cores in the soc designs. in this paper, we present a method for the bist design optimization problem for large-scale soc embedded memory cores, considering various real-world constraints such as peak current, ir drop, etc. our method is based on a three-stage technique: (1) assignment, (2) legalization, and (3) refinement. the first stage adopts an integer linear programming (ilp) formulation for each memory partition to find a desired assignment of memory cores to controllers. the second stage then legalizes the assignment to meet user-specified assignment constraints. the last stage refines the solution to further reduce its cost. experimental results show that our method can reduce the test time by 26.6%, the routing length by 8.9%, and the area by 24.1%, compared with a heuristic method currently used in industry.
quantifying robustness metrics in parameterized static timing analysis. process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. in the past few years, while much research has been aimed at handling parameter variations as part of timing analysis, few proposals have actually included ways to interpret the results of this parameterized static timing analysis (psta) step. in this paper, we propose a new post-variational analysis metric that can be used to quantify the (timing) robustness of designs to parameter variations. in addition to helping designers diagnose if and when different nodes can fail, this metric can guide optimization and can give insights on what to fix, by identifying nodes with small robustness values and proceeding to fix those nodes first. inspired by the rich literature on design centering, tolerancing, and tuning (dctt), we use distance as a measure for robustness. our analysis thus determines the minimum distance from the nominal point in the parameter space to any timing violation, and works under the assumption that parameters are specified as ranges rather than statistical distributions. we demonstrate the usefulness of this distance-based robustness metric on circuit blocks extracted from a commercial 45nm microprocessor.
crop: fast and effective congestion refinement of placement. modern circuits become harder to route with the ever decreasing design features. previous routability-driven placement techniques are usually tightly coupled with the underlying placers. so usually they cannot be easily integrated into various placement tools. in this paper, we propose a tool called crop (congestion refinement of placement) for mixed-size placement solutions. crop is independent of any placer. it takes a legalized placement solution and then relocates the modules to improve routability without significantly disturbing the original placement solution. crop interleaves a congestion-driven module shifting technique and a congestion-driven detailed placement technique. basically the shifting technique targets at better allocating the routing resources. shifting in each direction can be formulated as a linear program (lp) for resizing each g-cell. instead of solving the computationally expensive lp, we discover that the lp formulation could be relaxed and solved by a very efficient longest-path computation. then the congestion-driven detailed placement technique is proposed to better distribute the routing demands. congestion reduction is realized by weighting the hpwl with congestion coefficient during detailed placement. the experimental results show that crop is capable of effectively alleviating the congestion for unroutable placement solutions. we apply it to placement solutions generated by four different placers on the ispd05/06 placement benchmarks [1][2]. within a very short runtime, crop greatly improves the routability and saves execution time for the routing stage after refinement.
a circuit-software co-design approach for improving edp in reconfigurable frameworks. use of two-dimensional memory array for lookup table (lut) based reconfigurable computing frameworks has been proposed earlier for improvement in performance and energy-delay product (edp). in this paper, we propose an integrated solution for achieving significantly higher edp in these frameworks by leveraging on the read-dominant memory access pattern. first, we propose to employ an asymmetric memory cell design, which provides higher read performance (~2x) and lower read power (~1.6x) in order to improve the overall edp during operation. exploiting the fact that the proposed memory cell provides better read power/performance for cells storing logic '0', next we propose a content-aware application mapping approach, which tries to maximize the logic '0' content in the luts. we show that the joint circuit and application mapping level optimization approach provides significant improvement in system edp for a set of benchmark circuits.
pcramsim: system-level performance, energy, and area modeling for phase-change ram. phase-change random access memory (pcram) is an emerging memory technology with attractive features, such as fast read access, high density, and non-volatility. because of these attractive properties, pcram is regarded as a promising candidate for future universal memories, and system-level designers could open up new design opportunities by leveraging this new memory technology. however, the majority of the pcram research has been at the device level, and system-level design space exploration using pcram is still in its infancy due to the lack of high-level modeling tools for pcram-based caches and memories. in this paper, we present a pcram model, called pcramsim, to bridge the gap between the device-level and system-level research on pcram technology. the model is validated against industrial pcram prototypes. this new pcramsim tool is expected to help boost pcram-related studies such as next-generation memory subsystems.
moles: malicious off-chip leakage enabled by side-channels. economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. this trend leads to potential vulnerabilities from untrusted circuit foundries to covertly implant malicious hardware trojans into a genuine design. hardware trojans provide back doors for on-chip manipulation, or leak secret information off-chip once the compromised ic is deployed in the field. this paper explores the design space of hardware trojans and proposes a novel technique, "malicious off-chip leakage enabled by side-channels" (moles), which employs power side-channels to convey secret information off-chip. an experimental moles circuit is designed with fewer than 50 gates and is embedded into an advanced encryption standard (aes) cryptographic circuit in a predictive 45nm cmos technology model. engineered by a spread-spectrum technique, the moles technique is capable of leaking multi-bit information below the noise power level of the host ic to evade evaluators' detections. in addition, a generalized methodology for a class of moles circuits and design verification by statistical correlation analysis are presented. the goal of this work is to demonstrate the potential threats of moles on embedded system security. nevertheless, moles could be constructively used for hardware authentication, fingerprinting and ip protection.
variability analysis of finfet-based devices and circuits considering electrical confinement and width quantization. finfet is considered as the most likely candidate to substitute bulk cmos technology. finfet-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect) even in subthreshold regime. considering these exclusive properties of finfets, the sources of process variations and their effects on finfet-based circuit characteristics can be significantly different from that in bulk cmos devices. this paper identifies a new source of random process variation due to the gate work-function variation and resulting electrical confinement in emerging high-k/metal-gate finfet devices. in order to capture the effect of the variations on the characteristics of multifin finfets (considering their width quantization property), this paper also presents a new statistical framework to accurately predict the effective threshold voltage of multifin finfet devices. this framework is subsequently used to predict the leakage profile of finfet-based sram cells. since finfets are optimal for ultra-low-voltage operations due to near-ideal subthreshold swing (60 mv/dec), we focus on finfet-based sram (including subthreshold sram) design. contrary to the low sensitivity of the static noise margin (snm) to the width of the pull-down devices in bulk-cmos subthreshold srams, our analysis shows, for the first time, the significant impact of employing multifin pull-down devices on the snm of subthreshold finfet srams.
virtual probe: a statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. in this paper, we propose a new technique, referred to as virtual probe (vp), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process. vp exploits recent breakthroughs in compressed sensing [15]--[17] to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. by exploring the underlying sparse structure in (spatial) frequency domain, vp achieves substantially lower sampling frequency than the well-known (spatial) nyquist rate. in addition, vp is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. our industrial measurement data demonstrate that by testing the delay of just 50 chips on a wafer, vp accurately predicts the delay of the other 219 chips on the same wafer. in this example, vp reduces the estimation error by up to 10x compared to other traditional methods.
pre-atpg path selection for near optimal post-atpg process space coverage. path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. to guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. existing coverage-based path selection techniques, however, suffer from the loss of coverage after atpg (automatic test pattern generation), i.e., although the pre-atpg path selection achieves good coverage, after atpg, the coverage can be severely reduced as many paths turn out to be unsensitizable. this paper presents a novel path selection algorithm that, without running atpg, selects a set of n paths to achieve near optimal post-atpg coverage. details of the algorithm and its optimality conditions are discussed. experimental results show that, compared to the state-of-the-art, the proposed algorithm achieves not only superior post-atpg coverage, but also significant runtime speedup.
multi-functional interconnect co-optimization for fast and reliable 3d stacked ics. heat removal and power delivery have become two major reliability concerns in 3d stacked ic technology. for thermal problem, two possible solutions exist: thermal-through-silicon-vias (t-tsvs) and micro-fluidic channel (mfc) based liquid cooling. in case of power delivery, a highly complex power distribution network is required to deliver currents reliably to all parts of the 3d stacked ic while suppressing the power supply noise to an acceptable level. however, these thermal and power networks pose major challenges in signal routability and congestion. this is because the signal, power, and thermal interconnects are all competing for routing space. in this paper, we present a co-optimization methodology for the signal, power, and thermal interconnects for 3d stacked ics based on design of experiments (doe) and response surface method (rsm). the goal is to improve performance, thermal, noise, and congestion metrics with our holistic approach. we also provide in-depth comparison between t-tsv and mfc based cooling method and discuss how to employ doe and rsm to best co-optimize the multi-functional interconnects simultaneously.
task management in mpsocs: an asip approach. scheduling, mapping and synchronization have an essential impact on the performance of multi-processor system-on-chips (mpsocs), especially in heterogeneous systems with many cores and small tasks. this paper presents a technique to efficiently accelerate these operations. key contribution is an application-specific instruction-set processor (asip) called osip which is especially tailored to achieve this. in contrast to pure hw solutions, osip is programmable and hence features higher flexibility and better scalability. osip comes with a compiler and a firmware that ease its usability, and an abstract formal model that allows analytical evaluation and integration into fast system level simulators. together with osip, a thin software layer is proposed that leverages high level multi-task programming by abstracting osip's low level details away. in an extensive case study based on a synthetic benchmark and a benchmark from the multimedia domain (h.264), osip highlights its potential when compared against a standard risc and an arm926-ejs processor.