waashk/dblp huggingface dataset:
simulation-based techniques for dynamic test sequence compaction. simulation-based techniques for dynamic compaction of test sequences are proposed. the first technique uses a fault simulator to remove test vectors from the partially-specified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. the second technique uses genetic algorithms to fill the unspecified bits in the partially-specified test sequence in order to increase the number of faults detected by the sequence. significant reductions in test set sizes were observed for all benchmark circuits studied. fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computation-intensive deterministic test generator.
performance-driven read-after-write dependencies softening in high-level synthesis. conventional scheduling algorithms usually produce schedules whose cycle lengths are influenced by the operations latency. operations are assigned to one or several consecutive cycles (multicycle operators) and one operation cannot begin until all its predecessors have finished, except for operations chaining. this technique allows the execution in the same cycle of several data-dependent operations, being some bits of the chained operations calculated in parallel. chaining one operation to its predecessor requires the completion of both in the selected cycle. this paper presents a less restrictive technique based on the softening of the read-after-write dependencies among operations, which allows beginning the execution of one operation before the calculus of its predecessors has been completed. this becomes feasible when the execution of the predecessor has begun in the selected cycle or in a previous one, and even if it finishes in a posterior cycle. this design technique is applied before synthesis to transform behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance.
iterative [simulation-based genetics + deterministic techniques]= complete atpg0. simulation-based test vector generators require much less computer time than deterministic atpg but they generate longer test sequences and sometimes achieve lower fault coverage. this is due to the divergence in the search process. in this paper, we propose a correction technique for simulation-based atpg. this technique is based on identifying the diverging state and on computing a fault cluster (faults close to each other). a set of candidate faults from the cluster is targeted with a deterministic atpg and the resulting test sequence is used to restart the search process of the simulation-based technique. this above process is repeated until all faults are detected or proven to be redundant/untestable. the program implementing this approach has been used to generate tests with very high fault coverage, and runs about 10 times faster than traditional deterministic techniques with very good test quality in terms of test length and fault coverage.
what is the cost of delay insensitivity? deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. asynchronous speed-independent (si) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. on the other hand, building circuits totally delay-insensitive (di), for both gates and wires, is impractical. the paper presents an approach for automated synthesis of globally di and locally si circuits. it is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which signal transition graph, an interpreted petri net, is used. the method is successfully tested on a set of benchmarks and a realistic design example. it proves effective showing average cost of di interfacing at about 40% for area and 20% for speed.
minimizing power across multiple technology and design levels. approaches to achieve low-power and high-speed vlsi's are described with the emphasis on techniques across multiple technology and design levels. to suppress the leakage current in a standby mode, boosted gate mos (bgmos) is effective, which is based on cooperation between technology level and circuit level. to reduce the power in an active mode, vdd-hopping and vth-hopping are promising, which are cooperative approaches between circuit and software. power consumed in interconnect system can be reduced by a cooperative approach between application and layout as in bus shuffling. other low-power design approaches are also discussed.
functional timing optimization. it is widely believed that any true (or sensitizable) critical path of length &ge; t must be sped up in order for a circuit to have a delay < t. in this paper i demonstrate that this notion is pessimistic. many true paths can never affect the delay of the circuit &mdash; whenever such a path propagates a signal, some other path that is at least as long also propagates a signal.the theory for a new classification of paths based on the impact on the circuit delay is presented and conditions are given under which a path (or a set of paths) must be sped up in order to improve the circuit delay. the conditions for the categorization are independent of the delays in the circuit and are valid for all delay assignments.this work indicates that the widely employed notions of true and false paths may be misleading both for timing optimization and delay analysis of logic circuits.
the impact of device parameter variations on the frequency and performance of vlsi chips. the distance-correlated (continuous) within-die (wid) process variations of transistor parameters appears to be approximately scaling with process generations. furthermore, shrinking clock cycles and the scaling of functional block dimensions in complex chips (e.g. cpus), cause a shortening of interconnect distances. these effects mitigate correlated variations' impact on delay changes across a die. temperature has a small effect, and supply distribution can be well-understood and designed. furthermore, uncorrelated (random) variations (e.g. rdf, & ler) currently have a small impact on speed-setting paths, and even multiplying their effect (as processes shrink), would not make them very significant. coupled with methods for estimating the shift in the maximum operating frequency (f/sub max/) of a die (due to variations), it is shown that variations will continue to have a small effect on product speeds through the mid-term future.
a scalable substrate noise coupling model for mixed-signal ics. a scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. this model is simple since it requires only four parameters which can readily be extracted from a small number of device simulations or measurements. once these parameters have been determined the model can be used for any spacing between the injection and sensing contacts and for different contact geometries. the scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. the model is validated for a 2&mgr;m and a 0.5&mgr;m cmos process where it is shown that the simple model predicts the noise coupling accurately. measurements from a chip fabricated in a 0.5&mgr;m cmos process show good agreement with the model.
power exploration for embedded vliw architectures. in this paper, we propose a system-level power exploration methodology for embedded vliw architectures based on an instruction-level analysis. the instruction-level energy model targets a general pipeline scalar processor; several architectural parameters such as number and type of pipeline stages as well as average stall/latency cycles per instruction and inter-instruction effects are taken into account. the application of the proposed model to vliw processors results intractable from the point of view of both spatial and temporal complexity (which grow exponentially w.r.t. the number of possible operations in the isa). to reduce this complexity, the basic model has been extended by assuming that the energy associated with a long instruction is given by the sum of the energy associated with the single operations of the long instruction and the single pipeline stages. the instruction-level energy model has been applied to a simplified vliw architecture to demonstrate the validity of the proposed approach.1
time-constrained loop pipelining. this paper addresses the problem of time-constrained loop pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. this paper proposes a methodology, called tclp, based on dividing the problem into two simpler and independent tasks: retiming and scheduling. tclp explores different sets of resources, searching for a maximum resource utilization. this reduces area requirements. after a minimum set of resources has been found, the execution throughput is increased and the number of registers required by the loop schedule is reduced. tclp attempts to generate a schedule which minimizes cost in time and area (resources and registers). the results show that tclp obtains optimal schedules in most cases.
optimizing computations in a transposed direct form realization of floating-point lti-fir systems. the inherent computational redundancy in discrete-time lti-fir system response computations in digital signal processing have been exploited in a variety of ways to minimize the computational complexity. we present an improved algorithm-level computational optimization that uses sorted recursive differences between coefficients representing the system transfer function with a floating-point number representation to extract maximum benefits from this redundancy. it can be applied to any lti-fir system and there is no deterioration in accuracy compared to directly using the coefficients. the results for several practical fir systems show that there is a significant reduction in the computational complexity, hence power consumed, using this technique.
power vs. delay in gate sizing: conflicting objectives? abstract: the problem of sizing gates for power-delay tradeoffs is of great interest to designers. in this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. the dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimum power circuit is not necessarily the minimum-sized circuit.
nrg: global and detailed placement. we present a new approach to the placement problem. the proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. after determination of the grid size, the placement is carried out in three steps: global placement, detailed placement and final optimization. we will show that the output of the global placement can also serve as a fast and accurate predictor. current implementation is based on simulated annealing. we have put all algorithms together in a placement package called nrg (pronounced n-er-g). in addition to area minimization, nrg can perform timing-driven placement. experimental results are strong. we improve timberwolf's results (version 1.2, the commercial version which is suppose to be better than all university versions including version 7) by about 5%. our predictor can estimate the wirelength within 10-20% accuracy offering 2-20x speedup compared with the actual placement algorithm.
a novel geometric algorithm for fast wire-optimized floorplanning. as the size and complexity of vlsi circuits increase, the needfor faster floorplanning algorithms also grows.in this work weintroduce traffic, a new method for creating wire- and area-optimizedfloorplans.through the use of connectivity groupling,simple geometry, and efficient data structures, traffic achieveshigher result quality than simulated annealing (sa) in afraction of the time.this speed allows designers to explore alarge circuit design space in a reasonable amount of time,rapidly evaluate small changes to big circuits, and quicklyproduce initial solutions for other floorplanning algorithms.
speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. abstract: an algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented. in the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. the procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.
simulated quenching: a new placement method for module generation. this paper addresses a placement method good for module generation. conventional partitioning based method can not guarantee the best quality in consecutive partitioning, even if it can find a sequence of the minimum partitioning of a circuit into two subcircuits. also, when size of cells varies very much, which is often seen in module generation as leaf cells, it is sometimes too strong constraint for them to get the minimum partitioning under ``partitioning into two similar size of subcircuits''. on the other hand, although conventional simulated annealing (sa) based method gives a better result, it requires extremely long computation time, since they do not employ any divide and conquer technique. it is the purpose of this paper to propose an algorithm which is based on sa method and employs the divide and conquer technique so that it gives better quality than partitioning based method and also it gives drastically faster computation time than sa method. as the first step, we applied this idea to the linear placement. our algorithm is based on sorting inside subgroups, and this subgroup generation is done by plural cut-lines with a constant pitch. this constant pitch will be decreased from sufficiently large value to small value gradually, and this decreasing schedule is similar to the cooling schedule of sa method. and also, since there is a variation of offset in applying cut-lines even with the same pitch value, we randomly select one of them like sa method chooses a pair of components to be switched at random. sorting inside subgroups is only a rearrangement depending on the connection between subgroups and is very fast. it is found that the total wiring length is improved about 10% compared to that of spectral method which was recognized to be the best (slpc2). also, computation time was dramatically reduced over the sa method.
logic synthesis for look-up table based fpgas using functional decomposition and support minimization. this paper presents a logic synthesis method for look-up table (lut) based field programmable gate arrays (fpgas). we determine functions to be mapped to luts by functional decomposition. we use not only disjunctive decomposition but also nondisjunctive decomposition. furthermore, we propose a new boolean resubstitution technique customized for an lut network synthesis. resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share the common function among two or more functions. the boolean resubstitution is effectively carried out by solving a support minimization problem for an incompletely specified function. we can also handle satisfiability don't cares of an lut network using the technique.
deadlock-free routing and component placement for irregular mesh-based networks-on-chip. routing is one of the most crucial key factors which decides over the success of noc architecture based systems or their failure. this paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2d-mesh based network-on-chip (noc) architecture including oversized ip cores. the paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. the last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.
towards support for design description languages in eda framework. we report on a new framework service for design tool encapsulation, based on an information model for design management. the new service uses generated language processors that perform import and export of design files to and from a design management database with the support of nested syntax specifications and extension language scripts. our prototype design environment is based on the nelsis cad framework and several tools from the synopsys high-level synthesis and simulation tool suite.
unit delay simulation with the inversion algorithm. the inversion algorithm is an event driven algorithm whose performance meets or exceeds that of levelized compiled code simulation, even when the activity rate is unrealistically high. existing implementations of the inversion algorithm are based on the zero delay model. this paper extends the algorithm to more realistic timing models. the main problems discussed in this paper are avoiding scheduling conflicts, and minimizing the amount of storage space. these problems are made considerably more difficult by the deletion of not gates and the collapsing of various connections. these optimizations transform the simulation into a multi-delay simulation under the transport delay model. a complete solution to the scheduling problem is presented under these conditions.
address generation for memories containing multiple arrays. this paper presents techniques for generating addresses for memories containing multiple arrays. because these techniques rely on the inversion or rearrangement of address bits, they are faster and require less hardware to compute than offset addition. use of these techniques can decrease effective access time to arrays and reduce address generation hardware. the primary drawback is that extra memory space is occasionally required by these techniques, but this extra memory space is on average only 4% and no worse than 25.2% of the utilized memory space. this amount of wasted address space is less than the amount required by similar techniques.
functional simulation using binary decision diagrams. in many verification techniques fast functional evaluation of a boolean network is needed. we investigate the idea of using binary decision diagrams (bdds) for functional simulation. the area-time trade-off that results from different minimization techniques of the bdd is discussed. we propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.
power-aware microsensor design. military microsensors are networked distributed embedded systems composed of a processor, a radio, and sensors used for personnel or vehicle detection. they are most often found in minefield replacement and perimeter security applications where size, weight, power, and cost requirements are quite challenging. in this paper, we discuss the different system design approaches used in microsensor systems and introduce a modular, scalable, power-aware microsensor architecture intended span the entire dynamic range required of these systems. we describe a reference implementation of this concept and results from field experiments.
theoretical and practical validation of combined bem/fem substrate resistance modeling. in mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. as such, accurately modeling the properties of the substrate as a noise-propagator is becoming ever more important. a model can be obtained through the finite element method (fem) or the boundary element method (bem). the fem performs a full 3d discretization of the substrate, which makes this method very accurate and flexible but also slow. the bem only discretizes the contact areas on the boundary of the substrate, which makes it less flexible, but significantly faster. a combination between bem and fem can be efficient when we need flexibility and speed at the same time. this paper briefly describes the bem and the fem and their combination, but mainly concentrates on the theoretical validation of the combined method and the experimental verification through implementation in the space layout to circuit extractor and comparison with commercial bem and fem tools.
embedded systems design for low energy consumption. this tutorial covers the circuit fundamentals of cmos circuits which contribute to the consumption of energy in portable products, as well as guidelines for the design of systems in order to reduce energy consumption and prolong battery life. circuit fundamentals will include a definition of terms, basic circuit elements, laws of operation, and basic circuit theory applying energy consumption. we will then present three major principles of energy reduction: reducing number of transitions, reducing the amount of switched capacitance, and reducing the operating voltage. several guidelines that can be applied during the system design process which utilize the three major principles.
on modeling top-down vlsi design. we present an improved data model that reflects the whole vlsi design process including bottom-up and top-down design phases. the kernel of the model is a static version concept that describes the convergence of a design. the design history which makes the semantics of most other version concepts, is modeled explicitly by additional object classes (entities types) but not by the version graph itself. top-down steps are modeled by splitting a design object into requirements and realizations. the composition hierarchy is expressed by a simple but powerful configuration method. design data of iterative refinement processes are managed efficiently by storing incremental data only.
lazy-expansion symbolic expression approximation in synap. a lazy-expansion technique for generating small approximate symbolic analog circuit analysis expressions is described. statistics for this technique as implemented in the symbolic analysis program synap are presented and show a two order-of-magnitude speed improvement (on larger circuits) as compared with traditional full-expansion techniques. this technique also allows larger circuits to be analyzed. methods used in synap for eliminating pole and zero movement at the design point and for handling variables representing device mismatches are also presented
test planning for the effective utilization of port-scalable testers for heterogeneous core-based socs. many socs contain embedded cores with different scan frequencies. to better meet the test requirements for such heterogeneous socs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. however the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bitwidth used to access it. we present a scalable test planning technique that exploits port scalability of testers to reduce soc test time. we compare the proposed heuristic optimization method to two baseline methods based on prior work that use a single scan data rate for all the embedded cores.