waashk/dblp huggingface dataset:
performance counters and state sharing annotations: a unified approach to thread locality. this paper describes a combined approach for improving thread locality that uses the bardware performance monitors of modem processors and program-centric code annotations to guide thread scheduling on smps. the approach relies on a shared state cache model to compute expected thread footprints in the cache on-line. the accuracy of the model has been analyzed by simmations involving a set of parallel applications. we demonstrate how the cache model can be used to implement several practical locality-based thread scheduling policies with little overhead. active threads, a portable, high-performance thread system, has been built and used to investigate the performance impact of locality scheduling for several applications.
thread scheduling for cache locality. this paper describes a method to improve the cache locality of sequential programs by scheduling fine-grained threads. the algorithm relies upon hints provided at the time of thread creation to determine a thread execution order likely to reduce cache misses. this technique may be particularly valuable when compiler-directed tiling is not feasible. experiments with several application programs, on two systems with different cache structures, show that our thread scheduling method can improve program performance by reducing second-level cache misses.
shasta: a low overhead, software-only approach for supporting fine-grain shared memory. this paper describes shasta, a system that supports a shared address space in software on clusters of computers with physically distributed memory. a unique aspect of shasta compared to most other software distributed shared memory systems is that shared data can be kept coherent at a fine granularity. in addition, the system allows the coherence granularity to vary across different shared data structures in a single application. shasta implements the shared address space by transparently rewriting the application executable to intercept loads and stores. for each shared load or store, the inserted code checks to see if the data is available locally and communicates with other processors if necessary. the system uses numerous techniques to reduce the run-time overhead of these checks. since shasta is implemented entirely in software, it also provides tremendous flexibility in supporting different types of cache coherence protocols. we have implemented an efficient cache coherence protocol that incorporates a number of optimizations, including support for multiple communication granularities and use of relaxed memory models. this system is fully functional and runs on a cluster of alpha workstations.the primary focus of this paper is to describe the techniques used in shasta to reduce the checking overhead for supporting fine granularity sharing in software. these techniques include careful layout of the shared address space, scheduling the checking code for efficient execution on modern processors, using a simple method that checks loads using only the value loaded, reducing the extra cache misses caused by the checking code, and combining the checks for multiple loads and stores. to characterize the effect of these techniques, we present detailed performance results for the splash-2 applications running on an alpha processor. without our optimizations, the checking overheads are excessively high, exceeding 100% for several applications. however, our techniques are effective in reducing these overheads to a range of 5% to 35% for almost all of the applications. we also describe our coherence protocol and present some preliminary results on the parallel performance of several applications running on our workstation cluster. our experience so far indicates that once the cost of checking memory accesses is reduced using our techniques, the shasta approach is an attractive software solution for supporting a shared address space with fine-grain access to data.
supporting ada memory management in the iapx-432. in this paper, we describe how the memory management mechanisms of the intel iapx-432 are used to implement the visibility rules of ada. at any point in the execution of an ada&reg; program on the 432, the program has a protected address space that corresponds exactly to the program's accessibility at the corresponding point in the program's source. this close match of architecture and language did not occur because the 432 was designed to execute ada&mdash;it was not. rather, both ada and the 432 are the result of very similar design goals. to illustrate this point, we compare, in their support for ada, the memory management mechanisms of the 432 to those of traditional computers. the most notable differences occur in heap-space management and multitasking. with respect to the former, we describe a degree of hardware/software cooperation that is not typical of other systems. in the latter area, we show how ada's view of sharing is the same as the 432, but differs totally from the sharing permitted by traditional systems. a description of these differences provide some insight into the problems of implementing an ada compiler for a traditional architecture.
consistency management for virtually indexed caches. a virtually indexed cache can improve performance by allowing cache lookup and address translation to occur in parallel, thus reducing processor cycle time. unlike physically indexed caches, virtually indexed caches create consistency problems because a physical address may be represented in more than one cache line when it has been accessed through more than one virtual address. write-back virtually indexed caches create additional inconsistencies because memory may become stale with respect to the cache. in this paper we examine the problem of consistency management for a virtually indexed write-back cache. we assume that the hardware does not support intra-cache consistency. we present a model and software implementation strategy for maintaining consistency with virtually indexed caches. we present measurements from an implementation of this model on the hp in the context of the mach operating system. our measurements show that a virtually indexed cache can be managed with nearly the same cost as that required to manage a physically indexed one, even when used by a virtual memory system that encourages and exploits sharing.
compiler orchestrated prefetching via speculation and predication. this paper introduces a compiler orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. we focus the scope of the optimization on specific subsets of the program dependence graph that succinctly characterize the memory access pattern of both regular array-based applications and irregular pointer-intensive programs. we illustrate how program embedded precomputation via speculative execution can accurately predict and effectively prefetch future memory references with negligible overhead. the proposed techniques reduce the total running time of seven spec benchmarks and two olden benchmarks by 27% on an itanium 2 processor. the improvements are in addition to several state-of-the-art optimizations including software pipelining and data prefetching. in addition, we use cycle-accurate simulations to identify important and lightweight architectural innovations that further mitigate the memory system bottleneck. in particular, we focus on the notoriously challenging class of pointer-chasing applications, and demonstrate how they may benefit from a novel scheme of it sentineled prefetching. our results for twelve spec benchmarks demonstrate that 45% of the processor stalls that are caused by the memory system are avoidable. the techniques in this paper can effectively mask long memory latencies with little instruction overhead, and can readily contribute to the performance of processors today.
a case study of vax-11 instruction set usage for compiler execution. analysis of an instruction set as large and varied as the one specified for the vax-11 architecture is important for aiding processor design evaluation. this paper looks at dynamic vax-11 instruction set usage by one class of programs, and discusses the methodology and tools which have been developed to provide that information. six vax/vms native mode compilers from digital equipment corporation were used: basic, bliss, cobol, fortran, pascal, and pl/i. a summary of results generated by analyzing executions of these six compilers is presented. information is included for instruction and class frequency, general instruction features, operand specifiers, the memory data stream, register utilization, instruction sequencing, and branch displacements.
the 801 minicomputer. this paper provides an overview of an experimental system developed at the ibm thomas j. watson research center. it consists of a running hardware prototype, a control program, and an optimizing compiler. the basic concepts underlying the system are discussed, as are the performance characteristics of the prototype. in particular, three principles are examined: (1) system orientation towards the pervasive use of high-level language programming and a sophisticated compiler, (2) a primitive instruction set which can be completely hard-wired, and (3) storage hierarchy and i/o organization to enable the cpu to execute an instruction at almost every cycle.
hardware support for memory protection: capability implementations. this paper is intended to stimulate discussion on the present state of hardware supported capability systems. interest in such systems grew up in the mid-1960's and since that time information has been published on several different versions. in the opinion of some observers, the software complexity of these systems outweighs the advantage gained. the paper surveys the situation, and endeavors to set out the general features that a hardware supported capability system should possess. an attempt is made to identify the causes of the complexity and to make recommendations for removing them. the arguments for and against the tagging of capabilities are discussed and attention is drawn to a system of semi-tagging previously proposed by the author.
transactional lock-free execution of lock-based programs. this paper is motivated by the difficulty in writing correct high-performance programs. writing shared-memory multi-threaded programs imposes a complex trade-off between programming ease and performance, largely due to subtleties in coordinating access to shared data. to ensure correctness programmers often rely on conservative locking at the expense of performance. the resulting serialization of threads is a performance bottleneck. locks also interact poorly with thread scheduling and faults, resulting in poor system performance.we seek to improve multithreaded programming trade-offs by providing architectural support for optimistic lock-free execution. in a lock-free execution, shared objects are never locked when accessed by various threads. we propose transactional lock removal (tlr) and show how a program that uses lock-based synchronization can be executed by the hardware in a lock-free manner, even in the presence of conflicts, without programmer support or software changes. tlr uses timestamps for conflict resolution, modest hardware, and features already present in many modern computer systems.tlr's benefits include improved programmability, stability, and performance. programmers can obtain benefits of lock-free data structures, such as non-blocking behavior and wait-freedom, while using lock-protected critical sections for writing programs.
performance of a hardware-assisted real-time garbage collector. hardware-assisted real-time garbage collection offers high throughput and small worst-case bounds on the times required to allocate dynamic objects and to access the memory contained within previously allocated objects. whether the proposed technology is cost effective depends on various choices between configuration alternatives. this paper reports the performance of several different configurations of the hardware-assisted real-time garbage collection system subjected to several different workloads. reported measurements demonstrate that hardware-assisted real-time garbage collection is a viable alternative to traditional explicit memory management techniques, even for low-level languages like c++.
an empirical study of decentralized ilp execution models. recent fascination for dynamic scheduling as a means for exploiting instruction-level parallelism has introduced significant interest in the scalability aspects of dynamic scheduling hardware. in order to overcome the scalability problems of centralized hardware schedulers, many decentralized execution models are being proposed and investigated recently. the crux of all these models is to split the instruction window across multiple processing elements (pes) that do independent, scheduling of instructions. the decentralized execution models proposed so far can be grouped under 3 categories, based on the criterion used for assigning an instruction to a particular pe. they are: (i) execution unit dependence based decentralization (edd), (ii) control dependence based decentralization (cdd), and (iii) data dependence based decentralization (ddd). this paper investigates the performance aspects of these three decentralization approaches. using a suite of important benchmarks and realistic system parameters, we examine performance differences resulting from the type of partitioning as well as from specific implementation issues such as the type of pe interconnect.we found that with a ring-type pe interconnect, the ddd approach performs the best when the number of pes is moderate, and that the cdd approach performs best when the number of pes is large. the currently used approach---edd---does not perform well for any configuration. with a realistic crossbar, performance does not increase with the number of pes for any of the partitioning approaches. the results give insight into the best way to use the transistor budget available for implementing the instruction window.
designing computer systems with mems-based storage. for decades the ram-to-disk memory hierarchy gap has plagued computer architects. an exciting new storage technology based on microelectromechanical systems (mems) is poised to fill a large portion of this performance gap, significantly reduce system power consumption, and enable many new applications. this paper explores the system-level implications of integrating mems-based storage into the memory hierarchy. results show that standalone mems-based storage reduces i/o stall times by 4-74x over disks and improves overall application runtimes by 1.9-4.4x. when used as on-board caches for disks, mems-based storage improves i/o response time by up to 3.5x. further, the energy consumption of mems-based storage is 10-54x less than that of state-of-the-art low-power disk drives. the combination of the high-level physical characteristics of mems-based storage (small footprints, high shock tolerance) and the ability to directly integrate mems-based storage with processing leads to such new applications as portable gigabit storage systems and ubiquitous active storage nodes.
performance of database workloads on shared-memory systems with out-of-order processors. database applications such as online transaction processing (oltp) and decision support systems (dss) constitute the largest and fastest-growing segment of the market for multiprocessor servers. however, most current system designs have been optimized to perform well on scientific and engineering workloads. given the radically different behavior of database workloads (especially oltp), it is important to re-evaluate key system design decisions in the context of this important class of applications.this paper examines the behavior of database workloads on shared-memory multiprocessors with aggressive out-of-order processors, and considers simple optimizations that can provide further performance improvements. our study is based on detailed simulations of the oracle commercial database engine. the results show that the combination of out-of-order execution and multiple instruction issue is indeed effective in improving performance of database workloads, providing gains of 1.5 and 2.6 times over an in-order single-issue processor for oltp and dss, respectively. in addition, speculative techniques enable optimized implementations of memory consistency models that significantly improve the performance of stricter consistency models, bringing the performance to within 10--15% of the performance of more relaxed models.the second part of our study focuses on the more challenging oltp workload. we show that an instruction stream buffer is effective in reducing the remaining instruction stalls in oltp, providing a 17% reduction in execution time (approaching a perfect instruction cache to within 15%). furthermore, our characterization shows that a large fraction of the data communication misses in oltp exhibit migratory behavior; our preliminary results show that software prefetch and writeback/flush hints can be used for this data to further reduce execution time by 12%.
comprehensively and efficiently protecting the heap. the goal of this paper is to propose a scheme that provides comprehensive security protection for the heap. heap vulnerabilities are increasingly being exploited for attacks on computer programs. in most implementations, the heap management library keeps the heap meta-data (heap structure information) and the application's heap data in an interleaved fashion and does not protect them against each other. such implementations are inherently unsafe: vulnerabilities in the application can cause the heap library to perform unintended actions to achieve control-flow and non-control attacks.unfortunately, current heap protection techniques are limited in that they use too many assumptions on how the attacks will be performed, require new hardware support, or require too many changes to the software developers' toolchain. we propose heap server, a new solution that does not have such drawbacks. through existing virtual memory and inter-process protection mechanisms, heap server prevents the heap meta-data from being illegally overwritten, and heap data from being meaningfully overwritten. we show that through aggressive optimizations and parallelism, heap server protects the heap with nearly-negligible performance overheads even on heap-intensive applications. we also verify the protection against several real-world exploits and attack kernels.
machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures. this paper describes the design and implementation of virtual memory management within the cmu mach operating system and the experiences gained by the mach kernel group in porting that system to a variety of architectures. as of this writing, mach runs on more than half a dozen uniprocessors and multiprocessors including the vax family of uniprocessors and multiprocessors, the ibm rt pc, the sun 3, the encore multimax, the sequent balance 21000 and several experimental computers. although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of mach virtual memory consists of a single code module and its related header file. this separation of software memory management from hardware support has been accomplished without sacrificing system performance. in addition to improving portability, it makes possible a relatively unbiased examination of the pros and cons of various hardware memory management schemes, especially as they apply to the support of multiprocessors.
hardware architectures for programming languages and programming languages for hardware architectures. programming languages and operating systems introduce abstractions which allow the programmer to ignore details of an implementation. support of an abstraction must not only concentrate on promoting the efficiency of an implementation, but also on providing the necessary guards against violations of the abstractions. in the frantic drive for efficiency the second goal has been neglected. there are indications that recent designs which are claimed to be both simple and powerful, achieve efficiency by shifting the complex issues of code generation and of appropriate guards onto compilers.complexity has become the common hallmark of software as well as hardware designs. it cannot be mastered by the common practices of testing and simulation. hardware design may profit from developments in programming methodology by adopting proof techniques similar to those used in programming.
hardware/software cooperation in the iapx-423. the intel iapx-432 is an object-based microcomputer system with a unified approach to the design and use of its architecture, operating system, and primary programming language. the concrete architecture of the 432 incorporates hardware support for data abstraction, small protection domains, and language-oriented run-time environments. it also uses its object-orientation to provide hardware support for dynamic heap storage management, interprocess communication, and processor dispatching. we begin with an overview of the 432 architecture so readers unfamiliar with its basic concepts will be able to follow the succeeding discussion without the need to consult the references. following that, we introduce the various forms of hardware/software cooperation and the criteria by which a function or service is selected for migration. this is followed by several of the more interesting examples of hardware/software cooperation in the 432. a comparison of cooperation in the 432 with several contemporary machines and discussions of development issues, past and future, complete the paper.
mondrian memory protection. mondrian memory protection (mmp) is a fine-grained protection scheme that allows multiple protection domains to flexibly share memory and export protected services. in contrast to earlier page-based systems, mmp allows arbitrary permissions control at the granularity of individual words. we use a compressed permissions table to reduce space overheads and employ two levels of permissions caching to reduce run-time overheads. the protection tables in our implementation add less than 9% overhead to the memory space used by the application. accessing the protection tables adds than 8% additional memory references to the accesses made by the application. although it can be layered on top of demand-paged virtual memory, mmp is also well-suited to embedded systems with a single physical address space. we extend mmp to support segment translation which allows a memory segment to appear at another location in the address space. we use this translation to implement zero-copy networking underneath the standard read system call interface, where packet payload fragments are connected together by the translation system to avoid data copying. this saves 52% of the memory references used by a traditional copying network stack.