waashk/dblp huggingface dataset:
mixed-mode multicore reliability. future processors are expected to observe increasing rates of hardware faults. using dual-modular redundancy (dmr), two cores of a multicore can be loosely coupled to redundantly execute a single software thread, providing very high coverage from many difference sources of faults. this reliability, however, comes at a high price in terms of per-thread ipc and overall system throughput. we make the observation that a user may want to run both applications requiring high reliability, such as financial software, and more fault tolerant applications requiring high performance, such as media or web software, on the same machine at the same time. yet a traditional dmr system must fully operate in redundant mode whenever any application requires high reliability. this paper proposes a mixed-mode multicore (mmm), which enables most applications, including the system software, to run with high reliability in dmr mode, while applications that need high performance can avoid the penalty of dmr. though conceptually simple, two key challenges arise: 1) care must be taken to protect reliable applications from any faults occurring to applications running in high performance mode, and 2) the desire to execute additional independent software threads for a performance application complicates the scheduling of computation to cores. after solving these issues, an mmm is shown to improve overall system performance, compared to a traditional dmr system, by approximately 2x when one reliable and one performance application are concurrently executing.
software-based instruction caching for embedded processors. while hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use sram or scratchpad memories instead. these are simple array memory structures that are directly addressed and explicitly managed by software. compared to hardware caches of the same data capacity, they are smaller, have shorter access times and consume less energy per access. access times are also easier to predict with simple memories since there is no possibility of a "miss." on the other hand, they are more difficult for the programmer to use since they are not automatically managed.in this paper, we present a software system that allows all or part of an sram or scratchpad memory to be automatically managed as a cache. this system provides the programming convenience of a cache for processors that lack dedicated caching hardware. it has been implemented for an actual processor and runs on real hardware. our results show that a software-based instruction cache can be built that provides performance within 10% of a traditional hardware cache on many benchmarks while using a cheaper, simpler, sram memory. on these same benchmarks, energy consumption is up to 3% lower than it would be using a hardware cache.
accelerating critical section execution with asymmetric multi-core architectures. to improve the performance of a single application on chip multiprocessors (cmps), the application must be split into threads which execute concurrently on multiple cores. in multi-threaded applications, critical sections are used to ensure that only one thread accesses shared data at any given time. critical sections can serialize the execution of threads, which significantly reduces performance and scalability. this paper proposes accelerated critical sections (acs), a technique that leverages the high-performance core(s) of an asymmetric chip multiprocessor (acmp) to accelerate the execution of critical sections. in acs, selected critical sections are executed by a high-performance core, which can execute the critical section faster than the other, smaller cores. as a result, acs reduces serialization: it lowers the likelihood of threads waiting for a critical section to finish. our evaluation on a set of 12 critical-section-intensive workloads shows that acs reduces the average execution time by 34% compared to an equal-area 32t-core symmetric cmp and by 23% compared to an equal-area acmp. moreover, for 7 out of the 12 workloads, acs improves scalability by increasing the number of threads at which performance saturates.
tartan: evaluating spatial computation for whole program execution. spatial computing (sc) has been shown to be an energy-efficient model for implementing program kernels. in this paper we explore the feasibility of using sc for more than small kernels. to this end, we evaluate the performance and energy efficiency of entire applications on tartan, a general-purpose architecture which integrates a reconfigurable fabric (rf) with a superscalar core. our compiler automatically partitions and compiles an application into an instruction stream for the core and a configuration for the rf. we use a detailed simulator to capture both timing and energy numbers for all parts of the system.our results indicate that a hierarchical rf architecture, designed around a scalable interconnect, is instrumental in harnessing the benefits of spatial computation. the interconnect uses static configuration and routing at the lower levels and a packet-switched, dynamically-routed network at the top level. tartan is most energyefficient when almost all of the application is mapped to the rf, indicating the need for the rf to support most general-purpose programming constructs. our initial investigation reveals that such a system can provide, on average, an order of magnitude improvement in energy-delay compared to an aggressive superscalar core on single-threaded workloads.
producing wrong data without doing anything obviously wrong! this paper presents a surprising result: changing a seemingly innocuous aspect of an experimental setup can cause a systems researcher to draw wrong conclusions from an experiment. what appears to be an innocuous aspect in the experimental setup may in fact introduce a significant bias in an evaluation. this phenomenon is called measurement bias in the natural and social sciences. our results demonstrate that measurement bias is significant and commonplace in computer system evaluation. by significant we mean that measurement bias can lead to a performance analysis that either over-states an effect or even yields an incorrect conclusion. by commonplace we mean that measurement bias occurs in all architectures that we tried (pentium 4, core 2, and m5 o3cpu), both compilers that we tried (gcc and intel's c compiler), and most of the spec cpu2006 c programs. thus, we cannot ignore measurement bias. nevertheless, in a literature survey of 133 recent papers from asplos, pact, pldi, and cgo, we determined that none of the papers with experimental results adequately consider measurement bias. inspired by similar problems and their solutions in other sciences, we describe and demonstrate two methods, one for detecting (causal analysis) and one for avoiding (setup randomization) measurement bias.
supporting nested transactional memory in logtm. nested transactional memory (tm) facilitates software composition by letting one module invoke another without either knowing whether the other uses transactions. closed nested transactions extend isolation of an inner transaction until the toplevel transaction commits. implementations may flatten nested transactions into the top-level one, resulting in a complete abort on conflict, or allow partial abort of inner transactions. open nested transactions allow a committing inner transaction to immediately release isolation, which increases parallelism and expressiveness at the cost of both software and hardware complexity.this paper extends the recently-proposed flat log-based transactional memory (logtm) with nested transactions. flat logtm saves pre-transaction values in a log, detects conflicts with read (r) and write (w) bits per cache block, and, on abort, invokes a software handler to unroll the log. nested logtm supports nesting by segmenting the log into a stack of activation records and modestly replicating r/w bits. to facilitate composition with nontransactional code, such as language runtime and operating system services, we propose escape actions that allow trusted code to run outside the confines of the transactional memory system.
dynamic prediction of collection yield for managed runtimes. the growth in complexity of modern systems makes it increasingly difficult to extract high-performance. the software stacks for such systems typically consist of multiple layers and include managed runtime environments (mres). in this paper, we investigate techniques to improve cooperation between these layers and the hardware to increase the efficacy of automatic memory management in mres. general-purpose mres commonly implement parallel and/or concurrent garbage collection and employ compaction to eliminate heap fragmentation. moreover, most systems trigger collection based on the amount of heap a program uses. our analysis shows that in many cases this strategy leads to ineffective collections that are unable to reclaim sufficient space to justify the incurred cost. to avoid such collections, we exploit the observation that dead objects tend to cluster together and form large, never-referenced, regions in the address space that correlate well with virtual pages that have not recently been referenced by the application. we leverage this correlation to design a new, simple and light-weight, yield predictor that estimates the amount of reclaimable space in the heap using hardware page reference bits. our predictor allows mres to avoid low-yield collections and thereby improve resource management. we integrate this predictor into three state-of-the-art parallel compactors, implemented in the hotspot jvm, that represent distinct canonical heap layouts. our empirical evaluation, based on standard java benchmarks and open-source applications, indicates that inexpensive and accurate yield prediction can improve performance significantly.
introspective 3d chips. while the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. to deal with the complexity of modern systems, software developers are increasingly dependent on specialized development tools such as security profilers, memory leak identifiers, data flight recorders, and dynamic type analysis. many of these tools require full-system data which covers multiple interacting threads, processes, and processors. reducing the performance penalty and complexity of these software tools is critical to those developing next generation applications, and many researchers have proposed adding specialized hardware to assist in profiling and introspection. unfortunately, while this additional hardware would be incredibly beneficial to developers, the cost of this hardware must be paid on every single die that is manufactured.in this paper, we argue that a new way to attack this problem is with the addition of specialized analysis hardware built on separate active layers stacked vertically on the processor die using 3d ic technology. this provides a modular "snap-on" functionality that could be included with developer systems, and omitted from consumer systems to keep the cost impact to a minimum. in this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems. we show that hardware stubs could be inserted into commodity processors at design time that would allow analysis layers to be bonded to development chips, and that these stubs would increase area and power by no more than 0.021mm2 and 0.9% respectively.
per-thread cycle accounting in smt processors. this paper proposes a cycle accounting architecture for simultaneous multithreading (smt) processors that estimates the execution times for each of the threads had they been executed alone, while they are running simultaneously on the smt processor. this is done by accounting each cycle to either a base, miss event or waiting cycle component during multi-threaded execution. single-threaded alone execution time is then estimated as the sum of the base and miss event components; the waiting cycle component represents the lost cycle count due to smt execution. the cycle accounting architecture incurs reasonable hardware cost (around 1kb of storage) and estimates single-threaded performance with average prediction errors around 7.2% for two-program workloads and 11.7% for four-program workloads. the cycle accounting architecture has several important applications to system software and its interaction with smt hardware. for one, the estimated single-thread alone execution time provides an accurate picture to system software of the actually consumed processor cycles per thread. the alone execution time instead of the total execution time (timeslice) may make system software scheduling policies more effective. second, a new class of thread-progress aware smt fetch policies based on per-thread progress indicators enable system software level priorities to be enforced at the hardware level.
recording shared memory dependencies using strata. significant time is spent by companies trying to reproduce and fix bugs. bugnet and fdr are recent architecture proposals that provide architecture support for deterministic replay debugging. they focus on continuously recording information about the program's execution, which can be communicated back to the developer. using that information, the developer can deterministically replay the program's execution to reproduce and fix the bugs.in this paper, we propose using strata to efficiently capture the shared memory dependencies. a stratum creates a time layer across all the logs for the running threads, which separates all the memory operations executed before and after the stratum. a strata log allows us to determine all the shared memory dependencies during replay and thereby supports deterministic replay debugging for multi-threaded programs.
an evaluation of the trips computer system. the trips system employs a new instruction set architecture (isa) called explicit data graph execution (edge) that renegotiates the boundary between hardware and software to expose and exploit concurrency. edge isas use a block-atomic execution model in which blocks are composed of dataflow instructions. the goal of the trips design is to mine concurrency for high performance while tolerating emerging technology scaling challenges, such as increasing wire delays and power consumption. this paper evaluates how well trips meets this goal through a detailed isa and performance analysis. we compare performance, using cycles counts, to commercial processors. on spec cpu2000, the intel core 2 outperforms compiled trips code in most cases, although trips matches a pentium 4. on simple benchmarks, compiled trips code outperforms the core 2 by 10% and hand-optimized trips code outperforms it by factor of 3. compared to conventional isas, the block-atomic model provides a larger instruction window, increases concurrency at a cost of more instructions executed, and replaces register and memory accesses with more efficient direct instruction-to-instruction communication. our analysis suggests isa, microarchitecture, and compiler enhancements for addressing weaknesses in trips and indicates that edge architectures have the potential to exploit greater concurrency in future technologies.
slick: slice-based locality exploitation for efficient redundant multithreading. transient faults are expected a be a major design consideration in future microprocessors. recent proposals for transient fault detection in processor cores have revolved around the idea of redundant threading, which involves redundant execution of a program across multiple execution contexts. this paper presents a new approach to redundant threading by bringing together the concepts of slice-level execution and value and control-flow locality into a novel partial redundant threading mechanism called slick.the purpose of redundant execution is to check the integrity of the outputs propagating out of the core (typically through stores). slick implements redundancy at the granularity of backward-slices of these output instructions and exploits value and control-flow locality to avoid redundantly executing slices that lead to predictable outputs, thereby avoiding redundant execution of a significant fraction of instructions while maintaining extremely low vulnerabilities for critical processor structures.we propose the microarchitecture of a backward-slice extractor called sliceem that is able to identify backward slices without interrupting the instruction flow, and show how this extractor and a set of predictors can be integrated into a redundant threading mechanism to form slick. detailed simulations with spec cpu2000 benchmarks show that slick can provide around 10.2% performance improvement over a well known redundant threading mechanism, buying back over 50% of the loss suffered due to redundant execution. slick can keep the architectural vulnerability factors of processor structures to typically 0%-2%. more importantly, slick's slice-based mechanisms provide future opportunities for exploring interesting points in the performance-reliability design space based on market segment needs.
phantom-btb: a virtualized branch target buffer design. modern processors use branch target buffers (btbs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. ideally, btbs would be sufficiently large to capture the entire working set of the application and sufficiently small for fast access and practical on-chip dedicated storage. depending on the application, these requirements are at odds. this work introduces a btb design that accommodates large instruction footprints without dedicating expensive onchip resources. in the proposed phantom-btb (pbtb) design, a conventional btb is augmented with a virtual table that collects branch target information as the application runs. the virtual table does not have fixed dedicated storage. instead, it is transparently allocated, on demand, in the on-chip caches, at cache line granularity. the entries in the virtual table are proactively prefetched and installed in the dedicated conventional btb, thus, increasing its perceived capacity. experimental results with commercial workloads under full-system simulation demonstrate that pbtb improves ipc performance over a 1k-entry btb by 6.9% on average and up to 12.7%, with a storage overhead of only 8%. overall, the virtualized design performs within 1% of a conventional 4k-entry, single-cycle access btb, while the dedicated storage is 3.6 times smaller.
a defect tolerant self-organizing nanoscale simd architecture. the continual decrease in transistor size (through either scaled cmos or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. however, this decrease in size is also likely to increase defect densities, contributing to the exponentially increasing cost of top-down lithography. bottom-up manufacturing techniques, like self assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. therefore, regardless of fabrication methodology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities.this paper explores a defect tolerant simd architecture. a key feature of our design is the ability of a large number of limited capability nodes with high defect rates (up to 30%) to self-organize into a set of simd processing elements. despite node simplicity and high defect rates, we show that by supporting the familiar data parallel programming model the architecture can execute a variety of programs. the architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. on a medium sized system (~1cm2 area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). for larger systems (>1cm2), the proposed architecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores.
recovery domains: an organizing principle for recoverable operating systems. we describe a strategy for enabling existing commodity operating systems to recover from unexpected run-time errors in nearly any part of the kernel, including core kernel components. our approach is dynamic and request-oriented; it isolates the effects of a fault to the requests that caused the fault rather than to static kernel components. this approach is based on a notion of "recovery domains," an organizing principle to enable rollback of state affected by a request in a multithreaded system with minimal impact on other requests or threads. we have applied this approach on v2.4.22 and v2.6.27 of the linux kernel and it required 132 lines of changed or new code: the other changes are all performed by a simple instrumentation pass of a compiler. our experiments show that the approach is able to recover from otherwise fatal faults with minimal collateral impact during a recovery event.
understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. redundant threading architectures duplicate all instructions to detect and possibly recover from transient faults. several lighter weight partial redundant threading (prt) architectures have been proposed recently. (i) opportunistic fault tolerance duplicates instructions only during periods of poor single-thread performance. (ii) restore does not explicitly duplicate instructions and instead exploits mispredictions among highly confident branch predictions as symptoms of faults. (iii) slipstream creates a reduced alternate thread by replacing many instructions with highly confident predictions. we explore prt as a possible direction for achieving the fault tolerance of full duplication with the performance of single-thread execution. opportunistic and restore yield partial coverage since they are restricted to using only partial duplication or only confident predictions, respectively. previous analysis of slipstream fault tolerance was cursory and concluded that only duplicated instructions are covered. in this paper, we attempt to better understand slipstream's fault tolerance, conjecturing that the mixture of partial duplication and confident predictions actually closely approximates the coverage of full duplication. a thorough dissection of prediction scenarios confirms that faults in nearly 100% of instructions are detectable. fewer than 0.1% of faulty instructions are not detectable due to coincident faults and mispredictions. next we show that the current recovery implementation fails to leverage excellent detection capability, since recovery sometimes initiates belatedly, after already retiring a detected faulty instruction. we propose and evaluate a suite of simple microarchitectural alterations to recovery and checking. using the best alterations, slipstream can recover from faults in 99% of instructions, compared to only 78% of instructions without alterations. both results are much higher than predicted by past research, which claims coverage for only duplicated instructions, or 65% of instructions. on an 8-issue smt processor, slipstream performs within 1.3% of single-thread execution whereas full duplication slows performance by 14%.a key byproduct of this paper is a novel analysis framework in which every dynamic instruction is considered to be hypothetically faulty, thus not requiring explicit fault injection. fault coverage is measured in terms of the fraction of candidate faulty instructions that are directly or indirectly detectable before.