waashk/dblp huggingface dataset:
analysis and modeling of cd variation for statistical static timing. statistical static timing analysis (ssta) has become a key method for analyzing the effect of process variation in aggressively scaled cmos technologies. much research has focused on the modeling of spatial correlation in ssta. however, the vast majority of these works used artificially generated process data to test the proposed models. hence, it is difficult to determine the actual effectiveness of these methods, the conditions under which they are necessary, and whether they lead to a significant increase in accuracy that warrants their increased runtime and complexity. in this paper, we study 5 different correlation models and their associated ssta methods using 35420 critical dimension (cd) measurements that were extracted from 23 reticles on 5 wafers in a 130nm cmos process. based on the measured cd data, we analyze the correlation as a function of distance and generate 5 distinct correlation models, ranging from simple models which incorporate one or two variation components to more complex models that utilize principle component analysis and quad-trees. we then study the accuracy of the different models and compare their ssta results with the result of running sta directly on the extracted data. we also examine the trade-off between model accuracy and run time, as well as the impact of die size on model accuracy. we show that, especially for small dies (< 6.6mm x 5.7mm), the simple models provide comparable accuracy to that of the more complex ones, while incurring significantly less runtime and implementation difficulty. the results of this study demonstrate that correlation models for ssta must be carefully tested on actual process data and must be used judiciously.
verification through the principle of least astonishment. assessing the correctness of a digital design is a challenging task hampered by extremely large circuit netlists, counterintuitive property descriptions and ill-defined specifications. in this paper we propose a new verification methodology, inspired by the principle of least astonishment. the underlying idea is to provide an automatic assessment of what constitutes "common behavior" for a system, and use this to detect any anomaly in the design. deviant behavior is presented to the verification engineer through intuitive, compact diagrams which lend themselves to quick inspection for correctness. to enable this methodology we introduce inferno, a new tool which can analyze the results of a logic simulation trace and automatically extract high-level diagrams representing the design's transaction activity across any user-defined interface. in addition, inferno can automatically generate a checker module corresponding to a given transaction, suitable for use in a wide range of verification methodologies. we envision the deployment of inferno in a closed-loop constraint-random simulation methodology where any new transaction detected on the interface is presented to the user for analysis and, once deemed legal, it is merged into an "approved transactions" checker, which flags the detection of any new type of transactions. we provide a series of examples and experimental results to show the effectiveness of inferno and some of its possible uses.
from micro to nano: mems as an interface to the nano world. leveraging conventional microsystems technology, mems has become the technology of choice for a wide range of applications including inertial sensors for automotive, games, and consumer applications, projection displays or inkjet print heads. in support of recent efforts to shrink dimensions to the nanoscale, mems has established itself as a perfect technology for interaction with the nanoworld. we will describe initial results using mems to manipulate single molecules for medical diagnostics. this technology has the potential to turn complex laboratory procedures into procedures that are as simple as taking the temperature.
an electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. as cmos technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ics due to on-chip hot-spots and thermal gradients are beginning to impact vlsi design. moreover, elevated substrate (junction or die) temperature strongly influences ic performance, reliability, and packaging/cooling cost. hence, accurate estimation of substrate thermal profiles is critical. this paper presents an accurate chip-level electrothermally-aware methodology for spatial silicon substrate temperature estimation. the methodology self-consistently incorporates various electrothermal couplings arising mainly due to the strong dependence of subthreshold leakage on temperature and also employs an accurate package thermal model, to account for inhomogeneous layers and non-cubic structure, which are not considered in traditional methods. the proposed methodology becomes increasingly effective as technology scales due to increasing leakage. furthermore, it is shown that considering realistic package thermal models not only improves the accuracy of estimating temperature distribution but also has significant implications for power estimation and hot-spot management.
carbon nanotubes for potential electronic and optoelectronic applications. carbon nanotubes (cnts) are novel quasi-one-dimensional materials with excellent electrical properties in addition to their remarkable mechanical strength, thermal conductivity and chemical inertness. moreover, semiconducting cnts are directgap semiconductors that directly absorb and emit light. this offers the possibility of developing a cnt-based electric and optoelectronic technology. [1]
prospects for emerging nanoelectronics in mainstream information processing systems. the international technology roadmap for semiconduc-tors (itrs) seeks to stimulate invention and research lead-ing to one or more new nanoelectronics technologies that may extend functional scaling of information processing substantially beyond "ultimately scaled" cmos. introduction of such new technologies is envisioned in two phases - first by extending the cmos platform via heterogeneous integration of new technologies and, later, via a replace-ment for cmos that would provide the equivalent of sev-eral more technology nodes beyond ultimate cmos. 1d charge state materials (nanotubes and nanowires) appear to be particularly attractive for the first phase. ferromagnetic or spin-based logic devices are under investigation for the second phase. some recent work in both of these areas will be presented.
technology migration techniques for simplified layouts with restrictive design rules. designs using simple geometric layout objects (such as points, sticks and rectangles) with restrictive design rules (rdrs) on each layout object (i.e., it must be placed on a set of grids subject to a set of ground rules) have been introduced as an approach to better enable design for manufacturability (dfm) in ultra-deep submicron designs[9]. in this paper, we study the problem of migrating the conventional shape-based layouts to the simplified layouts with rdr constraints. we present a migration flow which consists of two process steps: (1) conversion where shapes (such as polygons) are converted to simple geometric objects (such as sticks) while the topology is maintained, and (2) grid legalization for rdrs where the simple geometric objects are placed on grid subject to the given set of ground rules by using a novel legalization algorithm, the minimum perturbation-driven graph-based grid legalization(mp-ggl) algorithm. we demonstrate the effectiveness of the flow by successfully migrating a set of library cells in the conventional shape-based technology to the simplified layouts with rdr constraints.
decoupling capacitor planning and sizing for noise and leakage reduction. decoupling capacitor (decap) is a popular means to reduce power supply noise in integrated circuits. since the decaps are usually inserted in the whitespace of the device layer, decap management during the floorplanning stage is desirable. in this paper, we devise the effective decap distance model to analyze how functional blocks are affected by non-neighboring decaps. in addition, we propose a generalized network flow-based algorithm to allocate the whitespace to the blocks and determine the oxide thicknesses for the decaps to be implemented in the whitespace. experimental results show that our decap allocation and sizing methods can significantly reduce decap budget and leakage power with a small increase in area and wirelength when integrated into 2d and 3d floorplanners.
adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design. chip-package thermal analysis is necessary for the design and synthesis of reliable, high-performance, low-power, compact integrated circuits (ics). many methods of ic thermal analysis suffer performance or accuracy problems that prevent use in ic synthesis and hinder use in architectural design. this article describes isac, a novel, fast, accurate thermal analysis system for use in ic synthesis and design. we present new, cooperative, temporal and spatial adaptation methods to dramatically accelerate accurate analysis. the proposed system unifies steady-state, time-domain, and frequency-domain analysis techniques. it is composed of our spatially-adaptive multigrid iterative solver, a new temporally and spatially adaptive asynchronous time marching solver, and a new spatially-adaptive frequency-domain moment matching solver. together, these cooperative adaptation and multi-domain analysis techniques allow the proposed system to efficiently solve the static, short time scale, and long time scale variants of the ic thermal analysis problem. experimental results demonstrate significant performance improvement over existing thermal analysis solutions. our spatial adaptation techniques bring a 21.6x -690.0x speedup over recently-published steady-state thermal analysis techniques. our unified spatial and temporal adaptation techniques, within our asynchronous time marching method, bring a 1,071x -1,890x speedup over other widely-used, time-domain thermal analysis techniques with less than 0.5% error. our spatial adaptation techniques enable the efficient use of our frequency-domain thermal analysis technique, which brings a 10x -100x speedup over the fastest-known time-domain technique, when used for long time scale thermal analysis. the thermal analysis system described in this article has been implemented as a c/c++ library that has been publicly released for free academic and personal use.
physical aware frequency selection for dynamic thermal management in multi-core systems. in order to maintain performance per watt in microprocessors, there is a shift towards the chip level multiprocessing paradigm. microprocessor manufacturers are experimenting with tens of cores, forecasting the arrival of hundreds of cores per single processor die in the near future. with such large-scale integration and increasing power densities, thermal management continues to be a significant design effort to maintain performance and reliability in modern process technologies. in this paper, we present two mechanisms to perform frequency scaling as part of dynamic frequency and voltage scaling (dvfs) to assist dynamic thermal management (dtm). our frequency selection algorithms incorporate the physical interaction of the cores on a large-scale system onto the emergency intervention mechanisms for temperature reduction of the hotspot, while aiming to minimize the performance impact of frequency scaling on the core that is in thermal emergency. our results show that our algorithm consistently succeeds in maximizing the operating frequency of the most critical core while successfully relieving the thermal emergency of the core. a comparison of our two alternative techniques reveals that our physical aware criticality-based algorithm results in 11.7% faster clock frequencies compared to our aggressive scaling algorithm. we also show that our technique is extremely fast and is suited for real time thermal management
a new rlc buffer insertion algorithm. most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. as delay-length dependence is approaching linear with inductance effect [1], fewer buffers are needed to reduce rlc delay. this motivates this work to propose a new algorithm for rlc buffer insertion. in this paper, a new buffer insertion algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. a new pruning technique that provides tremendous speedup and a new frequency estimation method that is very accurate in delay computation are also proposed. experiments on industrial netlists demonstrate that our new algorithm reduces the number of buffers up to 34.4% over the traditional van ginneken's algorithm that ignores inductance. our impedance delay estimation is very accurate compared to spice simulations, with only 10% error while the delay model used in the previous rlc algorithm has 20% error [2]. the accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. incorporating slew constraints, the algorithm is accelerated by about 4x with only slight degradation in solution quality.
clock buffer polarity assignment for power noise reduction. power/ground noise is a major source of vlsi circuit timing variations. this work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. a post-processing of clock buffer sizing is performed to achieve desired clock skew. spice based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 44% and 54% respectively.
carbon nanotube transistor circuits: models and tools for design and performance optimization. in this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. an hspice model for enhancement mode nanotube transistor has been developed. it can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. a model of the carbon nanotube transistor with schottky barrier is presented. the model enables device design and performance optimization.
fast and robust quadratic placement combined with an exact linear net model. this paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. the additional force which distributes the modules on the chip in force-directed quadratic placement is separated into two forces: hold force and move force. both of these forces are determined without any heuristics. based on this novel systematic force implementation, we show that our iterative placement algorithm converges to an overlapfree placement. in addition, engineering change order (eco) is efficiently supported by our placer. to handle the important trade-off between cpu time and placement quality, a deterministic quality control is presented. in addition, a new linear net model is proposed, which accurately models the half-perimeter wirelength (hpwl) in the quadratic cost function of quadratic placement. hpwl in general is a linear metric for netlength and represents an efficient and common estimation for routed wirelength. compared with the classical clique net model, our linear net model reduces memory usage by 75%, cpu time by 23% and netlength by 8%, which is measured by the hpwl of all nets. using the ispd-2005 benchmark suite for comparison, our placer combined with the new linear net model has just 5.9% higher netlength but is 16x faster than aplace, which offers the best netlength in this benchmark. compared to capo, our placer has 9.2% lower netlength and is 5.4x faster. in the recent ispd-2006 placement contest, in which quality is mainly determined by netlength and cpu time, our placer together with the new net model produced excellent results.
network coding for routability improvement in vlsi. with the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links. recently, there has been a significant interest in a novel paradigm of network coding. network coding generalizes the traditional routing approach by allowing the network nodes to generate new packets by performing algebraic operations on packets received over the incoming links. it has been shown that network coding can increase the throughput of multicast communication. in this paper, we explore the benefits of network coding for improving the routing characteristics of vlsi designs. we demonstrate that when data has to be routed across the ic, it is often beneficial to perform network coding. initial results demonstrate that network coding can result in a healthy reduction in wire length, wire area, interconnect power as well as the active area associated with the interconnects. this comes at a small delay penalty.
formal model of data reuse analysis for hierarchical memory organizations. in real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhance the system performance and also to reduce the energy consumption. savings of dynamic energy can be obtained by accessing frequently used data from smaller memories rather than from large background memories. the optimization of the hierarchical memory architecture implies the addition of layers of smaller memories to which heavily used data can be copied. this paper presents a formal model for data reuse analysis which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. tested on a two-layer memory hierarchy, this model led to savings in the dynamic energy from 40% to over 70% relative to the energy used in the case of a flat memory design.
stepping forward with interpolants in unbounded model checking. this paper addresses sat-based unbounded model checking based on craig interpolants. this recently introduced methodology is often able to outperform bdds and other sat-based techniques on large verification instances. based on refutation proofs generated by sat solvers, interpolants provide compact circuit representations of state sets, and abstract away several details non relevant for proofs. we propose three main contributions, aimed at controlling interpolant size and traversal depth. first of all, we introduce interpolant-based dynamic abstraction to reduce the support of the computed interpolant. second, we propose new advances in interpolant compaction by redundancy removal. both techniques rely on an effective application of the incremental sat paradigm. finally, we also introduce interpolant computation exploiting circuit quantification, instead of sat refutation proofs. experimental results are specifically oriented to prove properties, rather than disproving them (bug hunting). they show how the methodology is able to extend the applicability of interpolant based model checking to larger and deeper verification instances.
a revisit to floorplan optimization by lagrangian relaxation. with the advent of deep sub-micron (dsm) era, floorplanning has become increasingly important in physical design process. in this paper we clarify a misunderstanding in using lagrangian relaxation for the minimum area floorplanning problem. we show that the problem is not convex and its optimal solution cannot be obtained by solving its lagrangian dual problem. we then propose a modified convex formulation and solve it using min-cost flow technique and trust region method. experimental results under module aspect ratio bound [0.5, 2.0] show that the running time of our floorplanner scales well with the problem size in mcnc benchmark. compared with the floorplanner in [27], our flooplanner is 9.5x faster for the largest case "ami49". it also generates a floorplan with smaller deadspace for almost all test cases. in addition, since the generated floorplan has an aspect ratio closer to 1, it is more friendly to packaging. our floorplanner is also amicable to including interconnect cost and other physical design metrics.
microarchitecture parameter selection to optimize system performance under process variation. design variability due to within-die and die-to-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. this variability manifests itself by increasing the number and criticality of long delay paths. to quantify this impact, we use an architectural process variation model that is appropriate for the analysis of system performance in the earlystages of the design process. we propose a method of selecting microarchitectural parameters to mitigate the frequency impact due to process variability for distinct structures, while minimizing ipc (instructions-per-cycle) loss. we propose an optimization procedure to be used for system-level design decisions, and we find that joint architecture and statistical timing analysis can be more advantageous than pure circuit level optimization. overall, the technique can improve the 90% yield frequency by about 14% with 3% ipc loss for a baseline machine with a 20fo4 logic depth per pipestage. this approach is sensitive to the selection of processor pipeline depth, and we demonstrate that machines with aggressive pipelines will experience greater challenges in coping with process variability.
cache miss clustering for banked memory systems. one of the previously-proposed techniques for reducing memory energy consumption is memory banking. the idea is to divide the memory space into multiple banks and place currently unused (idle) banks into a low-power operating mode. the prior studies -- both hardware and software domain - in memory energy optimization via low-power modes do not take the data cache behavior explicitly into account. as a consequence, the energy savings achieved by these techniques can be unpredictable due to dynamic cache behavior at runtime. the main contribution of this paper is a compiler optimization, called the bank-aware cache miss clustering, that increases idle durations of memory banks, and as a result, enables better exploitation of available low-power capabilities supported by the memory system. this is because clustering cache misses helps to cluster cache hits as well, and this in turn increases bank idleness. we implemented our cache miss clustering approach within a compilation framework and tested it using seven array-intensive application codes. our experiments show that cache miss clustering saves significant memory energy as a result of increased idle periods of memory banks.