waashk/dblp huggingface dataset:
robust analog/rf circuit design with projection-based posynomial modeling. we propose a robust analog design tool (road) for post-tuning analog/rf circuits. starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, road extracts accurate posynomial performance models via transistor-level simulation and optimizes the circuit by geometric programming. importantly, road sets up all design constraints to include large-scale process variations to facilitate the tradeoff between yield and performance. a novel convex formulation of the robust design problem is utilized to improve the optimization efficiency and to produce a solution that is superior to other local tuning methods. in addition, a novel projection-based approach for posynomial fitting is used to facilitate scaling to large problem sizes. a new implicit power iteration algorithm is proposed to find the optimal projection space and extract the posynomial coefficients with robust convergence. the efficacy of road is demonstrated on several circuit examples.
a markov chain sequence generator for power macromodeling. in this paper, we present a novel sequence generator based on a markov chain model. specifically, we formulate the problem of generating a sequence of vectors with given average input probability p, average transition density d, and spatial correlation s as a transition matrix computation problem, in which the matrix elements are subject to constraints derived from the specified statistics. we also give a practical heuristic that computes such a matrix and generates a sequence of l n-bit vectors in o(nl + n2) time. derived from a strongly mixing markov chain, our generator yields binary vector sequences with accurate statistics, high uniformity, and high randomness. experimental results show that our sequence generator can cover more than 99% of the parameter space. sequences of 2,000 48-bit vectors are generated in less than 0.05 seconds, with average deviations of the signal statistics p, d, and s equal to 1.6%, 1.8%, and 2.8%, respectively.our generator enables the detailed study of power macromodeling. using our tool and the iscas-85 benchmark circuits, we have assessed the sensitivity of power dissipation to the three input statistics p, d, and s. our investigation reveals that power is most sensitive to transition density, while only occasionally exhibiting high sensitivity to signal probability and spatial correlation. our experiments also show that input signal imbalance can cause estimation errors as high as 100% in extreme cases, although errors are usually within 25%.
synthesis methodology for built-in at-speed testing. we discuss a new synthesis flow, which offers the ability to do easy delay testing almost free in terms of its impact on speed and area compared to corresponding implementations with standard cells. the methodology uses matched delays in pre-charged plas and bundled routing to produce a completion signal, which is guaranteed to lie on all critical paths. we give a nondelay testing method for ensuring matched delays are correct, i.e. that all completion signals arrive after their corresponding data signals. the design margins of the matched delays can be small since they are internal to the plas, which are regular structures and therefore more predictable.
fast thermal simulation for architecture level dynamic thermal management. as power density increases exponentially, runtime regulation of operating temperature by dynamic thermal managements becomes necessary. this paper proposes a novel approach to the thermal analysis at chip architecture level for efficient dynamic thermal management. our new approach is based on the observation that the power consumption of architecture level modules in microprocessors running typical workloads presents strong nature of periodicity. such a feature can be exploited by fast spectrum analysis in frequency domain for computing steady state response. to obtain the transient temperature changes due to initial condition and constant power inputs, numerically stable moment matching approach is carried out. the total transient responses is the addition of the two simulation results. the resulting fast thermal analysis algorithm leads to at least 10/spl times/-100/spl times/ speedup over traditional integration-based transient analysis with small accuracy loss.
linear decomposition algorithm for vlsi design applications. we propose a unified solution to both linear placement and partitioning. our approach combines the well-known eigenvector optimization method with the recursive max-flow min-cut method. a linearized eigenvector method is proposed to improve the linear placement. a hypergraph maxflow algorithm is then adopted to efficiently find the max-flow min-cut. in our unified approach, the max-flow min-cut provides an optimal ordered partition subject to the given seeds and the eigenvector placement provides heuristic information for seed selection. experimental results on mcnc benchmarks show that our approach is superior to other methods for both linear placement and partitioning problems. on average, our approach yields an improvement of 45.1% over eigenvector approach in terms of total wire length, and yields an improvement of 26.9% over paraboli in terms of cut size.
defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. the large-scale process and environmental variations for today's nanoscale ics are requiring statistical approaches for timing analysis and optimization. significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. in this paper (li et al., 2005) we demonstrate why the traditional concepts of slack and critical path become ineffective under large-scale variations, and we propose a novel sensitivity-based metric to assess the "criticality" of each path and/or arc in the statistical timing graph. we define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. an efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. the efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.
a framework for designing reusable analog circuits. recent analog design tools have started to allow designers to archivenot only the sized schematics but also some of the objectives thatthe circuit is trying to achieve. this paper first describes star(schematic tool for analog reuse), a system that captures designer'sknowledge as part of the archival circuit representation,and then describes how this system can be used to create portabledesign modules. creating portable analog modules require morethan just the optimization criteria for the cell. it must also includethe constraints on the cellýs environment (for proper operation), andhow these constraints should scale with technology. furthermore,the system must help the designer in the current task of creatingthe design, since it is rare that a designer thinks about creating ipfor someone else. we demonstrate the capability and utility of thissystem by examining the reuse of a phase-locked loop.
improving over-the-cell channel routing in standard cell design. the first stage of over-the-cell routing in the horizontally connected vertically connected (hcvc) model is formulated as followings: given two rows of terminals, find a planar routing to connect a subset of nets (with weights) on each row of terminals using a fixed number of tracks to maximize the total weight. this problem is called the two row fixed height planar routing (tfpr) problem [cpl93]. the complexity of the tfpr problem was unknown up to now. an approximation algorithm for the tfpr problem was presented in [cpl93]. in this paper we present a o(n2*h2) time algorithm to solve the tfpr problem optimally, where n is the number of terminals and h is the height of the standard cells. our algorithm can be used to improve the performance of several over-the-cell channel routers including the ones in [cpl93] and [hss93].
an efficient method for terminal reduction of interconnect circuits considering delay variations. this paper proposes a novel method to efficiently reduce the terminal number of general linear interconnect circuits with a large number of input and/or output terminals considering delay variations. our new algorithm is motivated by the fact that vlsi interconnect circuits have many similar terminals in terms of their timing and delay metrics due to their closeness in structure or due to mathematic approximation using meshing in finite difference or finite element scheme during the extraction process. by allowing some delay tolerance or variations, we can reduce many similar terminals and keep a small number of representative terminals. after terminal reduction, traditional model order reduction methods can achieve more compact models and improve simulation efficiency. the new method, termmerg, is based on the moments of the circuits as the metrics for the timing or delay. it then employs singular value decomposition (svd) method to determine the optimum number of clusters based on the low-rank approximation. after this, the k-means clustering algorithm is used to cluster the moments of the terminals into different clusters. experimental results on a number of real industry interconnect circuits demonstrate the effectiveness of the proposed method.
a graph theoretic optimal algorithm for schedule compression in time-multiplexed fpga partitioning. this paper presents an optimal algorithm to solve the schedule compression problem, which is an open problem proposed by trimberger [1] for time-multiplexed fpga partitioning. time-multiplexed fpgas have the potential to dramatically improve logic density by time-sharing logic. schedule compression is an important step in partitioning for time-multiplexed fpgas [1,4,9,10] and can greatly influence the quality of the partitioning solution. we exactly solve the schedule compression problem by converting it to a constrained min-max path problem. we further extend our algorithm to minimize the communication cost during schedule compression. experiments show that our optimal algorithm outperforms the existing heuristics and runs very efficiently.
fast 3-d inductance extraction in lossy multi-layer substrate. a mixed potential integral equation (mpie) technique combined with fast multi-layer green's functions and gaussian jacobi high order techniques is used to compute the 3-d frequency dependent inductances and resistances in lossy multi-layered substrate. compared to fasthenry, a multipole-accelerated 3-d inductance extraction program, the algorithm presented here is more accurate and faster for lossy multilayer structures due to two reasons. first, substrate and optional ground plane's lose and coupling effect are efficiently modeled by multilayer green's functions, while the green's functions are efficiently calculated via window-based acceleration technique. second, gaussian jacobi-based high order techniques are used to capture the singularity of the current distribution at metal edges, leading to significant reduction of problem size and speed-up of computation.
an algorithmic approach for generic parallel adders. binary addition is the most fundamental and frequentlyused operation. a well-designed adder should be fast andsatisfy the application requirements. we propose an algorithmicapproach to generate an irregular parallel-prefix adder, whichhas minimal delay for a given profile of input signals. it cancover different topologies such as ripple-carry, carry-skip andcarry-select adders. compared with kogge-stone and brent-kungadders, the results of the proposed approach have thesmallest output delay.
systematic design for power minimization of pipelined analog-to-digital converters. in this paper a general method to design a pipelined adc withminimum power consumption is presented. by expressing the totalpower consumption and the total input-referred noise of theconverter as functions of the capacitor values and the resolutions ofthe converter stages, an optimization algorithm is employed tocalculate the optimum values of these parameters, which lead tominimum power consumption while a specific noise requirement issatisfied. to determine the bias current values of operationalamplifiers an optimal choice for settling and slewing timeparameters is proposed. a practical design example is presented toshow the effectiveness of the proposed methodology.
concurrent logic restructuring and placement for timing closure. in this paper, an algorithm for simultaneous logic restructuring and placement is presented. this algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each supercell. the best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (ggp) problem. the process of identifying and optimizing the critical paths is iterated until timing closure is achieved. experimental results on a set of mcnc benchmarks demonstrate the effectiveness of our algorithm.
an exact solution to simultaneous technology mapping and linear placement problem. in this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. the proposed algorithm relies on generation of gate-area versus cut-width curves using a dynamic programming approach. a novel design flow, which extends this algorithm to minimize the circuit delay and handle general dag structures, is also presented. experimental results on mcnc benchmarks are reported.
interconnect lifetime prediction under dynamic stress for reliability-aware design. thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, ic package cost and reliability. while many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. this model is verified with numerical solutions. with this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. in fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. this model is similarly useful for temperature-aware dynamic runtime management.
abilbo: analog built-in block observer. this paper presents a novel multifunctional test structure called analog built-in block observer (abilbo). this structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. a high fault coverage was obtained by using a discrete switched-capacitor abilbo for testing a biquad filter. the abilbo area overhead and performance penalty can be very low if functional and testing circuitry are shared. this is typically the case of high order filters based on a cascade of biquads.
accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. in this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in vlsi designs. due to increasing operating frequencies, microwave-like effects will become important. therefore stronger demands are put on extraction and verification tools. we indicate the state-of-the-art for capacitance, resistance and substrate resistance extraction and discuss some open problems. we also discuss several model reduction techniques as well as issues related to simulation and implementation in a cad system.
distributed simulation of vlsi systems via lookahead-free self-adaptive optimistic and conservative synchronization. this paper presents a new protocol for parallel and distributed simulation of vlsi systems. it is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. all these features make it very convenient and practical, extending the class of applications to at least all vhdl circuits, including delta cycle. the proposed protocol has been implemented and used for vhdl simulation. experimental results on several large vhdl circuits (between 1411 and 14704 processes) have shown promising linear speedups. we also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. this protocol may have a string impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.
a super-scheduler for embedded reconfigurable systems. emerging reconfigurable systems attain high peformance with embedded optimized cores. for mapping designs on such special architectures, synthesis tools, that are aware of the special capabilities of the underlying architecture are necessary. in this paper we are proposing an algorithm to perform simultaneous scheduling and binding, targeting embedded reconfigurable systems. our algorithm differs from traditional scheduling methods in its capability of efficiently utilizing embedded blocks within the reconfigurable system. our algorithm can be used to implement several other scheduling techniques, such as asap, alap, and list scheduling. hence we refer to it as a super-scheduler. our algorithm is a path-based scheduling algorithm. at each step, an individual path from the input dfg is scheduled. our experiments with several dfg's extracted from mediabench suit indicate promising results. our scheduler presents capability to perform the trade-off between maximally utilizing the high-performance embedded blocks and exploiting parallelism in the schedule.
power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems. in this paper, we present a power-conscious algorithm for jointly scheduling multi-rate periodic task graphs and aperiodic tasks in distributed real-time embedded systems. while the periodic task graphs have hard deadlines, the aperiodic tasks can have either hard or soft deadlines. periodic task graphs are first scheduled statically. slots are created in this static schedule to accommodate hard aperiodic tasks. soft aperiodic tasks are scheduled dynamically with an on-line scheduler. flexibility is introduced into the static schedule and optimized to allow the on-line scheduler to make dynamic modifications to the static schedule. this helps minimize the response times of soft aperiodic tasks through both resource reclaiming and slack stealing. of course, the validity of the static schedule is maintained. the on-line scheduler also employs dynamic voltage scaling and power management to obtain a power-efficient schedule. experimental results show that the flexibility introduced into the static schedule helps improve the response times of soft aperiodic tasks by up to 43%. dynamic voltage scaling and power management reduce power by up to 68%. the scheme in which the static schedule is allowed to be flexible achieves up to 32% more power saving compared to the scheme in which no flexibility is allowed, when both schemes are power-conscious. our work gives an average architecture price saving of 30% over a previous approach for embedded system architectures synthesized with execution slots for hard aperiodic tasks present.
netbench: a benchmarking suite for network processors. in this study we introduce netbench, a benchmarking suite for network processors. netbench contains a total of 9 applications that are representative of commercial applications for network processors. these applications are from all levels of packet processing; small, low-level code fragments as well as large application level programs are included in the suite.using simplescalar simulator we study the netbench programs in detail and characterize the network processor workloads. we also compare key characteristics such as instructions per cycle, instruction distribution, branch prediction accuracy, and cache behavior with the programs from mediabench. although the aimed architectures are similar for mediabench and netbench suites, we show that these workloads have significantly different characteristics. hence a separate benchmarking suite for network processors is a necessity. finally, we present performance measurements from intel ixp1200 network processor to show how netbench can be utilized.
computational geometry based placement migration. placement migration is a critical step to address a variety of post-placement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. to fix a design problem, one would like to perturb the design as little as possible while preserving the integrity of the original placement. this work presents a novel computational geometry based placement migration method, and a new stability metric to more accurately measure the "similarity" between two placements. it has two stages, a bin-based spreading at coarse scale and a delaunay triangulation based spreading at finer grain. it has clear advantage over conventional legalization algorithms such that the neighborhood characteristics of the original placement are preserved. thus, the placement migration is much more stable, which is important to maintain. applying this technique to placement legalization demonstrates significant improvements in wire length and stability compared to other popular legalization algorithms.
a partitioning algorithm for system-level synthesis. the partitioning/scheduling/allocation algorithm developed for the capsys method is presented. the aim of this project is to define a tool able to automatically design dedicated and embedded vliw architectures for large and complex applications. it inherits a sizable knowledge-pool from the wider field of parallel processors, vliw compiler design and high-level synthesis. emphasis is placed on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. the proposed solution implements a software/hardware approach based on the list-scheduling heuristic