waashk/dblp huggingface dataset:
on a general property of memory mapping tables. the paper shows that memory mapping tables can be used to implement the display registers used in providing architectural support for block-structured languages such as algol 60. this allows full lexical level addressing to be implemented on so-called von-neuman machines. the problems of fragmentation of the paged address space are explored, and machines with memory mapping schemes capable of supporting the proposals identified. attention is drawn to the similarity between segmented and paged schemes, and it is suggested that the latter may be used to support the former.
formal online methods for voltage/frequency control in multiple clock domain microprocessors. multiple clock domain (mcd) processors are a promising future alternative to today's fully synchronous designs. dynamic voltage and frequency scaling (dvfs) in an mcd processor has the extra flexibility to adjust the voltage and frequency in each domain independently. most existing dvfs approaches are profile-based offline schemes which are mainly suitable for applications whose execution char-acteristics are constrained and repeatable. while some work has been published about online dvfs schemes, the prior approaches are typically heuristic-based. in this paper, we present an effective online dvfs scheme for an mcd processor which takes a formal analytic approach, is driven by dynamic workloads, and is suitable for all applications. in our approach, we model an mcd processor as a queue-domain network and the online dvfs as a feedback control problem with issue queue occupancies as feedback signals. a dynamic stochastic queuing model is first proposed and linearized through an accu-rate linearization technique. a controller is then designed and verified by stability analysis. finally we evaluate our dvfs scheme through a cycle-accurate simulation with a broad set of applications selected from mediabench and spec2000 benchmark suites. compared to the best-known prior approach, which is heuristic-based, the proposed online dvfs scheme is substantially more effective due to its automatic regulation ability. for example, we have achieved a 2-3 fold increase in efficiency in terms of energy-delay product improvement. in addition, our control theoretic technique is more resilient, requires less tuning effort, and has better scalability as compared to prior online dvfs schemes.we believe that the techniques and methodology described in this paper can be generalized for energy control in processors other than mcd, such as tiled stream processors.
oceanstore: an architecture for global-scale persistent storage. oceanstore is a utility infrastructure designed to span the globe and provide continuous access to persistent information. since this infrastructure is comprised of untrusted servers, data is protected through redundancy and cryptographic techniques. to improve performance, data is allowed to be cached anywhere, anytime. additionally, monitoring of usage patterns allows adaptation to regional outages and denial of service attacks; monitoring also enhances performance through pro-active movement of data. a prototype implementation is currently under development.
the structure and performance of interpreters. interpreted languages have become increasingly popular due to demands for rapid program development, ease of use, portability, and safety. beyond the general impression that they are "slow," however, little has been documented about the performance of interpreters as a class of applications.this paper examines interpreter performance by measuring and analyzing interpreters from both software and hardware perspectives. as examples, we measure the mipsi, java, perl, and tcl interpreters running an array of micro and macro benchmarks on a dec alpha platform. our measurements of these interpreters relate performance to the complexity of the interpreter's virtual machine and demonstrate that native runtime libraries can play a key role in providing good performance. from an architectural perspective, we show that interpreter performance is primarily a function of the interpreter itself and is relatively independent of the application being interpreted. we also demonstrate that high-level interpreters' demands on processor resources are comparable to those of other complex compiled programs, such as gcc. we conclude that interpreters, as a class of applications, do not currently motivate special hardware support for increased performance.
closing the window of vulnerability in multiphase memory transactions. multiprocessor architects have begun to explore several mechanisms such as prefetching, context-switching and software-assisted dynamic cache-coherence, which transform single-phase memory transactions in conventional memory systems into multiphase operations. multiphase operations introduce a window of vulnerability in which data can be invalidated before it is used. losing data due to invalidations introduces damaging livelock situations. this paper discusses the origins of the window of vulnerability and proposes an architectural framework that closes it. the framework is implemented in alewife, a large-scale multi-processor being built at mit.
fast out-of-order processor simulation using memoization. our new out-of-order processor simulatol; fastsim, uses two innovations to speed up simulation 8--15 times (vs. wisconsin simplescalar) with no loss in simulation accuracy. first, fastsim uses speculative direct-execution to accelerate the functional emulation of speculatively executed program code. second, it uses a variation on memoization---a well-known technique in programming language implementation---to cache microarchitecture states and the resulting simulator actions, and then "fast forwards" the simulation the next time a cached state is reached. fast-forwarding accelerates simulation by an order of magnitude, while producing exactly the same, cycle-accurate result as conventional simulation.
fine-grain access control for distributed shared memory. this paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. fine-grain access control forms the basis of efficient cache-coherent shared memory. this paper focuses on low-cost implementations that require little or no additional hardware. these techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing.this paper categorizes techniques based on where access control is enforced and where access conflicts are handled. we incorporated three techniques that require no additional hardware into blizzard, a system that supports distributed shared memory on the cm-5. the first adds a software lookup before each shared-memory reference by modifying the program's executable. the second uses the memory's error correcting code (ecc) as cache-block valid bits. the third is a hybrid. the software technique ranged from slightly faster to two times slower than the ecc approach. blizzard's performance is roughly comparable to a hardware shared-memory machine. these results argue that clusters of workstations or personal computers with networks comparable to the cm-5's will be able to support the same shared-memory interfaces as supercomputers.
fast procedure calls. a mechanism for control transfers should handle a variety of applications (e.g., procedure calls and returns, coroutine transfers, exceptions, process switches) in a uniform way. it should also allow an implementation in which the common cases of procedure call and return are extremely fast, preferably as fast as unconditional jumps in the normal case. this paper describes such a mechanism and methods for its efficient implementation.
synchronization and communication in the t3e multiprocessor. this paper describes the synchronization and communication primitives of the cray t3e multiprocessor, a shared memory system scalable to 2048 processors. we discuss what we have learned from the t3d project (the predecessor to the t3e) and the rationale behind changes made for the t3e. we include performance measurements for various aspects of communication and synchronization.the t3e augments the memory interface of the dec 21164 microprocessor with a large set of explicitly-managed, external registers (e-registers). e-registers are used as the source or target for all remote communication. they provide a highly pipelined interface to global memory that allows dozens of requests per processor to be outstanding. through e-registers, the t3e provides a rich set of atomic memory operations and a flexible, user-level messaging facility. the t3e also provides a set of virtual hardware barrier/eureka networks that can be arbitrarily embedded into the 3d torus interconnect.
lcm: memory system support for parallel language implementation. higher-level parallel programming languages can be difficult to implement efficiently on parallel machines. this paper shows how a flexible, compiler-controlled memory system can help achieve good performance for language constructs that previously appeared too costly to be practical.our compiler-controlled memory system is called loosely coherent memory (lcm). it is an example of a larger class of reconcilable shared memory (rsm) systems, which generalize the replication and merge policies of cache-coherent shared-memory. rsm protocols differ in the action taken by a processor in response to a request for a location and the way in which a processor reconciles multiple outstanding copies of a location. lcm memory becomes temporarily inconsistent to implement the semantics of c** parallel functions efficiently. rsm provides a compiler with control over memory-system policies, which it can use to implement a language's semantics, improve performance, or detect errors. we illustrate the first two points with lcm and our compiler for the data-parallel language c**.
segregating heap objects by reference behavior and lifetime. dynamic storage allocation has become increasingly important in many applications, in part due to the use of the object-oriented paradigm. at the same time, processor speeds are increasing faster than memory speeds and programs are increasing in size faster than memories. in this paper, we investigate efforts to predict heap object reference and lifetime behavior at the time objects are allocated. our approach uses profile-based optimization, and considers a variety of different information sources present at the time of object allocation to predict the object's reference frequency and lifetime. our results, based on measurements of six allocation intensive programs, show that program references to heap objects are highly predictable and that our prediction methods can successfully predict the behavior of these heap objects. we show that our methods can decrease the page fault rate of the programs measured, sometimes dramatically, in cases where the physical memory available to the program is constrained.
interleaving: a multithreading technique targeting multiprocessors and workstations. there is an increasing trend to use commodity microprocessors as the compute engines in large-scale multiprocessors. however, given that the majority of the microprocessors are sold in the workstation market, not in the multiprocessor market, it is only natural that architectural features that benefit only multiprocessors are less likely to be adopted in commodity microprocessors. in this paper, we explore multiple-context processors, an architectural technique proposed to hide the large memory latency in multiprocessors. we show that while current multiple-context designs work reasonably well for multiprocessors, they are ineffective in hiding the much shorter uniprocessor latencies using the limited parallelism found in workstation environments. we propose an alternative design that combines the best features of two existing approaches, and present simulation results that show it yields better performance for both multiprogrammed workloads on a workstation and parallel applications on a multiprocessor. by addressing the needs of the workstation environment, our proposal makes multiple contexts more attractive for commodity microprocessors.
multiple-block ahead branch predictors. a basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. this paper presents a novel cost-effective mechanism called the two-block ahead branch predictor. information from the current instruction block is not used for predicting the address of the next instruction block, but rather for predicting the block following the next instruction block.this approach overcomes the instruction fetch bottle-neck exhibited by wide-dispatch "brainiac" processors by enabling them to efficiently predict addresses of two instruction blocks in a single cycle. furthermore, pipelining the branch prediction process can also be done by means of our predictor for "speed demon" processors to achieve higher clock rate or to improve the prediction accuracy by means of bigger prediction structures.moreover, and unlike the previously-proposed multiple predictor schemes, multiple-block ahead branch predictors can use any of the branch prediction schemes to perform the very accurate predictions required to achieve high-performance on superscalar processors.
power aware page allocation. one of the major challenges of post-pc computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. memory is a particularly important target for efforts to improve energy efficiency. memory technology is becoming available that offers power management features such as the ability to put individual chips in any one of several different power modes. in this paper we explore the interaction of page placement with static and dynamic hardware policies to exploit these emerging hardware features. in particular, we consider page allocation policies that can be employed by an informed operating system to complement the hardware power management strategies. we perform experiments using two complementary simulation environments: a trace-driven simulator with workload traces that are representative of mobile computing and an execution-driven simulator with a detailed processor/memory model and a more memory-intensive set of benchmarks (spec2000). our results make a compelling case for a cooperative hardware/software approach for exploiting power-aware memory, with down to as little as 45% of the energy&bull; delay for the best static policy and 1% to 20% of the energy&bull; delay for a traditional full-power memory.
locality phase prediction. as computer memory hierarchy becomes adaptive, its performance increasingly depends on forecasting the dynamic program locality. this paper presents a method that predicts the locality phases of a program by a combination of locality profiling and run-time prediction. by profiling a training input, it identifies locality phases by sifting through all accesses to all data elements using variable-distance sampling, wavelet filtering, and optimal phase partitioning. it then constructs a phase hierarchy through grammar compression. finally, it inserts phase markers into the program using binary rewriting. when the instrumented program runs, it uses the first few executions of a phase to predict all its later executions.compared with existing methods based on program code and execution intervals, locality phase prediction is unique because it uses locality profiles, and it marks phase boundaries in program code. the second half of the paper presents a comprehensive evaluation. it measures the accuracy and the coverage of the new technique and compares it with best known run-time methods. it measures its benefit in adaptive cache resizing and memory remapping. finally, it compares the automatic analysis with manual phase marking. the results show that locality phase prediction is well suited for identifying large, recurring phases in complex programs.
space-time scheduling of instruction-level parallelism on a raw machine. increasing demand for both greater parallelism and faster clocks dictate that future generation architectures will need to decentralize their resources and eliminate primitives that require single cycle global communication. a raw microprocessor distributes all of its resources, including instruction streams, register files, memory ports, and alus, over a pipelined two-dimensional mesh interconnect, and exposes them fully to the compiler. because communication in raw machines is distributed, compiling for instruction-level parallelism (ilp) requires both spatial instruction partitioning as well as traditional temporal instruction scheduling. in addition, the compiler must explicitly manage all communication through the interconnect, including the global synchronization required at branch points. this paper describes rawcc, the compiler we have developed for compiling general-purpose sequential programs to the distributed raw architecture. we present performance results that demonstrate that although raw machines provide no mechanisms for global communication the raw compiler can schedule to achieve speedups that scale with the number of available functional units.
automatically characterizing large scale program behavior. understanding program behavior is at the foundation of computer architecture and program optimization. many programs have wildly different behavior on even the very largest of scales (over the complete execution of the program). this realization has ramifications for many architectural and compiler techniques, from thread scheduling, to feedback directed optimizations, to the way programs are simulated. however, in order to take advantage of time-varying behavior, we must first develop the analytical tools necessary to automatically and efficiently analyze program behavior over large sections of execution.our goal is to develop automatic techniques that are capable of finding and exploiting the large scale behavior of programs (behavior seen over billions of instructions). the first step towards this goal is the development of a hardware independent metric that can concisely summarize the behavior of an arbitrary section of execution in a program. to this end we examine the use of basic block vectors. we quantify the effectiveness of basic block vectors in capturing program behavior across several different architectural metrics, explore the large scale behavior of several programs, and develop a set of algorithms based on clustering capable of analyzing this behavior. we then demonstrate an application of this technology to automatically determine where to simulate for a program to help guide computer architecture research.
evolving rpc for active storage. we introduce scriptable rpc (srpc), an rpc-based framework that enables distributed system services to take advantage of active components. technology trends point to a world where each component in a system (whether disk, network interface, or memory) has substantial computational capabilities; however, traditional methods of building distributed services are not designed to take advantage of these new architectures, mandating wholesale change of the software base to exploit more powerful hardware. in contrast, srpc provides a direct and simple migration path for traditional services into the active environment.we demonstrate the power and flexibility of the srpc framework through a series of case studies, with a focus on active storage servers. specifically, we find three advantages to our approach. first, srpc improves the performance of distributed file servers, reducing latency by combining the execution of operations at the file server. second, srpc enables the ready addition of new functionality; for example, more powerful cache consistency models can be realized on top of a server that exports a simple nfs-like interface. third, srpc simplifies the construction of distributed services; operations that are difficult to coordinate across client and server can now be co-executed at the server, thus avoiding costly agreement and crash-recovery protocols.
simple compiler algorithms to reduce ownership operhead in cache coherence protocols. we study in this paper the design and efficiency of compiler algorithms that remove ownership overhead in shared-memory multiprocessors with write-invalidate protocols. these algorithms detect loads followed by stores to the same address. such loads are marked and constitute a hint to the cache to obtain an exclusive copy of the block. we consider three algorithms where the first one focuses on load-store sequences within each basic block of code and the other two analyse the existence of load-store sequences across basic blocks at the intra-procedural level. since the dataflow analysis we adopt is a trivial variation of live-variable analysis, the algorithms are easily incorporated into a compiler.through detailed simulations of a cache-coherent numa architecture using five scientific parallel benchmark programs, we find that the algorithms are capable of removing over 95% of the separate ownership acquisitions. moreover, we also find that even the simplest algorithm is comparable in efficiency with previously proposed hardware-based adaptive cache coherence protocols to attack the same problem.
petal: distributed virtual disks. the ideal storage system is globally accessible, always available, provides unlimited performance and capacity for a large number of clients, and requires no management. this paper describes the design, implementation, and performance of petal, a system that attempts to approximate this ideal in practice through a novel combination of features. petal consists of a collection of network-connected servers that cooperatively manage a pool of physical disks. to a petal client, this collection appears as a highly available block-level storage system that provides large abstract containers called virtual disks. a virtual disk is globally accessible to all petal clients on the network. a client can create a virtual disk on demand to tap the entire capacity and performance of the underlying physical resources. furthermore, additional resources, such as servers and disks, can be automatically incorporated into petal.we have an initial petal prototype consisting of four 225 mhz dec 3000/700 workstations running digital unix and connected by a 155 mbit/s atm network. the prototype provides clients with virtual disks that tolerate and recover from disk, server, and network failures. latency is comparable to a locally attached disk, and throughput scales with the number of servers. the prototype can achieve i/o rates of up to 3150 requests/sec and bandwidth up to 43.1 mbytes/sec.