waashk/dblp huggingface dataset:
a probabilistic model for correspondence problems using random walks with restart. technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (mpsocs) and chip multi-processors (cmps). in these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, nigh-bandwidth network-on-chip (noc) fabrics. as transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful noc architectures become feasible that can support more sophisticated and demanding applications. given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening noc design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. this prompted us to develop polaris 1, a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). polaris explores the plethora of noc designs based on projections of network traffic, architectures, and process characteristics. while the polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 noc design points. polaris is rapid and iterates over all these noc architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed noc synthesis results.
fingerspelling recognition through classification of letter-to-letter transitions. currently, most governments experience severe problems managing the large n tier, networked environment. while new it technologies aiming at automating the deployment and maintenance of it infrastructure are emerging, as manifested in the autonomic computing paradigm where the it infrastructure and its components are self-managing, the technology alone still cannot solve the complex information system manageability problems for e-government infrastructure. this paper proposes an information and knowledge management model that combines the benefit of autonomic computing system paradigm for self-managed infrastructure systems and an event-based awareness collaboration knowledge management approach for coordinating the infrastructure management processes. we hope it provides a more comprehensive guideline for managing e-government information systems.
adapting svm image classifiers to changes in imaging conditions using incremental svm: an application to car detection. with the fast development of the technology in database and internet, excessive information has become a problem that decision makers engage in electronic commerce have to affront. this paper firstly establishes the decision table for excessive data, then reduces knowledge of the decision table, and obtains the best rules. this can reduce the redundancy of the data, and improve the efficiency of knowledge obtaining. because of the high time complexity and spatial complexity the general algorithm has, this paper proposed a new algorithm based on analogical matrix, and carried out the algorithm. the practice proves that the algorithm can improve the efficiency of knowledge obtaining, and the rules is tidy and best.
fingerprint orientation field estimation: model of primary ridge for global structure and model of secondary ridge for correction. watermarks can be embedded into the host contents by multiplicative spread spectrum (mss) methods. however, the interference from the host contents hinders the successful detection of the embedded watermark. this interference can be compensated at the embedder, or be exploited at the detector to improve the detection rate. in this paper, we first derive the optimum decision rule for watermarking in the discrete cosine transform domain, and then proceed to present an enhanced mss scheme that compensates the host interference at the embedder. in our scheme, the host interference to be compensated is a generalized correlation tailored to the optimum decision rule. its effectiveness is validated through both theoretical analyses and experiments
super-resolution of multiple moving 3d objects with pixel-based registration. with the growing popularity of xml technology, developing effective and efficient query techniques of xml data becomes an important problem. in this paper, we introduce a query recommendation technique, which is able to provide both result recommendation and query input recommendation for xml queries, to help users to find useful information more efficiently. ln our approach, we mine association rules from xml documents to discover related xml fragments and recommend to the user the possibly interesting results, which are however not included in the original query results. in order to restrict the number of discovered rules and to discard uninteresting rules, our system allows users to specify constraints on the generated association rules. in addition to the recommendation of results, our system also provides potentially relevant xml queries to help users to find the desired content rapidly. our experimental results show that our methods can provide recommendations for both query results and query input effectively.
face relighting based on multi-spectral quotient image and illumination tensorfaces. this paper introduces compositional time petri net (ctpn) models. a ctpn is a modularized time petri net (tpn), which is composed of components and connectors. the paper also proposes a set of component-level reduction rules for tpns. each of these reduction rules transforms a tpn component to a very simple one while maintaining the net's external observable timing properties. consequently, the proposed method works at a coarse level rather than at an individual transition level. therefore, one requires significantly fewer applications to reduce the size of the tpn under analysis than those existing ones for tpns. the use and benefits of ctpns and reduction rules are illustrated by modeling and analyzing the response time of a command and control system to its external arriving messages
weighted map for reflectance and shading separation using a single image. this paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. conventional multiprocessor scheduling, applied to this architecture, will attempt to balance the thread load across cores. this research demonstrates that such an approach eliminates one of the big advantages of this architecture - the ability to use unbalanced schedules to allocate the right amount of execution resources to each thread. however, accommodating unbalanced schedules creates several difficulties, the biggest being the fact that the search space of all schedules (both balanced and unbalanced) is much greater than that of the balanced schedules alone. this work proposes and evaluates scheduling policies that allow the system to identify and migrate toward good thread schedules, whether the best schedules are balanced or unbalanced
spatially varying regularization of image sequences super-resolution. in this paper, we propose and evaluate a new protocol that provides topology change- and fault-tolerant real-time communication services on now and clusters. this protocol overcomes the main drawback of our previously proposed protocol, called dynamically re-established real-time channels (drrtc), which is physically limited by the number of virtual channels per port. the new protocol allows different real-time channels to share the same virtual channel. in this way, the new protocol allows us to establish a greater number of real-time channels than the previous one. moreover, its only limitation is the bandwidth devoted to real-time traffic. however, this introduces two new problems that are successfully managed by the new protocol: the existence of cyclic dependencies among different real-time channels and the increased complexity of deadline requirements. we present and analyze the performance evaluation results when a single switch or a single link is deactivated/activated for different topologies and workloads. the new protocol overwhelms the drrtc protocol while guaranteeing deadline requirements and channel recovery.
training support vector machines on large sets of image data. reduced resolution update (rru) video coding provides a better compression performance than h.264/avc does. it is implemented by encoding the predicted residuals after down-sampling at the encoder and at the decoder, is up-sampled to the full-resolution size while motion compensation prediction signal are still yielded in the full-resolution spatial domain. in this paper, the authors first extend the frame-level rru to the macroblock-level to obtain better coding performance than the frame-level rru. furthermore, a novel macroblock-level reduced resolution coding scheme was proposed which adaptively selects the part of dct coefficients in the zigzag scan order to obtain better coding efficiency in terms of rate distortion performance. experimental results exhibit that the proposed methods can achieve obvious improvements in both compression efficiency and decoding complexity compared with the frame-level rru and h.264/avc.
gable roof description by self-avoiding polygon. in this paper an analytic model for ge/si core/shell nanowire mosfets (nwfets) is developed. first, the electrostatic potential and charge model are derived out from classical device physics. then the drift-diffusion drain current model is obtained and verified by comparisons with the numerical simulation. the ballistic current model is obtained with the approximately described quantum-mechanical effect through modifying the intrinsic carrier concentration under 2-dimensional confinement. with the proposed model, the performances of ge/si core/shell nwfets are analyzed and significant characteristics are demonstrated in details. the analytic model in this paper provides a framework for further developing compact models of the nwfets with ge/si core/shell heterostructure for circuit design and simulation.
efficient classification of images with taxonomies. one important issue the designer of a scalable shared-memory multiprocessor must deal with is the amount of extra memory required to store the directory information. it is desirable that the directory memory overhead be kept as low as possible, and that it scales very slowly with the size of the machine. unfortunately, current directory architectures provide scalability at the expense of performance. this work presents a scalable directory architecture that significantly reduces the size of the directory for large-scale configurations of a multiprocessor without degrading performance. first, we propose multilayer clustering as an effective approach to reduce the width of directory entries. based on this concept, we derive three new compressed sharing codes, some of them with a space complexity of o(log2(log2(n))) for an n-node system. then, we present a novel two-level directory architecture to eliminate the penalty caused by compressed directories in general. the proposed organization consists of a small full-map first-level directory (which provides precise information for the most recently referenced lines) and a compressed second-level directory (which provides in-excess information for all the lines). the proposals are evaluated based on extensive execution-driven simulations (using rsim) of a 64-node cc-numa multiprocessor. results demonstrate that a system with a two-level directory architecture achieves the same performance as a multiprocessor with a big and nonscalable full-map directory, with a very significant reduction of the memory overhead.
a 7-round parallel hardware-saving accelerator for gaussian and dog pyramid construction part of sift. this paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. it shows that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget. this research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multi-core design. several examples are presented showing the need for careful co-design. for instance, increasing interconnect bandwidth requires area that then constrains the number of cores or cache sizes, and does not necessarily increase performance. also, shared level-2 caches become significantly less attractive when the overhead of the resulting crossbar is accounted for. a hierarchical bus structure is examined which negates some of the performance costs of the assumed base-line architecture.
polygonal light source estimation. this paper focuses on the problem of reasoning about concurrent assembly code with reentrant locks. our verification technique is based on concurrent separation logic (csl). in csl, locks are treated as non-reentrant locks and each lock is associated with a resource invariant, the lock-protected resources are obtained and released through acquiring and releasing the lock respectively. in order to accommodate for reentrancy, we introduce some additional notions into our specification language to describe reentrant level for each acquiring and releasing lock operation. keeping track of the reentrant level for each lock in the pre- and post- conditions enables the program logic to ensure that resources are not reacquired upon reentrancy, thus resources owned by a thread are prevented from reintroducing in the postcondition. our framework is fully mechanized. its soundness has been verified using the coq proof assistant. we demonstrate the usage of our framework through giving a safety proof of a simple program.
incrementally discovering object classes using similarity propagation and graph clustering. for improving the usability of the anonymous result, it is important to comply with the hierarchical structure when generalizing quasi-identifying attributes with hierarchical characteristics. we propose an unrestricted multi-dimensional anonymization model which combines global recoding and local recoding methods. the bottom-up anonymization algorithm with the minimal coverage subgraph constraint and the anonymization metric are proposed. the experiment results justify the effectiveness and scalability of this model.
skeleton graph matching based on critical points using path similarity. a fuzzy logic expert system for diagnosis and security assessment of power transformers (fdsapt) is presented. a prototype of this expert-system has been accomplished with the ai-language turbo-prolog on a microcomputer and satisfactory application results were obtained. in building a sophisticated expert system for fd-sapt, the main difficulties arise from the inexactness or impreciseness of the fault information, the uncertainty of the inference rules, the complexity of representing experts' knowledge, and the inference process. to solve these problems, the test information was represented by fuzzy sets obtained by the operation of predicate rules. a production rule with a certainty factor was adopted to represent the knowledge of experts, and a fuzzy inference approach based on fuzzy synthetic judgment theory was introduced into the inexact reasoning of the expert system. a complex inference mechanism with depth-first search strategy was successfully used in this system. the fdsapt system has been applied to beijing electric power system and satisfactory results were obtained
highly-automatic mi based multiple 2d/3d image registration using self-initialized geodesic feature correspondences. given a user keyword query, current web search engines return a list of individual web pages ranked by their "goodness" with respect to the query. thus, the basic unit for search and retrieval is an individual page, even though information on a topic is often spread across multiple pages. this degrades the quality of search results, especially for long or uncorrelated (multitopic) queries (in which individual keywords rarely occur together in the same document), where a single page is unlikely to satisfy the user's information need. we propose a technique that, given a keyword query, on the fly generates new pages, called composed pages, which contain all query keywords. the composed pages are generated by extracting and stitching together relevant pieces from hyperlinked web pages and retaining links to the original web pages. to rank the composed pages, we consider both the hyperlink structure of the original pages and the associations between the keywords within each page. furthermore, we present and experimentally evaluate heuristic algorithms to efficiently generate the top composed pages. the quality of our method is compared to current approaches by using user surveys. finally, we also show how our techniques can be used to perform query-specific summarization of web pages.
a variant of the trace quotient formulation for dimensionality reduction. the paper describes an algorithm for combining color and texture information for the segmentation of color images. the algorithm uses maximum likelihood classification combined with a certainty based fusion criterion. the algorithm was validated using mosaics of real color textures. it was also tested on real outdoor color scenes and aerial images. this algorithm is part of a more complex system which is currently being designed to assist an operator in updating an old map of an area using aerial images
background estimation based on device pixel structures for silhouette extraction. current trends in computing indicate that there is a great potential for service oriented computing and similar technologies, such as cisco's application oriented networks, where services provide a higher-level of abstraction to traditional applications. in such cases, providing and consuming services and establishing a relationship between consumers (users of services) and producers (providers of services) are still challenging and vastly researched aspects. we define a service location planning problem (slp) that is novel in the approach it takes to match consumers to producers, such that the cost of providing services is minimized while taking into account quality of service constraints of throughput and delay. in previous work, we presented an integer linear programming (ilp) model to formulate the service location planning problem. in this paper, we present lagrangean relaxation of the model for large-scale networks. we use the approach of trick [3] to decrease computational overheads.
a chromosome image recognition method based on subregions. biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and dna sequencing. current full-custom design techniques for digital microfluidic biochips do not scale well for increasing levels of system integration. analogous to classical vlsi synthesis, a top-down system-level design automation approach can shorten the biochip design cycle and reduce human effort. we present here an overview of a system-level design methodology that includes architectural synthesis and physical design. the proposed design automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays, time-consuming hardware design, and costly testing and maintenance procedures.
tracking endocardial boundary and motion via graph cut distribution matching and multiple model filtering. the sloan digital sky survey (sdss) science database describes over 230 million objects and is over 1.6 tb in size. the sdss catalog archive server (cas) provides several levels of query interface to the sdss data via the skyserver website. most queries execute in seconds or minutes. however, some queries can take hours or days, either because they require non-index scans of the largest tables, or because they request very large result sets, or because they represent very complex aggregations of the data. these "monster queries" not only take a long time, they also affect response times for everyone else - one or more of them can clog the entire system. to ameliorate this problem, we developed a multiserver multiqueue batch job submission, execution, and tracking system for the cas called casjobs. the transfer of very large result sets from queries over the network is another serious problem. statistics suggested that much of this data transfer is unnecessary; users would prefer to store results locally in order to allow further joins and filtering. to allow local analysis, a system was developed that gives users their own personal databases (mydb) at the server side. users may transfer data to their mydb, and then perform further analysis before extracting it to their own machine. mydb tables also provide a convenient way to share results of queries with collaborators without downloading them. casjobs is built using soap xml web services and has been in operation since may 2004.
image classification using probability higher-order local auto-correlations. color as a distinct feature is widely used for object representation and tracking. however, color-based tracking is often influenced by clutter background and illumination variation. this paper presents a robust color-based tracking method, in which robust color feature is extracted for constructing the observation model under the modified particle filter tracking framework. the object is represented by its dominant color, and the weighted histogram with spatial information of the dominant color is used to optimize object models. in the particle filter framework, an extended iterated likelihood weighting scheme is employed to utilize more valuable particles. the experimental results show it is a real-time robust tracker, and it can obtain more than 30 fps with 2.4 g cpu and 512 mram.
learning bundle manifold by double neighborhood graphs. with the rapid development of the field of industrial process control and the fast popularization of embedded arm processor, it has been a trend that arm processor can substitute the single-chip to realize data acquisition and control. a new kind of remote i/o data acquisition system based on embedded arm platform has been researched and developed in this paper, whose hardware platform use 32-bit embedded arm microprocessor, and software platform use the uc/os-ii core of real-time multitask operating system which is open-source and can be grafted, cut out and solidified. this system can measure all kinds of electrical and thermal parameters such as voltage, current, thermocouple, rtd, and so on. the measured data can be displayed on lcd of the system, and at the same time can be transmitted through rs485 or ethernet network to remote das or dcs monitoring system by using modbus/rtu or modbus/tcp protocol. the system has the dual redundant network and long-distance communication function, which can ensure the disturb rejection capability and reliability of the communication network.