waashk/dblp huggingface dataset:
dicer: distributed and cost-effective redundancy for variation tolerance. increasingly prominent variational effects impose imminent threat to the progress of vlsi technology. this work explores redundancy, which is a well-known fault tolerance technique, for variation tolerance. it is observed that delay variability can be reduced by making redundant paths distributed or less correlated. based on this observation, a gate splitting methodology is proposed for achieving distributed redundancy. we show how to avoid short circuit and estimate delay in dual-driver nets which are caused by gate splitting. a spin-off gate placement heuristic is developed to minimize redundancy cost. monte carlo simulation results on benchmark circuits show that our method can improve timing yield from 59% to 72% with only 03% increase on cell area and 2.2% increase on wirelength on average.
a soft error rate analysis (sera) methodology. we present a soft error rate analysis (sera) methodology for combinational and memory circuits. sera is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. sera achieves five orders of magnitude speed-up over monte carlo based simulation approaches with less than 5% error. dependence of soft error rate (ser) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 /spl mu/m cmos process. results show that the ser of logic is a much stronger function of timing parameters than the supply voltage. also, an "ser peaking" phenomenon in multipliers is observed where the center bits have an ser that is in order of magnitude greater than that of lsbs and msbs.
dynamic range estimation for nonlinear systems. it has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or asics, and therefore the overall circuit area, delay and power consumption. while recent advances in analytical dynamic range estimation can deliver results accurate enough to account for both spatial and temporal correlation, the reported methods are only valid for linear systems. in this paper, we use a powerful mathematical tool, called polynomial chaos, which enables not only the orthogonal decomposition of random processes, but also the propagation of random processes through nonlinear systems with difficult constructs such as multiplications, divisions and conditionals. we show that when applied to interesting nonlinear applications such as adaptive filters, polynomial filters and rational filters, this method can produce complete, accurate statistics of each internal variable, thereby allowing the synthesis of bitwidth with the desired tradeoff between circuit performance and signal-to-noise ratio.
architectural partitioning of control memory for application specific programmable processors. abstract: because of programmability of application specific programmable processors (aspps), microcode-based control is effectively used to drive aspp datapaths for different applications. in aspps, each application needs a separate microprogram resulting in large microcode memory. this paper proposes a distributed microcode memory model in which only distinct microcodes are stored in each separate memory module to save memory area. a hierarchical clustering approach is also proposed for the design of this distributed microcode memory. experimental results indicate this approach is especially well suited for aspp microcode memory design because of the existence of repetitive microcodes across multiple behaviors.
bit-flipping bist. a scan-based bist scheme is presented which guarantees complete fault coverage with very low hardware overhead. a probabilistic analysis shows that the output of an lfsr which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. these modifications may be implemented by a bit-flipping function which has the lfsr-state as an input, and flips the value shifted into the scan path at certain times. a procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode bist scheme requires less hardware for complete fault coverage than all the other scan-based bist approaches published so far.
synthesis of reusable dsp cores based on multiple behaviors. design with cores has become popular recently because it can decrease the design time and ease the complexity of the design process. this paper presents a new method for the design of dsp cores based on multiple behaviors. this method uses redesign technique based on reallocation transformations to extract those rtl components in an initial rtl structure which are highly reusable and uses them to construct a dsp core. experimental results are provided to illustrate the high reusability of core, extracted from given behaviors, when it accommodates new behaviors.
using a distributed rectangle bin-packing approach for core-based soc test scheduling with power constraints. we present a new algorithm to co-optimize test scheduling andwrapper design under power constraints for core-based socs(system on chip). core testing solutions are generated as a set ofwrapper designs, each represented by a rectangle with width equalto the test time and height equal to the number of tam (testaccess mechanism) wires used. the test-scheduling problem withpower constraints is formulated as the distributed rectangle bin-packingproblem, which allows wrapper pins to be assigned to non-consecutivesoc pins. the generalized problem for multiple-tamsis solved by global optimization using evolutionary strategy and thesequence-pair representation. experiments on itcý02 benchmarksare very encouraging.
frequency domain analysis of switching noise on power supply network. in this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (p/g) networks of tree topologies. we model the p/g network as a linear time invariant (lti) pseudo-distributed rlc network and the gates (or cells) as time-varying current sources. voltage fluctuation caused by the switching events is calculated based on the effective impedances seen by the corresponding current sources and the spatial correlation between the nodes of the power network. superposition is applied to the lti system to obtain the overall noise spectrum at any node of the power supply network. inverse fast fourier transformation (ifft) is then performed on the frequency domain noise spectrum to obtain the time domain noise waveform. the proposed algorithm has a complexity of o(n2). experimental results show that our approach can produce accurate noise waveforms.
eco algorithms for removing overlaps between power rails and signal wires. design eco commonly happens in industry due to constraints or target changes from manufacturing, marketing, reliability, or performance. at each step, designers usually want to modify the existing solution incrementally and keep the design as close as possible to the existing one. in this paper, we address the pso (power rail - signal wire overlap) problem which solves overlaps between power rails and signal wires due to the changes in power rail design on the top layer of a multiple layer routing region. pso problems are frequently caused by changes from power delivery system or package design. the new routing solution satisfies the following constraints: 1) keep the routing of power rails in the new design unchanged. 2) only the routing of the top two layers is changed. 3) horizontal (vertical) signal wire segments on the top layer can only move up/down (left/right). at the same time, the new routing solution keeps the routing pattern unchanged. this requires: a) if one end point of a horizontal (vertical) wire segment on the top layer is a fixed pin, this segment can not move. b) if vertical (horizontal) projections of two horizontal (vertical) signal wire segments have overlaps, then the up/down (left/right) relationship should not be changed. c) if two horizontal (vertical) segments belonging to different nets are on the same track, their left/right (up/down) relationship should not be changed as long as the two segments still exist in the new solution. 4) for each signal wire segment, the deviation (i.e., the difference between its new position and the old one) should not exceed the user-defined allowable deviation bound. different bounds can be set on different segments. we propose two algorithms to solve the pso problem. both algorithms guarantee to find a feasible solution as long as one exists. one is faster, while the other makes effort to minimize the total deviation as well as the max deviation. according to time and quality requirements, users can choose an appropriate algorithm to solve the problem. for a set of industrial test circuits, we were able to remove all overlaps between power rails and signal wires with minimal wire deviation.
an algorithm for simultaneous pin assignment and routing. macro-block pin assignment and routing are important tasks in physical design planning. existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing, and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. none of the existing algorithms is "exact" in the sense that the algorithm may fail to route all nets even though a feasible solution exists. this remains to be true even if only 2-pin nets between two blocks are concerned. in this paper, we present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for 2-pin nets from one block (source block) to all other blocks. in addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost &alpha; &middot; w + &beta; &middot; v, where w is the total wirelength and v is the total number of vias. our algorithm has various applications: 1) it is suitable in eco (engineering change order) situations where a designer wants to incrementally modify the existing solution instead of redoing everything after a design change. 2) given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all blocks. the method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. experimental results demonstrate its efficiency and effectiveness.
timing-driven partitioning for two-phase domino and mixed static/domino implementations. domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. in this paper, the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided. in addition, an efficient static mapping algorithm is described.
bus-driven floorplanning. in this paper, we present an integrated approach to floorplanningand bus planning, i.e., bus-driven floorplanning (bdf). we are givena set of circuit blocks and the bus specifications (i.e., the net list ofblocks for the buses). a feasible bdf solution is a placement ofall circuit blocks such that each bus can be realized as a rectangularstrip (horizontal or vertical) going through all the blocks connectedby the bus. the objective is to determine a feasible bdf solutionthat minimizes floorplan area and total bus area. our approachis based upon the sequence-pair floorplan representation. after acareful analysis of the relationship between bus ordering and blockordering in the floorplan represented by a sequence pair, we derivefeasibility conditions on sequence pairs that give feasible bdfsolutions. experimental results demonstrate the efficiency and effectivenessof our algorithm.
robust and passive model order reduction for circuits containing susceptance elements. numerous approaches have been proposed to address the overwhelming modeling problems that result from the emergence of magnetic coupling as a dominant performance factor for icsand packaging. firstly, model order reduction (mor) methods have been extended to robustly capture very high frequency behaviors for large rlc systems via methods such as prima[8] with guaranteed passivity. in addition, new models of the magnetic couplings in terms of susceptance (inverse of inductance) have shown great promise for robust sparsification of otherwise intractable inductance coupling-matrix problems [3--5]. however, model order reduction via prima for circuits that include susceptance elements does not guarantee passivity. moreover, susceptance elements are incompatible with the path tracing algorithms that provide the fundamental runtime efficiency of rice [10]. in this paper a novel mor algorithm, smor, is proposed as an extension of enor [11] which exploits the matrix properties of susceptance-based circuits for runtime efficiency, and provides for a numerically stable, provably passive mor using a new or-thonormalization strategy.
an efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. this paper describes a new moment-generation algorithm for efficient simulation of linear subnetworks characterized by measured or tabulated data using moment-matching techniques. the subnetwork moments are computed by performing an integration in time-domain on the measured data. the proposed technique is more accurate as it relies on integration as compared to the previously published approaches which depend on the differentiation of measured data in frequency-domain for computation of moments. using the new moment-generation technique, the cfh (complex frequency hopping) algorithm has been extended to handle measured subnetworks. also a generalized stencil for measured data for inclusion in circuit simulators and to facilitate efficient moment-generation has been presented. examples and comparison with conventional simulations are provided. the method is accurate while it is faster than the conventional approach by 1 to 2 orders of magnitude.
implicit enumeration of strongly connected components. this paper presents a bdd-based implicit algorithm to compute all maximal strongly connected components of directed graphs. the algorithm iteratively applies reachability analysis and sequentially identifies sccs. experiments suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency-matrix of the graphs.
interconnect-aware high-level synthesis for low power. interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. in this work, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. we present a methodology to integrate interconnect power optimization into high-level synthesis. our binding algorithm not only reduces power consumption in functional units and registers in the resultant register-transfer level (rtl) architecture, but also optimizes interconnects for power. we take physical design information into account for this purpose. to estimate interconnect power consumption accurately for deep sub-micron (dsm) technologies, wire coupling capacitance is taken into consideration. we observed that there is significant spurious (i.e., unnecessary) switching activity in the interconnects and propose techniques to reduce it. compared to interconnect-unaware power-optimized circuits, our experimental results show that interconnect power can be reduced by 53.1% on an average, while reducing overall power by an average of 26.8% with 0.5% area overhead. compared to area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0% with 44.4% area overhead.
post global routing rlc crosstalk budgeting. existing layout optimization methods often assume a set of interconnects with given rlc crosstalk bounds in a routing region. rlc crosstalk bound partitioning is critical for effectively applying these methods at the full-chip level. in this paper, we develop an optimal crosstalk budgeting scheme based on linear programming (lp) formulation, and apply it to shield insertion and net ordering at the full-chip level. experiment results show that compared to the best alternative approach, the lp based method reduces the total routing area by up to 7.61% and also uses less runtime. to the best of our knowledge, this is the first in-depth work that studies the rlc crosstalk budgeting problem.
a twisted bundle layout structure for minimizing inductive coupling noise. in this paper, we propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. in this structure, we create several routing regions and re-order the routing of nets in each of these routing regions. the purpose is to create complementary and opposite current loops in the twisted-bundle layout structure, such that the magnetic fluxes arising from any signal net within a twisted group cancel each other in the current loop of a net of interest. the effectiveness of the twisted-bundle structure in minimizing coupling inductance has been verified by the application of fasthenry extraction on a 16-bit bus structure. we achieve about two orders of magnitude reduction in inductive coupling. spice simulations also show that the 16-bit twisted-bundle bus structure is able to maintain high signal integrity at high frequency of operation.
a trade-off oriented placement tool. high quality placement results are always produced at the cost ofsignificant runtimes. in this paper, we study the trade-offbetween the overall quality and the runtime for standard-cellplacement problems. we implemented and studied a class ofschemes to achieve the runtime vs. quality trade-off. wedeveloped a new trade-off oriented placement tool (toop)which is controlled by decision trees. toop can adjust itselfbased on user's requests and netlist properties. compared tocadence qplace, even the fastest mode of toop (lowest quality)can produce placements with similar or better layout. toop alsoshows much stronger ability to produce routable placement whencompared to capo.
on-chip interconnect modeling by wire duplication. in this paper, we present a novel wire duplication-based interconnect modeling technique. the proposed modeling technique exploits the sparsity of the l&minus;1 matrix, where l is the inductance matrix, and constructs a sparse and stable equivalent rlc circuit by windowing the original inductance matrix. the model avoids matrix inversions. most important, it is more accurate and more efficient than many existing techniques.
power estimation for cycle-accurate functional descriptions of hardware. cycle-accurate functional descriptions (cafd) are being widely adopted in integrated circuit (ic) design flows. power estimation can potentially benefit from the inherent increase in simulation efficiency of cycle-based functional simulation. currently, most approaches to hardware power estimation operate at the register-transfer level (rtl), or lower levels of design abstraction. attempts at power estimation for functional descriptions have suffered from poor accuracy because the design decisions performed during their synthesis lead to an unavoidable, large uncertainty in any power estimate that is based solely on the functional description. we propose a methodology for cafd power estimation that combines the accuracy achieved by power estimation at the structural rtl with the efficiency of cycle-accurate functional simulation. we achieve this goal by viewing a cafd as an abstraction of a specific, known rtl implementation that is synthesized from it. we identify correlations between a cafd and its rtl implementation, and "back-annotate" information into the cafd solely for the purpose of power estimation. the resulting rtl-aware cafd contains a layer of code that instantiates virtual placeholders for rtl components, and maps values of cafd variables into the rtl components' inputs/outputs, thus enabling efficient and accurate power estimation. power estimation is performed in our methodology by simply co-simulating the rtl-aware cafd with a simulatable power model library that contains power macro-models for each rtl component. we present techniques to further improve the speed of cafd power estimation, through the use of control state-based adaptive power sampling. we have implemented and evaluated the proposed techniques in the context of a commercial c-based hardware design flow. experiments with a number of large industrial designs (up to 1 million gates) demonstrate that the proposed methodology achieves accuracy very close to rtl power estimation with two-to-three orders of magnitude speedup in estimation times.
post routing performance optimization via multi-link insertion and non-uniform wiresizing. most existing performance-driven and clock routing algorithms construct optimal routing topology for each net individually without considering its routability on the chip, so they can not guarantee performance after all nets are routed. this paper proposes a new approach for post routing performance optimization via multi-link insertion and non-uniform wiresizing, which improves the performance of a net topology obtained from a global routing solution. unlike previous approaches, it can achieve reduction in both maximum delay and skew to satisfy user specified constraints and minimizes the routing resource consumed. during optimization, the topology of the net is kept routable. experiments show that link insertion and wiresizing can improve net performance significantly, and among all approaches, multi-link insertion and wiresizing achieves the best performance and area efficiency.
fast algorithms for ir drop analysis in large power grid. due to the extremely large size of power grids, ir drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. although ir drop analysis can be naturally formulated as the problem of solving a linear system, the system is too large to be solved by existing linear solvers. in this paper, we present two iterative algorithms based on node-by-node traversals and row-by-row traversals of the power grid, respectively. our algorithms are extremely fast and guarantee convergence to the exact solutions. in fact, they can be considered as efficient implementations of the classical successive over relaxation iterative method for solving linear systems. our methods take full advantage of the special structure of the power grid. experimental results show that our algorithms out-perform the random-walk-based algorithm which is the best known method today. for a 16-million node problem, our row-based algorithm took 26.47 minutes while the random-walk-based algorithm took 19.6 hours. our row-based algorithm produced an exact solution while the random walk produced a solution with maximum error of 5.7 mv.