waashk/dblp huggingface dataset:
a delay fault model for at-speed fault simulation and test generation. we describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. at-speed test application allows a circuit to be tested under its normal operation conditions. however, fault simulation and test generation for the existing fault models become significantly more complex due to the need to handle faulty signal-transitions that span multiple clock cycles. the proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur. fault detection potentially occurs when an unspecified value reaches a primary output. due to the uncertainty that an unspecified value propagated to a primary output will be different from the fault free value, an inherent requirement in this model is that a fault would be potentially detected multiple times in order to increase the likelihood of detection. experimental results demonstrate that the model behaves as expected in terms of fault coverage and numbers of detections of target faults. a variation of an n-detection test generation procedure for stuck-at faults is used for generating test sequences under this model.
a stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. in this work we describe a stochastic integral equation method for computing the mean value and the variance of capacitance of interconnects with random surface roughness. an ensemble average green's function is combined with a matrix neumann expansion to compute nominal capacitance and its variance. this method avoids the time-consuming monte carlo simulations and the discretization of rough surfaces. numerical experiments show that the results of the new method agree very well with monte carlo simulation results.
smt(): a step toward scalability in system verification. we describe a sat-based decision method for the underlying logic in many formal verification problems; i.e. the counter arithmetic logic with lambda expressions and uninterpreted functions (clu). this logic is well suited for equivalence checking of two versions of a hardware design or the input and output of a compiler and has been recently utilized in several model checkers. our method follows the general satisfiability modulo theories or smt(t) framework and combines a dpll-style sat solver with two theory solvers; one specific to equality and the other to separation inequality atoms within clu. by adopting a combined implication scheme, we coordinate the efforts among theory solvers, and by efficiently processing uninterpreted functions involved in conflicts, we considerably improve the effectiveness of sat learning and backtracking routines. finally, we empirically demonstrate the effectiveness of our smt(clu) procedure and compare its performance to recent solvers on a wide range of hardware verification benchmarks.
a simultaneous bus orientation and bused pin flipping algorithm. the orientation of a bus is defined as the direction from the least significant bit (lsb) to the most significant bit (msb). bused pin flipping is a property that allows several bused pins to flip without changing the system functionality. in this paper a simultaneous bus orientation and bused pin flipping algorithm is presented. the algorithm can be integrated into a bus-centric floorplanner targeting bus-rich designs such as microprocessors. experimental results show that a floorplanner enhanced by the algorithm produces high quality floorplans in terms of bus routing.
joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable parameters. the two levels of tuning operate within a single variability budget, and because their effectiveness depends on the magnitude and the spatial structure of variability their joint co-optimization is required. in this paper we develop a formal optimization algorithm for such co-optimization and link it to the control and measurement overhead via the formal notions of measurement and control complexity. we describe an optimization strategy that unifies design-time gate-level sizing and post-silicon adaptation using adaptive body bias at the chip level. the statistical formulation utilizes adjustable robust linear programming to derive the optimal policy for assigning body bias once the uncertain variables, such as gate length and threshold voltage, are known. computational tractability is achieved by restricting optimal body bias selection policy to be an affine function of uncertain variables. we demonstrate good run-time and show that 5-35% savings in leakage power across the benchmark circuits are possible. dependence of results on measurement and control complexity is studied and points of diminishing returns for both metrics are identified.
yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling. automated circuit optimization is an important component of complex analog integrated circuit design. today's analog designs must be optimized not only for nominal performance but also for robustness in order to maintain a reasonable yield with highly scaled vlsi technologies. the complex nature of analog/mixed-signal systems, however, makes this yield-aware analog circuit optimization extremely difficult and costly. in this paper, we adopt a geostatistics motivated approach (i.e. kriging model) for efficient extraction of yield-aware pareto front performance models for analog circuits. an iterative search based optimization approach is proposed to efficiently seek optimal performance tradeoffs under yield constraints in high-dimensional design parameter and process variation spaces. our experiments confirm that the generated yield-aware pareto fronts are accurate and the optimization procedure is very efficient. the latter is achieved by the well controlled iterative update scheme in the presented techniques which avoids an excessive number of time consuming transistor-level simulations.
dynamic response time optimization for sdf graphs. synchronous data flow (sdf) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. existing scheduling methods are mainly static approaches that assume full knowledge of the environment, e.g. data arrival times. in a growing number of practical cases like internet multimedia applications there exists only partial knowledge of the environment, e.g. average data rates. here, only dynamic scheduling can yield optimal results. in this paper, we propose a new dynamic scheduling method that minimizes the maximal response time of the system. it is a generalization of a deadline revision method to allow treatment of data-dependent tasks using edf scheduling. the applicability and benefit of the new approach is shown using a real-world example.
using cad to shape experiments in molecular qca. this paper examines how circuits and systems made from molecular qca devices might function. our design constrain are "chemically reasonable" in that we consider the characteristics and dimensions of devices and scaffoldings (circuit boards to attach devices to) that have actually been fabricated (currently in isolation). we will show that not only is the work presented here a necessary first step for any work in qca cad, but also that by considering issues related to design can actually help shap shape experiments in the physical sciences for emerging, nano-scale devices. our work shows that circuits, scaffoldings, substrates, and devices must all be considered simultaneously. otherwise, there is a very real possibility that the devices and scaffoldings that are eventually manufactured will result in devices that only work in isolation. this work is especially timely as experimentalists are currently working to merge the different experimental tracks - i.e. to selectively place a qca device.
a case for cmos/nano co-design. the challenge of extending moore's law past the physical and economic barriers of present semiconductor technologies calls for novel nanoelectronic solutions. circuits composed of mixed silicon semiconductors and nanoelectronics can provide a means for gradually switching technology paradigms. we suggest a design methodology to accompany this concept. furthermore, we explore design tradeoffs for a nanoscale crossbar technology that supports cmos/nano co-design.
fast and accurate transaction level models using result oriented modeling. effcient communication modeling is a critical task in soc design and exploration. in particular, fast and accurate communication is needed to predict the performance of a system. recently, transaction level modeling (tlm) is used to speedup communication simulation at the cost of accuracy. this paper proposes a novel modeling technique called result oriented modeling (rom) which removes the accuracy drawback of tlm. using rom, models yield the same speed as their tlm counterparts, yet still are 100% accurate in timing. rom utilizes the fact that internal states in the communication channel are not observable by the caller. hence, rom omits the internal states entirely and optimistically predicts the end result. retroactively, the outcome is checked and, if necessary, corrective measures are taken to maintain the accuracy of the model. in this paper, we apply rom to the amba ahb bus architecture. our experimental results show that rom exhibits the same high simulation performance as traditional tlm, yet it retains the same accuracy as the bus functional model. thus, the proposed rom approach eliminates the speed/accuracy tradeoff exhibited by traditional tlm.
hybrid spectral/iterative partitioning. although spectral partitioning has been an active area of research, there are still many limitations which prevent its widespread use. these limitations include the inability to work directly with a hypergraph model, great difficulty in specifying design constraints, and the inability to specify arbitrary cost functions. none of those limitations are present in the commonly-used kernighan-lin/fiduccia-mattheyses (klfm) style iterative improvement heuristics. our current work focuses on developing a new multi-way, hybrid spectral/iterative hypergraph partitioning algorithm which combines the strengths of spectral partitioners and iterative improvement algorithms to create a new class of partitioners. we show how spectral information (the eigenvectors of a graph) can be incorporated into an iterative partitioning framework. we use spectral information to generate initial partitions, influence the selection of iterative improvement moves, and break out of local minima which may trap klfm improvement algorithms. our 3-way and 4-way partitioning results are better than the best published results, demonstrating the effectiveness of our new hybrid method.
fullwave volumetric maxwell solver using conduction modes. we present a gridless method for solving the interior problem for a set of conductors in an homogeneous dielectric, at sufficiently high frequencies, valid for conductor lengths that are not small compared to the minimum wavelength, and transverse dimensions that are large compared to the skin depth. for ic applications, we cover the regime 10--100 ghz and the inclusion of all relevant wire dimensions. we decompose the electromagnetic-field in terms of the eigenfunctions of the helmholtz equation for three dimensional current distributions inside the conductors. using a relatively small number of modes per conductor we obtain results comparable to filament or mesh decompositions using a much larger dimensionality for the resulting linear problem. the method is an extension to the fullwave regime of a method introduced in [1].
multi-level spectral hypergraph partitioning with arbitrary vertex sizes. this paper presents a new spectral partitioning formulation which directly incorporates vertex size information. the formulation results in a generalized eigenvalue problem, and this problem is reduced to the standard eigenvalue problem. experimental results show that incorporating vertex sizes into the eigenvalue calculation produces results that are 50% better than the standard formulation in terms of scaled ratio-cut cost, even when a kernighan-lin style iterative improvement algorithm taking into vertex sizes is applied as a post-processing step. the standard spectral partitioning formulation is impractical for use in multi-level partitioning schemes since it requires a contraction method that produces nearly-equal-size clusters. to evaluate the new method for use in multi-level partitioning, we combine the partitioner with a multi-level bottom-up clustering algorithm and iterative refinement. experimental results show that our new spectral algorithm is more effective than the standard spectral formulation and other partitioners in the multi-level partitioning of hypergraphs.
application-specific customization of parameterized fpga soft-core processors. soft-core microprocessors mapped onto field-programmable gate arrays (fpgas) represent an increasingly common embedded software implementation option. modern fpga soft-cores are parameterized to support application-specific customization, wherein pre-defined units, such as a multiplication unit or floating-point unit, may be included in the microprocessor architecture to speed up software execution at the expense of increased size. we introduce a methodology for fast applicationspecific customization of a parameterized fpga soft core, using synthesis and execution to obtain size and performance data in order to create a tool that can be used across a variety of tool platforms and fpga devices. as synthesizing a soft core takes tens of minutes, developing heuristics that execute in an acceptable time of an hour or two, yet find near-optimal results, is a challenge. we consider two approaches, one using a traditional cad approach that does an initial characterization using synthesis to create an abstract problem model and then explores the solution space using a knapsack algorithm, and the other using a synthesisin-the-loop exploration approach. we compare approaches for a variety of design constraints, on 11 eembc benchmarks, using an actual xilinx soft-core processor, and for two different commercial xilinx fpga devices. our results show that the approaches can generate a customized configuration exhibiting roughly 2x speedups over a base soft core, reaching within 4% of optimal in about 1.5 hours, including complete synthesis of the soft-core onto the fpga, compared to over 11 hours for exhaustive search. our results also show that including synthesisin-the-loop, compared to a traditional cad approach, improved speedups by an average of 20% when size constraints were tight. the approaches may also be applicable to soft-core processors targeted to asics in addition to fpgas.
an efficient method for statistical circuit simulation. the dynamic behavior of a vlsi circuit can be described by a system of differential-algebraic equations. when some circuit elements are affected by process variations, the dynamic behavior of the circuit will deviate from its nominal trajectory. monte-carlo-type random sampling methods are widely used to estimate the trajectory deviation. however they can be quite time-consuming when the dimension of the parameter space is large. this paper offers an alternative solution by casting the problem into the theoretic frame work of non-linear non-gaussian filtering. to estimate the mean and variance of the time-dependent circuit trajectory, we develop a method based on unscented transformation, which is an efficient bayesian analysis sampling technique. theoretically the method has linear runtime complexity. experimental results show that compared to traditional monte-carlo methods, the new method can achieve over 10x speedup with less than 2% error.
noise propagation and failure criteria for vlsi designs. noise analysis has become a critical concern in advanced chip designs. traditional methods suffer from two common issues. first, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. since this ignores the non-linear behavior of the driver gate the noise that develops on a net can be significantly underestimated. we therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation. after the propagated and injected noise are correctly combined on a victim net, it is necessary to determine if the noise can result in a functional failure. this is the second issue that we discuss in this paper. traditionally, noise failure criteria have been based on unity gain points of the dc or ac transfer curves. however, we will show that for digital designs, these approaches can result in a pessimistic analysis in some cases, while in other cases, they allow circuit operation that is extremely close to regions that are unstable and do not allow sufficient margin for error in the analysis. in this paper, we compare the effectiveness of the discussed noise failure criteria and also present a propagation based method, which is intended to overcome these drawbacks. the proposed methods were implemented in a noise analysis tool and we demonstrate results on industrial circuits.
online task-scheduling for fault-tolerant low-energy real-time systems. in this paper we investigate fault tolerance and dynamic voltage scaling (dvs) in hard real time systems. we present two low-complexity fault-aware scheduling algorithms that combine feasibility analysis of rate monotonic algorithm (rma) schedules and dvs-based frequency scaling using exact characterization of rma algorithm. these algorithms lay the foundation for highly efficient online schemes that minimize energy consumption by adapting dvs policies to runtime behavior of tasks and fault occurrences without violating the offline feasibility analysis. simulation results demonstrate energy savings of up to 60% over low-energy offline scheduling algorithms [22].
test of future system-on-chips. spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a single chip. being able to rapidly develop, manufacture, test, debug and verify complex socs is crucial for the continued success of the electronics industry. this growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. however, to make its production practical and cost effective, the industry road maps identify a number of major hurdles to be overcome. the key hurdle is related to test and diagnosis. this embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them. these solutions are meant to ensure that test and diagnosis contribute to the overall growth of the soc industry and do not slow it down. this embedded tutorial in addition presents the state-of-the-art in system-level integration and addresses the strategies and current industrial practices in the test of system-on-chip. it discusses the requirements for test reuse in hierarchical design, such as embedded test strategies for individual cores, test access mechanisms, optimizing test resource partitioning, and embedded test management and integration at the system-on-chip level. processor cores being one of the most common cores embedded in a soc, issues related to self-testing embedded processor cores are addressed. future research challenges and opportunities are discussed in enabling testing of future socs which use deep submicron technologies.
system-wide energy minimization for real-time tasks: lower bound and approximation. we present a dynamic voltage scaling (dvs) technique that minimizes system-wide energy consumption for both periodic and sporadic tasks. it is known that a system consists of processors and a number of other components. energy-aware processors can be run in different speed levels; components like memory and i/o subsystems and network interface cards can be in a standby state when they are active, but idle. processor energy optimization solutions are not necessarily efficient from the perspective of systems. current system-wide energy optimization studies are often limited to periodic tasks with heuristics in getting approximated solutions. in this paper, we develop an exact dynamic programming algorithm for periodic tasks on processors with practical discrete speed levels. the algorithm determines the lower bound of energy expenditure in pseudopolynomial time. an approximation algorithm is proposed to provide performance guarantee with a given bound in polynomial running time. because of their time efficiency, both the optimization and approximation algorithms can be adapted for online scheduling of sporadic tasks with irregular task releases. we prove that system-wide energy optimization for sporadic tasks is np-hard in the strong sense. we develop (pseudo-) polynomial-time solutions by exploiting its inherent properties.
using functional independence conditions to optimize the performance of latency-insensitive systems. in latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamically control their operations. in particular, a shell stalls a pearl whenever new valid data are not available on its input channels. we study how functional independence conditions (fic) can be applied to the performance optimization of a latency-insensitive system by avoiding unnecessary stalling of their pearls. we present a novel circuit design of a generic shell template that can exploit fics. we describe an automatic procedure for the logic synthesis of a fic-shell instance that is only based on the analysis of the logic structure of its corresponding pearl and does not require any input from the designers. we implemented the proposed technique within the logic synthesis tool abc and we use it to complete various experiments that demonstrate its performance benefits and limited overhead. in particular, we completed the semi-custom design of a system-on-chip (soc), an ultra-wideband baseband transmitter, using a state-of-the-art 90nm technology process. to the best of our knowledge this represents the first report on the complete latency-insensitive design of a real-world soc.
process and environmental variation impacts on asic timing. with each semiconductor process node, the impacts on performance of environmental and semiconductor process variations become a larger portion of the cycle time of the product. simple guard-banding for these effects leads to increased product development times and uncompetitive products. in addition, traditional static timing methodologies are unable to cope with the large number of permutations of process, voltage, and temperature corners created by these independent sources of variation. in this paper we will discuss the sources of variation; by introducing the concepts of systematic inter-die variation, systematic intra-die variation and intra-die random variation. we will show that by treating these forms of variations differently, we can achieve design closure with less guard-banding than traditional methods.