waashk/dblp huggingface dataset:
on bounding the delay of a critical path. process variations cause different behavior of timing-dependent effects across different chips. in this work, we analyze one example of timing-dependent effects, cross-coupling capacitance, and the complex problem space created by considering coupling and process variations together. the delay of a critical path under these conditions is difficult to bound for design and test. we develop a methodology that analyzes this complex space by decomposing the problem space along three dimensions: the aggressor space, test space, and sample space. for design, we utilize an obdd-based approach to prune the aggressor space based on logical constraints, which can be combined with a worst-case timing window simulator to prune based on both logical and timing constraints. after pruning, the reduced aggressor space can be used to derive a more accurate timing bound. solving the problems in the test and sample spaces is postponed to the post-silicon stage, where we propose a test selection methodology for bounding the delay of every sample. this methodology is based on probability density estimation and has a tradeoff between the number of tests to apply and the tightness of the delay bound obtained. experimental results based on benchmark examples are presented to show the effectiveness of the proposed methodology.
tip-opc: a new topological invariant paradigm for pixel based optical proximity correction. as the 193nm lithography is likely to be used for 45mm and even 32nm processes, much more stringent requirement will be posed on optical proximity correction (opc) technologies. currently, there are two opc approaches --- the model-based opc (mb-opc) and the inverse lithography technology (ilt). mb-opc generates masks which is less complex compared with il.t. but il.t produces much better results than mb-opc in terms of contour fidelity because ilt is a pixel based method. observing that mb-opc preserves the mask shape topologies which leads to a lower mask complexity, we combine the strengths of both methods --- the topology invariant property and the pixel based mask representation. to the best of our knowledge, it is the first time that this topological invariant pixel based opc (tip-opc) paradigm is proposed, which fills the critical hole of the opc landscape and potentially has many new applications. our technical novelty includes the lithography friendly mask topological invariant operations, the efficient fast fourier transform based cost function sensitivity computation and the tip-opc algorithm. the experimental results show that tip-opc can achieve much better post opc contours compared with mb-opc while maintaining the mask shape topologies.
automation in mixed-signal design: challenges and solutions in the wake of the nano era. the use of cmos nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. rising design complexities, tightening time-to-market constraints, leakage power, increasing technology tolerances, and reducing supply voltages are key challenges that designers face. novel types of devices, new process materials and new reliability issues are next on the horizon. we discuss new design methodologies and eda tools that are being or need to be developed to address the problems of designing such mixed-signal integrated systems.
yield prediction for 3d capacitive interconnections. capacitive interconnections are very promising structures for high-speed and low-power signaling in 3d packages. since the performance of ac links, in terms of band-width and bit-error-rate (ber), depends on assembly and synchronization accuracy we performed a statistical analysis of assembly procedures and communication circuits. in this paper we present a yield prediction methodology for 3d capacitive links: starting from the analysis of communication circuits and ber measurements, we analyze stacking variability in order to predict reliability and performance. the proposed parametric yield analysis is demonstrated on a test-case, with constrained inter-electrode coupling and operating frequency.
a high-quality mixed-size analytical placer considering preplaced blocks and density constraints. in addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. we propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by naylor et al. [20] and the multilevel framework. to handle preplaced blocks, we use a two-stage smoothing technique, gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement. the density is controlled by white-space re-allocation using partitioning and cut-line shifting during global placement and cell sliding during detailed placement. we further use the conjugate gradient method with dynamic step-size control to speed up the global placement and macro shifting to and better macro positions. experimental results show that our placer obtains the best published results.
a linear-time approach for static timing analysis covering all process corners. manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (sta) at every corner. this approach is becoming too expensive due to the exponential increase in the number of corners with modern processes. as an alternative, we propose a linear-time approach for sta which covers all process corners in a single pass. our technique assumes a linear dependence of delay on process parameters and provides tight bounds on the worst-case circuit delay. it exhibits high accuracy (within 1-3%) in practice and, if the circuit has m gates and n relevant process parameters, the complexity of the algorithm is o(mn).
enhanced error vector magnitude (evm) measurements for testing wlan transceivers. as wireless lan devices become more prevalent in the consumer electronics market, there is an ever increasing pressure to reduce their overall cost. the test cost of such devices is an appreciable percentage of the overall cost, which typically results from the high number of specifications, the high number of distinct test set-ups and equipment pieces that need to be used, and the high cost of each test set-up. in this paper, we investigate the versatility of evm measurements to test the variable-envelope wlan (wireless local area networks) receiver and transmitter characteristics. the goal is to optimize evm test parameters (input data and test limits) and to reduce the number of specification measurements that require high test times and/or expensive test equipment. our analysis shows that enhanced evm measurements(optimized data sequence and limits, use of rms, scale, and phase error vector values) in conjunction with a set of simple path measurements (input-output impedances) can provide the desired fault coverage while eliminating lengthy spectrum mask and noise figure tests
a fast block structure preserving model order reduction for inverse inductance circuits. most existing rcl-1 circuit reductions stamp inverse inductance l-1 elements by a second-order nodal analysis (na). the na formulation uses nodal voltage variables and describes inductance by nodal susceptance. this leads to a singular matrix stamping in general. we introduce a new circuit stamping for rcl-1 circuits using branch vector potentials. the new circuit stamping results in a first-order circuit matrix that is semi-positive definite and non-singular. we call this as vectorpotential based nodal analysis (vna). it enables an accurate and passive reduction. in addition, to preserve the structure of state matrices such as sparsity and hierarchy, we represent the flat vna matrix in a bordered-block diagonal (bbd) form. this enables us to build and simulate the macromodel efficiently. in experiments performed on several test cases, our method achieves up to 15x faster modeling building time, up to 33x faster simulation time, and as much as 67x smaller waveform error compared to sapor, the best existing second order rcl-1 reduction method.
state re-encoding for peak current minimization. in a synchronous finite state machine (fsm), huge current peaks are often observed at the moment of state transition. previous low power state encoding algorithms focus on the reduction of switching activities of state registers (i.e., state bits). however, even though the switching state registers are the same, different combinations of switching directions still result in different peak currents. based on that observation, in this paper, we propose the first approach to re-encode an fsm by considering the switching directions of state registers in order to minimize the peak current caused by the state transition. experimental data consistently show that the peak current is reduced with no penalty.
post-routing redundant via insertion and line end extension with via density consideration. redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. however, if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design. in this paper, we first study the problem of redundant via insertion, and present two methods to accelerate a state-of-the-art approach (which is based on a maximum independent set (mis) formulation) to solve it. we then consider the problem of simultaneous redundant via insertion and line end extension. we formulate the problem as a maximum weighted independent set (mwis) problem and modify the accelerated mis-based approach to solve it. lastly, we investigate the problem of simultaneous redundant via insertion and line end extension subject to the maximum via density rule, and present a two-stage approach for it. in the first stage, we ignore the maximum via density rule, and enhance the mwis-based approach to find the set of regions which violate the maximum via density rule after performing simultaneous redundant via insertion and line end extension. in the second stage, excess redundant vias are removed from those violating regions such that after the removal, the maximum via density rule is met while the total amount of redundant vias removed is minimized. this density-aware redundant via removal problem is formulated as a set of zero-one integer linear programming (0-1 ilp) problems each of which can be solved independently without sacrificing the optimality. the superiorities of our approaches are all demonstrated through promising experimental results.
energy management for real-time embedded systems with reliability requirements. with the continued scaling of cmos technologies and reduced design margins, the reliability concerns induced by transient faults have become prominent. moreover, the popular energy management technique dynamic voltage and frequency scaling (dvfs) has been shown to have direct and negative effects on reliability. in this work, for a set of real-time tasks, we focus on the slack allocation problem to minimize their energy consumption while preserving the overall system reliability. building on our previous findings for a single real-time application where a recovery task was used to preserve reliability, we identify the problem of reliability-aware energy management for multiple tasks as np-hard and propose two polynomial-time heuristic schemes. we also investigate the effects of on-chip/off-chip workload decomposition on energy management, by considering a generalized power model. simulation results show that ordinary energy management schemes could lead to drastically decreased system reliability, while the proposed reliability-aware heuristic schemes are able to preserve the system reliability and obtain significant energy savings at the same time.
a gate delay model focusing on current fluctuation over wide-range of process and environmental variability. this paper proposes a gate delay model that is suitable for timing analysis considering wide-range process and environmental variability. the proposed model focuses on current variation and its impact on delay is considered by replacing output load. the proposed model is applicable for large variability with current model constructed by dc analysis whose cost is small. the proposed model can also be used both in statistical static timing analysis and in conventional corner-based static timing analysis. experimental results in a 90nm technology show that the gate delays of inverter, nand and nor are accurately estimated under gate length, threshold voltage, supply voltage and temperature fluctuation. we also verify that the proposed model can cope with slow input transition and rc output load. we demonstrate applicability to multiple-stage path delay and flip-flop delay, and show an application of sensitivity calculation for statistical timing analysis.
a timing dependent power estimation framework considering coupling. in this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. we show that relative switching activities and times of coupled nets significantly affect dynamic power consumption, and neither should be ignored during power estimation. to capture the timing dependence, an approach to efficient representation and propagation of switching-window distributions through a circuit, considering coupling induced delay variations, is developed. based on the propagated switchingwindow distributions, power consumption in charging or discharging coupling capacitances is calculated, and accounted for in the total power. experimental results for the iscas'85 benchmarks demonstrate that ignoring the impact of timing dependent coupling on power can cause up to 59% error in coupling power estimation (up to 25% error in total power estimation).
nanowire addressing with randomized-contact decoders. methods for assembling crossbars from nanowires (nws) have been designed and implemented. methods for controlling individual nws within a crossbar have also been proposed, but implementation remains a challenge. a nw decoder is a device that controls many nws with, a much smaller number of lithographically produced mesoscale wires (mws). unlike traditional demultiplexers, all proposed nw decoders are assembled stochastically. in a randomized-contact decoder (rcd) [11], for example, field-effect transistors are randomly created at about half of the nw/mw junctions. in this paper, we tightly bound the number of mws required to produce a correctly functioning rcd with high probability. we show that the number of mws is logarithmic in the number of nws, even when errors occur. we also analyze the overhead associated with controlling a stochastically assembled decoder. as we explain, lithographically-produced control circuitry must store information regarding which mws control which nws. this requires more area than the mws themselves, but has received little attention elsewhere.
a unified non-rectangular device and circuit simulation model for timing and power. for 65nm and below devices, even after optical proximity correction (opc), the gate may still be non-rectangular. there are several limited works on the device and circuit characterizations for the post-opc non-ideal-shape wafer images, with significant impacts on timing and power. most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. in this paper, we propose a unified post-litho device characterization model and circuit simulation for timing and power. to our best knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. based on this method, the parameter extraction is also included in the model which was omitted by previous works. a post-litho model card is proposed for circuit simulation to combine these two techniques. our experimental results validate the new model.
improvements to combinational equivalence checking. the paper explores several ways to improve the speed and capacity of combinational equivalence checking based on boolean satisfiability (sat). state-of-the-art methods use simulation and bdd/sat sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run sat on the output (i.e. proving equivalence of the output to constant 0). this paper improves on this method by (a) using more intelligent simulation, (b) using cnf-based sat with circuit-based decision heuristics, and (c) interleaving sat with low-effort logic synthesis. experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. in several cases, the new solver succeeded in solving previously unsolved problems.
application-independent defect-tolerant crossbar nano-architectures. defect tolerance is a major issue in nano computing. in this paper, an application-independent defect tolerant scheme for reconfigurable crossbar nano-architectures is presented. architectural features are developed to reliably connect local defect-free subsets of crossbars in order to generate a defect-free architecture. it is also shown how to further reduce the area overhead associated with this flow by relaxing some constraints on the defect-free subsets. experimental results show more than 9x reduction in the area overhead without any negative impact on the usability of modified defect-free subsets.
analog placement with symmetry and other placement constraints. in order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. this paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. the problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. the maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. we have compared our method with the most updated results on this problem [2] when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. we will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising.
cmos-mems integration: why, how and what? cmos-mems integration can improve the performance of the mems (micro-electromechanical systems), allows for smaller packages and leads to a lower packaging and instrumentation cost. as argued in this article, processing mems above cmos is the most promising approach for cmos-mems integration, but it limits the thermal budget for mems processing. poly-sige provides the desired material properties for mems applications at significantly lower temperatures compared to poly-si. a case study of a cmos-integrated sige gyroscope will be presented.
performances improvement of fpga using novel multilevel hierarchical interconnection structure. this paper presents a new multilevel hierarchical fpga (mfpga) architecture that unifies two unidirectional programmable networks: a predictible downward network based on the butterfly-fat-tree topology, and an upward network using hierarchy. studies based on the rent's rule show that wiring and switch requirements in the mfpga grow slower than in traditional topologies. new tools are developed to place and route several benchmark circuits on this architecture. experimental results based on the mcnc benchmarks show that mfpga can implement circuits with an average gain of 40% in total area compared with mesh architecture.
soft error derating computation in sequential circuits. soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. accurate estimation of soft error rate (ser), the probability of system failure due to soft errors, is a key factor in design of cost-effective soft error resilient systems. we present a very fast and accurate approach based on enhanced static timing analysis and signal probabilities to estimate the probability of latching an incorrect value in the system bistables (timing derating). experimental results and comparison with fault injections using timing accurate monte-carlo simulations show that the accuracy of our approach is within 1% while orders of magnitude faster.
robust system level design with analog platforms. an approach to robust system level mixed signal design is presented based on analog platforms. the bottom-up characterization phase of platform components provides accurate performance models that export architectural constraints to the system level. from the one side, performance models can be affected by residual errors and usually do not consider process variations and modeling uncertainties. conversely, behavioral models cannot match accurate circuit level simulations, so that during the mapping (exploration) process circuit configurations difficult to be realized may be obtained. we propose a methodology that extends techniques from optimization and design centering to system level analog design exploiting general, implicit architectural constraints to control the robustness of the solution. the approach allows quantitative extension of robust techniques to hierarchical designs. its effectiveness is illustrated with the design of a pipeline a/d converter and a umts receiver front-end.
cost-aware synthesis of asynchronous circuits based on partial acknowledgement. designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor cad support in asynchronous world. a straightforward way is to structurally map the gates in a synchronous netlist to their functionally equivalent modules which use delay-insensitive codes. different trade-offs exist in previous methods between the overheads of the implementations and their robustness. the aim of this paper is to optimise the area of asynchronous circuits using partial acknowledgement concept. we employ this concept in two design flows, which are implemented in a software tool to evaluate the efficiency of the method. the benchmark results show the average reduction in area by 28% and in the number of inter-functional module wires that require timing verification by 67%, compared to ncl-x.
a novel framework for faster-than-at-speed delay test considering ir-drop effects. faster-than-at-speed test have been proposed to detect small delay defects. while these techniques increase the test frequency to reduce the positive slack of the path, they exacerbate the already well known issue of ir-drop during test. this may result in false identification of good chips to be faulty due to ir-drop rather than small delay defects. we present a case study of ir-drop effects due to faster-than-at-speed test. we propose a novel framework for pattern generation/application using any commercial no-timing atpg tool, to screen small delay defects and a technique to determine the optimal test frequency considering both performance degradation due to ir-drop effects and positive slack.