waashk/dblp huggingface dataset:
how to bridge the abstraction gap in system level modeling and design. as more and more processors and subsystems are integrated in a single system, the verification bottleneck is driving designers away from rtl and rtl-like strategies for verification and design to higher abstraction levels. increasing system complexity at the other hand requires much faster simulation and analysis tools. this is leading to new standards and tools around transaction level modeling. languages such as systemc and systemverilog are rich in behavioral and structural constructs which enable modeling designs at different levels of abstraction without imposing a top-down or bottom-up design flow. in fact, most design flows are iterative and modules at different levels of abstractions have to be considered. a more abstract model is very useful to increase simulation speed and to improve formal verification. systemc and systemverilog stress the importance of verification support for complex socs including improvement for hardware verification as well as for the verification of hardware dependent software. in todays design flows the software development can often only start after the hardware is available. this causes unacceptable delays for the software development. the idea of transaction level modeling (tlm) is to provide in an early phase of the hardware development transaction level models of the hardware. based on these tlms a fast enough simulation environment is the basis for the development of hardware and hardware dependent software. the presumption is to run these transaction level models at several tens or some hundreds of thousand transactions per second which should be fast enough for system level modeling and verification.
ficom: a framework for incremental consistency maintenance in multi-representation, structural vlsi databases. a framework for vlsi design databases which supports fine-grained incremental consistency maintenance between different views of a design is presented. the framework provides for structural views of a design such as logic or circuit schematic, symbolic layout, and physical layout, and supports representation of geometric design rule constraints between design objects. a prototype interactive design system which provides a user interface to three structural view types (gate and circuit schematics, and symbolic layouts) is presented. features of the prototype system are automatic propagation of incremental operations between views and high-speed online generation and evaluation of geometric design rule constraints
high-level synthesis: an essential ingredient for designing complex asics. it is common wisdom that synthesizing hardware from higher-level descriptions than verilog incurs a performance penalty. the case study here shows that this need not be the case. if the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written verilog rtl. differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. this exploration is not practical without quality synthesis from higher-level languages.
design and cad challenges in sub-90nm cmos technologies. this paper discusses design challenges of scaled cmos circuits insub-90nm technologies for high-performance digital applications.to continue scaling of the cmos devices deep into sub-90nm tech-nologies,fully depleted soi, strained-si on sige, finfets withdouble gate, and even further, three-dimensional circuits will be uti-lizedto design high-performance circuits. we will discuss uniquedesign aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process vari-ations.as the scaling approaches various physical limits, new soidesign issues such as vt modulation due to leakage, low-voltageimpact ionization, and higher v{t,lin} to maintain adequate v{t,sat},continue to surface.with an eye towards the future, design andcad issues related to sub-65nm device structures such as doublegate finfet will be discussed.
system level design and verification using a synchronous language. synchronous languages such as esterel, lustre, signal, andothers were originally developed for safety-critical embedded software and compiled into c. they have recently been extended to hardware with new language features and compilers to rtl. contrary to traditional hdl languages (verilog, vhdl) and recent system-level languages (systemc, system verilog), they have well defined formal semantics,which facilitate bug avoidance using correct-by-constructioncompilation and verification techniques.the tutorial will demonstrate what the synchronous language offers for the modeling, design, analysis and implementation of systems that comprise hardware and software.it will be based on esterel. esterel models have proved tobe useful for rapid design space exploration and verificationat system level, without resorting to detailed implementation and slow bit-level event-based simulation. we show how to model control-dominated ip blocks at a higher levelof abstraction and how to use the target c code or rtl inconjunction with other system-level tools. case studies include examples of design space exploration by synthesizing equivalent hardware or software from the same esterel description, with formal verification of safety properties such as bus protocol conformance. we conclude with a review of future research directions.
efficient breadth-first manipulation of binary decision diagrams. we propose new techniques for efficient breadth-first iterative manipulation of robdds. breadth-first iterative robdd manipulation can potentially reduce the total elapsed time by multiple orders of magnitude compared to the conventional depth-first recursive algorithms when the memory requirement exceeds the available physical memory. however, the breadth-first manipulation algorithms proposed so far have had a large enough overhead associated with them to make them impractical. our techniques are geared towards minimizing the overhead without sacrificing the speed up potential. experimental results indicate considerable success in that regard.
the disjunctive decomposition of logic functions. we present an algorithm for extracting a disjunctive decomposition from the bdd representation of a logic function f. the output of the algorithm is a multiple-level netlist exposing the hierarchical decomposition structure of the function. the algorithm has theoretical quadratic complexity in the size of the input bdd. experimentally, we were able to decompose most synthesis benchmarks in less than one second of cpu time, and to report on the decomposability of several complex iscas combinational benchmarks. we found the final netlist to be often close to the output of more complex dedicated optimization tools.
exploiting multi-cycle false paths in the performance optimization of sequential circuits. it is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. this observation offers techniques to improve the performance of sequential logic circuits. a preliminary implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a very modest area overhead
directional bias and non-uniformity in fpga global routing architectures. this paper investigates the effect of the prefabricated routing track distribution on the area-efficiency of fpgas. the first question we address is whether horizontal and vertical channels should contain the same number of tracks (capacity), or if there is a density advantage with a directional bias. secondly, should the channels have a uniform capacity, or is there an advantage when capacities vary from channel to channel? the key result is that the most area-efficient global routing architecture is one with uniform (or very nearly uniform) channel capacities across the entire chip in both the horizontal and vertical directions. several non-uniform and directionally-biased architectures, however, are fairly area-efficient provided that appropriate choices are made for the pin positions on the logic blocks and the logic array aspect ratio.
formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. traditional single-attribute optimization problems force a designer to choose either power or delay as the objective function and minimize it with constraints on other attributes. however this approach does not provide the designer with enough freedom to incorporate tradeoffs between various attributes such as leakage and delay. in this paper we present a utility theoretic approach for the joint optimization of leakage and delay. this provides a general framework for quantifying a designer's preferences for tradeoffs between leakage and delay. we show that energy-delay product (edp) is an element of a larger class of such utility functions. the resulting multi-attribute optimization problem is modeled as a convex gate sizing problem that is solved using geometric programming. the resulting solution is a design point that is optimal with respect to the designer's preferences.
using complete-1-distinguishability for fsm equivalence checking. this article introduces the notion of a complete-1-distinguishability (c-1-d) property for simplifying equivalence checking of finite state machines (fsms). when a specification machine has the c-1-d property, the traversal of the product machine can be eliminated. instead, a much simpler check suffices. the check consists of first obtaining a 1-equivalence mapping between the individually reachable states of the specification and the implementation machines, and then checking that it is a bisimulation relation. the c-1-d property can be used directly for specification machines on which it naturally holds---a condition that has not been exploited thus far in fsm verification. we also show how this property can be enforced on an arbitrary fsm by exposing some of its latch outputs as pseudo-primary outputs during synthesis and verification. in this sense, our synthesis/verification methodology provides another point in the trade-off curve between constraints-on-synthesis versus complexity-of-verification. practical experiences with this methodology have resulted in success with several examples for which it is not possible to complete verification using existing implicit state space traversal techniques.
estimation of signal arrival times in the presence of delay noise. delay due to capacitive coupling of interconnects has become an important reliability issue in the design of nanometer circuits. in this paper we present a probabilistic approach towards analyzing the impact of capacitive coupling noise on signal delay. the variation in the delay is due to the variation in the relative arrival times of the aggressors and the victim. we derive expressions for the moments of the victim voltage in the presence of noise. from these we compute estimates of the earliest and latest possible arrival times of the victim. we compare the analytical results with monte carlo simulations using spice. even though the analytical calculations are 200 times faster than the monte carlo simulations, the differences in the estimates of the mean and standard deviation of the arrival time is no more than 2.8%. in addition, the width of the timing intervals using the proposed approach is reduced by as much as 48% with a confidence level of 0.984. that is 98.4% of the monte carlo simulations result in an arrival time that falls within the derived interval which is 48% shorter.
fast functional simulation using branching programs. abstract: this paper addresses the problem of speeding up functional (delay-independent) logic simulation for synchronous digital systems. the problem needs very little new motivation-cycle-based functional simulation is the largest consumer of computing cycles in system design. most existing simulators for this task can he classified as being either event driven or levelized compiled-code, with the levelized compiled code simulators generally being considered faster for this task. an alternative technique, based on evaluation using branching programs, was suggested about a decade ago in the context of switch level functional simulation. however, this had very limited application since it could not handle the large circuits encountered in practice. this paper resurrects the basic idea present this technique and provides significant modifications that enable its application to contemporary industrial strength circuits. we present experimental results that demonstrate up to a 10x speedup over levelized compiled code simulation for a large suite of benchmark circuits as well as for industrial examples with over 40.000 gates.
au: timing analysis under uncertainty. due to excessive reduction in the gate length, dopant concentrationsand the oxide thickness, even the slightest of variations inthese quantities can result in significant variations in the performanceof a device. this has resulted in a need for efficient andaccurate techniques for performing statistical analysis of circuits.in this paper we propose a methodology based on bayesian networksfor computing the exact probability distribution of the delayof a circuit. in case of large circuits where it is not possible tocompute the exact distribution, we propose methods to reduce theproblem size and get a tight lower bound on the exact distribution.
analytical approach to custom datapath design. this paper addresses the problem of layout design automation of datapath cells. we present a novel approach to transistor placement problem for custom datapath designs and demonstrate that it can be applied to practical designs. our approach is based on an analytical model which employs a mixed integer linear programming (milp) technique. the novelty and originality of the method is the efficient management of the complexity of the underlying mathematical model. our prototype tool automatically handles transistor merging, folding, and intra-cell component sharing.
provably correct high-level timing analysis without path sensitization. this paper addresses the problem of true delay estimation during high level design. the existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive.we show that the paths in the implementation of a behavioral specification can be partitioned into two sets, sp and up. while the paths in sp can affect the delay of the circuit, the paths in up cannot. consequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in sp, eliminating the need for the computationally intensive process of path sensitization. experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation becomes computationally infeasible. the high-level delay estimates are verified by comparing with delay estimates obtained by gate-level timing analysis on the actual implementation.
an optimal chip compaction method based on shortest path algorithm with automatic jog insertion. a one-dimensional compaction method for layout patterns including rectilinear macrocells on any number of layers is presented. the algorithm is based on the shortest path search on a constraint graph. it generates an optimal layout pattern in the smallest area by introducing effective jogs in o (n log n) time, where n is the number of line segments of the input pattern and inserted jogs. the jogs are inserted by means of an enhanced plane-sweep method developed in the field of computational geometry. performance data of an experimental program show its efficiency
effects of global interconnect optimizations on performance estimation of deep submicron design. in this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. in doing so, we develop a new system-performance simulation model as a set of studies within the marco gsrc technology extrapolation (gtx) system. we model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. we demonstrate, for example, that optimal wire sizing models need to consider inductive effects -- and that use of more accurate {-1,3} worst-case capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional {0,2} bounds. we also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.
circuit power estimation using pattern recognition techniques. this paper proposes a circuit power estimation method using bayesian inference and neural networks. based on statistical distribution of circuit leakage power and switching energy, the entire state and transition space of a circuit are classified using neural networks into a limited few classes that represent different power consumption average values. this technique enables efficient table-lookup of circuit power of the entire state and transition space. theoretical basis of bayesian inference, feature extraction for neural networks of circuit leakage power and switching energy are discussed. experiments on a wide range of circuit topologies demonstrated the robustness of the proposed method for estimating circuit leakage power of all possible states and switching energy of all possible transitions.
sisma: a statistical simulator for mismatch analysis of mos ics. this paper presents a simulator for the statistical analysis of mos integrated circuits a ected by mismatch e ect. the tool is based on a rigorous formulation of circuit equations including random current sources to take into account technological tolerances. the simulator requires a simulation time of several orders of magnitude lower than that required by montecarlo analysis, while ensuring a good accuracy.
parameterized rtl power models for combinational soft macros. we propose a new rtl power macromodel that is suitable for re-configurable, synthesizable soft-macros. the model is parameterized with respect to the input data size (i.e., bit-width), and can be automatically scaled with respect to different technology libraries and/or synthesis options. scalability is obtained through a single additional characterizations run, and does not require the disclosure of any intellectual property. the model is derived from empirical analysis of the sensitivity of power on input statistics, input data size and technology. the experiments prove that, with limited approximation, it is possible to de-couple the effects on power of these three factors. the proposed solution is innovative, since no previous macromodel supports automatic technology scaling, and yields estimation errors within 15%.
a multi-harmonic probe technique for computing oscillator steady states. we present a novel method for finding periodic steady states of general classes of oscillators robustly. the new method, which we term the multi-harmonic probe (mhp) technique, generalizes the well-known technique of augmenting harmonic balance (hb) for oscillators using an external probe. by using non-sinusoidal periodic probes, mhp enhances the applicability of the standard probe method (which uses purely sinusoidal probes) to broader classes of oscillators. we thus obtain a general and robust method for the periodic steady state of any kind of oscillator. results on lc and ring oscillator circuits are presented that testify to the efficacy of our approach.
parameterized model order reduction of nonlinear dynamical systems. in this paper we present a parameterized reduction technique for non-linear systems. our approach combines an existing non-parameterized trajectory piecewise linear method for non-linear systems, with an existing moment matching parameterized technique for linear systems. results and comparisons are presented for two examples: an analog non-linear circuit, and a mem switch.
fault dictionary compaction by output sequence removal. fault dictionary compaction has been accomplished in the past by removing responses on individual output pins for specific test vectors. in contrast to the previous work, we present techniques for eliminating entire sequences of outputs and for efficiently storing the remaining output sequences. experimental results on the iscas 85 and iscas 89 benchmark circuits show that the sizes of dictionaries proposed are substantially smaller than the full fault dictionary, while the dictionaries retain most or all of the diagnostic capability of the full fault dictionary.
integrated fault diagnosis targeting reduced simulation. integrated fault diagnosis techniques attempt to overcome the limitations associated with static (pre-computed information usage) and dynamic (run-time analysis) techniques by using a limited amount of pre-computed information and coupling this with simulation at diagnosis time, for rapid fault diagnosis. a significant problem with previous integrated techniques is that the pre-computed information is not targeted specifically toward reducing the run-time costs. we present a new approach to integrated fault diagnosis, by specifically creating the precomputed information to provide later savings in the simulation costs at diagnosis time. experimental results on the iscas 85 and iscas 89 circuits illustrate the savings achieved by this technique.
a statistical study of the effectiveness of bist jitter measurement techniques. this paper describes a statistical study of the effectiveness of state-of-the-art built-in-self-test (bist) jitter measurement techniques. many bist solutions under-sample the signal under test, estimating the jitter in a system based upon a subset of the total number of clock edges. in this paper, we explore how under-sampling affects the accuracy of jitter measurements, and demonstrate a technique for estimating the actual jitter using a gaussian distribution estimation. our theoretical results were verified through a simulation study and comparison to experimental data collected from a 400 mhz phase-locked loop supplied by an industry sponsor.
extension of the asymptotic waveform evaluation technique with the method of characteristics. a problem inherent in methods for simulating distributed elements with the asymptotic waveform evaluation (awe) technique is that they use complex exponentials to approximate pure delays in the time responses of transmission lines. the aproximation can lead to spurious ringing in the simulation results. this problem can be overcome within the context of a spice-based simulator. the generalized method of characteristics is used to derive an equivalent circuit model for a system of coupled lines. this allows the pure delay to be factored out; awe can then be used to approximate the characteristic admittance, as well as the propagation functions of the lines. the awe approximation can be simulated efficiently within a modified version of spice. examples are presented to demonstrate that this technique is both accurate and faster than other methods