waashk/dblp huggingface dataset:
an experiment to improve operand addressing. mcode is a high-level language, stack machine designed to support strongly-typed, pascal-based languages with a variety of data types in a modular programming environment. the instruction set, constructed for efficiency and extensibility, is based on an analysis of 120,000 lines of pascal programs. the design was compared for efficiency with the instruction sets of the digital equipment pdp-11 and vax by examining the generated code from the same compiler for all three machines. in addition, the original design choices were tested by analyzing the generated code from 19,000 lines of starmod programs. as a result of this iterative experiment, we have summarized our observations in an efficient reorganization of the vax's addressing modes.
an out-of-order execution technique for runtime binary translators. a dynamic translator emulates an instruction set architccturc by translating source instructions to native code during execution. on statically-scheduled hardware, higher performance can potentially be achieved by reordering the translated instructions; however, this is a challenging transformation if the source architecture supports precise exception semantics, and the user-level program is allowed to register exception handlers. this paper presents a software technique which allows a translator to achieve the out-of-order execution of user-level programs, while preserving all sequential semantics. the design combines a translator, an interpreter, and a set of operating system services. using the proposed techniques, a dynamic translator can optimistically reorder instructions and speculate them across branch boundaries. if a mispeculated operation causes an exception, the recovery algorithm reverts the application state to a safe point, then retranslates the faulty code without reordering to disable further exceptions.
compiler chip: a hardware implementation of compiler. in this paper we discuss about another approch: compiler chip, which is a vlsi implementation of a compiler. constructing a compiler by a few vlsi chip, the computer manufacturer can deliver compilers by sets of vlsi chips, and these chips are installed in a intelligent terminal in order to remove the compilation from the tasks which are processed in the mainframe.
cool-mem: combining statically speculative memory accessing with selective address translation for energy efficiency. this paper presents cool-mem, a family of memory system architectures that integrate conventional memory system mechanisms, energy-aware address translation, and compiler-enabled cache disambiguation techniques, to reduce energy consumption in general purpose architectures. it combines statically speculative cache access modes, a dynamic cam based tag-cache used as backup for statically mispredicted accesses, various conventional multi-level associative cache organizations, embedded protection checking along all cache access mechanisms, as well as architectural organizations to reduce the power consumed by address translation in virtual memory. because it is based on speculative static information, the approach removes the burden of provable correctness in compiler analysis passes that extract static information. this makes cool-mem applicable for large and complex applications, without having any limitations due to complexity issues in the compiler passes or the presence of precompiled static libraries. based on extensive evaluation, for both spec2000 and mediabench applications, 12% to 20% total energy savings are obtained in the processor, with performance ranging from 1.2% degradation to 8% improvement, for the applications studied.
dynamic memory disambiguation using the memory conflict buffer. to exploit instruction level parallelism, compilers for vliw and superscalar processors often employ static code scheduling. however, the available code reordering may be severely restricted due to ambiguous dependences between memory instructions. this paper introduces a simple hardware mechanism, referred to as the memory conflict buffer, which facilitates static code scheduling in the presence of memory store/load dependences. correct program execution is ensured by the memory conflict buffer and repair code provided by the compiler. with this addition, significant speedup over an aggressive code scheduling model can be achieved for both non-numerical and numerical programs.
the dragon processor. the xerox parc dragon is a vlsi research computer that uses several techniques to achieve dense code and fast procedure calls in a system that can support multiple processors on a central high bandwidth memory bus.
an experimental coprocessor for implementing persistant objects on an ibm 4381. in this paper we describe an experimental coprocessor for an ibm 4381 that is designed to facilitate the exploration of persistent objects.
architecture and design of alphaserver gs320. this paper describes the architecture and implementation of the alphaserver gs320, a cache-coherent non-uniform memory access multiprocessor developed at compaq. the alphaserver gs320 architecture is specifically targeted at medium-scale multiprocessing with 32 to 64 processors. each node in the design consists of four alpha 21264 processors, up to 32gb of coherent memory, and an aggressive io subsystem. the current implementation supports up to 8 such nodes for a total of 32 processors. while snoopy-based designs have been stretched to medium-scale multiprocessors by some vendors, providing sufficient snoop bandwidth remains a major challenge especially in systems with aggressive processors. at the same time, directory protocols targeted at larger scale designs lead to a number of inherent inefficiencies relative to snoopy designs. a key goal of the alphaserver gs320 architecture has been to achieve the best-of-both-worlds, partly by exploiting the bounded scale of the target systems.this paper focuses on the unique design features used in the alphaserver gs320 to efficiently implement coherence and consistency. the guiding principle for our directory-based protocol is to address correctness issues related to rare protocol races without burdening the common transaction flows. our protocol exhibits lower occupancy and lower message counts compared to previous designs, and provides more efficient handling of 3-hop transactions. furthermore, our design naturally lends itself to elegant solutions for deadlock, livelock, starvation, and fairness. the alphaserver gs320 architecture also incorporates a couple of innovative techniques that extend previous approaches for efficiently implementing memory consistency models. these techniques allow us to generate commit events (which are used for ordering purposes) well in advance of formulating the reply to a transaction. furthermore, the separation of the commit event allows time-critical replies to bypass inbound requests without violating ordering properties. even though our design specifically targets medium-scale servers, many of the same techniques can be applied to larger-scale directory-based and smaller-scale snoopy-based designs. finally, we evaluate the performance impact of some of the above optimizations and present a few competitive benchmark results.
vlsi assist for a multiprocessor. multiprocessors have long been of interest to computer community. they provide the potential for accelerating applications through parallelism and increased throughput for large multi-user system. three factors have limited the commercial success of multiprocessor systems; entry cost, range of performance, and ease of application. advances in very large scale integration (vlsi) and in computer aided design (cad) have removed these limitations, making possible a new class of multiprocessor systems based on vlsi components. a set of requirements for building an efficient shared multiprocessor system are discussed, including: low-level mutual exclusion, interrupt distribution, inter-processor signaling, process dispatching, caching, and system configuration. a system that meets these requirements is described and evaluated.
precise miss analysis for program transformations with caches of arbitrary associativity. analyzing and optimizing program memory performance is a pressing problem in high-performance computer architectures. currently, software solutions addressing the processor-memory performance gap include compiler-or programmer-applied optimizations like data structure padding, matrix blocking, and other program transformations. compiler optimization can be effective, but the lack of precise analysis and optimization frameworks makes it impossible to confidently make optimal, rather than heuristic-based, program transformations. imprecision is most problematic in situations where hard-to-predict cache conflicts foil heuristic approaches. furthermore, the lack of a general framework for compiler memory performance analysis makes it impossible to understand the combined effects of several program transformations.the cache miss equation (cme) framework discussed in this paper addresses these issues. we express memory reference and cache conflict behavior in terms of sets of equations. the mathematical precision of cmes allows us to find true optimal solutions for transformations like blocking or padding. the generality of cmes also allows us to reason about interactions between transformations applied in concert. unlike our prior work, this framework applies to caches of arbitrary associativity. this paper also demonstrates the utility of cmes by presenting precise algorithms for intra-variable padding, inter-variable padding, and selecting tile sizes. our experiences with cmes implemented in the suif system show that they are a unifying mathematical framework offering the generality and precision imperative for compiler optimizations on current high-performance architectures.
the operating system and language support features of the bellmac-32 microprocessor. the bellmac-32 microprocessor is a 32-bit microprocessor, implemented with cmos technology, designed to support operating system functions and high level languages efficiently. the architecture was designed with the following objectives in mind: &bull; high performance. &bull; enhanced operating system support capabilities. &bull; high level language support. &bull; high reliability, availability and maintainability.
hoard: a scalable memory allocator for multithreaded applications. parallel, multithreaded programs such as web servers, database managers, news servers, and scientific applications are becoming increasingly prevalent. for these c and c++ applications, the memory allocator is often a bottleneck that severely limits program performance and scalability on multiprocessor systems. previous allocators suffer from problems that include poor performance and scalability, and heap organizations that introduce false sharing. worse, many allocators exhibit a "blowup" in memory consumption when confronted with a producer-consumer pattern of object allocation and freeing. this blowup can increase memory consumption by a factor of p (the number of processors) or lead to unbounded memory consumption. such pathological behavior can cause premature program termination by exhausting all available swap space. this paper introduces hoard, a fast, highly scalable allocator that avoids false sharing and blowup. hoard is the first allocator to simultaneously solve the above problems. hoard combines one global heap and p per-processor heaps with a novel discipline that provably bounds blowup and has near zero synchronization costs in the common case. our results on eleven programs demonstrate that hoard yields low average fragmentation and improves overall program performance over the standard solaris allocator by up to a factor of 60 on 14 processors, and up to a factor of 18 over the next best allocator we tested.
a cost-effective, high-bandwidth storage architecture. this paper describes the network-attached secure disk (nasd) storage architecture, prototype implementations oj nasd drives, array management for our architecture, and three, filesystems built on our prototype. nasd provides scalable storage bandwidth without the cost of servers used primarily, for transferring data from peripheral networks (e.g. scsi) to client networks (e.g. ethernet). increasing datuset sizes, new attachment technologies, the convergence of peripheral and interprocessor switched networks, and the increased availability of on-drive transistors motivate and enable this new architecture. nasd is based on four main principles: direct transfer to clients, secure interfaces via cryptographic support, asynchronous non-critical-path oversight, and variably-sized data objects. measurements of our prototype system show that these services can be cost-effectively integrated into a next generation disk drive ask. end-to-end measurements of our prototype drive andfilesysterns suggest that nasd cun support conventional distributed filesystems without performance degradation. more importantly, we show scaluble bandwidth for nasd-specialized filesystems. using a parallel data mining application, nasd drives deliver u linear scaling of 6.2 mb/s per clientdrive pair, tested with up to eight pairs in our lab.
avoiding conflict misses dynamically in large direct-mapped caches. this paper describes a method for improving the performance of a large direct-mapped cache by reducing the number of conflict misses. our solution consists of two components: an inexpensive hardware device called a cache miss lookaside (cml) buffer that detects conflicts by recording and summarizing a history of cache misses, and a software policy within the operating system's virtual memory system that removes conflicts by dynamically remapping pages whenever large numbers of conflict misses are detected. using trace-driven simulation of applications and the operating system, we show that a cml buffer enables a large direct-mapped cache to perform nearly as well as a two-way set associative cache of equivalent size and speed, although with lower hardware cost and complexity.
heat-and-run: leveraging smt and cmp to manage power density through the operating system. power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of supply voltage and thermal ability of packages to dissipate heat. power density is characterized by localized chip hot spots that can reach critical temperatures and cause failure. previous architectural approaches to power density have used global clock gating, fetch toggling, dynamic frequency scaling, or resource duplication to either prevent heating or relieve overheated resources in a superscalar processor. previous approaches also evaluate design technologies where power density is not a major problem and most applications do not overheat the processor. future processors, however, are likely to be chip multiprocessors (cmps) with simultaneously-multithreaded (smt) cores. smt cmps pose unique challenges and opportunities for power density. smt and cmp increase throughput and thus on-chip heat, but also provide natural granularities for managing power-density. this paper is the first work to leverage smt and cmp to address power density. we propose heat-and-run smt thread assignment to increase processor-resource utilization before cooling becomes necessary by co-scheduling threads that use complimentary resources. we propose heat-and-run cmp thread migration to migrate threads away from overheated cores and assign them to free smt contexts on alternate cores, leveraging availability of smt contexts on alternate cmp cores to maintain throughput while allowing overheated cores to cool. we show that our proposal has an average of 9% and up to 34% higher throughput than a previous superscalar technique running the same number of threads.
fast mutual exclusion for uniprocessors. in this paper we describe restartable atomic sequences, an optimistic mechanism for implementing simple atomic operations (such as test-and-set) on a uniprocessor. a thread that is suspended within a restartable atomic sequence is resumed by the operating system at the beginning of the sequence, rather than at the point of suspension. this guarantees that the thread eventually executes the sequence atomically. a restartable atomic sequence has significantly less overhead than other software-based synchronization mechanisms, such as kernel emulation or software reservation. consequently, it is an attractive alternative for use on uniprocessors that do no support atomic operations. even on processors that do support atomic operations in hardware, restartable atomic sequences can have lower overhead. we describe different implementations of restartable atomic sequences for the mach 3.0 and taos operating systems. these systems' thread management packages rely on atomic operations to implement higher-level mutual exclusion facilities. we show that improving the performance of low-level atomic operations, and therefore mutual exclusion mechanisms, improves application performance.
coherency for multiprocessor virtual address caches. a multiprocessor cache memory system is described that supplies data to the processor based on virtual addresses, but maintains consistency in the main memory, both across caches and across virtual address spaces. pages in the same or different address spaces may be mapped to share a single physical page. the same hardware is used for maintaining consistency both among caches and among virtual addresses. three different notions of a cache "block" are defined: (1) the unit for transferring data to/from main storage, (2) the unit over which tag information is maintained, and (3) the unit over which consistency is maintained. the relation among these block sizes is explored, and it is shown that they can be optimized independently. it is shown that the use of large address blocks results in low overhead for the virtual address cache.
access normalization: loop restructuring for numa compilers. in scalable parallel machines, processors can make local memory accesses much faster than they can make remote memory accesses. in addition, when a number of remote accesses must be made, it is usually more efficient to use block transfers of data rather than to use many small messages. to run well on such machines, software must exploit these features. we believe it is too onerous for a programmer to do this by hand, so we have been exploring the use of restructuring compiler tecnology for this purpose. in this paper, we start with a language like fortran-d with user-specified data distribution and develop a systematic loop transformation strategy called access normalization that restructures loop nests to exploit locality and block transfers. we demonstrate the power of our techniques using routines from the blas (basic linear algebra subprograms) library. an important feature of our approach is that we model loop transformations using invertible matrices and integer lattice theory, thereby generalizing banerjee's framework of unimodular matrices [5].
evaluating design alternatives for reliable communication on high-speed networks. we systematically evaluate the performance of five implementations of a single, user-level communication interface. each implementation makes different architectural assumptions about the reliability of the network hardware and the capabilities of the network interface. the implementations differ accordingly in their division of protocol tasks between host software, network-interface firmware, and network hardware. using microbenchmarks, parallel-programming systems, and parallel applications, we assess the performance impact of different protocol decompositions. we show how moving protocol tasks to a relatively slow network interface yields both performance advantages and disadvantages, depending on the characteristics of the application and the underlying parallel-programming system. in particular, we show that a communication system that assumes highly reliable network hardware and that uses network-interface support to process multicast traffic performs best for all applications.
a stateless, content-directed data prefetching mechanism. although central processor speeds continues to improve, improvements in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. to counter this loss of performance, numerous data and instruction prefetch mechanisms have been proposed. recently, several proposals have posited a memory-side prefetcher; typically, these prefetchers involve a distinct processor that executes a program slice that would effectively prefetch data needed by the primary program. alternative designs embody large state tables that learn the miss reference behavior of the processor and attempt to prefetch likely misses.this paper proposes content-directed data prefetching, a data prefetching architecture that exploits the memory allocation used by operating systems and runtime systems to improve the performance of pointer-intensive applications constructed using modern language systems. this technique is modeled after conservative garbage collection, and prefetches "likely" virtual addresses observed in memory references. this prefetching mechanism uses the underlying data of the application, and provides an 11.3% speedup using no additional processor state. by adding less than &frac12;% space overhead to the second level cache, performance can be further increased to 12.6% across a range of "real world" applications.
envy: a non-volatile, main memory storage system. this paper describes the architecture of envy, a large non-volatile main memory storage system built primarily with flash memory. envy presents its storage space as a linear, memory mapped array rather than as an emulated disk in order to provide an efficient and easy to use software interface.flash memories provide persistent storage with solid-state memory access times at a lower cost than other solid-state technologies. however, they have a number of drawbacks. flash chips are write-once, bulk-erase devices whose contents cannot be updated in-place. they also suffer from slow program times and a limit on the number of program/erase cycles. envy uses a copy-on-write scheme, page remapping, a small amount of battery backed sram, and high bandwidth parallel data transfers to provide low latency, in-place update semantics. a cleaning algorithm optimized for large flash arrays is used to reclaim space. the algorithm is designed to evenly wear the array, thereby extending its lifetime.software simulations of a 2 gigabyte envy system show that it can support i/o rates corresponding to approximately 30,000 transactions per second on the tpc-a database benchmark. despite the added work done to overcome the deficiencies associated with flash memories, average latencies to the storage system are as low as 180ns for reads and 200ns for writes. the estimated lifetime of this type of storage system is in the 10 year range when exposed to a workload of 10,000 transactions per second.