waashk/dblp huggingface dataset:
architectural support for the efficient generation of code for horizontal architectures. horizontal architectures, such as the cdc advanced flexible processor [i] and the fps api20-b [2}, consist of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. such architectures have been developed to perform high speed scientific computations at a modest cost: figure 1 displays those characteristics of horizontal architectures that are germane to the issues discussed in this paper. the simultaneous requirements of high performance and low cost lead to an architecture consisting of multiple pipelined processing elements (pes) such as adders and multipliers, a memory (which for scheduling purposes may be viewed as yet another pe with two operations: a read and a write), and an interconnect which ties them all together. the interconnect allows the result of one operation to be directly routed to another pe as one of the inputs for an operation that is to be performed there. the required memory bandwidth is reduced since temporary values need not be written to and read from the memory. the final aspect of horizontal processors that is of interest is that their program memories emit wide instructions which synchronously specify the actions of the multiple and possibly dissimilar pes. the program memory is sequenced by a conventional sequencer that assumes sequential flow of control unless a branch is explicitly specified. as a consequence of the simplicity of such an architecture, it is inexpensive relative to the potential performance of the multiple pipelined pes. however, if this potential performance is to be realized, the multiple resources of a horizontal processor must be scheduled effectively. the scheduling task for conventional horizontal processors is quite complex and the construction of highly optimizing compilers for them is a difficult and expensiw3 project. the polycyclic architecture [3- 6] is a horizontal architecture with architectural support for the scheduling task. the cause of the complexity involved in scheduling conventional horizontal processors and the manner in which the polycyclic architecture addresses this issue are outlined in this paper.
an analysis of operating system behavior on a simultaneous multithreaded architecture. this paper presents the first analysis of operating system execution on a simultaneous multithreaded (smt) processor. while smt has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. however, many of the applications most amenable to multithreading technologies spend a significant fraction of their time in kernel code. a full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.to carry out this study, we (1) modified the digital unix 4.0d operating system to run on an smt cpu, and (2) integrated our smt alpha instruction set simulator into the simos simulator to provide an execution environment. for an os-intensive workload, we ran the multithreaded apache web server on an 8-context smt. we compared apache's user- and kernel-mode behavior to a standard multiprogrammed specint workload, and compared the smt processor to an out-of-order superscalar running both workloads. overall, our results demonstrate the microarchitectural impact of an os-intensive workload on an smt processor and provide insight into the os demands of the apache web server. the synergy between the smt processor and web and os software produced a greater throughput gain over superscalar execution than seen on any previously examined workloads, including commercial databases and explicitly parallel programs.
the performance advantages of integrating block data trabsfer in cache-coherent multiprocessors. integrating support for block data transfer has become an important emphasis in recent cache-coherent shared address space multiprocessors. this paper examines the potential performance benefits of adding this support. a set of ambitious hardware mechanisms is used to study performance gains in five important scientific computations that appear to be good candidates for using block transfer. our conclusion is that the benefits of block transfer are not substantial for hardware cache-coherent multiprocessors. the main reasons for this are (i) the relatively modest fraction of time applications spend in communication amenable to block transfer, (ii) the difficulty of finding enough independent computation to overlap with the communication latency that remains after block transfer, and (iii) long cache lines often capture many of the benefits of block transfer in efficient cache-coherent machines. in the cases where block transfer improves performance, prefetching can often provide comparable, if not superior, performance benefits. we also examine the impact of varying important communication parameters and processor speed on the effectiveness of block transfer, and comment on useful features that a block transfer facility should support for real applications.
hoist: a system for automatically deriving static analyzers for embedded systems. embedded software must meet conflicting requirements such as be-ing highly reliable, running on resource-constrained platforms, and being developed rapidly. static program analysis can help meet all of these goals. people developing analyzers for embedded object code face a difficult problem: writing an abstract version of each instruction in the target architecture(s). this is currently done by hand, resulting in abstract operations that are both buggy and im-precise. we have developed hoist: a novel system that solves these problems by automatically constructing abstract operations using a microprocessor (or simulator) as its own specification. with almost no input from a human, hoist generates a collection of c func-tions that are ready to be linked into an abstract interpreter. we demonstrate that hoist generates abstract operations that are cor-rect, having been extensively tested, sufficiently fast, and substan-tially more precise than manually written abstract operations. hoist is currently limited to eight-bit machines due to costs exponential in the word size of the target architecture. it is essential to be able to analyze software running on these small processors: they are important and ubiquitous, with many embedded and safety-critical systems being based on them.
improving the accuracy of static branch prediction using branch correlation. recent work in history-based branch prediction uses novel hardware structures to capture branch correlation and increase branch prediction accuracy. we present a profile-based code transformation that exploits branch correlation to improve the accuracy of static branch prediction schemes. our general method encodes branch history information in the program counter through the duplication and placement of program basic blocks. for correlation histories of eight branches, our experimental results achieve up to a 14.7% improvement in prediction accuracy over conventional profile-based prediction without any increase in the dynamic instruction count of our benchmark applications. in the majority of these applications, code duplication increases code size by less than 30%. for the few applications with code segments that exhibit exponential branching paths and no branch correlation, simple compile-time heuristics can eliminate these branches as code-transformation candidates.
os and compiler considerations in the design of the ia-64 architecture. increasing demands for processor performance have outstripped the pace of process and frequency improvements, pushing designers to find ways of increasing the amount of work that can be processed in parallel. traditional risc architectures use hardware approaches to obtain more instruction-level parallelism, with the compiler and the operating system (os) having only indirect visibility into the mechanisms used.the ia-64 architecture [14] was specifically designed to enable systems which create and exploit high levels of instruction-level parallelism by explicitly encoding a program's parallelism in the instruction set [25]. this paper provides a qualitative summary of the ia-64 architecture features that support control and data speculation, and register stacking. the paper focusses on the functional synergy between these architectural elements (rather than their individual performance merits), and emphasizes how they were designed for cooperation between processor hardware, compilers and the os.
ecosystem: managing energy as a first class operating system resource. energy consumption has recently been widely recognized as a major challenge of computer systems design. this paper explores how to support energy as a first-class operating system resource. energy, because of its global system nature, presents challenges beyond those of conventional resource management. to meet these challenges we propose the currentcy model that unifies energy accounting over diverse hardware components and enables fair allocation of available energy among applications. our particular goal is to extend battery lifetime by limiting the average discharge rate and to share this limited resource among competing task according to user preferences. to demonstrate how our framework supports explicit control over the battery resource we implemented ecosystem, a modified linux, that incorporates our currentcy model. experimental results show that ecosystem accurately accounts for the energy consumed by asynchronous device operation, can achieve a target battery lifetime, and proportionally shares the limited energy resource among competing tasks.
compiler optimization of scalar value communication between speculative threads. while there have been many recent proposals for hardware that supports thread-level speculation (tls), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. in this paper, we focus on one important limitation of program performance under tls, which is stalls due to forwarding scalar values between threads that would otherwise cause frequent data dependences. we present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. in addition, we contrast our compiler techniques with related hardware-only approaches. with our most aggressive compiler and hardware techniques, we improve performance under tls by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
frequent value locality and value-centric data cache design. by studying the behavior of programs in the specint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the frequent value locality, according to which a few values appear very frequently in memory locations and are therefore involved in a large fraction of memory accesses. in these six programs ten distinct values occupy over 50% of all memory locations and on an average account for nearly 50% of all memory accesses during program execution. this observation holds for smaller blocks of consecutive memory locations and the set of frequent values remains quite stable over the execution of the program.in the six benchmarks with frequent value locality, on an average 50% of all cache misses occur during the reading or writing of the ten most frequently accessed values. we propose a new data cache structure, the frequent value cache (fvc), which employs a value-centric approach to caching data locations for exploiting the frequent value locality phenomenon. fvc is a small direct-mapped cache which is dedicated to holding only frequently occurring values. the value-centric nature of fvc enables us to store data in a compressed form where the compression is achieved by encoding the frequent values using a few bits. moreover this simple compression scheme preserves the random access to data values in a cache line.our experiments demonstrate that by augmenting a direct mapped cache (dmc) with a direct mapped fvc of size no more than 3 kbytes we can obtain reductions in miss rates ranging from 1% to 68%. in fact we observed that higher reductions in miss rates can be achieved by augmenting a dmc with a small fvc as opposed to doubling the size of dmc for the 124.m88ksim and 134.perl benchmarks.
dynamic tracking of page miss ratio curve for memory management. memory can be efficiently utilized if the dynamic memory demands of applications can be determined and analyzed at run-time. the page miss ratio curve(mrc), i.e. page miss rate vs. memory size curve, is a good performance-directed metric to serve this purpose. however, dynamically tracking mrc at run time is challenging in systems with virtual memory because not every memory reference passes through the operating system (os).this paper proposes two methods to dynamically track mrc of applications at run time. the first method is using a hardware mrc monitor that can track mrc at fine time granularity. our simulation results show that this monitor has negligible performance and energy overheads. the second method is an os-only implementation that can track mrc at coarse time granularity. our implementation results on linux show that it adds only 7--10% overhead.we have also used the dynamic mrc to guide both memory allocation for multiprogramming systems and memory energy management. our real system experiments on linux with applications including apache web server show that the mrc-directed memory allocation can speed up the applications' execution/response time by up to a factor of 5.86 and reduce the number of page faults by up to 63.1%. our execution-driven simulation results with spec2000 benchmarks show that the mrc-directed memory energy management can improve the energy * delay metric by 27--58% over previously proposed static and dynamic schemes.
hide: an infrastructure for efficiently protecting information leakage on the address bus. xom-based secure processor has recently been introduced as a mechanism to provide copy and tamper resistant execution. xom provides support for encryption/decryption and integrity checking. however, neither xom nor any other current approach adequately addresses the problem of information leakage via the address bus. this paper shows that without address bus protection, the xom model is severely crippled. two realistic attacks are shown and experiments show that 70% of the code might be cracked and sensitive data might be exposed leading to serious security breaches.although the problem of address bus leakage has been widely acknowledged both in industry and academia, no practical solution has ever been proposed that can provide an adequate security guarantee. the main reason is that the problem is very difficult to solve in practice due to severe performance degradation which accompanies most of the solutions. this paper presents an infrastructure called hide (hardware-support for leakage-immune dynamic execution) which provides a solution consisting of chunk-level protection with hardware support and a flexible interface which can be orchestrated through the proposed compiler optimization and user specifications that allow utilizing underlying hardware solution more efficiently to provide better security guarantees.our results show that protecting both data and code with a high level of security guarantee is possible with negligible performance penalty (1.3% slowdown).
a regulated transitive reduction (rtr) for longer memory race recording. now at vmware. multithreaded deterministic replay has important applications in cyclic debugging, fault tolerance and intrusion analysis. memory race recording is a key technology for multithreaded deterministic replay. in this paper, we considerably improve our previous always-on flight data recorder (fdr) in four ways: •longer recording by reducing the log size growth rate to approximately one byte per thousand dynamic instructions. •lower hardware cost by reducing the cost to 24 kb per processor core. •simpler design by modifying only the cache coherence protocol, but not the cache. •broader applicability by supporting both sequential consistency (sc) and total store order (tso) memory consistency models (existing recorders support only sc).these improvements stem from several ideas: (1) a regulated transitive reduction (rtr) recording algorithm that creates stricter and vectorizable dependencies to reduce the log growth rate; (2) a set/lru timestamp approximation method that better approximates timestamps of uncached memory locations to reduce the hardware cost; (3) an order-value-hybrid recording methodthat explicitly logs the value of potential sc-violating load instructions to support multiprocessor systems with tso.
hardbound: architectural support for spatial safety of the c programming language. the c programming language is at least as well known for its absence of spatial memory safety guarantees (i.e., lack of bounds checking) as it is for its high performance. c's unchecked pointer arithmetic and array indexing allow simple programming mistakes to lead to erroneous executions, silent data corruption, and security vulnerabilities. many prior proposals have tackled enforcing spatial safety in c programs by checking pointer and array accesses. however, existing software-only proposals have significant drawbacks that may prevent wide adoption, including: unacceptably high run-time overheads, lack of completeness, incompatible pointer representations, or need for non-trivial changes to existing c source code and compiler infrastructure. inspired by the promise of these software-only approaches, this paper proposes a hardware bounded pointer architectural primitive that supports cooperative hardware/software enforcement of spatial memory safety for c programs. this bounded pointer is a new hardware primitive datatype for pointers that leaves the standard c pointer representation intact, but augments it with bounds information maintained separately and invisibly by the hardware. the bounds are initialized by the software, and they are then propagated and enforced transparently by the hardware, which automatically checks a pointer's bounds before it is dereferenced. one mode of use requires instrumenting only malloc, which enables enforcement of perallocation spatial safety for heap-allocated objects for existing binaries. when combined with simple intraprocedural compiler instrumentation, hardware bounded pointers enable a low-overhead approach for enforcing complete spatial memory safety in unmodified c programs.
understanding the propagation of hard errors to software and implications for resilient system design. with continued cmos scaling, future shipped hardware will be increasingly vulnerable to in-the-field faults. to be broadly deployable, the hardware reliability solution must incur low overheads, precluding use of expensive redundancy. we explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults. fundamental to such a solution is a characterization of how hardware faults indifferent microarchitectural structures of a modern processor propagate through the application and os. this paper aims to provide such a characterization, resulting in identifying low-cost detection methods and providing guidelines for implementation of the recovery and diagnosis components of such a reliability solution. we focus on hard faults because they are increasingly important and have different system implications than the much studied transients. we achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator. our main results are: (1) we are able to detect 95% of the unmasked faults in 7 out of 8 studied microarchitectural structures with simple detectors that incur zero to little hardware overhead; (2) over 86% of these detections are within latencies that existing hardware checkpointing schemes can handle, while others require software checkpointing; and (3) a surprisingly large fraction of the detected faults corrupt os state, but almost all of these are detected with latencies short enough to use hardware checkpointing, thereby enabling os recovery in virtually all such cases.
the mapping collector: virtual memory support for generational, parallel, and concurrent compaction. parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (mres) to maintain scalability, as multi-core architectures and multi-threaded applications become pervasive. moreover, state-of-the-art mres commonly implement compaction to eliminate heap fragmentation and enable fast linear object allocation. our empirical analysis of object demographics reveals that unreachable objects in the heap tend to form clusters large enough to be effectively managed at the granularity of virtual memory pages. even though processes can manipulate the mapping of the virtual address space through the standard operating system (os) interface on most platforms, extant parallel/concurrent compactors do not do so to exploit this clustering behavior and instead achieve compaction by performing, relatively expensive, object moving and pointer adjustment. we introduce the mapping collector (mc), which leverages virtual memory operations to reclaim and consolidate free space without moving objects and updating pointers. mc is a nearly-single-phase compactor that is simpler and more efficient than previously reported compactors that comprise two to four phases. through effective mre-os coordination, mc maintains the simplicity of a non-moving collector while providing efficient parallel and concurrent compaction. we implement both stop-the-world and concurrent mc in a generational garbage collection framework within the open-source hotspot java virtual machine. our experimental evaluation using a multiprocessor indicates that mc significantly increases throughput and scalability as well as reduces pause times, relative to state-of-the-art, parallel and concurrent compactors.