waashk/dblp huggingface dataset:
a layout dependent full-chip copper electroplating topography model. in this paper, a layout dependent full-chip electroplating (ecp) topography model is developed based on the additive nature of the physics of the ep process. two layout attributes: layout density, and feature perimeter sum are used to compute the post-ecp topography. under a unified mechanism, two output variables representing the final topography: the array height and the step height are modeled simultaneously. using the proposed model long-range effects of the ecp process can be incorporated easily as well. the simulation results of our model were verified with test structure experimental data published in the literature and are presented in this paper. the results show that the errors are less than 5%. this model is not limited to the regular test structures; it can also be used for any practical design. the results of such partial application are shown here as well. our proposed ecp model can be used to model systematic variations caused by an ecp process or by a chemical mechanical planarization (cmp) process. the potential applications of this model include: layout design evaluation for catastrophic failure prevention; yield aware design (design for manufacturability), and variation- aware timing analysis.
a sequential quadratic programming approach to concurrent gate and wire sizing. with an ever-increasing portion of the delay in high- speed cmos chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. by transforming the gate and multilayer wire sizing problem into a convex programming problem for the elmore delay approximation, we demonstrate the efficacy of a sequential quadratic programming (sqp) solution method. for cases where accuracy greater than that provided by the elmore delay approximation is required, we apply sqp to the gate and wire sizing problem with more accurate delay models. since efficient calculation of sensitivities is of paramount importance during sqp, we describe an approach for efficient computation of the accurate delay sensitivities.
coupling-aware high-level interconnect synthesis for low power. ultra deep submicron (udsm) technology and system-on-chip (soc) have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are (1) the transition activities on the signal lines and (2) the coupling capacitances of the lines. however, there has been no easy way of optimizing (1) and (2) simultaneously at an early stage of the synthesis process. in this paper, we propose a new (on-chip) bus synthesis algorithm to minimize the total sum of (1) and (2) in the microarchitecture synthesis. specifically, unlike the previous approaches in which (1) and (2) are minimized sequentially without any interaction between them, or only one of them is minimized, we, given a scheduled dataflow graph to be synthesized, minimize (1) and (2) simultaneously by formulating and solving the two important issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of signal lines in each bus, both of which are the most critical factors that affect the results of (1) and (2). experimental results on a number of benchmark problems show that the proposed integrated low-power bus synthesis algorithm reduces power consumption by 24.8%, 40.3% and 18.1% on average over those in [12] (for minimizing (1) only), [1] (for (2) only) and [12, 1] (for (1) and then (2)), respectively.
an integrated data path optimization for low power based on network flow method. we propose an effective algorithm for power optimization in behavioral synthesis. in previous work, it has been shown that several hardware allocation/binding problems for power optimization can be formulated as network flow problems and be solved optimally. however, in these formulations, a fixed schedule was assumed. in such context, one key problem is: given an optimal network flow solution to a hardware allocation/binding problem for a schedule, how to generate a new optimal network flow solution rapidly for a local change of the schedule. to this end, from a comprehensive analysis of the relation between network structure and flow computation, we devise a two-step procedure: (step 1) max-flow computation step which finds a valid (maximum) flow solution while retaining the previous (maximum flow of minimum cost) solution as much as possible; (step 2) min-cost computation step which incrementally refines the flow solution obtained in step 1, using the concept of finding a negative cost cycle in the residual graph for the flow. the proposed algorithm can be applied effectively to several important high-level data path optimization problems (e.g., allocations/bindings of functional units, registers, buses, and memory ports) when we have the freedom to choose a schedule that will minimize power consumption. experimental results (for bus synthesis) on benchmark problems show that our designs are 5.2% more power-efficient over the best known results, which is due to (a) exploitation of the effect of scheduling and (b) optimal binding for every schedule instance. furthermore, our algorithm is about 2.8 times faster in run time over the full network flow based (optimal) bus synthesis algorithm, which is due to (c) our novel (two-step) mechanism which utilize the previous flow solution to reduce redundant flow computations.
interval-valued statistical modeling of oxide chemical-mechanical polishing. technology-oriented tools provide the raw data needed to optimize the fabrication process itself, and to predict problematic variational impacts on silicon design. unfortunately, even in these physics-oriented tools, statistically uncertain quantities appear as crucial inputs. to date, monte carlo techniques have been the dominant solution method. we suggest an alternative in which uncertainties are represented as correlated intervals, and interval-valued computations replace the standard scalar operations in the numerical algorithm for the tool. we use an oxide chemical-mechanical polishing tool as an example, and show how to "retrofit" workable statistical models on top of the original algorithm. accuracies to within /spl sim/1-10% of monte carlo simulation, and speedups of /spl sim/10-100x can be achieved, depending on whether we choose a formulation which emphasizes accuracy, or efficiency.
a methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. a general and efficient preprocessing algorithm which can increase circuit simulation efficiency is discussed. the algorithm identifies significant devices based upon circuit topology. device model complexity and error tolerances are varied based upon device significance which results in a reduction in the required model evaluation time
verification of systems containing counters. it is pointed out that systems containing counters have very large and deep state spaces, and the verification of properties on these systems can be very expensive in terms of memory space and computation time. a technique for automatically reducing the state space associated with the system on which some properties that can express both safeness and fairness constraints have to be proved is presented. in particular, a set of conditions upon which some counters can be reduced to three-state, nondeterministic machines is given. the controllers can be simplified by removing the redundancy induced by their interaction with the counter, so that the verification tasks can be more easily performed
a statistical optimization-based approach for automated sizing of analog cells. this paper presents a cad tool for automated sizing of analog cells using statistical optimization in a simulation based approach. a nonlinear penalty-like approach is proposed to define a cost function from the performance specifications. also, a group of heuristics is proposed to increase the probability of reaching the global minimum as well as to reduce cpu time during the optimization process. the proposed tool sizes complex analog cells starting from scratch, within reasonable cpu times (approximately 1 hour for a fully differential opamp with 51 transistors), requiring no designer interaction, and using accurate transistor models to support the design choices. tool operation and feasibility is demonstrated via experimental measurements from a working cmos prototype of a folded-cascode amplifier.
power minimization using system-level partitioning of applications with quality of service requirements. design systems to provide various quality of service (qos) guarantees has received a lot of attentions due to the increasing popularity of real-time multimedia and wireless communication applications. meanwhile, low power consumption is always one of the goals for system design, especially for battery-operated systems. with the design trend of integrating multiple processor cores and memory on a single chip, we address the problem of how to partition a set of applications among processors, such that all the individual qos requirements are met and the total energy consumption is minimized. we exploit the advantages provided by the variable voltage design methodology to choose the voltage for each application on the same processor optimally for this purpose. we also discuss how to partition applications among the processors to achieve the same goal. we formulate the problem on an abstract qos model and present how to allocate resources (e.g., cpu time) and determine the voltage profile for every single processor. experiments on media benchmarks have also been studied.
a cad framework for co-design and analysis of cmos-set hybrid integrated circuits. this paper introduces a cad framework for co-simulation ofhybrid circuits containing cmos and set (single electrontransistor) devices. an improved analytical model for set is alsoformulated and shown to be applicable in both digital and analogdomains. particularly, the extension of the recent mib model forsingle/multi gate symmetric/asymmetric device for a wide range ofdrain to source voltage and temperature is addressed. circuit levelco-simulations are successfully performed by implementing theset analytical model in analog hardware description language(ahdl) of a professional circuit simulator smartspice.validation at device and circuit level is carried out by monte-carlosimulations. some novel functionality hybrid cmos-setcircuit characteristics: (i) set neuron (ii) multiple valued logiccircuit and (iii) a new negative differential resistance (ndr)circuit, are also predicted by the proposed set model andanalyzed using the new hybrid simulator.
on the optimization power of redundancy addition and removal techniques for sequential circuits. this paper attempts to determine the capabilities of existing redundancy addition and removal (srar) techniques for logic optimization of sequential circuits. to this purpose, we compare this method with the retiming and resynthesis (rar) techniques. for the rar case the set of possible transformations has been established by relating them to stg transformations by other authors. following these works, we first formally demonstrate that logic transformations provided by rar are covered by srar as well. then we also show that srar is able to identify transformations that cannot be found by rar. this way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques.
minimum area retiming with equivalent initial states. traditional minimum area retiming algorithms attempt to achieve their prescribed objective with no regard to maintaining the initial state of the system. this issue is important for circuits such as controllers, and our work addresses this problem. the procedure described generates bounds on the retiming variables that guarantee an equivalent initial state after retiming. a number of possible sets of bounds can be derived, and each set is used to solve a minimum area retiming problem that is set up as a 0/1 mixed integer linear program, using a new technique that models the maximal sharing of flip-flops at latch outputs. the best solution is found through enumeration of these sets, terminated on achievement of a calculated lower bound. experimental results show that after a small number of enumerations, optimal or near-optimal results are achievable.
synthesis of multiplier-less fir filters with minimum number of additions. abstract: in this paper we present optimizing transformations to minimize the number of additions+subtractions in both the direct form (/spl sigma/ a/sub i/x/sub n-i/ based) and its transposed form (multiple constant multiplication based) implementation of fir filters. these transformations are based on the iterative elimination of 2-bit common subexpressions in the coefficients binary representations. we give detailed description of the algorithms and present results for eight low pass fir filters with the number of coefficients ranging from 16 to 128. the results show upto 35% reduction in the number of additions+subtractions to implement /spl sigma/ a/sub i/x/sub n-i/ based fir filter structures and upto 38% reduction to implement mcm based structures.
an optimal algorithm for area minimization of slicing floorplans. the traditional algorithm of stockmeyer for area minimization of slicing floorplans has time (and space) complexity o(n^2) in the worst case, or o(n\log n) for balanced slicing. for more than a decade, it is considered the best possible. in this paper, we present a new algorithm of worst-case time (and space) complexity o(n\log n), where n is the total number of realizations for the basic blocks, regardless whether the slicing is balanced or not. we also prove \omega(n\log n) is the lower bound on the time complexity of any area minimization algorithm. therefore, the new algorithm not only finds the optimal realization, but also has an optimal running time.
a logic simulation engine based on a modified data flow architecture. an optimum application-specific data flow architecture for accelerating the standard event driven logic simulation is developed. a conservative distributed simulation algorithm which minimizes the use of null messages is also developed, along with a pseudodynamic data flow architecture to implement this distributed algorithm efficiently. a comparison of the standard event driven algorithm-based data flow accelerator to the distributed simulation algorithm-based accelerator is made on several benchmark circuits. the distributed simulation algorithm on the specialized data flow accelerator outperforms the standard event driven algorithm based data flow accelerator by a factor of three in most cases
board-level multi-terminal net routing for fpga-based logic emulation. we consider a board-level routing problem applicable to fpga-based logic emulation systems such as the realizer system [3] and the enterprise emulation system [5] manufactured by quickturn systems. optimal algorithms have been proposed for the case where all nets are two-terminal nets [10,11]. in this paper, we show how multi-terminal nets can be handled by decomposition into two-terminal nets. we show that the multi-terminal net decomposition problem can be modelled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. a network flow-based algorithm that solves both problems is proposed. it determines if there is a feasible decomposition and gives one whenever such a decomposition exists.
minimum replication min-cut partitioning. logic replication has been shown to be very effective in reducing the number of cut nets in partitioned circuits. liu et al. considered the circuit partitioning problem with logic replication for separating two given nodes and presented an algorithm to determine a partitioning of the minimum possible cut size. in general, there are many possible partitioning solutions with the minimum cut size and the difference of their required amounts of replication can be significant. since there is a size constraint on each component of the partitioning in practice, it is desirable to also minimize the amount of replication. in this paper, we present a network-flow based algorithm to determine an optimum replication min-cut partitioning that requires minimum replication. and we show that the algorithm can be generalized to separate two given subsets of nodes and determine an optimum partitioning of the minimum possible cut size using the least possible amount of replication. we also show that our algorithm can be used to improve the solutions produced by any heuristic replication min-cut partitioning algorithm by reducing the cut size and shrinking the replication set.
generation of bdds from hardware algorithm descriptions. we propose a new method for generating bdds from hardware algorithm descriptions written in a programming language. our system can deal with control structures, such as conditional branches (if-then-else) and data dependent loops (while-end). once bdds are generated, we can immediately check the equivalence of two different algorithm descriptions just by comparing bdds. this method can also be applied to verification between algorithm-level and gate-level designs. another interesting application is to synthesize loop-free logic circuits from algorithm descriptions. we show the experimental results for some practical examples, such as greatest common divisor (gcd) calculation. although our method has a limitation in size of problems, it is very practical and useful for actual design verification.
built-in self-test and fault diagnosis of fully differential analogue circuits. an approach to the test and diagnosis of fully differential analogue circuits is described in this paper. the test approach is based on off-line monitoring via an analogue bist observer the inputs of the operational amplifiers in the circuit. the analogue bist can detect both hard and soft faults. diagnosis resolution is improved by also monitoring the outputs of the operational amplifiers. faulty components can then be located and the actual defective value of a faulty passive component determined.
design for manufacturability in submicron domain. key characteristics of newly emerging ic technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. this tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ics. the discussion also covers analysis of design for manufacturability (dfm) trade-offs. yield and cost models needed to analyze these trade-offs are explained as well.
idap: a tool for high level power estimation of custom array structures. while array structures are a significant source of power dissipation,there is a lack of accurate high-level power estimatorsthat account for varying array circuit implementationstyles. we present a methodology and a tool, the implementationdependent array power (idap) estimator, that modelpower dissipation in sram based arrays accurately basedon a high-level description of the array, parameterized bythe array operations, the implementation styles, and varioustechnology dependent parameters. the methodologyis generic and the idap tool has been validated on industrialdesigns across a wide variety of array implementationsin the e500 processor core. for these industrial designs,idap generates high-level estimates for dynamic power dissipationthat are highly accurate with an error margin ofless than 22.2% of detailed (layout extracted) spice simulations.
simplification of non-deterministic multi-valued networks. we discuss the simplification of non-deterministic mv networks and their internal nodes using internal flexibilities. given the network structure and its external specification, the flexibility at a node is derived as a non-deterministic mv relation. this flexibility is used to simplify the node representation and enhance the effect of boolean resubstitution. we show that the flexibility derived is maximum. the proposed approach has been implemented and tested in mvsis [16]. experimental results show that it performs well on a variety of mv and binary benchmarks.
a theory of non-deterministic networks. both non-determinism and multi-level networks compactlycharacterize the flexibility allowed in implementing a circuit.a theory for representing and manipulating non-deterministic(nd) multi-level networks is developed. the theory supports allthe network manipulations commonly applied to deterministicbinary networks, such as node minimization, elimination, anddecomposition. it is shown that an nd network's behavior can beinterpreted in three ways, all of which coincide when the networkis deterministic. operations performed on an nd network areanalyzed under each interpretation for changes in a network'sbehavior. modifications of a few operations are given which mustbe used to guarantee that a network's behavior does not violateits external specification. these modifications depend on whichbehavior is being used and the location of related non-determinism.this theory has been implemented in a system,mvsis. we provide comparisons among the uses of the various behaviors.
a new heuristic for rectilinear steiner trees. the minimum rectilinear steiner tree (rst) problem is one of the fundamental problems in the field of electronic design automation. the problem is np-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among rst heuristics is the batched iterated 1-steiner (bi1s) heuristic of kahng and robins. in a recent development, exact rst algorithms have witnessed spectacular progress: the new release of the geosteiner code of warme, winter, and zachariasen has average running time comparable to that of the fastest available bi1s implementation, due to robins. we are thus faced with the paradoxical situation that an exact algorithm for an np-hard problem is competitive in speed with a state-of-the-art heuristic for the problem.the main contribution of this paper is a new rst heuristic, which has at its core a recent 3/2 approximation algorithm of rajagopalan and vazirani for the metric steiner tree problem on quasi-bipartite graphs&mdash;these are graphs that do not contain edges connecting paris of steiner vertices. the rv algorithm is built around the linear programming relaxation of a sophisticated integer program formulation, called the bidirected cut relaxation. our heuristic achieves a good running time by combining an efficient implementation of the rv algorithm with simple, but powerful geometric reductions.experiments conducted on both random and real vlsi instances show that the new rst heuristic runs significantly faster than robins' implementation of bi1s and than the geosteiner code. moreover, the new heuristic typically gives higher-quality solutions than bi1s.
an output encoding problem and a solution technique. we present a new output encoding problem as follows: given a specification table, such as a truth table or a finite state machine state table, where some of the outputs are specified in terms of 1's, 0's and don't cares, and others are specified symbolically, and assuming that the minimum number of bits are used to encode the symbolic outputs (ceiling(log_2_(n)) bits for n symbolic outputs), determine a binary code for each symbol of the symbolically specified output column such that the total number of output functions to be implemented after encoding the symbolic outputs and compacting the columns is minimum. there are several applications of this output encoding problem, one of which is to reduce the area overhead while implementing scan or pseudo-random bist in a circuit with one-hot signals. we develop an exact algorithm to solve the above problem and present experimental data to validate the claim that our encoding strategy helps to reduce the area of a synthesized circuit.