waashk/dblp huggingface dataset:
schematic-based lumped parameterized behavioral modeling for suspended mems. schematic-based lumped parameterized behavioral modeling and simulation methodologies have become available since the emergence of analog hdls. they greatly ease iterative hierarchical multi-domain simulation, which is critical to the design of mems. nodas is one of such tools, with models written in veriloga and simulation performed within the cadence framework.this paper focuses on several key modeling issues in nodas, including schematic representation, element communication, linear, nonlinear and multi-domain modeling, and extensibility to new physical effects, processes and physical domains. a nonlinear beam model and an electrostatic gap model are discussed as examples. simulation comparison to finite element analyses and experimental data verifies the accuracy of the models and validates the simulation methodology.
simulation coverage enhancement using test stimulus transformations. this paper introduces the concept of abstract state exploration histories to a simulation environment, and present a test stimulus transformation (tst) technique to improve simulation coverage. state exploration histories are adapted from reachability analysis in formal verification. in tst, an aggressively abstracted state exploration history is maintained during simulation. while this history is being collected, test stimuli from an existing test bench are transformed on-the-fly to explore new scenarios that are not in the history. the results showed that 3-fold increase in transition coverage for a cache coherence controller, and 10 times faster coverage convergence for a mpeg2 decoder can be achieved.
a game theoretic approach to dynamic energy minimization in wireless transceivers. adaptive transceivers can significantly reduce the energyconsumption of a mobile, battery-powered node by capturing real-timechanges in the communication channel. this paper proposes agame-theoretic solution to the optimization of the energy consumptionin wireless transceivers. this is accomplished by dynamicallyadapting the modulation level of the transmitter modulator and theerror correction aptitude of the receiver decoder with respect tochannel conditions subject to specified average bit-error-rate andthroughput constraints. experimental results demonstrate energysavings of up to 15%.
a cache-defect-aware code placement algorithm for improving the performance of processors. yield improvement through exploiting fault-free sections of defective chips is a well-known technique (koren and singh (1990) and stapper et al. (1980)). the idea is to partition the circuitry of a chip in a way that fault-free sections can function independently. many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed. in this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. to the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. in some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.
a new algorithm for the binate covering problem and its application to the minimization of boolean relations. the binate covering problem (bcp) is the problem of finding a minimum cost assignment to variables that is a solution of a boolean equation f=1. it is a generalization of the set covering (or unate covering) problem, where f is positive unate, and is generally given as a table with rows corresponding to the set elements and the columns corresponding to the subsets. previous methods have considered the case when f is given as a product-of-sum formula or as a binary decision diagram (bdd). a branch-and-bound algorithm for the bcp that assumes f is expressed as the conjunction of multiple bdds is presented. the bcp solver that has been implemented can be applied to several problems, including exact minimization of boolean relations, for which results are presented. it has been possible to solve large, difficult problems (up to 4692 variables) which could not be solved by the product of sum based method
efficient model order reduction via multi-node moment matching. the new concept of multi-node moment matching (mmm) is introduced in this paper. the mmm technique simultaneously matches the moments at several nodes of a circuit using explicit moment matching around s=0. as compared to the well-known single-point moment matching (smm) techniques (such as awe), mmm has several advantages. first, the number of moments required by mmm is significantly lower than smm for a reduced order model of the same accuracy, which directly translates into computational efficiency. this higher computational efficiency of mmm as compared to smm increases with the number of inputs to the circuit. second, mmm has much better numerical stability as compared to smm. this characteristic allows mmm to calculate an arbitrarily high order approximation of a linear system, achieving the required accuracy for systems with complex responses. finally, mmm is highly suitable for parallel processing techniques especially for higher order approximations while smm has to calculate the moments sequentially and cannot be adapted to parallel processing techniques.
low power system scheduling and synthesis. many scheduling techniques have been presented recently which exploit dynamic voltage scaling (dvs) and dynamic power management (dpm) for both uniprocessors and distributed systems, as well as both real-time and non-real-time systems. while such techniques are power-aware and aim at extending battery lifetimes for portable systems, they need to be augmented to make them battery-aware as well. we will survey such power-aware and battery-aware scheduling algorithms. also, system synthesis algorithms for real-time systems-on-a-chip (socs), distributed and wireless client-server embedded systems, etc., have begun optimizing power consumption in addition to system price. we will survey such algorithms as well, and point out some open problems.
computation of signal threshold crossing times directly from higher order moments. this work introduces a simple method for calculating the times at which any signal crosses a pre-specified threshold voltage (e.g. 10%, 20%, 50%, etc.) directly from the moments. the method can use higher order moments to asymptotically improve the accuracy of the estimated crossing times. this technique bypasses the steps involved in calculating poles and residues to obtain time-domain information. once q moments are calculated, only 2q multiplications and (q-i) additions are required to determine any threshold crossing time at a certain node. moreover, this technique avoids other problems such as pole instability. several orders of approximations are presented for different threshold crossing times depending on the number of moments involved. for example, the worst case error of a first to a seventh order (single to seven moments) approximation of 50% rc delay is 1650%, 192.26%, 11.31%, 3.37%, 2.57%, 2.56%, and 1.43%, respectively. if the whole waveform is required it can be easily determined by interpolation between different threshold crossing points. the presented technique works for rc circuits for both step and nonstep inputs, including piecewise linear waveforms.
efficient statistical capacitance variability modeling with orthogonal principle factor analysis. due to the ever-increasing complexity of vlsi designs and ic process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern vlsi designs. in this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. the explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. experimental results demonstrate that the proposed method exhibits over 100/spl times/ speedup compared with monte carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.
repeater insertion in tree structured inductive interconnect. the effects of inductance on repeater insertion in rlc trees is the focus of this paper. an algorithm is introduced to insert and size repeaters within an rlc tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. the algorithm has a complexity proportional to the square of the number of possible repeater positions, permitting a repeater solution to be chosen that is close to the global minimum. the repeater insertion algorithm is used to insert repeaters within several copper-based interconnect trees to minimize the maximum path delay based on both an rc model and an rlc model. the two buffering solutions are compared using the as/x dynamic circuit simulator. it is shown that as inductance effects increase, the area and power consumed by the inserted repeaters to minimize the path delays of an rlc tree decreases. by including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an rc model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees from a 0.25 &mgr;m cmos technology. the average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.
don't cares and multi-valued logic network minimization. we address optimizing multi-valued (mv) logic functions in a multi-level combinational logic network. each node in the network, called an mv-node, has multi-valued inputs and single multi-valued output. the notion of don't cares used in binary logic is generalized to multi-valued logic. it contains two types of flexibility: incomplete specification and non-determinism. we generalize the computation of observability don't cares for a multi-valued function node. methods are given to compute (a) the maximum set of observability don't cares, and (b) the compatible set of observability don't cares for each mv-node. we give a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized. the methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.
module selection and data format conversion for cost-optimal dsp synthesis. in high level synthesis each node of a synchronous dataflow graph (dfg) is scheduled to a specific time and allocated to a processor. in this paper we present new integer linear programming (ilp) models which generate a blocked schedule for a dfg with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. a blocked schedule is a schedule which overlaps multiple iterations of the dfg to guarantee a minimum number of processors. component modules are selected from a library of processors to minimize cost. furthermore, we include data format converters between processors of different data formats. in addition, we minimize the unfolding factor of the blocked schedule.
sensitivity analysis of iterative design processes. as design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. in this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. two applications illustrate this approach, one involving a pareto analysis of an asic design process and the other an optimization of a software design process to determine the lower bound of the process completion time.
efficient validity checking for processor verification. we describe an efficient validity checker for the quantifier-free logic of equality with uninterpreted functions. this logic is well suited for verifying microprocessor control circuitry since it allows the abstraction of datapath values and operations. our validity checker uses special data structures to speed up case splitting, and powerful heuristics to reduce the number of case splits needed. in addition, we present experimental results and show that this implementation has enabled the automatic verification of an actual high-level microprocessor description.
timing-driven partial scan. we present a partial scan approach, which aims at reducing both area overhead and performance degradation caused by test logic. given a target speed and an initial design that meets the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break all sequential cycles and (2) will not violate the performance requirement after the scan logic is added. if such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all sequential cycles are broken and (2) the total area increase caused by the scan logic and the subsequent performance optimization to meet the target speed is minimized.experimental results on some of the iscas'89 sequential circuits are presented as well as comparisons between the new method and the existing methods. for circuits synthesized by automatic synthesis tools, we suggest a new design flow, which selects/inserts the partial scan logic after area optimization, but before performance optimization. for meeting both performance and testability requirements, the new design flow tends to produce designs with less area increase than the traditional design flow, which considers testability and adds test logic after performance optimization.this work represents an important concept for considering the three major design parameters, namely, performance, area, and testability, together during the synthesis phase for obtaining the right partial scan solution.
a fast and memory-efficient diagnostic fault simulation for sequential circuits. in this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. in it, a two-level optimization technique is developed and used to prompt the processing speed. in the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus the number of diagnostic comparisons is minimized. in the second low level, a bit-parallel comparison is developed to speed up the comparing process. therefore, the different diagnostic measure reports for a given test set can be generated very quickly. in addition, the simulator is extended to diagnose the single stuck-at device fault. experimental results show that this diagnostic simulator achieves a significant speedup compared to previous methods.
condition graphs for high-quality behavioral synthesis. identifying mutual exclusiveness between operators during behavioral synthesis is important in order to reduce the required number of control steps or hardware resources. to improve the quality of the synthesis result, we propose a representation, the condition graph, and an algorithm for identification of mutually exclusive operators. previous research efforts have concentrated on identifying mutual exclusiveness by examining language constructs such as if-then-else statements. thus, their results heavily depend on the description styles. the proposed approach can produce results independent of description styles and identify more mutually exclusive operators than any previous approaches. the condition graph and the proposed algorithm can be used in any scheduling or binding algorithms. experimental results on several benchmarks have shown the efficiency of the proposed representation and algorithm.
direct synthesis of timed asynchronous circuits. this paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. the synthesis procedure begins with a deterministic graph specification with timing constraints. a timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. then, a hazard-free implementation of the specification is synthesized by analyzing precedence graphs which are constructed by using the timed concurrency and timed causality relations. the major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates synthesized circuits that have nearly the same area as compared to previous timed circuit methods. in particular, this paper shows that a timed circuit &mdash; not containing circuit hazards under given timing constraints &mdash; can be found by using the relations between signal transitions of the specification. moreover, the relations can be efficiently found using a heuristic timing analysis algorithm. by allowing significantly larger designs to be synthesized, this work is a step towards the development of high-level synthesis tools for system level asynchronous circuits.
a new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. abstract: this paper presents a new algorithm to attain optimized network scaling in single loop, 1 bit sigma delta analog 1d digital converters (sd adc) of order three or more. the algorithm is based on a novel mathematical description of stability and performance criteria of the sd adc and on the application of nonlinear interactive optimization techniques. the feasibility of the new algorithm has been confirmed in practical implementations. the method brings new insight on the correlation between system stability, performance, system order and the choice of the network scaling. our method is extendible to cascaded sd as well as sd based on filter topologies.
maximum independent sets on transitive graphs and their applications in testing and cad. we present a polynomial time algorithm that finds the maximum weighted independent set of a transitive graph. the studied problem finds applications in a variety of vlsi contexts, including path delay fault testing, scheduling in high level synthesis and channel routing in physical design automation. the algorithm has been implemented and incorporated in a cad tool for path delay fault testing. we experimentally verify its impact in the latter context.
copy detection for intellectual property protection of vlsi designs. we give the first study of copy detection techniques for vlsi cad applications; these techniques are complementary to previous watermarking-based ip protection methods in finding and proving improper use of design ip. after reviewing related literature (notably in the text processing domain), we propose a generic methodology for copy detection based on determining basic elements within structural representations of solutions (ips), calculating (context-independent) signatures for such elements, and performing fast comparisons to identify potential violators of ip rights. we give example implementations of this methodology in the domains of scheduling, graph coloring and gate-level layout; experimental results show the effectiveness of our copy detection schemes as well as the low overhead of implementation. we remark on open research areas, notably the potentially deep and complementary interaction between watermarking and copy detection.
non-tree routing for reliability and yield improvement. we propose to introduce redundant interconnects for manufacturing yield and reliability improvement. by introducing redundant interconnects, the potential for open faults is reduced at the cost of increased potential for short faults; overall, manufacturing yield and fault tolerance can be improved. we focus on a post-processing, tree augmentation approach which can be easily integrated in current physical design flows. our contributions are as follows:&bull; we formulate the problem as a variant of the classical 2-edge-connectivity augmentation problem in which we take into account such practical issues as wirelength increase budget, routing obstacles, and use of steiner points.&bull; we show that an optimum solution can always be found on the hanan grid defined by the terminals and the corners of the feasible routing region.&bull; we give a compact integer program formulation which, for up to 100 terminal nets, is solved in practical runtime by the commercial optimization package cplex.&bull; we give a well-scaling greedy algorithm which has practical runtime up to 1,000 terminals, and comes on the average within 1--2% of the optimum computed by cplex.&bull; we give a comprehensive experimental study comparing the solution quality and runtime of our methods with the best reported methods for 2-edge-connectivity augmentation, including a sophisticated heuristic based on minimum-weight branchings [9] and a recent genetic algorithm [14].experiments on randomly generated and industry testcases show that our greedy augmentation method achieves significant increase in reliability (as measured by the percentage of biconnected tree edges) with very small increase in wirelength. for example, on 1,000 terminal nets the average percentage of biconnected tree edges is 34.19% for a wire-length increase of only 1%, and 87.73% for a wirelength increase of 20%. spice simulations on industry routed nets show that non-tree routing has the additional benefit of reducing maximum sink delay by an average of 28.26% compared to steiner routing, and by an average of 3.72% compared to timing optimized routing. spice simulations further imply that non-tree routing has smaller delay variation due to process variability.
on mismatches between incremental optimizers and instance perturbations in physical design tools. the incremental, "construct by correction" design methodology has become widespread in constraint-dominated dsm design. we study the problem of eco for physical design domains in the general context of incremental optimization. we observe that an incremental design methodology is typically built from a full optimizer that generates a solution for an initial instance, and an incremental optimizer that generates a sequence of solutions corresponding to a sequence of perturbed instances. our hypothesis is that in practice, there can be a mismatch between the strength of the incremental optimizer and the magnitude of the perturbation between successive instances. when such a mismatch occurs, the solution quality will degrade -- perhaps to the point where the incremental optimizer should be replaced by the full optimizer. we document this phenomenon for three distinct domains -- partitioning, placement and routing -- using leading industry and academic tools. our experiments show that current cad tools may not be correctly designed for eco-dominated design processes. thus, compatibility between optimizer and instance perturbation merits attention both as a research question and as a matter of industry design practice.