waashk/dblp huggingface dataset:
is wire tapering worthwhile? wire sizing and buffer insertion/sizing are critical optimizations in deep submicron design. the past years have seen several studies of buffer insertion, wire sizing, and their simultaneous optimization. when wiring long interconnect, tapering, i.e., reducing the wire width as the distance from the driver increases, has proven effective. however, tapering is not widely utilized in industry since it is difficult to integrate into a complete routing methodology. this work examines the benefits of wire sizing with tapering when combined with buffer insertion. we perform several experiments with actual ibm technologies. results indicate that wire tapering reduces delay typically by less than 5% compared to uniform wire sizing, when buffers can be inserted. consequently, we suggest that it may not be worthwhile to maintain a routing methodology that supports wire tapering.
accurate estimation of global buffer delay within a floorplan. closed formed expressions for buffered interconnect delay approximation have been around for some time. however, previous approaches assume that buffers are free to be placed anywhere. in practice, designs frequently have large blocks that make the ideal buffer insertion solution unrealizable. the theory of otten (1998) is extended to show how one can model the blocks into a simple delay estimation technique that applies both to two-pin and to multi-pin nets. even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer insertion solution. potential applications include wire planning, timing analysis during floorplanning or global routing. our experiments show that our approach accurately predicts delay when compared to constructing a realizable buffer insertion with multiple buffer types.
a general framework for vertex orderings, with applications to netlist clustering. we present a general framework for the construction of vertex orderings for netlist clustering. our window algorithm constructs an ordering by iteratively adding the vertex with highest attraction to the existing ordering. variant choices for the attraction function allow our framework to subsume many graph traversals and clustering objectives from the literature. the dp-rp method of [3] is then applied to optimally split the ordering into a k-way clustering. our approach is adaptable to use-specified cluster size constraints. experimental results for clustering and multi-way partitioning are encouraging.
an assembly-level execution-time model for pipelined architectures. the aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter-instruction effects. such effects depend on the processor state and the pipeline behavior, and are related to the dynamic execution of assembly code. the paper proposes a mathematical model of the delays deriving from instruction dependencies and gives a statistical characterization of such timing overheads. the model has been validated on a commercial architecture, the intel486, by means of timing analysis of a set of benchmarks, obtaining an error within 5%. this model can be seamlessly integrated with a static energy consumption model in order to obtain precise software power and energy estimations.
minimum-buffered routing of non-critical nets for slew rate and reliability control. in high-speed digital vlsi design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. bounding load capacitance also improves reliability with respect to hot-carrier oxide breakdown and ac self-heating in interconnects, and guarantees bounded input rise/fall times at buffers and sinks.this paper introduces a new minimum-buffer routing problem (mbrp) formulation which requires that the capacitive load of each buffer, and of the source driver, be upper-bounded by a given constant. our contributions include the following.&bull; we give linear-time algorithms for optimal buffering of a given routing tree with a single (inverting or non-inverting) buffer type.&bull; for simultaneous routing and buffering with a single non-inverting buffer type, we give a factor 2(1 + &epsilon;) approximation algorithm and prove that no algorithm can guarantee a factor smaller than 2 unless p=np. for the case of a single inverting buffer type, we give a factor 4(1 + &epsilon;) approximation algorithm.&bull; we give local-improvement and clustering based mbrp heuristics with improved practical performance, and present a comprehensive experimental study comparing the runtime/quality tradeoffs of the proposed mbrp heuristics on test cases extracted from recent industrial designs.
free space management for cut-based placement. ip blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. we observe that top-down placement based on recursive bisection with multilevel partitioning performs poorly on these porous designs. however, analytic solvers have the ability to find the natural distribution of cells in the layout. consequently, we propose an enhancement to cut-based placement called analytic constraint generation (acg). acg utilizes an analytic engine to set constraints for the multi-level partitioner. we show that for real industry designs, acg significantly improves the performance of cut-based placement, as implemented within a state-of-the-art industrial placer.
fast power estimation for deterministic input streams. the power dissipated by digital systems under realistic input stimuli is not accurately described by a single average value, but by a waveform that shows how power consumption varies over time as the system responds to the inputs. we face the problem of obtaining accurate power waveforms for combinational and sequential circuits under typical usage patterns. we propose a multi level simulation engine that achieves high accuracy in estimating the average power as well as the time domain power waveform with high computational efficiency.
reuse of design objects in cad frameworks. the reuse of well-tested and optimized design objects is an important aspect for decreasing design times, increasing design quality, and improving the predictability of designs. reuse spans from the selecting cells from a library up to adapting already designed objects.in this paper, we present a new model for reusing design objects in cad frameworks. based on experiences in other disciplines, mainly in software engineering and case-based reasoning, we developed a feature-based model to describe design objects and their similarities. our model considers generic modules as well as multi-functional units. we discuss the relationships of the model to design process and to the configuration hierarchy of complex design objects. we examined our model with the prototype system rodeo.
function unit specialization through code analysis. many previous attempts at asip synthesis have employed template matching techniques to target function units to application code, or directly design new units to extract maximum performance. this paper presents an entirely new approach to specializing hardware for application specific needs. in our framework of a parameterized vliw processor, we use a post-modulo scheduling analysis to reduce the allocated hardware resources while increasing the code's performance. initial results indicate significant savings in area, as well as optimizations to increase fir filter code performance 200% to 300%.
weibull based analytical waveform model. current cmos technologies are characterized by interconnectlines with increased relative resistance w.r.t. driver outputresistance. designs generate signal waveshapes that are verydifficult to model using a single parameter model such as thetransition time. in this paper, we present a simple and robustparameter analytical expression for waveform modeling based onthe weibull cumulative distribution function. the weibull modelaccurately captures the variety of waveshapes without introducingsignificant runtime overhead and produces results with less than5% error. we also present a fast and simple algorithm to convertwaveforms obtained by circuit simulation to the weibull model. amethodology for characterizing gates for the new model is alsopresented. simulation results for many single and multiple inputgates show errors well below 5%. our model can be used in amixed environment where some signals may still be characterizedby a single parameter.
modeling unbuffered latches for timing analysis. unbuffered latches are often used in high-performance designs with custom timing flows. adding these circuits to a standard library enables improved designs without blowing the library size. we observe a high potential frequency gain (up to 16%) for smaller power consumption. accurate models for static timing analysis are required to reach a good point on the safety to performance trade-off. we are proposing a complete modeling methodology that can fit in a standard timing analysis flow. an accurate n-model is presented for the input impedance of an unbuffered latch with less than 2% error. we also present a new setup criteria required for these latches. we also show that more advanced waveform models are required to model the output. a weibull waveform model proves to be effective in this case.
efficient use of large don't cares in high-level and logic synthesis. this paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. the following three issues are discussed: 1) how to describe and extract don't-care conditions from high-level descriptions; 2) how to pass don't-care conditions from high-level to logic synthesis; and 3) how to optimize the logic using don't-care conditions. efficient techniques are given for these three problems which allow the use of large don't-care sets. results from several examples demonstrate that these techniques are very effective for both area and delay minimization.
zamlog: a parallel algorithm for fault simulation based on zambezi. we present a new multiprocessor sequential circuit fault simulator, zamlog, based on a novel uniprocessor simulator, zambezi. both the fault and test sets are partitioned for multiprocessor simulation. the parallelization technique, designed to preserve the efficiency of zambezi, is simple to implement and has low communication requirements. experimental results indicate that zamlog can obtain speedups of up to 95. the speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.
the a to z of socs. the exploding complexity of new chips and the ever decreasing time-to-market window are forcing fundamental changes in the way systems are designed. the advent of systems-on-chip (soc) based on pre-designed intellectual-property (ip) cores has become an absolute necessity for embedded systems companies to remain competitive. designing an soc, however, is extremely complex, as it encompasses a range of difficult problems in hardware and software design. this paper explains a wide range of soc issues including market drivers and trends, technology and integration aspects, early architecture definition, methodology, hardware and software design and verification techniques.
low-power programmable routing circuitry for fpgas. we propose two new fpga routing switch designs that are programmable to operate in three different modes: high-speed, low-power or sleep. high-speed mode provides similar power and performance to a traditional routing switch. in low-power mode, speed is curtailed in order to reduce power consumption. our first switch design reduces leakage power consumption by 36-40% in low-power vs. high-speed mode (on average); dynamic power is reduced by up to 28%. leakage power in sleep mode is 61% lower than in high-speed mode. a second switch design offers a 36% smaller area overhead and reduces leakage by 28-30% in low-power vs. high-speed mode. the proposed switch designs require only minor changes to a traditional routing switch, making them easy to incorporate into current fpga interconnect. the applicability of the new switches is motivated through an analysis of timing slack in industrial fpga designs. specifically, we show that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.
improving coverage analysis and test generation for large designs. state space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. by comparing the state and edge coverage provided by tests with that which is possible in the design's state graph, the designer can estimate how well tested the design is and identify areas that need better testing. unfortunately, for many interesting designs, the full state graph may be too large to fully explore, or if it is explorable, the resulting coverage may be so low as to provide limited feedback. several techniques have been proposed that identify and work with an interesting subset of the design's state machines, but they still require computing the full state graph before projecting it. in this paper we discuss projection directed state exploration, in which a projection from the full graph is found while exploring only the relevant portion of the full graph. even with this limited exploration, bdd size blowup is still a problem. to deal with this, we have also developed several interactive tools that provide feedback to the designer, and allow them to add hints to help with the exploration.
simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption. the voltage scaling technique achieves energy efficiency by simultaneously scaling the supply and body bias voltages in the case of processors and buses with repeaters, while energy efficiency on fat wires is achieved through dynamic voltage swing scaling. we also introduce a set of accurate communication models for the energy estimation of voltage scalable embedded systems. in particular, we demonstrate that voltage scaling of bus repeaters and dynamic adaption of the voltage swing on fat wires can significantly influence the system's energy consumption. experimental results, conducted on numerous generated benchmarks and a real-life example, demonstrate that substantial energy savings can be achieved with the proposed techniques.
computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. the gate sizing problem is the problem of finding load drive capabilities for all gates in a given boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and/or power consumption is minimal. this paper describes a way to obtain the entire cost versus delay trade-off curve of a combinational logic circuit in an efficient way. every point on the resulting curve is the global optimum of the corresponding gate sizing problem. the problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. it is shown that this setup is very efficient, and can produce trade-off curves for large circuits (thousands of gates) in a few minutes. benchmark results for the entire set of mcnc '91 two-level examples are given.
equivalent design representations and transformations for interactive scheduling. it is pointed out that high-level synthesis (hls) requires more designer interaction to better meet the needs of experienced designers. however, attempts to create a highly interactive synthesis process are hampered by incompatibility of various representations used during synthesis. to overcome this problem, equivalent representations are needed, as well as equivalence-preserving synthesis transformations. the structured finite state machine (sfsm) design model for scheduled behavior is presented, its equivalence to the control data flow graph (cdfg) model is shown, and primitive behavior-preserving transformations for scheduling are defined. this model and these transformations have been integrated into the bif interactive environment to permit manual rescheduling of a design
efficient orthonormality testing for synthesis with pass-transistor selectors. this paper presents the mapping problem for pass transistor selector mapping, which has not been addressed before. pass transistor synthesis is potentially important for semi- or full-custom design techniques, which are increasingly attracting attention. pass transistors have the advantage that fewer transistors are needed, and that circuits with high fanin and small delay can be constructed. technology mapping approaches in the existing literature cannot handle these selectors, due to the restriction of 1-hot encoding of the control signals. we present a new algorithm to address this problem, which is based on the novel idea of a general boolean oracle. our oracle is based on atpg techniques, and compared to bdds, the oracle has the advantage that failure to complete only affects optimization locally, and does not hinder optimization elsewhere in the logic. a limitation of bdds is that it is difficult to complete the algorithm if a bdd grows too large. the experimental results show up to 82% improvement in transistor count for the mcnc combinatorial multi-level examples.
analytical macromodeling for high-level power estimation. this paper present a new macromodeling technique for high-level power estimation. our technique is based on a parameterizable analytical model that relies exclusively on statistical information of the circuit's primary inputs. during estimation, the statistics of the required metrics are extracted from the input stream, and a power estimate is obtained by evaluating a model function that has been characterized in advance. our model yields power estimates within seconds, because it does not rely on the statistics of the circuit's primary outputs and, consequently, does not perform any simulation during estimation. moreover, it achieves better accuracy than previous macromodeling approaches by taking into account both spatial and temporal correlations in the input stream.in experiments with the iscas-85 combinational circuits, the average absolute relative error of our power macromodeling technique was at most 1.8%. the worst-case error was at most 12.8%. for a ripple-carry adder family, in comparison with power estimates that were obtained using spice, the average absolute and worst-case errors of our model's estimates were at most 5.1% and 19.8%, respectively.in addition to power dissipation, our macromodeling technique can be used to estimate the statistics of a circuit's primary outputs with very low average errors. it is thus suitable for power estimation in core-based systems with pre-characterized blocks. once the metrics of the primary inputs are known, the power dissipation of the entire system can be estimated by simply propagating this information through the blocks using their corresponding model functions.
a new built-in self-test approach for digital-to-analog and analog-to-digital converters. this paper proposes a test approach and circuitry suitable for built-in self-test (bist) of digital-to-analog (d/a) and analog-to-digital (a/d) converters. offset, gain, linearity and differential linearity errors are tested without using test equipment. the proposed bist structure decreases the test cost and test time. the bist circuitry has been designed to d/a and a/d converters using cmos 1.2 &mgr;m technology. by only a minor modification the test structure would be able to localize the fail situation. the small value of area overhead (aoh), the simplicity and efficiency of the proposed bist architecture seem to be promising for manufacturing.
design space exploration for a umts front-end exploiting analog platforms. universal mobile telecommunication system (umts) front end design is challenging because of the need to optimize power while satisfying a very high dynamic range requirement. dealing with this design problem at the transistor level does not allow exploring efficiently the design space, while using behavioral models does not allow taking into consideration important second-order effects. we present an extension of the platform-based design methodology originally developed for digital systems to the analog domain to conjugate the need of higher levels of abstraction to deal with complexity as well as the one of capturing enough of the actual circuit-level characteristics to deal with second order effects. we show how this methodology applied to the umts front-end design yields power savings as large as 47% versus an original hand optimized design.
a signature based approach to regularity extraction. regularity extraction is an important step in the design flow of datapath-dominated circuits. this paper outlines a new method that automatically extracts regular structures from the netlist. the method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the hdl level; and designs with no such structured cluster information. the method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.
efficient analog platform characterization through analog constraint graphs. we propose a scheme for improving the efficiency of the characterization process for system-level models of analog circuits within the analog platform based design paradigm. we leverage designer knowledge to map basic functional requirements of the circuit into circuit parameters relations so that the sampling space can be significantly reduced. a set of equalities and inequalities in the circuit parameters is used to represent the constraints. a feasible parameter space lies at the intersection of the sets of design parameters that satisfy equalities and inequalities, defining a manifold in the parameter space. we introduce a bipartite graph representation denoted analog constraint graphs (acg) to represent these constraints. acgs are instrumental for obtaining a random configuration generator that samples configurations in the manifold. the sampler is automatically translated into executable code to fit the characterization framework starting from a mathematical description of constraints. results show that the automatically generated samplers are comparable in terms of code efficiency with hand-written ones. furthermore, a heuristics to generate uniformly distributed configuration enabled by the tools is presented and applied to a complex adc design, yielding a reduction in power consumption by more than 28%.
efficient ltl compilation for sat-based model checking. this work describes an algorithm of automata construction for ltl safety properties, suitable for bounded model checking. existing automata construction methods are tailored to bdd-based symbolic model checking. the novelty of our approach is that we construct deterministic automata, unlike the standard approach, which constructs nondeterministic automata. we show that the proposed method has significant advantages for bounded model checking over traditional methods.