waashk/dblp huggingface dataset:
slot allocation using logical networks for tdm virtual-circuit configuration for network-on-chip. configuring time-division-multiplexing (tdm) virtual circuits (vcs) for network-on-chip must guarantee conflict freedom for overlapping vcs besides allocating sufficient time slots to them. these requirements are fulfilled in the slot allocation phase. in the paper, we define the concept of a logical network (ln). based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free vcs. using these theorems, slot allocation for vcs becomes a procedure of computing lns and then assigning vcs to different lns. tdm vc configuration can thus be predictable and correct-by-construction. we have integrated this slot allocation method into our multi-node vc configuration program and applied the program to an industrial application.
analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. clock meshes posses inherent low clock skews and excellent immunity to pvt variations, and have increasingly found their way to high-performance ic designs. however, analysis of such massively coupled networks is significantly hindered by the sheer size of the network and tight coupling between non-tree interconnects and large numbers of clock drivers. the presented harmonic-weighted model order reduction algorithm is motivated by the key observation of the steady-state operation of the clock networks, and its efficiency is facilitated by the locality analysis via port sliding. the scalability of the analysis is significantly improved by eliminating the need of computing infeasible multi-port passive reduced order interconnect models with large port count. and the overall task is decomposed into tractable and naturally parallelizable model generation and fft/inverse-fft operations, all on a per driver or per sink basis.
optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example. connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. high-speed links are particularly hard to analyze because of the complex interplay of device/circuit parasitics and channel filtering operation. in this paper we introduce optimization-based framework for link design-space exploration, connecting the link transmission quality and top-level filter settings with circuit power, sizing and biasing. we derive a special analytical discrete time representation that avoids the size explosion of the symbolic problem description improving the parsing and solver time by orders of magnitude and making this joint optimization possible in real-time. this robust and accurate problem formulation is derived in signomial form and is compatible with existing optimization approaches to circuit sizing. we demonstrate this optimization framework on a link design-space exploration example, investigating trade-offs between the transmit preemphasis and linear receiver equalizer and their impact on overall link power vs. data rate.
inductive equivalence checking under retiming and resynthesis. retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. however, their applicability is much limited due to verification concerns. overcoming the verification bottleneck is a supreme task. this paper studies both the theoretical and practical aspects of inductive verification on the equivalence between circuits under retiming and resynthesis transformation. we study the completeness condition of the inductive approach to equivalence checking and show that prior work is only complete for circuits transformed under retiming or resynthesis, but not both. we overcome prior limitation and make complete the equivalence checking for circuits transformed up to retiming+resynthesis+retiming. the theoretical insights lead to a robust satisfiability formulation of verification under various retiming and resynthesis scenarios. experimental results demonstrate the scalability of the approach. several previously unverifiable circuits and unverifiable transformation scenarios can now be verified effectively.
formal verification at higher levels of abstraction. most formal verification tools on the market convert a high-level register transfer level (rtl) design into a bit-level model. algorithms that operate at the bit-level are unable to exploit the structure provided by the higher abstraction levels, and thus, are less scalable. this tutorial surveys recent advances in formal verification using high-level models. we present word-level verification with predicate abstraction and satisfiability modulo theories (smt) solvers. we then describe techniques for term-level modeling and ways to combine word-level and term-level approaches for scalable verification.
automated refinement checking of concurrent systems. stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. for instance, it can be used to build a synthesis approach for digital circuits from high level specifications. it can also be used for post-synthesis modification such as in engineering change orders (ecos). therefore, checking if a system, modeled as a set of concurrent processes, is a refinement of another is of tremendous value. in this paper, we focus on concurrent systems modeled as communicating sequential processes (csp) and show their refinements can be validated using insights from translation validation, automated theorem proving and relational approaches to reasoning about programs. the novelty of our approach is that it handles infinite state spaces in a fully automated manner. we have implemented our refinement checking technique and have applied it to a variety of refinements. we present the details of our algorithm and experimental results. as an example, we were able to automatically check an infinite state space buffer refinement that cannot be checked by current state of the art tools such as fdr. we were also able to check the data part of an industrial case study on the ep2 system.
statistical analysis of rf circuits using combined circuit simulator-full wave field solver approach. as technologies continue to shrink in size, modeling the effect of process variations on circuit performance is assuming profound significance. process variations affect the on-chip performance of both active and passive components. this necessitates the inclusion of the effect of these variations on distributed interconnect structures in modeling overall circuit performance. in this work, first it is shown through field-solver simulations that larger process variations lead to non-gaussian pdfs (probability density functions) for the circuit equivalent parameters of distributed passives. next, a method for accurate statistical analysis of coupled circuit-em (electromagnetic) systems without computing the equivalent circuit parameters of em-modeled objects is demonstrated. this method also obviates the need to generate random variables representing the equivalent circuit parameters, from distributions which are correlated, non-gaussian and non-closed-form. the proposed approach relies on application of the response surface (rs) methodology to the y-parameters of both the circuit and the distributed structures independently and expressing the eventual performance measures through a suitable combination of the y-parameters. the eventual performance measures are expressed through a hierarchical approach in terms of the underlying gaussian random variables representing the process parameters. a rapid response surface monte carlo (rsmc) analysis on these derived response surfaces furnishes the pdfs and can also be used to predict the yield based on different qualifying criteria and objective functions.
intsim: a cad tool for optimization of multilevel interconnect networks. interconnect issues are becoming increasingly important for ulsi systems. intsim, an interconnect cad tool, has been developed to obtain pitches of different wiring levels and die size for circuit blocks or logic cores of microchips. it includes a methodology for co-optimization of signal, power and clock interconnects, and a newly derived stochastic wiring distribution that gives reduced error than prior work when compared to measured data. results of intsim are found to match well with actual data from an analyzed microprocessor. several case studies are conducted to show this cad tool's utility as a system level simulator: (i) wire resistivity increases due to size effects are projected to increase die size of a 22nm low power logic core by 30% and power by 7%. (ii) when compared to a 22nm low power logic core with copper interconnects, a similar logic core with carbon nanotube interconnects could reduce power by 25% and die area by 27%, or increase frequency by 15% and reduce die area by 11%. (iii) a future 22nm 8 ghz 96m gate logic core's power, die size and optimal multilevel interconnect architecture are predicted. a version of intsim with a graphical user interface is available for download from www.ece.gatech.edu/research/labs/gsigroup.
a frequency-domain technique for statistical timing analysis of clock meshes. we propose a frequency-domain modeling technique with applications on the statistical timing analysis of clock mesh/grid networks. using transmission lines to model clock mesh edges, we express the means and (co)variances of the sink arrival times as polynomial functions of the arrival times of the input signals and the wire widths of the mesh edges, with up to second order accuracy. experimental results show that the proposed frequency-domain statistical timing analysis technique is efficient and accurate. the relative mean error is less than 1% and relative variance error less than 3%.
hybrid cegar: combining variable hiding and predicate abstraction. variable hiding and predicate abstraction are two popular abstraction methods to obtain simplified models for model checking. although both methods have been used successfully in practice, no attempt has been made to combine them in counterexample guided abstraction refinement (cegar). in this paper, we propose a hybrid abstraction method that allows both visible variables and predicates to take advantages of their relative strengths. we use refinement based on weakest preconditions to add new predicates, and under certain conditions trade in the predicates for visible variables in the abstract model. we also present heuristics for improving the overall performance, based on static analysis to identify useful candidates for visible variables, and use of lazy constraints to find more effective unsatisfiable cores for refinement. we have implemented the proposed hybrid cegar procedure. our experiments on public benchmarks show that the new abstraction method frequently outperforms the better of the two existing abstraction methods.
large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale cmos digital and high-frequency integrated circuits. modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance is nonlinear and hard to be modeled in current compact models. therefore, a large-scale statistically sound "atomistic" device/circuit coupled simulation approach is proposed to characterize the random-dopant-induced characteristic fluctuations in 16-nm-gate cmos integrated circuits concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations. the variations of transition time of digital circuit (inverter, nand, and nor gates) and high-frequency characteristic of common-source amplifier are estimated. for the digital circuits, the function-dependent and circuit-topology-dependent characteristic fluctuations resulted from random nature of discrete dopants is for the first time discussed. this study provides an insight into random-dopant- induced intrinsic timing and high-frequency characteristic fluctuations. the accuracy of the simulation technique is confirmed by the use of experimentally calibrated transistor physical model.
efficient computation of current flow in signal wires for reliability analysis. electromigration (em) and self-heating are critical reliability concerns for metal wires in high performance designs. em reliability rules for a vlsi technology are typically expressed in terms of average, root-mean-square and peak current limits for each metal layer in the technology. to ensure em reliability of a design, current flowing through each wire segment in the design should not violate the em reliability rules. in this work, we present closed-from analytical models for efficient computation of average, root-mean-square and peak currents through any element in an arbitrary rc tree. the proposed models are validated against spice simulations for several rc nets extracted from an industrial asic design. the results show that the models exhibit very good accuracy with a mean error of only 3.1% in root-mean-square and 0.2% in average current estimation.
yield-aware hierarchical optimization of large analog integrated circuits. hierarchical optimization using building circuit block pareto performance models is an efficient and well established approach for optimizing the nominal performances of large analog circuits. however, the extension to yield-aware hierarchical methodology, as dictated by the need for safeguarding chip manufacturability in scaled technologies, is completely nontrivial. we address two fundamental difficulties in achieving such a methodology: yield-aware pareto performance characterization at the building block level and yield-aware system-level optimization problem formulation. it is shown that our approach is not only able to effectively capture the block performance trade-offs at different yield levels, but also correctly formulate the whole system yield and efficiently perform system-level optimization in presence of process variations. our approach extends the efficiency of hierarchical analog optimization, enjoyed for improving nominal circuit performances, to yield-aware optimization. our methodology is demonstrated by the hierarchical optimization of a phased locked loop (pll) consisting of multiple circuit blocks.
stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions. in this paper we present several results concerning the stabilization of piecewise-linear reduced order models. we include proofs of internal and external stability for models whose system matrices possess special structures. we then introduce a new projection scheme, and a new set of weighting functions which allow us to extend some of these results to piecewise-linear systems comprised of arbitrary matrices, at least one of which is hurwitz. included are an algorithm for creating switching piecewise-linear reduced models comprised of globally exponentially stable systems, and stable simulation results for a system which produces unstable results when using the standard tpwl method.
pars: fast and near-optimal grid-based cell sizing for library-based design. we propose pars, a parallel and randomized tool which solves the discrete gate sizing (cell sizing) problem on a grid. pars is formulated based on an optimization framework known as nested partitions which uses parallelism and randomization from a novel perspective to better identify the optimization direction. it achieves nearoptimal solutions for minimizing total power and area subject to meeting a delay constraint. the embarrassingly-parallel nature of pars makes it highly efficient. we show small algorithm run-times, in at most minutes for circuits with over 47,000 cells. we make comparison with the optimal solution generated by a custom and parallel branch-and-bound algorithm. consequently, we are able to generate the optimal solution within hours. while the optimal algorithm uses up to 200 nodes in our grid, pars achieves its speedups and near-optimal solutions using only 20 nodes.
effective ir-drop reduction in at-speed scan testing using distribution-controlling x-identification. test data modification based on test relaxation and x-filling is the preferable approach for reducing excessive ir-drop in at-speed scan testing to avoid test-induced yield loss. however, none of the existing test relaxation methods can control the distribution of identified don't care bits (x-bits), thus adversely affecting the effectiveness of ir-drop reduction. in this paper, we propose a novel test relaxation method, called distribution-controlling x-identification (dc-xid), which controls the distribution of x-bits identified from a set of fully-specified test vectors for the purpose of effectively reducing ir-drop. experimental results on large industrial circuits demonstrate the effectiveness and practicality of the proposed method in reducing ir-drop, without any impact on fault coverage, test data volume, or test circuit size.
a statistical approach for full-chip gate-oxide reliability analysis. gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. in practice, however, gate-oxide thickness varies from die-to-die and within-die and as the precision of process control worsens an alternative reliability analysis approach is needed. in this work, we propose a statistical framework for chip level gate oxide reliability analysis while considering both die-to-die and within-die components of thickness variation. the thickness of each device is modeled as a distinct random variable and thus the full chip reliability estimation problem is defined on a huge sample space of several million devices. we observe that the full chip oxide reliability is independent of the relative location of the individual devices. this enables us to transform the problem such that the resulting representation can be expressed in terms of only two distinct random variables. using this transformation we present a computationally efficient and accurate approach for estimating the full chip reliability while considering spatial correlations of gate-oxide thickness. we show that, compared to monte carlo simulation, the proposed method incurs an error of only 1~6% while improving the runtime by around three orders.
correct-by-construction microarchitectural pipelining. this paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. our method combines previously known bypass and retiming transformations with a few transformations valid only for elastic systems with early evaluation (namely, empty fifo insertion, fifo capacity sizing, insertion of anti-tokens, and introducing early evaluation multiplexors). by converting the design to a synchronous elastic form and then applying this extended set of transformations, one can pipeline a functional specification with an automatically generated distributed controller that implements stalling logic resolving data hazards off the critical path of the design. we have developed an interactive toolkit for exploring elastic microarchitectural transformations. the method is illustrated by pipelining a few simple examples of instruction set architecture isa specifications.
comprehensive procedure for fast and accurate coupled oscillator network simulation. coupled oscillator networks occur in various domains such as biology, astrophysics and electronics. in this paper, we present a comprehensive procedure for rapid and accurate simulation of large coupled oscillator networks using widely accepted, fully-nonlinear perturbation projection vector (ppv) phase macromodels. we validate our method against full simulation of 20x20 coupled network of brusselator biochemical oscillator and obtain computational speedups of 170x over full simulation. furthermore, we apply the method to study self-organization phenomenon of brusselator under asymmetric coupling and time period variations.
efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. we address the problem of efficient online computation of the speeds of different cores of a multi-core processor to maximize the throughput (which is expressed as a weighted sum of the speeds), subject to an upper bound on the core temperatures. we first compute the solution for steady-state thermal conditions by solving a linear program. we then present two approaches to computing the transient speed curves for each core: (i) a local solution, which involves solving a linear program every time step (of about 10 ms), and (ii) a global solution, which computes the optimal speed curve over a large time window (of about 100 s) by solving a non-linear program. we showed that the local solution is insensitive to the weights assigned in the performance objective (hence the need for the global solution). this is because a reduction in the speed of a core can only reduce the temperature of the other cores over much larger time periods (of the order of several seconds). the local solution is then completely determined by the temperature constraint equations. we show that the constraint matrix exhibits a special property - it can be expressed as the sum of a diagonal matrix and a matrix with identical rows. this allows us to solve the multi-core thermal constraint equations analytically to determine the (temporally) local optimum speeds. further, we showed that due to this property, the steady-state speed solution selects a set of threads to operate at maximum temperature, and turns off all unused cores. hence, to ensure that all available threads are scheduled, we impose a "fairness" constraint. finally, we show how the open-loop speed control methods proposed above could be used together with a feedback controller to achieve robustness to model uncertainty.
diastolic arrays: throughput-driven reconfigurable computing. diastolic arrays are arrays of processing elements that communicate exclusively through first-in first-out (fifo) queues. fifo virtualization units enable relaxed timing of data transfers, and include hardware support to guarantee bandwidth and buffer space for all data transfers, which may follow composite paths through the network. we show that the architecture of diastolic arrays enables efficient synthesis from high-level specifications of communicating finite state machines so average throughput is maximized. preliminary results are presented on an h.264 decoding benchmark.
a capacitance solver for incremental variation-aware extraction. lithographic limitations and manufacturing uncertainties are resulting in fabricated shapes on wafer that are topologically equivalent, but geometrically different from the corresponding drawn shapes. while first-order sensitivity information can measure the change in pattern parasitics when the shape variations are small, there is still a need for a high-order algorithm that can extract parasitic variations incrementally in the presence of a large number of simultaneous shape variations. this paper proposes such an algorithm based on the well-known method of floating random walk (frw). specifically, we formalize the notion of random path sharing between several conductors undergoing shape perturbations and use it as a basis of a fast capacitance sensitivity extraction algorithm and a fast incremental variational capacitance extraction algorithm. the efficiency of these algorithms is further improved with a novel frw method for dealing with layered media. our numerical examples show a 10x speed up with respect to the boundary-element method adjoint or finite-difference sensitivity extraction, and more than 560x speed up with respect to a non-incremental frw method for a high-order variational extraction.