waashk/dblp huggingface dataset:
resilience in computer systems and networks. the term resilience is used differently by different communities. in general engineering systems, fast recovery from a degraded system state is often termed as resilience. computer networking community defines it as the combination of trustworthiness (dependability, security, performability) and tolerance (survivability, disruption tolerance, and traffic tolerance). dependable computing community defined resilience as the persistence of service delivery that can justifiably be trusted, when facing changes. in this paper, resilience definitions of systems and networks will be presented. metrics for resilience will be compared with dependability metrics such as availability, performance, performability. simple examples will be used to show quantification of resilience via probabilistic analytic models.
grema: graph reduction based efficient mask assignment for double patterning technology. double patterning technology (dpt) has emerged as the most hopeful candidate for the next technology node of the itrs roadmap [1]. the goal of a dpt decomposer is to decompose the entire layout on each layer onto two masks. it assigns two features to different masks if their spacing is less than a predefined threshold. besides, some features must be sliced and put onto two masks so that there would be a feasible solution for mask assignment. such slicing will cause stitches that affect yield. so decomposer needs to minimize their number. in this paper, we formulate the dpt decomposition problem as a maximum cut problem. we propose an extremely efficient two-stage decomposition algorithm called grema. the first stage of grema generates a set of candidate stitches to ensure that feasible solutions exist for dpt decomposition. the second stage uses maximum cut to find the minimal set of stitches. our decomposer is able to solve much larger realistic design problems. experiments demonstrated that grema achieved great performance on resolving conflicts with greatly reduced runtime.
characterizing within-die variation from multiple supply port iddq measurements. the importance of within-die process variation and its impact on product yield has increased significantly with scaling. within-die variation is typically monitored by embedding characterization circuits in product chips. in this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die variation. the proposed technique monitors within-die variation by measuring quiescent (iddq) currents at multiple power supply ports during wafer-probe test. we show that the spatially distributed nature of power ports enables spatial observation of process variation. we demonstrate our methodology on an experimental test-chip fabricated in 65-nm technology. the measurement results show that the iddq currents drawn by multiple power supply ports correlate very well with the variation trends introduced by state-dependent leakage patterns.
retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits. pulsed-latches take advantage of both latches in their high performance and flip-flops in their convenience of timing analysis. to minimize the clock period of pulsed-latch-based circuits for a higher performance, a problem of combined retiming and time borrowing is formulated, where the latter is enabled by using a handful of different pulse widths. the problem is first approached by formulating it as an integer linear programming to lay a theoretical foundation. a heuristic approach is proposed, which solves the problem by performing clock skew scheduling for the minimum clock period and gradually converting skew into a combination of retiming and time borrowing. experiments with 45-nm technology demonstrate that the clock period close to the minimum can be achieved for all benchmark circuits with an average of 1.03x with less use of extra latches compared to the conventional retiming.
pre-bond testable low-power clock tree design for 3d stacked ics. pre-bond testing of 3d stacked ics involves testing individual dies before bonding. the overall yield of 3d ics improves with prebond testability because designers can avoid stacking defective dies with good ones. however, pre-bond testability presents unique challenges to 3d clock tree design. first, each die needs a complete 2d clock tree for the pre-bond testing. in addition, the entire 3d stack needs a complete 3d clock tree for post-bond testing and normal operations. in the case of two-die stack, a straightforward solution is to have two complete 2d clock trees connected with a single through-silicon-via (tsv). we show that this solution suffers from long wirelength and high clock power consumption. instead, our algorithm minimizes the overall wirelength and clock power consumption while providing the pre-bond testability and post-bond operability under given skew and slew constraints. compared with the single-tsv solution, spice simulation results show that our multi-tsv approach significantly reduces the clock power by up to 15.9% for two-die and 29.7% for four-die stack. in addition, the wirelength reduction is up to 24.4% and 42.0%.
yield estimation of sram circuits using "virtual sram fab". static random access memories (srams) are key components of modern vlsi designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. we present a computational framework, referred to as "virtual sram fab", for analyzing and estimating pre-si sram array manufacturing yield considering both lithographic and electrical variations. the framework is being demonstrated for sram design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. the application and merit of the framework are illustrated using two different sram cells in a 45nm pd/soi technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. we also demonstrate the application of virtual sram fab for prediction of layout-induced imbalance in an 8t cell, which is a popular candidate for sram implementation in 32-22nm technology nodes.
gene-regulatory memories: electrical-equivalent modeling, simulation and parameter identification. the development of gene-regulatory memory circuits provides key understandings of biological information storage and enables new biological applications. computer models and simulations can provide quantitative analysis and prediction of the behaviors and functions of genetic networks, thereby providing valuable verification and design guidance. in this paper, we model the nonlinear dynamics associated with various chemical reactions in gene-regulatory memory networks using chemical reaction equations. these reaction equations are mapped into a set of electrical-equivalent models and the network is simulated by an extended spice-like circuit simulation environment. furthermore, we address the practical difficulty in direct characterization of network model parameters by developing a simulation-driven bayesian framework for parameter identification. to ensure the reliable identification of key system properties, we propose a two-step structure-preserving parameter identification approach. the first step infers bistability, the most critical characteristics of a memory device; and the second step is geared towards identifying dynamical properties of the network while maintaining the identified bistability. we demonstrate the proposed approaches through extensive simulations that well agree with established biological understandings and identified networks that recreate measured circuit responses in a statistical sense.
a parallel preconditioning strategy for efficient transistor-level circuit simulation. we describe a parallel computing approach for large-scale spice-accurate circuit simulation, which is based on a new strategy for the parallel preconditioned iterative solution of circuit matrices. this strategy consists of several steps, including singleton removal, block triangular form (btf) reordering, hypergraph partitioning, and a block jacobi pre-conditioner. our parallel implementation makes use of a mixed load balance, employing a different parallel partition for the matrix load and solve. based on message-passing, our circuit simulation code was originally designed for large parallel computers, but for the purposes of this paper we demonstrate that it also gives good parallel speedup in modern multi-core environments. we show that our new parallel solver outperforms a serial direct solver, a parallel direct solver and an alternative iterative solver on a set of circuit test problems.
generation of optimal obstacle-avoiding rectilinear steiner minimum tree. in this paper, we present an efficient method to solve the obstacle-avoiding rectilinear steiner tree problem optimally. our work is developed based on the geosteiner approach, modified and extended to allow rectilinear blockages in the routing region. we extended the proofs on the possible topologies of full steiner tree (fst) in [4] to allow blockages, where fst is the basic concept used in geosteiner. we can now handle hundreds of pins with multiple blockages, generating an optimal solution in a reasonable amount of time. this work serves as a pioneer in providing an optimal solution to this difficult problem.
nanoelectromechanical (nem) relays integrated with cmos sram for improved stability and low leakage. we present a hybrid nanoelectromechanical (nem)/cmos static random access memory (sram) cell, in which the two pull-down transistors of a conventional cmos six transistor (6t) sram cell are replaced with nem relays. this sram cell utilizes the infinite subthreshold slope and hysteretic properties of nem relays to dramatically increase the cell stability compared to the conventional cmos 6t sram cells. it also utilizes the zero off-state leakage of nem relays to significantly decrease static power dissipation. the structure is designed so that the relatively long mechanical delay of the nem relays does not result in performance degradation. circuit simulations are performed using a veriloga model of a nem relay. compared to a 65nm cmos 6t sram cell, when 10nm-gap nem relays (pull-in voltage = 0.8v, pull-out voltage = 0.2v, on resistance = 1k&omega;) are integrated, hold and read static noise margin (snm) improve by ~110% and ~250%, respectively. in addition, static power dissipation decreases by ~85%. the write delay decreases by ~60%, while read delay decreases by ~10%. the advantages in snm and static power dissipation are expected to increase with scaling.
interpolant generation without constructing resolution graph. in this paper, we proposed a novel interpolant generation algorithm without constructing the resolution graph of the unsatisfiability proof. our algorithm generates the interpolant by building sub-interpolants from conflict analyses and then merges them based on the last decision conflict. the experimental results show that our algorithm has the advantages over the prior interpolant generation techniques in both memory usage and interpolation circuit size.
an electrical-level superposed-edge approach to statistical serial link simulation. brute-force simulation approaches to estimating serial-link bit-error rates (bers) become computationally intractable for the case when bers are low and the interconnect electrical response is slow enough to generate intersymbol interference that spans dozens of bit periods. electrical-level statistical simulation approaches based on superposing pulse responses were developed to address this problem, but such pulse-based methods have difficulty analyzing jitter and rise/fall asymmetry. in this paper we present a superposing-edge approach for statistical simulation, as edge-based methods handle rise/fall asymmetry and jitter in straightforward way. we also resolve a key problem in using edge-based approaches, that edges are always correlated, by deriving an efficient inductive approach for propagating the edge correlations. examples are presented demonstrating the edge-based method's accuracy and effectiveness in analyzing combinations of uniform, gaussian, and periodic distributed random jitter.
memory organization and data layout for instruction set extensions with architecturally visible storage. present application specific embedded systems tend to choose instruction set extensions (ises) based on limitations imposed by the available data bandwidth to custom functional units (cfus). adoption of the optimal ise for an application would, in many cases, impose formidable cost increase in order to achieve the required data bandwidth. in this paper we propose a novel methodology for laying out data in memories, generating high-bandwidth memory systems by making use of existing low-bandwidth low-cost ones and designing custom functional units all with the desirable data bandwidth for only a fraction of the additional cost required by traditional techniques.
a study of through-silicon-via impact on the 3d stacked ic layout. through-silicon-via (tsv) is the enabling technology for the fine-grained 3d integration of multiple dies into a single stack. these tsvs occupy non-negligible silicon area because of their sheer size. this significant silicon area occupied by the tsvs and the interconnections made to the tsvs greatly affect area, power, performance, and reliability of 3d ic layouts. well-managed tsvs alleviate congestion, reduce wirelength, and improve performance, whereas excessive tsvs not only increase the die area, but also have negative impact on many design objectives. in this paper, we study the impact of tsv on various aspects of 3d layouts. we use gdsii layouts of 2d and 3d designs, and thoroughly compare the pros and cons of tsv usage. we propose a new force-directed 3d gate-level placement that efficiently handles tsvs. in addition, we present an algorithm that assigns tsvs to nets to complete routing that involves tsvs. this algorithm, together with our 3d placer, is integrated into a commercial p&r tool to generate fully validated gdsii layouts. our experiments based on synthesized benchmarks indicate that our algorithms help generate gdsii layouts of 3d designs that are optimized in terms of area, wirelength, and metal layer count.
exact route matching algorithms for analog and mixed signal integrated circuits. as soc designs are getting more popular, the importance of design automation for analog and mixed-signal ics is increasing. in this paper, we study the problem of exact route matching, which is an important physical design constraint commonly imposed on specific analog signals for the purpose of correct analog functionality. for this, we first propose a mathematical formulation that models the route matching problem exactly. based on this formulation, we derive important theoretical conclusions, and propose dynamic-programming algorithms to solve the problem. we also discuss how to use heuristic search techniques to enable faster computations. our experimental results show the effectiveness of our algorithms.
improved heuristics for finite word-length polynomial datapath optimization. conventional high-level synthesis techniques are not able to manipulate polynomial expressions efficiently due to the lack of suitable optimization techniques for redundancy elimination over z2n. this paper, in comparison with [1], presents 1) an improved partitioning heuristic based on single-variable monomials instead of checking all sub-polynomials, 2) an improved compensation heuristic which is able to compensate monomials as well as coefficients, and 3) a combined area-delay-optimized factorization approach to extract the most frequently used sub-expressions from multi-output polynomials over z2n. experimental results have shown an average saving of 32% and 27.2% in the number of logic gates and critical path delay respectively compared to the state-of-the-art techniques. regarding the comparison with [1], the number of gates and delay are improved by 14.3% and 13.9% respectively. furthermore, the results show that the combined area-delay optimization can reduce the average delay by 26.4%.
adaptive sampling for efficient failure probability analysis of sram cells. in this paper, an adaptive sampling method is proposed for the statistical sram cell analysis. the method is composed of two components. one part is the adaptive sampler that manipulates an alternative sampling distribution iteratively to minimize the estimated yield error. the drifts of the sampling distribution are re-configured in each iteration toward further minimization of the estimation variance by using the data obtained from the previous circuit simulations and applying a high-order householder's method. secondly, an analytical framework is developed and integrated with the adaptive sampler to further boost the efficiency of the method. this is achieved by the optimal initialization of the alternative multi-variate gaussian distribution via setting its drift vector and covariance matrix. the required number of simulation iterations to obtain the yield with a certain accuracy is several orders of magnitude lower than that of the crude-monte carlo method with the same confidence interval.
fast detection of node mergers using logic implications. in this paper, we propose a new node merging algorithm using logic implications. the proposed algorithm only requires two logic implications to find the substitute nodes for a given target node, and thus can efficiently detect node mergers. furthermore, we also apply the node merger identification algorithm for area optimization in vlsi circuits. we conduct experiments on a set of iwls 2005 benchmarks. the experimental results show that our algorithm has a competitive capability on area optimization compared to a global observability don't care (odc)-based node merging algorithm which is highly time-consuming. our speedup is approximately 86 times for overall benchmarks.
timing model extraction for sequential circuits considering process variations. as semiconductor devices continue to scale down, process variations become more relevant for circuit design. facing such variations, statistical static timing analysis is introduced to model variations more accurately so that the pessimism in traditional worst case timing analysis is reduced. because all delays are modeled using correlated random variables, most statistical timing methods are much slower than corner based timing analysis. to speed up statistical timing analysis, we propose a method to extract timing models for flip-flop and latch based sequential circuits respectively. when such a circuit is used as a module in a hierarchical design, the timing model instead of the original circuit is used for timing analysis. the extracted timing models are much smaller than the original circuits. experiments show that using extracted timing models accelerates timing verification by orders of magnitude compared to previous approaches using flat netlists directly. accuracy is maintained, however, with the mean and standard deviation of the clock period both showing usually less than 1% error compared to monte carlo simulation on a number of benchmark circuits.
operating system scheduling for efficient online self-test in robust systems. very thorough online self-test is essential for overcoming major reliability challenges such as early-life failures and transistor aging in advanced technologies. this paper demonstrates the need for operating system (os) support to efficiently orchestrate online self-test in future robust systems. experimental data from an actual dual quad-core system demonstrate that, without software support, online self-test can significantly degrade performance of soft real-time and computation-intensive applications (by up to 190%), and can result in perceptible delays for interactive applications. to mitigate these problems, we develop os scheduling techniques that are aware of online self-test, and schedule/migrate tasks in multi-core systems by taking into account the unavailability of one or more cores undergoing online self-test. these techniques eliminate any performance degradation and perceptible delays in soft real-time and interactive applications (otherwise introduced by online self-test), and significantly reduce the impact of online self-test on the performance of computation-intensive applications. our techniques require minor modifications to existing os schedulers, thereby enabling practical and efficient online self-test in real systems.
a novel post-atpg ir-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. reducing ir-drop in the test cycle during at-speed scan testing has become mandatory for avoiding test-induced yield loss. an efficient approach for this purpose is post-atpg test modification based on x-identification and x-filling since it causes no circuit/clock design change and no test vector count inflation. however, applying this approach to test compression has been considered challenging due to the limited availability of x-bits. this paper solves this serious problem by proposing a novel and practical ca (compression-aware) test modification scheme for reducing ir-drop in the widely-used broadcast-scan based test compression environment. this unique scheme features (1) ca circuit remodeling for minimizing the effort of applying test modification to broadcast-scan-based test compression, (2) ca x-identification for increasing x-bits for risky test vectors, and (3) ca x-filling for effectively using limited x-bits in reducing ir-drop. as a result, the ca test modification scheme can achieve significant ir-drop reduction even when a test cube only has a small number of x-bits. this advantage is clearly demonstrated by experimental results on three compression configurations created from an industrial circuit.
a scalable decision procedure for fixed-width bit-vectors. efficient decision procedures for bit-vectors are essential for modern verification frameworks. this paper describes a new decision procedure for the core theory of bit-vectors that exploits a reduction to equality reasoning. the procedure is embedded in a congruence closure algorithm, whose data structures are extended in order to efficiently manage the relations between bit-vector slicings, modulo equivalence classes. the resulting procedure is incremental, backtrackable, and proof producing: it can be used as a theory-solver for a lazy smt schema. experiments show that our approach is comparable and often superior to bit-blasting on the core fragment, and that it also helps as a theory layer when applied over the full bit-vector theory.
security against hardware trojan through a novel application of design obfuscation. malicious hardware trojan circuitry inserted in safety-critical applications is a major threat to national security. in this work, we propose a novel application of a key-based obfuscation technique to achieve security against hardware trojans. the obfuscation scheme is based on modifying the state transition function of a given circuit by expanding its reachable state space and enabling it to operate in two distinct modes -- the normal mode and the obfuscated mode. such a modification obfuscates the rareness of the internal circuit nodes, thus making it difficult for an adversary to insert hard-to-detect trojans. it also makes some inserted trojans benign by making them activate only in the obfuscated mode. the combined effect leads to higher trojan detectability and higher level of protection against such attack. simulation results for a set of benchmark circuits show that the scheme is capable of achieving high levels of security at modest design overhead.