waashk/dblp huggingface dataset:
logic decomposition during technology mapping. a problem in technology mapping is that quality of the final implementation depends significantly on the initially provided circuit structure. to resolve this problem, conventional techniques iteratively but separately apply technology independent transformations and technology mapping.in this paper, we propose a procedure which performs logic decomposition and technology mapping simultaneously. we show that the procedure effectively explores all possible algebraic decompositions. it finds an optimal tree implementation over all the circuit structures examined, while the run time is typically logarithmic in the number of decompositions.
design based analog testing by characteristic observation inference. in this paper, a new approach to analog test design based on the circuit design process, called characteristic observation inference (coi), is presented. in many situations, it is prohibitive to directly verify the circuit specifications due to the test equipment costs. our approach considers a given universal set of reasonable input stimuli and measurements that can be performed with the given test equipment. from this universal set, a minimal number of measurements is automatically selected that represent a set of observations characterizing the state of the circuit under test with respect to parametric faults. a parametric fault model is introduced which is related to the individual circuit specifications. for each given circuit specification, a corresponding test inference criterion is computed, based on logistic discrimination analysis. by applying these criteria, the satisfaction or violation of the given circuit specifications can be inferred from the observations of the circuit under test. the coi method applied to a complex operational amplifier yields very encouraging simulated results with respect to parametric faults as well as to catastrophic faults.
basic concepts for an hdl reverse engineering tool-set. designer's productivity has become the key-factor of the development of electronic systems. an increasing application of design data reuse is widely recognized as a promising technique to master future design complexities. since the intellectual property of a design is more and more kept in software-like hardware description languages (hdl), successful reuse depends on the availability of suitable hdl reverse engineering tools. this paper introduces new concepts for an integrated hdl reverse engineering tool-set and presents an implemented evaluation prototype for vhdl designs. starting from an arbitrary collection of hdl source code files, several graphical and textual views on the design description are automatically generated. the tool-set provides novel hypertext techniques, expressive graphical code representations, a user-defined level of abstraction, and interactive configuration mechanisms in order to facilitate the analysis, adoption and upgrade of existing hdl designs.
path selection and pattern generation for dynamic timing analysis considering power supply noise effects. noise effects such as power supply and crosstalk can significantly affect the performance of deep submicron designs. these delay effects are highly input pattern dependent. existing path selection and timing analysis techniques cannot capture the effects of noise on cell/interconnect delays. therefore, the selected critical paths may not be the longest paths and predicted circuit performance might not reflect the worst-case circuit delay. in this paper, we propose a path selection technique that can consider power supply noise effects on the propagation delays. next, for the selected critical paths, we propose a pattern generation technique for dynamic timing analysis such that the patterns produce the worst-case power supply noise effects on the delays of these paths. our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered vs. when these effects are ignored. thus, they validate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.
clock tree synthesis for multi-chip modules. while designing interconnect for mcm's, one must take into consideration the distributed rlc effects, due to which signals may display nonmonotonic behavior and substantial ringing. this paper considers the problem of designing clock trees for mcm's. a fully distributed rlc model is utilized for awe-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. experimental results, verified by spice simulations, show that this method can be used to build clock trees with near-zero skews.
on theoretical and practical considerations of path selection for delay fault testing. in current industrial practice, critical path selection is an indispensable step for ac delay test and timing validation. traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. the assumption of discrete timing models can be invalidated by delay effects in the deep sub-micron domain, where timing defects and process variation are statistical in nature. in this paper, we study the problem of optimizing critical path selection, under both fixed delay and statistical delay assumptions. with a novel problem formulation and new theoretical results, we prove that the problem in both cases are computationally intractable. we then discuss practical heuristics and their theoretical performance bounds, and demonstrate that among all heuristics under consideration, only one is theoretically feasible. finally, we provide consistent experimental results based upon defect-injected simulation using an efficient statistical timing analysis framework.
analog circuit sizing based on formal methods using affine arithmetic. we present a novel approach to optimization-based variation-tolerant analog circuit sizing. using formal methods based on affine arithmetic, we calculate guaranteed bounds on the worst-case behavior and deterministically find the global optimum of the sizing problem by means of branch-and-bound optimization. to solve the nonlinear circuit equations with parameter variations, we define a novel affine-arithmetic newton operator that gives a significant improvement in computational efficiency over an implementation using interval arithmetic. the calculation of guaranteed worst-case bounds and the global optimization are demonstrated by a prototype implementation.
cad challenges in multimedia computing. abstract: this tutorial surveys the present and future of multimedia computing systems and outlines new challenges for cad presented by these systems. multimedia computing is a challenging domain for several reasons: it requires both high computation rates and memory bandwidth; it is a multirate computing problem; and requires low-cost implementations for high-volume markets. as a result, the design of multimedia computing systems introduces new challenges for cad at all levels of abstraction, ranging from layout to system design. after surveying the nature of the multimedia computing problem, we examine two experiences in multimedia computer design from a cad perspective: the design of vlsi systems-on-chips for multimedia: and the successive refinement of an application from software to a high-volume chip using advanced cad synthesis tools.
spider: simultaneous post-layout ir-drop and metal density enhancement with redundant fill. this paper presents spider, a novel methodology that advantageously utilizes metal fill to simultaneously fulfil metal density requirements and reduce ir-drop of the power distribution network. this is achieved through the addition of partially redundant connections between metal fills and power meshes. our technique is especially significant for 90nm process technology or below because (1) metal fill must now be done as part of the ic implementation flow due to its increasing impact on timing, (2) the tolerance for ir drop is tightening due to voltage scaling, and the increasingly conservative power mesh design to address ir-drop is adding significant burden on the available routing resources, (3) ir-drop is getting worse due to increasing design sizes, and (4) the large degree of design uncertainty demands irdrop repair capabilities that can be applied after routing is completed. spider addresses all these issues practically with little or no cost. experimental results further demonstrated the robustness and effectiveness of our approach: spider achieves an average ir-drop reduction of 62.2% in 16 designs of various sizes.
an efficient method for improving the quality of per-test fault diagnosis. per-test fault diagnosis methodology has been shown to be an effective one for the identification of complex defects. we improve a recent per-test technique by applying additional diagnosis on the outputs of the circuit. the new method brings in more evidence to support the true failures, hence improves the diagnostic quality. we show that this method can very well address several problems in previous work.
what is the limit of energy saving by dynamic voltage scaling? dynamic voltage scaling (dvs) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amount of energy consumption. it has been demonstrated as one of the most effective low power system design techniques, in particular for real time systems. previously, there are works on both ends of the dvs systems: the ideal variable voltage system which can change its voltage with no physical constraints, and the multiple voltage system which has a number of discrete voltages available simultaneously. in this paper, we study the dvs systems between these two extreme cases. we consider systems that can vary the operating voltage dynamically under various real-life physical constraints. based on the system's different behavior during voltage transition, we define the feasible dvs system and the practical dvs system. we build mathematical model to analyze the potential of dvs on energy saving for these different systems. finally, we simulate the behavior of a secure wireless communication networks with dvs systems. the results show that dvs results in energy reduction from 36% to 79%, and the real life dvs systems can be very close to the ideal system in energy saving.
algorithms for address assignment in dsp code generation. this paper presents dsp code optimization techniques, which originate from dedicated memory address generation hardware. we define a generic model of dsp address generation units. based on this model, we present efficient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. improvements and generalizations of previous work are described, and the efficacy of the proposed algorithms is demonstrated through experimental evaluation.
energy optimization of distributed embedded processors by combined data compression and functional partitioning. transmitting compressed data can reduce inter-processor communicationtraffic and create new opportunities for dvs (dynamicvoltage scaling) in distributed embedded systems. however, datacompression alone may not be effective unless coordinated withfunctional partitioning. this paper presents a dynamic programmingtechnique that combines compression and functional partitioningto minimize energy on multiple voltage-scalable processorsrunning pipelined data-regular applications under performance constraints.our algorithm computes the optimal functional partitioning,cpu speed for each node, and their respective compression ratios.we validate the algorithm's effectiveness on a real distributedembedded system running an image processing algorithm.
function inlining under code size constraints for embedded processors. function inlining is a compiler optimization that generally increases performance at the expense of larger code size. however, current inlining techniques do not meet the special demands in the design of embedded systems, since they are based on simple heuristics, and they generate code of unpredictable size. this paper presents a novel approach to function inlining in c compilers for embedded processors, which aims a maximum program speedup under a global limit on code size. the core of this approach is a branch-and-bound algorithm which allows to quickly explore the large search space. in an application study we show how this algorithm can be applied to maximize the execution speed of an application under a given code size constraint.
optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization. new embedded systems offer rich power management features in the form of multiple operational and nonoperational power modes. while they offer mechanisms for better energy efficiency, they also complicate power management decisions in the presence of realtime constraints. a traditional dynamic power management techniques based on localized break-even-time analysis with simple on/off power controls often yield suboptimal if not incorrect results globally. to address these problems, this work presents two core algorithms for reducing idle energy consumption at the component level and system level. the first algorithm discovers the optimal sequence for mode transition over multiple power modes under timing constraints. it assists the second algorithm that performs a sophisticated global search strategy to aggressively explore system-wide energy savings by correctly interpreting the constraints across all subsystems. experimental results show that in an embedded radio system where idle energy cost matches or exceeds the active energy consumption, our technique can further reduce the idle energy by 50-70%, which translates into 30-50% of overall system energy compared to existing techniques.
verifying correct pipeline implementation for microprocessors. we introduce a general, automatic verification technique for pipelined designs. the technique is based on a scalable, formal methodology for analyzing pipelines. the key advantages to our technique are: it specifically targets pipeline control, making it more efficient; it requires no explicit specification, since it compares hardware against itself; it can be used within the broader framework of hierarchical verification; and, it can be easily extended to handle certain "complex" pipelined structures.
a behavioral signal path modeling methodology for qualitative insight in and efficient sizing of cmos opamps. this paper describes a new modeling methodology that allows to derive systematically behavioral signal path models of operational amplifiers. combined with symbolic simulation, these models provide high qualitative insight in the small-signal functioning of a circuit. the behavioral signal path model provides compact interpretable expressions for the poles and zeros that constitute the signal path. these expressions show which design parameters have dominant influence on the position of a pole/zero and thus enable a designer to control a manual interactive sizing process. the methodology consists of the application of a sequence of abstractions, so that one gradually progresses from a full device to a full behavior circuit representation. during this translation, qualitative insight and design requirements are obtained. the methodology is implemented in an open tool called \eftoef. the behavioral signal path model is also used for optimization based sizing in order to achieve pole placement in an efficient way. for optimization based sizing, a new strategy for hierarchical penalty function composition is proposed, which allows sequential pruning of the design space. combined with an operating point driven \dc formulation and local minimax optimization, a fast sizing method is obtained which can be used for interactive design space exploration. experimental results of both modeling and sizing are shown.
efficient performance estimation for general real-time task systems. the paper presents a novel approach to compute tight upper bounds on the processor utilization independent of the implementation for general real-time systems where tasks are composed of subtasks and precedence constraints may exist among subtasks of the same task. we formulate the problem as a set of linear programming (lp) problems. observations are made to reduce the number of lp problem instances required to be solved, which greatly improves the computation time of the utilization bounds. furthermore, additional constraints are allowed to be included under certain circumstances to improve the quality of the bounds.
a delay metric for rc circuits based on the weibull distribution. physical design optimizations such as placement, interconnect synthesis, oorplanning, and routing require fast and accurate analysis of rc networks. because of its simple close form and fast evaluation, the elmore delay metric has been widely adopted. the recently proposed delay metrics primo and h-gamma match the rst three circuit moments to the probability density function of a gamma statistical distribution. although these methods demonstrate impressive accuracy compared to other delay metrics, their implementations tend to be challenging. as an alternative to matching to the gamma distribution, we propose to match the rst two circuit moments to a weibull distribution. the result is a new delay metric called weibull based delay (wed). the primary advantages of wed over primo and h-gamma are its efciency and ease of implementation. experiments show that wed is robust and has satisfactory accuracies at both near and far-end nodes.
compiler-directed voltage scaling on communication links for reducing power consumption. reducing power consumption of communication networks is an important optimization goal in many application domains, ranging from large-scale simulation codes to embedded multi-media applications. most of the prior efforts on network power optimization are hardware-based schemes. these schemes are predictive by definition as they control communication link status based on the observations made in the past. since prediction may not be very accurate most of the time, these approaches can result in overheads in terms of both performance and power. this paper proposes a compiler driven approach to communication link voltage management. in this approach, an optimizing compiler analyzes the application code and extracts the data communication pattern among parallel processors. this information along with network topology is used for identifying the link access patterns. these patterns and the inherent data dependence information of the underlying code help the compiler decide the optimum voltages/frequencies to be used for communication links at a given time frame. our focus in this work is on loop-intensive codes which frequently appear in data intensive video and image processing. we exploit the regularity in data accesses of these codes to abstract out their inter-processor communication patterns, which in turn enable us select the most appropriate voltage/frequency level to employ for each communication link at any time.
a gradient method on the initial partition of fiduccia-mattheyses algorithm. in this paper, a fiduccia-mattheyses (fm) algorithm incorporating a novel initial partition generating method is proposed. the proposed algorithm applies to both bipartitioning and multi-way partitioning problems with or without replication. the initial partition generating method is based on a gradient decent algorithm. on partitioning without replication, our algorithm achieves an average of 17% improvement over the analytical method, paraboli, on bipartitioning, 10% better than primal-dual method on 4-way partitioning and 51% better than net-based method. on partitioning allowing replication, our algorithm achieves an average of 23% improvement over the directed fiduccia-mattheyses algorithm on replication graph (fmrg) method on bipartitioning.
improving scratch-pad memory reliability through compiler-guided data block duplication. recent trends in embedded computing indicates an increasing use of scratch-pad memories (spms) as on-chip store for instructions and data. an important characteristic of these memory components is that they are managed by software, instead of hardware. ever-scaling process technology and employment of several power-saving techniques in embedded systems (e.g., voltage scaling) make these systems particularly vulnerable to soft errors and other transient errors. therefore, it is very important in practice to consider the impact of soft errors in spms. while it is possible to employ classical memory protection mechanisms such as parity checks and ecc, each of these has its drawbacks. specifically, a pure parity-based protection cannot correct any errors, and eccs can be an overkill in the normal operation state when no soft error is experienced. this paper proposes an alternate approach to protect spms against soft errors. the proposed approach is based on data block duplication under compiler control. more specifically, an optimizing compiler duplicates data blocks within the spm and protects each data block by parity if such a duplication does not hurt performance. the goal of this scheme is to provide only parity protection for data blocks (and reduce the overheads at runtime when no error occurs) but correct errors using the duplicate (when an error occurs in the primary copy), provided that the duplicate is not corrupted.
cama: a multi-valued satisfiability solver. this paper presents the multi-valued sat solver cama. camageneralizes the recently developed speed-up techniques usedin state-of-the-art binary sat solvers, such as the two-literal-watching scheme for boolean constraint propagation (bcp), conflict-based learning with identifying the first unique implication point (uip), and non-chronological back-tracking. in addition, a novel minimum value set (mvs) technique is introduced for improving the efficiency of conflict-based learning. by analyzing the conflict clauses, mvs can potentially prune conflictingspace that has not been searched before. two different decisionheuristics are discussed and evaluated. finally the performanceof cama is compared with chaff using on a one-hot-encodingscheme. the experimental results show that, for mv-sat problemswith large variable domains, cama outperforms chaff.
comprehensive frequency-dependent substrate noise analysis using boundary element methods. we present a comprehensive methodology for the electrodynamic modeling of substrate noise coupling. a new and efficient method is introduced for the calculation of the green's function that can accommodate arbitrary substrate doping profiles and thus facilitate substrate noise analysis using boundary element methods. in addition to a discussion of the application of the method and its validation in the context of substrate transfer resistance extraction, preliminary results from its application to frequency-dependent substrate noise modeling are presented also.
diagnosis of small-signal parameters for broadband amplifiers through s-parameter measurements and sensitivity-guided evolutionary search. with increasing uncertainties in the modeling and processing of semiconductor devices, it is essential that the sources of failures be identified once the devices are manufactured. we present a methodology to diagnose the problems in broadband amplifiers by determining the most important small signal parameters of the internal transistors. we use an evolutionary algorithm specifically designed to mimic the expected errors to ensure fast convergence to the correct solution. sensitivity analysis is used to determine the set of the most impactful small signal parameters and to guide the evolutionary search. experimental results indicate the proposed algorithm determines the parameters accurately and it scales well in terms of accuracy and computation time.