waashk/dblp huggingface dataset:
a spectrally accurate integral equation solver for molecular surface electrostatics. electrostatic analysis of complicated molecular surfaces arises in a number of nanotechnology applications including: biomolecule design, carbon nanotube simulation, and molecular electron transport. molecular surfaces are typically smooth, without the corners common in electrical interconnect problems, and are candidates for methods with higher order convergence than that of the commonly used flat panel methods. in this paper we describe and demonstrate a spectrally accurate approach for analyzing molecular surfaces described by a collection of surface points. the method is a synthesis of several techniques, and starts by using least squares to fit a high order spherical harmonic surface representation to the given points. then this analytic representation is used to construct a differentiable map from the molecular suface to a cube, an orthogonal basis is generated on the rectangular cube surfaces, and a change of variables is used to desingularize the required integrals of products of basis functions and green's function. finally, an efficient method for solving the discretized system using a matrix-implicit scheme is described. the combined method is demonstrated on an analytically solvable sphere problem, capacitance calculation of complicated molecular surface, and a coupled poisson/poisson-boltzmann problem associated with a biomolecule. the results demonstrate that for a tolerance of 10-3 this new approach requires one to two orders of magnitude fewer unknowns than a flat panel method.
optimal useful clock skew scheduling in the presence of variations using robust ilp formulations. this paper exploits useful skew to improve system performance and robustness. we formulate a robust integer linear programming problem considering the interactions between data and clock paths on a microprocessor chip to improve clock frequency. the timing slack is optimized for each path to determine a clock schedule. the percentage of timing violations, obtained from a 1000 point monte carlo simulation, is higlighted as yield predictions and conveys the robustness of the clock schedule. the results show performance improvement of up to 9.747% with 20% yield and up to 6.682% with 100% yield. the novelty of the proposed method is its ability to tradeoff between performance improvement in frequency and robustness, via a single variable in the formulation.
parameterized model order reduction via a two-directional arnoldi process. this paper presents a multiparameter moment-matching based model order reduction technique for parameterized interconnect networks via a novel two-directional arnoldi process. it is referred to as a pimtap algorithm, which stands for parameterized interconnect macromodeling algorithm via a two-directional arnoldi process. pimtap inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. it is numerically stable and adaptive, and preserves the passivity of parameterized rlc networks.
optimal bus sequencing for escape routing in dense pcbs. the pcb routing problem has become so difficult that no commercial cad software can provide an automatic solution for high-end boards. existing algorithms for escape routing, an important step in pcb routing, are net-centric. directly applying these algorithms will result in mixing nets of different buses together. but in practice, it is preferred to bundle together nets in a bus. thus the bus-centric escape routing problem can be naturally divided into two subproblems: (1) finding a subset of buses that can be routed on the same layer without net mixings and crossings, which we refer to as the bus sequencing problem, and (2) finding the escape routing solutions for each chosen bus, which can be solved by a net-centric escape router. in this paper, we solve the bus sequencing problem. we introduce a new optimization problem called the longest common interval sequence (lcis) problem and model the bus sequencing problem as an lcis problem. by using dynamic programming and balanced search tree data structure, we present an lcis algorithm which can find an optimal solution in o(n log n) time. we also show that o(n log n) is a lower-bound for this problem and thus the time complexity of our algorithm is also the best possible.
a selective pattern-compression scheme for power and test-data reduction. this paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. the proposed scheme will selectively supply the test patterns either through the compressed scan chain whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using minimum transition filling method. due to shorter length of a compressed scan chain, the potential switching activities and the required storage bits can be both reduced. furthermore, the proposed scheme also supports multiple scan chains. the experimental results demonstrate that, with few hardware overhead, the proposed scheme can achieve significant improvement in shift-in power reduction and large amount of test data volume reduction.
can nano-photonic silicon circuits become an intra-chip interconnect technology? surprisingly, nano-photonic silicon has already emerged as a commercial inter-chip optical communications technology. this was made possible by silicon-on-insulator (soi), technology, which integrates many of the optical communications components directly in silicon cmos chips. intel and luxtera have both announced > 10gb/sec optical modulators, integrated into silicon. all the other customarily required opto-electronic components; detectors, waveguides, splitters, couplers, filters, etc., are fully executed in cmos designs, as well. continuous wave optical power is provided from off-chip, just as dc power is currently provided from off-chip. the initial commercial applications are optical 10gb/s ethernet, infiniband, and other inter-chip, communications applications. the question to be addressed in this talk, is whether silicon nano-photonics can now make the final jump, to intra-chip optical interconnects?
engineering change using spare cells with constant insertion. in the vlsi design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. this correction process is referred to as engineering change (ec). usually, an ec problem is resolved by using spare cells, which have been inserted into the unused spaces of a chip. in this paper, we propose an iterative method to generate feasible mapping solutions for an ec problem considering spare cells whose inputs may be tied to vdd or gnd, called constant insertion. applying constant insertion can increase a cell's flexibility in aspect of functionalities, so far-away spare cells need not be used just for some specific functionality. our experimental results show that the area in which there are enough spare cells for a mapping solution with constant insertion is only 82% of the area without constant insertion.
module assignment for pin-limited designs under the stacked-vdd paradigm. this paper addresses the module assignment problem in pin-limited designs under the stacked-vdd circuit paradigm. a partition-based algorithm is presented for efficiently assigning modules at the floorplanning level so as to reuse currents between the vdd domains, and minimize the power wasted during the operation of the circuit. experimental results on a dlx architecture show that compared with assigning modules to different vdd rails using a bin-packing technique, the circuit generated by our algorithm has 32% lower wasted power, on average. in addition, experiments on a 3d ic example show that our module assignment approach is equally effective in reducing the power waste in 3d ics.
sizing and placement of charge recycling transistors in mtcmos circuits. a downside of using multi-threshold cmos (mtcmos) technique for leakage reduction is the energy consumption during transitions between sleep and active modes. previously, a charge recycling (cr) mtcmos architecture was proposed to reduce the large amount of energy consumption that occurs during the mode transitions in power-gated circuits. considering the rc parasitics of the virtual ground and vdd lines, proper sizing and placement of charge-recycling transistors is key to achieving the maximum power saving. in this paper, we show that the sizing and placement problems of charge-recycling transistors in cr-mtcmos can be formulated as a linear programming problem, and hence, can be efficiently solved using standard mathematical programming packages. the proposed sizing and placement techniques allow us to employ the cr-mtcmos solution in large row-based standard cell layouts while achieving nearly the full potential of this power-gating architecture, i.e., we achieve 44% saving in switching energy due to the mode transition in cr-mtcmos compared to standard mtcmos.
probabilistic decision diagrams for exact probabilistic analysis. a decision diagram based framework is proposed for representing the probabilistic behavior of circuits with faulty gates. we introduce probabilistic decision diagrams (pdd) as an exact computational tool which along with vast expressive power holds many other useful properties such as space efficiency (on average) and efficient manipulation algorithms (polynomial in size.) an algorithm for constructing the pdd for a circuit is proposed. useful information about probabilistic behavior of the circuit (such as output error probability for arbitrary input probability distribution) can be directly extracted from the pdd representation. experimental results demonstrate the effectiveness and applicability of the proposed approach.
remote activation of ics for piracy prevention and digital right management. we introduce a remote activation scheme that aims to protect integrated circuits (ic) intellectual property (ip) against piracy. remote activation enables designers to lock each working ic and to then remotely enable it. the new method exploits inherent unclonable variability in modern manufacturing for unique identification (id) and integrated the ids into the circuit functionality. the objectives are realized by replication of a few states of the finite state machine (fsm) and adding control to the state transitions. on each chip, the added control signals are a function of the unique ids and are thus unclonable. on standard benchmark circuits, the experimental results show that the novel activation method is stable, unclonable, attack-resilient, while having a low overhead and a unique key for each ic.
combining static and dynamic defect-tolerance techniques for nanoscale memory systems. nanoscale technology promises dramatically increased device density, but also decreased reliability. with bit error rates projected to be as high as 10%, designing a usable nanoscale memory system poses a significant challenge. in particular, we need to bootstrap a sea of unreliable bits into contiguous address ranges which are preferably as large as 4k-byte virtual memory pages. we accomplish this bootstrapping through a combination of dynamic error correction codes within 32-bit blocks and a static defect map which tracks usability of these blocks. the key insight is that statically-determined defect locations can be much more powerful than dynamically correcting for unknown locations, but that defect maps are only practical at a coarse granularity. using a combination of bch error correction codes and a bloom-filter-based defect map, we achieve a memory efficiency of 60% and 13% for 4k-byte pages at 1% and 10% bit-error rates, respectively.
timing constraint-driven technology mapping for fpgas considering false paths and multi-clock domains. modern fpga chips contain multiple dedicated clocking networks, because nearly all real designs contain multiple clock domains. in this paper, we present an fpga technology mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. we use timing constraints to handle these unique clocking issues. we work on timing constraint graphs and process multiple arrival/required times for each node in the gate-level netlist. we also recognize and process constraint conflicts efficiently. our algorithm produces a mapped circuit with the optimal mapping depth under timing constraints. to the best of our knowledge, this is the first fpga mapping algorithm working with multi-clock domains. experiments show that our algorithm is able to improve circuit performance by 16.8% on average after placement and routing for a set of benchmarks with multi-cycle paths, comparing to a previously published depth-optimal algorithm that does not consider multi-cycle paths.
counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens. this paper introduces a novel approach to efficiently implement several useful architectural features in asynchronous application-specific ics (asics). these features include speculation, preemption, and eager evaluation, which have so far only been available on cpus, and have not been adequately investigated for custom asics. for the efficient implementation of the new architectural features, a radically new approach inspired by sproull's counterflow pipelines [7] is proposed. the key idea is to allow special commands, called anti-tokens, to be propagated in a direction opposite to that of data, allowing certain computations to be killed before they are completed, if their results are no longer required. the net impact is a significant improvement in the throughput of a certain class of systems---e.g., those involving conditional computation---where a bottleneck pipeline stage can often be preempted if its result is determined to be no longer needed. experimental results indicate that our approach can improve the system throughput by a factor of up to 2.2x, along with an energy savings of up to 27%.
optimal polynomial-time interprocedural register allocation for high-level synthesis and asip design. register allocation, in high-level synthesis and asip design, is the process of determining the number of registers to include in the resulting circuit or processor. the goal is to allocate the minimum number of registers such that no scalar variable is spilled to memory. previously, an optimal polynomial-time algorithm for this problem has been presented for individual procedures represented in static single assignment (ssa) form. this result is now extended to complete programs (or sub-programs), as long as: (1) each procedure is represented in ssa form; and (2) at every procedure call, all live variables are split at the call point. with this representation, it is possible to ensure that the interprocedural interference graph (iig) is chordal, and can therefore be colored optimally in polynomial time. an optimal coloring of the iig can be achieved by allocating registers for each procedure individually. previous work has shown that optimal register allocation in ssa form does not require an interference graph. optimal interprocedural register allocation, therefore, is achieved without constructing an interference graph, giving the optimal algorithm a significant runtime advantage over prior sub-optimal heuristics.
from molecular interactions to gates: a systematic approach. the continuous minituarization of integrated circuits may reach atomic scales in a couple of decades. some researchers have already built simple computation engines by manipulating individual atoms on metal surfaces. this paper presents a systematic approach to automate the design of logic gates using molecule cascades. temporal logic is used to characterize molecular interactions and specify the behavior of logic gates. model-checking techniques are used for the exploration of structures behaviorally equivalent to the logic gates. as an example, a complete library of combinational logic gates has been designed using a particular molecular system. this new approach provides a methodology to bridge the gap between physical chemists and computer scientists in seeking computational structures at atomic scales.
mosfet modeling for 45nm and beyond. compact mosfet models are a critical link between technology and design. the inexorable reduction in supply voltage and geometry to 45nm and below adds or emphasizes physical effects not important in the past, and so continues to expand the requirements for mosfet models. at and below 45nm, process variations, reliability, proximity effects, high-k gate materials, and non-classical device structures all challenge modeling. this tutorial presents fundamentals and evolution of compact mosfet models, and techniques to address the new challenges.
allocation cost minimization for periodic hard real-time tasks in energy-constrained dvs systems. energy-efficiency and power-awareness for electronic systems have been important design issues in hardware and software implementations. we consider the scheduling of periodic hard real-time tasks along with the allocation of processors under a given energy constraint. each processor type could be associated with its allocation cost. the objective of this work is to minimize the entire allocation cost of processors so that the timing and energy constraints are both satisfied. we develop approximation algorithms for processor types with continuous processor speeds or discrete processor speeds. the capability of the proposed algorithms was evaluated by a series of experiments, and it was shown that the proposed algorithms always derived solutions with system costs close to those of optimal solutions in the experiments.
automating post-silicon debugging and repair. modern ic designs have reached unparalleled levels of complexity, resulting in more and more bugs discovered after design tape-out however, so far only very few eda tools for post-silicon debugging have been reported in the literature. in this work we develop a methodology and new algorithms to automate this debugging process. key innovations in our technique include support for the physical constraints specific to post-silicon debugging and the ability to repair functional errors through subtle modifications of an existing layout. in addition, our proposed post-silicon debugging methodology (fogclear) can repair some electrical errors while preserving functional correctness. thus, by automating this traditionally manual debugging process, our contributions promise to reduce engineers' debugging effort. as our empirical results show, we can automatically repair more than 70% of our benchmark designs.
a new statistical max operation for propagating skewness in statistical timing analysis. statistical static timing analysis (ssta) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. for computing the statistical max of two arrival time probability distributions, existing analytical ssta approaches use the results given by clark in [8]. these analytical results are exact when the two operand arrival time distributions have jointly gaussian distributions. due to the nonlinear max operation, arrival time distributions are typically skewed. furthermore, nonlinear dependence of gate delays and non-gaussian process parameters also make the arrival time distributions asymmetric. therefore, for computing the max accurately, a new approach is required that accounts for the inherent skewness in arrival time distributions. in this work, we present analytical solution for computing the statistical max operation.1 first, the skewness in arrival time distribution is modeled by matching its first three moments to a so-called skewed normal distribution. then by extending clark's work to handle skewed normal distributions we derive analytical expressions for computing the moments of the max. we then show using initial simulations results that using a skewness based max operation has a significant potential to improve the accuracy of the statistical max operation in ssta while retaining its computational efficiency.
a hybrid scheme for compacting test responses with unknown values. this paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking multiple input signature registers (misr). the proposed scheme guarantees no coverage loss for the modeled faults. the proposed hybrid scheme can also be tuned to observe any user-specified percentage of responses for controlling the coverage loss for un-modeled faults. the experimental results demonstrate that, in comparison with a space compactor or an unknown-blocking misr alone, the hybrid compaction scheme achieves a lower coverage loss without demanding more test-data volume. in addition, we propose a quantitative approach to estimate the required percentage of observable responses for the proposed scheme, directly based on a test-quality metric of un-modeled faults.
organic electronic device modeling at the nanoscale. electronic devices with nanoscale features (~ 100 nm or smaller) are becoming increasingly important in electronics technology. while nanoscale electronic devices comprise a variety of different material sets and structures, many of the nanoscale devices developed in the last decade employ organic materials. in this talk, we discuss the modeling of organic electronic thin film devices. in our approach, analysis of such devices begins on the molecular scale, and device level behavior is then derived from the combination of individual molecular properties and physical models of intermolecular interactions. we present a general purpose monte carlo simulator based on molecular-scale physical models and employ this simulator to analyze device behavior.
a design flow dedicated to multi-mode architectures for dsp applications. this paper addresses the design of multi-mode architectures for digital signal processing applications. we present a dedicated design flow and its associated high-level synthesis tool, named gaut. given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single rtl hardware architecture optimized in area is generated. in order to reduce the register, steering logic (multiplexers) and controller (decoding logic) complexities, we propose a joint-scheduling algorithm which maximizes the similarities between control steps and specific binding approaches for both functional units and storage elements which maximize the similarities between the datapaths. we show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art.
ppv-hb: harmonic balance for oscillator/pll phase macromodels. a unique feature of oscillators is that small but sustained external perturbations lead to unboundedly large changes in phase, thereby making standard harmonic balance (hb) inapplicable to realistic oscillator phase macromodels. in this paper, we rectify this situation by presenting a novel extension of hb that is capable of handling oscillator phase macromodels. key to the new method, termed ppv-hb, is a formulation that separates unboundedly increasing phase terms from the bounded, periodic components. ppv-hb can be used not only on individual oscillators, but it also enables the application of hb-like techniques for simulating system-level equation systems composed of higher-level macromodels of blocks. we validate ppv-hb on individual oscillators and a pll system, demonstrating excellent matches with transient simulation using phase macromodels. speedups of 1-2 orders of magnitude are obtained, over and above additional speedups of another 2-3 orders of magnitude that stem from using macromodels (as opposed to full circuit simulation).