waashk/dblp huggingface dataset:
inter-core cooperative tlb for chip multiprocessors. translation lookaside buffers (tlbs) are commonly employed in modern processor designs and have considerable impact on overall system performance. a number of past works have studied tlb designs to lower access times and miss rates, specifically for uniprocessors. with the growing dominance of chip multiprocessors (cmps), it is necessary to examine tlb performance in the context of parallel workloads. this work is the first to present tlb prefetchers that exploit commonality in tlb miss patterns across cores in cmps. we propose and evaluate two inter-core cooperative (icc) tlb prefetching mechanisms, assessing their effectiveness at eliminating tlb misses both individually and together. our results show these approaches require at most modest hardware and can collectively eliminate 19% to 90% of data tlb (d-tlb) misses across the surveyed parallel workloads. we also compare performance improvements across a range of hardware and software implementation possibilities. we find that while a fully-hardware implementation results in average performance improvements of 8-46% for a range of tlb sizes, a hardware/software approach yields improvements of 4-32%. overall, our work shows that tlb prefetchers exploiting inter-core correlations can effectively eliminate tlb misses.
virtualized and flexible ecc for main memory. we present a general scheme for virtualizing main memory error-correction mechanisms, which map redundant information needed to correct errors into the memory namespace itself. we rely on this basic idea, which increases flexibility to increase error protection capabilities, improve power efficiency, and reduce system cost; with only small performance overheads. we augment the virtual memory system architecture to detach the physical mapping of data from the physical mapping of its associated ecc information. we then use this mechanism to develop two-tiered error protection techniques that separate the process of detecting errors from the rare need to also correct errors, and thus save energy. we describe how to provide strong chipkill and double-chip kill protection using existing dram and packaging technology. we show how to maintain access granularity and redundancy overheads, even when using ×8 dram chips. we also evaluate error correction for systems that do not use ecc dimms. overall, analysis of demanding spec cpu 2006 and parsec benchmarks indicates that performance overhead is only 1% with ecc dimms and less than 10% using standard non-ecc dimm configurations, that dram power savings can be as high as 27%, and that the system energy-delay product is improved by 12% on average.
decoupling contention management from scheduling. many parallel applications exhibit unpredictable communication between threads, leading to contention for shared objects. the choice of contention management strategy impacts strongly the performance and scalability of these applications: spinning provides maximum performance but wastes significant processor resources, while blocking-based approaches conserve processor resources but introduce high overheads on the critical path of computation. under situations of high or changing load, the operating system complicates matters further with arbitrary scheduling decisions which often preempt lock holders, leading to long serialization delays until the preempted thread resumes execution. we observe that contention management is orthogonal to the problems of scheduling and load management and propose to decouple them so each may be solved independently and effectively. to this end, we propose a load control mechanism which manages the number of active threads in the system separately from any contention which may exist. by isolating contention management from damaging interactions with the os scheduler, we combine the efficiency of spinning with the robustness of blocking. the proposed load control mechanism results in stable, high performance for both lightly and heavily loaded systems, requires no special privileges or modifications at the os level, and can be implemented as a library which benefits existing code.
analyzing multicore dumps to facilitate concurrency bug reproduction. debugging concurrent programs is difficult. this is primarily because the inherent non-determinism that arises because of scheduler interleavings makes it hard to easily reproduce bugs that may manifest only under certain interleavings. the problem is exacerbated in multi-core environments where there are multiple schedulers, one for each core. in this paper, we propose a reproduction technique for concurrent programs that execute on multi-core platforms. our technique performs a lightweight analysis of a failing execution that occurs in a multi-core environment, and uses the result of the analysis to enable reproduction of the bug in a single-core system, under the control of a deterministic scheduler. more specifically, our approach automatically identifies the execution point in the re-execution that corresponds to the failure point. it does so by analyzing the failure core dump and leveraging a technique called execution indexing that identifies a related point in the re-execution. by generating a core dump at this point, and comparing the differences betwen the two dumps, we are able to guide a search algorithm to efficiently generate a failure inducing schedule. our experiments show that our technique is highly effective and has reasonable overhead.
conservation cores: reducing the energy of mature computations. growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. in this regime, specialized, energy-efficient processors can increase parallelism by reducing the per-computation power requirements and allowing more computations to execute under the same power budget. to pursue this goal, this paper introduces conservation cores. conservation cores, or c-cores, are specialized processors that focus on reducing energy and energy-delay instead of increasing performance. this focus on energy makes c-cores an excellent match for many applications that would be poor candidates for hardware acceleration (e.g., irregular integer codes). we present a toolchain for automatically synthesizing c-cores from application source code and demonstrate that they can significantly reduce energy and energy-delay for a wide range of applications. the c-cores support patching, a form of targeted reconfigurability, that allows them to adapt to new versions of the software they target. our results show that conservation cores can reduce energy consumption by up to 16.0x for functions and by up to 2.1x for whole applications, while patching can extend the useful lifetime of individual c-cores to match that of conventional processors.
request behavior variations. a large number of user requests execute (often concurrently) within a server system. a single request may exhibit fluctuating hardware characteristics (such as instruction completion rate and on-chip resource usage) over the course of its execution, due to inherent variations in application execution semantics as well as dynamic resource competition on resource-sharing processors like multicores. understanding such behavior variations can assist fine-grained request modeling and adaptive resource management. this paper presents operating system management to track request behavior variations online. in addition to metric sample collection during periodic interrupts, we exploit the frequent system calls in server applications to perform low-cost in-kernel sampling. we utilize identified behavior variations to support or enhance request modeling in request classification, anomaly analysis, and online request signature construction. a foundation of our request modeling is the ability to quantify the difference between two requests' time series behaviors. we evaluate several differencing measures and enhance the classic dynamic time warping technique with additional penalties for asynchronous warp steps. finally, motivated by fluctuating request resource usage and the resulting contention, we implement contention-easing cpu scheduling on multicore platforms and demonstrate its effectiveness in improving the worst-case request performance. experiments in this paper are based on five server applications -- apache web server, tpcc, tpch, rubis online auction benchmark, and a user-content-driven online teaching application called webwork.
respec: efficient online multiprocessor replayvia speculation and external determinism. deterministic replay systems record and reproduce the execution of a hardware or software system. while it is well known how to replay uniprocessor systems, replaying shared memory multiprocessor systems at low overhead on commodity hardware is still an open problem. this paper presents respec, a new way to support deterministic replay of shared memory multithreaded programs on commodity multiprocessor hardware. respec targets online replay in which the recorded and replayed processes execute concurrently. respec uses two strategies to reduce overhead while still ensuring correctness: speculative logging and externally deterministic replay. speculative logging optimistically logs less information about shared memory dependencies than is needed to guarantee deterministic replay, then recovers and retries if the replayed process diverges from the recorded process. externally deterministic replay relaxes the degree to which the two executions must match by requiring only their system output and final program states match. we show that the combination of these two techniques results in low recording and replay overhead for the common case of data-race-free execution intervals and still ensures correct replay for execution intervals that have data races. we modified the linux kernel to implement our techniques. our software system adds on average about 18% overhead to the execution time for recording and replaying programs with two threads and 55% overhead for programs with four threads.
joint optimization of idle and cooling power in data centers while maintaining response time. server power and cooling power amount to a significant fraction of modern data centers' recurring costs. while data centers provision enough servers to guarantee response times under the maximum loading, data centers operate under much less loading most of the times (e.g., 30-70% of the maximum loading). previous server-power proposals exploit this under-utilization to reduce the server idle power by keeping active only as many servers as necessary and putting the rest into low-power standby modes. however, these proposals incur higher cooling power due to hot spots created by concentrating the data center loading on fewer active servers, or degrade response times due to standby-to-active transition delays, or both. other proposals optimize the cooling power but incur considerable idle power. to address the first issue of power, we propose powertrade, which trades-off idle power and cooling power for each other, thereby reducing the total power. to address the second issue of response time, we propose surgeguard to overprovision the number of active servers beyond that needed by the current loading so as to absorb future increases in the loading. surgeguard is a two-tier scheme which uses well-known over-provisioning at coarse time granularities (e.g., one hour) to absorb the common, smooth increases in the loading, and a novel fine-grain replenishment of the over-provisioned reserves at fine time granularities (e.g., five minutes) to handle the uncommon, abrupt loading surges. using real-world traces, we show that combining powertrade and surgeguard reduces total power by 30% compared to previous low-power schemes while maintaining response times within 1.7%.
compass: a programmable data prefetcher using idle gpu shaders. a traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. these powerful computing cores are mainly used for accelerating graphics applications or enabling low-cost scientific computing. to further reduce the cost and form factor, an emerging trend is to integrate gpu along with the memory controllers onto the same die with the processor cores. however, given such a system-on-chip, the gpu, while occupying a substantial part of the silicon, will sit idle and contribute nothing to the overall system performance when running non-graphics workloads or applications lack of data-level parallelism. in this paper, we propose compass, a compute shader-assisted data prefetching scheme, to leverage the gpu resource for improving single-threaded performance on an integrated system. by harnessing the gpu shader cores with very lightweight architectural support, compass can emulate the functionality of a hardware-based prefetcher using the idle gpu and successfully improve the memory performance of single-thread applications. moreover, thanks to its flexibility and programmability, one can implement the best performing prefetch scheme to improve each specific application as demonstrated in this paper. with compass, we envision that a future application vendor can provide a custom-designed compass shader bundled with its software to be loaded at runtime to optimize the performance. our simulation results show that compass can improve the single-thread performance of memory-intensive applications by 68% on average.
speculative parallelization using software multi-threaded transactions. with the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades. while many scientific programs can be parallelized without speculative techniques, speculative parallelism appears to be the key to continuing this trend for general-purpose applications. recently-proposed code parallelization techniques, such as those by bridges et al. and by thies et al., demonstrate scalable performance on multiple cores by using speculation to divide code into atomic units (transactions) that span multiple threads in order to expose data parallelism. unfortunately, most software and hardware thread-level speculation (tls) memory systems and transactional memories are not sufficient because they only support single-threaded atomic units. multi-threaded transactions (mtxs) address this problem, but they require expensive hardware support as currently proposed in the literature. this paper proposes a software mtx (smtx) system that captures the applicability and performance of hardware mtx, but on existing multicore machines. the smtx system yields a harmonic mean speedup of 13.36x on native hardware with four 6-core processors (24 cores in total) running speculatively parallelized applications.
a randomized scheduler with probabilistic guarantees of finding bugs. this paper presents a randomized scheduler for finding concurrency bugs. like current stress-testing methods, it repeatedly runs a given test program with supplied inputs. however, it improves on stress-testing by finding buggy schedules more effectively and by quantifying the probability of missing concurrency bugs. key to its design is the characterization of the depth of a concurrency bug as the minimum number of scheduling constraints required to find it. in a single run of a program with n threads and k steps, our scheduler detects a concurrency bug of depth d with probability at least 1/nkd-1. we hypothesize that in practice, many concurrency bugs (including well-known types such as ordering errors, atomicity violations, and deadlocks) have small bug-depths, and we confirm the efficiency of our schedule randomization by detecting previously unknown and known concurrency bugs in several production-scale concurrent programs.
macross: macro-simdization of streaming applications. simd (single instruction, multiple data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. although simd-enabled architectures have the capability of boosting the performance of many application domains by exploiting data-level parallelism, it is very challenging for compilers and also programmers to identify and transform parts of a program that will benefit from a particular simd engine. the focus of this paper is on the problem of simdization for the growing application domain of streaming. streaming applications are an ideal solution for targeting multi-core architectures, such as shared/distributed memory systems, tiled architectures, and single-core systems. since these architectures, in most cases, provide simd acceleration units as well, it is highly beneficial to generate simd code from streaming programs. specifically, we introduce macross, which is capable of performing macro-simdization on high-level streaming graphs. macro-simdization uses high-level information such as execution rates of actors and communication patterns between them to transform the graph structure, vectorize actors of a streaming program, and generate intermediate code. we also propose low-overhead architectural modifications that accelerate shuffling of data elements between the scalar and vectorized parts of a streaming program. our experiments show that macross is capable of generating code that, on average, outperforms scalar code compiled with the current state-of-art auto-vectorizing compilers by 54%. using the low-overhead data shuffling hardware, performance is improved by an additional 8% with less than 1% area overhead.
shimon: an interactive improvisational robotic marimba player. shimon is an autonomous marimba-playing robot designed to create interactions with human players that lead to novel musical outcomes. the robot combines music perception, interaction, and improvisation with the capacity to produce melodic and harmonic acoustic responses through choreographic gestures. we developed an anticipatory action framework, and a gesture-based behavior system, allowing the robot to play improvised jazz with humans in synchrony, fluently, and without delay. in addition, we built an expressive non-humanoid head for musical social communication. this paper describes our system, used in a performance and demonstration at the chi 2010 media showcase.
interactive diagram layout. we examine an approach for defining layout algorithms for diagrams. such an algorithm is specified on an abstract level and may be applied to many kinds of visual languages. it mainly allows for incremental diagram drawing and attaches great importance on mental map preservation. with the approach, it is possible to combine graph drawing algorithms and other layout algorithms. it is capable of defining layout behavior for non-graph-like visual languages like nassi-shneiderman diagrams or gui forms as well as graph-like visual languages such as class diagrams, mindmaps, or business process models. in this paper, we demonstrate that the combination of graph drawing algorithms and other layout algorithms is meaningful by presenting three visual language editors that have been created by students.
location aware applications to support mobile food vendors in the developing world. this paper describes an ongoing research project to explore the potential of location aware mobile phone-based applications to support mobile food vendors in the developing world. these vendors are a ubiquitous phenomenon in the developing world and can be seen hawking their wares in carts, bicycles or motorcycles. we report preliminary findings from nine interviews conducted with various mobile food vendors in indonesia. based on these findings, we present our initial system design for a mobile phone-based application that allows these vendors to advertize their current location, accept orders from customers, and have customers recommend particular vendors.
managing user experience: managing change. as managers of user experience and design teams we often find ourselves in environments where it is difficult to position the work of our team members. their roles are often misunderstood and our adjacent disciplines such as product management and development see their work as unnecessary or in some cases are threatened by them. we find that the culture of the company we are trying to deploy ux resources into isn't ready to accept them and we find that our role becomes more that of a change manager than a user experience manager. we have a vision for what the future processes of the company can look like but we find it hard to communicate that vision and engage our adjacent disciplines. what are effective strategies user experience leaders can use to impact change? how can we leverage current business and engineering trends to move corporate cultures in a direction that support our work? what are the potential traps and pitfalls? what does a culture of design thinking really mean in this context? what is a realistic expectation for an end state?
there's a monster in my kitchen: using aversive feedback to motivate behaviour change. in this paper we argue that "persuasive technologies," developed to motivate behaviour change in users, have so far failed to exploit the established body of empirical research within behavioural science. we propose that persuasive technologies may benefit from both adapting to individual preferences, and a constructive use of aversive, in addition to appetitive, feedback. we detail an example application that demonstrates how this approach can be incorporated into an application designed to train users to adopt more environmentally friendly behaviours in their domestic kitchens.
a classification scheme for user intentions in image search. searching for images on the web is still an open problem. while multiple approaches have been presented, there has been surprisingly little work on the actual goals and intentions of users. in this poster we present our classification scheme for user goals in image search and describe our ongoing work focusing on identification and classification of user intentions during image search tasks.
model-driven development of advanced user interfaces. the workshop on model-driven development of advanced user interfaces will be a forum of multi-disciplinary discussion on how to integrate model-driven development with the often more informal methodologies used in user-centered design. starting point of the discussion will be the tools, models, methods and experiences of the workshop participants.
empowering products: personal identity through the act of appropriation. this paper explores the relationship between personal identity and the act of appropriating digital objects in the home--specifically do-it-yourself--to inform the design of empowering products. it reports ongoing research and provides a preliminary analysis of the steampunk movement as a case study for personal appropriation. appropriation-identity design guidelines are provided as a result of the data analysis.
lightweight selective availability in instant messaging. selective availability in instant messaging systems can improve connectiveness while at the same time keeping disruption low. in this paper we report on a four-week experience sampling study of selective availability in instant messaging to inform the design of lightweight mechanisms with little user effort.
robotany: breeze. this paper describes breeze, a live roboticized tree. visitor interaction with breeze is interpreted through a series of narratives. these narratives yield results with implications for human-computer interaction research.