waashk/dblp huggingface dataset:
high-level synthesis of distributed logic-memory architectures. with the increasing cost of global communication on-chip, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout a chip, while restricting computations and communications to geographic proximities. in this paper, we present a methodology for high-level synthesis (hls) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. conventional hls tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. this work provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse- and fine-grained parallelism from data accesses and computations in a synergistic manner. our methodology selects many possible ways of organizing data and computations, carefully examines the trade-offs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional hls techniques for intermediate steps.we have evaluated the proposed framework on several benchmarks by generating register-transfer level (rtl) implementations using an existing commercial hls tool with and without our enhancements, and by subjecting the resulting rtl circuits to logic synthesis and layout. the results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (upto, 5.31x average of 3.45x) performance improvements over well-optimized conventional designs with small area overheads (upto 19.3%, 15.1% on average).
a formal basis for design process planning and management. in this paper we present a design formalism that allows for a complete and general characterization of design disciplines and for a unified representation of arbitrarily complex design processes. this formalism has been used as the basis for the development of several prototype cad meta-tools that offer effective design process planning and management services.
synthesis of heterogeneous distributed architectures for memory-intensive applications. memory-intensive applications present unique challenges to an asicdesigner in terms of the choice of memory organization, memory size requirements,bandwidth and access latencies, etc. the high potential of single-chip distributed logic-memory architectures in addressing many of these issues has been recognized ingeneral-purpose computing, and more recently in asic design. however, such architectureswill be adopted widely by designers only when general techniques and toolsfor efficient high-level synthesis (hls) of multi-partitioned asics become available.the techniques presented in this paper are motivated by the fact that many memory-intensiveapplications exhibit irregular array data access patterns (due to conditionalsin loop nests, etc.). synthesis should, therefore, be capable of determining a partitionedarchitecture, wherein array data and computations may have to be heterogeneouslydistributed for achieving the best performance speedup. furthermore, the synthesismethodology should not be restricted by the nature of array index functions (affine orotherwise) in a behavior. therefore, our methodology employs simulation to provideinformation about the access patterns of array data references in a behavior, which isused by the rest of our analysis. we use a combination of clustering and min-cut stylepartitioning techniques to partition the behavior into sub-behaviors while consideringvarious factors including data access locality, balanced workloads, inter-partitioncommunication, etc. finally, we also employ an iterative improvement strategy to determinethe best way of distributing array data into physical memory in each partition.our experiments with several benchmark applications show that the proposed techniquescan yield partitioned architectures that can achieve upto 2.2x performancespeed-up over conventional hls solutions, while achieving upto 1.6x performancespeedup over the best homogeneous partitioning solution feasible.
lower bound on latency for vliw asip datapaths. traditional lower bound estimates on latency for dataflow graphs assume no data transfer delays. while such approaches can generate tight lower bounds for datapaths with a centralized register file, the results may be uninformative for datapaths with distributed register file structures that are characteristic of vliw asips. in this paper we propose a latency bound that accounts for such data transfer delays. the novelty of our approach lies in construction the "window dependency graph" and bounds associated with the problem which capture delay penalties due to operation serialization and/or data moves among distributed register files. through a set of benchmark examples, we show that the bound is competitive with state-of-the-art approaches. moreover, our experiments show that the approach can aid an iterative improvement algorithm in determining good functional unit assignment ?-- a key step in code generation for vliw asips.
high-level synthesis using computation-unit integrated memories. high-level synthesis (hls) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. however, increasing performance and energy demands faced by application-specific integrated circuits (asic) are forcing designers to alter the fundamental architectural template of the hls output, namely, a controller-datapath associated with a memory subsystem (monolithic, banked, etc.). we propose an architectural template for the hls output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated. the enhanced memory subsystem is called computation-unit integrated memory (cim). a cim offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller-datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. this work addresses the challenge of providing an automatic synthesis framework for a cim-based architecture. our framework can analyze the various trade-offs involved in selecting suitable operations in a behavior for execution using a cim and generate a high-performance, low-overhead implementation. experiments with several behaviors indicate that an average performance improvement of 1.88/spl times/ (a maximum of 2.63/spl times/) is possible with very low area overheads. the energy-delay product improves by an average of 2.1/spl times/ (maximum of 3.4/spl times/).
exploring performance tradeoffs for clustered vliw asips. vliw asips provide an attractive solution for increasingly pervasive real-time multimedia and signal processing embedded applications. in this paper we propose an algorithm to support trade-off exploration during the early phases of the design/specialization of vliw asips with clustered datapaths. for purposes of an early exploration step, we define a parameterized family of clustered datapaths d(m,n), where m and n denote interconnect capacity and cluster capacity constraints on the family. given a kernel, the proposed algorithm explores the space of feasible clustered datapaths and returns: a datapath configuration; a binding and scheduling for the operations; and a corresponding estimate for the best achievable latency over the specified family. moreover, we show how the parameters m and n, as well as a target latency optionally specified by the designer, can be used to effectively explore trade-offs among delay, power/energy, and latency. extensive empirical evidence is provided showing that the proposed approach is strikingly effective at attacking this complex optimization problem.
analysis and evaluation of a hybrid interconnect structure for fpgas. in this paper, a cluster-based fpga is proposed. the proposed fpga has a hybrid interconnect structure which takes advantages of both mesh and tree topologies. we analyze the area and performance of proposed fpga in terms of the needed switches by comparing with those of conventional fpgas. we evaluate the proposed architecture on a series of benchmark designs. the experimental results show that the proposed model can significantly reduce the routing area, achieve high performance and admit more implementations of various designs at the price of a modest increase of switches required for that architecture.
efficient partitioning and analysis of digital cmos-circuits. a library independent method for the partitioning and analysis of switch-level cmos circuits is presented. this method is superior to the existing methods for extraction, because it is able to recognize cmos tristate drivers connected to a bus individually. moreover, it can improve the state-of-the-art algorithms for the determination of unidirectional signal flow, because its functional analysis is able to recognize groups of transistors which always constitute signal sources. the local functional analysis of the partitions is improved by the exclusion of impossible paths. additionally, the recognition of fully complementary gates allows the improvement of existing algorithms for signal flow analysis
mongrel: hybrid techniques for standard cell placement. we give an overview of a standard-cell placer mongrel. the prototype tool adopts a middle-down methodology in which a grid is imposed over the layout area and cells are assigned to bins forming a global placement. the optimization technique applied in this phase is based on the relaxation-based local search (rbls) framework in which a combinatorial search mechanism is driven by an analytical engine. this enables a more global view of the problem and results in complex modifications of the placement in a single search "move". details of this approach including a novel placement legalization procedure are presented. when a global placement has converged, a detailed placement is formed and further optimized by the proposed optimal interleaving technique. experimental results are presented and are quite promising, demonstrating that there is significant room for improvement in state of the art placement.
physical placement driven by sequential timing analysis. traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. as a result, the potential of re-balancing path delays through post-placement applications of clock skew scheduling and in-place retiming cannot be fully realized. in this paper we describe a new placement algorithm that is based on a tight integration of sequential timing analysis in the inner loop of an analytic solver. instead of minimizing the maximum path delay, our approach minimizes the maximum mean delay on any circuit loop, thus enabling the full optimization potential of clock skew scheduling and in-place retiming. we present two versions of the new algorithm: one approximates sequential criticality and weights wires accordingly (cong and lim, 2000), the other extends this with the inclusion of explicit wire-length constraints for loops that limit the final clock period. our algorithms are implemented using a hybrid, gordlan-style sequence of analytical placement steps interleaved with cell partitioning (kleinhans et al., 1988). our experiments on a set of large industrial designs demonstrate that the presented placement algorithm can minimize the contribution of interconnection delays to the clock period on average by 23.5% compared to a solution based on combinational delays.
accurate delay computation for noisy waveform shapes. in this paper we present a new gate delay model for accurate modeling of difficult waveform shapes, such as those resulting from coupling capacitance noise, inductive ringing and resistive shielding. our modeling approach uses a process of time shifting and time stretching of a set of so-called base-waveforms. these base-waveforms are selected from a large set of noisy waveform shapes that occur in interconnect structures with coupling and other types of noise, such that the delay error across all considered waveforms is minimized. depending on the desired accuracy one or more base-waveforms can be used. this method is also used to model the gate output waveforms allowing for closure, in terms of the used base-waveforms across a circuit library. we show that the determination of the optimal set of base-waveforms under such input-to-output closure is exponential in complexity. we, therefore, propose an heuristic approach that maps the problem to the unate covering problem for which efficient solution methods are available. the new delay model can be applied in a timing analysis program with minor changes. we present results that demonstrate the accuracy of the new delay model for waveforms perturbed with noise for a large set of waveform shapes.
software-assisted cache replacement mechanisms for embedded systems. we address the problem of improving cache predictability and performance in embedded systems through the use of software-assisted replacement mechanisms. these mechanisms require additional software controlled state information that affects the cache replacement decision. software instructions allow a program to kill a particular cache element, i.e., effectively make the element the least recently used element, or keep that cache element, i.e., the element will never be evicted.we prove basic theorems that provide conditions under which kill and keep instructions can be inserted into program code, such that the resulting performance is guaranteed to be as good as or better than the original program run using the standard lru policy. we developed a compiler algorithm based on the theoretical results that, given an arbitrary program, determines when to perform software-assisted replacement, i.e., when to insert either a kill or keep instruction. empirical evidence is provided that shows that performance and predictability (worst-case performance) can be improved for many programs.
fast simulation of vlsi interconnects. this work introduces an efficient and accurate interconnect simulation technique. a new formulation for typical vlsi interconnect structures is proposed which, in addition to providing a compact set of modeling equations, also offers a potential for exploiting sparsity at the simulation level. simulations show that our approach can achieve 50 /spl times/ improvement in computation time and memory over inductwise (which in turn has been shown to be 400 /spl times/ faster than spice) while preserving simulation accuracy.
on interactions between routing and detailed placement. the main goal of this work is to develop deeper insights into viable placement-level optimization of routing. two primary contributions are made. first, an experimental framework in which the viability of predictive models of routing congestion for optimization during detailed placement can be evaluated, is developed. the main criteria of consideration in these experiments is how (un)reliably various models from the literature detect routing hot-spots. we conclude that such models appear to be too unreliable for detailed placement optimization. second, motivated by the first result, we present a unified combinatorial framework in which cell placement and exact routing structures are captured and optimized; the framework relies on the trunk-decomposition of global routing structures and optimization is performed by a generalized optimal interleaving algorithm (hur and lillis, 2000). a proof of concept implementation of this framework is studied in the fpga domain. the technique can reduce the number of channels at maximum density by almost 45% on average with maximum reduction of 68% for optimized global routing.
a predictive system shutdown method for energy saving of event-driven computation. we present a system-level power management technique for power saving of event-driven applications. we present a new predictive system shutdown method to exploit sleep mode operations for power saving. we use an exponential-average approach to predict the upcoming idle period. we introduce two mechanisms, prediction-miss correction and pre-wakeup, to improve the hit ratio and to reduce the delay overhead. experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of power saving with low delay penalties.
an integrated algorithm for combined placement and libraryless technology mapping. this paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. the original aspects of our work are the use of libraryless mapping and a state space search mechanism that is used to find the best solution. several heuristics are presented for speeding up the search. comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable cpu times, on benchmark circuits.
cash: a novel "clock as shield" design methodology for noise immune precharge-evaluate logic. in gigascale integrated circuits (gsi), interconnects are expected to play a more dominant role in circuit performance than transistor cells. the circuit performance is affected by signal integrity as cross-talk becomes more significant with the scaling of feature sizes. many attempts have been made to improve noise immunity, but all require the sacrifice of speed as a trade-off, especially in dynamic circuits. avoiding noise problems while maintaining the desired speed would involve increased wire spacing or extensive shielding, both of which are unfavorable due to demands for high density and a relatively higher cost of wires in current process technologies. we propose a novel methodology in which clock lines are used as shielding wires to reduce cross-talk effects in domino circuits, thereby minimizing the possibility of functional failures. in addition, this method provides another benefit: a small buffer size is required for driving a long interconnect for iso-noise immunity. since clock lines, which are always required in domino circuits, are used to shield signal lines, speed penalty and area overhead which are drawbacks of previous work can be avoided. this design methodology cash (clock as shielding) demonstrates the superiority over conventional methods. hspice simulations on a 2-input domino and gate and 4 and 8-bit full adders designed in cash show higher noise immunity over conventional design.
hardware/software managed scratchpad memory for embedded system. we propose a methodology for energy reduction and performance improvement. the target system comprises of an instruction scratchpad memory instead of an instruction cache. highly utilized code segments are copied into the scratchpad memory, and are executed from the scratchpad. the copying of code segments from main memory to the scratchpad is performed during runtime. a custom hardware controller is used to manage the copying process. the hardware controller is activated by strategically placed custom instructions within the executing program. these custom instructions inform the hardware controller when to copy during program execution. novel heuristic algorithms are implemented to determine locations within the program to insert these custom instructions, as well as to choose the best sets of code segments to be copied to the scratchpad memory. for a set of realistic benchmarks, experimental results indicate the method uses 50.7% lower energy (on average) and improves performance by 53.2% (on average) when compared to a traditional cache system which is identical in size. cache systems compared had sizes ranging from 256 to 16k bytes and associativities ranging from 1 to 32.
multi-level network optimization for low power. this paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. power is minimized by modifying the function of each intermediate node in the network such that the power consumption of the node is decreased without increasing the power consumption of the other nodes in the network. a formal analysis of how changes in the switching activity of an intermediate node affect the switching activity of other nodes in the networks is given first. using this analysis, a procedure for calculating the set of compatible power don't cares for each node in the network is presented. finally it is shown how these don't cares are used to optimize the network for low power. these techniques have been implemented and results show an average of 10% improvement in total power consumption of the network compared to the results generated by the conventional network optimization techniques.
two-level logic minimization for low power. abstract: we study the problem of two-level logic minimization for low power in static cmos circuits. we start by defining power prime implicants (ppis) which identify the set of all implicants that are sufficient and necessary for obtaining a minimum power solution. we then provide an efficient algorithm for generating the set of all ppis of a function. the set of all ppis is then used in a minimum covering problem to find the best power solution. the feasibility of generating the set of all ppis and the increased complexity of solving the minimum covering problem are analyzed by deriving an upper bound on the expected number of ppis which shows it to be linearly proportional to the number of prime implicants of the function. the results of our experiments are then used to draw conclusions on the effectiveness of low power two-level logic minimization.
a metal and via maskset programmable vlsi design methodology using plas. in recent times there has been a substantial increase in the cost and complexity of fabricating a vlsi chip. the lithography masks themselves can cost between /spl epsi/ and /spl ges/. it is conjectured that due to these increasing costs, the number of asic starts in the last few years has declined. we address this problem by using an array of dynamic plas which require only metal and via mask customization in order to implement a new design. this would allow several similar-sized designs to share the same base set of masks (right up to the metal layers) and only have different metal and via masks. we have implemented our methodology for both combinational and sequential designs, and demonstrate that our approach strikes a reasonable compromise between asic and field programmable design methodologies in terms of placed-and-routed area and delay. our method has a 2.89/spl times/ (3.58/spl times/) delay overhead and a 4.96/spl times/ (3.44/spl times/) area overhead compared to standard cells for combinational (sequential) designs.
test generation for acyclic sequential circuits with hold registers. we present a method of test generation for acyclic sequential circuits with hold registers. a complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (tems) of the circuit. we propose a class of acyclic sequential circuits for which the number of maximal tems is one, i.e, the maximum tem exists. for a circuit in the class, test generation can be performed by using only the maximum tem.the proposed class of sequential circuits with the maximum tem properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.