waashk/dblp huggingface dataset:
the synthesis of combinational logic to generate probabilities. as cmos devices are scaled down into the nanometer regime, concerns about reliability are mounting. instead of viewing nano-scale characteristics as an impediment, technologies such as pcmos exploit them as a source of randomness. the technology generates random numbers that are used in probabilistic algorithms. with the pcmos approach, different voltage levels are used to generate different probability values. if many different probability values are required, this approach becomes prohibitively expensive. in this work, we demonstrate a novel technique for synthesizing logic that generates new probabilities from a given set of probabilities. three different scenarios are considered in terms of whether the given probabilities can be duplicated and whether there is freedom to choose them. in the case that the given probabilities cannot be duplicated and are predetermined, we provide a solution that is fpga-mappable. in the case that the given probabilities cannot be duplicated but can be freely chosen, we provide an optimal choice. in the case that the given probabilities can be duplicated and can be freely chosen, we demonstrate how to generate arbitrary decimal probabilities from small sets -- a single probability or a pair of probabilities -- through combinational logic.
leveraging efficient parallel pattern search for clock mesh optimization. mesh-based clock distribution network has been employed in many high-performance microprocessor designs due to its favorable properties such as low clock skew and robustness. such clock distributions are usually highly complex. while the simulation of clock meshes is already time consuming, tuning such networks under tight performance constraints is a more daunting task. in this paper, we address the challenging task of driver size optimization with a goal of skew minimization. the expensive objective function evaluations and difficulty in getting explicit sensitivity information make this problem intractable to standard optimization methods. we propose to explore the recently developed asynchronous parallel pattern search (apps) method for efficient driver size tuning. while being a search-based method, apps not only provides the desirable derivative-free optimization capability, but is also amenable to parallelization and possesses appealing theoretically rigorous convergence properties. we show how such a method can lead to powerful parallel sizing optimization of large clock meshes with significant runtime and quality advantages over the traditional sequential quadratic programming (sqp) method. we also show how design-specific properties and speeding-up techniques can be exploited to make the optimization even more efficient while maintaining the convergence of apps in a practical sense.
a performance analytical model for network-on-chip with constant service time routers. performance models for network-on-chip (noc) are essential for design, optimization and quality of service (qos) assurance. classical queueing theory has been often used to provide fast analytical models to estimate average performance. this paper presents a new analytical model that focuses on qos assurance. it assumes that the noc has an underlying synchronous behavior with constant service time routers. the comparisons with simulation results show a tangible improvement with regard to the classical m/d/1 models when estimating the worst-case latencies and queue delays. the model can be applied to any network modeled as a queueing system with constant-time routers.
battery allocation for wireless sensor network lifetime maximization under cost constraints. wireless sensor networks hold the potential to open new domains to distributed data acquisition. however, such networks are prone to premature failure because some nodes deplete their batteries more rapidly than others due to workload variations, non-uniform communication, and heterogenous hardware. many-to-one traffic patterns are common in sensor networks, further increasing node power consumption heterogeneity. most previous sensor network lifetime enhancement techniques focused on balancing power distribution, based on the assumption of uniform battery capacity allocation among homogeneous nodes. this paper gives a formulation and solution to the cost-constrained lifetime-aware battery allocation problem for sensor networks with arbitrary topologies and heterogeneous power distributions. an integer nonlinear programming formulation is given. based on an energy-cost battery pack model and optimal node partitioning algorithm, a rapid battery pack selection heuristic is developed and its deviation from optimality is quantified. experimental results indicate that the proposed technique achieves network lifetime improvements ranging from 3--11x compared to uniform battery allocation, with no more than 10 battery pack energy levels. the proposed technique achieves 2--5 orders of magnitude speedup compared to a general-purpose commercial nonlinear program solver, solution quality improves, and little approximation error is observed.
joint design-time and post-silicon optimization for digitally tuned analog circuits. joint design time and post-silicon optimization for analog circuits has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. in this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric yield, subject to power and area constraints. a general optimization framework combing the branch-and-bound algorithm and gradient ascent method is proposed. we demonstrate our framework with two examples in high-speed serial link, the transmitter design and the phase-locked-loop (pll) design. simulation results show that compared with the design heuristic from analog designers' perspective, joint design-time and post-silicon optimization can improve the yield by up to 47% for transmitter design and up to 56% for pll design under the same area and power constraints. to the best of the authors' knowledge, this is the first in-depth study on yield-driven analog circuit design technique that optimizes post-silicon tuning together with the design-time optimization.
layout-dependent sti stress analysis and stress-aware rf/analog circuit design optimization. with the continuous shrinking of feature size, various effects due to shallow-trench-isolation (sti) stress are becoming more and more significant. the resulting nonuniform distribution of stress affects the mosfet characteristics and hence changes the circuit behavior. this paper proposes a complete flow to characterize the influence of sti stress on performance of rf/analog circuits based on layout design and process information. an accurate and efficient fem-based stress simulator has been developed to handle the layout dependence. a comprehensive mosfet model is also proposed to capture the effects of sti stress on mobility, threshold voltage, and leakage current. the influence of layout-dependent sti stress on the circuit performance is further studied, and the corresponding optimization strategies to circuit design are discussed. a realistic pll design realized using 90nm cmos technology is used as a test case for the proposed approach.
optimal layer assignment for escape routing of buses. escape routing is a critical problem in pcb design. in ic-cad'07, a layer assignment algorithm was proposed for escape routing of buses. the algorithm is optimal for single layer design in the sense that it determines if a set of buses can all be escaped on one layer. if they cannot, the algorithm is able to select a maximum subset of the buses that can be escaped on one layer. this, in turn, leads to a heuristic for the layer assignment problem with multiple layers, which is to repeatedly assign a maximum subset of the unassigned buses to a new layer. in this work, we present an algorithm that solves the multi-layer layer assignment problem optimally. our algorithm guarantees to produce a layer assignment with minimum number of layers. we applied our algorithm on industrial data and obtained encouraging results.
automatic memory partitioning and scheduling for throughput and power optimization. hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. selected computation kernels for acceleration are usually captured by nest loops, which are optimized by state-of-the-art techniques like loop tiling and loop pipelining. however, memory bandwidth bottlenecks prevent designs to reach optimal throughput with respect to available parallelism. in this paper we present an automatic memory partitioning technique which can efficiently improve throughput and reduce energy consumption of pipelined loop kernels for given throughput constraints and platform requirement. our partition scheme consists of two steps, the first step considers cycle accurate scheduling information to meet the hard constraints on memory bandwidth requirements specifically for synchronized hardware designs. experimental results show an average 6x throughput improvement on a set of real world designs with moderate area increase (about 45% on average), given that less resource sharing opportunities exist with higher throughput in optimized designs. the second step further partitions the memory banks for reducing the dynamic power consumption of the final design. in contrast with previous approaches, our technique can statically compute memory access frequencies in polynomial time with little to none profiling. experimental results show about 30% power reduction on the same set of benchmarks.
energy-optimal dynamic thermal management for green computing. existing thermal management systems for microprocessors assume that the thermal resistance of the heat-sink is constant and that the objective of the cooling system is simply to avoid thermal emergencies. but in fact the thermal resistance of the usual forced-convection heat-sink is inversely proportional to the fan speed, and a more rational objective is to minimize the total power consumption of both processor and cooling system. our new method of dynamic thermal management uses both the fan speed and the voltage/frequency of the microprocessor as control variables. experiments show that tracking the energy-optimal steady-state temperature can saves up to 17.6% of the overall energy, when compared with a conventional approach that merely avoids over-heating.
mitigation of intra-array sram variability using adaptive voltage architecture. sram cell design is driven by the need to satisfy static noise margin, write margin and read current margin (rcm) over all cells in the array in an energy-efficient manner. these constraints determine both the minimum cell size and supply voltage. rcm is set by the maximum read access time over the array. the randomness of transistor threshold voltages, and thus read times, makes maximum read time follow extreme order statistics, specifically, the gumbel distribution which is characterized by long tails. thus, the margin specification needs to be met at the high sigma corners in order to reach acceptable yield, resulting in oversizing and increased vdd. in this work, we demonstrate that a reduced-area bitcell design is achievable by reducing the impact of intra-array randomness through a new architecture that employs an adaptive voltage scheme in a partitioned sram array. the key idea is to be able to shift empirical distributions (realizations) of read time in a set of rows that form a single partition to meet the target. because the partition is smaller than the whole array, the tail of the gumbel distribution is significantly reduced. the adaptive voltage tuning policy is driven by the worst partition access time. for the blocks whose delay violates access time constraints, a higher voltage is selected out of the available set to gain yield, otherwise voltage is reduced for power saving. this permits smaller cell area and lower vdd at identical yield. the cost of adaptivity is in generation and routing of a small number (in our experiments, four) voltage levels and the area of one-per-partition set of pmos switches. we demonstrate that through the voltage tuning architecture we propose, it is possible to obtain mean power consumption reduction on average by 21% iso-area. alternatively, bitcell area can be reduced on average by 7% iso-power compared to the existing design strategy.
maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. in this paper a precise formulation of the problem of minimizing the maximum completion time of tasks on a multi-core processor, subject to thermal constraints is presented. the power model used in this work, accounts for the leakage dependence on temperature, while the thermal model is based on the hotspot model. the general problem is shown to be a non-linear optimization problem that includes cyclic constraints between temperature and power. the derived policy of dynamic frequency and voltage control results in a performance improvement of 19.6% over an optimal policy which performs speed-only control.
value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. in synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. in this paper, we use adjustable delay buffers (adb) whose delays can be tuned or adjusted to minimize clock skew under different power modes. assuming that the positions of k adbs are already determined, we propose a linear-time optimal algorithm which assigns the values of adbs so that the skew is optimal among all possible adb assignments. we also propose an efficient heuristic to determine good positions for adbs. our results show significant improvement when compared to cases without adbs.
global routing revisited. recent progress in the area of global routing has been remarkable; yet, in many ways, the classical formulation has yet to catch up with the demands imposed by modern physical synthesis flows. in this work, we visit (and revisit) the topic of global routing. we provide a brief review of global routing's history, and touch on recent work that has contributed to the state-of-the-art in the field. while we cover in depth the basic principles behind leading approaches, we also emphasize open challenges and problems that remain unresolved. we argue that not only does the current academic formulation lack key components of the true routing problem - such as scenic control, layer directives, and capabilities for integration with physical synthesis - but also that present methods are likely to fail when extended toward the more generalized formulation. finally, we offer a revised incarnation of the ispd benchmarks to encourage continued progress in the research community.
a variation-aware preferential design approach for memory based reconfigurable computing. static random access memory (sram) arrays designed in sub-90nm technologies are highly vulnerable to process variation induced read/write/access failures. in memory based reconfigurable computing frameworks, which use large high density memory array, such failures lead to incorrect execution of mapped applications. it causes loss in quality of service (qos) for digital signal processing (dsp) applications. we propose a "preferential design" approach at both application mapping and circuit level, which can significantly improve qos and yield under large parameter variations. such a architecture/circuit co-design approach can also tolerate increased failure rate at low operating voltage, thus facilitating low-power operation. simulation results for a common dsp application show 45% improvement in power at iso--qos and 47% in yield for a target peak signal to noise ratio (psnr) at 45nm technology.
a rigorous framework for convergent net weighting schemes in timing-driven placement. we present a rigorous framework that defines a class of net weighting schemes in which unconstrained minimization is successively performed on a weighted objective. we show that, provided certain goals are met in the unconstrained minimization, these net weighting schemes are guaranteed to converge to the optimal solution of the original timing-constrained placement problem. these are the first results that provide conditions under which a net weighting scheme will converge to a timing optimal placement. we then identify several weighting schemes that satisfy the given convergence properties and implement them, with promising results: a modification of the weighting scheme given in [11]results in consistently improved delay over the original, 4% on average, without increase in computation time.
fast trade-off evaluation for digital signal processing systems during wordlength optimization. this paper presents a novel precision analysis approach, which optimizes the fractional wordlengths of signals in digital signal processing systems. quantization-operation-error model is proposed to formulate the quantization error bound propagations through modules. based on that, explicit relationship between output accuracy and hardware cost is built up, and a greedy search algorithm is proposed to find the minimum implementation cost while meeting output error constraint. moreover, the greedy search steps can form a near pareto-optimal front, which can be used for a fast trade-off evaluation between output accuracy and implementation cost, such as area, power and latency. experimental results and comparisons with existing state-of-the-art methods demonstrate the efficiency of proposed approach.
from 2d to 3d nocs: a case study on worst-case communication performance. advanced integration technologies enable the construction of network-on-chip (noc) from two dimensions to three dimensions. studies have shown that 3d nocs can improve average communication performance because of the possibility of using the additional dimension to shorten communication distance. in this paper, we present a detailed case study on worst-case communication performance in regular k-ary-2-mesh networks. through both analysis and simulation, we show that, while 3d networks achieve better average performance, this may not be the case for worst-case performance mainly due to constraints on vertical channels. our analysis is based on network calculus, which allows to calculate theoretical delay bounds for constrained flows traversing network elements.
remis: run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. reconfigurable processors provide a means to flexible and energy-aware computing. in this paper, we present a new scheme for runtime energy minimization (remis) as part of a dynamically reconfigurable processor that is exposed to run-time varying constraints like performance and footprint (i.e. amount of reconfigurable fabric). the scheme chooses an energy-minimizing set of so-called special instructions (considering leakage, dynamic, and reconfiguration energy) and then 'power-gates' a temporarily unused subset of the special instruction set. we provide a comprehensive evaluation for different technologies (ranging from 65 nm to 150 nm) and thereby show that our scheme is technology independent, i.e. it is beneficial for various technologies alike. by means of an h.264 video encoder we demonstrate that for certain performance constraints our scheme (applied to our in-house reconfigurable processor) achieves an allover energy saving of up to 40.8% (avg. 24.8%) compared to a performance-maximizing scheme. we also demonstrate that our scheme is equally beneficial to various other state-of-the-art reconfigurable processor architectures like molen [9] where it achieves energy savings of up to 48.7% (avg. 28.93%) at 65 nm. we have employed an h.264 encoder within this paper as an application in order to demonstrate the strengths of our scheme, since the h.264's complexity and run-time unpredictability present a challenging scenario for state-of-the-art architectures.
synthesizing complementary circuits automatically. one of the most difficult jobs in designing communication and multimedia chips, is to design and verify complex complementary circuit pair (e, e-1), in which circuit e transforms information into a format that is suitable for transmission and storage, while e's complementary circuit e-1 recovers this information. in order to ease this job, we propose a novel two-step approach to synthesize complementary circuit e-1 from e fully automatically. first, we assume that the circuit e satisfies parameterized complementary assumption, which means its input can be recovered from its output under some parameter setting. we check this assumption with sat solver and find out proper values of these parameters. second, with parameter values and the sat instance obtained in the first step, we build the complementary circuit e-1 with an efficient satisfying assignments enumeration technique that is specially designed for circuits with lots of xor gates. to illustrate its usefulness and efficiency, we run our algorithm on several complex encoders from industrial projects, including pcie and 10g ethernet, and successfully generate correct complementary circuits for them.
nonvolatile memristor memory: device characteristics and design implications. the search for new nonvolatile universal memories is propelled by the need for pushing power-efficient nanocomputing to the next higher level. as a potential contender for the next-generation memory technology of choice, the recently found "the missing fourth circuit element", memristor, has drawn a great deal of research interests. in this paper, we characterize the fundamental electrical properties of memristor devices by encapsulating them into a set of compact closed-form expressions. our derivations provide valuable design insights and allow a deeper understanding of key design implications of memristor-based memories. in particular, we investigate the design of read and write circuits and analyze data integrity and noise-tolerance issues.
compacting test vector sets via strategic use of implications. as the complexity of integrated circuits has increased, so has the need for improving testing efficiency. unfortunately, the types of defects are also becoming more complex, which in turn makes simple approaches for testing inadequate. using n-detect testing can improve detect coverage; however, this approach can greatly increase the test set size. in this proof-of-concept paper we investigate the use of logic implication checkers, inserted in hardware, as an aid in compacting n-detect test sets. we show that checker hardware with minimal area overhead can reduce test set size by up to 25%. in addition, this implication checker can serve a dual purpose for online error detection.
a methodology for robust, energy efficient design of spin-torque-transfer ram arrays at scaled technologies. in this paper we propose a methodology for energy efficient spin-torque-transfer random access memory (sttram) array design at scaled technology nodes. we present a model to estimate and analyze the energy dissipation of an sttram array. the presented model shows the strong dependence of the array energy on the silicon transistor width, word line voltage and row/column organization. using the array energy model we propose a design methodology for sttram arrays which minimizes the energy dissipation while maintaining the required robustness in read and write operations at scaled technologies.