waashk/dblp huggingface dataset:
design of pipeline analog-to-digital converters via geometric programming. in this paper we present a method for the design of analog-todigital converters (adcs). this method computes the sizes of the different components (transistors, capacitors, etc.) in a predefined adc topology so that the design specifications are met in the desired process technology.the method is based on formulating the adc design constraints such as specifications on power, signal-to-noise ratio (snr), area, and sampling frequency in special convex form in terms of the component sizes of the adc and intermediate design variables. more specifically, we cast the problem of sizing the components of the adc as a geometric program. therefore, all design constraints are formulated as posynomial inequality or monomial equality constraints. very efficient numerical algorithms are then used to solve the resulting geometric program and to compute the component sizes of an adc that meets the desired specifications. the synthesis method is fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected.this paper introduces the concept of hierarchical problem formulation within a geometric programming framework. this modular formulation allows a high re-use of the adc posynomial model.
design and optimization of lc oscillators. we present a method for optimizing and automating component and transistor sizing for cmos lc oscillators. we observe that the performance measures can be formulated as posynomial functions of the design variables. as a result, the lc oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. the synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. we can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power.
energy efficient address assignment through minimized memory row switching. data transfer intensive applications consume a significant amount of energy in memory access. the selection of a memory location from a memory array involves driving row and column select lines. a signal transition on a row select line often consumes significantly more energy than a transition on a column select line. in order to exploit this difference in energy consumption of row and column select lines, we propose a novel address assignment methodology that aims to minimize high energy row transitions by assigning spatially and temporally local data items to the same row. the problem of energy efficient address assignment has been formulated as a multi-way graph partitioning problem and solved with a heuristic. our experiments demonstrate that our methodology achieves row transition counts very close to the optimum and that the methodology can, for some examples, reduce row transition count by 40--70% over row major mapping. moreover, we also demonstrate that our methodology is capable of handling access sequences with over 15 million accesses in moderate time.
model reduction of variable-geometry interconnects using variational spectrally-weighted balanced truncation. this paper presents a spectrally-weighted balanced truncation technique for rlc interconnects, a technique needed when the interconnect circuit parameters change as a result of variations in the manufacturing process. the salient features of this algorithm are the inclusion of parameter variations in the rlc interconnect, the guaranteed stability of the reduced transfer function, and the availability of provable frequency-weighted error bounds for the reduced-order system. this paper shows that the balanced truncation technique is an effective model-order reduction technique when variations in the circuit parameters are taken into consideration. experimental results show that the new variational spectrally-weighted balanced truncation attains, on average, 20% more accuracy than the variational krylov-subspace-based model-order reduction techniques while the run-time is also, on average, 5% faster.
lazy group sifting for efficient symbolic state traversal of fsms. this paper proposes lazy group sifting for dynamic variable re-ordering during state traversal. the proposed method relaxes the idea of pairwise grouping of present state variables and their corresponding next state variables. this is done to produce better variable orderings during image computation without causing bdd size blowup in the substitution of next state variables with present state variables at the end of image computation. experimental results show that our approach is more robust in state traversal than the approaches that either unconditionally group variable pairs or never group them.
boom - a heuristic boolean minimizer. we present a two-level boolean minimization tool (boom) based on a new implicant generation paradigm. in contrast to all previous minimization methods, where the implicants are generated bottom-up, the proposed method uses a top-down approach. thus instead of increasing the dimensionality of implicants by omitting literals from their terms, the dimension of a term is gradually decreased by adding new literals. unlike most other minimization tools like espresso, boom doesn't use the definition of the function to be minimized as a basis for the solution, thus the original coverage influences the solution only indirectly through the number of literals used.most minimization methods use two basic phases introduced by quine-mccluskey, known as prime implicant (pi) generation and the covering problem solution. some more modern methods, like espresso, combine these two phases, reducing the number of pis to be processed. this approach is also used in boom, the search for new literals to be included into a term aims at maximum coverage of the output function.the function to be minimized is defined by its on-set and off-set, listed in a truth table. thus the don't care set, often representing the dominant part of the truth table, need not be specified explicitly. the proposed minimization method is efficient above all for functions with a large number of input variables while only few care terms are defined.the minimization procedure is very fast, hence if the first solution does not meet the requirements, it can be improved in an iterative manner. the method has been tested on several different kinds of problems, like the mcnc standard benchmarks or larger problems generated randomly.
a fast crosstalk- and performance-driven multilevel routing system. in this paper, we propose a novel framework for fast multilevelrouting considering crosstalk and performance optimization. to handlethe crosstalk minimization problem, we incorporate an intermediatestage of layer/track assignment into the multilevel routing framework.for performance-driven routing, we propose a novel minimum-radiusminimum-cost spanning-tree (mrmcst) heuristic for global routing.compared with the state-of-the-art multilevel routing, the experimentalresults show that our approach achieved a 6.7x runtime speedup, reducedthe respective maximum and average crosstalk (coupling length)by about 30% and 24%, reduced the respective maximum and averagedelay by about 15% and 5%, and resulted in fewer failed nets.
interconnect scaling implications for cad. interconnect scaling to deep submicron processes presents many challenges to today's cad flows. a recent analysis by sylvester and keutzer examined the behavior of average length wires under scaling, and controversially concluded that current cad tools are adequate for future module-level designs. in our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. however, examining only average length wires is optimistic, since long wires are the ones that primarily cause cad tool exceptions. in a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. more importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. thus, if the design team size and per-designer workload is to remain relatively constant, future cad tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention.
smart simulation using collaborative formal and simulation engines. we present ketchum, a tool that was developed to improve the productivity of simulation-based functional verification by providing two capabilities: (1) automatic test generation and (2) unreachability analysis. given a set of "interesting" signals in the design under test (dut), automatic test generation creates input stimuli that drive the dut through as many different combinations (called coverage states) of these signals as possible to thoroughly exercise the dut. unreachability analysis identifies as many unreachable coverage states as possible.ketchum differs from the previous published results for several reasons. first, ketchum provides 10x higher capacity than previous published results. the higher capacity is achieved by carefully orchestrating simulation and multiple formal methods including symbolic simulation, sat-based bmc, symbolic fixpoint computation and automatic abstraction. second, ketchum performs not only automatic test generation but also unreachability analysis, which enables the test generation effort to be focused on coverage states that are not unreachable. third, the backbone of ketchum is an off-the-shelf commercial simulator. it enables ketchum to reach deep states of the design quickly and supports simulation monitors through the standard api of the simulator during test generation.we applied ketchum to several industrial designs, including the picojava microprocessor from sun and the dw8051 microcontroller from synopsys and obtained very promising results. the experiments show that ketchum can (1) handle design blocks containing more than 4500 latches and 170k gates, (2) reach up to 6x more coverage states than random simulation and (3) identify a majority of the unreachable coverage states.
synthesis of operation-centric hardware descriptions. most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (cfsm) as the underlying abstraction. in the cfsm framework, a designer explicitly manages the concurrency by scheduling the exact cycle-by-cycle interactions between multiple concurrent state machines. design mistakes are common in coordinating interactions between two state machines because transitions in different state machines are not semantically coupled. it is also difficult to modify one state machine without considering its interaction with the rest of the system.this paper presents a method for hardware synthesis from an "operation centric" description, where the behavior of a system is described as a collection of "atomic" operations in the form of rules. typically, a rule is defined by a predicate condition and an effect on the state of the system. the atomicity requirement simplifies the task of hardware description by permitting the designer to formulate each rule as if the rest of the system is static.an implementation can execute several rules concurrently in a clock cycle, provided some sequential execution of those rules can reproduce the behavior of the concurrent execution. in fact, detecting and scheduling valid concurrent execution of rules is the central issue in hardware synthesis from operation-centric descriptions. the result of this paper shows that an operation-centric framework offers significant reduction in design time, without loss in implementation quality.
a methodology for the design of application specific instruction set processors (asip) using the machine description language lisa. the development of application specific instruction set processors (asip) is currently the exclusive domain of the semiconductor houses and core vendors. this is due to the fact that building such an architecture is a difficult task that requires expertise knowledge in different domains: application software development tools, processor hardware implementation, and system integration and verification. this paper presents a retargetable framework for asip design which is based on machine descriptions in the lisa language. from that, software development tools can be automatically generated including hll c-compiler, assembler, linker, simulator and debugger frontend. moreover, synthesizable hdl code can be derived which can then be processed by standard synthesis tools. implementation results for a low-power asip for dvb-t acquisition and tracking algorithms designed with the presented methodology will be given.
corner block list: an effective and efficient topological representation of non-slicing floorplan. in this paper, a corner block list -- a new efficient topological representation for non-slicing floorplan is proposed with applications to vlsi floorplan and building block placement. given a corner block list, it takes only linear time to construct the floorplan. unlike the o-tree structure, which determines the exact floorplan based on given block sizes, corner block list defines the floorplan independent of the block sizes. thus, the structure is better suited for floorplan optimization with various size configurations of each block. based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. soft blocks and the aspect ratio of the chip are taken into account in the simulated annealing process. the experimental results demonstrate the algorithm is quite promising.
bus optimization for low-power data path synthesis based on network flow method. sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and rt level of design. this paper addresses the problem of minimizing power dissipated in switching of the buses in data path synthesis. unlike the previous approaches in which minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on reduction of power dissipated on the buses more fully and effectively. we accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds maximum flow of minimum cost solutions in the network. experimental results on a number of benchmark problems show that given resource and global timing constraints our designs are 22% power-efficient over the designs produced by a random-move based solution, and 18% power-efficient over the designs by a clock-step based optimal solution.
power optimization in disk-based real-time application specific systems. while numerous power optimization techniques have been proposed at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-electronic subsystems, such as disks, has not been addressed. we propose a conceptually simple, but realistic power consumption model for disk drives. we present heuristics for optimization of power consumption in several common hard real-time disk-based design systems. we show how to coordinate task scheduling and disk data assignment, in order to minimize power consumption in both electronic and mechanical components of used disks. extensive experimental results indicate significant power reduction.
throughput optimization of general non-linear computations. this paper addresses an optimal technique for throughput optimization of general non-linear data flow computations using a set of transformations. throughput is widely recognized as the most important design metric of the modern dsp and communication applications. numerous approaches have been proposed for throughput optimization, but most was restricted to limited classes of computations. they have limited effectiveness when applied to large complex non-linear dsp and communication computations. the new technique is used as an optimization engine in a divide-and-conquer global approach for throughput optimization. we demonstrate the effectiveness of the new technique on numerous real-life non-linear designs.
power optimization using divide-and-conquer techniques for minimization of the number of operations. we develop an approach to minimizing power consumption of portable wireless dsp applications using a set of compilation and architectural techniques. the key technical innovation is a novel divide-and-conquer compilation technique to minimize the number of operations for general dsp computations. our technique optimizes not only a significantly wider set of computations than the previously published techniques, but also outperforms (or performs at least as well as other techniques) on all examples. along the architectural dimension, we investigate coordinated impact of compilation techniques on the number of processors which provide optimal trade-off between cost and power. we demonstrate that proper compilation techniques can significantly reduce power with bounded hardware cost. the effectiveness of all techniques and algorithms is documented on numerous real-life designs.
a novel dimension reduction technique for the capacitance extraction of 3d vlsi interconnects. in this paper, we present a new capacitance extraction method named dimension reduction technique (drt) for 3d vlsi interconnects. the drt converts a complex 3d problem into a series of cascading simple 2d problems. each 3d problem is solved separately, so we can choose the most efficient method according to the arrangement of conductors. more importantly, it is very easy to obtain the analytical solutions of 2d problem in many layers such as the pure dielectric layers and the layers with parallel signal lines. therefore, the domain that has to be analyzed numerically is minimized. this leads to the drastic reduction of the computing time and memory needs. we have used the drt to extract the capacitances of multilayered and multiconductor cross-overs, bends, via with signal lines and open-end. the results are in good agreement with those of ansoft's spicelink and mit's fastcap, but the computing time and memory size used by the drt are several even tens times less than those used by spicelink and fastcap.
factoring and eliminating common subexpressions in polynomial expressions. polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities for optimization. however existing compiler techniques for reducing code complexity such as common subexpression elimination and value numbering are targeted towards general purpose applications and are unable to fully optimize these expressions. this work presents algorithms to reduce the number of operations to compute a set of polynomial expression by factoring and eliminating common subexpressions. these algorithms are based on the algebraic techniques for multi-level logic synthesis. experimental results on a set of benchmark applications with polynomial expressions showed an average of 42.5% reduction in the number of multiplications and 39.6% reduction in the number of clock cycles for computation of these expressions on the arm processor core, compared to common subexpression elimination.
effects of delay models on peak power estimation of vlsi sequential circuits. previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. however, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulation is expensive. thus, we would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays. results for four delay models are reported for the iscas85 combinational benchmark circuits, iscas89 sequential benchmark circuits, and several synthesized circuits.
synchronous equivalence for embedded systems: a tool for design exploration. this paper presents a new protocol for parallel and distributed simulation of vlsi systems. it is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. all these features make it very convenient and practical, extending the class of applications to at least all vhdl circuits, including delta cycle. the proposed protocol has been implemented and used for vhdl simulation. experimental results on several large vhdl circuits (between 1411 and 14704 processes) have shown promising linear speedups. we also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. this protocol may have a string impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.
a vectorless estimation of maximum instantaneous current for sequential circuits. both the ir drop and em problems require accurate analysis of maximum instantaneous current (mic) on the power supply bus. we propose a vectorless approach to deriving a tight upper bound on mic. we first characterize different types of signal correlation which may cause the mic estimation to lose accuracy. we next propose theorems to identify gates which switch mutually exclusively, taking into account correlation across sequential elements (flip-flops). note that previous research of this topic addressed on combinational circuits only. after obtaining the information of mutually exclusive switching, we then apply a graph algorithm to obtain an upper bound on mic. in average, our results on sequential benchmarks are 212% tighter than those from imax and 129% tighter than those from pie based on h. kriplani et al. (1995).
statistical sampling and regression analysis for rt-level power evaluation. in this paper, we propose a statistical power evaluation framework at the rt-level. we first discuss the power macro-modeling formulation, and then propose a simple random sampling technique to alleviate the the overhead of macro-modeling during rtl simulation. next, we describe a regression estimator to reduce the error of the macro-modeling approach. experimental results indicate that the execution time of the simple random sampling combined with power macro-modeling is 50 x lower than that of conventional macro-modeling while the percentage error of regression estimation combined with power macro-modeling is 16 x lower than that of conventional macro-modeling. hence, we provide the designer with options to either improve the accuracy or the execution time when using power macro-modeling in the context of rtl simulation.