waashk/dblp huggingface dataset:
bsg-route: a length-matching router for general topology. length-matching routing is a very important issue for pcb routing. previous length-matching routers [1]--[3] all have assumptions on the routing topology whereas practical designs may be free of any topological constraint. in this paper, we propose a router that deals with general topology. unlike previous routers, our router does not impose any restriction on the routing topology. moreover, our router is gridless. its performance does not depend on the routing grid size of the input while routers in [1]--[3] do. this is a big advantage because modern pcb routing configurations usually imply huge routing grids. the novelty of this work is that we view the length-matching routing problem as an area assignment problem and use a placement structure, bounded-sliceline grid (bsg) [4], to help solving the problem. experimental results show that our router can handle practical designs that previous routers can't handle. for designs that they could handle, our router runs much faster. for example, in one of our data, we obtain the result in 88 seconds while the router in [3] takes more than one day.
architecting parallel programs. the current shift from sequential to multicore and manycore processors presents serious challenges to software developers. a significant part of the industrial and research communities believes that either a) they can squeak by or b) the right compiler, parallel language etc will save them. such ad hoc responses are likely to prove neither correct nor sustainable. to systematically find and exploit parallelism, and to achieve forward scalability --- that is, designs which efficiently scale to much larger numbers of cores --- will require re-architecting software applications such as eda. we believe that the key to re-architecting software is the use of design patterns and a pattern language. furthermore, structural patterns (aka architectural styles) and computational patterns (aka the thirteen dwarfs) are the key high-level design patterns. the patterns are then used to create programming frameworks that can be used to facilitate implementation of the software architecture. this tutorial presents the most recent research results by uc berkeley and intel. we will present our working pattern language and give examples on its use in eda and other application areas.
cad for displays! we take displays for granted in devices like our laptops, television, cell phones, and cars -to name a few places. the tft lcd processes in use now are as mature as cmos was 20 years ago, which is when we started seeing asic companies doing fabless chip design and investing heavily in cad. today, the display, as i believe i showed while working on the olpc, is really just an asic! why focus on the display? the display is the most expensive and power hungry component in your laptops, it can now be "taped out" just like an asic using standard tft lcd fabs, and -in the limit- the laptop or the cell phone will become just a display in which the electronics are integrated into. i believe that we are about to see a revolution in display design, with gradual subsumption of more and more of the cpu and motherboard electronics, to further drive down cost and power consumption. the acm portal is published by the association for computing machinery. copyright © 2010 acm, inc. terms of usage privacy policy code of ethics contact us useful downloads: adobe acrobat quicktime windows media player real player
exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinates. as the semiconductor technology is scaling down to nanometer regime, accurate layout analysis requires operations with simulated contours of vlsi layouts which are non-rectilinear. the basic operations on non-rectilinear shapes include "intersection", "difference", "union", "find connected components" and "find boundary". whatever precision one would choose for the representation of vertices of shapes a and b the exact representation of, say, a&cap;b would require an even higher precision. consequently rounding of intermediate results of a chain of basic operations seems to be inevitable. the presence of rounding errors is unacceptable because the implementation of algorithms for all operations which involve topology, such as "find connected components", " find boundary", etc, becomes impossible or extremely complex we present a complete solution to the following problem: let a vlsi design or a simulated through a lithography process image of a vlsi design be given by a number of two-dimensional point sets. each point set consists of polygons with arbitrary (not necessarily 90&deg;) angles and with vertices on an integer grid. perform any amount of sequential basic operations so that: &bull; the resulting point sets are mathematically exact, that is no rounding errors are allowed. in particular the connectivity of the point sets remains intact, the boundaries remain undistorted and the statements like "a = (a \ b) &cup; (a &cap; b)", "(a \ b) is disjoint with b" and "a &cap; b &sub; a" always hold. &bull; the amount of time and memory per one basic geometric operation on elementary polygons (trapezoids) is constant. for example it would not be an acceptable solution to represent the vertices of the new shapes which appear as a result of the operations of intersection, difference, etc, by unlimited length rational numbers.
statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. for the first time, a new source of random threshold voltage (vth) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. the new source of variability, christened work-function variation (wfv), is caused by the dependency of metal work-function on the orientation of its grains. a statistical framework is developed, which enables estimation of the key parameters of work-function distribution by identifying the physical dimensions of the devices and properties of materials used in the fabrication. this paper offers three major contributions for process, device and circuit designers. first, the proposed model can be employed to identify suitable materials and fabrication processes that can reduce the impact of vth fluctuation due to wfv. for instance, four types of metal nitride gate materials (tin and tan for nmos and wn and mon for pmos devices) are studied and it is shown that tin and wn result in lower vth fluctuation. second, device engineers can benefit from the result of this work by evaluating the wfv level of various types of classical or non-classical metal-gate cmos transistors. as an example, it is shown that finfet transistors are less affected by wfv compared to fd-soi and bulk-si devices due to their larger gate area. third, circuit designers can utilize this model to investigate the impact of such a variation on the key performance and reliability parameters of the circuits. for instance, an sram cell is analyzed in the presence of vth fluctuations due to wfv and it is shown that such variations can result in considerable performance and reliability degradation.
silicon feedback to improve frequency of high-performance microprocessors: an overview. in modern high-performance microprocessors designed using advanced process technologies, the frequency of the part is often slower than what the static timing analysis tools predict before tape out. we give an overview of techniques used to observe the failing path on the tester, identify the dominant devices impacting the delay of the path, and learn from the failing path to fix other similar paths in the design. in particular, we describe a support vector machine based approach for learning from speedpaths observed in silicon.
pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. pulsed latches, latches driven by a brief clock pulse, offer the convenience of flip-flop-like timing verification and optimization, while retaining superior design parameters of latches over flip-flops. but, pulsed latch-based design using a single pulse width has a limitation in reducing clock period. the limitation still exists even if clock skew scheduling is employed, since the amount of skew that can be assigned is practically limited due to process variations. the problem of allocating pulse width (out of discrete number of predefined widths) and scheduling clock skew (within prescribed upper bound) is formulated, for the first time, for optimizing pulsed latch-based sequential circuits. an allocation algorithm called pwcs_optimize is proposed to solve the problem. experiments with 65-nm technology demonstrate that small number of variety of pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield minimum clock period for many benchmark circuits. the design flow including pwcs_optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.
process variation aware system-level task allocation using stochastic ordering of delay distributions. design variability due to within-die and die-to-die variations has potential to significantly reduce the maximum operating frequency and effective performance of the system in future process technology generations. when multiple cores in mpsoc have different delay distributions, the problem of assigning tasks to the cores become challenging. this paper targets system level task allocation to stochastically minimize the total execution time of an application on mpsoc under process variation. in this work, we first introduce stochastically optimal task allocation problem. we provide formal theorems of the optimality of the solution in simple scenarios. we extend our theoretical work for generic cases in normal distribution. the proposed techniques enable efficient computation of task allocation using non-stochastic analysis. we apply these techniques in allocating tasks in the embedded system benchmark suites on mpsoc. we show that deterministic solution for system-level task allocation on widely used benchmark topologies and distributions (normal distribution) is almost as good as the best probabilistic solution.
constraint graph-based macro placement for modern mixed-size circuit designs. in this paper, we propose a constraint graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs. improving over the constraint graph by working only on its essential edges without loss of the solution quality, our algorithm can search for high-quality macro placement solutions effectively and efficiently. instead of packing macros along chip boundaries like most recent previous work, our placer can determine a non-compacted macro placement by linear programming and placement region cost evaluation and handle various placement constraints/objectives. compared with various leading academic macro placers, our algorithm can consistently and significantly reduce the wirelengths for designs with different utilization rates, implying that our macro placer is robust and has very high quality.
more moore: foolish, feasible, or fundamentally different? moore's law has been a foundation of modern electronics, sustained primarily by scaling. but can this continue despite the serious problems of litho, variability, device physics, and cost? this panel looks at several possibilities. perhaps moore's law will muddle through, as it has so far, with a combination of tools, process, and design. but even if technically possible, moore's law is in practice driven by economics, and economics might turn against further scaling. also, we've all seen how performance of single cores has topped out, despite scaling. might this be a fundamental problem with planar technologies, prompting the need to go 3-d to get further performance increases? or might cmos itself give way to other technologies, allowing moore's law yet another respite? compare and contrast for yourself these four very different visions of the future of your job, your industry, and your personal gadgets.
a highly efficient optimization algorithm for pixel manipulation in inverse lithography technique. an efficient algorithm based on the pixel-based mask representation is proposed for fast synthesis of model-based inverse lithography technology (ilt) to improve the resolution and pattern fidelity in optical lithography. this new algorithm reduces n2 intensity computations to three (3) equivalent intensity computations per iteration, where n2 is the total number of pixels in a mask. this algorithm has been demonstrated using different critical dimensions (cds) and different mask technologies with incoherence and partial-coherence image models. this algorithm is about 60 times faster and more effective than the current gradient-based algorithm. the final image fidelity has quite a weak dependence on the initial condition. good fidelity images are achieved when cd is reduced to 45nm.
adjustment-based modeling for statistical static timing analysis with high dimension of variability. this paper presents an adjustment-based modeling framework for statistical static timing analysis (ssta) when the dimension of parameter variability is high. instead of building a complex model between the circuit timing and parameter variability, we build a model which adjusts an approximate variation-aware timing into an accurate one. the intuition is that it is simpler to build a model which adjusts an approximate estimate into an accurate one. it is also more efficient to obtain an approximate circuit timing model. the combination of these two observations makes the use of an adjustment-based model a good choice for ssta with high dimension of parameter variability. to build the adjustment model, we use a simulation-based approach, which is based on gaussian process. combined with intelligent sampling, we show that an adjustment-based model can more effectively capture the nonlinearity of the circuit timing with respect to parameter variability compared to polynomial modeling. we also show that with only 200 samples of the circuit timing and 42 independent parameter variations, adjustment-based modeling obtains higher accuracy than direct ssta using quadratic modeling.
module locking in biochemical synthesis. we are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent logic synthesis. our method synthesizes biochemical reactions that compute output quantities of molecular types as a function of input quantities, either deterministically or probabilistically. an important constraint is the timing, captured in the relative rates of the biochemical reactions: all the outputs of a given phase must be produced before the next phase can begin consuming them as inputs. to achieve this synchronization, the reaction rates must sometimes be separated by orders of magnitude: some much faster than others, some much slower. this might be costly or infeasible given a specific library of biochemical reactions. in this paper, we describe a novel mechanism for locking the computation of biochemical modules - analogous to handshaking mechanisms in asynchronous circuit design. with locking, our method synthesizes robust computation that is nearly rate independent, requiring at most two speeds ("fast" and "slow"). the trade-off is with respect to the size of the solution: more reactions are needed. we characterize this trade-off for inter-and intra-module locking in general and for a variety of specific modules that we have designed. in particular, we discuss locking in detail for a stochastic module that implements probabilistic computation, producing different combinations of molecular types according to specified probability distributions.
efficient block-based parameterized timing analysis covering all potentially critical paths. in order for the results of timing analysis to be useful, they must provide insight and guidance on how the circuit may be improved so as to fix any reported timing problems. a limitation of many recent variability-aware timing analysis techniques is that, while they report delay distributions, or verify multiple corners, they do not provide the required guidance for re-design. we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delay at every point in the parameter space, by reporting all paths that can become critical. using an efficient pruning algorithm, only those potentially critical paths are carried forward, while all other paths are discarded during propagation. this allows one to examine local robustness to parameters in different regions of the parameter space, not by considering differential sensitivity at a point (which would be useless in this context) but by knowledge of the paths that can become critical at nearby points in parameter space. we give a formal definition of this problem and propose a technique for solving it that improves on the state of the art, both in terms of theoretical computational complexity and in terms of run time on various test circuits.
post-silicon timing characterization by compressed sensing. we address post-silicon characterization of the unique gate delays and their timing distributions on each manufactured ic. our proposed approach is based upon the new theory of compressed sensing. the first step in performing timing measurements is to find the sensitizable paths by traditional testing methods. next, we show that the timing variations are sparse in the wavelet domain. the sparsity is exploited for estimation of the gate delays using the compressed sensing theory. this estimation method requires significantly less number of timing measurements compared to the case where the dependence between the gate delays is not directly integrated within the estimation framework. we discuss a number of applications for the new post-silicon timing characterization method. experimental results on benchmark circuits show that using compressed sensing theory can characterize the post-silicon variations with a mean accurately of 95% in the pertinent sparse basis.
sparse implicit projection (sip) for reduction of general many-terminal networks. this paper is concerned with model order reduction of large scale dynamic systems that have sparse matrix representations, particularly systems with large numbers of input/output "ports." we present an algorithm that combines the advantages of widely-used approaches such as prima and ticer but avoids many of the drawbacks of both. the resulting algorithm is capable of highorder rational approximation, exploits network sparsity, preserves passivity, can be extended to general non-symmetric systems, and can be applied to networks with hundreds or thousands of ports. we develop a common mathematical framework that can encompass all three algorithms, show mathematical relations between them, and point out certain special cases where they are equivalent. we show examples from analysis of industrial on-chip rc/rlc networks that demonstrate performance advantages of more than three orders of magnitude.
evaluation of voltage interpolation to address process variations. post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. this paper explores design considerations and vlsi-cad support for a recently proposed postfabrication tuning knob called voltage interpolation. the paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. the paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks and shows that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. the analysis shows that the scheme can match the nominal delay target with a 10% power cost, or for the same power budget, incur only a 9% delay overhead after variations.
verifying external interrupts of embedded microprocessor in soc with on-chip bus. the microprocessor verification challenge becomes higher in the on-chip bus (ocb) than in the unit-level. especially for the external interrupts, since they interface with other ip components, they suffer from the complicated bus protocol and ip conflict problems. this paper proposes a automatic method to verify the microprocessor external interrupt behaviors on the ocb. the verification approach is based on the processor external interrupt verification tool (pevt) whose simulation environment is direct-connected memory. in this paper, we implement the pevt-soc and successfully verify two soc platforms, one academic microprocessor and one public domain microprocessor. an interesting bug appears that is impossible to be discovered in the memory bus and not easy to be identified on the ocb. the result shows that the pevt-soc effectively shortens the verification time regardless of the system complexity and can be easily migrated to different platforms/microprocessors. with little human effort, even an inexperience designer can generate extensive verification cases in a systematic way.
graphene nanoribbon fets: technology exploration and cad. graphene nanoribbon fets (gnrfets) have emerged as a promising candidate for nanoelectronics applications. this paper summarizes (i) current understanding and prospects for gnrfets as ultimately scaled, ideal ballistic transistors, (ii) physics-based modeling of gnrfets to support circuit design and cad, and (iii) variability and defects in gnrs and their impact on gnrfet circuit performance and reliability.
breaking the simulation barrier: sram evaluation through norm minimization. with process variation becoming a growing concern in deep submicron technologies, the ability to efficiently obtain an accurate estimate of failure probability of sram components is becoming a central issue. in this paper we present a general methodology for a fast and accurate evaluation of the failure probability of memory designs. the proposed statistical method, which we call importance sampling through norm minimization principle, reduces the variance of the estimator to produce quick estimates. it builds upon the importance sampling, while using a novel norm minimization principle inspired by the classical theory of large deviations. our method can be applied for a wide class of problems, and our illustrative examples are the data retention voltage and the read/write failure tradeoff for 6t sram in 32 nm technology. the method yields computational savings on the order of 10000x over the standard monte carlo approach in the context of failure probability estimation for sram considered in this paper.