waashk/dblp huggingface dataset:
time domain analysis of nonuniform frequency dependent high-speed interconnects. a method based on numerical inversion of the laplace transform for the transient analysis of nonuniform high-speed interconnects in lsi/vlsi circuits is described. the interconnects are treated as lossy multiconductor nonuniform frequency dependent transmission lines. an algorithm for overcoming the inherent initial value instability encountered while numerically integrating transmission line equations is described. the method is directly compatible with the piecewise decomposition technique (pdt) and can be extended to interconnect networks with nonlinear terminations. further speed up can be achieved by using parallel processors. examples and comparisons with published results are presented
schedulability analysis of multiprocessor real-time applications with stochastic task execution times. this paper presents an approach to the analysis of task sets implemented on multiprocessor systems, when the task execution times are specified as generalized probability distributions. because of the extreme complexity of the problem, an exact solution is practically impossible to be obtained even for toy examples. therefore, our methodology is based on approximating the generalized probability distributions of execution times by coxian distributions of exponentials. thus, we transform the generalized semi-markov process, corresponding to the initial problem, into a continuous markov chain (ctmc) which, however, is extremely large and, hence, most often is impossible to be stored in memory. we have elaborated a solution which allows to generate and analyze the ctmc in an efficient way, such that only a small part has to be stored at a given time. several experiments investigate the impact of various parameters on complexity, in terms of time and memory, as well as the trade-offs regarding the accuracy of generated results.
system-level routing of mixed-signal asics in wren. techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal asic are discussed. a comparatively simple geometric model of the problem is combined with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets
verification of executable pipelined machines with bit-level interfaces. we show how to verify pipelined machine models with bit-level interfaces by using a combination of deductive reasoning and decision procedures. while decision procedures such as those implemented in uclid can be used to verify pipelined machines, the models are at the term level: they abstract away the datapath, require the use of numerous abstractions, implement a small subset of the instruction set, and are far from executable. in contrast, we focus on verifying executable machines with bit-level interfaces. such proofs have previously required substantial expert guidance and the use of deductive reasoning engines. we show that by integrating uclid with the acl2 theorem proving system, we can use acl2 to reduce the proof that an executable, bit-level machine refines its instruction set architecture to a proof that a term level abstraction of the bit-level machine refines the instruction set architecture, which is then handled automatically by uclid. in this way, we exploit the strengths of acl2 and uclid to prove theorems that are not possible to even state using uclid and that would require prohibitively more effort using just acl2.
a complete compositional reasoning framework for the efficient verification of pipelined machines. we present a compositional reasoning framework based on refinement for verifying that pipelined machines satisfy the same safety and liveness properties as their instruction set architectures. our framework consists of a set of convenient, easily-applicable, and complete compositional proof rules. we show that our framework greatly extends the applicability of decision procedures by verifying a complex, deeply pipelined machine that state-of-the-art tools cannot currently handle. we discuss how our framework can be added to the design cycle and highlight what arguably is the most important benefit of our approach over current methods, that the counterexamples generated are much simpler, as bugs are isolated to a particular step in the composition proof.
unified complete mosfet model for analysis of digital and analog circuits. in this paper, we describe the complete mosfet model developed for circuit simulations. the model describes all transistor characteristics as functions of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. the key idea of this development is to put as much physics as possible into the equations describing the surface potentials. since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. the unified treatment of our model allows all transistor characteristics to be calculated without any nonphysical fitting parameters. additionally the calculation time is drastically reduced in comparison with a conventional piece-wise model.
simulation and sensitivity analysis of transmission line circuits by the characteristics method. in this paper we use the method of characteristics to derive a new simulation model of lossy transmission lines, and we present the sensitivity analysis in the time-domain. the simulation model is as fast as the recursive convolution model based on moment matching and pade' approximation, but does not have the stability problem. the sensitivity analysis model is particularly useful for transmission line circuits containing nonlinear elements, and is believed to be the first time- domain model. both the simulation and sensitivity analysis models are applicable to uniform and nonuniform transmission lines with arbitrary nonzero initial states. also we show that any nonlinear circuit element has a very simple linear model in sensitivity analysis. furthermore, we demonstrate that for any circuits, the modified nodal admittance(mna) matrices in simulation and in sensitivity analysis equations are the same, therefore no lu decomposition is needed in sensitivity analysis. the contributions in this paper have been implemented into a general-purpose program cssc(circuit simulation and sensitivity analysis with characteristics) which shows excellent accuracy and efficiency in both simulation and sensitivity analysis of transmission line circuits.
a force-directed macro-cell placer. in this paper we present a novel force-directed placement algorithm, which is used to solve macro-cell placement problems. a new wire model replaces the traditional clique model and makes possible early awareness of routing congestion. issues such as cell orientation, overlap elimination, and pad positioning are also considered. experiments show satisfactory performance and fast run time.
transformational partitioning for co-design of multiprocessor systems. this paper presents the underlying methodology of cosmos, an interactive approach for hardware/software co-design capable of handling multiprocessor systems and distributed architectures. the approach covers the co-design process through a set of user guided transformations allowing semi-automatic partitioning. the transformations are based on a powerful set of primitives for functional partitioning, structural reorganization and communication transformation. it leads to a fast transformation of a system-level specification into an architecture with a short design time and fast exploration of design space. the application of this approach is illustrated using several design examples starting from a system-level specification given in sdl to a distributed hardware/software architecture described in c/vhdl. we show that the use of transformational approach allows: application of the expertise of the designer during partitioning ; - the user to understand the results of the co-design process ; the process to take into account partial existing solutions ; - large design space exploration ; the designer to start from a very high-level specification language of the system to be designed.
a force-directed maze router. a new routing algorithm is presented. it is based on a multiple star net model, force-directed placement and maze searching techniques. the algorithm inherits the power of maze routing in that it is able to route complex layouts with various obstructions. the large memory requirement of the conventional maze algorithm is alleviated through successive net refinement, which constrains the maze searching to small regions. the algorithm shows advantages in routing designs with complicated layout obstructions.
application-driven processor design exploration for power-performance trade-off analysis. this paper presents an efficient design exploration environment for high-end core processors. the heart of the proposed design exploration framework is a two-level simulation engine that combines detailed simulation for critical portions of the code with fast profiling for the rest. our two-level simulation methodology relies on the inherent clustered structure of application programs and is completely general and applicable to any microarchitectural power/performance simulation engine. the proposed simulation methodology is 3-17x faster, while being sufficiently accurate (within 5%) when compared to the fully detailed simulator. the design exploration environment is able to vary different microarchitectural configurations and find the optimal one as far as energyxdelay product is concerned in a matter of minutes. the parameters that are found to affect drastically the core processor power/performance metrics are issue width, instruction window size, and pipeline depth, along with correlated clock frequency. for very high-end configurations for which balanced pipelining may not be possible, opportunities for running faster stages at lower voltage exist. in such cases, by using up to 3 voltage levels, the energyxdelay product is reduced by 23-30% when compared to the single voltage implementation.
noise analysis of phase-locked loops. this work addresses the problem of noise analysis of phase locked loops (plls). the problem is formulated as a stochastic differential equation and is solved in presence of circuit white noise sources yielding the spectrum of the pll output. specifically, the effect of loop filter characteristics, phase-frequency detector and phase noise of the open loop voltage controlled oscillator (vco) on the pll output spectrum is quantified. these results are derived using a full nonlinear analysis of the vco in the feedback loop and cannot be predicted using traditional linear analyses or the phase noise analysis of open loop oscillators. the computed spectrum matches well with measured results, specifically, the shape of the output spectrum matches very well with measured pll output spectra reported in the literature for different kinds of loop filters and phase detectors. the pll output spectrum computation only requires the phase noise of the vco, loop filter and phase detector noise, phase detector gain and loop filter transfer function and does not require the transient simulation of the entire pll which can be very expensive. the noise analysis technique is illustrated with some examples.
architectural-level synthesis of digital microfluidics-based biochips. microfluidics-based biochips offer a promising platform for massively parallel dna analysis, automated drug discovery, and real-time biomolecular recognition. current techniques for full-custom design of droplet-based "digital" biochips do not scale well for concurrent assays and for next-generation system-on-chip (soc) designs that are expected to include fluidic components. we propose a system design methodology that attempts to apply classical architectural-level synthesis techniques to the design of digital microfluidics-based biochips. we first develop an optimal scheduling strategy based on integer linear programming. since the scheduling problem is np-complete, we also develop two heuristic techniques that scale well for large problem instances. a clinical diagnostic procedure, namely multiplexed in-vitro diagnostics on human physiological fluids, is used to evaluate the proposed method.
switching activity analysis considering spatiotemporal correlations. this work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation. complex spatiotemporal correlations among the circuit inputs and internal nodes are considered by using a lag-one markov chain model. evaluations of the model and a comparative analysis presented for benchmark circuits demonstrates the accuracy and the practicality of the method. the results presented in this paper are useful in power estimation and low power design.
steady-state analysis of voltage and current controlled oscillators. this paper introduces the problem of finding the steady-state and the numerical value of the controlling voltage or current for oscillators where the frequency of oscillation is known beforehand. these situations are very common when the oscillator is part of a phase-locked loop (pll). in plls, the reference frequency as well as the divide ratios are known at the time of design. therefore the desired frequency of the voltage (current) controlled oscillator is known but not the controlling voltage (current). we formulate this problem as the solution of an appropriate nonlinear equation. we present robust and efficient numerical techniques for solving this nonlinear equation both in time and frequency domain. we demonstrate using experimental results that this technique is at par with classical methods of calculating oscillator steady-state and period of oscillation for a given control voltage. we show that compared to a search-based approach to calculating the desired control voltage or current, our direct method is a order of magnitude faster for the same accuracy.
post-route optimization for improved yield using a rubber-band wiring model. this paper presents a unique approach to improve yield given a routed layout. currently after routing has been completed and compacted, it generally proceeds to verification without further modifications. however, to improve manufacturability, we introduce a concept called even wire distribution, a key element of the surf physical design tool. to alleviate congestion, we first move vias and wires torwards less dense areas in a manner which preserves the existing wiring paths. depending on locally available area, we then increase wire spacing to reduce defect sensitivity, without changing the area of the design. carafe, an inductive fault analysis tool is used to evaluate the new layout.
system-level power/performance analysis of portable multimedia systems communicating over wireless channels. this paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. more precisely, we introduce an analytical approach based on concurrent processes modeled as stochastic automata networks (sans) that can be effectively used to integrate power and performance metrics in system-level design. we show that 1) under various input traces and wireless channel conditions, the average-case behavior of a multimedia system consisting of a video encoder/decoder pair is characterized by very different probability distributions and power consumption values and 2) in order to identify the best trade-off between power and performance figures, one must take into consideration the entire environment (i.e., encoder, decoder, and channel) for which the system is being designed. compared to using simulation, our analytical technique reduces the time needed to find the steady-state behavior by orders of magnitude, with some limited loss in accuracy compared to the exact solution. we illustrate the potential of our methodology using the mpeg-2 video as the driver application.
sequential optimisation without state space exploration. we propose an algorithm for area optimization of sequential circuits through redundancy removal. the algorithm finds compatible redundancies by implying values over nets in the circuit. the potentially exponential cost of state space traversal is avoided and the redundancies found can all be removed at once. the optimized circuit is a safe delayed replacement of the original circuit. the algorithm computes a set of compatible sequential redundancies and simplifies the circuit by propagating them through the circuit. we demonstrate the efficacy of the algorithm even for large circuits through experimental results on benchmark circuits.
fault-tolerant techniques for ambient intelligent distributed systems. ambient intelligent systems provide an unexplored hardware platformfor executing distributed applications under strict energy constraints.these systems must respond quickly to changes in userbehavior or environmental conditions and must provide high availabilityand fault-tolerance under given quality constraints. thesesystems will necessitate fault-tolerance to be built into applications.one way to provide such fault-tolerance is to employ the use of redundancy.hundreds of computational devices will be available indeeply networked ambient intelligent systems, providing opportunitiesto exploit node redundancy to increase application lifetime orimprove quality of results if it drops below a threshold. pre-copyingwith remote execution is proposed as a novel, alternative techniqueof code migration to enhance system lifetime for ambient intelligentsystems. self-management of the system is considered in two differentscenarios: applications that tolerate graceful quality degradationand applications with single-point failures. the proposed techniquecan be part of a design methodology for prolonging the lifetime ofa wide range of applications under various types of faults, despitescarce energy resources.
noise analysis of non-autonomous radio frequency circuits. in this paper we consider the important problem of noise analysis of non-autonomous nonlinear rf circuits in presence of input signal phase noise. we formulate this problem as a stochastic differential equation and solve it in the presence of circuit white noise sources. we show that the output noise of a nonlinear non-autonomous circuit, driven by a periodic input signal with phase noise, is stationary and not cyclostationary (as would be predicted by traditional analyses). we also show that effect of input signal phase noise is to act as additional white noise source. this result is derived using a full nonlinear analysis of the problem and cannot be predicted by traditional linear analysis based techniques. input signal phase noise can be an important portion of the overall output noise of the non-autonomous circuit. in our opinion, existing analyses have not considered this effect in a rigorous manner. we also relate this solution to results of the existing nonlinear time domain and frequency domain methods of noise analysis and point out the modifications required for the present techniques. we illustrate our technique using an example.
hybrid structured clock network construction. this paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating from the mesh nodes. we propose a mesh construction procedure, which guarantees zero skew under the elmore delay model, using a simple and efficient linear programming formulation. buffers are inserted to reduce the transition time (or rise time). as a post-processing step, wire width optimization under an accurate higher-order delay metric is performed to further minimize the transition time and propagation delay/skew. experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree.
a realistic variable voltage scheduling model for real-time applications. voltage scheduling is indispensable for exploiting the benefit of variable voltage processors. though extensive research has been done in this area, current processor limitations such as transition overhead and voltage level discretization are often considered insignificant and are typically ignored. we show that for hard, real-time applications, disregarding such details can lead to sub-optimal or even invalid results. we propose two algorithms that guarantee valid solutions. the first is a greedy yet simple approach, while the second is more complex but significantly reduces energy consumption under certain conditions. through experimental results on both real and randomly generated systems, we show the effectiveness of both algorithms, and explore what conditions make it beneficial to use the complex algorithm over the basic one.
combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. dynamic voltage scaling (dvs) reduces the power consumption of processors when peak performance is unnecessary. however, the achievable power savings by dvs alone is becoming limited as leakage power increases. in this paper, we show how the simultaneous use of adaptive body biasing (abb) and dvs can be used to reduce power in high-performance processors. analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with spice simulation. we then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. the usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. the results demonstrate that application of simultaneous dvs and abb results in an average energy reduction of 48% over dvs alone.
the circuit design of the synergistic processor element of a cell processor. a 32b 4-way simd dual-issue synergistic processor element of a cell processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm soi technology. cmos static gates implement the majority of the logic. dynamic circuits are used in critical areas, occupying 19% of the nonsram area. isa, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. correct operation has been observed up to 5.6ghz at 1.4v supply and 56/spl deg/c.
detection of multiple transitions in delay fault test of sparc64 microprocessor. this work presents a new non-robust delay fault test generation method for the purpose of screening delay defects of microprocessors with fewer test vectors. it is important to reduce the number of test vectors in order to reduce test time, memory usage in the tester, and the overall testing cost. by paying attention to the constraints of off-path inputs in a non-robust test, we made it possible to generate a pair of test vectors to detect multiple delay faults based on the traditional dynamic compaction technique. delay fault test based on our method is applied to sparc64 microprocessor with 1.3 ghz clock for screening delay defects, and we achieved 90% coverage with 3,567 test vectors. the comparison results also show that the robust test is not practical for the screening purpose, since it needs more than three times the number of test vectors as compared to the non-robust test.