waashk/dblp huggingface dataset:
memories: a programmable, real-time hardware emulation tool for multiprocessor server design. modern system design often requires multiple levels of simulation for design validation and performance debugging. however, while machines have gotten faster, and simulators have become more detailed, simulation speeds have not tracked machine speeds. as a result, it is difficult to simulate realistic problem sizes and hardware configurations for a target machine. instead, researchers have focussed on developing scaling methodologies and running smaller problem sizes and configurations that attempt to represent the behavior of the real problem. given the increasing size of problems today, it is unclear whether such an approach yields accurate results. moreover, although commercial workloads are prevalent and important in today's marketplace, many simulation tools are unable to adequately profile such applications, let alone for realistic sizes.in this paper we present a hardware-based emulation tool that can be used to aid memory system designers. our focus is on the memory system because the ever-widening gap between processor and memory speeds means that optimizing the memory subsystem is critical for performance. we present the design of the memory instrumentation and emulation system (memories). memories is a programmable tool designed using fpgas and sdrams. it plugs into an smp bus to perform on-line emulation of several cache configurations, structures and protocols while the system is running real-life workloads in real-time, without any slowdown in application execution speed. we demonstrate its usefulness in several case studies, and find several important results. first, using traces to perform system evaluation can lead to incorrect results (off by 100% or more in some cases) if the trace size is not sufficiently large. second, memories is able to detect performance problems by profiling miss behavior over the entire course of a run, rather than relying on a small interval of time. finally, we observe that previous studies of splash2 applications using scaled application sizes can result in optimistic miss rates relative to real sizes on real machines, providing potentially misleading data when used for design evaluation.
operating system support for improving data locality on cc-numa compute servers. the dominant architecture for the next generation of shared-memory multiprocessors is cc-numa (cache-coherent non-uniform memory architecture). these machines are attractive as compute servers because they provide transparent access to local and remote memory. however, the access latency to remote memory is 3 to 5 times the latency to local memory. cc-now machines provide the benefits of cache coherence to networks of workstations, at the cost of even higher remote access latency. given the large remote access latencies of these architectures, data locality is potentially the most important performance issue. using realistic workloads, we study the performance improvements provided by os supported dynamic page migration and replication. analyzing our kernel-based implementation, we provide a detailed breakdown of the costs. we show that sampling of cache misses can be used to reduce cost without compromising performance, and that tlb misses may not be a consistent approximation for cache misses. finally, our experiments show that dynamic page migration and replication can substantially increase application performance, as much as 30%, and reduce contention for resources in the numa memory system.
bytecode fetch optimization for a java interpreter. interpreters play an important role in many languages, and their performance is critical particularly for the popular language java. the performance of the interpreter is important even for high-performance virtual machines that employ just-in-time compiler technology, because there are advantages in delaying the start of compilation and in reducing the number of the target methods to be compiled. many techniques have been proposed to improve the performance of various interpreters, but none of them has fully addressed the issues of minimizing redundant memory accesses and the overhead of indirect branches inherent to interpreters running on superscalar processors. these issues are especially serious for java because each bytecode is typically one or a few bytes long and the execution routine for each bytecode is also short due to the low-level, stack-based semantics of java bytecode. in this paper, we describe three novel techniques of our java bytecode interpreter, write-through top-of-stack caching (wt), position-based handler customization (phc), and position-based speculative decoding (psd), which ameliorate these problems for the powerpc processors. we show how each technique contributes to improving the overall performance of the interpreter for major java benchmark programs on an ibm power3 processor. among three, phc is the most effective one. we also show that the main source of memory accesses is due to bytecode fetches and that phc successfully eliminates the majority of them, while it keeps the instruction cache miss ratios small.
joint local and global hardware adaptations for energy. this work concerns algorithms to control energy-driven architecture adaptations for multimedia applications, without and with dynamic voltage scaling (dvs). we identify a broad design space for adaptation control algorithms based on two attributes: (1) when to adapt or temporal granularity and (2) what structures to adapt or spatial granularity. for each attribute, adaptation may be global or local. our previous work developed a temporally and spatially global algorithm. it invokes adaptation at the granularity of a full frame of a multimedia application (temporally global) and considers the entire hardware configuration at a time (spatially global). it exploits inter-frame execution time variability, slowing computation just enough to eliminate idle time before the real-time deadline.this paper explores temporally and spatially local algorithms and their integration with the previous global algorithm. the local algorithms invoke architectural adaptation within an application frame to exploit intra-frame execution variability, and attempt to save energy without affecting execution time. we consider local algorithms previously studied for non-real-time applications as well as propose new algorithms. we find that, for systems without and with dvs, the local algorithms are effective in saving energy for multimedia applications, but the new integrated global and local algorithm is best for the systems and applications studied.
the case for a single-chip multiprocessor. advances in ic processing allow for more microprocessor design options. the increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. this paper shows that in advanced technologies it is possible to implement a single-chip multiprocessor in the same area as a wide issue superscalar processor. we find that for applications with little parallelism the performance of the two microarchitectures is comparable. for applications with large amounts of parallelism at both the fine and coarse grained levels, the multiprocessor microarchitecture outperforms the superscalar architecture by a significant margin. single-chip multiprocessor architectures have the advantage in that they offer localized implementation of a high-clock rate processor for inherently sequential applications and low latency interprocessor communication for parallel applications.
performance isolation: sharing and isolation in shared-memory multiprocessors. shared-memory multiprocessors (smps) are being extensively used as general-purpose servers. the tight coupling of multiple processors, memory, and i/o provides enormous computing power in a single system, and enables the efficient sharing of these resources.the operating systems for these machines (unix or windows nt) provide very few controls for sharing the resources of the system among the active tasks or users. this unconstrained sharing model is a serious limitation for a server because the load placed by one user can adversely affect other users' performance in an unpredictable manner. we show that this lack of isolation is caused by the resource allocation scheme (or lack thereof) carried over from singleuser workstations. multi-user multiprocessor systems require more sophisticated resource management, and we show how the proposed "performance isolation" scheme can address the current weaknesses of these systems. we have implemented performance isolation in the silicon graphics irix operating system for three important system resources: cpu time, memory, and disk bandwidth. running a number of workloads we show that our proposed scheme is successful at providing workstation-like isolation under heavy load, smp-like latency under light load, and smp-like throughput in all cases.
enhancing software reliability with speculative threads. this paper advocates the use of a monitor-and-recover programming paradigm to enhance the reliability of software, and proposes an architectural design that allows software and hardware to cooperate in making this paradigm more efficient and easier to program.we propose that programmers write monitoring functions assuming simple sequential execution semantics. our architecture speeds up the computation by executing the monitoring functions speculatively in parallel with the main computation. for recovery, programmers can define fine-grain transactions whose side effects, including all register modifications and memory writes, can either be committed or aborted under program control. transactions are implemented efficiently by treating them as speculative threads.our experimental results suggest that monitored execution is more amenable to parallelization than regular program execution. code monitoring is sped up by a factor of 1.5 by exploiting single-thread instruction-level parallelism, and by an additional factor of 1.6 using thread-level speculation. this results in an overall improvement of 2.5 times and a sustained 5.4 instructions-per-cycle performance. a monitored execution that used to be 2.5 times slower executes with a degradation of only 12% when compared to the performance on the baseline machine. we also show that the concept of fine-grain transactional programming is useful in catching buffer overrun errors through a number of real-life examples.
evaluating the performance of software cache coherence. in a shared-memory multiprocessor with private caches, cached copies of a data item must be kept consistent. this is called cache coherence. both hardware and software coherence schemes have been proposed. software techniques are attractive because they avoid hardware complexity and can be used with any processor-memory interconnection. this paper presents an analytical model of the performance of two software coherence schemes and, for comparison, snoopy-cache hardware. the model is validated against address traces from a bus-based multiprocessor. the behavior of the coherence schemes under various workloads is compared, and their sensitivity to variations in workload parameters is assessed. the analysis shows that the performance of software schemes is critically determined by certain parameters of the workload: the proportion of data accesses, the fraction of shared references, and the number of times a shared block is accessed before it is purged from the cache. snoopy caches are more resilient to variations in these parameters. thus when evaluating a software scheme as a design alternative, it is essential to consider the characteristics of the expected workload. the performance of the two software schemes with a multistage interconnection network is also evaluated, and it is determined that both scale well.
locality-aware request distribution in cluster-based network servers. we consider cluster-based network servers in which a front-end directs incoming requests to one of a number of back-ends. specifically, we consider content-based request distribution: the front-end uses the content requested, in addition to information about the load on the back-end nodes, to choose which back-end will handle this request. content-based request distribution can improve locality in the back-ends' main memory caches, increase secondary storage scalability by partitioning the server's database, and provide the ability to employ back-end nodes that are specialized for certain types of requests.as a specific policy for content-based request distribution, we introduce a simple, practical strategy for locality-aware request distribution (lard). with lard, the front-end distributes incoming requests in a manner that achieves high locality in the back-ends' main memory caches as well as load balancing. locality is increased by dynamically subdividing the server's working set over the back-ends. trace-based simulation results and measurements on a prototype implementation demonstrate substantial performance improvements over state-of-the-art approaches that use only load information to distribute requests. on workloads with working sets that do not fit in a single server node's main memory cache, the achieved throughput exceeds that of the state-of-the-art approach by a factor of two to four.with content-based distribution, incoming requests must be handed off to a back-end in a manner transparent to the client, after the front-end has inspected the content of the request. to this end, we introduce an efficient tcp handoflprotocol that can hand off an established tcp connection in a client-transparent manner.
the mahler experience: using and intermediate language as the machine description. division of a compiler into a front end and a back end that communicate via an intermediate language is a well-known technique. we go farther and use the intermediate language as the official description of a family of machines with simple instruction sets and addressing capabilities, hiding some of the inconvenient details of the real machine from the users and the front end compilers.to do this credibly, we have had to hide not only the existence of the details but also the performance consequences of hiding them. the back end that compiles and links the intermediate language tries to produce code that does not suffer a performance penalty because of the details that were hidden from the front end compiler. to accomplish this, we have used a number of link-time optimizations, including instruction scheduling and interprocedural register allocation, to hide the existence of such idiosyncracies as delayed branches and non-infinite register sets. for the most part we have been sucessful.
an evaluation of memory consistency models for shared-memory systems with ilp processors. relaxed consistency models have been shown to significantly outperform sequential consistency for single-issue, statically scheduled processors with blocking reads. however, current microprocessors aggressively exploit instruction-level parallelism (ilp) using methods such as multiple issue, dynamic scheduling, and non-blocking reads. researchers have conjectured that two techniques, hardware-controlled non-binding prefetching and speculative loads, have the potential to equalize the hardware performance of memory consistency models on such processors.this paper performs the first detailed quantitative comparison of several implementations of sequential consistency and release consistency optimized for aggressive ilp processors. our results indicate that hardware prefetching and speculative loads dramatically improve the performance of sequential consistency. however, the gap between sequential consistency and release consistency depends on the cache write policy and the complexity of the cache-coherence protocol implementation. in most cases, release consistency significantly outperforms sequential consistency, but for two applications, the use of a write-back primary cache and a more complex cache-coherence protocol nearly equalizes the performance of the two models.we also observe that the existing techniques, which require on-chip hardware modifications, enhance the performance of release consistency only to a small extent. we propose two new software techniques --- fuzzy acquires and selective acquires --- to achieve more overlap than allowed by the previous implementations of release consistency. to enhance methods for overlapping acquires, we also propose a technique to eliminate control dependences caused by an acquire loop, using a small amount of off-chip hardware called the synchronization buffer.
helper threads via virtual multithreading on an experimental itanium 2 processor-based platform. helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run ``assist'' threads. previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. in order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (vmt), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. the compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. the vmt approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.the concept of vmt is prototyped on an itanium ® 2 processor using features provided by the processor abstraction layer (pal) firmware mechanism already present in currently shipping processors. on a 4-way mp physical system equipped with vmt-enabled itanium 2 processors, helper threading via the vmt mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (dss) using the ibm db2 universal database. we measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the dss workload.
analysis of cache invalidation patterns in multiprocessors. to make shared-memory multiprocessors scalable, researchers are now exploring cache coherence protocols that do not rely on broadcast, but instead send invalidation messages to individual caches that contain stale data. the feasibility of such directory-based protocols is highly sensitive to the cache invalidation patterns that parallel programs exhibit. in this paper, we analyze the cache invalidation patterns caused by several parallel applications and investigate the effect of these patterns on a directory-based protocol. our results are based on multiprocessor traces with 4, 8 and 16 processors. to gain insight into what the invalidation patterns would look like beyond 16 processors, we propose a classification scheme for data objects found in parallel applications and link the invalidation traffic patterns observed in the traces back to these high-level objects. our results show that synchronization objects have very different invalidation patterns from those of other data objects. a write reference to a synchronization object usually causes invalidations in many more caches. we point out situations where restructuring the application seems appropriate to reduce the invalidation traffic, and others where hardware support is more appropriate. our results also show that it should be possible to scale &ldquo;well-written&rdquo; parallel programs to a large number of processors without an explosion in invalidation traffic.
improving cache performance with balanced tag and data paths. there are two concurrent paths in a typical cache access --- one through the data array and the other through the tag array. the path through the data array drives the selected set out of the array. the path through the tag array determines cache hit/miss and, for set-associative caches, selects the appropriate line from within the selected set. in both direct-mapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. in this paper, we propose a path balancing technique help match the delays of the tag and data paths. the basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a design that provides higher performance. performance evaluation using both tpc-c and spec92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache designs. for tpc-c, improvements in the range of 6% to 28% are possible.
a study of scalar compilation techniques for pipelined supercomputers. this paper studies two compilation techniques for enhancing scalar performance in high-speed scientific processors: software pipelining and loop unrolling. we study the impact of the architecture (size of the register file) and of the hardware (size of instruction buffer) on the efficiency of loop unrolling. we also develop a methodology for classifying software pipelining techniques. for loop unrolling, a straightforward scheduling algorithm is shown to produce near-optimal results when not inhibited by recurrences or memory hazards. our study indicates that the performance produced with a modified cray-1s scalar architecture and a code scheduler utilizing loop unrolling is comparable to the performance achieved by the cray-1s with a vector unit and the cft vectorizing compiler. finally, we show that the combination of loop unrolling and dynamic software pipelining, as implemented by a decoupled computer, substantially outperforms the vector cray-1s.
capturing dynamic memory reference behavior with adaptive cache topology. memory references exhibit locality and are therefore not uniformly distributed across the sets of a cache. this skew reduces the effectiveness of a cache because it results in the caching of a considerable number of less-recently-used lines which are less likely to be re-referenced before they are replaced. in this paper, we describe a technique that dynamically identifies these less-recently-used lines and effectively utilizes the cache frames they occupy to more accurately approximate the global least-recently-used replacement policy while maintaining the fast access time of a direct-mapped cache. we also explore the idea of using these underutilized cache frames to reduce cache misses through data prefetching. in the proposed design, the possible locations that a line can reside in is not predetermined. instead, the cache is dynamically partitioned into groups of cache lines. because both the total number of groups and the individual group associativity adapt to the dynamic reference pattern, we call this design the adaptive group-associative cache. performance evaluation using trace-driven simulations of the tpc-c benchmark and selected programs from the spec95 benchmark suite shows that the group-associative cache is able to achieve a hit ratio that is consistently better than that of a 4-way set-associative cache. for some of the workloads, the hit ratio approaches that of a fully-associative cache.