waashk/dblp huggingface dataset:
performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression. process variations in modern vlsi technologies are growing in both magnitude and dimensionality. to assess performance variability, complex simulation and performance models parameterized in a high-dimensional process variation space are desired. however, the high parameter dimensionality, imposed by a large number of variation sources encountered in modern technologies, can introduce significant complexion in circuit analysis and may even render performance variability analysis completely intractable. we address the challenge brought by high-dimensional process variations via a new performance-oriented parameter dimension reduction technique. the basic premise behind our approach is that the dimensionality of performance variability is determined not only by the statistical characteristics of the underlying process variables, but also by the structural information imposed by a given design. using the powerful reduced rank regression (rrr) and its extension as a vehicle for variability modeling, we are able to systematically identify statistically significant reduced parameter sets and compute not only reduced-parameter but also reduced-parameter-order models that are far more efficient than what was possible before. for a variety of interconnect modeling problems, it is shown that the proposed parameter reduction technique can provide more than one order of magnitude reduction in parameter dimensionality. such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized interconnect reduced order models. as a general parameter dimension reduction methodology, it is anticipated that the proposed technique is broadly applicable to a variety of statistical circuit modeling problems, thereby offering a useful framework for controlling the complexity of statistical circuit analysis.
design and cad challenges in 45nm cmos and beyond. with semiconductor industry's aggressive march towards 45nm cmos technology and introduction of new materials and device structures in sight for 32nm and 22nm nodes, it is crucial for the ic design and cad community to understand the challenges posed by these potential technology changes. this tutorial will focus on these challenges starting from front end of line (devices) to the back end of line (interconnects) and finally the impact on cad. we will discuss the impact of various device technology options/improvements, such as high-k, metal gate, low temperature operation, increased mobility and reduced variability, on the overall chip performance in the context of power-constrained technology optimization. this will show that power constraints limit, but do not eliminate, the performance improvements available from new technology. the integration issues related to low-k materials for interconnects in 45nm and beyond will be examined in the context of advanced ic design. ultra low-k materials, evolution of etch and chemical mechanical polishing (cmp), and techniques to limit damage during processing and their impact on design performance will be discussed in detail. these advanced device and interconnect structures and materials including 3d technology have tremendous impact on the direction of the cad industry. we will discuss the design methodology and cad implications of these imminent technology changes.
precise identification of the worst-case voltage drop conditions in power grid verification. identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern ic design. in this paper we develop a novel methodology for power grid verification which is based on accurately constructing the space of current variations of the supplied modules and locating its precise points that yield the worst-case voltage drop conditions. the construction of the current space is performed via plain simulation and statistical extrapolation using results from extreme value theory. the method overcomes limitations of past methods which either relied on loosely bounding the worst-case voltage drop, or abstracted the current space in a vague and incomplete set of bound-type constraints. experimental results verify the potential of the proposed method to identify worst-case conditions and demonstrate the pessimism inherent in previous bound-type approaches.
a high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. this work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. the proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case delay as in previous works. we also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. the accuracy of the model has been assessed by means of extensive experiments. moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput.
importance of volume discretization of single and coupled interconnects. this paper presents figures of merit and error formulae to determine which interconnects require volume discretization in the ghz range. most of the previous work focused mainly on efficient modeling of volume discretized interconnects using several integration and reduction techniques. however, little work has been done to characterize when using the simple dc model has an impact on critical circuit metrics such as delay, impedance ...etc. most of the previous work simply assumes that when skin depth becomes smaller than the wire cross section dimensions, volume discretization becomes essential. however, careful analysis in this paper shows that this assumption is invalid and a figure of merit is derived to characterize when volume discretization of single and coupled wires is required. this derived figure of merit is shown to depend solely on the interconnect dimensions and spacing and is independent of the type of the materials used or technology scaling.
near-term industrial perspective of analog cad. analog and mixed-signal cad looks like a nice success story: there's been significant research in building design automation tools since the late 80's, and commercial tools have been on the market for several years now. however, the majority of ams (analog/mixed-signal) designers still use manual design only, focused around the spice simulator. so why are designers not or slowly adopting these cad tools? this paper will present a reality check on the current state of the art of ams design tools for industrial usage.
fast wire length estimation by net bundling for block placement. the wire length estimation is the bottleneck of packing based block placers. to cope with this problem, we present a fast wire length estimation method in this paper. the key idea is to bundle the 2-pin nets between block pairs, and measure the wire length bundle by bundle, instead of net by net. previous bundling method [5] introduces a huge error which compromises the performance. we present an errorfree bundling approach which utilizes the piecewise linear wire length function of a pair of blocks. with the function implemented into a lookup table, the wire length can be computed promptly and precisely by binary search. furthermore, we show that 3-pin nets can also be bundled, resulting in a further speedup. the effectiveness of our method is verified by experiments.
tp-ppv: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate pll simulation. we present a novel method for generating small, accurate pll macromodels that capture transient response and jitter performance with unprecedented accuracy, while offering large speedups. the method extracts and uses a highly accurate oscillator phase macromodel termed the tp-ppv macromodel. the core idea behind the novel extraction procedure is to combine concepts from strongly nonlinear trajectory piecewise macromodeling techniques together with ppv-based timeshifted nonlinear phase macromodels. as a result, tp-ppv generated macromodels offer excellent global as well as local fidelity. these properties are necessary for handing large excursions in pll control voltages during capture/lock in, e.g., hopping frequency synthesizers. we validate tp-ppv on a 5-stage interpolative ring vco based pll and compare results against full simulation, as well as against prior macromodels. we show that, unlike prior macromodels that only work well when the control voltage of the vco has small excursions, the tp-ppv macromodel provides near-perfect matches against full spicelevel simulation over a wide range of design scenarios, while achieving speedups of about three orders of magnitude.
efficient process-hotspot detection using range pattern matching. in current manufacturing processes, certain layout configurations are likely to have reduced yield and/or reliability due to increased susceptibility to stress effects or poor tolerance to certain processes like lithography. these problematic layout configurations need to be efficiently detected and eliminated from a design layout to enable better yield. in this paper, such layout configurations are called processhotspots and an efficient and scalable algorithm is proposed to detect such process-hotspots in a given layout. the concept of a range pattern is introduced and used to accurately and compactly represent these process-hotspots. this representation is flexible and can incorporate information about the deficiencies of available modeling and/or subsequent correction (for instance, mask synthesis) techniques. each range pattern can also be associated with a scoring mechanism to score the problem regions according to yield impact. a library of range patterns is being developed in collaboration with a fab. the proposed process-hotspot detection system assumes that process-hotspots are specified as a library of range patterns and determines all occurrences of any of these range patterns in a layout. it is fast and accurate and can be applied to large industrial layouts. unlike previous work, the proposed scheme can identify problems that cannot be efficiently modeled or corrected by subsequent mask synthesis techniques and can thereby complement existing work in that area. experimental results are quite promising and show that all locations that match a range pattern in a given layout can be found in a matter of minutes.
wire density driven global routing for cmp variation and timing. in this paper, we propose the first wire density driven global routing that considers cmp variation and timing. to enable cmp awareness during global routing, we propose a compact predictive cmp model with dummy fill, and validate it with extensive industry data. while wire density has some correlation and similarity to the conventional congestion metric, they are indeed different in the global routing context. therefore, wire density rather than congestion should be a unified metric to improve both cmp variation and timing. the proposed wire density driven global routing is implemented in a congestion-driven global router [5] for cmp and timing optimization. the new global router utilizes several novel techniques to reduce the wire density of cmp and timing hotspots. our experimental results are very encouraging. the proposed algorithm improves cmp variation and timing by over 7% with negligible overhead in wirelength and even slightly better routability, compared to the pure congestion-driven global router [5].
dynamic voltage and frequency management based on variable update intervals for frequency setting. an efficient adaptive method to perform dynamic voltage and frequency management (dvfm) for minimizing the energy consumption of microprocessor chips is presented. instead of using a fixed update interval, the proposed dvfm system makes use of adaptive update intervals for optimal frequency and voltage scheduling. the optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. the method, which is based on introducing the concept of an effective deadline, utilizes the correlation between consecutive values of the workload. in practice because the frequency and voltage update rates are dynamically set based on variable update interval lengths, voltage fluctuations on the power network are also minimized. the technique, which may be implemented by simple hardware and is completely transparent from the application, leads to power savings of up to 60% for highly correlated workloads compared to dvfm systems based on fixed update intervals.
platform-based resource binding using a distributed register-file microarchitecture. behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. this paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (drfm) that makes efficient use of distributed embedded memory blocks as register files in modern fpgas. a drfm contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. compared with the traditional discrete-register counterpart, a drfm allows use of the platform-featured on-chip memory or register-file ip blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. drfm provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. based on drfm, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. by applying our approach, significant reductions on multiplexors and global-interconnections are observed. on the xilinx virtex ii fpga platform, our experimental results show a 2x logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.
fill for shallow trench isolation cmp. shallow trench isolation (sti) is the mainstream cmos isolation technology. it uses chemical mechanical polishing (cmp) to remove excess of deposited oxide and attain a planar surface for successive process steps. despite advances in sti cmp technology, pattern dependencies cause large post-cmp topography variation that can result in functional and parametric yield loss. fill insertion is used to reduce pattern variation and consequently decrease post-cmp topography variation. traditional fill insertion is rulebased and is used with reverse etchback to attain desired planarization quality. due to extra costs associated with reverse etchback, "single-step" sti cmp in which fill insertion suffices is desirable. to alleviate the failures caused by imperfect cmp, we focus on two objectives for fill insertion: oxide density variation minimization and nitride density maximization. a linear programming based optimization is used to calculate oxide densities that minimize oxide density variation. next a fill insertion methodology is presented that attains the calculated oxide density while maximizing the nitride density. averaged over the two large testcases, the oxide density variation is reduced by 63% and minimum nitride density increased by 79% compared to tiling-based fill insertion. to assess post-cmp planarization, we run cmp simulation on the layout filled with our approach and find the planarization window (time window in which polishing can be stopped) to increase by 17% and maximum final step height (maximum difference in post-cmp oxide thickness) to decrease by 9%.
information processing in nanoscale arrays: dna assembly, molecular devices, nano-array architectures. arrays of simple, nanoscale components are promising for future information processing circuitry. large arrays could provide high functionality by exploiting the nonlinear dynamics of locally connected components, while circumventing nanoscale power dissipation and interconnect limits. to realize such a paradigm shift, however, many new physical design and system-level issues must be addressed. here, i will describe 1) results on dna-directed assembly of components in 2d arrays, 2) the search for electrically active molecular components and 3) schemes for information processing in arrays of simple nanoscale components.
stable and compact inductance modeling of 3-d interconnect structures. recent successful techniques for the efficient simulation of largescale interconnect models rely on the sparsification of the inverse of the inductance matrix l. while there are several techniques for sparsifying l-1, the stability of these approximations for general interconnect structures has not been established, i.e., the sparsified reluctance and inductance matrices are not guaranteed to be positive-definite. in this paper, we present a novel technique for reluctance sparsification for general interconnect structures that enjoys several advantages: first, the resulting sparse approximation is guaranteed to be positive definite. second, the approximation is optimal, in a certain well-defined sense. third, owing to its computational efficiency and numerical stability, the algorithm is applicable for very large problem sizes. finally our approach yields a compact representation of both inductance and reluctance matrices for general cases.
factor cuts. enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. the standard algorithm does not scale beyond 6 or 7 inputs because it enumerates all cuts and there are too many of them. we address the enumeration problem by introducing the notion of cut factorization. in cut factorization, one enumerates global and local cuts (collectively called the factor cuts) of the network, and uses these to generate other cuts. depending on how global and local cuts are defined, one obtains different factorization schemes. in the first scheme, complete factorization, it is possible to generate any cut from factor cuts. however, complete factorization is expensive though less expensive than exhaustive enumeration. in the second scheme, partial factorization, there is no guarantee of generating all cuts from factor cuts. however, it is much faster, and produces good results. in this paper we also present two applications of factor cuts: lut mapping and macrocell mapping. in lut mapping, we find that considering only factor cuts guarantees depth optimality for most nodes in the network. for the remaining nodes, other cuts need to be generated from factor cuts and examined. in macrocell mapping, we focus on a particular 9-input macrocell, and use factor cuts as a heuristic method to improve depth by reducing structural bias. factor cuts are used to map the macrocell as a whole whenever possible instead of mapping its parts separately. in this context factor cuts enable a new quality-run-time tradeoff between mapping parts of the macrocell separately (poor quality), and mapping using all 9-input cuts (long run-time).
system-level process-driven variability analysis for single and multiple voltage-frequency island systems. the problem of determining bounds for application completion times running on generic systems comprised of single or multiple voltage-frequency islands (vfis) with arbitrary topologies is addressed in the context of manufacturing-driven variability. the approach provides an exact solution for the system-level timing yield in single clock, single voltage (ssv) and vfi systems with an underlying tree-based topology, and a tight upper bound for generic, non-tree based topologies. the results show that: (a) timing yield for overall source-to- sink completion time for generic systems can be modeled in an exact manner for both ssv and vfi systems; and (b) multiple vfi, latency-constrained systems can achieve 11--90% higher timing yield than their ssv counterparts. the results are proven formally and supported by experimental results on two embedded applications, namely software defined radio and mpeg2 encoder.
current path analysis for electrostatic discharge protection. the electrostatic discharge (esd) problem has become a challenging reliability issue in nanometer circuit design. high voltages resulted from esd might cause high current densities in a small device and burn it out, so on-chip protection circuits for ic pads are required. to reduce the design cost, the protection circuit should be added only for the ic pads with an esd current path, which arises the esd current path analysis problem. in this paper, we first introduce the analysis problem for esd protection in circuit design. we then model the circuit as a constrained graph, decompose esd connected components linked with the pads, and apply the breadth-first search (bfs) to identify the esd connected components in each constrained graph and thus the current paths. experimental results show that our algorithm can detect all esd paths very efficiently and economically. to our best knowledge, our algorithm is the first point tool available to the public for the esd analysis.
soft error reduction in combinational logic using gate resizing and flipflop selection. soft errors in logic are emerging as a significant reliability problem for vlsi designs. this paper presents novel circuit optimization techniques to mitigate soft error rates (ser) of combinational logic circuits. first, we propose a gate sizing algorithm that trades off ser reduction and area overhead. this approach first computes bounds on the maximum achievable ser reduction by resizing a gate. this bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit ser. second, we propose a flipflop selection method that uses slack information at each primary output node to determine the flipflop configuration that produces maximum ser savings. this approach uses an enhanced flipflop library that contains flipflops of varying temporal masking ability. third, we propose a unified, cooptimization approach combining flipflop selection with the gate sizing algorithm. the joint optimization algorithm produces larger ser reductions while incurring smaller circuit overhead than either technique taken in isolation. experimental results on a variety of benchmarks show ser reductions of 7.9x with gate sizing, 6.6x with flipflop assignment, and 28.2x for the combined optimization approach, with no delay penalties and area overheads within 5--6%. the runtimes for the optimization algorithms are on the order of 1--3 minutes.
design optimization for single-event upset robustness using simultaneous dual-vdd and sizing techniques. an optimization algorithm for the design of combinational circuits that are robust to single-event upsets (seus) is described. a simple, highly accurate model for the seu robustness of a logic gate is developed. this model -- in posynomial form -- is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. simulation results for design optimization using simultaneous dual- vdd and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach.