waashk/dblp huggingface dataset:
model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems. previous model order reduction methods fit into the framework of identifying the low-order linear subspace and using the linear projection to project the full state space into the low-order subspace. despite its simplicity, the macromodel might automatically include redundancies. in this paper, we present a model order reduction approach, named manimor, which extends the linear projection framework to a general nonlinear projection framework. the two key ideas of manimor are (1) it explicitly separates the construction of the low-order subspace and projection operation; (2) it constructs a nonlinear manifold which captures important system responses and defines the corresponding nonlinear projection operator. the low-order manifold subspace in manimor is identified by stitching together the low-order linear subspaces around a set of sample points on the manifold. after the manifold is determined, it is embedded into a global nonlinear coordinate system. the projection function is defined in a piece-wise linear manner, and the model evaluation is conducted directly in the manifold subspace using cheap matrix-vector product computations. as a result, a compact model is generated by precomputing all the functions and jacobians and storing them in a look-up table. we apply manimor on two analog circuits and a bio-chemical system to validate its correctness. extensive comparisons with the results of the full model and other macromodels are provided. experimental results show that manimor manages to obtain a huge reduction -- e.g., from 52 to 5 for the i/o buffer circuit and from 304 to 30 for yeast pheromone pathway system. this is less than half of the size of the tpwl model with the same accuracy. with great promise to capture important system responses, manimor presents a novel and powerful paradigm for nonlinear model reduction, and casts inspirations for further researches.
nthu-route 2.0: a fast and stable global router. we present in this paper a fast and stable global router called nthu-route 2.0 that improves the solution quality and runtime of a state-of-the-art router, nthu-route, by the following enhancements: (1) a new history based cost function, (2) new ordering methods for congested region identification and rip-up and reroute, and (3) two implementation techniques. the experimental results show that nthu-router 2.0 solves all ispd98 benchmarks with very good quality. moreover, it routes 7 of 8 ispd07 benchmarks without any overflow. in particular, for one of the ispd07 benchmarks which are thought to be difficult cases previously, nthu-route 2.0 can completely eliminate its total overflow. nthu-route 2.0 also successfully solves 12 of 16 ispd08 benchmarks without causing any overflow.
electrically driven optical proximity correction based on linear programming. conventional optical proximity correction (opc) tools aim to minimize edge placement errors (epe) due to the optical and resist process by moving mask edges. however, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve. in addition, prohibitively high mask complexity is incurred, leading to high mask cost. given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. in fact, we show that contours with non-minimal epe may result in closer match to the desired electrical performance. towards achieving this objective, we developed a new electrically driven opc (ed-opc) algorithm. the tool combines lithography simulation with accurate electrical modeling of resist contours to predict the on/off current through a transistor gate. the computation of mask edge movements is cast as a linear program based on optical and electrical sensitivities. the objective is to minimize the error in saturation current between printed and target shapes. this optimization is then solved with fast runtime. the results on industrial 45nm soi layouts using high-na immersion lithography models show up to a 5% improvement in accuracy of timing over conventional opc. this is achieved at less than 26% runtime overheads, while also lowering mask complexity by up to 43%. the results confirm that better timing accuracy can be achieved despite larger edge placement error.
guiding global placement with wire density. this paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. the proposed method identifies congested regions of the chip and incorporates the model of the routed wirelength into the objective function in order to effectively alleviate these regions from congestion. the method is integrated in the analytical placement framework and the two-level structure improves the scalability of the placer and speeds up the algorithm. the proposed analytical placer provides the best-so-far average routed wirelength in the ibm version2 benchmark suite.
a voltage-frequency island aware energy optimization framework for networks-on-chip. in this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient vfi (voltage-frequency island) based network-on-chip. unlike the recent work [10] which only performs partitioning together with voltage-frequency assignment for a given mesh network layout, our framework consists of three key vfi-aware components, i.e., vfi-aware partitioning, vfi-aware mapping, and vfi-aware routing. thus our technique effectively reduces vfi overheads such as mixed clock fifos and voltage level converters by over 82% and energy consumption by over 9% compared with the previous state-of-art works [10].
on the modeling of resistance in graphene nanoribbon (gnr) for future interconnect applications. in this paper, we present a comprehensive model for the resistance in graphene nanoribbon (gnr) interconnects. we use the recent experimental and theoretical results to model the impact of stacking of graphene layers in multi-layer gnr interconnects. we compare the resistance of gnr interconnects with both single-walled carbon nanotube (swcnt) bundle interconnects and conventional copper interconnects. our simulation results demonstrate the performance superiority of multi-layer gnr interconnects over conventional copper interconnects at small widths (< 15 nm). consequently, multi-layer gnr interconnects demonstrate a great potential to replace conventioanl copper interconnects in future technologies.
synthesis from multi-cycle atomic actions as a solution to the timing closure problem. one solution to the timing closure problem is to perform infrequent operations in more than one cycle. despite simplicity of the solution statement, it is not easily considered because it requires changes in rtl, which, in turn, exacerbates the verification problem. we offer a timing closure solution guaranteed to preserve functional correctness of designs expressed using atomic actions or rules. we exploit the fact that the semantics of atomic actions are untimed, that is, the time to execute an action is not specified. the current hardware synthesis technique from atomic actions assumes that each rule takes one clock cycle to complete its computation. consequently, the rule with the longest combinational path determines the clock cycle of the entire design, often leading to needlessly slow circuits. we present a synthesis procedure for a system where the combinational circuits embodied in a rule can take multiple cycles without changing the semantics of the original design. we also present preliminary results based on an experimental compiler which uses the bluespec (bsv) compiler front end and generates verilog. the results show that the clock speed and the performance of circuits can be improved substantially by allowing slow paths to complete over multiple cycles. our technique is orthogonal to solutions based on multiple clock domains.
physical models for electron transport in graphene nanoribbons and their junctions. physics-based equivalent circuit models are presented for armchair and zigzag graphene nanoribbons (gnrs), and their conductances have been benchmarked against those of carbon nanotubes and copper wires. it is demonstrated that gnrs that have large coherence length behave like waveguides for electrons. this poses both challenges and opportunities for designing graphene nanoelectronic circuits.
practical, fast monte carlo statistical static timing analysis: why and how. statistical static timing analysis (ssta) has emerged as an essential tool for nanoscale designs. monte carlo methods are universally employed to validate the accuracy of the approximations made in all ssta tools, but monte carlo itself is never employed as a strategy for practical ssta. it is widely believed to be "too slow" -- despite an uncomfortable lack of rigorous studies to support this belief. we offer the first large-scale study to refute this belief. we synthesize recent results from fast quasi-monte carlo (qmc) deterministic sampling and efficient karhunen-lo&eacute;ve expansion (kle) models of spatial correlation to show that monte carlo ssta need not be slow. indeed, we show for the iscas89 circuits, a few hundred, well-chosen sample points can achieve errors within 5%, with no assumptions on gate models, wire models, or the core sta engine, with runtimes less than 90 s.
clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. a new approach to the problem of clock buffer polarity assignment for minimizing power/ground noise on the clock network is presented. the previous approaches solve the assignment problem in two separate steps: (step 1) generating a clock routing tree of minimum total wirelength, satisfying the clock skew constraint and then (step 2) inserting buffering elements with their polarities under the objective of minimizing power/ground noise while satisfying the clock skew constraint. yet, there is no easy way to predict the result of step 2 during step 1. in our approach, we place the primary importance on the cost of power/ground noise. consequently, we try to minimize the cost of power/ground noise first and then to construct a clock routing tree later while satisfying the clock skew constraint. through experimentation using several benchmark circuits, it is shown that this approach is quite effective and produces very good solutions, reducing the power/ground noise by 75% and the peak current by 26% at the expense of 5% wirelength overhead compared to that produced by the conventional approach.
design and optimization of a digital microfluidic biochip for protein crystallization. proteins crystallization is a commonly used technique for protein analysis and subsequent drug design. it predicts the three-dimensional arrangement of the constituent amino acids, which in turn indicates the specific biological function of a protein. protein crystallization experiments are typically carried out manually on multi-well plates in the laboratory. these experiments are slow, expensive, and error-prone. we present the design of a multi-well plate microfluidic biochip for protein crystallization; this biochip can transfer protein samples, prepare candidate solutions, and carry out crystallization automatically. to reduce the manufacturing cost of such devices, we present an efficient algorithm to generate a pin-assignment plan for the proposed design. the resulting biochip enables control of a large number of on-chip electrodes using only a small number of pins. based on the pin-constrained chip design, we present an efficient shuttle-passenger-like droplet manipulation method to achieve high-throughput and defect-tolerant well loading.
a polynomial time approximation scheme for timing constrained minimum cost layer assignment. as vlsi technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. compared to gate delays, wires are becoming increasingly resistive which makes it more difficult to propagate signals across the chip. however, more advanced technologies (65nm and 45nm) provide relief as the number of metal layers continues to increase. the wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. this provides an entirely new dimension to the traditional wire sizing problem, namely, layer assignment for efficient timing closure. assigning all wires to thick metals improves timing, however, routability of the design may be hurt. the challenge is to assign minimal amount of wires to thick metals to meet timing constraints. in this paper, the minimum cost layer assignment problem is proven to be np-complete. as a theoretical solution for np-complete problems, a polynomial time approximation scheme is proposed. the new algorithm can approximate the optimal layer assignment solution by a factor of 1 + &epsilon; in o(m log log m &middot; n3/&epsilon;2) time for 0 < &epsilon; < 1, where n is the number of nodes in the tree and m is the number of routing layers. this work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem. in addition to its theoretical guarantee, the new algorithm is highly practical. our experiments on 500 testcases demonstrate that the new algorithm can run 2x faster than the optimal dynamic programming algorithm with only 2% additional wire.
modeling and simulation for on-chip power grid networks by locally dominant krylov subspace method. fast analysis of power grid networks has been a challenging problem for many years. the huge size renders circuit simulation inefficient and the large number of inputs further limits the application of existing krylov-subspace macromodeling algorithms. however, strong locality has been observed that two nodes geometrically far have very small electrical impact on each other because of the exponential attenuation. however, no systematic approaches have been proposed to exploit such locality. in this paper, we propose a novel modeling and simulation scheme, which can automatically identify the dominant inputs for a given observed node in a power grid network. this enables us to build extremely compact models by projecting the system onto the locally dominant krylov subspace corresponding to those dominant inputs only. the resulting simulation can be very fast with the compact models if we only need to view the responses of a few nodes under many different inputs. experimental results show that the proposed method can have at least 100x speedup over spice-like simulations on a number of large power grid networks up to 1m nodes.
incorporating logic exclusivity (le) constraints in noise analysis using gain guided backtracking method. crosstalk noise becomes one of the critical issues gating design closure for nano-meter designs. pessimism in noise analysis can lead to significant additional time spent addressing false violations. taking logic correlation into consideration, noise analysis can reduce pessimism significantly by eliminating false noise signals [1]-[3][5]-[7][10]-[13]. eliminating the aggressors from the aggressor candidate set that can not switch simultaneously restricted by the logic exclusivity (le) relationship among them can save simulation time as well. the le problem, being proved as np-complete, is basically to determine the subset (possibly multiple equivalent subsets) of a given aggressor candidate set which has the largest combined weight out of all possible subsets governed by logic exclusivity constraints. this paper presents a new approach in resolving the le problem, which employs a gain guided backtrack search technique that does not require exhaustive search of all the binary paths to reach an optimal solution. we first prove that under certain conditions, if the gain at each level is non-negative, then the result will be optimal. based on this theorem, a new algorithm is developed. the experimental results demonstrate the efficiency and accuracy of this approach. the algorithm can quickly find the optimal solutions for most cases from industry designs and outperforms other methods.
process variability-aware transient fault modeling and analysis. due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. as technology scales further, the increase in transistor integration capacity also leads to the increase in process and environmental variations. despite these difficulties, it is expected that systems remain reliable while delivering the required performance. reliability and variability are emerging as new design challenges, thus pointing to the importance of modeling and analysis of transient faults and variation sources for the purpose of guiding the design process. this work presents a symbolic approach to modeling the effect of transient faults in digital circuits in the presence of variability due to process manufacturing. the results show that using a nominal case and not including variability effects, can underestimate the ser by 5% for the 50% yield point and by 10% for the 90% yield point.
spm management using markov chain based data access prediction. leveraging the power of scratchpad memories (spms) available in most embedded systems today is crucial to extract maximum performance from application programs. while regular accesses like scalar values and array expressions with affine subscript functions have been tractable for compiler analysis (to be prefetched into spm), irregular accesses like pointer accesses and indexed array accesses have not been easily amenable for compiler analysis. this paper presents an spm management technique using markov chain based data access prediction for such irregular accesses. our approach takes advantage of inherent, but hidden reuse in data accesses made by irregular references. we have implemented our proposed approach using an optimizing compiler. in this paper, we also present a thorough comparison of our different dynamic prediction schemes with other spm management schemes. spm management using our approaches produces 12.7% to 28.5% improvements in performance across a range of applications with both regular and irregular access patterns, with an average improvement of 20.8%.
temperature aware task sequencing and voltage scaling. on-chip power density and temperature are rising exponentially with decreasing feature sizes. this alarming trend calls for temperature management at every level of system design. in this paper, we propose task sequencing as a powerful and complimentary mechanism to voltage scaling in improving the thermal profile of an embedded system executing a set of periodic heterogenous tasks under timing constraints. we first derive the peak temperature of a repeating task sequence analytically and develop a heuristic to construct the task sequence that minimizes the peak temperature. experimental evaluation shows that our task sequencing heuristic achieves peak temperature within 0.5&deg;c of the optimal solution and 7.47&deg;c lower, on an average, compared to the worst sequence for a large range of embedded task sets. we also propose an iterative algorithm that combines task sequencing with voltage scaling to further lower the peak temperature while satisfying the timing constraints. for embedded task sets, our combined task sequencing and voltage scaling approach achieves, on an average, 2.1&deg;c -- 6.94&deg;c reduction in peak temperature compared to voltage scaling alone.
hardware protection and authentication through netlist level obfuscation. hardware intellectual property (ip) cores have emerged as an integral part of modern system-on-chip (soc) designs. however, ip vendors are facing major challenges to protect hardware ips and to prevent revenue loss due to ip piracy. in this paper, we propose a novel design methodology for hardware ip protection and authentication using netlist level authentication. the proposed methodology can be integrated in the soc design and manufacturing flow to provide hardware protection to the ip vendors, the chip designer, and the system designer. simulation results on iscas-89 benchmark circuits show that we can achieve high levels of security through a well-formulated obfuscation scheme at less than 10% area overhead under delay constraint.
thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. this paper presents a new approach to active sub-threshold leakage reduction using task migration. the main idea is to replicate a hot module in a design so as to actively migrate its computation at regular intervals, reducing the on-chip temperature and thereby the subthreshold leakage. we observe that choosing which blocks to migrate and their placement in a floorplan is a chicken-and-egg problem. to solve this, we propose a two step floorplanning methodology, wherein, given a base floorplan, we first choose the modules to replicate and then effectively utilize the deadspaces in it by exploiting the lateral conduction of heat in the floorplan to place a module's replica. with an optimized floorplan, using task migration we obtain an average savings of 29% in the active sub-threshold leakage at the expense of about 6% additional area.
a novel fixed-outline floorplanner with zero deadspace for hierarchical design. fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. in this paper, a novel sa-based fixed-outline floorplanner with the optimal area utilization named saffoa is introduced to improve the total wirelength. the basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outline constraint of any aspect ratio. a new topological representation called ordered quadtree is then custom-made for this basic idea to facilitate its integration into sa iterations. after the fixed-outline constraint with 100% area utilization is achieved, we will solve the tradeoff between the chip area and wirelength and thus concentrate on the latter in sa process. experimental results show that the chip wirelength is decreased by about 16.8% and 8.6% on average, compared with two previous fixed-outline floorplanners on soft modules, which are both proved to be better than parquet. besides, our method is still competitive on the wirelength, even if compared with some leading-edge outline-free floorplanners. at last, local refinement is also adopted to guide the sa process and reshape soft modules to meet the constraint on their aspect ratios (ars). with its help, saffoa can still generate feasible floorplans with no deadspace under a strict ar constraint such as [0.5,2].
automated extraction of expert knowledge in analog topology selection and sizing. this paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. the methodology is to take a data-mining perspective on a pareto optimal set of sized analog circuit topologies, then doing: extraction of a specs-to-topology decision tree; global nonlinear sensitivity analysis on topology and sizing variables; and determining analytical expressions of performance tradeoffs. these approaches are all complementary as they answer different designer questions. once the knowledge is extracted, it can be readily distributed to help other designers, without needing further synthesis. results are shown for operational amplifier design on a database containing thousands of pareto optimal designs across five objectives.