waashk/dblp huggingface dataset:
tam optimization for mixed-signal socs using analog test wrappers. we present a new approach for tam optimization and testscheduling in the modular testing of mixed-signal socs. a testplanning approach for digital socs is extended to handle analogcores in a plug-and-play fashion. a test wrapper based on anadc/dac pair and a digital configuration circuit is designed foranalog cores such that these cores can be accessed through digitaltams. in this way, there is no dependence on an analog testbus and expensive mixed-signal testers. experimental results arepresented for several itc'02 soc test benchmarks to which threeanalog cores are added. the results show that the testing of analogcores can be interleaved with the testing of digital cores to reducethe overall testing time for a mixed-signal soc.
dynamic platform management for configurable platform-based system-on-chips. general-purpose system-on-chip platforms consistingof configurable components are emerging as an attractivealternative to traditional, customized solutions (e.g., asics,custom socs), owing to their flexibility, time-to-market advantage,and low engineering costs. however, the adoptionof such platforms in many high-volume markets (e.g, wirelesshandhelds) is limited by concerns about their performance andenergy-efficiency. this paper addresses the problemof enablingthe use of configurable platforms in domains where custom approacheshave traditionally been used. we introduce dynamicplatform management, a methodology for customizing a configurablegeneral-purpose platform at run-time, to help bridgethe performance and energy efficiency gap with custom approaches.the proposed technique uses a software layer that detectstime-varying processing requirements imposed by a set ofapplications, and dynamically optimizes architectural parametersand platform components. dynamic platform managementenables superior application performance, more efficient utilizationof platform resources, and improved energy efficiency,as compared to a statically optimized platform, without requiringany modifications to the underlying hardware.we illustrate dynamic platform management by applying itto the design of a dual-access umts/wlansecurity processingsystem, implemented on a general-purpose configurable platform.experiments demonstrate that, compared to a staticallyoptimized design (on the same platform), the proposed techniquesenable upto 33% improvements in security processingthroughput, while achieving 59% savings in energy consumption(on average).
a specified delay accomplishing clock router using multiple layers. clock routing to minimize the clock skew is very necessary to make high performance lsis. our clock routing method: (1) realizes the specified delay to each input terminal and provides a zero skew; (2) uses multiple routing layers for pin-to-pin routing; and (3) considers the delay arising from the resistance of a through-hole. experimental results show that the delay is within 1% error compared to the specified delay and the skew can be controlled within pico second order.
multi.objective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization. in this paper we present a family of multi-objective hypergraphpartitioning algorithms based on the multilevel paradigm, whichare capable of producing solutions in which both the cut and themaximum subdomain degree are simultaneously minimized. thistype of partitionings are critical for existing and emerging applications in vlsi cad as they allow to both minimize and evenly distribute the interconnects across the physical devices. our experimental evaluation on the ispd98 benchmark show that ouralgorithms produce solutions that when compared against thoseproduced by hmetis have a maximum subdomain degree that isreduced by up to 35% while achieving comparable quality in terms of cut.
latch optimization in circuits generated from high-level descriptions. in a gate-level description of a finite state machine (\fsm), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. we efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. we reduce the number of latches while controlling the logic size. we demonstrate the efficacy of our techniques on some large industrial examples.
optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. it is generally accepted that the dynamic voltage scaling (dvs) is one of the most effective techniques for energy minimization. according to the granularity of units to which voltage scaling is applied, the dvs problem can be divided into two subproblems: (i) inter-task dvs problem; and (ii) intra-task dvs problem. a lot of effective dvs techniques have addressed either one of the two subproblems, but none of them have attempted to solve both simultaneously, which is mainly due to an excessive computation complexity to solve it optimally. this work addresses this core issue, that is, can the combined problem be solved effectively and efficiently? more specifically, our work shows, for a set of inter-dependent tasks, that the combined dvs problem can be solved optimally in polynomial time. experimental results indicate that the proposed integrated dvs technique is able to reduce energy consumption by 10.6% on average over the results by (zhang et al., 2002 and seo et al., 2004) (i.e., a straightforward combination of two optimal inter- and intra task dvs techniques).
akord: transistor level and mixed transistor/gate level placement tool for digital data paths. this paper describes akord, a transistor level and mixed transistor/gate level placement tool. akord has unique layout capabilities that address the digital data path layout problem. in order to improve communication between the placement and routing steps, new post placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. akord supports dynamically: 1. transistor folding without usage of device libraries that contain variants of the same device; 2. device merging, including information about optimal transistor chain formation; and 3. well area minimization. experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest.
exploiting level sensitive latches in wire pipelining. wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. existing approaches on wire pipelining are mostly based on edge triggered flip-flops. in this paper, we demonstrate the advantages of using level sensitive latches in terms of both latency and area cost. the input-output timing coupling and the strict short path constraint for latches demand additional design elaborations compared with flip-flops. new approaches are proposed in this work to solve these difficulties so that the advantages of latches can be fully utilized. in particular, a deferred delay padding technique is developed to correct short path violations with the minimal extra cost. these techniques are integrated with a dynamic programming based concurrent synchronous element and repeater insertion framework. experimental results confirm the advantages of using latches as well as effectiveness of our algorithms.
repeater insertion and wire sizing optimization for throughput-centric vlsi global interconnects. as technology advances towards billion transistor systems, the cost of complex wire networks will require area efficient wiring methodologies. this paper explores the tradeoffs between wire latency, throughput and area for deep submicron (dsm) interconnect technologies. from basic physical models, optimal wiring sizing for repeater networks are rigorously derived and compared to hspice simulations. key case studies from 250nm to 70nm technologies reveal that significant wire area reduction (20--50%) can be achieved with optimal wire sizing to maximize the throughput per unit wire area.
discrete vt assignment and gate sizing using a self-snapping continuous formulation. this paper presents a novel approach towards the simultaneous vt-assignment and gate-sizing problem. this inherently discrete problem is formulated as a continuous problem, allowing it to be solved using any of several widely available and highly efficient non-linear optimizers. we prove that, under our formulation, the optimal solution has discrete vts assigned to almost every gate, thus eliminating the need for a sophisticated snapping heuristic. we show that this technique performs dual-vt assignment and gate sizing in a very efficient manner. compared to a sensitivity based method, we achieve average leakage savings of 31% and average total power savings of 7.4% with very efficient runtimes.
macromodeling of analog circuits for hierarchical circuit design. hierarchy plays a significant role in the design of digital and analog circuits. at each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. this paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. a modified simplicial approximation technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. however, due to lack of space, only details of the performance macromodeling techniques are included. macromodels are developed and verified for analog blocks at three different levels of hierarchy (current mirror, opamp, and a/d converter).
shaping interconnect for uniform current density. as the vlsi technology scaling down, the electromigration problem becomes one of the major concerns in high-performance ic design for both power network and signal interconnects. for a uniform width metal interconnect, the current flows through the driving point is much larger than that flows through the fan-out point since much of current bypasses to the ground through the parasitic capacitance. this causes the lifetime of driving point to be quite shorter than that of fan-out point due to electromigration. in order to avoid breakdown at the driving point, wire sizing is an effective solution. thus we present a wire shape, of which the current density as well as the lifetime is uniform along the wire. spice simulation results show the uniformity of current density of this wire shape. under the same current density bound, we demonstrate that chip area and power consumption are significantly reduced for this wire shape compared to the uniform width wire. the wire shape functions we derived are continuous. however, it is not necessary to ultra-accurately reproduce the continuous shape on the silicon, since we can round the continuous shape to the nearest available litho width and this will not degrade the uniformity of current density.
accurate cmos bridge fault modeling with neural network-based vhdl saboteurs. this paper presents a new bridge fault model that is based on a multiple layer feedforward neural network and implemented within the framework of a vhdl saboteur cell. empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than existing approaches. the new model computes exact bridged node voltages and propagation delay times with due attention to surrounding circuit elements. this is significant since, with the exception of full analog simulation, no other technique attempts to model the delay effects of bridge defects. yet, compared to these analog simulations, the new approach is orders of magnitude faster and achieves reasonable accuracy; computing bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps.
expanding the frequency range of awe via time shifting. the new technique of time shifted moment matching (tsmm) is introduced in this paper. the tsmm technique performs moment matching (for expansion around s = 0) on a time-shifted version of the original signal. as compared to other well-known techniques (such as awe by pillage and rohrer, 1990), tsmm offers distinct advantages. the 50% delay and rise time are determined with much more accuracy for a given approximation order. moreover, the solutions have significantly improved accuracy as compared to awe, especially for moderate to highly inductive signals. tsmm is able to achieve the approximation capability of pvl (feldmann and freund, 1995) and prima (odabasioglu et al., 1998) with much lower approximation order.
branch merge reduction of rlcm networks. in this paper we consider the problem of finding asmaller rlcm circuit that approximately replicates thebehavior (up to a certain frequency) of a given rlcm circuit.targeted at parasitic extractors for verification of vlsidesigns, the proposed algorithm uses a branch merge, nodeelimination methodology, with the choice of nodes forelimination being guided by time-constant criteria.reliable,accurate, easy to code, the algorithm works well for coupledbuses and clocks, strongly inductive networks, and low-losstransmission lines, as well as for lossy rlc networks.
ticer: realizable reduction of extracted rc circuits. time constant equilibration reduction (ticer) is a novel rc reduction method tailored for extract/reduce cad tools. geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. the resulting rc circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, ticer produces smaller, less-stiff rc networks. it produces realizable rc circuits; can retain original network topology; scales well to large networks (~107 nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.
equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. this paper addresses the problem of equivalence verification of rtl descriptions. the focus is on datapath-oriented designs that implement polynomial computations over fixed-size bit-vectors. when the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself as polynomial algebra over finite integer rings of residue classes z/sub 2//sup m/. the verification problem then reduces to that of checking equivalence of multi-variate polynomials over z/sub 2//sup m/. this paper exploits the concepts of polynomial reducibility over z/sub 2//sup m/ and derives an algorithmic procedure to transform a given polynomial into a unique canonical form modulo 2/sup m/. equivalence testing is then carried out by coefficient matching. experiments demonstrate the effectiveness of our approach over contemporary techniques.
recursive bipartitioning of bdds for performance driven synthesis of pass transistor logic circuits. in this paper, we address the problem of performance oriented synthesis of pass transistor logic (ptl) circuits using a binary decision diagram (bdd) decomposition technique. we transform the bdd decomposition problem into a recursive bipartitioning problem and solve the latter using a max-flow min-cut technique. we use the area and delay cost of the ptl implementation of the logic function to guide the bipartitioning scheme. using recursive bipartitioning and a one-hot multiplexer circuit, we show that our ptl implementation has logarithmic delay in the number of inputs, under certain assumptions. the experimental results on benchmark circuits are promising, since they show the significant delay reductions with small or no area overheads as compared to previous approaches.
on average power dissipation and random pattern testability of cmos combinational logic networks. the implications of the observation that the probability of the occurrence of a transition on a wire of a circuit affects both the average power dissipation and the random pattern testability of a circuit are investigated. it is shown that restructuring a logic circuit can significantly affect its average power dissipation. various methods for the synthesis of combinational logic networks are presented and the effect of different algorithms on the power dissipation of the circuit is demonstrated. the dual problem of improving the random pattern testability of logic circuits is emphasized. it is shown that modifying the signal probabilities can significantly affect the random pattern testability of a circuit
reversible logic circuit synthesis. reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. they are also a fundamental requirement in the emerging field of quantum computation. we investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). we prove constructively that every even permutation can be implemented without temporary storage using not, cnot and toffoli gates. we describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting distributions of circuit sizes. finally, in an application important to quantum computing, we synthesize oracle circuits for grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.
graph algorithms for clock schedule optimization. for performance-driven synthesis of sequential circuits, the optimal clocking problem is considered, and it is shown that it is reducible to a parametric shortest path problem. constraints are used that take into account both the short and long paths. the main contributions are efficient graph algorithms to solve the set of constraints necessary for correct clocking
efficient implementation of retiming. retiming is a technique for optimizing sequential circuits. it repositions the registers in a circuit leaving the combinational cells untouched. the objective of retiming is to find a circuit with the minimum number of registers for a specified clock period. more than ten years have elapsed since leiserson and saxe first presented a theoretical formulation to solve this problem for single-clock edge-triggered sequential circuits. their proposed algorithms have polynomial complexity; however naive implementations of these algorithms exhibit o(n3) time complexitiy and o(n2) space complexity when applied to digital circuits with n combinational cells. this renders retiming ineffective for circuits with more than 500 combinational cells. this paper addresses the implementation issues required to exploit the sparsity of circuit graphs to allow min-period retiming and constrained min-area retiming to be applied to circuits with as many as 10,000 combinational cells. we believe this is the first paper to address these issues and the first to report retiming results for large circuits.
body-voltage estimation in digital pd-soi circuits and its application to static timing analysis. we describe a technique for estimating the floating body potentials of partially-depleted silicon-on-insulator (pd-soi) circuits under steady switching activity and under initial activity after a long period of quiescence. the approach is based on a unique state diagram abstraction of the pd-soi fet that captures all of the essential device physics. this picture yields a simple analytic model of the body voltage which is used within the context of a prototype transistor-level static timing analysis engine. results are presented that demonstrate the accuracy of the analytic body-voltage model and the reduction in delay uncertainty possible with this technique.
noise in deep submicron digital design. as technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of vlsi systems. this paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. the noise sources which are plaguing digital systems are explained. a metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. analysis issues associated with on-chip interconnect are also considered. this paper concludes with a discussion of the device, ciruit, layout, and logic design issues associated with noise.
global harmony: coupled noise analysis for full-chip rc interconnect networks. noise is becoming one of the most important metrics in the design of vlsi systems, certainly of comparable importance to area, timing, and power. in this paper, we describe global harmony, a methodology for the analysis of coupling noise in the global interconnect of large vlsi chips, being developed for the design of high-performance microprocessors. the architecture of global harmony involves a careful combination of static noise analysis, static timing analysis, and reduced-order modelling techniques. we describe a reduced-order modelling approach that allows for passive multiport reduction of rc netlists as impedance macromodels while preserving the symmetry and sparsity of the state matrices for efficient storage. we describe how the macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis.
full-chip, three-dimensional, shapes-based rlc extraction. in this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, rlck extraction tool, developed as part of a university-industry collaboration. the technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. mutual inductances are extracted for accurate noise analysis. the tool, assura rlcx, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to cadence's existing assura rcx extractor.
spin-test: automatic test pattern generation for speed-independent circuits. spin-test is a simulation-based gate-level atpg system for speed-independent circuits. its core engine is an a* search algorithm which employs an accurate fault simulator and an efficient cost function to guide a deterministic test pattern generation phase. a random test pattern generation phase is also available in order to improve run time. the key atpg challenge in speed-independent circuits is the generation of patterns that are valid independently of the relative timing and the order of arrival of signals. spin-test addresses this challenge by guaranteeing fault sensitization with hazard/race-free patterns and response observation that is not affected by oscillations or non-deterministic circuit states. experimental results on benchmark circuits demonstrate the efficiency of spin-test in terms of both high fault coverage and low test generation time.