waashk/dblp huggingface dataset:
a network-flow approach to timing-driven incremental placement for asics. we present a novel incremental placement methodology called flowplace for significantly reducing critical path delays of placed standard-cell circuits. flowplace includes: a) a timing-driven (td) analytical global placer tan that uses accurate delay functions and minimizes a combination of linear and quadratic objective functions; b) a network flow based detailed placer tif that has new and effective techniques for performing td incremental placement and satisfying rowlength (white space) constraints. we have obtained results on three sets of benchmarks: i) td versions of the ibm benchmark suite that we have constructed; ii) benchmarks used in td-dragon; iii) the faraday benchmarks. results show that starting with dragon-placed circuits, we are able to obtain up to 34% and an average of 18% improvement in critical path delays, at an average of 17.5% of the run-time of the dragon placer. starting with a state-of-the-art td placer td-dragon, for the td-dragon benchmarks we obtain up to about 10% and an average of 4.3% delay improvement with 12% of td-dragon's run times; this is significant as we are extracting performance improvements from a performanceoptimized layout. wire length deterioration on the average over all benchmark suites is less than 8%.
variability and yield improvement: rules, models, and characterization. yield and variability are becoming detractors for successful design in sub-90-nm process technologies. we consider the fundamental lithography and process issues that are driving variability and yield and the role of design rules in future processes. we examine the importance of layout-aware modeling and layout regularity, including advantages and cost. characterization structures for examining the electrical effects of device-level variability are discussed as well as circuit techniques for mitigating variability and yield challenges.
an analytical model for negative bias temperature instability. negative bias temperature instability (nbti) in pmos transistors has become a significant reliability concern in present day digital circuit design. with continued scaling, the effect of nbti has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. since nbti is strongly dependent on the time for which the pmos device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. this has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to nbti. an analytical model for nbti is derived using the framework of the reaction-diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. simulations on iscas benchmarks under a 70nm technology show that nbti causes a delay degradation of about 8% in combinational logic based circuits after 10 years (&ap; 3 x 108s).
a statistical framework for post-silicon tuning through body bias clustering. adaptive body biasing (abb) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constraints. assigning individual bias control to each gate leads to severe overhead, rendering the method impractical. however, assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness. in this paper, we propose a new variability-aware method that clusters gates at design time into a handful of carefully chosen independent body bias groups, which are then individually tuned post-silicon for each die. we show that this allows us to obtain near-optimal performance and power characteristics with minimal overhead. for each gate, we generate the probability distribution of its post-silicon ideal body bias voltage using an efficient sampling method. we then use these distributions and their correlations to drive a statistically-aware clustering technique. we study the physical design constraints and show how the area and wirelength overhead can be significantly limited using the proposed method. compared to a fixed design time based dual threshold voltage assignment method, we improve leakage power by 38-71% while simultaneously reducing the standard deviation of delay by 2-9x.
guaranteeing performance yield in high-level synthesis. meeting timing constraint is one of the most important issues for modern design automation tools. this situation is exacerbated with the existence of process variation. current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today's deterministic design to statistical or probabilistic design. in this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. the proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint.
robust estimation of parametric yield under limited descriptions of uncertainty. reliable prediction of parametric yield for a specific design is difficult; a significant reason is the reliance of the yield estimation methods on the hard-to-measure distributional properties of the process data. existing methods are inadequate when dealing with real-life distributions of process and environmental parameters, and limited availability of parameter data during early design. this paper proposes a robust technique for full-chip parametric yield estimation; the proposed work is based on the rigorous notions of non-parametric robust statistics which permits estimation based on the knowledge of the range and the limited number of moments (e.g. mean and variance) of the parameter distributions. fully or partially specified process and environmental parameters can be described by robust representations, and used to estimate probabilistic bounds for leakage dissipation. the proposed approach is applied to estimating the chip-level parametric yield. the experimental results show that the robust estimation algorithm improves the total leakage estimate by 5-13% at the 99th percentile across distinct frequency bins, compared to using only the intervals of partially-specified parameters.
from single core to multi-core: preparing for a new exponential. in the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. recently, clock speeds have tapered and thermal and power dissipation envelopes have remained flat. however, the demand for increasing performance continues which has fueled the move to integrated multiple processor (multi-core) designs. this paper discusses this trend towards multi-core processor designs, the design challenges that accompany it and a view of the research required to support it.
un/dopack: re-clustering of large system-on-chip designs with interconnect variation for low-cost fpgas. fpga device area is dominated by interconnect, so low-cost fpga architectures often have reduced interconnect capacity. this limited routing capacity creates a hard channel width constraint that can make it difficult for cad tools to successfully map a circuit into these devices. instead of migrating a design to a high-cost, resource-rich architecture that is easier to route, we present a cheaper alternative: a fully automated cad flow (un/dopack) that finds local regions of high interconnect demand and reduces it by spreading out the logic in that region. this is done by introducing whitespace in the form of empty logic elements (les) within the configurable logic blocks (clbs) of the congested region. after spreading, the congested region occupies more routing channels and so obtains access to greater aggregate interconnect capacity. although this has the side effect of using more clbs, it has the advantage of lowering peak interconnect demands and making a previously-unroutable circuit routable. we also design a new set of synthetic benchmark circuits that model interconnect variation within a large design. using these benchmarks, we show that circuits with high interconnect variation require fpga devices to have large channel widths. however, since congestion of such circuits is localized, un/dopack is very good at reducing the peak demands of circuits with high interconnect variation. our results suggest that even for an average rent exponent of 0.62 (a modest value), a large variation of this exponent within a design will also require fpgas to have large channel widths. thus, it is crucial to study interconnect variation of benchmark circuits when designing lowcost fpgas. previous research studying interconnect properties focuses on average rent exponent values of each design, but we believe new work should study variation as well. for circuits with high interconnect variation, we demonstrate that channel widths can be reduced by up to ~40% with only ~10% increase in area.
energy budgeting for battery-powered sensors with a known task schedule. battery-powered wireless sensors are severely constrained by the amount of the available energy. a method for computing the energy budget per sensing task can be a valuable design aid for sensor network optimizations. this work presents such a method that computes the upper and lower bounds on the task energy budget for a sensor node that must remain operational over a specified lifetime, with a known task schedule. these bounds take into account nonlinear changes in the battery voltage, capacity loss at high discharge rates, charge recovery, and capacity fade over time. we also propose efficient approximations replacing expensive calculations of the battery voltage while computing the energy budget bounds.
a code refinement methodology for performance-improved synthesis from c. although many recent advances have been made in hardware synthesis techniques from software programming languages such as c, the performance of synthesized hardware commonly suffers due to the use of c constructs and coding practices that are not appropriate for hardware. most previous approaches to addressing this problem require drastic changes to coding practice. we present an approach that instead requires only minimal changes but yields significant speedups. in this approach, a software developer initially writes c code as they normally would, and then applies simple refinement guidelines to only the performance-critical code regions, which are the regions most likely to be synthesized to hardware. alternatively, if a designer is aware of performance-critical parts of the application, the guidelines could be followed during development. in this study, we analyze dozens of embedded benchmarks to determine the most common c coding practices that limit hardware performance, and introduce coding guidelines to make the code more amenable to synthesis. those guidelines typically require minimal coding effort, generally consisting of less than ten lines of code for each guideline. the guidelines typically represent modifications that require designer knowledge, making the guidelines difficult or impossible for synthesis tools to automate. we apply these guidelines to six benchmarks, resulting in average speedups of 3.5x compared to synthesis from the original code with a negligible software size and performance overhead.
studying a gals fpga architecture using a parameterized automatic design flow. routing delays dominate other delays in current fpga designs. we have proposed a novel globally asynchronous locally synchronous (gals) fpga architecture called the gapla to deal with this problem. in the gapla architecture, the fpga area is divided into locally synchronous blocks and the communications between them are through asynchronous i/o interfaces. an automatic design flow is developed for the gapla architecture. starting from behavioral description, a design is partitioned into smaller modules and fit to gapla synchronous blocks. the asynchronous communications between modules are then sytthesized. the cad flow is parameterized in modeling the gapla architecture. by manipulating the parameters, we could study different factors of the designed gapla arcitecturc. our experimental results show an average of 20% performance improvement could be achieved by the gapla architecture.
analytical modeling of sram dynamic stability. in this paper, for the first time, a theory for evaluating dynamic noise margins of sram cells is developed analytically. the results allow predicting the transient error susceptibility of an sram cell using a closed-form expression. the key innovation involves using the methods of nonlinear system theory in developing the model. it is shown that when a transient noise of given magnitude affects a sensitive node of a cell, the bi-stable, feedback-driven nature of the cell determines whether the noise will be suppressed or will evolve to eventually flip state. the specific formal and quantitative result is a closed-form expression that can be used to predict whether a cell flip will occur for a noise signal with specific characteristics, and for a given sram cell design. experiments show excellent match between the analytical prediction and the spice simulation results.
an efficient technique for synthesis and optimization of polynomials in gf(2). this paper presents an efficient technique for synthesis and optimization of polynomials over gf(2m), where m is a non-zero positive integer. the technique is based on a graph-based decomposition and factorization of polynomials over gf(2m), followed by efficient network factorization and optimization. a technique for efficiently computing coefficients over gf(pm), where p is a prime number, is first presented. the coefficients are stored as polynomial graphs over gf(pm). the synthesis and optimization is initiated from this graph based representation. the technique has been applied to minimize multipliers over all the 51 fields in gf(2k), k = 2...8 in 0.18 micron cmos technology with the help of the synopsys&reg; design compiler. it has also been applied to minimize combinational exponentiation circuits, and other multivariate bit- as well as word-level polynomials. the experimental results suggest that the proposed technique can reduce area, delay, and power by significant amount.
combinatorial algorithms for fast clock mesh optimization. we present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. due to the high redundancy, a mesh architecture offers high tolerance towards variation in the clock skew. however, such a redundancy comes at the expense of mesh wire length and power dissipation. based on survivable network theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redundancy. such a formulation offers designer the option to trade-off between power and tolerance to process variations. experimental results indicate that our techniques can result in power savings up to 28% with less than 4% delay penalty.
runtime distribution-aware dynamic voltage scaling. we propose a new intra-task dynamic voltage scaling (dvs) method to capture an important fact of 'software runtime distribution' and integrate it into dvs effectively. specifically, the proposed method finds performance levels, for a given software runtime distribution, i.e. statistical profiling of execution cycles (neither the execution cycle of worst-case execution path nor the worst-case execution cycles of basic blocks), which leads to a 'minimal energy consumption while satisfying the given deadline constraints. experimental results report that the proposed method gives 19.2%~33.3% further energy reduction compared with the best-known methods for two industrial multimedia software programs, h.264 decoder and mpeg4 decoder.
a framework for statistical timing analysis using non-linear delay and slew models. in this paper we propose a framework for statistical static timing analysis (ssta) considering intra-die process variations. given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. using these accurate delay models, we propose a method to perform ssta based on a quadratic delay and slew model. the method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. our results indicate less than 4% error in the variance of the delay models compared to spice monte carlo and less than 1% error in the variance of the circuit delay compared to monte carlo simulations.
template-based parasitic-aware optimization and retargeting of analog and rf integrated circuit layouts. parasitic effects are extremely significant for the performance of analog and rf integrated circuits. although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics cannot be guaranteed to meet the performance requirements. in this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/rf integrated circuits. given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints. using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved effectively and efficiently. the algorithm has successfully retargeted operational amplifiers and an rf low-noise amplifier within minutes of cpu time.
automatic memory reductions for rtl model verification. we present several techniques for automatically reducing memories in rtl designs. this includes a new memory abstraction algorithm that allows us to greatly reduce the size of memories and a technique based on-term rewriting that further improves the abstraction. in contrast to previously proposed methods for abstracting memories of rtl designs, our methods are general---e.g., they allow us to arbitrarily and directly compare memories---and they are sound and complete---e.g., there are no false positives or negatives. in addition, the combination of our techniques allows us to automatically verify rtl pipelined machine designs beyond the reach of current state-of-the-art methods, as our experimental results show.
accelerating high-level bounded model checking. sat-based bounded model checking (bmc) has been found promising in finding deep bugs in industry designs and scaling well with design sizes. however, it has limitations due to requirement of finite data paths, inefficient translations and loss of high-level design information during the bmc problem formulation. these shortcomings inherent in boolean-level bmc can be avoided by using high-level bmc. we propose a novel framework for high-level bmc, which includes several techniques that extract high-level design information from efsm models to make the verification model "bmc friendly", and use it on-the-fly to simplify the bmc problem instances. such techniques overcome the inherent limitations of boolean-level bmc, while allowing integration of state-of-the-art techniques for bmc. in our controlled experiments we found signficant performance improvements achievable by the proposed techniques.
molecular organic electronic circuits. electronic energy disorder associated within amorphous and polycrystaline molecular organic thin film structures strongly affects the macroscopic observable behavior of organic field effect transistors (ofet) and poses practical challenges to implementing ofet circuits. it has been convenient to ignore the detailed physical processes associated with this disorder and model ofet behavior as equivalent to silicon fets, but such simplifications limit our ability to develop integrated circuit technology as they fail to predict the true integrated ofet behavior. this talk will highlight the evolution of the organic electronic circuit technology and the challenges that lay ahead, emphasizing the need for physically accurate models of device behavior as the cornerstone of any future circuit advancements.
simultaneous power and thermal integrity driven via stapling in 3d ics. the existing work on via-stapling in 3d integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. this paper presents the first in-depth study on simultaneous power and thermal integrity driven viastapling in 3d design. the transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal vias by on average 11.5%, and simultaneous optimization using transient thermal analysis reduces non-signal vias by on average 34%. the via reduction would be higher for the 3d design with more device layers.
faster, parametric trajectory-based macromodels via localized linear reductions. trajectory-based methods offer an attractive methodology for automated, on-demand generation of macromodels for custom circuits. these models are generated by sampling the state trajectory of a circuit as it simulates in the time domain, and building macromodels by reducing and interpolating among the linearizations created at a suitably spaced subset of the time points visited during training simulations. however, a weak point in conventional trajectory models is the reliance on a single, global reduction matrix for the state space. we develop a new, faster method that generates and weaves together a larger set of smaller localized linearizations for the trajectory samples. the method not only improves speedups to 30x over spice, but as a side benefit also provides a platform for parametric small-signal simulation of circuits with variational device/process parameters, at a speedup of roughly 200x over spice.