waashk/acm huggingface dataset:
lyra: a new approach to geometric layout rule checking  lyra is a layout rule checking program for manhattan vlsi circuits. in lyra, rules are specified in terms of constraints that must hold at certain corners in the design. the corner-based mechanism permits a wide variety of rules to be specified easily, including rules involving asymmetric constructs such as transistor overhangs. lyra's mechanism also has locality, which can be exploited to construct incremental and/or hierarchical checkers. a rule compiler translates symbolic rules into efficient code for checking those rules, and permits the system to be retargeted for different processes.  michael h. arnold john k. ousterhout
a performance comparison of contemporary dram architectures in response to the growing gap between memory access time and processor speed, dram manufacturers have created several new dram architectures. this paper presents a simulation- based performance study of a representative group, each evaluated in a small system organization. these small-system organizations correspond to workstation-class computers and use on the order of 10 dram chips. the study covers fast page mode, extended data out, synchronous, enhanced synchronous, synchronous link, rambus, and direct rambus designs. our simulations reveal several things: (a) current advanced dram technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-l2 address stream still contains significant locality, though it varies from application to application; and (d) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time. vinodh cuppu bruce jacob brian davis trevor mudge
a practical online design rule checking system  in this paper, we propose a practical online design rule checking system, which can provide the following features: an ability to cope with a complicated and wide variety of design rules with high accuracy, easy use, high speed incremental drc (simultaneous checking with pattern editing) and total drc (non-simultaneous checking), high speed pattern editing, and a small memory space. for the last three items, a field block data structure is developed. experimental results show this system is very effective for vlsi cell layout design.  goro suzuki yoshio okamura
microarchitecture modelling through adl  adl is an architecture description language that has been developed to model computer architectures at different levels of detail, as for instance, at the microarchitecture level.  target architectures described in adl are processed by the support system of the language which generates an interpreter program related to the description of the target machine. the interpreter reproduces the behavior of the architecture being modeled, including the interpretation of the target code.  in addition to a brief review of the language and the implementation details of its support system, this paper also shows some methods to deal with target machine parallelism, and the modeling of two microprogrammable machines.  e. s.t. fernandes
ils - interactive logic simulator  due to increasing vlsi complexity, logic level simulators have become necessary tools for design verification and test generation. logic simulators must respond to this increased demand by providing additional functionality in a user-friendly environment. ils (interactive logic simulator) currently under development in the cad lab of hewlett-packard co. provides these features.  ils accepts a hierarchical, scoped description of the network topology. this description may consist of libraries, blocks, ils-defined primitives (transistors and gates), or user-defined primitives. these multiple levels simplify network description and allow ils to accurately simulate a wide variety of circuits. the simulator incorporates a new modeling scheme which allows functional, logic, and circuit level primitives to communicate efficiently. in addition, ils features a new concept in simulation control languages to facilitate generation of functional test programs. this paper will briefly review these significant benefits provided by the ils simulator.  gregory d. jordan brij b. popli
symbolic parasitic extractor for circuit simulation (specs)  this paper describes the design, development and implementation of the program specs. the purpose of specs is to automatically extract from a rockwell microelectronic symbolic matrix description a netlist for circuit simulation. this program differs from others in that it uses a symbol layout matrix as an input, calculates both interelectrode and intrinsic capacitance, calculates conductor resistance, produces a schematic representation of the network and has a selective trace, i.e., traces only the circuit or network of interest.  j. d. bastian m. ellement p. j. fowler c. e. huang l. p. mcnamee
automatic tub region generation for symbolic layout compaction  this paper describes a new algorithm that automatically generates tub regions for vlsi symbolic layouts with quality comparable to that of human designers. the algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. in addition, the algorithm runs at o(n2) time and o(n) space with the expected run time of o(nlogn).  c.-y. lo
is sc + ilp = rc? sequential consistency (sc) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high performance implementations. release consistency (rc), however, enables the highest performance implementations but puts the burden on the programmer to specify which memory operations need to be atomic and in program order. this paper shows, for the first time, that sc implementations can perform as well as rc implementations if the hardware provides enough support for speculation. both sc and rc implementations rely on reordering and overlapping memory operations for high performance. to enforce order when necessary, an rc implementation uses software guarantees, whereas an sc implementation relies on hardware speculation. our sc implementation, called sc++, closes the performance gap because: (1) the hardware allows not just loads, as some current sc implementations do, but also stores to bypass each other speculatively to hide remote latencies, (2) the hardware provides large speculative state for not just processor, as previously proposed, but also memory to allow out-of-order memory operations, (3) the support for hardware speculation does not add excessive overheads to processor pipeline critical paths, and (4) well-behaved applications incur infrequent rollbacks of speculative execution. using simulation, we show that sc++ achieves an rc implementation's performance in all the six applications we studied. chris gniady babak falsafi t. n. vijaykumar
design of concurrently testable microprogrammed control units  four schemes for the design of concurrently testable microprogrammed control units are presented. in schemes 1 and 2 the concept of path signatures is used for detection of malfunctions in the control unit. two different methods for computation of signatures are given. in schemes 3 and 4, a check-symbol is assigned to each microinstruction and the integrity of these check-symbols is checked concurrently. a deterministic approach is used for generation of check-symbols in scheme 4. a comparative study of these schemes is done with respect to storage and time overhead, error coverage, and implementation complexity.  masood namjoo
fault-tolerant wafer-scale architectures for vlsi  the basic problem which limits both yields and chip sizes is the fact that circuits created using current design techniques will not function correctly in the presence of even a single flaw of sufficient size anywhere on the chip. in this work we examine the problem of constructing chips up to the size of a wafer which operate correctly despite the presence of such flaws. this can be accomplished by building on the wafer a nearest-neighbor network of small, independent, asynchronously communicating modules. a specific algorithm to be performed by the wafer is then mapped onto a fault-free subgraph of the network. we are interested in algorithms which map naturally onto a linear array of identical processors. construction of fault-tolerant implementations of these algorithms is addressed in two contexts. first we consider the general problem of finding a fault-free subgraph of the host network which is isomorphic to the linear array required to solve a problem. we then examine ways to tailor a specific, known algorithm to the fault-tolerant context.  donald fussell peter varman
physical design for fpgas  fpgas have been growing at a rapid rate in the past few years. their ever- increasing gate densities and performance capabilities are making them very popular in the design of digital systems. in this paper we discuss the state- of-the-art in fpga physical design. compared to physical design in traditional asics, fpgas pose a different set of requirements and challenges. consequently the algorithms in fpga physical design have evolved differently from their asic counterparts. apart from allowing fpga users to implement their designs on fpgas, fpga physical design is also used extensively in developing and evaluating new fpga architectures. finally, the future of fpga physical design is discussed along with how it is interacting with the latest fpga technologies.  rajeev jayaraman
tradeoffs and design of an ultra low power uhf transceiver integrated in a standard digital cmos process  a broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. these systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost and versatility. the design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1v).  these considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5μm digital cmos process. the chip is dedicated to a distributed sensors network and is based on a direct- conversion architecture. the circuit prototype operates in the 434 mhz ism band and consumes only 1mw in receive mode. it achieves a -95dbm sensitivity for a data rate of 24kbit/s. the transmitter section is designed for 0dbm output power under the minimum 1v supply, with a global efficiency higher than 15%.  alain-serge porret thierry melly e. a. vittoz c. c. enz
a new heuristic for single row routing problems  in this paper, we present a new heuristic algorithm for the classical single row routing problem. the algorithm is based on a graph theoretic decomposition scheme and uses modified cut-numbers. the algorithm was implemented in c on vax 8200. the experimental results show that the quality of solutions generated by our algorithm could be up to 36% better as compared to the existing algorithms.  n. a. sherwani j. s. deogun
exfi: a low-cost fault injection system for embedded microprocessor-based boards  evaluating the faulty behavior of low-cost embedded microprocessor-based boards is an increasingly important issue, due to their adoption in many safety critical systems. the architecture of a complete fault injection environment is proposed, integrating a module for generating a collapsed list of faults, and another for performing their injection and gathering the results. to address this issue, the paper describes a software- implemented fault injection approach based on the trace exception mode available in most microprocessors. the authors describe exfi, a prototypical system implementing the approach, and provide data about some sample benchmark applications. the main advantages of exfi are the low cost, the good portability, and the high efficiency  a. benso p. prinetto m. rebaudengo m. sonza reorda
parity logging disk arrays  parity-encoded redundant disk arrays provide highly reliable, cost-effective secondary storage with high performance for reads and large writes. their performance on small writes, however, is much worse than mirrored disks---the traditional, highly reliable, but expensive organization for secondary storage. unfortunately, small writes are a substantial portion of the i/o workload of many important, demanding applications such as on-line transaction processing. this paper presents parity logging, a novel solution to the small- write problem for redundant disk arrays. parity logging applies journalling techniques to reduce substantially the cost of small writes. we provide detailed models of parity logging and competing schemes---mirroring, floating storage, and raid level 5---and verify these models by simulation. parity logging provides performance competitive with mirroring, but with capacity overhead close to the minimum offered by raid level 5. finally, parity logging can exploit data caching more effectively than all three alternative approaches.  daniel stodolsky mark holland william v. courtright garth a. gibson
plus: a distributed shared-memory system  plus is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of cpu- bound applications. plus supports shared memory and efficient synchronization. memory access latency is reduced by non-demand replication of pages with hardware-supported coherence between replicated pages. the architecture has been simulated in detail and the paper presents some of the key measurements that have been used to substantiate our architectural decisions. the current implementation of plus is also described.  roberto bisiani mosur ravishankar
automatic layout algorithms for function blocks of cmos gate arrays  automatic layout algorithms, placement and routing, for function blocks of cmos gate arrays are presented.  the placement algorithm assigns transistors to basic cells so as to minimize the number of cells used and to minimize the number of interconnections crossing cut-lines. the former objective is achieved by finding a maximum matching and the latter is achieved by iterative interchanges of transistor pairs. a new routing technique based on channel routing methods is introduced to handle the internal cell area. it intends to route with the primary use of the first layer and with the least use of tracks.  a program based on the algorithms has been developed and applied to many block designs for up to 200 transistors. the results show that the presented algorithms could realize as good a layout as manual.  shigeo noda hitoshi yoshizawa etsuko fukuda haruo kato hiroshi kawanishi takashi fujii
co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors  this paper presents a hardware/software co-synthesis approach to pipelined isp (instruction set processor) design. the approach synthesizes the pipeline structure from a given instruction set architecture (behavioral) specification. in addition, it generates a set of reordering constraints that guides the compiler back-end (reorderer) to properly schedule instructions so that possible pipeline hazards are avoided and throughput is improved.  co-synthesis takes place while resolving pipeline hazards, which can be attributed to interin-struction dependencies (iids). an extended taxonomy of iids have been proposed for the systematic analysis of pipeline hazards. hardware/software methods are developed to resolve iids. algorithms based on taxonomy and resolutions are constructed and integrated into the pipeline synthesis process to explore hardware and software design space. application benchmarks are used to evaluate possible designs and guide the design decision. the power of the co-synthesis tool piper is demonstrated through pipeline synthesis of one illustrative example and two isps, including an industrial one (tdy-43). in comparison with other related approaches, our approach achieves higher throughput and provides a systematic way to explore the hardware/software trade-off.  ing-jer huang
provably correct high-level timing analysis without path sensitization  this paper addresses the problem of true delay estimation during high level design. the existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive.  we show that the paths in the implementation of a behavioral specification can be partitioned into two sets, sp and up. while the paths in sp can affect the delay of the circuit, the paths in up cannot. consequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in sp, eliminating the need for the computationally intensive process of path sensitization. experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation becomes computationally infeasible. the high-level delay estimates are verified by comparing with delay estimates obtained by gate-level timing analysis on the actual implementation.  subhrajit bhattacharya sujit dey franc brglez
synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits  in this paper we apply recently developed necessary and sufficient conditions for robust path-delay-fault testability to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. for circuits which can be flattened to two levels, we give a covering procedure which optimizes for robust path delay fault testability. these two-level circuits can then be algebraically factored to produce robustly path- delay-fault testable multilevel circuits. for regular structures which cannot be flattened to two levels, we give a composition procedure which allows for the construction of robustly path- delay-fault testable regular structures. finally, we show how these two techniques can be combined to produce cascaded combinational logic blocks that are robustly path-delay-fault testable. we demonstrate these techniques on a variety of examples. it is possible to produce entire chips that are fully path delay testable using these techniques.  srinivas devadas kurt keutzer
parameterized schematics  this paper presents a design capture system that allows parameterized schematics and code to be intermixed freely to produce annotated net lists. a key feature of the system is its extensibility. it provides a small set of powerful abstractions for design description that can easily be extended by users. the system also allows convenient graphical specification of layout generators, and has been used to produce several large vlsi chips.  richard barth bertrand serlet pradeep sindhu
low-power micromachined microsystems (invited talk)  micromachined microsystems and micro electro mechanical systems (mems) have made possible the development of highly accurate and portable sensors and instrument for a variety of applications in the health care, industrial, consumer products, avionics, and defense. design of low-power circuits for these applications, and use of micromachined sensors and actuators in combination with integrated circuits to implement even lower power microinstruments has now become possible and the focus of attention. this paper reviews the state of the art in the development of micromachined microsystems and mems, discusses low-power design approaches for microsystems, and reviews some recent development in power generation and energy harvesting from the environment.  khalil najafi
"cool low power" 1ghz multi-port register file and dynamic latch in 1.8 v,0.25 m soi and bulk technology (poster session)this paper describes power analysis at sub-zero temperatures for a highperformance dynamic multiport register file (6 read and 2 write ports, 32wordlines x 64 bitlines) fabricated in 0.25 μm silicon on insulator (soi) andbulk technologies. based on the hardware it is shown that the performance ofboth register file and latch improves by 2-3.5% per 10Â c reduction intemperature. the standby power for soi reduces by 1.5% to 3per 10Â ctemperature drop down to -30Â c. the soi chip is shown to havemore significantperformance improvement at low temperatures compared tobulk chip due to thefloating body effect which partially offsets the increase in the thresholdvoltages (vt). the low temperature performance gain is attributed to reductionin capacitance (around 7-8%) and rest is due to dynamic threshold voltages. at30Â c the register file is capable of functioning close to 1.02 ghz for readand write operations in a single cycle.r. v. joshi w. hwang s. c. wilson c. t. chuang
bias boosting technique for a 1.9ghz class ab rf amplifier  a bias boosting technique for a 3.2v, 1.9ghz class ab rf amplifier designed in a 30ghz bicmos process is presented in this paper. in a class ab amplifier, the average current drawn from the supply depends on the input signal level. as the output power increases so does the average currents in both the emitter and the base of the power transistor. the increased average current causes an increased voltage drop in the biasing circuitry and the ballast resistor. this reduces the conduction angle in the amplifier, pushing it deep into class b and even class c operation, reducing the maximum output power by 25%. to avoid the power reduction, the amplifier should have a larger bias which inevitably has a larger power dissipation at low output power levels. the proposed bias boosting circuitry dynamically increases the bias of the power transistor as the output power increases. the amplifier has less power dissipation at low power levels with an increased maximum output power.  tirdad sowlati sifen luo
a customized control store design in microprogrammed control units  the paper reports on the control store cost minimization using an approach related to the bit reduction method. a methodology is presented for finding the microinstruction format which provides a minimum joint cost of the control store and microinstruction decoder circuitry for a given set of microprograms. the optimization criterion measures the area taken by the control store and decoders in a large scale integrated circuit. the methodology is based on the concepts of codable microoperation classes and microoperation class distributivity introduced in the paper. the codable classes are those that provide the length reduction of the microinstruction field used for binary encoding microoperation combinations, compared to the single bit/microoperation encoding method. microoperation class properties and basic types of fields assignments in microinstruction word formats for codable class approach are also discussed.  m. s. tudruj
efficiently supporting fault-tolerance in fpgas  while system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for fpga-based systems that comes at a reduced cost in terms of design time, volume, and weight. we partition the physical design into a set of tiles. in response to a component failure, we capitalize on the unique reconfiguration capabilities of fpgas and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. unlike fixed structure fault-tolerance techniques for asics and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. experimental results conducted on a subset of the mcnc benchmarks demonstrate a high level of realiability with low timing and hardware overhead.  john lach william h. mangione-smith miodrag potkonjak