waashk/acm huggingface dataset:
performing remote operations efficiently on a local computer network  this paper discusses communication among computers connected by a very high speed local network and focuses on ways to support distributed programs that require efficient interprocessor communication. it is motivated by the availability of increasingly high speed local networks and inefficiencies in existing communication subsystems.  mechanisms such as remote procedure calls, monitor calls, and message passing primitives are bases for interprocessor communication at high levels (i.e., within a programming language). at lower levels, interprocessor communication occurs via the transmission of data over some communication medium. on a local network, this basic communication mechanism is the transmission of packets.  this paper is concerned with an intermediate communication layer for high speed local networks. to provide overall efficiency, this layer should provide communication primitives that (1) are a good basis on which to implement high level primitives and (2) are specialized enough to be implemented efficiently; for example, in a combination of microcode and hardware.  to analyze communication primitives for this intermediate layer, we present a communication model called the remote reference/remote operation model in which a taxonomy of communication primitives is defined. we illustrate the model by describing an implementation of simple communication primitives on xerox alto computers interconnected with a 3 megabit ethernet.  alfred z. spector
a unified vector/scalar floating-point architecture  in this paper we present a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. the goal of this architecture is to yield improved scalar performance while broadening the range of vectorizable applications. for example, reduction operations and recurrences can be expressed in vector form in this architecture. this approach results in greater overall performance for most applications than does the approach of emphasizing peak vector performance. the hardware required to support the enhanced vector capability is insignificant, but allows the execution of two operations per cycle for vectorized code. moreover, the size of the unified vector/scalar register file required for peak performance is an order of magnitude smaller than traditional vector register files, allowing efficient on-chip vlsi implementation. the results of simulations of the livermore loops and linpack using this architecture are presented.  n. p. jouppi j. bertoni d. w. wall
bidirectional token flow system  over the last few years there has been an avalanche of technical literature on techniques for allowing nodes to access and share one of the most valuable resources of a computer communication network, i.e., the bandwidth of the communication media.1 this report describes the design of a new type of local area computer network called bid that uses a bidirectional token flow as a form of token passing.2 the design of bid not only allows it to process messages having various properties but also makes it possible to operate simultaneously in a packet and circuit- switching mode. this latter mode, using minipackets, enables bid to be used for those applications having real- time response requirements.  in describing bid this report defines the basic concepts of the implicit token, token carrier, token generator, and token wait time. it also describes a new preemption technique which reduces the walk time normally associated with token and polling systems.  a gpss computer simulation was made of the bid system to determine the average delay times experienced by the various priority classes of messages. an analytical model using a single priority class of messages is presented, and the results of the computer simulation are compared with this. the simulation results also indicate the uniformity of the average delays experienced by the bus interface units across the bus resulting from the use of bidirectional flow of tokens.  m. e. ulug g. m. white w. j. adams
connection closures adding application-defined behaviour to network connections new techniques in the implementation of out-of-band control in atm networks are causing both industry and research laboratories to look again at the whole question of atm signalling. these techniques devolve the control from the network devices into a higher level distributed processing environment, resulting in simpler network devices and more flexible control architectures.this paper takes this idea one stage further and suggests that at least in some cases, the only place in which control can be exerted without inhibiting applications is within the applications themselves. we call the combination of an application defined control policy and a network connection a _connection closure_. s. rooney
towards a unifying approach to mobile computing in this paper we address the diversity of mobile devices and the related problematic issues with a largely platform-independent approach to development. our work is motivated by the amount and variety of mobile devices foreseen to reside in future ubiquitous computing environments. to reduce the development effort and to augment data exchange facilities, we present an application framework that abstractly defines common interaction objects in user interfaces on mobile devices. carsten magerkurth thorsten prante
pc-cube, a personal computer based hypercube  pc-cube is an ensemble of ibm pcs or close compatibles connected in the hypercube topology with ordinary computer cables. communication occurs at the rate of 115.2 k-baud via the rs-232 serial links. available for pc-cube is the crystalline operating system iii (cros iii), mercury operating system, cubix and plotix which are parallel i/o and graphics libraries. a cros performance monitor was developed to facilitate the measurement of communication and computation time of a program and their effects on performance. also available are cxlisp, a parallel version of the xlisp interpreter; grafix, some graphics routines for the ega and cga; and a general execution profiler for determining execution time spent by program subroutines. pc-cube provides a programming environment similar to all hypercube systems running cros iii, mercury and cubix. in addition, every node (personal computer) has its own graphics display monitor and storage devices. these allow data to be displayed or stored at every processor, which has much instructional value and enables easier debugging of applications. some application programs which are taken from the book solving problems on concurrent processors [fox 88] were implemented with graphics enhancement on pc-cube. the applications range from solving the mandelbrot set, laplace equation, wave equation, long range force interaction, to wa-tor, an ecological simulation.  a. ho g. c. fox d. w. walker s. snyder d. chang s. chen m. breaden t. cole
a run time support system for multiprocessor machines  we report on the design and development of a run time support system (rts) which overcomes known disadvantages of other existing systems. the rts is independent of the configuration - if the system is reconfigured there is no need to change user's processes. it supports both synchronous and asynchronous communication.  a system based on the same design philosophy with this rts is actually implemented for messages of arbitrary length in the prototype of the padmavati machine, being developed within esprit project 1219 (967). experiments were conducted in this environment and performance measurements were obtained and are reported here.  m. a. tsoukarellas t. s. papatheodorou
rate analysis for embedded systems  embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative time separation of the components. in this article, we model an embedded system using concurrent processes interacting through synchronization. we assume that there are rate constraints on the execution rates of processes imposed by the designer or the environment of the system, where the execution rate of a process is the number of its executions per unit time. we address the problem of computing bounds on the execution rates of processes constituting an embedded system, and propose an interactive rate analysis framework. as part of the rate analysis framework we present an efficient algorithms for checking the consistency of the rate constraints. bounds on the execution rate of each process are computed using an efficient algorithm based on the relationship between the execution rate of a process and the maximum mean delay cycles in the process graph. finally, if the computed rates violate some of the rate constraints, some of the processes in the system are redesigned using information from the rate analysis step. this rate analysis framework is implemented in a tool called ratan. we illustrate by an example how ratan can be used in an embedded system design.  anmol mathur ali dasdan rajesh k. gupta
architectural and protocol frameworks for multicast data transport in multi- service networks the paper presents architectural and protocol techniques for multicast transport of multi-service data (such as video, audio and graphics). a tree-structured channel in the network is employed as building block for constructing multicast transport services. data from different sources are multiplexed over a shared tree channel for reaching destinations through intermediate network nodes and links. the choice of multicast architecture is based on the extent of sharing of common links in a tree across multi-source data flows to allow finer degree of link bandwidth allocation control and reduce the fixed cost of links for data transport. the canonical network substrate so constructed exemplifies a 'programmable network' that may be 'plugged-in' with qos and flow parameters to instantiate the network behavior for matching the needs of each application. this philosophy is in alignment with the evolving 'internet service layer' functionalities. the paper describes the functional and protocol elements of multicast architectures to support the 'programmable network' view. it also describes the salient features of an implementation embedding these architectures. k. ravindran
algorithms for energy-efficient multicasting in static ad hoc wireless networks  in this paper we address the problem of multicasting in ad hoc wireless networks from the viewpoint of energy efficiency. we discuss the impact of hte wireless medium on the multicasting problem and the fundamental trade-offs that arise. we propose and evaluate several algorithms for defining multicast trees for session (or connection-oriented) traffic when transceiver resources are limited. the algorithms select the relay nodes and the corresponding transmission power levels, and achieve different degrees of scalability and performance. we demonstrate that the incorporation of energy considerations into multicast algorithms can, indeed, result in improved energy efficiency.  jeffrey e. wieselthier gam d. nguyen anthony ephremides
a multi-user data flow architecture  this paper discusses the design of a prototype data flow machine that has memory management hardware in each memory block. this facility allows loading and deleting code that is produced by independent compilations. the first sections of the paper deal with the general architecture of the machine and the format specifications for the instruction cells, logical addresses, and switch packets. the paper concludes with a discussion of the mapping hardware used in the memory blocks. the results of a simulation study for this subsystem are also presented.  f. j. burkowski
quality of service over ethernet for telelearning applications the objective of this investigation is to implement a technology that provides measurements of quality of service (qos) of established local area networks. improvements of the required infrastructure for applications of telelearning (videoconference, electronic blackboard, shared applications…) are implemented with a minimal cost. we are implementing features of atm on ethernet local area networks, through the protocol "cells in frame" (cif). this protocol encapsulates atm cells in ethernet frames using cif specification. values of measured parameters reveal that the implementation provides the atm quality of service necessary for telelearning traffic type. j. m. arco b. alarcos a. m. hellín d. meziat
spread - sprectrum cdma packet radio mac protocol using channel overload detection and blocking  an analytical and simulation performance evaluation is presented for a multi - access protocol for a data packet radio network with a limited user capacity. the network employs direct - sequence code division multiple access ds - cdma in a centralised channel load - sensing scheme with channel overload collision detection and blocking via a separate ancillary channel state information broadcast system. traffic models that incorporate both a finite population and an infinite population and variable length data messages are considered. results show that an improved throughput delay performance can be obtained by implementing a channel overload detection message dropping scheme as well as a channel overload avoidance message blocking scheme. the channel overload threshold β is fixed at the system's maximum user capacity whereas it is shown that the overload avoidance blocking threshold should be variable and dependent on the mean message arrival rate.  garth judge fambirai takawira
simple constant-time consensus protocols in realistic failure models  using simple protocols, it is shown how to achieve consensus in constant expected time, within a variety of fail-stop and omission failure models. significantly, the strongest models considered are completely asynchronous. all of the results are based on distributively flipping a coin, which is usable by a significant majority of the processors. finally, a nearly matching lower bound is also given for randomized protocols for consensus.  benny chor michael merritt david b. shmoys
the 801 minicomputer  this paper provides an overview of an experimental system developed at the ibm t. j. watson research center. it consists of a running hardware prototype, a control program and an optimizing compiler. the basic concepts underlying the system are discussed as are the performance characteristics of the prototype. in particular, three principles are examined:  system orientation towards the pervasive use of high level language programming and a sophisticated compiler,  a primitive instruction set which can be completely hard- wired,  storage hierarchy and i/o organization to enable the cpu to execute an instruction at almost every cycle.  george radin
a network environment for computer-supported cooperative work  a second generation computer supported cooperative work system called electronic information exchange system (eies2) is described in this paper. the eies2 communications environment allows users to network across geographical constraints using asynchronous or synchronous communications. the architecture of the network environment is decentralized, and is implemented using modern standards, and an easy-to-use user interface.  at the heart of eies2 is a high-level, object oriented pseudo machine which incorporates a distributed, communications-oriented database.  the set of tools provided by the eies2 communications environment is well suited for implementing group communication systems that have an extensive set of user features built into it. these tools are well suited to support the group communication model described by the amigo task force (ifip 6.5 and iso tc97/sc18/wg64). the eies2 application layer protocols, using ccitt/iso x.410 remote operations, support a distributed object oriented database.  j. whitescarver p. mukherji m. turoff r. j. deblock r. m. czech b. k. paul
modelling and performance evaluation of multiprocessor based packet switches  this paper presents an approximate analytic model for the performance analysis of a class of multiprocessor based packet switches. for these systems, processors and common memory modules are grouped in clusters, each of them composed of several processor-memory pairs that communicate through a multiple bus interconnection network. intercluster communication is also achieved using one or more busses. the whole network operates in a circuit- switched mode.  after access completion, a processor remains active for an exponentially distributed random time. access times are also exponential with different means, depending upon the location (local, cluster, external) of the referenced module. the arbitration is done on a priority basis.  the performance is predicted by computing the average number of switched packets per time unit. other related indexes are also given. numerical results are obtained rather easily by solving a set of two algebraic equations. simulation is used to validate the accuracy of the approximations used in the model.  j. l. melús e. sanvicente j. magriñá
towards a new standard for system-level design  huge new design challenges for system-on-chip (soc) are the result of decreasing time- to-market coupled with rapidly increasing gate counts and embedded software representing 50-90 percent of the functionality. the exchange of system-level intellectual property (ip) models for creating executable specifications has become a key strategic element for efficient system-to-silicon design flows. because c and c++ are the dominant languages used by chip architects, systems engineers and software engineers today, we believe that a c-based approach to hardware modeling is necessary. this will enable co-design, providing a more natural solution to partitioning functionality between hardware and software. in this paper we present the design of systemc, a c++ class library that provides the necessary features for modeling design hierarchy, concurrency, and reactivity in hardware. we will also describe experiences of using systemc 1) for the co-verification of 8051 processor with a bus-functional model and 2) for the modeling and simulation of an mpeg-2 video decoder.  stan y. liao
a system for constructing configurable high-level protocols new distributed computing applications are driving the development of more specialized protocols, as well as demanding greater control over the communication substrate. here, a network subsystem that supports modular, fine-grained construction of high-level protocols such as atomic multicast and group rpc is described. the approach is based on extending the standard hierarchical model of the _x_-kernel with composite protocols in which micro- protocol objects are composed within a standard runtime framework. each micro- protocol realizes a separate semantic property, leading to a highly modular and configurable implementation. in contrast with similar systems, this approach provides finer granularity and more flexible inter-object communication. the design and prototype implementation runing on mach are described. performance results are also given for a micro-protocol suite implementing variants of group rpc. nina t. bhatti richard d. schlichting
questions for local area network panelists  much has been written and spoken about the capabilities of emerging designs for local area networks (lan's). the objective for this panel session was to gather together companies and agencies that have brought lan's into operation. questions about the performance of lans have piqued the curiosity of the computer/communications community.  each member of the panel briefly described his or her lan installation and workload as a means of introduction to the audience. questions about performance were arranged into a sequence by performance attributes. those attributes thought to be of greatest important were discussed first. discussion on the remainder of the attributes continued as time and audience interaction permitted.  mitchell g. spiegel
a routing architecture for mobile integrated services networks  a drawback of the conventional internet routing architecture is that its route computation and packet forwarding mechanisms are poorly integrated with congestion control mechanisms. any datagram offered to the network is accepted; routers forward packets on a best-effort basis and react to congestion only after the network resources have already been wasted. a number of proposals improve on this to support multimedia applications; a promising example is the integrated services packet network (ispn) architecture. however, these proposals are oriented to networks with fairly static topologies and rely on the same conventional internet routing protocols to operate. this paper presents a routing architecture for mobile integrated services networks in which network nodes (routers) can move constantly while providing end-to-end performance guarantees. in the proposed connectionless routing architecture, packets are individually routed towards their destinations on a hop by hop basis. a packet intended for a given destination is allowed to enter the network if and only if there is at least one path of routers with enough resources to ensure its delivery within a finite time. once a packet is accepted into the network, it is delivered to its destination, unless resource failures prevent it. each router reserves resources for each active destination, rather than for each source-- destination session, and forwards a received packet along one of multiple loop-free paths towards the destination. the resources and available paths for each destination are updated to adapt to congestion and topology changes. this mechanism could be extended to aggregate dissimilar flows as well.  shree murthy j. j. garcia-luna-aceves
multimedia, network protocols and users - bridging the gap  in this paper we present the case for using specifically configured protocol stacks geared towards human requirements in the delivery of distributed multimedia. we define quality of perception (qop) as representing the user side of the more technical and traditional quality of service (qos). qop is a term which encompasses not only a user's satisfaction with the quality of multimedia presentations, but also his/her ability to analyse, synthesise and assimilate the informational content of multimedia displays. the dynamically reconfigurable protocol stacks (drops) architecture supports low cost reconfiguration of individual protocol mechanisms in an attempt to best maintain qop in connections where the provided qos fluctuates unpredictably. results show that drops can be used to improve on the qop provided by legacy protocol stacks (tcp/ip, udp/ip), especially in the case of dynamic and complex sequences.  g. ghinea j. p. thomas r. s. fish