waashk/acm huggingface dataset:
the application of genetic algorithms to the design of reconfigurable reasoning vlsi chips  in this paper, we present a new genetic- algorithm-based design methodology for reasoning vlsi chips, called as lodett (logic design with the evolved truth table). in lodett, each task's case database is transformed into truth tables, which are evolved to obtain generalization capability (i.e. rules behind the past cases) through genetic algorithms. digital circuits are synthesized from the evolved truth-tables. parallelism in each task can be embedded directly in the circuits by the direct hardware implementation of the case database. we applied lodett to the english pronunciation reasoning (epr) problem, resulting in a gatalk chip. a gatalk chip has been designed with about 270k gates, and its reasoning time is about 100 ns for each phoneme. a prototype of the gatalk chip has been implemented using xilinx xc4010 fpga chips. it achieved a reasoning accuracy of 81.9% which is almost the same accuracy as nettalk in neural networks and mbrtalk in parallel ai.  moritoshi yasunaga jung hwan kim ikuo yoshihara
allende: a procedural language for the hierarchical specification of vlsi layouts  allende is a simple and powerful procedural language for vlsi layout. in allende the layout is described hierarchically as a composition of cells; absolute sizes or positions are never specified. the layout description is translated into linear constraints, which express design rules and relative position of the layout elements. by solving these constraints we obtain the absolute layout, which is guaranteed to be free of design rule violations. errors in the layout description are immediately detected and easily located.  allende consists of five procedures to be called from a pascal or c program. a lot of parameterization is possible when specifying layout elements, besides the ability to make use of the full power of pascal or c. the allende system has been implemented for the nmos technology.  jose monteiro de mata
factoring large numbers with programmable hardware  most advanced forms of security for electronic transactions rely on the public-key cryptosystems developed by rivest, shamir and adleman. unfortunately, these systems are only secure while it remains difficult to factor large integers. the fastest published algorithms for factoring large numbers have a common sieving step. these sieves collect numbers that are completely factored by a set of prime numbers that are known in advance. furthermore, the time required to execute these sieves currently dominates the runtime of the factoring algorithms. we show how the sieving process can be mapped to the mojave configurable computing architecture. the mapping exploits unique properties of the sieving algorithms to fully utilize the bandwidth of a multiple bank interleaved memory system. the sieve has been mapped to a single programmable hardware unit on the mojave computer, and achieves a clock frequency of 16 mhz. the full system implementation sieves over 28 times faster than an ultrasparc workstation. a simple upgrade to 8ns srams will result in a speedup factor of 160.  hea joung kim william h. mangione-smith
energy estimation for 32-bit microprocessors  estimation of software power consumption is becoming one of the major problems for many embedded applications. the paper presents a novel approach to compute the energy of an instruction set, through a suitable functional decomposition of the activities involved during instruction execution. one of the main advantages of this approach is the capability to predict the power figures of the overall instruction-set starting from a small subset. a formal discussion on the statistical properties of the model is included, together with its application on five commercial 32-bit microprocessors.  c. brandolese w. fornaciari f. salice d. sciuto
field programmable port extender (fpx) for distributed routing and queuing  field programmable gate arrays (fpgas) are being used to provide fast internet protocol (ip) packet routing and advanced queuing in a highly scalable network switch. a new module, called the field-programmable port extender (fpx), is being built to augment the washington university gigabit switch (wugs) with reprogrammable logic.  fpx modules reside at the edge of the wugs switching fabric. physically, the module is inserted between an optical line card and the wugs gigabit switch back-plane. the hardware used for this project allows ports of the switch populated with an fpx to operate at rates up to 2.4 gigabits/second. the aggregate throughput of the system scales with the number of switch ports.  logic on the fpx module is implemented with two fpga devices. the first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. the logic on the second fpga can be reprogrammed dynamically via control cells sent over the network.  the flexibility of the fpx has made the card of interest for several networking applications. this year, fifty fpx hardware modules will be fabricated and distributed to researchers at eight universities around the country who are interested in experimenting with reprogrammable networks and per-flow queuing mechanisms. the fpx hardware will first be used to implement fast ip lookup algorithms and distributed input queueing.  john w. lockwood jon s. turner david e. taylor
simultaneous driver and wire sizing for performance and power optimization  in this paper, we study the simultaneous driver and wire sizing (sdws) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipation minimization. we present general formulations of the sdws problem under these two objectives based on the distributed elmore delay model with consideration of both capacitive power dissipation and short- circuit power dissipation. we show several interesting properties of the optimal sdws solutions under the two objectives, including an important result (theorem 3) which reveals the relationship between driver sizing and optimal wire sizing. these results lead to polynomial time algorithms for computing the lower and upper bounds of optimal sdws solutions under the two objectives, and efficient algorithms for computing optimal sdws solutions under the two objectives. we have implemented these algorithms and compared them with existing design methods for driver sizing only or independent driver and wire sizing. accurate spice simulations shows that our methods reduce the delay by up to 11%--47% and power dissipation by 26%--63% compared with existing design methods.  jason cong cheng-kok koh
rule-based vlsi verification system constrained by layout parasitics  this paper addresses a rule-based method for vlsi design review, constrained by parasitics. using the new ideas discussed in this paper, extraction from layout is not limited anymore to conventional electrical data, but additionally allows modelling of functional and timing behaviour. an extendable rule based validation algorithm operates on extracted models, decorated with parasitic effects, to formally prove most aspects of design correctness.  j. wenin j. verhasselt m. van camp j. leonard p. guebels
on modeling top-down vlsi design  we present an improved data model that reflects the whole vlsi design process including bottom-up and top-down design phases. the kernel of the model is a static version concept that describes the convergence of a design. the design history which makes the semantics of most other version concepts, is modeled explicitly by additional object classes (entities types) but not by the version graph itself. top-down steps are modeled by splitting a design object into requirements and realizations. the composition hierarchy is expressed by a simple but powerful configuration method. design data of iterative refinement processes are managed efficiently by storing incremental data only.  bernd schurmann joachim altmeyer martin schutze
low power state assignment targeting two-and multi-level logic implementations  the problem of minimizing power consumption during the state encoding of a finite state machine is considered. a new power cost model for state encoding is proposed and encoding techniques that minimize this power cost for two- and multi-level logic implementations are described. these techniques are compared with those which minimize area or the switching activity at the present state bits. experimental results show significant improvements.  chi-ying tsui massoud pedram chih-ang chen alvin m. despain
ibm fsd vlsi chip design methodology  the ibm corporation's federal systems division (fsd) has designed, developed and implemented a vlsi design methodology selected specifically for the dod's design environment. the military industry vlsi requirements and ibm fsd's design system goals for developing chip design methodology are described. substantial reduction in computer costs and design schedule using the methodology and the design system components is demonstrated. the rationale behind selecting the specific combination of tools, from the many design systems in ibm, for forming the fsd chip design system and the methodology is explained.  k. ahdoot r. alvarodiaz l. crawley
optimal layout to avoid cmos stuck-open faults  a set of layout rules is presented to cope with cmos stuck-open faults by a design for testability at the layout-level. in applying these rules, open connections may either be avoided or their effects can be described by an easily detectable type of open faults known from cmos inverters and nmos logic. hence, remaining open faults are usually covered by a complete stuck-at test pattern set.  s. koeppe
an efficient technique for device and interconnect optimization in deep submicron designs  in this paper, we formulate a new class of optimization problem, named the general ch-posynomial program, and reveal the general dominance property. we propose an efficient algorithm based on the extended local refinement operation to compute lower and upper bounds of the exact solution to the general ch-posynomial program. we apply the algorithm to solve the simultaneous transistor and interconnect sizing (stis) problem under the table-based device model, and the global interconnect sizing and spacing (giss) problem with consideration of the crosstalk capacitance. experiment results show that our algorithm can handle many device and interconnect modeling issues in deep submicron designs and is very efficient.  jason cong lei he
effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization  this paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. the assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. we focus on control-flow intensive descriptions, characterized by the presence of mutually exclusive paths due to the presence of nested conditional branches and loops.  we show that clustering multiple operations in the same state of the schedule, possibly leading to chaining of functional units (fus) in the rtl circuit, is an effective way to minimize the total number of clock cycles, and hence total execution time. we present an assignment algorithm that is particularly effective for such design styles by minimizing data chaining and hence the clock period of the circuit, thereby leading to further reduction in total execution time.  existing resource sharing and assignment approaches for reducing the clock period of the resulting circuit either increase the resource allocation or use faster modules, both leading to leading to larger area requirements. in this paper we show that even when the type of available resource units and the number of resource units of each type is fixed, different assignments may lead to circuits with significant differences in clock period.  we provide a comprehensive analysis of how resource sharing and assignment introduces long paths in the circuit. based on the analysis, we develop an assignment algorithm that uses a high-level delay estimator to asign operations to a fixed set of available resources so as to minimize the clock period of the resultant circuit, with no or minimal effect on the area of the circuit. experimental results on several conditional-intensive designs demonstrate the effectiveness of the assignment algorithm.  subhrajit bhattacharya sujit dey franc breglez
decomposition of logic networks into silicon  this paper describes a module compiler for decomposing arbitrary functional units of any complexity into abstract cells for customized vlsi layouts. the compiler takes the description of a functional unit as input and builds a dependence graph representation. the graph is then partitioned and the nodes are packed into abstract cell output descriptions. the algorithm will tailor the design to a given area and aspect ratio. routing is done automatically through the cells.  steven t. healey daniel d. gajski
mild - a cell-based layout system for mos-lsi  a standard-cell-based layout system for mos-lsi termed mild is reported. mild has several features which seem to be profitable from the practical viewpoint of lsi developers; one of them is that macro blocks such as memory cells can be contained in the chip laid out.  koji sato takao nagai mikio tachibana hiroyoshi shimoyama masaru ozaki toshihiko yahara
adding content-based searching to a traditional music library catalogue server  most online music library catalogues can only be searched by textual m etadata. whilst highly effective - since the rules for maintaining consistency have been refined over many years - this does not allow searching by musical content. many music librarians are familiar with users humming their enquiries. most systems providing a "query by humming&amp;r; dquo; interface tend to run independently of music library catalogue systems and not offer similar textual metadata searching. this paper discusses the ongoing investigative work on integrating these two types of system conducted as part of the nsf/jisc funded omras project (http://www.omras.org).  matthew j. dovey
data modeling: order out of chaos  data modeling, in a sense, is an attempt to bring order out of chaos. the data requirements of a system normally consist of an unstructured collection of various types of data descriptions. the aim is to produce from these an understandable, precise, and complete representation of the data requirements. the field of data modeling itself, however, is not so orderly. even a satisfactory definition of the term is hard to find. the different data modeling methodologies seem as numerous and diverse as the situations to be modeled. categorizing them is difficult as well. the paper will present a sampling of the data modeling methodologies currently in use and suggest some possible categorizations.  carolyn budinger seaman
design and technology for collaborage: collaborative collages of information on physical walls  a collaborage is a collaborative collage of physically represented information on a surface that is connected with electronic information, such as a physical in/out board connected to a people-locator database. the physical surface (board) contains items that are tracked by camera and computer vision technology. events on the board trigger electronic services. this paper motivates this concept, presents three different applications, describes the system architecture and component technologies, and discusses several design issues.  thomas p. moran eric saund william van melle anuj u. gujar kenneth p. fishkin beverly l. harrison
cumulating and sharing end users knowledge to improve video indexing in a video digital library  in this paper, we focus on a user driven approach to improve video ind exing. it consists in cumulating the large amount of small, individual efforts done by the users who access information, and to provide a community management mechanism to let users share the elicited knowledge. this technique is currently being developed in the "opales" environment and tuned up at the "institut national de l'audiovisuel&amp;r; dquo;(ina), a national video library in paris, to increase the value of its patrimonial video archive collections. it relies on a portal providing private workspaces to end users, so that a large part of their work can be shared between them. the effort for interpreting documents is directly done by the expert users who work for their own job on the archives. opales provides an original notion of "point of view" to enable the elicitation and the sharing of knowledge between communities of users, without leading to messy structures. the overall result consists in linking exportable private metadata to archive documents and managing the sharing of the elicited knowledge between users communities.  provide bring together the leaders developing the national smete digital library to provide a brief background and broad overview of the nsdl program. panelists will discuss the overall vision and broad steps underway to develop the national smete digital library.  building the national smete digital library presents many challenges:  developing a shared vision for the form and function of the nsdl;  meeting the needs of diverse learners and of the many disciplines encompassed by the nsdl;  acquiring input from the community of users to ensure that the nsdl is both used and useable;  evaluating progress and impacts;  integrating technologies that already exist, and the development of new technologies; and  providing mechanisms for sharing and cooperation of knowledge and resources among nsdl collaborators.  marc nanard jocelyne nanard
an adaptive real-time web search engine  the internet provides a wealth of information scattered all over the world. the fact that the information may be located anywhere makes it both convenient for placing information on the web and difficult for others to find. conventional search engines can only locate information that is in their search index and users do not have much choice in limiting or expanding the search parameters. some web pages like those for news services change frequently and will not work well with index based search engines because the indexed information may become obsolete at any moment.  we are proposing an efficient algorithm for finding information on the web that gives the user greater control over the search path and what to search for. unlike the conventional techniques, our algorithm does not use an index and works in real time. we save on space, we can search any part of the internet indicated by the user, and since the search is in real time, the result will be current.  augustine chidi ikeji farshad fotouhi
the changing face of information retrieval systems  information retrieval is a fundamental capability of computers, of whatever size and type. what distinguishes one computer's retrieval performance from another's, from the standpoint of the user, are such factors as: the number and sizes of files that can be handled; the number and types of access points available to the user; the number, types, and sophistication of the search features provided; the number and kinds of error-correction, tutorial, and other user-help features available; the speed with which the system performs all of its functions; and the knowledge and skill required for successful use of the system. all of these, of course, are very dependent on the retrieval software, as well as on the computer per se.  since their beginnings in the 1950s, information retrieval systems have improved steadily---and often dramatically---in capacity, responsiveness, cost-effectiveness, and user- friendliness. multi-user online access, which was just beginning to come into view about 20 years ago, has almost completely supplanted batch processing as the standard means of searching machine- readable files, a change that has been accelerated by the establishment and success of many commercial online retrieval service bureaus. according to the most recent issue of the directory of online databases, more than 150 computer service bureaus are providing online access to over 870 databases, at the present time. some of these databases contain millions of records and require billions of bytes of online storage.  carlos a. cuadra
event tracking based on domain dependency  this paper proposes a method for event tracking on broadcast news stories based on distinction between a topic and an event. a topic and an event are identified using a simple criterion called domain dependency of words: how greatly a word features a given set of data. the method was tested on the tdt corpus which has been developed by the tdt pilot study and the result can be regarded as promising the usefulness of the method.  fumiyo fukumoto yoshimi suzuki
set oriented retrieval  the broad way in which we look at how an irs functions influences the types of questions we ask about it and the ways we try to improve performance. in the recent past, retrieval methodologies have been based on retrieving documents one at a time. in this paper we are introducing a set oriented view. we observe that this view is quite consistent with the single-document or sequential methods, and define a precise model to capture the set-oriented approach. we then examine a number consequences of the model, such as the limitations implied by a finite index vocabulary. finally, we discuss various ways in which the set orientation can influence our thinking about ir.  a. bookstein
algorithms for creating indexes for very large tables without quiescing updates  as relational dbmss become more and more popular and as organizations grow, the sizes of individual tables are increasing dramatically. unfortunately, current dbmss do not allow updates to be performed on a table while an index (e.g., a b+-tree) is being built for that table, thereby decreasing the systems' availability. this paper describes two algorithms in order to relax this restriction. our emphasis has been to maximize concurrency, minimize overheads and cover all aspects of the problem. builds of both unique and nonunique indexes are handled correctly. we also describe techniques for making the index-build operations restartable, without loss of all work, in case a system failure were to interrupt the completion of the creation of the index. in this connection, we also present algorithms for making a long sort of operation restartable. these include algorithms for the sort and merge phases of sorting.  c. mohan inderpal narang
comparison of two information retrieval methods on videotex: tree-structure versus alphabetical directory  videotex systems are two-way communnication systems intended to give users access to large amounts of stored information from their homes and offices. these systems link computer databases to modified television sets over the telephone network. a central computer is used as a large information storage device, monitoring requests for information from several users at one time, finding and sending the information to the person who requested it.  it is possible however, that the addition of an inexpensive supplement to the hierarchical tree search will improve user search performance without substantially altering the cost-benefits of the menu selection approach. one such method of retrieval is the on-line alphabetical directory approach where users look for a search term from a list of alphabetically organized items by menu selection.  an example will indicate the difference between this method and a typical hierarchical search:  jo w. tombaugh scott a. mcewen