waashk/acm huggingface dataset:
multicast and multiprotocol support for atm based internets  both the internet engineering task force (ietf) and atm forum are addressing the issue of building higher layer networks using atm. the ietf's focus is on ip, while the atm forum has expanded its vision to include all common network layer protocols. the task faced by both organizations is to develop solutions that will cause minimal interoperability problems, both for users and network architects.  this paper focuses on the solutions coming out of the ietf's ip over atm working group, including the author's proposal for flexible, high performance ip multicast over atm. the emerging next hop resolution protocol from the ietf's routing over large cloud group is briefly examined, and its possible conflict with the atm forum's multiprotocol over atm'work is also discussed. the author finishes by noting how current ietf work could support 'multiprotocol' networks.  g. j. armitage
a fetch-and-op implementation for parallel computers  an efficient fetch-and-op circuit is described. a bit-serial circuit-switched implementation requires only 5 gates per node in a binary tree. this versatile circuit is also capable of test-and-set primitives (priority circuits) and swap operators, as well as and and or operations used in simd tests such as "branch on all carries set." it provides an alternative implementation for the combining fetch-and-add circuit to the one designed for the ultracomputer project; this implementation is suited to simd computing and can be adapted to mimd computing.  g. j. lipovski p. vaughan
the case for persistent-connection http the success of the world-wide web is largely due to the simplicity, hence ease of implementation, of the hypertext transfer protocol (http). http, however, makes inefficient use of network and server resources, and adds unnecessary latencies, by creating a new tcp connection for each request. modifications to http have been proposed that would transport multiple requests over each tcp connection. these modifications have led to debate over their actual impact on users, on servers, and on the network. this paper reports the results of log-driven simulations of several variants of the proposed modifications, which demonstrate the value of persistent connections. jeffrey c. mogul
a unified resource management and execution control mechanism for data flow machines  this paper presents a unified resource management and execution control mechanism for data flow machines. the mechanism integrates load control, depth-first execution control, cache memory control and a load balancing mechanism. all of these mechanisms are controlled by such basic information as the number of active state processes, na. in data flow machines, synchronization among processes is an essential hardware function. hence, na can easily be detected by the hardware.  load control and depth-first execution control make it possible to execute a program with a designated degree of parallelism, and depth-first order. a cache memory of data flow processors in multiprocessing environments can be realized by using load and depth-first execution controls together with a deterministic replacement algorithm, i.e. replacement of only waiting state processes. a new load balancing method called group load balancing is also presented to evaluate the above mentioned mechanisms in multiprocessor environments.  these unified control mechanisms are evaluated on a register transfer level simulator for a list-processing oriented data flow machine.  m. takesue
m3l: a list-directed architecture  this paper describes the basic principles and the architecture of a general host machine based upon lists processing. current works in this field are dealing with conventional direct execution schemes which use lineary structured directly executable languages: prefixed languages with varying formats for operators and operands. if these languages are convenient for interpretation and provide an efficient execution scheme, on the other hand, they are very hard to generate.  therefore, we propose here a new direct execution model based upon the definition of a class of directly executable languages with a list oriented structure using lisp as model. the first part of the scheme is held by an editor which translates the high level source-text into the internal tree- structured form. the second part is held by an interpreter which executes this form on an appropriate machine.  in this paper we pursue the design of the list-structured intermediate form and we give the reasons of our choice. once we have brought out the concepts and the functions required for the implementation of non-numerical processing and particularly for list-structured forms, we discuss the architecture of the lists-directed machine.  j. p. sansonnet m. castan c. percebois
design and performance of special purpose hardware for time warp  a special purpose simulation engine based on the time warp mechanism is proposed to attack large-scale discrete event simulation problems. a key component of this engine is the rollback chip, a hardware component that efficiently implements state saving and rollback functions in time warp. the algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. results of simulation studies are presented that show that the rollback chip can virtually eliminate the state saving overhead that plagues current software implementations of time warp.  r. m. fujimoto j.-j. tsai g. gopalakrishnan
improving call admission policies in wireless networks  it is well known that the call admission policy can have a big impact on the performance of a wireless network. however, the nonlinear dependence of new calls and handoff calls makes the search for a better call admission policy -- in terms of effective utilization -- a difficult task. many studies on optimal policies have not taken the correct dependence into consideration. as a result, the reported gains in those studies cannot be confirmed in a real network. in this paper we develop a solution to the problem of finding better call admission policies. the technique consists of three components. first, we search for the policy in an approximate reduced-complexity model. second, we modify the linear programming technique for the inherently nonlinear policy- search problem. third, we verify the performance of the found policy in the exact, high-complexity, analytical model. the results shown in the paper clearly demonstrate the effectiveness of the proposed technique.  chi-jui ho chin-tau lea
artificial synesthesia via sonification: a wearable augmented sensory system  a design for an implemented, prototype wearable artificial sensory system is presented, which uses data sonification to compensate for normal limitations in the human visual system. the system gives insight into the complete visible-light spectra from objects being seen by the user. long-term wear and consequent training might lead to identification of various visually- indistinguishable materials based on the sounds of their spectra. a detailed system design and results of user testing are presented, and many possible extensions to both the sonification and the sensor package are discussed.  leonard n. foner
mobile radio slotted aloha with capture, diversity and retransmission control in the presence of shadowing  in this paper, the capture performance of a random access scheme in the presence of rayleigh fading, shadowing and diversity is studied. the conditional throughput c_n, i.e., the average number of packets which are correctly received per slot, given the number of colliding packets, n, is computed, as well as its limit as n\to\infty. some different diversity schemes are compared. also, retransmission control is considered as a means to enhance the system performance. the stability of the controlled system is directly proved. finally, the effect of long-term attenuations on the system performance and stability is discussed.  michele zorzi
an architecture of a dataflow single chip processor  a highly parallel (more than a thousand) dataflow machine em-4 is now under development. the em-4 design principle is to construct a high performance computer using a compact architecture by overcoming several defects of dataflow machines. constructing the em-4, it is essential to fabricate a processing element (pe) on a single chip for reducing operation speed, system size, design complexity and cost. in the em-4, the pe , called emc-r, has been specially designed using a 50,000-gate gate array chip. this paper focuses on an architecture of the emc-r. the distinctive features of it are: a strongly connected arc dataflow model; a direct matching scheme; a risc-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular pipeline and a register-based advanced control pipeline. these features are intensively examined, and the instruction set architecture and the configuration architecture which exploit them are described.  s. sakai y. yamaguchi k. hiraki y. kodama t. yuba
topology-based tracking strategies for personal communication networks  this paper explores tracking strategies for mobile users in personal communication networks which are based on the topology of the cells. we introduce the notion of topology-based strategies in a very general form. in particular, the known paging areas, overlapping paging areas, reporting centers, and distance-based strategies are covered by this notion. we then compare two topology-based strategies with the time-based strategy on the line and mesh cell topology.  amotz bar-noy ilan kessler mahmoud naghshineh
comparison of dataflow control techniques in distributed data-intensive systems  in dataflow architectures, each dataflow node (i.e., operation) is typically executed on a single physical node. we are concerned with distributed data- intensive systems, in which each base (i.e., persistent) set of data has been declustered over many physical nodes to achieve load balancing. because of large base set size, each operation is executed where the base set resides, and intermediate results are transferred between physical nodes. in such systems, each dataflow node is typically executed on many physical nodes. furthermore, because computations are data- dependent, we cannot know until run time which subset of the physical nodes containing a particular base set will be involved in a given dataflow node. this uncertainty affects program loading, task activation and termination, and data transfer among the nodes.  in this paper we focus on the problem of how a dataflow node in such an environment knows when it has received data from all the physical nodes from which it is ever going to receive. we call this the dataflow control problem. the interesting part of the problem is trying to achieve correctness efficiently. we propose three solutions to this problem, and compare them quantitatively by the metrics of total message traffic, message system throughput and data transfer response time.  w. alexander g. copeland
clock rate versus ipc: the end of the road for conventional microarchitectures  the doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scali ng of the processor clock with technology generation. our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. in this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. using the results of these models, we measure the simulated performance---estimating both clock rate and ipc ---of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. we perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. we find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.  vikas agarwal m. s. hrishikesh stephen w. keckler doug burger
fast and scalable layer four switching in layer four switching, the route and resources allocated to a packet are determined by the destination address as well as other header fields of the packet such as source address, tcp and udp port numbers. layer four switching unifies firewall processing, rsvp style resource reservation filters, qos routing, and normal unicast and multicast forwarding into a single framework. in this framework, the forwarding database of a router consists of a potentially large number of filters on key header fields. a given packet header can match multiple filters, so each filter is given a cost, and the packet is forwarded using the _least cost matching filter_.in this paper, we describe two new algorithms for solving the least cost matching filter problem at high speeds. our first algorithm is based on a grid-of-tries construction and works optimally for processing filters consisting of two prefix fields (such as destination-source filters) using linear space. our second algorithm, cross-producting, provides fast lookup times for arbitrary filters but potentially requires large storage. we describe a combination scheme that combines the advantages of both schemes. the combination scheme can be optimized to handle pure destination prefix filters in 4 memory accesses, destination-source filters in 8 memory accesses worst case, and all other filters in 11 memory accesses in the typical case. v. srinivasan g. varghese s. suri m. waldvogel
type of service wide area networking  there are a variety of long distance types of circuits that can be used for data communication. this paper describes an experiment which optimizes the simultaneous use of terrestrial and satellite circuits in a tcp/ip network. traditionally, there have been problems effectively using the full capacity of high bandwidth satellite circuits, due to long round trip times coupled with tcp window-size limitations. the experiment significantly reduced the problem, and the result was effective use of all the available bandwidth of a satellite circuit for a single data transfer. this experiment also demonstrates the use of multiple t1 communication lines, and type of service networking over these lines.  j. lekashman
atm virtual private networks  asynchronous transfer mode (atm) networks are aimed at supporting a variety of services, including voice, video and data, while allowing the users to efficiently share network resources. efficiency and flexibility in managing the resources are essential to meet the different quality requirements of these services. network resources include trunk bandwidth, switching capacity, and buffer space in the atm cross- connects. sharing these resources is a complex task, since different applications have different traffic characteristic and quality of service (qos) requirements. for example, video is characterized by continuous bit rate (cbr) or variable bit rate (vbr) traffic, while voice and data are bursty in nature. the quality requirements also depend on the type of service under considerations---some services, like video and voice, have strict end-to-end delay requirements, whereas others may be carried on a best-effort basis.  shivi fotedar mario gerla paola crocetti luigi fratta
satellite systems for personal communication networks  the paper addresses some issues related to satellite personal communication networks (s-pcns). the role of satellite communications in that scenario is discussed, and some characteristics of s-pcns are identified. in addition, the problem of the integration of s-pcns with the universal mobile telecommunication system (umts) is considered. in this respect an original methodology for accomplishing such integration is proposed; such methodology aims at avoiding complex protocol conversions at the interfaces between the terrestrial and the satellite segment. the paper is partly based upon the work performed by the authors in the framework of the european community insured project "integrated satellite umts real environment demonstrator".  fulvio ananasso francesco delli priscoli
internet nuggets this column consists of selected traffic from the comp.arch newsgroup, a forum for discussion of computer architecture on internet---an international computer network. as always, the opinions expressed in this column are the personal views of the authors, and do not necesarily represent the institutions to which they are affiliated. text which sets the context of a message appears in italics; this is usually text the author has quoted from earlier messages. the code-like expressions below the authors' names are their addresses on internet. mark thorson
reducing branch costs via branch alignment  several researchers have proposed algorithms for basic block reordering. we call these branch alignment algorithms. the primary emphasis of these algorithms has been on improving instruction cache locality, and the few studies concerned with branch prediction reported small or minimal improvements. as wide-issue architectures become increasingly popular the importance of reducing branch costs will increase, and branch alignment is one mechanism which can effectively reduce these costs.  in this paper, we propose an improved branch alignment algorithm that takes into consideration the architectural cost model and the branch prediction architecture when performing the basic block reordering. we show that branch alignment algorithms can improve a broad range of static and dynamic branch prediction architectures. we also show that a program performance can be improved by approximately 5% even when using recently proposed, highly accurate branch prediction architectures. the programs are compiled by any existing compiler and then transformed via binary transformations. when implementing these algorithms on a alpha axp 21604 up to a 16% reduction in total execution time is achieved.  brad calder dirk grunwald
sending messages to mobile users in disconnected ad-hoc wireless networks  an ad-hoc network is formed by a group of mobile hosts upon a wireless network interface. previous research in this area has concentrated on routing algorithms which are designed for fully connected networks. the usual way to deal with a disconnected ad-hoc network is to let the mobile computer wait for network reconnection passively, which may lead to unacceptable transmission delays. in this paper, we propose an approach that guarantees message transmission in minimal time. in this approach, mobile hosts actively modify their trajectories to transmit messages. we develop algorithms that minimize the trajectory modifications under two different assumptions: (a) the movements of all the nodes in the system are known and (b) the movements of the hosts in the system are not known.  qun li daniela rus
branch folding in the crisp microprocessor: reducing branch delay to zero  a new method of implementing branch instructions is presented. this technique has been implemented in the crisp microprocessor. with a combination of hardware and software techniques the execution time cost for many branches can be effectively reduced to zero. branches are folded into other instructions, making their execution as separate instructions unnecessary. branch folding can reduce the apparent number of instructions needed to execute a program by the number of branches in that program, as well as reducing or eliminating pipeline breakage. statistics are presented demonstrating the effectiveness of branch folding and associated techniques used in the crisp microprocessor.  d. r. ditzel h. r. mclellan
a two-bit contention-based tdma technique for data transmissions  the performance of a contention-based tdma technique is studied in this paper. the frame structure of the time-axis is similar to [1] and [2]. the protocols proposed in [1],[2] and here are all active multiaccess techniques. the protocol in [1] is contention free and suitable for heavy traffic while a contention-based protocol suitable for light traffic is considered in [2]. the protocol to be studied in this paper is also contention in nature and performs considerably better than [2]. this protocol is less complicated than [1] and out-performs [1] unless traffic is very high. performance analyses, both transient and steady-state, have been successfully completed. results obtained include average queue length and packet delay, etc. the validity of analysis is also verified by computer simulations.  d tsai j chang
a signaling and control architecture for mobility support in wireless atm networks  this paper presents a signaling and control architecture for mobility support in a "wireless atm" network that provides integrated broadband services to mobile terminals. a system level protocol architecture for a wireless atm network is outlined. the proposed protocol stack incorporates new wireless link mac, dlc and wireless control sublayers, together with appropriate mobility extensions to the existing atm network control layer. wireless control and atm signaling capabilities required for mobility support are discussed, and preliminary solutions are given for selected major functions. potential extensions to standard q.2931 atm signaling are proposed to support handoff and service parameter/qos renegotiation required for mobility. an associated wireless control protocol for supporting terminal migration, resource allocation, and handoff is discussed. preliminary experimental results are given which validate the proposed handoff control protocol on an atm network testbed.  r. yuan s. k. biswas l. j. french j. li d. raychaudhuri
design & application of a memory-coupled microprocessor network  in the present paper, design and applications of a memory coupled network of four 8080a microprocessors are discussed. the architecture fully exploits all the inherent capabilities of a network namely, flexibility, dynamic reconfiguration, redundancy for fault-tolerance, higher throughput due to parallelism and pipelining and most effective utilisation of expensive resources. a simple and novel hardware protocole completely eliminates the communications software and provides a fast access to shared resources to each processor in the network. the network is extremely versatile and finds application in vast number of completely divergent areas.  p. w. dandekar
stochastic control of path optimization for inter-switch handoffs in wireless atm networks  one of the major design issues in wireless atm networks is the support of inter-switch handoffs. an inter-switch handoff occurs when a mobile terminal moves to a new base station connecting a different switch. apart from resource allocation at the new base station, inter-switch handoff also requires connection rerouting. with the aim of minimizing the handoff delay while using the network resources efficiently, the two-phase handoff protocol uses path extension for each inter-switch handoff, followed by path optimization if necessary. the objective of this paper is to determine when and how often path optimization should be performed. the problem is formulated as a semi-markov decision process. link cost and signaling cost functions are introduced to capture the tradeoff between the network resources utilized by a connection and the signaling and processing load incurred on the network. the time between inter-switch handoffs follows a general distribution. a stationary optimal policy is obtained when the call termination time is exponentially distributed. numerical results show significant improvement over four other heuristics.  vincent w. s. wong mark e. lewis victor c. m. leung