waashk/acm huggingface dataset:
the vhsic hardware description language (vhdl) program  the emergence of the importance of vlsi design automation and the vlsi custom/semicustom industry has spurred a wide-spread interest in hardware description languages. starting in 1981, the vhsic program has acted as a catalyst to develop a standard hardware description language that could beneficially serve the government, industry, and academic communities. this panel will discuss from different viewpoints the issues associated with vlsi interoperability standards and the potential role of the vhsic hardware description language.  al dewey
selecting partial scan flip-flops for circuit partitioning  this paper presents a new method of selecting scan flip-flops (ffs) in partial scan designs of sequential circuits. scan ffs are chosen so that the whole circuit can be partitioned into many small subcircuits which can be dealt with separately by a test pattern generator. this permits easy automatic test pattern generation for arbitrarily large sequential circuits. algorithms of selecting scan ffs to allow such partitioning and of scheduling tests for subcircuits are given. experimental results show that the proposed method makes it possible to generate test patterns for extra large sequential circuits which previous approaches cannot deal with.  toshinobu ono
multiple instruction issue and single-chip processors  in this paper we evaluate the performance of single-chip processors with multiple functional units. as a basis for our studies we use a processor model that is very similar to many of today's single-chip processors. using this basic machine model, we investigate the performance that can be achieved if some limited form of multiple instruction issue is supported. for these investigations, we use 4 variants of the basic machine that represented different memory access times and branch execution times. in particular, we evaluate issuing 2 instructions per cycle and find that by restricting multiple instruction issue to load or branch instructions much of the same performance gains can be achieved as in the unrestricted form.  a. r. pleszkun g. s. sohi
event propagation conditions in circuit delay computation  accurate and efficient computation of delays is a central problem in computer- aided design of complex vlsi circuits. delays are determined by events (signal transitions) propagated from the inputs of a circuit to its outputs, so precise characterization of event propagation is required for accurate delay computation. although many different propagation conditions (pcs) have been proposed for delay computation, their properties and relationships have been far from clear. we present a systematic analysis of delay computation based on a series of waveform models that capture signal behavior rigorously at different levels of details. the most general model, called the exact of w0 model, specifies each event occurring in a circuit signal. a novel method is presented that generates approximate waveforms by progressively eliminating signal values from the exact model. for each waveform model, we drive the pcs that correctly capture the requirements under which an event propagates along a path. the waveform models and their pcs are shown to form a well-defined hierarchy, which provides a means to trade accuracy for computational effort. the relationships among the derived pcs and existing ones are analyzed in depth. it is proven that though many pcs, such as the popular floating mode condition, produce a correct upper bound on the circuit delay, they can fail to recognize event propagation in some instances. this analysis further enables us to derive new and useful pcs. we describe such a pc, called safe static. experimental results demonstrate that safe static provides an excellent accuracy/efficiency tradeoff.  hakan yalcin john p. hayes
a coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing  in this work, we propose a circuit partitioning and test pattern generation algorithm for built-in pseudoexhaustive self-testing of vlsi circuits. the circuit partitioning process is to partition a given circuit into a set of subcircuits such that pseudoexhaustive self-testing will be possible, while the test pattern generation process is to generate the pseudoexhaustive test patterns for each subcircuit using a linear feedback shift register (lfsr). both problems are considered and solved in the same phase and lead to an efficient and well-coordinated solution. experiments using computer simulation have been conducted. the results demonstrate that the proposed method is very good, especially for circuits that are highly locally connected.  w.-b. jone c. a. papachristou
a unified framework for race analysis of asynchronous networks  a unified framework is developed for the study of asynchronous circuits of both gate and mos type. a basic network model consisting of a directed graph and a set of vertex excitation functions is introduced. a race analysis model, using three values (0, 1, and x), is developed for studying state transitions in the network. it is shown that the results obtained using this model are equivalent to those using ternary simulation. it is also proved that the set of state variables can be reduced to a minimum size set of feedback variables, and the analysis still yields both the correct state transitions and output hazard information. finally, it is shown how the general results above are applicable to both gate and mos circuits.  j. a. brzozowski c.-j. seger
macromodeling of digital mos vlsi circuits  this paper presents a method for modeling mos combinational logic gates. analyses are given for power consumption, output response delay, output response waveshape, and input capacitance. the models are both computationally efficient and accurate, typically lying within 5% of spice estimates. they are pertinent to simulation and optimization applications. a general macromodeling software support package is described. a related paper [1] discusses a circuit optimizer based on these models.  mark d. matson
a new approach for factorizing fsm's  exact factors as defined in [2], if present in an fsm can result in most effective way of factorization. however, it has been found that most of the fsm's are not exact factorizable. in this paper, we have suggested a method of making fsm's exact factorizable by minor changes in the next state space while maintaining the functionality of the fsm. we have also developed a new combined state assignment algorithm for state encoding of factored and factoring fsm's. experimental results on mcnc benchmark examples, after running misii on the original fsm, factored fsm and factoring fsm have shown a reduction of 40% in the worst case signal delay through the circuit in a multilevel implementation. the total number of literals, on an average is the same after factorization as that obtained by running misii on the original fsm. for two-level implementation, our method has been able to factorize benchmark fsm's with a 14% average increase in overall areas, while the areas of combinational components of factored and factoring fsm's have been found to be significantly less than the area of the combinational component of the original fsm.  c. rama mohan p. p. chakrabarti
completion time multiple branch prediction for enhancing trace cache performance  the need for multiple branch prediction is inherent to wide instruction fetching. this paper presents a completion time multiple branch predictor called the tree-based multiple branch predictor (tmp) that builds on previous single branch prediction techniques. it employs a tree structure of branch predictors, or tree-node predictors, and achieves accurate multiple branch prediction by leveraging the high accuracies of the individual branch predictors. a highly-efficient tmp design uses the 2-bit saturating counters for the tree-node predictors. to achieve higher prediction rate, the tmp employs two-level schemes for the tree-node predictors resulting in a three- level tmp design. placing the tmp at completion time reduces the critical latency in the front-end of the pipeline; the resultant longer update latency does not significantly impact the overall performance. in this paper the tmp is applied to a trace cache design and shown to be very effective in increasing its performance.  results: a realistic-size tmp (72kb) can predict 1, 2, 3, and 4 consecutive blocks with compounded prediction accuracies of 96%, 93%, 87%, and 82%, respectively. the block-based trace cache with this tmp achieves 4.75 ipc for specint95 on an idealized machine, which is a 20% performance improvement over the original design [1]. this improved performance is 8% above that of a conventional i-cache design with perfect single branch prediction.  ryan rakvic bryan black john paul shen
optimization of hierarchical designs using partitioning and resynthesis  this paper explores the influence of optimization along the boundary between hierarchically described components. a novel technique called repartitioning combines partitioning and sequential resynthesis of the design under various quality measures. it is applied to various digital circuits which consist of a controller and a datapath. the outcome of this effort is a versatile, parametrizable resynthesis tool which preserves this hierarchy. due to the cost measures, an average improvement ranging between 5% and 15% was obtained.  heinz-josef eikerling ralf hunstock raul camposano
global microcode compaction under timing constraints  existing global microcode compaction algorithms have all been based on the assumption that the parallelism exploitation is constrained only by data dependency and resource limitation. however, the timing constraint also has great impact upon microcode compaction, thus it is highly necessary to study global microcode compaction under timing constraints. this paper conducts an analysis on the global timing problem, modifies the mo motion rules and presents an algorithm based on trace scheduling for global microcode compaction under timing constraints.  b. su j. wang j. xia
high-performance carry chains for fpgas  carry chains are an important consideration for most computations, including fpgas. current fpgas dedicate a portion of their logic to support these demands via a simple ripple carry scheme. in this paper we demonstrate how more advanced carry constructs can be embedded into fpgas, providing significantly higher performance carry computations. we redesign the standard ripple carry chain to reduce the number of logic levels in each cell. we also develop entirely new carry structures based on high performance adders such as carry select, carry lookahead, and brent-kung. overall, these optimizations achieve a speedup in carry performance of 3.8 times over current architectures.  scott hauck matthew m. hosler thomas w. fry
dynamical identification of critical paths for iterative gate sizing  since only sensitizable paths contribute to the delay of a circuit, false paths must be excluded in optimizing the delay of the circuit. just identifying false paths in the first place is not sufficient since during iterative optimization process, false paths may become sensitizable, and sensitizable paths false. in this paper, we examine cases for false path becoming sensitizable and sensitizable becoming false. based on these conditions, we adopt a so-called loose sensitization criterion which is used to develop an algorithm for dynamically identification of sensitizable paths. by combining gate sizing and dynamically identification of sensitizable paths, an efficient performance optimization tool is developed. results on a set of circuits from iscas benchmark set demonstrate that our tool is indeed very effective in reducing circuit delay with less number of gate sized as compared with other methods.  how-rern lin tingting hwang
performance estimation of multiple-cache ip-based systems: case study of an interdependency problem and application of an extended shared memory model  in estimating the performance of multiple-cache ip- based systems, we face a problem of interdependency between cache configuration and system behavior. in this paper, we investigate the effects of the interdependency on system performance in a case study. we present a method that gives fast and accurate estimation of system performance by simulating ip cores at the behavioral level with annotated delays and by simulating the multiple-cache communication architecture with an extended shared memory model. experiments show the effectiveness of the proposed method.  sungjoo yoo kyoungseok rha youngchul cho jinyong jung kiyoung choi
revisiting floorplan representations  floorplan representations are a fundamental issue in designing floorplan algorithms. in this paper, we first derive the exact number of configurations of mosaic floorplans and slicing floorplans. we then present two non-redundant representations: a twin binary tree structure for mosaic floorplans and a slicing ordered tree for slicing floorplans. finally, the relations between the state-of-the-art floorplan representations are discussed and their efficiency is explored.  bo yao hongyu chen chung-kuan cheng ronald graham
data dependency graph bracing  the sunburst compiler refined at utah state university employs a powerful mechanism for management of data anti- dependencies in data dependency graphs, ddg's: the ddg bracer. the term bracing1 is used to mean the fastening of two or more parts together. there are two major goals in bracing: 1) semantic correctness, and 2) creation of an optimal ddg. bracing provides necessary joining of code fragments, produced by a divide and conquer code generation algorithm, while yielding multiple code sequences.  since no anti-dependency arcs are present, the input ddg's are said to be in normal form. because anti-dependency arcs occur only when a resource must be reused, a ddg in normal form represents infinite resources. the output ddg is a merging of the two input ddg's such that data dependency arcs between the two ddg's are inserted and data anti-dependency arcs are added to sequentialize the use of common resources.  vegdahl [veg82] was one of the first to recognize the importance of live track manipulation. a live track is an ordered pair: the first component is the microoperation node ( mo) in which a resource is born, and the second component is the set of nodes in which the resource dies.  v. h. allan
programmable memory blocks supporting content-addressable memory  the embedded system block (esb) of the apex e programmable logic device family from altera corporation includes the capability of implementing content addressable memory (cam) as well as product term macrocells, rom, and dual port ram. in cam mode each esb can implement a 32 word cam with 32 bits per word. in product term mode, each esb has 16 macrocells built out of 32 product terms with 32 literal inputs. the ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. the architecture and features of this embedded system block are described.  frank heile andrew leaver kerry veenstra
a comprehensive fault macromodel for opamps  in this paper, a comprehensive macromodel for transistor level faults in an operational amplifier is developed. with the observation that faulty behavior at output may result from interfacing error in addition to the faulty component, parameters associated with input and output characteristics are incorporated. test generation and fault classification are addressed for stand-alone opamps. a high fault coverage is achieved by a proposed testing strategy. transistor level short/bridging faults are analyzed and classified into catastrophic faults and parametric faults. based on the macromodels for parametric faults, faults simulation is performed for an active filter. we found many parametric faults in the active filter cannot be detected by traditional functional testing. a dft scheme alone with a current testing strategy to improve fault coverage is proposed.  chen-yang pan kwang-ting cheng sandeep gupta
flexible processors: a promising application-specific processor design approach  a new approach to application specific processor design is presented in this paper. existing application specific processors are either based on existing general purpose processors or custom designed special purpose processors. the availability of a new technology, the xilinx logic cell array, presents the opportunity for a new alternative. the flexible processor cell is a prototype of an extremely reconfigurable application specific processor. flexible processors can potentially provide the performance advantages of special purpose processors as well as the cost advantages of general purpose processors. the flexible processor concept opens many potential areas for future research in processor architecture and implementation. this paper presents the design, implementation, and preliminary performance evaluation of an experimental flexible processor.  a. wolfe p. shen
closed form solutions to simultaneous buffer insertion/sizing and wire sizing  in this paper, we consider the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. we consider three cases, namely using no buffer (i.e., wire sizing alone), using a given number of buffers, and using the optimal number of buffers. we provide elegant closed form optimal solutions for all three problems. these closed form solutions are useful in early stages of the vlsi design flow such as logic synthesis and floorplanning.  chris chu d. f. wong
the use of static column ram as a memory hierarchy  the static column ram devices recently introduced offer the potential for implementing a direct- mapped cache on-chip with only a small increase in complexity over that needed for a conventional dynamic ram memory system. trace-driven simulation shows that such a cache can only be marginally effective if used in the obvious way. however it can be effective in satisfying the requests from a processor containing an on-chip cache. the scram cache is more effective if the processor cache handles both instructions and data.  james r. goodman men-chow chiang
technology mapping for k/m-macrocell based fpgas  in this paper, we study the technology mapping problem for a novel fpga architecture that is based on k-input single-output pla-like cells, or, k/m-macrocells. each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. we develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. the experiment results show our algorithm can achieve depth- optimality in practically all cases. furthermore it is shown that the k/m-macrocell based fpgas are practically equivalent to the traditional k-lut based fpgas with only a relatively small number of product terms (m≤k \\+ 3). we also investigate thetotal are and delay of k/m-macrocell based fpgas on various benchmarks to compare it with commonly used 4-lut based fpgas. the experimental result shows k/m-macrocell based fpgas can outperform 4-lut based fpgas in terms of both delay and area after placement and routing by vpr.  jason cong hui huang xin yuan
automated layout generation using gate matrix approach  this paper presents a software system alsugma for automated gate matrix layout generation. its structured net-list and realization matrix models which are different from previous interval graph approach are introduced. algorithms to minimize and realize the gate matrix layout are also presented with examples. empirical results showed good performance in terms of both speed and layout quality. folding technique for such layout style is also introduced.  y.-c. chang s.-c. chang l.-h. hsu
the k2 parallel processor: architecture and hardware implementation  k2 is a distributed-memory parallel processor designed to support a multi- user, multi-tasking, time-sharing operating system and an automatically parallelizing fortran compiler. this paper presents the architecture and the hardware implementation of k2, and focuses on the architectural features required by the operating system and the compiler. a prototype machine with 24 processors is currently being developed.  marco annaratone marco fillo kiyoshi nakabayashi marc viredaz
bist plas, pass or fail - a case study  numerous built-in self testing (bist) designs now exist for the testing of programmable logic arrays (pla), but their practical usefulness has not been studied. in this paper, we implement and compare several bist designs using a common methodology of implementation. we also perform an yield analysis to characterize the yield degradation due to the bist design methodology. our preliminary findings of this work is that bist approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for plas.  shambhu j. upadhyaya john a. thodiyil
test generation for scan design circuits with tri-state modules and bidirectional terminals  this paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. the test generation procedure uses a path sensitization technique with 14 signal values. the principal features of this program are test generation with automatic decision of i/o mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches(srls) by using shift-in function of srls.  takuji ogihara shinichi murai yuzo takamatsu kozo kinoshita hideo fujiwara
placement of irregular circuit elements on non-uniform gate arrays  a program is described which was designed primarily to automatically place 5000 gate circuits comprising irregular drop-in components onto the uk5000 type gate array. the architecture of this array is unique, having latch cells together with basic logic cells already predefined on the uncommitted die and so is not a uniform structure. the program uses levels of automatic partitioning and placement forming initial solutions constructively followed by iterative improvement techniques. the concept of function dependent targeting for partitions is introduced together with a novel constructive initial partitioning algorithm. the concept extends throughout most of the subsequent improvement and placement processes. a novel placement improvement algorithm which considers the distribution of unused cells following initial placement is also introduced. the program is entirely file-driven, and uses plug-in algorithms making it suitable for a wide range of placement problems.  i. h. kirk p. d. crowhurst j. a. skingley j. d. bowman g. l. taylor