waashk/acm huggingface dataset:
fast and accurate timing simulation with regionwise quadratic models of mos i-v characteristics  this paper presents a technique called regionwise quadratic (rwq) modeling that allows highly accurate mos models, as well as measured i-v data, to be used in fast timing simulation. this technique significantly increases the accuracy of fast timing simulation while maintaining efficiency by permitting analytical solutions of node equations. a fast timing simulator using these rwq models has been implemented. several examples of rwq modeling are provided, and comparisons of simulation results with spice3 are shown to demonstrate accuracy and efficiency. speedups of two to three orders of magnitude for circuits containing up to 2000 transistors are observed.  a. dharchoudhury s. m. kang k. h. kim s. h. lee
cregs: a new kind of memory for referencing arrays and pointers  often, pointer and subscripted array references touch memory locations for which there are several possible aliases, hence these references cannot be made from registers. although conventional caches can increase performance somewhat, they do not provide many of the benefits of registers, and do not permit the compiler to perform many optimizations associated with register references. the creg (pronounced "c-reg") mechanism combines the hardware structures of cache and registers to create a new kind of memory structure, which can be used either as processor registers or as a replacement for conventional cache memory. by permitting aliased names to be grouped together, cregs resolve ambiguous alias problems in hardware, resulting in more efficient execution than even the combination of conventional registers and cache can provide.  this paper discusses both the conceptual creg hardware structure and the compiler analysis and optimization techniques to manage that structure.  h. dietz c. h. chi
vlsi design synthesis with testability  a vlsi design synthesis approach with testability, area, and delay constraints is presented. this research differs from other synthesizers by implementing testability as part of the vlsi design solution. a binary tree data structure is used throughout the testable design search. its bottom up and top down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. the partitioning and two dimensional characteristics of the binary tree structure provide vlsi design floorplans and global information for test incorporation. an elliptical wave filter example was used to illustrate the design synthesis with testability constraints methodology. test methodologies such as multiple chain scan paths and bist with different test schedules were explored. design scores comprised of area, delay, fault coverage, and test length were computed and graphed. results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.  catherine h. gebotys mohamed i. elmasry
time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits  as a new approach for timing verification of logic circuits, we propose a new concept of time-symbolic simulation. while a conventional symbolic simulator treats signal values as logical expressions, a time-symbolic simulator treats time as algebraic expressions. in this paper, we describe algorithms for time- symbolic simulation, and its application to hazard detection and verification of asynchronous sequential circuits.  n. ishiura m. takahashi s. yajima
parity logging overcoming the small write problem in redundant disk arrays  parity encoded redundant disk arrays provide highly reliable, cost effective secondary storage with high performance for read accesses and large write accesses. their performance on small writes, however, is much worse than mirrored disks---the traditional, highly reliable, but expensive organization for secondary storage. unfortunately, small writes are a substantial portion of the i/o workload of many important, demanding applications such as on-line transaction processing. this paper presents parity logging, a novel solution to the small write problem for redundant disk arrays. parity logging applies journalling techniques to substantially reduce the cost of small writes. we provide a detailed analysis of parity logging and competing schemes--- mirroring, floating storage, and raid level 5--- and verify these models by simulation. parity logging provides performance competitive with mirroring, the best of the alternative single failure tolerating disk array organizations. however, its overhead cost is close to the minimum offered by raid level 5. finally, parity logging can exploit data caching much more effectively than all three alternative approaches.  daniel stodolsky garth gibson mark holland
balance in architectural design  we introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of vlsi theory and the price / performance ratio of advertising literature. this metric captures the idea of a piece of hardware "pulling its own weight," i.e. contributing as much to performance as it costs in resources. we then prove general theorems for stating when the size of a given part is in balance with its utilization, and give specific formulas for commonly found linear and quadratic devices. we also apply these formulas to an analysis of a specific processor element, and discuss the implications for bit-serial vs word- parallel, risc vs cisc, and vliw designs.  samuel ho lawrence snyder
integrated test of interacting controllers and datapaths  in systems consisting of interacting datapaths and controllers and utilizing built-in self test (bist), the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. this work facilitates the testing of datapath/controller pairs in an integrated fashion. the key to the approach is the addition of logic to the system that interacts with the existing controller to push the effects of controller faults into the data flow, so that they can be observed at the datapath registers rather than directly at the controller outputs. the result is to reduce the bist overhead over what is needed if the datapath and controller are tested independently, and to allow a more complete test of the interface between datapath and controller, including the faults that do not manifest themselves in isolation. fault coverage and overhead results are given for four example circuits.  mehrdad nourani joan carletta christos papachristou
april: a processor architecture for multiprocessing  processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. this paper describes the architecture of a rapid-context-switching processor called april with support for fine-grain threads and synchronization. april achieves high single-thread performance and supports virtual dynamic threads. a commercial risc-based implementation of april and a run-time software system that can switch contexts in about 10 cycles is described. measurements taken for several parallel applications on an april simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of two over a corresponding implementation on the encore multimax. the scalability of a multiprocessor based on april is explored using a performance model. we show that the sparc-based implementation of april can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles.  anant agarwal beng-hong lim david kranz john kubiatowicz
noise estimation due to signal activity for capacitively coupled cmos logic gates  the effect of interconnect coupling capacitance on neighboring cmos logic gates driving coupled interconnections strongly depends upon the signal activity. a transient analysis of two capacitively coupled cmos logic gates is presented in this paper for different combinations of signal activity. the uncertainty of the effective load capacitance and propagation delay due to the signal activity is addressed. analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. the propagation delay based on these analytical expressions is within 3% as compared to spice, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. the logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the signal delay. the peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of spice.  kevin t. tang eby g. friedman
functional testing of digital systems  functional testing is testing aimed at validating the correct operation of a digital system with respect to its functional specification. we have designed and implemented a practical test generation methodology that can generate tests directly from a system's high-level specification. solutions adopted include multi-level fault models and multi- stage test generation. tests generated from the methodology were compared against test programs supplied by a computer manufacturer and were found to detect more faults with much better efficiency. the experiment demonstrated that functional testing can be both practical and efficient. automatic generation of design validation tests is now closer to reality.  kwok-woon lai daniel p. siewiorek
a low power unified cache architecture providing power and performance flexibility (poster session)  advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the devices components. the m7core m3 architecture was developed specifically for these embedded applications. to address the growing need for longer battery life and higher performance, an 8-kbyte, 4-way set-associative, unified (instruction and data) cache with pro-grammable features was added to the m3 core. these features allow the architecture to be optimized based on the applications requirements. in this paper, we focus on the features of the m340 cache sub-system and illustrate the effect on power and perfor-mance through benchmark analysis and actual silicon measure-ments.  afzal malik bill moyer dan cermak
sequence-pair based placement method for hard/soft/pre-placed modules  this paper proposes a placement method for a mixed set of hard, soft, and pre- placed modules, based on a placement topology representation called sequence- pair. under one sequence-pair, a convex optimization problem is efficiently formulated and solved to optimize the aspect ratios of the soft modules. the method is used in two ways: i) directly applied in simulated annealing to present the most exact placement method, ii) applied as a post process in an approximate placement method for faster computation. the performance of these two methods are reported using mcnc benchmark examples.  hiroshi murata ernest s. kuh
a study of instruction cache organizations and replacement policies  instruction caches are analyzed both theoretically and experimentally. the theoretical analysis begins with a new model for cache referencing behavior--- the loop model. this model is used to study cache organizations and replacement policies. it is concluded theoretically that random replacement is better than lru and fifo, and that under certain circumstances, a direct- mapped or set associative cache may perform better than a full associative cache organization. experimental results using instruction trace data are then given. the experimental results are shown to support the theoretical conclusions.  james e. smith james r. goodman
a low-voltage cmos multiplier for rf applications (poster session)  a low-voltage analog multiplier operating at 1.2v is presented. the multiplier core consists of four mos transistors operating in the saturation region. the circuit exploits the quadratic relation between current and voltage of the mos transistor in saturation. the circuit wasdesigned using standard 0.6μm cmos technology. simulation results indicate an ip3 of 4.9dbm and a spur free dynamic range of 45db.  carl james debono franco maloberti joseph micallef
dynajust: an efficient automatic routing technique optimizing delay conditions  a new routing technique dynajust, dynamic wire length adjustment, is described. it accurately realizes specified wire lengths to fulfill delay conditions. the implementation, based on the combination of shortest path algorithms, is proposed to achieve a high completion ratio in a short processing time. the technique is useful in practical situations where high accuracy is required of many nets.  y. fujihara y. sekiyama y. ishibashi m. yanaka
a logic minimizer for vlsi pla design  this paper describes logmin, a new, interactive computer aided logic design tool. logmin automates the increasingly complex problems of vlsi pla design which has made the specification, manipulation, minimization and generation of plas difficult to do by hand.  logmin allows the specification of both combinational functions and sequential machines. combinational functions may be described using a variety of operators, intermediate variables or pla code. a state machine description language (smdl) was developed for the specification of sequential machines.  this paper describes the background and motivation for logmin, the algorithms used and the grammar for smdl. several examples are provided.  bill teel doran wilde
program path analysis to bound cache-related preemption delay in preemptive real-time systems  unpredictable behavior of cache memory males it difficult to statically analyze the worst-case performance of real-time systems. this problem is exacerbated in case of preemptive multitask systems due to intertask cache in terference, called cache-related preemption delay (crpd). this paper proposes an approach to analysis of the tight upper bound on crpd which a task might impose on lower-priority tasks. our method determines the program execution path of the task which requires the maximum number of cache blocks using an integer linear programming technique. experimental results show that our approach provides up to 69% tighter bounds on crpd than a previous approach.  hiroyuki tomiyama nikil d. dutt
optimizations for a highly cost-efficient programmable logic architecture  architects of programmable logic devices (plds) face several challenges when optimizing a new device family for low manufacturing cost. when given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. once low die cost is achieved, it is seen that testing and packaging costs must be considered. interactions among these three cost contributors pose trade-offs that prevent independent optimization. this paper discusses solutions discovered by the architects optimizing the altera flex 6000 architecture.  kerry veenstra bruce pedersen jay schleicher chiakang sung
efficient algorithms for computing the longest viable path in a combinational network  we consider the elimination of false paths in combinational circuits. we give the single generic algorithm that is used to solve this problem, and demonstrate that it is parameterized by a boolean function called the sensitization condition. we give two criteria which we argue that a valid sensitization condition must meet, and introduce four conditions that have appeared in the recent literature, of which two meet the criteria and two do not. we then introduce a dynamic programming procedure for the tightest of these conditions, the viability condition, and discuss the integration of all four sensitization conditions in the lllama timing environment. we give results on the iwls and iscas benchmark examples and on carry-bypass adders.  p. c. mcgeer r. k. brayton
functional verification of mos circuits  this report describes the ideas behind silica pithecus, a program which verifies synchronous digital mos vlsi circuits. silica pithecus accepts the schematic of an mos vlsi circuit, declarations of the logical relationships between the inputs signals (e.g., which inputs are mutually exclusive), and a specification of the intended digital behavior of the circuit. if the circuit fails to meet its specification silica pithecus returns to the designer the precise reason it fails to do so. unlike previous verification systems, silica pithecus employs a realistic electrical model. it also automatically generates the constraints on the inputs of a circuit which ensure the circuit will exhibit its intended digital behavior. these constraints are necessary for hierarchical verification. silica pithecus operates hierarchically, interactively, and incrementally.  d. weise
power minimization of functional units partially guarded computation  this paper deals with power minimization problem for data-dominated applications based on a novel concept called partially guarded computation. we divide a functional unit into two parts - msp (most significant part) and lsp (least significant part) - and allow the functional unit to perform only the lsp computation if the range of output data can be covered by lsp. we dynamically disable msp computation to remove unnecessary transitions thereby reducing power consumption. we also propose a systematic approach for determining optimal location of the boundary between the two parts during high-level synthesis. experimental results show about 10~44% power reduction with about 30~36% area overhead and less than 3% delay overhead in functional units.  junghwan choi jinhwan jeon kiyoung choi
transistor reordering for power minimization under delay constraint  in this article we address the problem of optimization of vlsi circuits to minimize power consumption while meeting performance goals. we present a method of estimating power consumption of a basic or complex cmos gate which takes the internal capacitances of the gate into account. this method is used to select an ordering of series-connected transistors found in cmos gates to achieve lower power consumption. the method is very efficient when used by library-based design styles. we describe a multipass algorithm that makes use of transistor reordering to optimize performance and power consumption of circuits, has a linear time complexity per pass, and converges to a solution in a small number of passes. transformations in addition to transistor reordering can be used by the algorithm. the algorithm has been benchmarked on several large examples and the results are presented.  s. c. prasad k. roy
the proposal of a computing model for prototypes of microprogrammed machines solving complex problems  our research work concerns the definition of computational systems for the solution of complex scientific problems. in this work we present the analysis of a computing model for the definition and the implementation of microprogrammed prototypal machines. the computing model is expressed in terms of a system of equations. the structure and the control of a microprogrammed machine is directly implied by the formally defined properties of the system of equations.  e. binaghi g. pasi g. r. sechi
hyhope: a fast fault simulator with efficient simulation of hypertrophic faults  in sequential circuit fault simulation, the hypertrophic faults, which result from lengthened initialization sequence in the faulty circuits, usually produce a large number of fault events during simulation and require excessive gate evaluations. these faults degrade the performance of fault simulators attempting to simulate them exactly. in this paper, an exact simulation algorithm is developed to identify the hypertropic faults and to minimize their effects during the fault simulation. the simulator hyhope based on this algorithm shows that the average speedup ratio over hope 1.1 is 1.57 for iscas89 benchmark circuits. furthermore, the result indicates the performance of hyhope is close to the approximate simulator in which faults are simply dropped when they become potentially detected.  chen-pin kung chen- shang lin
timing uncertainty analysis for time-of-flight systems  time-of-flight synchronization is a new digital design methodology that eliminates all latching devices, allowing higher clock rates than alternative timing schemes. synchronization is accomplished by precisely balancing connection delays. many effective pipeline stages are created by pipelining combinational logic, similar in concept to wave pipelining but differing in several respects. due to the unique flow-through nature of circuits and to the need for pulse-mode operation, time-of-flight design exposes interesting new areas for cad timing analysis. this paper discusses how static propagation delay uncertainty limits the clock period for time-of-flight circuits built with opto-electronic devices. we present algorithms for placing a minimum set of clock gates to restore timing in feedback loops that implement memory and for propagating delay uncertainty through a circuit graph. a mixed integer program determining the minimum feasible clock period subject to pulse width and arrival time constraints is discussed. algorithms are implemented in xhatch, a time-of- flight cad package.  john r. feehrer harry f. jordan
test generation for bridging faults in cmos ics based on current monitoring versus signal propagation  bridge-type defects play a dominant role in state-of-the-art cmos technologies. this paper describes a combined functional and overcurrent-based test generation approach for cmos circuits, which is optionally based on layout information. comparative results for benchmark circuits are given to demonstrate the feasibility of voltage-based versus iddq-based testing.  u. gläser h. t. vierhaus m. kley a. wiederhold
testing of uncustomized segmented channel field programmable gate arrays  this paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (fpgas) such as those manufactured by actel. the principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the fpga as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ilas). these arrays can then be tested by establishing appropriate conditions such as constant testability (c-testability). a design approach is proposed. this approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ila configuration as a one- dimensional unilateral array. it also requires the addition of a further primary pin. features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original fpga configuration of [1]. the proposed approach requires 8+2nf vectors for testing the uncommitted fpga of [1], where nf is the number of flip-flops (equal to the number of sequential modules for the fpga of [1]) in a row of the fpga.  tong liu wei kang huang fabrizio lombardi