waashk/acm huggingface dataset:
multiple operation memory structures  this paper describes architectures based on a new memory structure. memory systems which can perform multiple transfers are described and issues in processor architecture are considered. a general model for memory operations is given, and the classical single transfer memory structures are described. based on the generalized model, new structures which allow multiple transfers to be performed as a single processor operation are developed. some architectural considerations at the processor level to support these kinds of memory systems are then discussed. the advantages and disadvantages of these new structures as compared to conventional memories are also discussed and a preliminary performance evaluation is done. this discussion generally refers to the random access, physical, main memory in the system, although many of the results are applicable to other storage devices.  m. c. ertem
a new rapid prototyping firmware (rpf) tool  microprogramming has progressed from a method for systematically designing control units to its wide-spread application to the design, emulation, analysis, and implementation of instruction sets for general-purpose computers. the application was greatly enhanced through the family-oriented architectures of the ibm system 360 and on into the dec pdp-11 family, culminating in the vax family of machines. today, systolic, vlsi, and vhsic microarchitectures are demanding increased centralized microprogrammable control capability. however, microprogramming has always been a tedious, time consuming, difficult to verify and, therefore, costly exercise. a new rapid prototyping firmware (rpf) tool is described which ameliorates most of the problems.  m. andrews f. lam
test pattern generation based on arithmetic operations  existing built-in self test (bist) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. in this paper, we propose a novel method for implementing test pattern generators based on adders widely available in data- path architectures and digital signal processing circuits. test patterns are generated by continuously accumulating a constant value and their quality is evaluated in terms of the pseudo-exhaustive state coverage on subspaces of contiguous bits. this new test generation scheme, along with the recently introduced accumulator-based compaction scheme facilitates a bist strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and area overhead.  sanjay gupta janusz rajski jerzy tyszer
auxiliary variables for bdd-based representation and manipulation of boolean functions  bdds are the state-of-the-art technique for representing and manipulating boolean functions. their introduction caused a major leap forward in synthesis, verification, and testing. however, they are often unmanageable because of the large amount of nodes. to attack this problem, we insert auxiliary variables that decompose monolithic bdds in smaller ones. this method works very well for boolean function representation. as far as combinational circuits are concerned, representing their functions is the main issue. going into the sequential domain, we focus on traversal techniques. we show that, once we have boolean functions in decomposed form, symbolic manipulations are viable and efficient. we investigate the relation between auxiliary variables and static and dynamic ordering strategies. experimental evidence shows that we achieve a certain degree of independence from variable ordering. thus, this approach can be an alternative to dynamic re-ordering. experimental results on boolean function representation, and exact and approximate forward symbolic traversal of fsms, demonstrate the benefits both in terms of memory requirements and of cpu time.  gianpiero cabodi paolo camurati stefano quer
themis logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator  a new logic simulator called themistm logic simulator for the design of lsi, vlsi and pcbs is described. themis supports design verification and test development from initial specification in behavioral and rtl languages to analysis of the final layout at the gate and switch level. to allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. themis is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. this paper gives an overview of themis and its use by design engineers.  mahesh h. doshi roderick b. sullivan donald m. schuler
towards vlsi complexity: the da algorithm scaling problem: can special da hardware help?  with the increasing scale of integration we need to employ da algorithms to assist us in managing the complexities involved. many of our current techniques are already costly and slow and yet scale by some power law as the gate count increases. an analysis of the strategies open to us leads to the possibility that in many cases specialised da hardware is cost effective.  this paper then describes a series of trials to employ a 64 x 64 distributed array processor at da tasks. some unexpected results were obtained as algorithms evolved in the area of tracking, simulation, placement, test generation, fault simulation, and layout rule checking.  the paper concludes with a discussion of the overheads incurred in employing unconventional hardware.  h. g. adshead
supporting reference and dirty bits in spur's virtual address cache  virtual address caches can provide faster access times than physical address caches, because translation is only required on cache misses. however, because we don't check the translation information on each cache access, maintaining reference and dirty bits is more difficult. in this paper we examine the trade-offs in supporting reference and dirty bits in a virtual address cache. we use measurements from a uniprocessor spur prototype to evaluate different alternatives. the prototype's built-in performance counters make it easy to determine the frequency of important events and to calculate performance metrics.  our results indicate that dirty bits can be efficiently emulated with protection, and thus require no special hardware support. although this can lead to excess faults when previously cached blocks are written, these account for only 19% of the total faults, on average. for reference bits, a miss bit approximation, which checks the references bits only on cache misses, leads to more page faults at smaller memory sizes. however, the additional overhead required to maintain true reference bits far exceeds the benefits of a lower fault rate.  d. a. wood r. h. katz
chip assemblers: concepts and capabilities  a chip assembler is a tool for managing design information. it encourages a structured design methodology, wherein a design is described by a collection of hierarchical design decompositions, one for each of its representations. it assists in the enforcement of consistency constraints up, down, and across the different hierarchies. we argue that a chip assembler, as an integrated design environment, requires an integrated approach for the management of design data. we describe what a chip assembler is, how it is used for design management, and what are its desirable features.  randy h. katz shlomo weiss
a representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms  this paper gives a representation for graph data structures as electronic circuits in reconfigurable hardware. graph properties, such as vertex reachability, are computed quickly by exploiting a graph's edge parallelism--- signals propagate along many graph edges concurrently. this new representation admits arbitrary graphs in which vertices/edges may be inserted and deleted dynamically at low cost---graph modification does not entail any re-fitting of the graph's circuit. dynamic modification is achieved by rewriting cells in a reconfigurable hardware array. dynamic graph algorithms are given for vertex reachability, transitive closure, shortest unit path, cycle detection, and connected-component identification. on the task of computing a graph's transitive closure, for example, simulation of such a dynamic graph processor indicates possible speedups greater than three orders of magnitude compared to an efficient software algorithm running on a contemporaneously fast uniprocessor. implementation of a prototype in an fpga verifies the accuracy of the simulation and demonstrates that a practical and efficient (compact) mapping of the graph construction is possible in existing fpga architectures. in addition to speeding conventional graph computations with dynamic graph processors, we note their potential as parallel graph reducers implementing general (turing equivalent) computation.  lorenz huelsbergen
segmented channel routing  routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. these may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. the segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. the general problem is np- complete, but it can be adequately solved in practice. experiments indicate that a segmented channel with judiciously chosen segment lengths may near the efficiency of a conventional channel.  jonathan greene vwani roychowdhury sinan kaptanoglu abbas el gamal
ibm 3081 system overview and technology  the development of the ibm 3081 established the methodology for designing and manufacturing a high- performance computer from an lsi chip technology. the high density packaging of the lsi chip is used to minimize interconnections and to support a fast machine cycle time. this paper will describe the methods used and will highlight some of the design problems that were solved, to offer an understanding of the challenges that lsi brings to the design cycle.  clive a. collins
fast, small, and static combinatorial cmos circuits  we present alps, a new way to generate layout from boolean equations. we use an original tree- structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbolic manipulation and natural mapping onto silicon. this implementation of alps produces static cmos layout using a cascode-switch style. we present measurements done on fabricated circuits. for a large class of functions, particularly semi-regular control logic, vlsi layout generated by alps compares favorably in speed and area to plas and standard-cell designs.  b. p. serlet
an lpga with foldable pla-style logic blocks  laser- programmed gate arrays (lpgas) represent a new approach to application specific integrated circuit prototyping and implementation. this paper proposes a new lpga logic block architecture called a foldable pla-style logic block. the proposed logic block architecture is similar to that found in commercially available cplds. the term foldable means that the granularity of the logic block can be varied. this is achieved using the lpga laser disconnect methodology. a custom cad tool has been developed to map circuits into the new logic block architecture. an experimental study shows that lpgas with foldable logic blocks are more area-efficient than those based on normal unfoldable logic blocks.  jason helge anderson stephen dean brown
the impact of vlsi on microprogramming  there are four "cultures" of microprogramming: the bit-slice culture, the commercial processor culture, the microprogrammable processor culture, and the single-chip culture. the effect of trends in vlsi (very large scale integration) on microprogramming can be assessed by looking the effect on each culture. the bit-slice culture will be affected because levels of integration in bipolar have reached 32-bit slices and the performance of cmos is improving to compete with the dominant bipolar technologies in these applications. the commercial processor culture and the microprogrammable processor culture will be least affected by changes in technology and integration levels. the single- chip culture will be most affected. there are about two more microprocessor generations to go before chips contain an essentially complete cpu. after that, designs will diversify. microprogramming still has a good future.  n. tredennick
a loosely coupled parallel algorithm for standard cell placement  we present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. our algorithm is a derivative of simulated annealing. the implementation of our algorithm is targeted towards networks of unix workstations. this is the very first reported parallel algorithm for standard cell placement which yields as good or better placement results than its serial version. in addition, it is the first parallel placement algorithm reported which offers nearly linear speedup, in terms of the number of processors (workstations) used, over the serial version. despite using the rather slow local area network as the only means of interprocessor communication, the processor utilization is quite high, up to 98% for 2 processors and 90% for 6 processors. the new parallel algorithm has yielded the best overall results ever reported for the set of mcnc standard cell benchmark circuits.  wern-jieh sun carl sechen
an fpga implementation and performance evaluation of the serpent block cipher  with the expiration of the data encryption standard (des) in 1998, the advanced eneryption standard (aes) development process is well underway. it is hoped that the result of the aes process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by des as well as the capability of long-term protection of sensitive information. the technical analysis used in determining which of the potential aes candidates will be selected as the advanced encryption algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. reprogrammable devices such as field programmable gate arrays (fpgas) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. this contribution investigates the significance of an fpga implementation of serpent, one of the advanced encryption standard candidate algorithms. multiple architecture options of the serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an fpga in order to support security for current and future high bandwidth applications. one of the main findings is that serpent can be implemented with encryption rates beyond 4 gbit/s on current fpgas.  a. j. elbirt c. paar
the impact of synchronization and granularity on parallel systems  in this paper, we study the impact of synchronization and granularity on the performance of parallel systems using an execution-driven simulation technique. we find that even though there can be a lot of parallelism at the fine grain level, synchronization and scheduling strategies determine the ultimate performance of the system. loop-iteration level parallelism seems to be a more appropriate level when those factors are considered. we also study barrier synchronization and data synchronization at the loop iteration level and found both schemes are needed for a better performance.  ding-kai chen hong-men su pen-chung yew
task response time optimization using cost-based operation motion  we present a technique for task response time improvement based on the concept of code motion from the software domain. relaxed operation motion (rom) is a simple yet powerful approach for performing safe and useful operation motion from heavily executed portions of a design task to less visited segments. we introduce here our algorithm, how it differs from other code motion approaches, and its application to the embedded systems domain. results of our investigation indicate that cost-guided operation motion has the potential to improve task response time significantly.  bassam tabbara abdallah tabbara alberto sangiovanni-vincentelli
a fast signature simulation tool for built-in self-testing circuits  this paper describes a fast signature simulator (fss) tool for built- in self- testing (bist) circuits. the fss consists of a simulator generator and a compiled code simulator. the simulator generator comprises a controlling program called the executive and translation software called sim-gen. sim-gen accepts a hardware description language (hdl) representation of the circuit- under-test as its input and produces c code simulation modules comprising boolean relations that represent the structure of the circuit. these c code modules are then compiled and linked together to form the basis of the compiled code simulator. simulation is invoked by executing the compiled c code description of the circuit. the simulation time is minimised by the use of parallel simulation techniques in conjunction with efficient functional models and novel mapping techniques for the lfsrs. performances approaching 5 million gate evaluations per second (geps) have been achieved using the fss.  s. b. tan k. totton k. baker p. varma r. porter
calculation of ramp response of lossy transmission lines using two-port network functions  in this paper, we present a new analytical approach for computing the ramp response of an rlc interconnect line with a pure capacitive load. the approach is based on the two-port representation of the transmission line and accounts for the output resistance of the driver and the line inductance. the results of our analysis are compared with the results of hspice simulations demonstrating the high accuracy of our solution under various values of driver, interconnect, and load impedances.  payam heydari massoud pedram
the trap as a control flow mechanism  in this paper we show how traditional hardware trap handlers can be generalized into an efficient vehicle for conditional branches. these ideas are being used in a vlsi processor under design.  conditional branches are often a major bottleneck in scheduling microinstructions on a horizontally microcoded machine. several tests and conditional branches are frequently ready for scheduling simultaneously, but only one test and branch is possible in a given cycle.  the trap facility is traditionally treated as an interrupt scheme for the notification of exceptional conditions. in this paper we study how the role of the trap mechanism may be expanded to include the parallel evaluation of arbitrary user-specified tests, and the concomitant performance benefits.  j. a. chandross h. v. jagadish a. asthana
an algebra for logic strength simulation  to simulate tri-state logic in a non-pessimistic way, a six valued algebra is shown to be necessary. this is then extended to quin-state logic (strong 0, strong 1, weak 0, weak 1, high impedance) and a fifteen valued algebra. the improved accuracy is as important for fault simulation as for design verification. the requirements for non- pessimistic test generation algebras for tri-state and quin-state logic are also discussed. pessimism in test generation increases the search space and hence the run time.  p. l. flake p. r. moorby g. musgrave
the effect of lut and cluster size on deep-submicron fpga performance and density  we use a fully timing-driven experimental flow [4] [15] in which a set of benchmark circuits are synthesized into different cluster-based [2] [3] [15] logic block architectures, which contain groups of luts and flip- flops. we look across all architectures with lut sizes in the range of 2 inputs to 7 inputs, and cluster size from 1 to 10 luts. in order to judge the quality of the architecture we do both detailed circuit level design and measure the demand of routing resources for every circuit in each architecture.  these experiments have resulted in several key contributions. first, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the lut size (k) and cluster size (n). second, contrary to previous results, we have shown that when the cluster size is greater than four, that smaller luts (size 2 and 3) are almost as area efficient as 4-input luts, as suggested in [11]. however, our results also show that the performance of fpgas with these small lut sizes is significantly worse (by almost a factor of 2) than larger luts. hence, as measured by area- delay product, or by performance, these would be a bad choice. also, we have discovered that lut sizes of 5 and 6 produce much better area results than were previously believed. finally, our results show that a lut size of 4 to 6 and cluster size of between 4 and 10 provides the best area-delay product for an fpga.  elias ahmed jonathan rose
multiple instruction issue in the nonstop cyclone processor  this paper describes the architecture for issuing multiple instructions per clock in the nonstop cyclone processor. pairs of instructions are fetched and decoded by a dual two-stage prefetch pipeline and passed to a dual six-stage pipeline for execution. dynamic branch prediction is used to reduce branch penalties. a unique microcode routine for each pair is stored in the large duplexed control store. the microcode controls parallel data paths optimized for executing the most frequent instruction pairs. other features of the architecture include cache support for unaligned double-precision accesses, a virtually-addressed main memory, and a novel precise exception mechanism.  robert w. horst richard l. harris robert l. jardine
is redundancy necessary to reduce delay  logic optimization procedures principally attempt to optimize three criteria: performance, area and testability. the relationship between area optimization and testability has recently been explored. as to the relationship between performance and testability, experience has shown that performance optimizations can, and do in practice, introduce single stuck-at-fault redundancies into designs. are these redundancies necessary to increase performance or are they only an unnecessary byproduct of performance optimization? in this paper we give a constructive resolution of this question in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. we demonstrate the utility of this algorithm on a well known circuit, the carry-skip adder, and present a novel irredundant design of that adder. as our algorithm may either increase or decrease circuit area, we leave unresolved the question as to whether every circuit has an irredundant circuit that is at least as fast and is of equal or lesser area.  kurt keutzer sharad malik alexander saldanha
mesh arrays and logician: a tool for their efficient generation  this paper introduces a standard structure for vlsi design which we call the mesh array and describes a design tool called logician which minimizes a set of functions for realization in cmos mesh arrays. logician features multi- level logic synthesis through recursive enumeration of each function. several techniques to speed-up the minimization process in logician are described.  j. a. beekman r. m. owens m. j. irwin