waashk/acm huggingface dataset:
a layout system for the random logic portion of mos lsi  the random logic portion of an mos lsi chip intended mainly for a calculator is constructed of an array of mos complex gates, each composed of an mos ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. in this paper, a layout system for this portion of an lsi is described, which is constructed on the basis of a set of optimization heuristics. experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.  isao shirakawa noboru okuda takashi harada sadahiro tani hiroshi ozaki
statistics on logic simulation  the high costs associated with logic simulation of large vlsi based systems have led to the need for new computer architectures tailored to the simulation task. such architectures have the potential for significant speedups over standard software based logic simulators. several commercial simulation engines have been produced to satisfy needs in this area. to properly explore the space of alternative simulation architectures, data is required on the simulation process itself. this paper presents a framework for such data gathering activity by first examining possible sources of speedup in the logic simulation task, examining the sort of data needed in the design of simulation engines, and then presenting such data. the data contained in the paper includes information on subtask times found in standard discrete event simulation algorithms, event intensities, queue length distributions and simultaneous event distributions.  k. f. wong m. a. franklin r. d. chamberlain b. l. shing
software-fault detector for microprocessors  for the realization of the means to develop more reliable software for the microcomputers especially in real time environments, we design a hardware tool called "software-fault detector" which detects software faults such as misaccess to an element beyond the range of an array. the implementation of the mechanism for such address range checks is generally difficult in microprocessor environment, since internal registers are not readily visible to external logics. we introduce an "incremental" key-lock protection scheme into the fixed microcomputer architecture of the intel 8080 because of its popularity and simplicity. in this scheme, a "lock" is a protection code associated with the storage cell, and a "key" is associated with access capability such as address. in each memory access to a cell, a check is made whether a key matched against the lock of the addressed cell. in this paper, we present the details of the scheme and its analysis. further, we present an actual hardware design of the software fault detector. our design methodology is to realize a dector by the use of identical microprocessor 8080s, as an independent one-board module which could be connected to the memory bus of the host system.  kozo itano tetsuo ida
the design of a hardware recognizer for utilization in scanning operations  this paper addresses the design issues and the performance evaluation of a special purpose hardware recognizer device capable of performing pattern matching and text retrieval operations. in addition, the vlsi design and the time and space complexities of the proposed organization are discussed. the structure of the system is based on the concept of the non-deterministic finite state model with a high degree of parallelism incorporated into the design. the system simulates a parallel finite state automaton by utilizing a number of identical units called "cells" which have associative processing capabilities.  the proposed system improves the performance of pattern matching operations by matching several patterns in parallel. because of the similarities between the scanning process during compilation and the pattern matching operations, the proposed module can be used as a hardware scanner. the hardware scanner can be used as an interface between the user and the compiler in the conventional general purpose systems as well as the language oriented or high-level language computers.  a. r. hurson s. shirazi
more wires and fewer luts: a design methodology for fpgas  in designing fpgas, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has look-up tables (luts), and wiring resources. it is difficult to find an optimal solution. in this paper, w e presen t an fpga design methodology to efficiently find well-balanced fpga architectures. the method covers all aspects of fpga development from the architecture- decision process to physical implementation. it has been used to develop a new fpga that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. this indicates that the methodology is effectiv e in dev eloping well- balanced fpgas.  atsushi takahara toshiaki miyazaki takahiro murooka masaru katayama kazuhiro hayashi akihiro tsutsui takaki ichimori ken-nosuke fukami
a generalized channel router  a "generalized" channel router operates on horizontal and vertical channels generated from an irregular cell structure, and is free of a routing grid. such a router can solve virtually any routing problem. it has two major phases: the global routing phase and the channel routing phase. this paper describes both phases as they have been implemented at ti. it concludes with a demonstration of the versatility of the router (it is used to solve the hampton court maze) and with applications of the router in ti's i2l (integrated injector logic) / stl (schottky transistor logic) automatic layout system.  david w. hightower robert l. boyd
automatic vlsi layout verification  xerox has instituted a set of software tools that close the loop between circuit design and mask generation of vlsi and provide checks and analysis along the way. the software includes circuit extraction, capacitance calaulation, nodal analysis and logic recognition as well as interfaces to graphic systems. the systematic method of capturing circuit designs and the software packages for analyzing mask data are described in this paper. the kinds of errors checked and the method of reporting errors are explained.  this paper traces a single design from circuit description to mask making. it shows all the check points and verification tools presently available to a designer at xerox.  the example used for demonstration is the design of a small component of a chip called a cell. it should be pointed out that the tools described are not restricted to cell verification. for the most part they will accommodate up to full chip designs.  laurin williams
constraints from hell; how to tell makes a good fpga (panel)  the fpga development is an extraordinarily complex task, involving many people working in architecture, chip design, software, marketing and production. each tends to focus on their immediate task, and have their own measures of goodness for what they do, as well as very particular constraints relevant to their discipline. in this panel we will discuss these measures and constraints in an attempt to see how they succeed in transcending the artificial borders in each discipline.  an fpga customer presents a set of impossible demands: create a chip that will do whatever he wants, and do it as cheaply as possible, run at the required speed, be available in the right package and have an easy to use software that does everything automatically with no manual intervention and no design iteration.  an fpga architect tries to meet some of these demands. he must address the needs of the greatest number of customers, many of which may be conflicting. what are his metrics? early on in the architecture development, when tools may not be available, how does he make decisions? what are the constraints that force particular types of decisions? what about later?  although software development and architecture go hand in hand, the software group brings additional constraints to the table: having to maintain large chunks of code in the face of major new architectures, interface and integration of external tools supplied by cad vendors (schematic capture, synthesis, simulation, etc.) what measures of goodness are applied in the software development and integration process? how do these affect architectural decisions?  marketing often plays the role of representing the customer, by relaying his demands to the architects and other developers. what is marketing's true goal? depending on whether dilbert holds sway or not, this can be a nefarious or an inspired role.  academics seeking to add knowledge to the community often create various metrics to measure the goodness of their own work such as track count, pin count, logic block count, area models, net delay, path delay, published paper count, happiness of funding agency representatives, etc. do any of these reflect reality that will convey true knowledge?  operations also have their concerns with regard to yields, wafer sort, testing, packaging, and even inventory and shipping. how do these concerns define a measure of goodness for fpgas?  finally, there is the long-term health of the fpga industry itself. have we made progress against gate arrays and standard cells? will the micro-processor sneak up and bite us from behind?  jonathan rose sinan kaptanoglu clive mccarthy rob smith sandip vij steve taylor
cost minimization of partitioned circuits with complex resource constraints in fpgas (poster abstract)  in this paper, we formulated a new cost minimization partition problem with complex resource constraints in large fpgas and proposed a maximum matching and ilp based algorithm to solve it. in traditional partitioning methods, one starts with a random initial partition of the circuit. instead, we proposed a maximum matching based algorithm to generate a feasible initial partition efficiently. the proposed problem is formulated in ilp model. the ilp solver, lingo, is employed to find the number of fpga chips of each type to minimize the total cost. further, a new vertex ordering matching algorithm is proposed to get a smaller cut-size partition. experimental results on the mcnc lgsynth91 benchmark show that circuit partition with multiple resource types has 20% lower cost on average than that use simple resource type fpga. the proposed vertex ordering method reduces the cost by 19% compared with the method without vertex ordering considerations.  yu-chung lin su-feng tseng tsai-ming hsieh
paraspice: a parallel circuit simulator for shared-memory multiprocessors  this paper presents a general approach to parallelizing direct method circuit simulation. the approach extracts parallel tasks at the algorithmic level for each compute-intensive module and therefore is suitable for a wide range of shared-memory multiprocessors. the implementation of the approach in spice2 resulted in a portable parallel direct circuit simulator, paraspice. the superior performance of paraspice is demonstrated on an 8-ce alliant fx/80 using a number of benchmark circuits.  gung-chung yang
a rate selection algorithm for quantized undithered dynamic supply voltage scaling (poster session)  in this paper we propose a novel rate calculation algorithm called quantized rate selection (qrs) for quantized undithered dynamic supply voltage scaling (dsvs) systems. the algorithm monitors the total buffered workload, and where possible selects a ratevalue equal to a quantized rate value. at quantized rate values, energy dissipation of quantized dsvs systems approaches continuous voltage level dsvs systems. our experimental work on fmidct computation using nine video sequences and a 4-level quantized undithered system shows that additional energy savings of 1.4% to 18.5% can be achieved from qrs, compared to the existing averaging technique.  lama h. chandrasena michael j. liebelt
on approximation algorithms for microcode bit minimization  the bit (or width) minimization problem for microprograms is known to be np- complete. motivated by its practical importance, we address the question of obtaining near-optimal solutions. two main results are presented. first, we establish a tight bound on the quality of solutions produced by algorithms which minimize the number of compatibility classes. second, we show that the bit minimization problem has a polynomial time relative approximation algorithm only if the vertex coloring problem for graphs with n nodes can be approximated to within a factor of (logn) in polynomial time.  s. s. ravi d. gu
a hardware assisted design rule check architecture  this paper describes an architecture for design rule checking that uses a small amount of special purpose hardware to achieve a significant speed improvement over conventional methods. a fixed grid raster scan algorithm is used that allows checking of 45 angled edges at a modest cost in performance. operations implemented directly in hardware include width checks, edge condition checks, boolean operations on masks, and shrinking and expansion of masks. hardware support for rasterization is also provided. software in a controlling processor handles all geometric data manipulation. this architecture should be able to check a simple set of design rules on a 300 mil square layout in one and one half minutes, if the controlling processor can provide data quickly enough. layouts have been completed for two of four custom chips used in this architecture, and one has been fabricated and proven functional.  larry seiler
a fault analysis method for synchronous sequential circuits  in this paper we extend the use of the fault analysis method dealing with combinational circuits[1] to synchronous sequential circuits. using the iterative array model, extended forward propagation and backward implication are performed. based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. any stuck fault can be identified, even in a circuit without any initialization sequence. a fault which is covered is tested unconditionally; thus the results obtained would not be invalidated in the presence of untested or untestable lines. examples will be given to demonstrate the ability of our method.  t. y. kuo j. y. lee j. f. wang
formally based static analysis of microcode  algebraic methods have been widely used to find properties of programs, especially for use in compiler optimisation. this paper describes the use of this kind of method to prove the absence of particular errors in microcode, or to detect and locate such errors. in order to show the kind of error which may be found we consider a number of examples. all of these have found errors in practical microcode, written for the perq computer.  j. m. foster
a layout verification system for analog bipolar integrated circuits  a new layout verification system, called alas (alayout analysis system) is presented. its main intention is to tackle the particular verification problems of analog bipolar circuits. at present, the system comprises four main parts: a device recognition program produces a list of devices, a plot program converts these data to a layout- oriented circuit diagram, a connectivity analysis program yields device- oriented or net-oriented descriptions of the derived circuit and a network comparison program tests the consistency of this actual circuit with the intended nominal one. a fifth program, that will calculate the parameters of the actual circuit, is under development.  to derive the actual circuit from layout alas uses geometrical mask data only; no additional circuit information is needed. if not available from the design system, a description of the nominal circuit may be supplied manually in a spice-like input format.  erich barke
low power and high performance design challenges in future technologies  we discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. in particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. functionality of special circuits in the presence of high leakage, sram cell stability, bit line delay scaling, and power consumption in clocks & interconnects, will be the primary design challenges in the future. soft error rate control and power delivery pose additional challenges. all of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. the excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.  vivek de shekhar borkar
fast and accurate estimation of floorplans in logic/high-level synthesis  in many applications such as high-level synthesis (hls) and logic synthesis and possibly engineering change order (eco) we would like to get fast and accurate estimations of different performance measures of the chip, namely area, delay and power consumption. these measures cannot be estimated with high accuracy unless a fairly detailed layout of the chip, including the floorplan and routing is available, which in turn are very costly processes in terms of running time. as we have entered the deep sub-micron era, we have to deal with designs which contain million gates and up. not only we should consider the area occupied by the modules, but we also have to consider the wiring congestion. in this paper we propose a cost function that is, in addition to other parameters, a function of the wiring area. we also propose a method, to avoid running the floorplanning process after _every_ change in the design, by considering the possible changes in advance and generating a floorplan which is _tolerant_ to these modifications, i.e., the changes in the netlist does not dramatically change the performance measures of the chip. experiments are done in the high-level synthesis domain, but the method can be applied to logic synthesis and eco as well. we gain speedups of 184% on the average over the traditional estimation methods used in hls.  kiarash bazargan abhishek ranjan majid sarrafzadeh
design of a low-power cmos baseband circuit for wideband cdma testbed (poster session)  in this paper, the design and performance of a cmos baseband circuit for wcdma direct conversion receiver are presented. consisting of one 5th-order anti- aliasing filter, one 4th-order tunable channel filter, and three variable gain amplifier (vga) stages, the baseband chain provides 72db gain range with 2db gain step and is tunable to select three differentbandwidths (from 5mhz to 20mhz radio-frequency spacing). it dissipates only18mw from a single 3v supply. the input ip3 is 10dbm, and the input-referred noise in the passband is 41nv/$\sqrt{hz}$.  chunlei shi yue wu mohammed ismail
a timing analysis algorithm for circuits with level-sensitive latches  for a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. we developed efficient algorithms based on the modified shortest and longest path method. the computational complexity of our algorithm is generally better than that of known algorithms in the literature. the implementation (cyclopss) has been applied to an industrial chip to verify the clock schedules.  jin-fuw lee donald t. tang c. k. wong
synthesis of concurrent system interface modules with automatic protocol conversion generation  we describe a new high-level compiler called integral for designing system interface modules. the input is a high-level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computations, abstract communication, and low-level behavior. for abstract communication between two communicating modules that obey different i/o protocols, the necessary protocol conversion behaviors are automatically synthesized using a petri net theoretic approach. we present a synthesis trajectory that can synthesize the necessary hardware resources, control circuitry, and protocol conversion behaviors for implementing system interface modules.  bill lin steven vercauteren
an adaptive timing-driven layout for high speed vlsi  an adaptive timing-driven layout system, called june, has been developed. the constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. the placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. experimental results for industrial sea-of-gates chips confirmed effectiveness of this approach.  suphachai sutanthavibul eugene shragowitz
layla: a vlsi layout language  this paper describes layla, a pascal- based hardware description language for the specification of vlsi layouts. the primary application of layla is the development of parameterized cell libraries. important features include pascal's computational power and file i/o facilities, hierarchical (cell- based) layout generation, a run-time design parameter file, an extendible layer set, external compilation, the ability to support different output formats, and the automatic generation of parameterized layla from artwork.  warren e. cory
accuracy management for mixed-mode digital vlsi simulation  accuracy management (am) offers delay-oriented control of simulation accuracy in automated mixed-mode simulation of digital vlsi circuits. am heuristics, with little additional computation, can achieve a required level of accuracy in output timing predictions while insuring computational efficiency by using simulations with appropriate levels of accuracy throughout a circuit. these results are demonstrated through both mathematical predictions on some benchmark circuit topologies, and actual mixed-mode timing simulations on large combinational circuit benchmarks. simulation speedups of 5-10 over corresponding standard, wave-form relaxation-based circuit simulations are demonstrated.  gary l. dare charles a. zukowski
celtic - solving the problems of lsi design with an integrated polycell da system  the major problems associated with lsi design include those of design complexity, documentation, mapping, design verification both functional and physical, physical implementation, and the manufacturing interface. the design aids group at burroughs, cumbernauld, have developed an integrated lsi design system, celtic, which solves these problems with a polycell design approach, direct graphics entry of logic diagrams, and automatic generation of lsi layouts. the system reduces the time required to lay out lsi's from months to weeks.  g. martin j. berrie t. little d. mackay j. mcvean d. tomsett l. weston
designing gate arrays using a silicon compiler  this paper describes a programming environment in which gate array designs can be developed. it allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. the principle features of this are a high-level language for design description, completely automatic layout, and an integrated simulator. the total package can be referred to as a silicon compiler in the gate array design style.  john p. gray irene buchanan peter s. robertson
a variable observation time method for testing delay faults  test methodologies for delay faults usually observe output patterns at a single observation time, and the same observation time is used for all faults in the circuit under test. in this paper we show that use of a single observation time is not advantageous for testing delay faults, and we are able to show that the detection threshold can be dramatically improved by using a testing methodology that allows variable, fault-dependent and output-dependent observation times. a "waveform-type" simulation method is used for calculating detection thresholds for definitely detectable faults. statistical distributions of delay fault detection thresholds are presented for ten benchmark circuits.  wei-wei mao michael d. ciletti