waashk/acm huggingface dataset:
an interactive test data system for lsi production testing  this paper describes a software system, itds, which supplies a chip or module tester with test data. there are two major components to the system: an interactive data entry system, itlg; and a generator of environmental test data, spec/gen. by "conversing" with its user, itlg creates a technology library from a document of circuit specifications. the user does not need to be familiar with the tester. itlg will guide the user by showing him how to enter the necessary data, by auditing his response and by informing him of the accuracy of his response. the spec/gen system uses the technology library from itlg to create a data set of final test values. these values are the result of calculations that consider the technology, tester, and the i/o electrical characteristics of the part number to be tested. this paper also shows how data set for final test is automatically created.  h. d. schnurmann r. m. peters
design for test calculus: an algorithm for dft rules checking  a new one-pass algorithm for checking networks for compliance to a set of design for test (dft) rules is presented. the algorithm is based on a "design for test calculus" which defines various types of signals and nodes in the network, signal sets attached to node's inputs and outputs, and rules for transferring signal sets through nodes. the rule checking is accomplished by examining the characteristic contents of the signal sets transferred. the calculus is capable of handling a wide variety of "test point flip- flops" and test access schemes, and has features that make hierarchical rule checking feasible.  dilip k. bhavsar
vgaua: the variable geometry automated universal array layout system  this paper presents the variable geometry automated universal array (vgaua) fully automatic physical layout program for gate array lsi which uses a single unique metalization pattern to personalize the array design. this fully automatic layout system minimizes the cost and time required for ic design and can be used over a range of array sizes from 800 to 3,500 gates. each array size has its own unique, optimized, fixed geometry design for all levels except the programmable metalization level.  the paper discusses both the topological design which makes the vgaua program feasible and the software which makes the system automatic. the key to the success of the system is that the two items are heavily interrelated and highly interdependent.  david c. smith richard noto fred borgini shanti s. sharma joseph c. werbickas
a new string search hardware architecture for vlsi  this paper presents a new architecture for practical string search hardware design. this architecture is based on the finite state automaton design concept using a character control charge transfer model. the resultant hardware is a set of programmable sequential logic (psl) circuits, each of which consists of a sequential logic and memory parts. the logic part is an array of logical gates, each of which is controlled by the read-out signal from the memory part, to connect the flip-flops. the memory part stores each variable-length pattern string character on a bit line by bit line basis. then, several pattern strings in the memory part can be compared with the serial input data string in parallel, even at a non-anchor mode and an approximate matching mode. this new hardware can be easily implemented in an lsi chip, which allows 8192 pattern string storage using 1 mb ram cells.  k. takahashi h. yamada h. nagai k. matsumi
on global wire ordering for macro-cell routing  in an automatic routing system for macro-cell layout the wiring area is decomposed into a number of smaller regions. these regions are routed separately by a detailed router such as a channel router or a switch-box router. the position of the pins at the junction between two adjacent regions is usually determined by the detailed router. the locality of this 'bottom-up' ordering disregards the global topologies of the nets which usually span several routing regions. this may result in twisted wires, unnecessary vias and waste of area. an algorithm to prevent twisted wires during detailed routing is presented. a consistent order is determined for the junction pins which ensures that no unnecessary wire twisting is introduced. if wires have to cross their intersection will preferably be placed in such a position that the chip area is least affected.  p. groenveld
an automatic test generation algorithm for hardware description languages  a new approach to test generation from hardware description language circuit models has been developed and implemented. the described e-algorithm generates tests for control, operation, and data faults in sequential and combinational logic modeled at the functional level. a symbolic variable notation is introduced to permit systematic fault propagation through control structures. results of the implementation are given for a set of test cases and the application of the algorithm to a semi-custom asic are discussed.  f. e. norrod
hardware support for large atomic units in dynamically scheduled machines  microarchitectures that implement conventional instruction set architectures are usually limited in that they are only able to execute a small number of microoperations concurrently. this limitation is due in part to the fact that the units of work that the hardware treats as indivisible are small. while this limitation is not important for microarchitectures with a low level of functionality, it can be significant if the goal is to build hardware that can support a large number of microoperations executing concurrently. in this paper we address the tradeoffs associated with the sizes of the various units of work that a processor considers indivisible, or atomic. we argue that by allowing larger units of work to be atomic, restrictions on concurrent operation are reduced and performance is increased. we outline the implementation of a front end for a dynamically scheduled processor with hardware support for large atomic units. we discuss tradeoffs in the design and show that with a modest investment in hardware, the run-time advantages of large atomic units can be realized without the need to alter the instruction set architecture.  s. w. melvin m. c. shebanow y. n. patt
an experimental representation for organizational level designs and synthesis  a representation for computer organization is presented. the objectives of this work were to have a representation that permits expression of organizational level designs, can be used for synthesis of logic networks, and serves as a communication medium between system and logic designers. features of the language for design capture and synthesis are identified and discussed. finally an experimental language based on an existing hardware description language, used to test the concepts in the design of the representation is discussed.  jwahar r. bammi
a novel high throughput reconfigurable fpga architecture  with increased logic density due to the shift towards deep submicron technologies (dsm), fpgas have become a viable option for implementing large designs. however, most commercial fpgas, due to their general purpose architectural nature, cannot handle designs which require very high throughput. in this paper, we propose a novel high throughput fpga architecture which tries to combine the high-performance of application specific integrated circuits (asics) and the flexibility afforded by the reconfigurability of fpgas. this architecture utilizes the concept of 'wave- steering' and works best for designs which are highly regular and have almost equal delays along all paths. it has enormous potential in digital signal and image processing applications since a good portion of these applications are regular in nature. preliminary results for some commonly used dsp designs are encouraging and yield throughputs in the neighborhood of 770 mhz in 0.5μ cmos technology.  amit singh luca macchiarulo arindam mukherjee malgorzata marek-sadowska
performance comparison of load/store and symmetric instruction set architectures  is it true that a load/store architecture is both simpler and faster than a symmetric architecture, or does the symmetric architecture offer a potential performance advantage that can be realized by the use of additional hardware?  in order to answer it quantitatively, we simulated two models that were equal in all aspects except the factor that we measure. we found that the load/store model executes 12% more instructions but only 4% more cycles.  d. alpert a. averbuch o. danieli
abstract data types and high-level synthesis  previous data abstraction efforts in software and hardware description have approached abstract data types from a specification and simulation standpoint. this paper addresses the use of abstract data types for high-level synthesis. data types are extended to support don't care information and new synthesis steps are presented. results from a number of realistic design examples indicate that the area and delay of logic implementations can be substantially reduced when data abstraction and appropriate synthesis procedures are incorporated into the high-level synthesis process.  gregory s. whitcomb a. richard newton
a new look at logic synthesis  despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization. however, larger scales of integration have made other design requirements and technology restrictions as important as circuit count, and have increased the cost of making an engineering change. thus it is becoming increasingly important to insure that initial chip designs are correct. this paper outlines an investigation into the feasibility of logic synthesis in this new context. a system is described which will produce a naive implementation automatically from a functional specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture. the use of simple local transformations will insure correct implementations, will isolate technology-specific data, and will allow the total process to be applied to larger vlsi designs. this approach has been tested on the design of a single chip with encouraging results. a prototype synthesis system is now being used to perform further experiments.  john a. darringer william h. joyner
the incorporation of functional level element routines into an existing digital simulation system  cc-tegas3 is a digital logic simulation system containing subsystems which can perform three different modes of simulation. these modes are used for logic or design verification, worst case timing analysis, and fault simulation. the basic device models are for boolean gates, a wide range of flip-flops and latches, and a number of mos elements such as transfer gates. a comprehensive list of functional level device models were incorporated into the system and the resulting system is called cc- tegas4. this approach was considered advantageous for today's technology, and an absolute necessity for the lsi and vlsi technologies that are forthcoming. this paper is concerned with the problems encountered and some of the techniques used to implement these functional level models, and results obtained in terms of reduction in required computer resources needed to simulate a network utilizing these new models.  e. w. thompson patrick karger w. r. read don ross john smith richard von blucher
runtime and quality tradeoffs in fpga placement and routing  many applications of fpgas, especially logic emulation and custom computing, require the quick placement and routing of circuit designs. in these applications, the advantages fpga-based systems have over software simulation are diminished by the long run-times of current cad software used to map the circuit onto fpgas. to improve the run-time advantage of fpga systems, users may be willing to trade some mapping quality for a reduction in cad tool runtimes. in this paper, we seek to establish how much quality degradation is necessary to achieve a given runtime improvement. for this purpose, we implemented and investigated numerous placement and routing algorithms for fpgas. we also developed new tradeoff-oriented algorithms, where a tuning parameter can be used to control this quality vs. runtime tradeoff. we show how different algorithms can achieve different points within this tradeoff spectrum, as well as how a single algorithm can be tuned to form a curve in the spectrum. we demonstrate that the algorithms vary widely in their tradeoffs, with the fastest algorithm being 8x faster than the slowest, and the highest quality algorithm being 5x better than the least quality algorithm. compared to the commercial xilinx cad tools, we can achieve a 3x speed-up by allowing 1.27x degradation in quality, and a factor of 1.6x quality improvement with 2x slowdown.  chandra mulpuri scott hauck
candidate subcircuits for functional module identification in logic circuits  _recovering functional information from existing hardware is a difficult problem in design automation. however, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. often, the only reliable information available about a piece of digital hardware is the hardware itself. documentation, even if it is available, may be outdated or incorrect. existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. the next step in this process is the gate-level to module- level transformation, the focus of this paper. we have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated._  jennifer l. white anthony s. wojcik moon-jung chung travis e. doom
multi-level synthesis for safe replaceability  we describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. we formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observing the input-output behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replacement is potentially unsafe). our condition allows simplification of the state transition diagram of an original design. we use the safe replacement condition to derive a sequential resynthesis method for area reduction of gate-level designs. we have implemented our resynthesis algorithm and we report experimental results.  carl pixley vigyan singhal adnan aziz robert k. brayton
algorithms for accuracy enhancement in a hardware logic simulator  in this paper, we describe a hardware multiple delay logic simulator that incorporates efficient timing analyses algorithms for event cancellations, spike and race analyses and oscillation detection. the algorithms are implemented on a set of reconfigurable processors, arranged in a pipelined configuration. spike analysis is accomplished by dynamic pulse width measurement. both zero and non-zero delay oscillations are detected. results of simulating industrial vlsi chips are presented to illustrate the effectiveness of the algorithms with minimal performance penalty.  p. agrawal r. tutundjian w. dally
a recursive technique for computing lower-bound performance of schedules  we present a fast recursive technique for estimating lower-bound performance of data path schedules. the method relies on the determination of an asapuc a(s soon as possible under constraint) time-step value for each node of the dfg (data-flow graph) that is based on the asapuc values of its predecessor nodes. that is, the lower-bound estimation is applied to each subgraph permitting the derivation of a tight lower bound on the performance of the complete dfg. applying the greedy lower-bound estimator of rim and jain [1994] to each subgraph improves the complete lower bound in more than 50% of the experiments reported in rim and jain [1994], and the cpu time is only about twice as long. the recursive methodology can be extended to exploit other lower-bound techniques, for example, considering other constraints such as the number of busses or registers.  m. langevin e. cerny
a cell-based power estimation in cmos combinational circuits  in this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. based on the model, a cell-based power estimation (cbpe) method is developed to estimate the power dissipation in cmos combinational circuits. in our technique, we first construct a modified state transition graph called stgpe to model the power consumption behavior of a logic gate. then, according to the input signal probabilities and transition densities of the logic gate, we perform an efficient method to estimate the expected activity number of each edge in the stgpe. finally, the energy consumption of a logic gate is calculated by summing the energy consumptions of each edge in stgpe. for a set of benchmark circuits, experimental results show that the power dissipation estimated by cbpe is on average within 10-percent errors as compared to the exact spice simulation while the cpu time is more than two order-of-magnitudes faster.  jiing-yuan lin tai-chien liu wen-zen shen
facom 6443 magneto-optic disk sub-system  there has always been a strong market requirement for rewritable optical disk drive as a follow-on product to read-only and write-once type optical disks. fujitsu has been researching magneto-optic recording technologies for rewritable optical disk, and has developed a disk sub-system with initiative of the national aerospace laboratory (nal) in tokyo. the drive has a large storage capacity of 8.9 gb/spindle with a few seconds of access time. it can store data economically in a small floor space, and it can be used as a supplement or partial alternative to magnetic disk drives or tape library units. the sub-system will be used from the beginning of 1989. this paper explains the drive technologies, support software as well as the application of this new sub- system at nal.  y. inouye s. hatayama
improving direct-mapped cache performance by the addition of a small fully- associative cache and prefetch buffers  projections of computer technology forecast processors with peak performance of 1,000 mips in the relatively near future. these processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. this paper presents hardware techniques to improve the performance of caches.  miss caching places a small fully-associative cache between a cache and its refill path. misses in the cache that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache. small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches.  victim caching is an improvement to miss caching that loads the small fully- associative cache with the victim of a miss and not the requested line. small victim caches of 1 to 5 entries are even more effective at removing conflict misses than miss caching.  stream buffers prefetch cache lines starting at a cache miss address. the prefetched data is placed in the buffer and not in the cache. stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. stream buffers are more effective than previously investigated prefetch techniques at using the next slower level in the memory hierarchy when it is pipelined. an extension to the basic stream buffer, called multi-way stream buffers, is introduced. multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams.  together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of six large benchmarks.  norman p. jouppi
on fault detection in cmos logic networks  this paper considers the problem of detecting faults in cmos combinational networks. effects of open and short faults in cmos networks are analyzed. it is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. a simple and efficient heuristic method for organizing the test sequence to detect all single faults in a cmos network is suggested.  kuang-wei chiang zvonko g. vranesic
microprogramming instruction systolic arrays  the instruction systolic array (isa) is a programmable parallel architecture suitable for vlsi implementation. this paper presents a generalization of the isa, called the microprogrammed isa, which uses simple microprogramming techniques. microprogrammed isas use dynamic microcodes whose length and contents are tailor made to the current program to be executed, and this can be efficiently implemented in vlsi. here, microprogramming has the novel advantage of extending the range of algorithms that can be implemented on a given isa. in particular, microprogramming can extend an isa's effective communication abilities. also, the reduction of the program input bandwidth (and pinout) afforded by microprogramming is even more important on large- scale mimd architectures, such as the isa. this paper also presents a weakest precondition semantics for the (microprogrammed) isa model, which provides a means for verifying microprogrammed isa programs. the semantics is modeled at the micro level, and has potential in the optimization of the microcodes of isa programs.  p. m. lenders h. schröder p. strazdins
universal switch modules for fpga design  a switch module m with w terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (i.e., the number of nets on each side of m is at most w) is simultaneously rout able through m. in this article, we present a class of universal switch modules. each of our switch modules has 6wswitches and switch-module flexibility three (i.e, fs=3). we prove that no switch module with less than 6w switches can be universal. we also compare our switch modules with those used in the xilinx xc4000 family fpgas and the antisymmetric switch modules (with fs=3) suggested by rose and brown [1991]. although these two kinds of switch modules also have fs=3 and 6w switches, we show that they are not universal. based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25% more routing instances, compared with the xc4000-type switch module of the same size. experimental results demonstrate that our universal switch modules improve routability at the chip level. finally, our work also provides a theoretical insight into the important observation by rose and brown [1991] (based on extensive experiments) that fs=3 is often sufficient to provide high routability.  yao-wen chang d. f. wong c. k. wong
a gate level model for cmos combinational logic circuits with application to fault detection  a procedure to derive gate level equivalent circuits for cmos combinational logic circuits is given. the procedure leads to a model containing and, or and not gates. specifically it does not require memory elements as does an earlier model and also uses fewer gates. it is shown that tests for classical stuck- at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled cmos circuit.  sudhakar m. reddy vishwani d. agrawal sunil k. jain