waashk/acm huggingface dataset:
an ethernet compatible low cost/high performance communication solution  the lan-hub is a new local area network designed to combine the properties of several existing lan standards to provide highly reliable communication at a relatively lower cost per station, improve network capacity/delay performance and increase the lan user's flexibility in configuring his network. the lan- hub network is configured around the codex 4320 lan-hub communication controllers which allow up to eight ethernet/ieee 802.3 stations to transparently share one network transceiver or rf modem. each lan-hub controller executes a fair, collision free, arbitration among its local stations attached to its lan ports, using a patented collision avoidance algorithm. the hub's rear panel further provides a network port which can be attached to a standard 802.3 transceiver, to another hub or terminated in a loop back mode. the hubs, thus, allow stations to be organized in a standalone star network, in a "cascading" star configuration, or as an integrated bus/star network. when organized as star or cascaded star networks, the hub controllers provide highly reliable and controlled, collision free, bandwidth allocation suitable for applications such as cpu room clusters. alternately, in a bus configuration the hubs support an ethernet type bus network, with random access channel control. in the latter configuration the hubs provide a lower cost/higher performance solution for bursty traffic users, since they reduce cabling requirements, decrease cost by sharing each transceiver among several lan stations and improve network throughput/delay performance by eliminating local collisions. the lan-hub is thus effective in creating a local communication solution with a significant degree of flexibility in choosing the network layout and the type of service, random or deterministic, provided to the network users.  i. chlamtac a. herman
predicting rf coverage in large environments using ray-beam tracing and partitioning tree represented geometry  we present a system for efficient prediction of rf power distribution in site specific environments using a variation of ray tracing, which we called ray- beam tracing. the simulation results were validated against measured data for a number of large environments with good statistical correlation between the two. we represent geometric environments in full 3d which facilitates rooftop deployment along with any other 3d locations. we use broadcast mode of propagation, whose cost increases more slowly with an increase in the number of receiving bins. the scheme works well both for indoor and outdoor environments. simple ray tracing has a major disadvantage in that adjacent rays from a transmitter diverge greatly after large path lengths due to multiple reflections, such that arbitrarily large geometric entities could fall in between these rays. this results in a sampling error problem. the error increases arbitrarily as the incident angle approaches $90^\circ $. the problem is addressed by introducing the notion of beams while retaining the simplicity of rays for intersection calculations. a beam is adaptively split into child beams to limit the error. a major challenge for computational efficiency is to quickly determine the closest ray-surface intersection. we achieve this by using partitioning trees which allows representation of arbitrarily oriented polygonal environments. we also use partitioning trees for our full 3d interactive visualization along with interactive placement of transmitters, receiving bins, and querying of power.  a. rajkumar b. f. naylor f. feisullin l. rogers
exploiting data parallelism in signal processing on a dataflow machine  this paper will show that the massive data parallelism inherent to most signal processing tasks may be easily mapped onto the parallel structure of a data flow machine. a special system called structflow has been designed to optimize the static data flow model for hardware efficiency and low latency. the same abstractions from the general purpose data flow model that lead to a quasi systolic operation of the processing elements make explicit flow control of the data tokens as they pass through the arcs of the flow graph obsolete. we will describe the architecture of the system and discuss the restrictions on the structure of the flow graphs.  p. nitezki
architecture of a message-driven processor  we propose a machine architecture for a high-performance processing node for a message-passing, mimd concurrent computer. the principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.  w. j. dally l. chao a. chien s. hassoun w. horwat j. kaplan p. song b. totty s. wills
an effective low powr design methodology based on interconnect prediction  the demand for low power digital systems has motivated significant research. however, the power estimation at the logic level is a difficult task because interconnect plays a role in determining the total chip power dissipation. as a result, the power optimization at the logic level may be inaccurate due to the lack of physical place and route information. in this paper, we will present an effective low power design methodology based on interconnect prediction at the logic level. the proposed design methodology includes the method to create wire load models and the design procedures to select the appropriate wire load model during synthesis. the main distinction of the proposed approach is that it constructs physical hierarchy during the synthesis stage. by taking advantage of wire load models, the proposed design methodology is able to develop low power digital systems while speeding up the design process. experimental data shows that this design methodology achieved very good results.  shih-hsu huang
receiver-initiated busy-tone multiple access in packet radio networks  the aloha and carrier sense multiple access (csma) protocols have been proposed for packet radio networks (prn). however, csma/cd which gives superior performance and has been successful applied in local area networks cannot be readily applied in prn since the locally generated signals will overwhelm a remote transmission, rendering it impossible to tell whether a collision has occurred or not. in addition, csma and csma/cd suffer from the "hidden node" problem in a multihop prn. in this paper, we develop the receiver-initiated busy-tone multiple access protocol to resolve these difficulties. both fully connected and multihop networks are studied. the busy tone serves as an acknowledgement and prevents conflicting transmissions from other nodes, including "hidden nodes".  c. wu v. li
phs terminating call control  this paper describes terminating call control for personal handyphone system (phs), which is achieved by simultaneously forwarding terminating call control messages to multiple interfaces. the network assisted reforwarding (nar) scheme in which a terminating call control message is reforwarded after a certain period of time to improve the likelihood of its receipt by the personal station (ps), is described. the nar scheme is modeled and analyzed. this paper also proposes an enhanced nar (e-nar) scheme in which the terminating call control messages are reforwarded only if the response is not received within a certain time-period. the e-nar scheme is modeled, analyzed and compared with the nar scheme. finally, a secure control method that prevents fraud for terminating call control is proposed.  shigefusa suzuki takeshi ihara yoshiaki shikata
source-oriented topology aggregation with multiple qos parameters in hierarchical networks  in this paper, we investigate the problem of topology aggregation (ta) for scalable, qos-based routing in hierarchical networks. ta is the process of summarizing the topological information of a subset of network elements. this summary is flooded throughout the network and used by various nodes to determine appropriate routes for connection requests. a key issue in the design of a ta scheme is the appropriate balance between compaction and the corresponding routing performance. the contributions of this paper are twofold. first, we introduce a source-oriented approach to ta, hich provides better performance than existing approaches. the intuition behind this approach is that the advertised topology-state information is used by source nodes to determine tentative routes for connection requests. accordingly, only information relevant to source nodes needs to be advertised. we integrate the source-oriented approach into three new ta schemes that provide different trade-offs between compaction and accuracy. second, we extend our source- oriented approach to multi-qos-based ta. a key issue here is the determination of appropriate values for the multiple qos parameters associated with a logical link. two new approaches to computing these values are introduced. extensive simulations are used to evaluate the performance of out proposed schemes.  turgay korkmaz marwan krunz
high-speed processing schemes for summation type and iteration type vector instructions on hitachi supercomputer s-820 system  the hitachi supercomputer s-820 system has been developed as hitachi's top end supercomputer. it is also rated as one of the most powerful supercomputers in the world.  among the vector instructions which supercomputers support, summation type vector instructions and iteration type vector instructions are not suitable for parallel processing, since elements to be processed are not independent in these instructions. the s-820 employs high-speed processing schemes for summation type vector instructions and iteration type vector instructions; the performance of summation type instructions is enhanced by high-speed post- processing scheme and the performance of iteration type instructions is enhanced by high-speed parallelizing scheme for iteration arithmetic.  thanks to these schemes, the execution speeds for kernel 3 and kernel 4 of the lawrence livermore laboratory's 24 kernels become 838.7 mflops and 258.5 mflops respectively, and those for kernel 5, kernel 6 and kernel 11 of the lawrence livermore laboratory's 14 kernels become 114.6 mflops, 111.8 mflops and 98.4 mflops, respectively.  h. wada k. ishil m. fukagawa h. murayama s. kawabe
resource management in a distributed internetwork environment  the resource management system is designed to support location-transparent access to resources and to improve performance in a distributed internetwork environment. in this environment, access to one of several machines that have a given resource is determined by the effective bandwidth and reliability of internetwork communications, the ability to interact with the machines offering the resources, and the load on those machines. using these criteria, the resources management system enables applications to determine and obtain access to the "best" copy of a resource. should the resource become unavailable from one machine, the resource management system can dynamically direct the applications to another machine known to offer the same resource. this paper discusses some of the problems that motivated the design, an implementation for a unix workstation environment, and future directions for the resource management system.  g. skinner j. m. wrabetz louis schreir
performance analysis of circuit switching, baseline interconnection networks  performance evaluation, using both analytical and simulation models, of circuit switching baseline networks is presented. two configurations of the baseline networks, single and dual, are evaluated. in each configuration, two different conflict resolution strategies, drop and hold, are tried to see the performance difference. our analytical models are based on a more realistic assumption. new analyses are given and are verified by simulation results. in single network configuration, it is shown that the drop strategy is better than the hold strategy in the case that the data transfer time is longer than 10 cycles under a high request rate. in the dual network configuration, five different communication strategies are investigated and the optimum performance level is shown to be dependent on the length of the data transfer time.  manjai lee chuan-lin wu
impossibility of distributed consensus with one faulty process  the consensus problem involves an asynchronous system of processes, some of which may be unreliable. the problem is for the reliable processes to agree on a binary value. in this paper, it is shown that every protocol for this problem has the possibility of nontermination, even with only one faulty process. by way of contrast, solutions are known for the synchronous case, the "byzantine generals" problem.  michael j. fischer nancy a. lynch michael s. paterson
multiplexing issues in communication system design  this paper considers some of the multiplexing issues in communication system design by examining overall system issues. in particular, we distinguish physical multiplexing of resources from logical multiplexing of streams. both physical- resource multiplexing and logical multiplexing determine the service that can be provided by a communication system. we also discuss two issues affected by logical multiplexing - flow control and the relationship between control and data streams of a connection.  we conclude that the granularity of physical resource sharing must be fine enough to meet the jitter and latency constraints of demanding applications. also, high speed communication systems should restrict their logical multiplexing to layer 3.  c. c. feldmeier
binary translation and architecture convergence issues for ibm system/390  we describe the design issues in an implementation of the esa/390 architecture based on binary translation to a very long instruction word (vliw) processor. during binary translation, complex esa/390 instructions are decomposed into instruction "primitives" which are then scheduled onto a wide-issue machine. the aim is to achieve high instruction level parallelism due to the increased scheduling and optimization opportunities which can be exploited by binary translation software, combined with the efficiency of long instruction word architectures. a further aim is to study the feasibility of a common execution platform for different instruction set architectures, such as esa/390, rs?6000, as/400 and the java virtual machine, so that multiple systems can be built around a common execution platform.  michael gschwind kemal ebcioglu erik altman sumedh sathaye
a scalable web cache consistency architecture the rapid increase in web usage has led to dramatically increased loads on the network infrastructure and on individual web servers. to ameliorate these mounting burdens, there has been much recent interest in web caching architectures and algorithms. web caching reduces network load, server load, and the latency of responses. however, web caching has the disadvantage that the pages returned to clients by caches may be _stale_, in that they may not be consistent with the version currently on the server. in this paper we describe a scalable web cache consistency architecture that provides fairly tight bounds on the staleness of pages. our architecture borrows heavily from the literature, and can best be described as an _invalidation_ approach made scalable by using a caching hierarchy and application-level multicast routing to convey the invalidations. we evaluate this design with calculations and simulations, and compare it to several other approaches. haobo yu lee breslau scott shenker
an inclusive session level protocol for distributed applications  the design of an inclusive session level protocol targeted at distributed applications on local networks is presented. the session protocol is motivated by the observation that application requirements, as well as network characteristics, for current and future distributed systems are not well matched to available protocol suites. the nature of services provided in the proposed protocol are derived from typical application requirements, and include group communications, synchronization and recovery, and integrated distributed primitives such as mutual exclusion and consensus. the protocol is also influenced by the characteristics of typical local networks that support sequenced delivery with data integrity, have low latency and high throughput, and are well suited to global addressing schemes. initial experiences with a test implementation indicate that high level service support is valuable and can be provided with good performance.  v. s. sunderam
a scalable wireless virtual lan  this paper presents a wireless virtual local area network (wvlan) to support mobility in ip-over-atm local area networks. mobility is handled by a joint atm-layer handoff for connection rerouting and mac-layer handoff for location tracking, such that the effects of mobility are localized and transparent to the higher-layer protocols. different functions, such as address resolution protocol (arp), mobile location, and atm connection admission are combined to reduce protocol overhead and front-end delay for connectionless packet transmission in connection-oriented atm networks. the proposed wvlan, through the use of atm technology, provides a scalable wireless virtual lan solution for ip mobile hosts.  zhao liu malathi veeraraghavan kai y. eng
escrow techniques for mobile sales and inventory applications  we address the design of architectures and protocols for providing mobile users with integrated personal information services and applications (pisa), such as personalized news and financial information, and mobile database access. we present a system architecture for delivery of pisa based on replicated distributed servers connected to users via a personal communications services (pcs) network. the pisa architecture partitions the geographical coverage area into service areas, analogous to pcs registration areas, each of which is served by a single local server. when a user moves from one service area to another, the service is provided by the new local server. this is accomplished by a service handoff, analogous to a pcs call handoff, which entails some context information transfer from the old to the new server. we focus on the mobile sales and inventory application as an example of a pisa with a well- defined market segment. we design a database management protocol for supporting both mobile and stationary salespersons. our design uses the site- transaction escrow method, thus allowing faster responses to mobile clients, minimizing the amount of context information which must be transferred during a service handoff, and allowing mobile clients to operate in disconnected mode by escrowing items on their local disks. we develop a formal model for reasoning about site-transaction escrow, and develop a scheme for performing dynamic resource reconfiguration which avoids the need for time-consuming and costly database synchronization operations (i.e., a two-phase commit) when the mobile sales transaction completes. a further refinement to the scheme avoids an n-way two-phase commit during resource reconfiguration operations, replacing it with several simpler two-phase commits.  narayanan krishnakumar ravi jain
an architectural framework for migration from cisc to higher performance platforms  we describe a novel architectural framework that allows software applications written for a given complex instruction set computer (cisc) to migrate to a different, higher performance architecture, without a significant investment on the part of the application user or developer. the framework provides a hardware mechanism for seamless switching between two instruction sets, resulting in a machine that enhances application performance while keeping the same program behavior (from a user perspective). high execution speed on migrated applications is achieved through automated translation of the object code of one machine to that of the other, using advanced global optimization and scheduling techniques. issues affecting application behavior, such as precise exceptions, as well as self-modifying code, are addressed. relaxation of full compatibility on these issues lead to further possible performance gains, encouraging applications to adopt the newer architecture.  the proposed framework offers a path for moving from complex instruction set computers (ciscs) to newer architectures, such as reduced instruction set computers (riscs), superscalars, or very long instruction word (vliw) machines, while protecting the extensive economic investment represented by existing software. to illustrate our approach, we show how system code written (and compiled) for the ibm system/390 can yield fine-grain parallelism, as it is targeted for execution by a vliw machine, with encouraging performance results.  gabriel m. silberman kemal ebcioglu
efficient mapping of algorithms to single-stage interconnections  in this paper, we consider the problem of restructuring or transforming algorithms to efficiently use a single-stage interconnection network. all algorithms contain some freedom in the way they are mapped to a machine. we use this freedom to show that superior interconnection efficiency can be obtained by implementing the interconnections required by the algorithm within the context of the algorithm rather than attempting to implement each request individually. the interconnection considered is the bidirectional shuffle- shift. it is shown that two algorithm transformations are useful for implementing several lower triangular and tridiagonal system algorithms on the shuffle-shift network. of the 14 algorithms considered, 85% could be implemented on this network. the transformations developed to produce these results are described. they are general-purpose in nature and can be applied to a much larger class of algorithms.  robert h. kuhn
data buffering: run-time versus compile-time support  data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. the memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). this paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).  a utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. this paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). this paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. it shows the utility increase of applying register allocation for multiple register sets. the paper also shows a potential utility decrease inherent to stack buffers. the observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion  h. mulder