waashk/acm huggingface dataset:
on designing ulm-based fpga logic modules  in this paper, we give a method to design fpga logic modules, based on an extension of classical work on designing universal logic modules (ulm). specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. thus, a lot of functions can be implemented using a single logic module. the significance of our work lies in our ability to generate a large set of such logic modules. a choice can be made from this set based on design criteria. we demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by actel's fp-gas. our functions can specialize to up to 23 times the number of functions that actel functions can. we also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of actel modules. we demonstrates the effectiveness of these modules in mapping benchmark circuits. we observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of actel's on these circuits.  shashidhar thakur d. f. wong
pace - a microprogram evaluation system  this paper describes pace (product assurance code evaluation) system, a tool for evaluating microprograms. pace incorporates both static analysis and dynamic analysis capabilities and it provides features that enable systematic and comprehensive evaluations of large-scale microcoded systems.  the pace static analysis capability performs a control flow analysis of the code being evaluated, reports various anomalous program constructs, and generates a program flow graph that is subsequently employed by pace's dynamic analysis procedures.  the pace dynamic analysis capability uses encoded execution trace data to produce microcode test-coverage reports and formatted code-execution traces. the dynamic analysis capability provides quantitative code execution coverage data that enables an assessment of testing thoroughness and is useful in the identification of effective regression test cases.  robert e. skibbe
general purpose router  numerous solutions to the problem of detailed routing of wires on a chip have been proposed for two routing layers but few are general enough to also handle switchboxes, more than two layers, variable channel widths, or multiple-layer problems with stacked terminals (3-d routing) without extensive modifications. we propose a different routing approach that not only can solve the two layer problem but the other problems as well. the inherent parallelism of the approach lead to a coarse-grained parallel algorithm.  r. j. enbody h. c. du
a study of i/o behavior of perfect benchmarks on a multiprocessor  the i/o behavior of some scientific applications, a subset of perfect benchmarks, executing on a multiprocessor is studied. the aim of this study is to explore the various patterns of i/o access of large scientific applications and to understand the impact of this observed behavior on the i/o subsystem architecture. i/o behavior of the program is characterized by the demands it imposes on the i/o subsystem. it is observed that implicit i/o or paging is not a major problem for the applications considered and the i/o problem is mainly manifest in the explicit i/o done in the program. various characteristics of i/o accesses are studied and their impact on architecture design is discussed.  a. l. narasimha reddy prithviraj banerjee
algebraic analysis of nondeterministic behavior  this paper is concerned with the analysis of design errors that lead to unpredictable response of digital systems. besides classical topics, such as hazards and races, the analysis of malfunctions in real circuits is also included. after defining the notion of behavior and nondeterministic response, a general approach for detecting such design problems through algebraic analysis is presented. compared with existing simulation methods, the algebraic technique provides results of improved accuracy. another basic advantage is the ability to accomodate modular synthesis of digital systems.  examples show how the proposed methods deal with sequential circuits under various delay assumptions. in particular, analysis of designs based on nominal delay parameters and on window delays is presented. a novel method, aiming at spike detection, is also presented. the ability of the algebraic analysis to detect errors in a modular design environment is illustrated by means of an example.  finally, the topic of nondeterministic behavior at rtl is briefly discussed. notably, an algebraic method for deriving setup and hold time constraints from the circuit delay parameters is proposed.  s. leinwand t. lamdan
board-level multiterminal net routing for fpga-based logic emulation  we consider a board-level routing problem applicable to fpga-based logic emulation systems such as the realizer system [varghese et al. 1993] and the enterprise emulation system [maliniak 1992] manufactured by quickturn design systems. optimal algorithms have been proposed for the case where all nets are two-terminal nets [chan and schlag 1993; mak and wong 1995]. we show how multiterminal nets can be handled by decomposition into two-terminal nets. we show that the multiterminal net decomposition problem can be modeled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. a network flow-based algorithm that solves both problems is proposed. it determines if there is a feasible decomposition and gives one whenever such a decomposition exists.  wai-kei mak d. f. wong
wattch: a framework for architectural-level power analysis and optimizations  power dissipation and thermal issues are increasingly significant in modern processors. as a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. in addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.  this paper presents wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. wattch is 1000x or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. this paper presents several validations of wattch's accuracy. in addition, we present three examples that demonstrate how architects or compiler writers might use wattch to evaluate power consumption in their design process.  we see wattch as a complement to existing lower- level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. it also opens up the field of power- efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar simplescalar framework.  david brooks vivek tiwari margaret martonosi
palace: a layout generator for scvs logic blocks  a novel approach to the automatic layout synthesis of dynamic cmos circuits is presented. a set of logic expressions is realized in a row of cells. taking multi-level boolean expressions as input, logic transistors are placed and routed. efficient solutions are achieved by permuting the variables of the expressions and by row folding. the layout is designed on a coarse grid taking timing requirements into account and afterwards adapted to the geometric design rules by a compactor. a comparison to handcrafted layouts shows that the results of palace are nearly equivalent. at the same time the design productivity is increased significantly.  knut m. just edgar auer werner l. schiele alexander schwaferts
the ispd98 circuit benchmark suite  from 1985-1993, the mcnc regularly introduced and maintained circuit benchmarks for use by the design automation community. however, during the last five years, no new circuits have been introduced that can be used for developing fundamental physical design applications, such as partitioning and placement. the largest circuit in the existing set of benchmark suites has over 100,000 modules, but the second largest has just over 25,000 modules, which is small by today's standards. this paper introduces the ispd98 benchmark suite which consists of 18 circuits with sizes ranging from 13,000 to 210,000 modules. experimental results for three existing partitioners are presented so that future researchers in partitioning can more easily evaluate their heuristics.  charles j. alpert
a mixed-mode simulator  to provide flexibility and efficiency in logic and timing verification of mos vlsi circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. such a capability is provided by the mixed-mode simulator described here. this simulator allows different elements of a circuit to be modeled and simulated at different levels of detail. the modeling levels are mos transistor level, logic gate level and functional level. the simulation levels are timing, multiple delay and unit delay. the simulator is being used on production lsi chips and its performance is discussed.  v. d. agrawal a. k. bose p. kozak h. n. nham e. pacas-skewes
configuration compression for fpga-based embedded systems  fpgas are a promising technology for developing high-performance embedded systems. the density and performance of fpgas have drastically improved over the past few years. consequently, the size of the configuration bit-streams has also increased considerably. as a result, the cost-effectiveness of fpga- based embedded systems is significantly affected by the memory required for storing various fpga configurations. this paper proposes a novel compression technique that reduces the memory required for storing fpga configurations and results in high decompression efficiency. decompression efficiency corresponds to the decompression hardware cost as well as the decompression rate. the proposed technique is applicable to any sram-based fpga device since configuration bit-streams are processed as raw data. the required decompression hardware is simple and is independent of the individual semantics of configuration bit-streams or specific features of the on-chip configuration mechanism. moreover, the time to configure the device is not affected by our compression technique. using our technique, we demonstrate up to $41 \%$ savings in memory for configuration bit-streams of several real- world applications.  andreas dandalis viktor k. prasanna
test generation for lsi  a new automatic test generation approach for lsi circuits has been presented in the companion papers [1,2]. in this paper we generate tests for a typical lsi circuit using the new approach. the goal of this study is to gain insight into the problems involved in using the test generation procedures. a formal model c for a 1-bit microprocessor slice is defined which has all the main features of commercially available bit slices such as the am2901. the circuit c is modeled as a network of interconnected functional modules. the functions of the individual modules are described using binary decision diagrams, or equivalently using experiments derived from the diagrams. using our test generation technique, we derive tests for the circuit c capable of detecting various faults covered by our fault model [1]. it is shown that backtracking is rarely needed while generating tests for c. also, we show that generating a multiple vector test is not required for any of the faults considered in the study. the length of the circuit's test sequence is significantly reduced using the fault collapsing method. a discussion of how to model some of the features of lsi circuits that are not included in the circuit c is presented. a comparison between the length of the test generated by our method and other manually-generated ones is also presented.  magdy s. abadir hassan k. reghbati
timing verification by formal signal interaction modeling in a multi-level timing simulator  a new multi-level macromodeling technique for timing simulation has been developed. this technique is based upon the modeling of the behavior of subcircuits under single input changes. the possible interactions between multiple input changes determine the range of validity of the models. a formal method for developing the model validity conditions is presented. this work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. the availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. as a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.  j. benkoski a. j. strojwas
an exact solution to the minimum size test pattern problem this article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. this problem has different applications in testing, including the identification of "don't care" conditions to be used in the synthesis of built-in self-test (bist) logic. the proposed solution is based on an integer linear programming (ilp) formulation which builds on an existing propositional satisfiability (sat) model for test pattern generation. the resulting ilp formulation is linear on the size of the original sat model for test generation, which is linear on the size of the circuit. nevertheless, the resulting ilp instances represent complex optimization problems, that require dedicated ilp algorithms. preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ilp algorithm. paulo f. flores horácio c. neto joão p. marques-silva
generating highly-routable sparse crossbars for plds  a method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. the evaluation method uses a network flow algorithm to accurately compute the percentage of random test vectors that can be routed. the construction method attempts to maximize the spread of the switch locations, such that any given subset of input wires can connect to as many output wires as possible. based on hall's theorem, we argue that this increases the likelihood of routing.  the hardest test vectors to route are those which attempt to use all of the crossbar outputs. results in this paper show that area-efficient sparse crossbars can be constructed by providing more outputs than required and a sufficient number of switches. in a few specific case studies, it is shown that sparse crossbars with about 90% fewer switches than a full crossbar can be constructed, and these crossbars are capable of routing over 95% of randomly chosen routing vectors. in one case, a new switch matrix which can replace the one in the altera flex8000 family is shown. this new switch matrix uses approximately 14% more transistors, yet can increase the routability of the most difficult test vectors from 1% to over 96%.  guy lemieux paul leventis david lewis
low power techniques and design tradeoffs in adaptive fir filtering for prml read channels  in this paper, we describe area and power reduction techniques for a low- latency adaptive finite-impulse response filter for magnetic recording read channel applications. various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. a parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low- area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. area, speed and power comparisons with other low- power implementation options are also shown. the proposed filter has been fabricated using a 0.18 l-effective cmos technology and operates at 550 msamples/s.  khurram muhammad robert b. staszewski poras t. balsara
gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories  deep-submicron cmos designs have resulted in large leakage energy dissipation in microprocessors. while sram cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appli?ions. this paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruc?n caches. we propose, gated-vdd, a circuit-level technique to gate the supply voltage and reduce leakage in unused sram cells. our results indicate that gated-vdd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.  michael powell se-hyun yang babak falsafi kaushik roy t. n. vijaykumar
2n-way jump microinstruction hardware and an effective instruction binding method  a scheme is developed by which multiway microprogram jumps may be made to any of 2n next possible microinstructions as a function of any selection of n > 1 logically independent tests. an efficient method of binding microinstructions to memory locations allows this to be done at very low cost, both in terms of speed and hardware.  independent simultaneous tests are a necessity if horizontally microcodable machines are to continue to get wider, since algorithms presumably have fixed operations/tests ratios. this scheme will give parallelizers for such machines maximum flexibility in rearranging flow control.  joseph a. fisher
verification of hardware descriptions by retargetable code generation  this paper proposes a new method for hardware verification. the basic idea is the application of a retargetable compiler as verification tool. a retargetable compiler is able to compile programs into the machine code of a specified hardware (target). if the program is the complete behavioural specification of the target, the compiler can be used to verify that a properly programmed structure implements the behaviour. methods, algorithms and applications of an existing retargetable compiler are described.  l. nowak p. marwedel
multi-level logic optimization by implication analysis  this paper proposes a new approach to multi-level logic optimization based on atpg (automatic test pattern generation). previous atpg-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. we show that the atpg-based method presented here allows (in principle) the transformation of a given combinational network c into an arbitrary, structurally different but functionally equivalent combinational network c'. furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. by identifying indirect implications between signals in the circuit, transformations can be derived which are "good" candidates for the minimization of the circuit. in particular, it is shown that recursive learning can derive "good" boolean divisors justifying the effort to attempt a boolean division. for 9 out of 10 iscas-85 benchmark circuits our tool hannibal obtains smaller circuits than the well-known synthesis system sis.  wolfgang kunz prem r. menon
efficient algorithms for acceptable design exploration  in this paper, we present an efficient approach to find effective module selections under resource, latency, and power constraints. the framework contains two phases: choosing a resource configuration, and determining a module binding for each resource. the first phase applies _inclusion scheduling_ to estimate generic resources required. in the second phase, _module utility_ measurement is used to determine module selections. a heuristic which perturbs module utility values until they lead to superior selections according to design objectives are also proposed. the experiments on well-known benchmarks show the effectiveness of the approach when comparing the obtained module selections with the results from enumerating all module selections, as well as mssr and psga.  chantana chantrapornchai edwin h.-m. sha xiaobo hu
the case for sram main memory the growing cpu-memory gap is resulting in increasingly large cache sizes. as cache sizes increase, associativity becomes less of a win. at the same time, since costs of going to dram increase, it becomes more valuable to be able to pin critical data in the cache---a problem if a cache is direct-mapped or has a low degree of associativity. something else which is a problem for caches of low associativity is reducing misses by using a better replacement policy. this paper proposes that l2 cache sizes are now starting to reach the point where it makes more sense to manage them as the main memory of the computer, and relegate the traditional dram main memory to the role of a paging device. the paper details advantages of an sram main memory, as well as problems that need to be solved, in managing an extra level of virtual to physical translation. philip machanick
boolean matching for complex plbs in lut-based fpgas with application to architecture evaluation  in this paper, we developed boolean matching techniques for complex programmable logic blocks (plbs) in lut-based fpgas. a complex plb can not only be used as a k-input lut, but also can implement some wide functions of more than k variables. we apply previous and develop new functional decomposition methods to match wide functions to plbs. we can determine exactly whether a given wide function can be implemented with a xc4000 clb or other three plb architectures (including the xc5200 clb). we evaluate functional capabilities of the four plb architectures on implementing wide functions in mcnc benchmarks. experiments show that the xc4000 clb can be used to implement up to 98% of 6-cuts and 88% of 7-cuts in mcnc benchmarks, while two of the other three plb architectures have a smaller cost in terms of logic capability per silicon area. our results are useful for designing future logic unit architectures in lut based fpgas.  jason cong yean-yow hwang
attacking the semantic gap between application programming languages and configurable hardware  it is difficult to exploit the massive, fine- grained parallelism of configurable hardware with a conventional application program?g language such as c, pascal or java. the difficulty arises from the mismatch between the synchronous, concurrent processing capability of the hardware and the expressiveness of the lan?ge-the so-called "semantic gap." we attack this problem by using a programming model matched to the hardware's capabilities that can be implemented in any (unmodified) object-oriented lan?ge, and building a corresponding compiler. the result is appli?ion code that can be developed, compiled, debugged and executed on a personal computer using conventional tools (such as visual c++ or visual cafe), and then recompiled without modifi?ion to the configurable hardware target. a straightforward c++ implementation of the serpent encryption algorithm compiled with our compiler onto a virtex xcv1000 fpga yielded an implemen?ion that was smaller (3200 vs. 4502 clbs) and faster (77 mhz vs. 38 mhz) than an independent vhdl implementation with the same degree of pipelining. a tuned version of the source yielded an implementation that ran at 95 mhz.  greg snider barry shackleford richard j. carter