waashk/acm huggingface dataset:
a knowledge based system for selecting a test methodology for a pla  testability is a very important aspect of vlsi circuits. numerous design for testability (dft) methods exist. often designers face the complex problem of selecting the best dft techniques for a particular chip under a set of design constraints and goals. in order to aid in designing testable circuits, a prototype knowledge based system has been developed which simulates a human expert on design of testable plas. the system, described in this paper, has knowledge about testable pla design methodologies and is able to negotiate with the user so as to lead the user through the design space to find a satisfactory solution. a new search strategy, called reason analysis, is introduced.  m. a. breuer xi-an zhu
the directory-based cache coherence protocol for the dash multiprocessor  dash is a scalable shared-memory multiprocessor currently being developed at stanford's computer systems laboratory. the architecture consists of powerful processing nodes, each with a portion of the shared-memory, connected to a scalable interconnection network. a key feature of dash is its distributed directory-based cache coherence protocol. unlike traditional snoopy coherence protocols, the dash protocol does not rely on broadcast; instead it uses point-to-point messages sent between the processors and memories to keep caches consistent. furthermore, the dash system does not contain any single serialization or control point. while these features provide the basis for scalability, they also force a reevaluation of many fundamental issues involved in the design of a protocol. these include the issues of correctness, performance and protocol complexity. in this paper, we present the design of the dash coherence protocol and discuss how it addresses the above issues. we also discuss our strategy for verifying the correctness of the protocol and briefly compare our protocol to the ieee scalable coherent interface protocol.  daniel lenoski james laudon kourosh gharachorloo anoop gupta john hennessy
high-level design verification of microprocessors via error modeling  a design verification methodology for microprocessor hardware based on modeling design errors and generating simulation vectors for the modeled errors via physical fault testing techniques is presented. we have systematically collected design error data from a number of microprocessor design projects. the error data is used to derive error models suitable for design verification testing. a class of basic error models is identified and shown to yield tests that provide good coverage of common error types. to improve coverage for more complex errors, a new class of conditional error models is introduced. an experiment to evaluate the effectiveness of our methodology is presented. single actual design errors are injected into a correct design, and it is determined if the methodology will generate a test that detects the actual errors. the experiment has been conducted for two microprocessor designs and the results indicate that very high coverage of actual design errors can be obtained with test sets that are complete for a small number of synthetic error models.  d. van campenhout h. al- asaad j. p. hayes t. mudge r. b. brown
low-cost branch folding for embedded applications with small tight loops  many portable and embedded applications are characterized by spending a large fraction of execution time on small program loops. to improve performance, many embeded systems use special instructions to handle program loop executions. these special instructions, however, consume opcode space, which is valuable in the embedded computing environments. in this paper, we propose a hardware technique for folding out branches when executing these small loops. this technique does not require any special branch instructions. it is based on the detection and utilization of certain short backward branch instructions (sbb). a sbb is any pc-relative branch instruction with a limited backward branch distance. once a sbb is detected, its displacement field is used by the hardware to identify the actual program loop size. it does so by loading this negative displacement field into a counter and incrementing the counter for each instruction sequentially executed. as the count approaches zero, the hardware folds out the sbb by predicting that it is always taken. the hardware overhead for this technique is minimal. using a 5-bit increment counter, the performance improvement over a set of embedded applications is about 7.5%.  lea hwang lee jeff scott bill moyer john arends
selective, accurate, and timely self-invalidation using last-touch prediction  communication in cache-coherent distributed shared memory (dsm) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. this paper proposes last-touch predictors (ltps) that learn and predict the "last touch" to a memory block by one processor before the block is accessed and subsequently invalidated by another. by predicting a last- touch and (self-)invalidating the block in advance, an ltp hides the invalidation time, significantly reducing the coherence overhead. the key behind accurate last-touch prediction is trace-based correlation, associating a last-touch with the sequence of instructions (i.e., a trace) touching the block from a coherence miss until the block is invalidated. correlating instructions enables an ltp to identify a last-touch to a memory block uniquely throughout an application's execution.  in this paper, we use results from running shared-memory applications on a simulated dsm to evaluate ltps. the results indicate that: (1) our base case ltp design, maintaining trace signatures on a per-block basis, substantially improves prediction accuracy over previous self-invalidation schemes to an average of 79%; (2) our alternative ltp design, maintaining a global trace signature table, reduces storage overhead but only achieves an average accuracy of 58%; (3) last-touch prediction based on a single instruction only achieves an average accuracy of 41% due to instruction reuse within and across computation; and (4) ltp enables selective, accurate, and timely self- invalidation in dsm, speeding up program execution on average by 11%.  an-chow lai babak falsafi
simultaneous logic decomposition with technology mapping in fpga designs  conventional technology mapping algorithms for sram-based field programmable gate arrays (fpgas) are normally carried out on a fixed logic decomposition of a circuit. the impact of logic decomposition on delay and area of the technology mapping solutions is not well understood. in this paper, we present an algorithm named sldmap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints. our study leads to two conclusions: (1) for depth minimization, the best algorithms in conventional flow (dmig + cutmap) produce satisfactory results with a short runtime, even with a fixed decomposition; (2) when all the structural decompositions of the 6-bounded boolean network are explored, sldmap consistently outperforms the state-of-the-art separate flow (dmig + cutmap) by 12% in depth and 10% in area on average; it also consistently outperforms the state-of-the-art combined approach dogma by 8% in depth and 6% in area on average.  gang chen jason cong
multes/is: an effective and reliable test generation system for partial scan and non-scan synchronous circuits  this paper describes an automatic test generation system which effectively generates test vectors by recognizing the circuit blocks for which vectors are automatically generated and the circuit blocks for which vectors have to be manually prepared.  test vectors for full scan, partial scan and nonscan synchronous circuit blocks are automatically generated. test vectors for asynchronous circuit blocks have to be manually prepared.  t. ogihara k. muroi g. yonemori s. murai
logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection  this paper presents new logic synthesis techniques for generating multilevel circuits with concurrent error detection based on a parity-check code scheme that can detect all errors caused by single stuck-at faults. these synthesis techniques fully automate the design process and allow for a better quality result than previous methods thereby reducing the cost of concurrent error detection. an algorithm is described for selecting a good parity-check code for encoding the outputs of a circuit. once the code has been chosen, a new procedure called structure- constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. the implementation that is generated is path fault secure and when augmented by a checker forms a self-checking circuit. results indicate that self-checking multilevel circuits can be generated which require significantly less area than using duplication.  nur a. touba edward j. mccluskey
the conlan project: status and future plans  conlan (consensus language) is a general formal language construction mechanism for the description of hard- and firmware at different levels of abstraction. it has been developed by the international conlan working group. members of the conlan language family are derived from a common root language called bcl (base conlan). this language provides the basic object types and operations to describe the behavior and the structure of digital systems in space and time. the paper is based on the conlan draft report (in print). the purpose of the paper is (1) to provide an informal introduction to the draft report version of bcl together with examples of its application (2) to outline some work on the derivation of languages from bcl and (3) to describe status and further plans for software tools supporting language derivation and implementation.  robert piloty dominique borrione
algorithmic transformations in the implementation of k- means clustering on reconfigurable hardware  in mapping the k-means algorithm to fpga hardware, we examined algorithm level transforms that dramatically increased the achievable parallelism. we apply the k-means algorithm to multi-spectral and hyper-spectral images, which have tens to hundreds of channels per pixel of data. k-means is an iterative algorithm that assigns assigns to each pixel a label indicating which of k clusters the pixel belongs to.  k-means is a common solution to the segmentation of multi-dimensional data. the standard software implementation of k-means uses floating-point arithmetic and euclidean distances. floating point arithmetic and the multiplication- heavy euclidean distance calculation are fine on a general purpose processor, but they have large area and speed penalties when implemented on an fpga. in order to get the best performance of k-means on an fpga, the algorithm needs to be transformed to eliminate these operations. we examined the effects of using two other distance measures, manhattan and max, that do not require multipliers. we also examined the effects of using fixed precision and truncated bit widths in the algorithm.  it is important to explore algorithmic level transforms and tradeoffs when mapping an algorithm to reconfigurable hardware. a direct translation of the standard software implementation of k-means would result in a very inefficient use of fpga hardware resources. analysis of the algorithm and data is necessary for a more efficient implementation. our resulting implementation exhibits approximately a 200 times speed up over a software implementation.  mike estlick miriam leeser james theiler john j. szymanski
diagnostic simulation of stuck-at faults in sequential circuits using compact lists this article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. the simulator represents indistinguishable classes of faults as memory efficient lists. the use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. the lists also make it easy to drop faults when they are fully distinguished from other faults. experimental results on the iscas89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices, and for large circuits is faster and more memory efficient than a recent method based on lists of indistinguishable faults. the paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large iscas circuits with known deterministic tests. the diagnostic fault simulator has also been modified to diagnose defects, given the output responses of failing devices. results on simulated bridging defects show that the diagnosis time is comparable to the time for fault simulation with fault dropping. ismed hartanto srikanth venkataraman w. kent fuchs elizabeth m. rudnick janak h. patel sreejit chakravarty
a verification technique for hardware designs  most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. this paper discusses an analytic verification technique with examples of its application.  this technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.  fumihiro maruyama takao uehara nobuaki kawato takao saito
locating functional errors in logic circuits  in the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistencies that may exist between the functional-level description and its gate-level implementation. in this paper we present a method that determines the areas, within the gate-level circuit, that contain the functional errors. the indicated areas are shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.  k. a. tamura
increasing cache port efficiency for dynamic superscalar microprocessors the memory bandwidth demands of modern microprocessors require the use of a multi- ported cache to achieve peak performance. however, multi-ported caches are costly to implement. in this paper we propose techniques for improving the bandwidth of a single cache port by using additional buffering in the processor, and by taking maximum advantage of a wider cache port. we evaluate these techniques using realistic applications that include the operating system. our techniques using a single-ported cache achieve 91% of the performance of a dual-ported cache. kenneth m. wilson kunle olukotun mendel rosenblum
comparing structurally different views of a vlsi design  in large design projects, it is desirable to compare alternate views that use different hierarchies. however, existing techniques either require essentially identical hierarchies (which is sometimes an unacceptable restriction) or must flatten to remove the differences (which may be very costly). a new technique, informed comparison, has neither shortcoming. first, hierarchy transformations are applied to reconcile the structures of the views; then a hierarchical base comparison finishes the task. the reconciliation is guided by a small amount of additional design information: the intended relationship between the hierarchies of the views. some qualities of informed comparison depend on the reconciliation repertoire and the base comparison. two examples are studied.  mike spreitzer
automatic incorporation of on-chip testability circuits  this paper presents a system which automatically incorporates testability circuits into ecl chips. this system incorporates three types of circuit: (1) random access scan circuit, (2) clock suppression circuit for delay fault testing, and (3) pin scan-out circuit for chip i/o pin observation in board testing. fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. this system was used to develop the new fujitsu vp-2000 supercomputer.  noriyuki ito
a low-power clock and data recovery circuit for 2.5 gb/s sdh receivers  a low power monolithic clock and data recovery ic for 2.5 gb/s sdh stm-16 systems has been designed and fabricated using maxim gst-2 27 ghz-ft silicon bipolar technology. the circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 v supply voltage is required, and power consumption results below 350 mw. this ic and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 w. preliminary measurements under a 223-1 prbs data stream have shown an input sensitivity below 20 mvpp and a rms jitter of 10 ps.  andrea pallotta francesco centurelli alessandro trifiletti
dynamic processor allocation in hypercube computers  fully recognizing various subcubes in a hypercube computer efficiently is nontrivial due to the specific structure of the hypercube. we propose a method with much less complexity than the multiple-gc strategy in generating the search space, while achieving complete subcube recognition. this method is referred to as a dynamic processor allocation scheme because the search space generated is dependent upon the dimension of the requested subcube dynamically, rather than being predetermined and fixed. the basic idea of this strategy lies in collapsing the binary tree representations of a hypercube successively so that the nodes which form a subcube but are distant would be brought close to each other for recognition. the strategy can be implemented efficiently by using shuffle operations on the leaf node addresses of binary tree representations. extensive simulation runs are carried out to collect experimental performance measures of interest of different allocation strategies. it is shown from analytic and experimental results that this strategy compares favorably in many situations to any other known allocation scheme capable of achieving complete subcube recognition.  po-jen chuang nian-feng tzeng
supporting system-level power exploration for dsp applications  _system-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional blocks. we focus on power estimation for data-dominated systems specified as synchronous data-flows and implemented on a single- processor architecture. our estimator is integrated within the ptolemy design environment, and provides information to system designers on the power dissipated by every task in a given specification. power estimation is based on instruction-level power models. we demonstrate the applicability of our tool on a few design examples and target architectures._  luca benini marco ferrero alberto macii enrico macii massimo poncino
logic synthesis for programmable gate arrays  the problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architectures: table-look-up and multiplexor-based. the constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources.  rajeev murgai yoshihito nishizaki narendra shenoy robert k. brayton alberto sangiovanni-vincentelli
a distributed i/o architecture for harts  the issue of i/o device access in harts --- a distributed real-time computer system under construction at the real-time computing laboratory (rtcl), the university of michigan --- is explicitly addressed. several candidate solutions are introduced, explored, and evaluated according to cost and complexity, reliability, and performance: (1) "node-direct" distribution with the intra-node bus and a local i/o bus, (2) use of dedicated i/o nodes which are placed in the hexagonal mesh as regular applications nodes but which provide i/o services rather than computing services, and (3) use of a separate i/o network which has led to the proposal of an "interlaced" i/o network. the interlaced i/o network is intended to provide both high performance without burdening node processors with i/o overhead as well as a high degree of reliability. both static and dynamic multi-ownership protocols are developed for managing i/o device access in this i/o network. the relative merits of the two protocols are explored and the performance and accessibility which each provide are simulated.  kang g. shin greg dykema
recency-based tlb preloading  caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. however, tlb misses have become a serious bottleneck as working sets are growing beyond the capacity of tlbs.  this work presents one of the first attempts to hide tlb miss latency by using preloading techniques. we present results for traditional next-page tlb miss preloading - an approach shown to cut some of the misses. however, a key contribution of this work is a novel tlb miss prediction algorithm based on the concept of "recency", and we show that it can predict over 55% of the tlb misses for the five commercial applications considered.  ashley saulsbury fredrik dahlgren per stenström
optimization of critical paths in circuits with level-sensitive latches  a simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. the extended formulation provides a sufficient set of constraints to ensure that, when all slacks are non-negative, the corresponding circuit will be free of late signal timing problems. cycle stealing is directly permitted by the formulation. however, moderate restrictions may be necessary to ensure that the timing constraint graph is acyclic. forcing the constraint graph to be acyclic allows a broad range of existing optimization algorithms to be easily extended to better optimize circuits with level-sensitive latches. we describe the extension of two such algorithms, both of which attempt to solve the problem of selecting parts from a library to minimize area subject to a cycle time constraint.  timothy m. burks karem a. sakallah
horizontal partitioning of pla-based finite state machines  we present a new form of partitioning of pla-based fsms that combines the advantages of traditional vertical pla partitioning (i.e. via inputs and/or outputs) and counter embedding which consists of replacing the fsm state memories by a counter. like the former, horizontal partitioning allows the reduction of the number of input and/or output columns in the plas resulting from the partition. furthermore, the technique also reduces the total number of product terms, as in counter embedding techniques. this reduction is due to a decomposition of state transitions into two classes that are realized by two sets of logic. in this case however, a second pla-based fsm is used in place of the counter. this results in area reductions of 30% to 60% (with respect to regular two-level logic minimization) for the benchmark examples presented.  p. g. paulin