waashk/acm huggingface dataset:
a hierarchical bit-map format for the representation of ic mask data  an alternative representation to the usual outline description of geometric entities for ic mask artwork is described. rather than identifying opaque areas of a mask by individual shape outlines as described by their corners' coordinates, both the opaque and transparent areas of the design are represented by 1' s and 0's respectively in a grid pattern or "bit map" of the entire mask plane.  a bit-map representation is well suited to many computer design aids which deal with ic layout data. artwork output programs which require a "merge" operation on all shapes of each mask benefit from this data format since it already contains the merged version of each mask's geometric entities. the bit-map format especially promises to increase the operational efficiency of boolean comparisons of various mask levels as performed by artwork analysis programs for locating design rule errors and for identifying circuit elements directly from the masks.  a hierarchical scheme for describing the bit patterns of a mask efficiently is presented which limits the memory requirements of this data format to a size proportional to the usual outline description. consequently the bit-map representation can be used not only in those computer aids where it supports program functions very well, but also as the central data format for a cad system.  james a. wilmore
accelerated transition fault simulation  this paper presents a new and an effective approach to fault simulation of transition faults in combinational or scan - based logic. an experiment with a set of benchmark circuits demonstrates the efficiency of the approach, achieved by combining a very fast single stuck - at fault simulation algorithm with a quasi - static definition of a transition fault. tests that cover transition faults are becoming increasingly important as they also provide a cover for most typical transistor stuck - open faults in cmos.  m. h. schultz f. brglez
performance-driven mapping for cpld architectures  in this paper we present a performance-driven mapping algorithm, plamap, for cpld architectures which consist of a large number of pla-style logic cells. the primary goal of our mapping algorithm is to minimize the depth of the mapped circuit. meanwhile, we have successfully reduced the area of the mapped circuits by applying several heuristic techniques, including threshold control of pla fanouts and product terms, slack-time relaxation, and pla-packing. we compare our plamap with a recently-published algorithm templa [1] and a commercial tool, altera's max+plus ii [16]. experimental results on various mcnc benchmarks show that overall templa uses 8 to 11% less area at the cost of 96 to 106% more mapping depth, and max+plus ii uses 12% less area but 58% more delay compared with our mapper.  deming chen jason cong milos d. ercegovac zhijun huang
towards design and validation of mixed-technology socs  _this paper illustrates an approach to design and validation of heterogeneous systems. the emphasis is placed on devices which incorporate mems parts in either a single mixed-technology (cmos_ \\+ _micromachining) soc device, or alternatively as a hybrid system with the mems part in a separate chip. the design flow is general, and it is illustrated for the case of applications embedding cmos sensors. in particular, applications based on finger-print recognition are considered since a rich variety of sensors and data processing algorithms can be considered. a high level multi- language/multi-engine approach is used for system specification and co- simulation. this also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. from the selected system specification, the actual architecture is finally generated via a multi- language co-design approach which can result in both hardware and software parts. the hardware parts are composed of available ip cores. for the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the soc devices discussed_.  s. mir b. charlot g. nicolescu p. coste f. parrain n. zergainoh b. courtois a. jerraya m. rencz
gate array layout automation: a tutorial  gate array layout is becoming an increasingly important topic in design automation, as utilization of these components expands. in this tutorial a model of gate array physical design is first presented, introducing nomenclature used thereafter. the architecture of a typical gate array layout system is briefly discussed, establishing the environmental setting for more detailed examination of placement and routing techniques.  the placement problem is next defined, along with evaluation metrics and practical considerations related to placement. constructive initial placement techniques based on cluster growth and mincut algorithms are next presented in some detail. iterative improvement algorithms based on pairwise exchange, force-relaxation and unconnected set relocation are then presented. coverage of gate array placement concludes with a comparison of results achieved with these methods, a brief exploration of the proper role of graphics placement, and enumeration of some promising topics for research in placement.  robert j. smith
adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays  we present a new min-cut based placement algorithm for large scale sea-of- gates arrays. in the past all such algorithms used a fixed cut line sequence that is determined before min-cut partitioning is performed. in our approach, we adaptively select a next partitioning pattern based on the current parameter value; we then perform the corresponding min-cut partitionings and measure a new parameter value. we repeat this process until all cut lines are processed. as a parameter, we introduce a new global objective function based on wire congestions on cut lines. we establish a close relation between this function and cut line sequences. this relation is used to develop an innovative method of adaptively determining a cut line sequence so as to minimize this global function. with this adaptive selection of cut lines along with a new cluster-based min-cut partitioning technique, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. this has led to its successful production use, having generated more than 400 cmos sea-of- gates array chips.  kazuhiro takahashi kazuo nakajima masayuki terai koji sato
selective cache ways: on-demand cache resource allocation  increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application requirements. selective cache ways provides the ability to disable a subset of the ways in a set associative cache during periods of modest cache activity, while the full cache may remain operational for more cache-intensive periods. because this approach leverages the subarray partitioning that is already present for performance reasons, only minor changes to a conventional cache are required, and therefore, full- speed cache operation can be maintained. furthermore, the tradeoff between performance and energy is flexible, and can be dynamically tailored to meet changing application and machine environmental conditions. we show that trading off a small performance degradation for energy savings can produce a significant reduction in cache energy dissipation using this approach.  david h. albonesi
regression-based rtl power modeling  register-transfer level (rtl) power estimation is a key feature for synthesis- based design flows. the main challenge in establishing a sound rtl power estimation methodology is the construction of accurate, yet efficient, models of the power dissipation of functional macros. such models should be automatically built, and should produce reliable average power estimates. in this paper we propose a general methodology for building and tuning rtl power models. we address both hard macros (presynthesized functional blocks)and soft macros (functional units for which only a synthesizable hdl description is provided). we exploit linear regression and its nonparametric extensions to express the dependency of power dissipation on input and output activity. bottom-up off-line characterization of regression-based power macromodels is discussed in detail. moreover, we introduce a low overhead on-line characterization method for enhancing the accuracy of off-line characterization.  alessandro bogliolo luca benini giovanni de micheli
weak ordering - a new definition  a memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. this model guarantees that all memory accesses will appear to execute atomically and in program order. an alternative model, weak ordering, offers greater performance potential. weak ordering was first defined by dubois, scheurich and briggs in terms of a set of rules for hardware that have to be made visible to software.  the central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than having to think about weaker memory, or even write buffers. following this hypothesis, we re-define weak ordering as a contract between software and hardware. by this contract, software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent to at least the software that obeys those constraints. we illustrate the power of the new definition with a set of software constraints that forbid data races and an implementation for cache- coherent systems that is not allowed by the old definition.  sarita v. adve mark d. hill
performance-constrained hierarchical pipelining for behaviors, loops, and operations  behavioral specifications of dsp systems generally contain a number of nested loops. in order to obtain high date rates for such systems, it is necessary to pipeline the system within the behavior, within the loop bodies, and also within the operations. in order to hierarchically pipeline a performance- constrained system, an important step consists of distributing the performance constraint among the loops in such a manner that the constraint is satisfied and design cost is minimized. this paper presents an algorithm for propagating constraints and hierarchically pipelining a given throughput- constrained system. along with pipelining, the algorithm schedules the operations within the loop bodies and selects components for them, with the aim of minimizing cost while satisfying the constraint propagated to the loop body. results demonstrate the necessity of pipelining across the three granularity levels in order to obtain high performance designs. they also demonstrate the feasibility and quality of our approach, the indicate that it may be efficiently used for synthesizing or estimating within system-level design.  smita bakshi daniel d. gajski
a wave-pipelined router architecture using ternary associative memory  in this paper a wave-pipelining scheme is used to increase the performance of a router architecture. wave-pipelining has a potential of significantly reducing clock cycle time and power. the design approach considered in this paper allows the propagation of data from stage to stage to occur without the use of intermediate latches. control signals are used to ensure that intermixing of _data waves_ does not occur. the results of the study show that wave-pipelining helps to reduce the clock period.  jose g. delgado-frias jabulani nyathi laxmi bhuyan
detailed routing architectures for embedded programmable logic ip cores  as the complexity of integrated circuits increases, the ability to make post- fabrication changes to fixed asic chips will become more and more attractive. this ability can be realized using programmable logic cores. these cores are blocks of programmable logic that can be embedded into a fixed- function asic or a custom chip. such cores differ from stand-alone fpgas in that they can take on a variety of shapes and sizes. with this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. we quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. we also present a new switch block family optimized for rectangular cores. compared to a simple extension of an existing switch block, our new architecture leads to an 8.7% improvement in density with little effect on speed. finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 1.1%.  peter hallschmid steven j. e. wilton
performance-driven synthesis of asynchronous controllers  we examine the implications of a new hazard-free combinational logic synthesis method, which generates multiplexor trees from binary decision diagrams (bdds)---representations of logic functions factored recursively with respect to input variables---on extended burst-mode asynchronous synthesis. first, the use of the bdd-based synthesis reduces the constraints on state minimization and assignment, which reduces the number of additional state variables required in many cases. second, in cases where conditional signals are sampled, it eliminates the need for state variable changes preceding output changes, which reduces overall input to output latency. third, selection variables can easily be ordered to minimize the latency on a user-specified path, which is important for optimizing the performance of systems that use asynchronous components. we present extensive evaluations showing that, with only minimal optimization, the bbd-based synthesis gives comparable results in area with our previous exact two-level synthesis method. we also give a detailed example of the specified path optimization.  kenneth y. yun bill lin david l. dill srinivas devadas
vlsi timing simulation with selective dynamic regionization  accurate timing simulations are crucial to the design of mos vlsi circuits, but can take prohibitively large amounts of time. this paper describes dynamic regionization techniques applied to an event based simulator for mos timing simulation that have proven to be more efficient and as accurate as the static reorganization method. the mos network is first statically partitioned into groups of strongly coupled nodes called regions. big regions are then incrementally and dynamically partitioned into and replaced by subregions. subregions are treated just like normal regions in the event based simulation process. this simulator has been used to verify the timing and functionality of several large vlsi chips. performance is 3 to 7 times faster than a static regionalization method.  meng-lin yu bryan d. ackland
bimos, an mos oriented multi-level logic simulator  in this paper, a new mos oriented multilevel logic simulator is presented in which primitives can be conventional unidirectional gates as well as high level functional blocks and bidirectional mos transistors.  first the simulator and its capabilities are introduced, then the simulation algorithm, the delay model and a new initialization scheme are presented. finally, the use of the simulator in a hierarchical design methodology is illustrated.  p. stevens g. arnout
balanced sequences and optimal routing  the objective pursued in this paper is two-fold. the first part addresses the following combinatorial problem: is it possible to construct an infinite sequence over n letters where each letter is distributed as "evenly" as possible and appears with a given rate? the second objective of the paper is to use this construction in the framework of optimal routing in queuing networks. we show under rather general assumptions that the optimal deterministic routing in stochastic event graphs is such a sequence.  eitan altman bruno gaujal arie hordijk
a hardware description language for processor based digital systems  a new hdl (hardware description language) for describing processor modules and support chips is presented in [1,2]. this paper presents a portion of the dissertation and illustrates the effectiveness of the new descriptive technique in describing complex digital systems with example descriptions of the pdp-11 computer system and the 2900 bit-slice components. the examples presented illustrate that the descriptive technique allows functional abstraction not only at the chip interface level (as in the m6800 system description presented in [1,2]) but also at the subsystem (or pcb module) level (as shown in the pdp-11 example). language modifications and enhancements to increase the power of the language are also presented.  j. h. tracey k. s. kumar
a symbolic functional description language  this paper describes a new diagrammatic hardware description language sfdl (symbolic functional description language) and a hierarchical logic design supporting system ldss (logic design supporting system).  sfdl has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable for computer processing. besides, the ldss allows designers to draw diagrams without the attention to complicated drawing rule and translate the sfdl diagrams into a text-styled hardware description language.  through experiments, the effectiveness of the sfdl for hierarchical logic design has been confirmed.  gotaro odawara jun sato masahiro tomita
gate matrix layout synthesis with two-dimensional folding  we have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. the conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. the incomplete representations may mislead the search process for an optimal solution during the layout partitioning and the gate ordering phases. we propose a new graph- based model called hierarchical dynamic net-list to improve the schematic representation. based on the new model, the folded layout area in the partitioning phase can be more accurately estimated. the new gate ordering algorithm proposed by us also takes the advantages of the hierarchical dynamic net-list model to handle the gate placement in the folded layouts. the experimental results show 12% to 15% improvement in layout area for small circuits and 30% improvement for a large circuit.  i. lin d. h. c. du s. h. c. yen
test pattern generation for sequential mos circuits by symbolic fault simulation  the cosmos symbolic fault simulator generates test sets for combinational and sequential mos circuits represented at the switch level. all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (x) logic values are captured. to generate tests for a circuit, the program derives boolean functions representing the behavior of the good and faulty circuits over a sequence of symbolic input patterns. it then determines a set of assignments to the input variables that will detect all faults. symbolic simulation provides a natural framework for the user to supply an overall test strategy, letting the program determine the detailed conditions to detect a set of faults. symbolic preprocessing of switch-level networks, combined with efficient boolean manipulation makes this approach feasible.  k. cho r. e. bryant
precomputation-based sequential logic optimization for low power  we address the problem of optimizing logic-level sequential circuits for low power. we present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. we present two different precomputation architectures which exploit this observation.  we present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation. we present experimental results on various sequential circuits. up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.  mazhar alidina jose monteiro srinivas devadas abhijit ghosh marios papaefthymiou
philo-a vlsi design system  this paper describes a design system capable of designing chips in the range of 5k to 7k equivalent three-way nor gates. a key feature of the system is the ability to design chips with large macros (rams and plas). this design system is part of ibm's corporate-wide engineering design system (eds). eds provides the capabilities of logic simulation, automatic placement and wiring, checking, and test pattern generation (i). this paper describes the key capabilities of the system, specifically as applied to ibm's silicon gate process. topics covered include a description of the chip image and circuits, the automatic generation of large macros, the automatic placement and interconnection of circuits and macros, and a delay calculator/optimizer.  r. donze j. sanders m. jenkins g. sporzynski
hardware identification of cache conflict misses  this paper describes the miss classification table, a simple mechanism that enables the processor or memory controller to identify each cache miss as either a conflict miss or a capacity (non-conflict) miss. the miss classification table works by storing part of the tag of the most recently evicted line of a cache set. if the next miss to that cache set has a matching tag, it is identified as a conflict miss. this technique correctly identifies 87% of misses in the worst case.  several applications of this information are demonstrated, including improvements to victim caching, next-line prefetching, cache exclusion, and a pseudo- associative cache. this paper also presents the adaptive miss buffer (amb), which combines several of these techniques, targeting each miss with the most appropriate optimization, all within a single small miss buffer. the amb's combination of techniques achieves 16% better performance than any single technique alone.  jamison d. collins dean m. tullsen
global wires: harmful?  in this paper a shift is proposed in the design of vlsi circuits. in conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off. these violations are used to hand an updated specification to synthesis. such iteration is not desirable, and for really high performance not feasible. to come to a design flow, higher level synthesis should distribute delay over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.  ralph h. j. m. otten