waashk/acm huggingface dataset:
on measuring the effectiveness of various design validation approaches for powerpc microprocessor embedded arrays  design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. at somerset, validation of array designs relies on both formal verification and vector simulation. although several methods for array design validation have been proposed and had great success [ganguly et al. 1996; pandey et al. 1996, 1997; wang and abadir 1997], little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. in this paper, we measure the effectiveness of different validation approaches based on automatic design error injection and simulation. the technique provides a systematic way to evaluate various validation approaches at both logic and transistor levels. experimental results on recent powerpc microprocessor arrays will be discussed and reported.  li-c. wang magdy s. abadir jing zeng
soprano: an efficient automatic test pattern generator for stuck-open faults in cmos combinational circuits  in this paper, we describe a highly efficient automatic test pattern generator for stuck-open (sop) faults, called soprano, in cmos combinational circuits. the key idea of soprano is to convert a cmos circuit into an equivalent gate level circuit and sop faults into the equivalent stuck-at faults. then soprano derives test patterns for sop faults using a gate level test pattern generator. several techniques to reduce the test set size are introduced in soprano. experimental results performed on eight benchmark circuits show that soprano achieves high sop fault coverage and short processing time.  hyung ki lee dong sam ha
automatic layout for gate arrays with one layer of metal  gate arrays with only one layer of metal have some advantages-notably that they are easier to make than arrays with two or three layers of metal and are correspondingly cheaper. these are countered by the increased difficulty of layout, particularly if this is to be achieved automatically by a design automation system. this paper presents an automatic layout system providing placement and routing for the c-series of uncommitted logic arrays from ferranti; although the techniques and programs are applicable generally to gate arrays with one layer of metal.  peter robinson
data cache management using frequency-based replacement  we propose a new frequency-based replacement algorithm for managing caches used for disk blocks by a file system, database management system, or disk control unit, which we refer to here as data caches. previously, lru replacement has usually been used for such caches. we describe a replacement algorithm based on the concept of maintaining reference counts in which locality has been "factored out". in this algorithm replacement choices are made using a combination of reference frequency and block age. simulation results based on traces of file system and i/o activity from actual systems show that this algorithm can offer up to 34% performance improvement over lru replacement, where the improvement is expressed as the fraction of the performance gain achieved between lru replacement and the theoretically optimal policy in which the reference string must be known in advance. furthermore, the implementation complexity and efficiency of this algorithm is comparable to one using lru replacement.  john t. robinson murthy v. devarakonda
a new approach to fast control of r2 r2 3-stage benes networks of r r crossbar switches  the routing control of benes networks has proven to be costly. this paper introduces a new approach to fast control of n × n 3-stage benes networks of r × r crossbar switches as building blocks, where n = r2 and r ≥ 2\. the new approach consists of setting the leftmost column of switches to an appropriately chosen configuration so that the network becomes self-routed while still able to realize a given family of permutations. this approach requires that, for any given family of permutations, a configuration for the leftmost column be found. such a family is called compatible and the configuration of the leftmost column is called the compatibility factor. in this paper, compatibility is characterized and a technique to determine compatibility and the compatibility factor is developed. the technique is used to show the compatibility and find the compatibility factor of -realizable permutations, the permutations needed to emulate a hypercube, and the families of permutations required by fft, bitonic sorting, tree computations, multidimensional mesh and torus computations, and multigrid computations. an o(log2 n) time routing algorithm for the 3-stage benes will also be developed. finally, as only 3 compatibility factors are required by the above families of permutations, it will be proposed to replace the first column by 3 multiplexed connections yielding a self-routing network with strong communication capabilities.  abdou youssef bruce arden
low-power considerations in the design of bluetooth (invited talk)  in this paper, we review the bluetooth technology, a new universal radio interface enabling electronic devices to connect and communicate wirelessly via short-range connections. motivations for the radio requirements are given, and the implications of system parameters like operating modes, frequency hopping, interference resistance are discussed from a low-power perspective. speci!c characteristics enabling low-cost single-chip implementations and supporting low power consumption are outlined.  sven mattisson
upper and lower bounds on switching energy in vlsi  a technology- independent framework is established for measuring theswitching energy consumed by verylarge scale integrated (vlsi) circuits. techniques are developed foranalyzing functional energy consumption, and for designingenergy- efficient vlsi circuits. a wire (or gate) in a circuit usesswitching energy when it changes state from 1 to 0 or vice versa. thispaper develops the uniswitch model(usm) of energy consumption, which measures thedifferences between pairs of states of an embeddedcircuit.…  \\---from the author's abstract gloria kissin
timing analysis for nmos vlsi  tv and ia are timing analysis programs for nmos vlsi designs. based on the circuit obtained from existing circuit extractors, tv determines the minimum clock duty and cycle times. it calculates the direction of signal flow through all transistors before the timing analysis is performed. the timing analysis is breadth-first (block- oriented) and pattern independent, using the values stable, rise, fall, as well as information about clock qualification. tv has fast running time, small user input requirements, and the ability to offer the user valuable advice. ia (tv's interactive advisor) allows the user to quickly experiment with ways to increase circuit performance. several delay models can be used; when compared to circuit simulation and fabricated chips, accuracies within 20% for most critical paths have been achieved.  norman p. jouppi
overcoming wireload model uncertainty during physical design  the advent of deep sub-micron technologies has created a number of problems for existing design methodologies. most prominent among them is the problem of timing closure, whereby design time is dramatically increased due to iterations between gate-level synthesis and physical design. it is well known that the heart of this problem lies in the use of wireload models based on wirelength statistics from legacy designs. some technology projections in have suggested that wireload models will remain effective to block sizes on the order of 50k gates. this suggests that synthesis will not have to be changed much since this is approximately the maximum size for which logic synthesis is effective. however, our analyses on production designs show that the problem is not quite so straightforward, and the efficacy of synthesis using wireload models depends upon technology data as well as specific characteristics of the design. we analyze these effects and dependencies in detail in this paper, and draw some conclusions about the amount of physical information that is required for synthesis to be effective. finally, we discuss the implications on hierarchical design flows, and propose a solution via physical prototyping.  padmini gopalakrishnan altan odabasioglu lawrence pileggi salil raje
on high-speed computing with a programmable linear array  it has been observed by many researchers that systolic arrays are very suitable for certain high-speed computations. in this paper, using a formal methodology, a single simple programmable linear systolic array capable of solving large number of problems drawn from a variety of applications is designed. the methodology is applicable to problems solvable by sequential algorithms that can be specified as nested for loops of arbitrary depth. the algorithms of this form that can be computed on the array presented in this paper include 25 algorithms dealing with signal and image processing, algebraic computations, matrix arithmetic, pattern matching, database operations, sorting, and transitive closure. assuming bounded i/o, for 18 of those algorithms the time and storage complexities are optimal, and therefore no improvement can be expected by utilizing dedicated special purpose linear systolic arrays designed for individual algorithms.  p. z. lee z. m. kedem
ecbl: an extended corner block list with solution space including optimumplacementa non-slicing floorplanning algorithm based on cbl[1], corner block list, waspresented recently. it can represent non-slicing floorplans without emptyrooms. in this paper, we propose an extended corner block list structure,ecbll, to represent general non-slicing floorplans, which may include emptyrooms. by setting lã-1..3], where l is the extending ratio, our algorithm cantranslate a topological floorplan to its corresponding placement in o(n) time,where n is the number of blocks. also, based on the optimum solution theoremof bounded-sliceline grid in [2], we proved that the solution space of ecblncontains the optimum block placement, which has the minimum area. experimentalresults on mcnc benchmarks show promising performance with 7% improvement inwire length and 2% decrease in dead space over algorithms based on cbl.meanwhile, compared with other algorithms, our algorithm can get betterresults with less runtime.shuo zhou sheqin dong chung-kuan cheng jun gu
optimization of negative gate networks realized in weinberger-likf layout in a boolean level silicon compiler  the random logic portion of a chip implementing a set of boolean functions and sequential circuits usually represents a major contribution to chip area. obviously, there are many circuits which realize the same boolean function. unfortunately, at present there is no general theory that provides designers (and design automation programs) with lower bounds for total area, for gate oxide area, and for delay time of logic implementations in integrated systems. therefore, the main task for the computer optimization program appears in choice of the circuit with the most convenient layout.  diades is a design automation system with register-transfer level description on its input and cif file on output [5]. the digital circuit can be described in both behavioral and structural mode. a set of successive compilations and hardware implementing and optimizing transformations create the description of the network on the level of logic gates and pass transistors. as the output of hardware compilation from the higher level, this description is usually nonoptimal and thus is next optimized by recursive technology independent transformations based on boolean algebra (like a*o o, a*a a, etc.). inverters are also inserted into long chains of and or or gates, being the results of iterative circuits' compilation [4].  the next stages are: technology dependant optimization of the logic network, and network's layout. it is assumed that the resultant network is multilevel, consists of complex negative gates, and is realized in semiregular weinberger- style gate matrix layout. the logic minimization method intended for layout minimization is described in this paper.  it is assumed in our silicon compiler, that logic is constructed of n-channel, polysilicon gate mosfet ratioless complex gates, performing any negative function. by negative function we understand negation of positive function, while positive function is any combination of and and or functors [1]. functions for evaluation of circuit's performance parameters such as total area, area of gate oxide, and gate delay time are used. these functions are defined in terms of basic technology and selected topology parameters. the method can be adapted to other technologies.  andrzej wieclawski marek perkowski
the ic module compiler, a vlsi system design aid  the ic module compiler is a new design aid that applies structured hierarchical design methodology, similar to aspects of the methodology pioneered by the caltech silicon structures project [gra79], to the task of defining vlsi chip logic. it converts designs described as interconnections of msi level modules into detailed logic or functional descriptions for simulators and other chip design aids. detailed models of the modules, including adders, counters, multiplexers and memory elements, are stored in a library. along with a simple syntax for circuit connectivity data, the module compiler language features c language style constructs to support module parameterization and maximize flexibility. this paper describes the features and structure of the module compiler and illustrates its application through examples.  n. j. elias a. w. wetzel
a fault simulation methodology for vlsi  some deficiencies of existing simulators in the context of vlsi design and testing are considered. a fault simulation approach based on csa (connector- switch-attenuator) theory is defined which overcomes many of these deficiencies. the csa circuit elements and logic values needed to model combinational circuits are described and applied to the analysis of various types of mos circuits. a charge-storage element called a well is introduced to simulate sequential behavior. it is shown that many fault types, including stuck-line faults, short circuits, open circuits, and delay faults can be modeled in a uniform and efficient manner.  john p. hayes
a method for ic layout verification  a method for mos integrated circuit layout verification based on net list extraction and logic simulation is presented. the net list elements are on the gate level or higher, defined by the user. a self developed net list extractor, netex, is described. netex is interfaced to a commercially available layout system and logic simulator. results show that this is a fast and reliable way of connectivity checking. limitations and further improvements are discussed.  ola a. marvik
a simplified six-waveform type method for delay fault testing  a new, simplified waveform method is presented for delay fault testing. the method enables accurate calculation of a delay fault detection threshold for definitely detectable faults, and a delay fault range for possibly detectable faults. the method is shown to correctly classify definitely detectable faults which are mis-classified by methods recently reported elsewhere [1,2]. a quantitative delay fault model with variable fault size is used, and the effect of the delay fault is explicitly described by the new waveform method. the calculation of the detectable delay size threshold occurs in linear time for any definitely detectable fault.  w.-w. mao m.d. ciletti
non-scan design-for-testability of rt-level data paths  this paper presents a non-scan design-for-testability technique applicable to register-transfer (rt) level data path circuits, which are usually very hard- to-test due to the presence of complex loop structures. we develop a new testability measure, and utilize the rt-level structure of the data path, for cost-effective re-design of the circuit to make it easily testable, without having to either scan any flip-flop or breakloops directly. the non-scan dft technique was applied to several data path circuits. experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at- speed. the hardware overhead and the test application time required for the non-scan designs is significantly lower than the corresponding partial scan designs.  sujit dey miodrag potkonjak
peephole optimization as a targeting and coupling tool  the term peephole optimization is used to mean the pattern matching and conditional replacement performed on small sections of the intermediate form.  the circular dependence between the code generation phases implies that local optimals are rarely global optimals. there are several reactions: (1) accept the local optimal, (2) develop intermediate goals whose achievement suggest global optimality, (3) retain the choices so that the decisions can be made later, (4) optimize the object code by replacing awkward or overly constrained segments of code with improved ones. optimizing the object code has several advantages. first, code generation is greatly simplified. the code generator is allowed to forgo case analysis and utilize only a subset of the machine's instructions and addressing modes [bd88,df84a,df84b,df87]. second, a phase ordering problem often encountered in optimizations is reduced.  v. h. allan
analysis, reduction and avoidance of crosstalk on vlsi chips  as chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on- chip timing and even functionality. a method is presented to analyze crosstalk while taking into account timing relationship and timing criticality between coupling wires. the method is based upon the geometrical layout of the wires (adjacency), the signal slopes on the wires (circuit driving capability) and timing considerations.  based on these wire characteristics, a pattern driven routing tool imbeds the crosstalk critical nets in non-adjacent wiring tracks for crosstalk avoidance. the pattern driven routing capability may also be used for rerouting crosstalk critical nets of an already existing routing for crosstalk reduction.  the crosstalk analysis and the routing tool described in this paper were used in three generations of vlsi processor chip designs for ibm's s/390 computers, always resulting in crosstalk-resistant hardware.  tilmann stöhr markus alt asmus hetzel jurgen koehl
pronto: quick pla product reduction  a pla is a regular, modular combinational function implementation popular in vlsi design. among methods which reduce the cost of implementing a given pla specification, reducing the number of product terms is particularly fruitful.  optimum product term reduction for practical-sized problems is prohibitively complex. previous suboptimal, heuristic product term reducers have been iterative or indirect. pronto is a direct, one-pass method for heuristically reducing the number of product terms required to specify a pla. results of using pronto on a small set of examples show solutions up to 21% better than previously reported, using a procedure of modest complexity.  jorge f. martinez- carballido v. michael powers
power optimization of system-level address buses based on software profiling  the paper aims at defining a methodology for the optimization of the switching power related to the processor-to memory communication on system- level buses. first, a methodology to profile the switching activity related to system-level buses has been defined, based on the tracing of benchmark programs running on the sun sparc v8 architecture. the bus traces have been analyzed to identify temporal correlations between consecutive patterns. second, a framework has been set up for the design of high-performance encoder/decoder architectures to reduce the transition activity of the system- level buses. novel bus encoding schemes have been proposed, whose performance has been compared with the most widely adopted power-oriented encodings. the experimental results have shown that the proposed encoding techniques provide an average reduction in transition activity up to 74.11% over binary encoding for instruction address streams. the results indicate the suitability of the proposed techniques for high-capacitance wide buses, for which the power saving due to the transition activity reduction is not offset by the extra power dissipation introduced in the system by the encoding/decoding logic.  w. fornaciari m. polentarutti d. sciuto c. silvano
low power synthesis of sum-of-products computation (poster session)  novel techniques for the power efficient synthesis of sum-of-product computations are presented. simple and efficient heuristics for scheduling and assignment are described. different partly static cost functions are proposed to drive the synthesis tasks. the proposed cost functions target the power consumption either in the buses connecting the functional units with the storage elements or inside the functional units. the partly static nature of the proposed cost functions reduces the time of the synthesis procedure. experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.  k. masselos s. theoharis p. k. merakos t. stouraitis c. e. goutis
monsoon: an explicit token-store architecture  dataflow architectures tolerate long unpredictable communication delays and support generation and coordination of parallel activities directly in hardware, rather than assuming that program mapping will cause these issues to disappear. however, the proposed mechanisms are complex and introduce new mapping complications. this paper presents a greatly simplified approach to dataflow execution, called the explicit token store (ets) architecture, and its current realization in monsoon. the essence of dynamic dataflow execution is captured by a simple transition on state bits associated with storage local to a processor. low-level storage management is performed by the compiler in assigning nodes to slots in an activation frame, rather than dynamically in hardware. the processor is simple, highly pipelined, and quite general. it may be viewed as a generalization of a fairly primitive von neumann architecture. although the addressing capability is restrictive, there is exactly one instruction executed for each action on the dataflow graph. thus, the machine oriented ets model provides new understanding of the merits and the real cost of direct execution of dataflow graphs.  gregory m. papadopoulos david e. culler
a module generator for optimized cmos buffers  a module generator for cmos buffers have been written in c. the generator optimizes buffer design with respect to a user specified objective function both in terms of performance and layout. speed, area, power consumption, power-delay, at and at2 are selectively optimized before the layout is produced. such layout is generated in various configurations depending on load size. technology file is easily updatable.  a. j. al-khalili y. zhu d. al-khalili
real: a program for register allocation  this paper describes the real register allocation program. real uses a track assignment algorithm taken from channel routing called the left edge algorithm. real is optimal for non-pipelined designs with no conditional branches. it is thought that real is also optimal for designs with conditional branches, pipelined or not. experimental results are included in the report, which illustrate the optimal solutions found by real. real is part of the adam advanced design automation system, and will be used to process designs output from maha and sehwa.  f. j. kurdahi a. c. parker