waashk/acm huggingface dataset:
vhsic hardware description (vhdl) development program  the vhsic program has realized the importance of a standard hardware description language to facilitate the design and documentation of future military digital systems incorporating vhsic technology. to that end, the vhsic hardware description language development program has been organized to generate a language and an associated hierarchical simulator. the paper briefly covers some back-ground information and then outlines the general structure of the program. the latter is explained with respect to the requirements of the vhsic hardware description language effort and how the tasks have been designed to meet the requirements.  al dewey
low power mixed analog-digital signal processing  the power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and accumula?ns, is analyzed. an implementation is proposed, composed of switched-capacitor mixed analog/digital multiply accumulate units in the analog front-end, followed by an a/d converter. this imple?tation is shown to be superior in respect of power consumption compared to an equivalent implementation with a high-speed a/d converter in the front-end, to execute signal processing tasks that include decimation. the power savings are only due to relaxed requirement on a/d conversion rate, as a direct consequence of the decimation. in a case study of a narrowband fir filter, realized with four multiply accumulate units, and with a decimation factor of 100; power saving is 54 times. implementation details are given, the power consumption, and the thermal noise are analyzed.  mattias duppils christer svensson
power estimation approach for sram-based fpgas  this paper presents the power consumption estimation for the novel virtex architecture. due to the fact that the xc4000 and the virtex core architecture are very similar, we used the basic approaches for the xc4000-fpgas power consumption estimation and extended that method for the new virtex family. we determined an appropriate technology-dependent power factor kp to calculate the power consumption on virtex-chips, and developed a special benchmark test design to conduct our investigations. additionally, the derived formulas are evaluated on two typical industrial designs. our own emulation environments called spyder- asic-x1 and spyder-virtex-x2 were used, which are best suited for the emulation of hardware designs for embedded systems.  karlheinz weiß carsten oetker igor katchan thorsten steckstor wolfgang rosenstiel
an automated design of minimum-area ic power/ground nets  given tree topologies for routing power/ground (p/g) nets in integrated circuits, this paper formulates and solves the problem of determining the widths of the branches of the trees. constraints are developed in order to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule and regularity requirements. the area required by the p/g distribution system is minimized subject to these constraints. some case studies are also presented.  s. chowdhury
retiming-based factorization for sequential logic optimization  current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. retiming is typically applied as a postprocessing step to the gate- level implementation obtained after technology mapping. this paper introduces a new sequential logic transformation which integrates retiming with logic transformations at the technology-independent level. this transformation is based on implicit retiming across logic blocks and fanout stems during logic optimization. its application to sequential network synthesis results in the optimization of logic across register boundaries. it can be used in conjunction with any measure of circuit quality for which a fast and reliable gain estimation method can be obtained. we immplemented our new technique within the sis framework and demonstrated its effectiveness in terms of cycle- time minimization on a set sequential benchmark circuits.  surendra bommu niall o'neill maciej ciesielski
towards support for design description languages in eda framework  we report on a new framework service for design tool encapsulation, based on an information model for design management. the new service uses generated language processors that perform import and export of design files to and from a design management database with the support of nested syntax specifications and extension language scripts. our prototype design environment is based on the nelsis cad framework and several tools from the synopsys high-level synthesis and simulation tool suite.  olav schettler susanne heymann
cmos stuck-open fault detection using single test patterns  cmos combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. two or multi- pattern sequences may fail to detect cmos stuck-open faults in the presence of glitches. the available methods for augmenting cmos gates to test cmos stuck- open faults, are found to be inadequate in the presence of glitches. a new cmos testable design is presented. the scheme uses two additional mosfets, which convert a cmos gate to either pseudo nmos or pseudo pmos gate during testing. the proposed design ensures the detection of stuck-open faults using a single vector during testing  r. rajsuman a. p. jayasumana y. k. malaiya
dual-vt sram cells with full-swing single- ended bit line sensing for high- performance on-chip cache in 0.13 m technology generation  comparisons among different dual-vt design choices for a large on-chip cache with single-ended sensing show that the design using a dual-vt cell and low-vt peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-vt cells.  fatih hamzaoglu yibin te ali keshavarzi kevin zhang siva narendra shekhar borkar mircea stan vivek de
recent developments in high-level synthesis  we survey recent developments in high level synthesis technology for vlsi design. the need for higher-level design automation tools are discussed first. we then describe some basic techniques for various subtasks of high-level synthesis. techniques that have been proposed in the past few years (since 1994) for various subtasks of high-level synthesis are surveyed. we also survey some new synthesis objectives including testability, power efficiency, and reliability.  youn-long lin
sharps: a hierarchical layout system for vlsi  a hierarchical layout system for vlsi provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom lsi's.  toru chiba noboru okuda takashi kambe ikuo nishioka tsuneo inufushi seiji kimura
fast transient power and noise estimation for vlsi circuits  today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabilty constraints emerging in vlsi circuits. in this paper a new technique to accurately estimate the transient behavior of large cmos cell- based circuits in a reasonable amount of time is presented. gate-level simulations and a consistent modeling methodology are employed to compute the time-domain waveforms for signal voltages, supply currents, power consumption and Δ noise on power lines. this can be done for circuit blocks and complete designs by our new tool powtim, which adds spice-like capabilities to digital design standards.  wolfgang t. eisenmann helmut e. graeb
lib: a cell layout generator  we present an automatic layout generation system, called lib, for the library cells used in cmos asic design. lib takes a transistor-level circuit schematic in spice format and outputs a symbolic layout. our layout style is similar to that proposed by uehara and van cleemput in [17]. we propose several heuristic algorithms to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems, respectively. experimental results are presented to show the capability of lib.  yung-ching hsieh chi-yi hwang youn-long lin yu-chin hsu
a vlsi design methodology based on parametric macro cells  a new methodology for designing vlsi circuits has been developed at harris gss. the methodology is based on the concept of parametric macro cells. a parametric macro cell is an msi-level circuit which can be modified by a computer program to meet the needs of a particular design. in this paper we discuss the design methodology, chip layout, the simulation techniques and other software tools used to ensure a valid design, plus the wafer testing approach.  r. a. kriete r. k. nettleton
the design and implementation of fault insertion capabilities for isps  fault tolerance is an important attribute of most computer systems, and to be effective it must be an explicit objective from the beginning of the design process. inserting faults into a simulation of the machine and observing its behavior is a thorough and economical technique for evaluating prospective fault detection, diagnosis, recovery, and repair mechanisms. as systems become larger due to rising semiconductor integration, the expense of these fault simulations increasingly necessitates that they be performed at higher levels of abstraction (such as the register transfer level) rather than lower (such as the gate level). this can achieve major cost savings without significantly compromising fault coverage.  this paper describes the design and implementation of a high level fault insertion mechanism for the instruction set processor specification (isps) simulator. the isps simulator was chosen because it is an interactive, high level simulator which is capable, mature, and widely used and accepted. the faults which can be simulated include hard and transient, deterministic and probabilistic, stuck-at and bridged, data, control, and operation types. these facilities have been implemented and demonstrated to be sound in both concept and implementation. they have been incorporated as a standard feature in the latest release of the isps simulator  j. duane northcutt
vvds: a verification/diagnosis system for vhdl  in this paper, an interactive verification and diagnosis system for vhdl [vm88], vvds, is presented. in vvds, hybrid simulation, which simulates with both numerical and symbolic data, is implemented to achieve an effective compromise of the enormous quantity of input test data in the conventional simulation and the complexity of symbolic expression in the symbolic execution. to support efficient user interface in the verification and diagnosis process, both on- line programming of commands and micro-probing capability to passively and actively probe any level of design hierarchy are provided.  h. t. liaw k.-t. tran c.-s. lin
perturb and simplify: multi-level boolean network optimizer  in this paper, we discuss the problem of optimizing a multi-level logic combinational boolean network. our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation atpg based reasoning. in particular, we propose several new ways in which one or more redundant gates or wires can be added to a network. we show how to identify gates which are good candidates for local functionality change. furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network. we also address the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests. we have performed experiments on mcnc benchmarks and compared the results to those of misii and rambo. experimental results are very encouraging.  shih-chieh chang malgorzata marek-sadowska
algorithm selection: a quantitative computation-intensive optimization approach  given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalent algorithms. we demonstrate an extraordinary potential of algorithm selection for achieving high throughput, low cost, and low power implementations.  we introduce an efficient technique for low-bound evaluation of the throughput and cost during algorithm selection and propose a relaxation-based heuristic for throughput optimization. we also present an algorithm for cost optimization using algorithm selection. the effectiveness of methodology and algorithms is illustrated using examples.  miodrag potkonjak jan rabaey
asynchronous and clocked control structures for vlsi based interconnection networks  a central issue in the design of multiprocessor systems is the interconnection network which provides communications paths between the processors. for large systems, high bandwidth interconnection networks will require numerous 'network chips' with each chip implementing some subnetwork of the original larger network. modularity and growth are important properties for such networks since multiprocessor systems may vary in size. this paper is concerned with the question of timing control of such networks. two approaches, asynchronous and clocked, are used in the design of a basic network switching module. the modules and the approaches are then modelled and equations for network time delay are developed. these equations form the basis for a comparison between the two approaches. the importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.  mark a. franklin donald f. wann
chdstd - application support for reusable hierarchical interconnect timing views  this paper describes an important new facility for timing-driven design applications within the new chdstd standard for a sematech design system for large complex chips. we first review eda requirements for chdstd hierarchy for large complex leading edge chips and current eda problems in accurately and efficiently handling complex interconnect. we then describe our approach for fully-reusable hierarchical interconnect timing views in support of timing driven design for 0.25 technologies and below. the result is a method which builds on sematech's new controlled error parasitic timing calculation capability for deep submicron, providing means for compactly storing and reusing accurate hierarchical timing views for 28m to 100m transistor chip designs.  s. grout g. ledenbach r. g. bushroe p. fisher d. cottrell d. mallis s. dasgupta j. morrell amrich chokhavtia
scheduling techniques for variable voltage low power designs  this paper presents an integer linear programming (ilp) model and a heuristic for the variable voltage scheduling problem. we present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. experimental results show that our heuristic produces results competitive with those of the ilp method in a fraction of the run- time. the results also show that a wide range of design alternatives can be generated using our design space exploration method. using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3v and 5v supply voltages.  yann-rue lin cheng-tsung hwang allen c.-h. wu
achieving utility arbitrarily close to the optimal with limited energy  energy is one of the limited resources for modern systems, especially the battery-operated devices and personal digital assistants. the backlog in new technologies for more powerful battery is changing the traditional system design philosophies. for example, due to the limitation on battery life, it is more realistic to design for the optimal benefit from limited resource rather than design to meet all the applications' requirement. we consider the following problem: a system achieves a certain amount of utility from a set of applications by providing them certain levels of quality of service(qos). we want to allocate the limited system resources to get the maximal system utility. we formulate this utility maximization problem, which is np-hard in general, and propose heuristic algorithms that are capable of finding solutions provably arbitrarily close to the optimal. we have also derived explicit formulae to guide the allocation of resources to actually achieve such solutions. simulation shows that our approach can use 99.9% of the given resource to achieve 25.6% and 32.17% more system utilities over two other heuristics, while providing qos guarantees to the application program.  gang qu miodrag potkonjak
prove that a faulty multiplier is faulty!?  formal verification of integer multipliers was an open problem for a long time as the size of any reduced ordered binary decision diagram (bdd) [1] which represents integer multiplication is exponential in the width of the operands [2]. in 1995, bryant and chen [4] introduced multiplicative binary moment diagrams (*bmd) which are a canonical data structure for pseudo boolean functions allowing a linear representation of integer multipliers. based on this data structure, bryant/chen [4] and hamaguchi et.al. [5] experimentally showed that integer multipliers up to a word size of 64 bits can be formally verified. however, all these results only handle the problem of proving a faultless integer multiplier to be correct. but, what happens if the multiplier is faulty? does the backward construction method of hamaguchi et.al. stop after a short time? after what time can i be sure that the integer multiplier under consideration is faulty? in this paper, we show that these questions are relevant in practice. in particular, we investigate simple add- step multipliers and show that simple design errors can lead to exponential growth of the *bmds occuring during backward construction. this proves that the backward construction method can only be applied as filter during formal logic combinational verification unless sharp upper bounds for the sizes of the *bmds occuring during the backward construction have been proven for the various circuit types as keim et.al. [6] did it for wallace tree multipliers.  sandro wefel paul molitor
emerging opportunities for binary tools in recent years, binary instrumentation and optimization tools have been used effectively to understand and improve performance of significant programs. however, new opportunities are emerging in the distributed computing model of the internet that has strong requirements for reliability and performance. these systems demand continuous operations in presence of open-ended design where some parts may be operated by third party services. because we cannot reproduce the scale and complexity of this environment on our desktops or in our labs, our traditional testing-based approaches to correctness and performance optimization will prove insufficient; these tasks must extend beyond the traditional idea of product development.in the past, compilation has been about turning source code into executables, balancing compilation speed against code optimization. binary tools "hacked" their way into the compilation process by intercepting and transforming executables; binary modification stage was not designed to be part of the compilation process. in the new environment, the definition of compilation must broaden: compilation will start very early---perhaps when we write the specification of a program \---and continues very late---perhaps through all the program's various executions on the client machines.this dynamic and heterogeneous environment provides great challenges and opportunities to expand the role of binary tools. this talk discusses the new opportunities and requirements for binary tools. it also describes vulcan, a second generation technology that is designed to address some of these challenges. vulcan has both static and dynamic code modification capabilities. it can provide system level analysis with heterogenoeus programs. vulcan works in the win32 environment and can process x86, ia64, and msii binaries. vulcan can process large commercial applications and has been used to improve performance and reliability of microsoft products in a production environment. amitabh srivastava
logic fault simulation on a vector hypercube multiprocessor  fault simulation is the process of simulating the response of a logic circuit to input patterns in the presence of all possible single faults and is an essential part of test generation for vlsi circuits. parallelization of the deductive and parallel simulation methods, on a hypercube multiprocessor and vectorization of the parallel simulation method are described. experimental results are presented.  f. ozguner c. aykanat o. khalid
a hardware mechanism for dynamic extraction and relayout of program hot spots  this paper presents a new mechanism for collecting and deploying runtime optimized code. the code-collecting component resides in the instruction retirement stage and lays out hot execution paths to improve instruction fetch rate as well as enable further code optimization. the code deployment component uses an extension to the branch target buffer to migrate execution into the new code without modifying the original code. no significant delay is added to the total execution of the program due to these components. the code collection scheme enables safe runtime optimization along paths that span function boundaries. this technique provides a better platform for runtime optimization than trace caches, because the traces are longer and persist in main memory across context switches. additionally, these traces are not as susceptible to transient behavior because they are restricted to frequently executed code. empirical results show that on average this mechanism can achieve better instruction fetch rates using only 12kb of hardware than a trace cache requiring 15kb of hardware, while producing long, persistent traces more suited to optimization.  matthew c. merten andrew r. trick erik m. nystrom ronald d. barnes wen-mei w. hmu
critical path tracing - an alternative to fault simulation  we present an alternative to fault simulation, referred to as critical path tracing, that determines the faults detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. critical path tracing is an approximate method, but the approximations introduced occur seldom and do not affect its usefulness. this method is more efficient than conventional fault simulation.  m. abramovici p. r. menon d. t. miller
performance-driven soft-macro clustering and placement by preserving hdl design hierarchy  in this paper, we present a performance-driven soft-macro clustering and placement method which preserves hdl design hierarchy to guide the soft-macro placement process. we also present a complete chip design methodology by integrating the proposed method and a set of commercial eda tools. experiments on three industrial designs ranging from 75k to 230k gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.  hsiao-pin su allen c.-h. wu youn-long lin