waashk/acm huggingface dataset:
a placement technique based on minimization and even distribution of crossovers  the component placement problem encountered in the design of cards pcb's, etc. is a complex one. although many solutions have been reported, they appear to share one common characteristic, i.e., the objective functions to be optimized are usually based on the classic minimum wiring distance.  the time seems ripe for both industry and academia to realize that better and more effective objective functions are needed. a concept of producing placement by abandoning the traditional distance based criterion is presented. the emphasis is on a minimal number of crossovers and even distributions of these crossovers along some boundaries.  since the concept has not been implemented, there is no numerical data available for comparison. a few points of concern are raised and hopefully they will stimulate further research in the area of component placement.  pao-tsin wang
test generation of stuck-open faults using stuck-at test sets in cmos combinational circuits  in this paper we investigate two aspects regarding the detection of stuck-open (sop) faults using stuck-at test sets. first, we measure the sop fault coverage of stuck-at test sets for various cmos combinational circuits. the sop fault coverage is compared with that of random pattern test sets. second, we propose a method to improve the sop fault coverage of stuck-at test sets by organizing the test sequence of stuck-at test sets. the performance of the proposed method is compared with that of a competing method. experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high sop fault coverage.  h. k. lee d. s. ha k. kim
using architectural "families" to increase fpga speed and density  in order to narrow the speed and density gap between fpgas and mpgas we propose the development of "families" of fpgas. each fpga family is targeted at a single maximum logic capacity, and consists of several "siblings", or fpgas of different yet complementary architectures. any given application circuit is implemented in the sibling with the most appropriate architecture. with properly chosen siblings, one can develop a family of fpgas which will have better speed and density than any single fpga. we apply this concept to create two different fpga families, one composed of architectures with different types of hard-wired logic blocks and the other created from architectures with different types of heterogeneous logic blocks. we found that a family composed of eight chips with different hard-wired logic block architectures simultaneously improves density by 12 to 14% and speed by 18 to 20% over the best single hard-wired fpga.  vaughn betz jonathan rose
an intermediate representation for behavioral synthesis  this paper describes an intermediate representation for behavioral and structural designs that is based on annotated state tables. it facilitates user control of the synthesis process by allowing specification of partially design structures, and a mixture of behavior, structure and user specified bindings between the abstract behavior and the structure. the format's general model allows the capture of synchronous and asynchronous behavior, and permits hierarchical descriptions with concurrency. the format is easily translated to vhdl for simulation at each stage of the design process. it therefore complements a good simulation language (vhdl) by providing an excellent input path for behavioral and register-transfer synthesis. the format's simple and uniform syntax allows it to be used both as an intermediate exchange format for various behavioral synthesis tools, and as a graphical tabular interface for the user, thereby allowing a natural medium for automatic or manual refinement of the design.  nikil d. dutt tedd hadley daniel d. gajski
reliable low-power design in the presence of deep submicron noise (embedded tutorial session)  scaling of feature size in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. this has been the driver for the revolution in communications and computing. however, questions regarding the limits of scaling (and hence moore's law) have arisen in recent years due to the emergence of deep submicron noise. the tutorial describes noise in deep submicron cmos and their impact on digital as well as analog circuits. in particular, noise-tolerance is proposed as an effective means for achieving energy and performance efficiency in the presence of dsm noise.  naresh shanbhag k. soumyanath samuel martin
memory system energy (poster session): influence of hardware-software optimizations  memory system usually consumes a significant amount of energy in many battery- operated devices. in this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms (block buffering and sub-banking) and three widely used compiler optimization techniques (linear loop transformation, loop tiling, and loop unrolling). our results show that the pure hardware optimizations (eight block buffers and four sub-banks in a 4k, 2-way cache) provided up to 4% energy saving, with an average saving of 2% across all benchmarks. in contrast, the pure software optimization approach that uses all three compiler optimizations, provided at least 23% energy saving, with an average of 62%. however, a closer observation reveals that hardware optimization becomes more critical for on-chip cache energy reduction when executing optimized codes.  g. esakkimuthu n. vijaykrishnan m. kandemir m. j. irwin
high-level library mapping for memories  we present high-level library mapping, a technique that synthesizes a source memory module from a library of target memory modules. in this paper, we define the problem of high-level library mapping for memories, identify and solve the three subproblems associated with this task, and finally combine these solutions into a suite of two memory mapping algorithms. experimental results on a number of memory- intensive designs demonstrate that our memory mapping approach generates a wide variety of cost-effective designs, often counter-intuitive ones, based on a user-given cost function, the target library, and the mapping algorithm used.  pradip k. jha nikil d. dutt
an 8ma, 3.8db nf, 40db gain cmos front-end for gps applications  a fully differential 0.35μm cmos lna plus mixer, tailored to a double conversion architecture, for gps applications has been realized. the lna makes use of an inductively degenerated input stage and a resonant lc load, featuring 12% frequency tuning, accomplished by an mos varactor. the mixer is a gilbert cell like, in which an nmos and a pmos differential pair, shunted together, realize the input stage. this topology allows to save power, for given mixer gain and linearity. the front-end measured performances are: 40db gain, 3.8db nf, -25.5dbm iip3, 1.3ghz input frequency, 140mhz output frequency, with 8ma from a 2.8v voltage supply.  f. svelto s. deantoni g. montagna r. castello
efficient and realistic simulation of disk cache performance  this paper describes an improved method for evaluating disk cache performance using trace driven simulation. this method differentiates between reads and writes in the trace data which results in higher miss ratios than when all traced events are treated alike. it allows for simulating various update policies and update intervals, physical blocks that are part of different files at different times, and the optimum replacement policy gopt. these methods are applied to traces from a vax 11/780 running 4.3 bsd unix to illustrate the importance of including writes in the traces and also to analyze the effects of choosing various update intervals.  john f. cigas
timing-driven placement for fpgas  in this paper we introduce a new simulated annealing-based timing-driven placement algorithm for fpgas. this paper has three main contributions. first, our algorithm employs a novel method of determining source-sink connection delays during placement. second, we introduce a new cost function that trades off between wire-use and critical path delay, resulting in significant reductions in critical path delay without significant increases in wire-use. finally, we combine connection-based and path-based timing-analysis to obtain an algorithm that has the low time- complexity of connection-based timing- driven placement, while obtaining the quality of path-based timing-driven placement.  a comparison of our new algorithm to a well known non-timing-driven placement algorithm demonstrates that our algorithm is able to increase the post-place- and-route speed (using a full path-based timing-driven router and a realistic routing architecture) of 20 mcnc benchmark circuits by an average of 42%, while only increasing the minimum wiring requirements by an average of 5%.  alexander marquardt vaughn betz jonathan rose
energy-driven integrated hardware-software optimizations using simplepower  with the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, area, and accuracy/precision as a major design constraint. thus, designers must be concerned with both optimizing and estimating the energy consumption of circuits, architectures, and software. most of the research in energy optimization and/or estimation has focused on single components of the system and has not looked across the interacting spectrum of the hardware and software. the novelty of our new energy estimation framework, simplepower, is that it evaluates the energy considering the system as a whole rather than just as a sum of parts, and that it concurrently supports both compiler and architectural experimentation.  we present the design and use of the simplepower framework that includes a transition- sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition sensitive energy models for the memory and bus subsystems, respectively. we analyzed the energy consumption of ten codes from the multidimensional array domain, a domain that is important for embedded video and signal processing systems, after applying different compiler and architectural optimizations. our experiments demonstrate that early estimates from the simplepower energy estimation framework can help identify the system energy hotspots and enable architects and compiler designers to focus their efforts on these areas.  n. vijaykrishnan m. kandemir m. j. irwin h. s. kim w. ye
using sparse crossbars within lut  in fpgas, the internal connections in a cluster of lookup tables (luts) are often fully-connected like a full crossbar. such a high degree of connectivity makes routing easier, but has significant area overhead. this paper explores the use of sparse crossbars as a switch matrix inside the clusters between the cluster inputs and the lut inputs. we have reduced the switch densities inside these matrices by 50% or more and saved from 10 to 18% in area with no degradation to critical-path delay. to compensate for the loss of routability, increased compute time and spare cluster inputs are required. further investigation may yield modest area and delay reductions.  guy lemieux david lewis
a hardware implementation of gridless routing based on content addressable memory  a new gridless router accelerated by content addressable memory (cam) is presented. a gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. the router runs in linear time by means of the cam-based accelerator. experimental results show that the more obstacles there are in the routing region, the more effective the cam-based approach is.  masao sato kazuto kubota tatsuo ohtsuki
energy-efficient 32 32-bit multiplier in tunable near-zero threshold cmos  an 80,000 transistor, low swing, 32~x~32-bit multiplier was fabricated in a standard 0.35μm,vth=0.5 v cmos process and in a 0.35μm, back-bias tunable, near-zero vth process. while standard cmos atvdd=3.3 v runs at 136 mhz, the same performance can be achieved in the low- vth version at vdd=1.3 v, resulting in more than 5 times lower power. similar power reductions are obtained for frequencies down to 10 mhz. in addition, the low-vth version is able to run at 188 mhz, which is 38% faster than standard cmos.  vjekoslav svilan masataka matsui james b. burr
edge-map: optimal performance driven technology mapping for iterative lut based fpga designs  we consider the problem of performance driven lookup-table (lut) based technology mapping for fp-gas using a general delay model. in the general delay model, each interconnection edge has a weight representing the delay of the interconnection. this model is particularly useful when combined with an iterative re-technology mapping process where the actual delays of the placed and routed circuit are fed-back to the technology mapping phase to improve the mapping based on the more realistic delay estimation. well-known technology mappers such as flowmap and chortle-d only minimize the number of levels in the technology mapped circuit and hence are not suitable for such an iterative re-technology mapping process. recently, mather and liu in [ml94] studied the performance driven technology mapping problem using the general delay model and presented an effective heuristic algorithm for the problem. in this paper, we present an efficient technology mapping algorithm that achieves provably optimal delay in the technology mapped circuit using the general delay model. our algorithm is a non-trivial generalization of flowmap. a key problem in our algorithm is to compute a k-feasible network cut such that the circuit delay on every cut edge is upper- bounded by a specific value. we implemented our algorithm in a lut based fpga technology mapping package called edge-map, and tested edge-map on a set of benchmark circuits.  honghua yang d. f. wong
a memory coherence technique for online transient error recovery of fpga configurations  the partial reconfiguration feature of some of the current-generation field programmable gate arrays (fpgas) can improve dependability by detecting and correcting errors in on-chip configuration data. such an error recovery process can be executed online with minimal interference of user applications. however, because look-up tables (luts) in configurable logic blocks (clbs) of fpgas can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. in this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory- configured luts. theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.  wei-je huang edward j. mccluskey
trace-driven simulations for a two-level cache design in open bus systems  two-level cache hierarchies will be a design issue in future high- performance cpus. in this paper we evaluate various metrics for data cache* designs. we discuss both one- and two- level cache hierarchies. our target is a new 100+ mips cpu, but the methods are applicable to any cache design. the basis of our work is a new trace-driven, multiprocess cache simulator. the simulator incorporates a simple priority-based scheduler which controls the execution of the processes. the scheduler blocks a process when a system call is executed. a workload consists of a total of 60 processes, distributed among seven unique programs with about nine instances each. we discuss two open bus systems supporting a coherent memory model, futurebus+ and sci, as the interconnect system for main memory.  håkon o. bugge ernst h. kristiansen bjørn o. bakka
sequential test generation at the register-transfer and logic levels  the problem of test generation for non-scan sequential vlsi circuits is addressed. a novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register- transfer-level (rtl) design information is presented. our approach is targeted at chips with data-path like stg.  the problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free state justification and fault- free state differentiation. standard combinational test generation algorithms are used to generate test vectors for stuck-at faults in the logic-level implementation. the required state corresponding to the test vector is justified using a fault-free justification step that is performed using the rtl specification. similarly, if the effect of the fault has been propagated by the test vector to the flip-flop inputs alone, the faulty state produced is differentiated from the true next state by a differentiation step that uses the rtl specification.  new and efficient algorithms for fault-free state justification and differentiation on rtl descriptions that contain arithmetic as well as random logic modules are described. unlike previous approaches, this approach does not require the storage of covers or a partial stg and can be used to generate tests for entire chips without scan. exploiting rtl information, together with a new conflict resolution technique results in improvements of up to 100x in performance over sequential test generation techniques restricted to operate at the logic level. we have successfully generated tests for the viterbi speech processor chip [18].  abhijit ghosh srinivas devadas a. richard newton
the performance impact of block sizes and fetch strategies  this paper explores the interactions between a cache's block size, fetch size and fetch policy from the perspective of maximizing system-level performance. it has been previously noted that given a simple fetch strategy the performance optimal block size is almost always four or eight words [10]. if there is even a small cycle time penalty associated with either longer blocks or fetches, then the performance-optimal size is noticeably reduced. in split cache organizations, where the fetch and block sizes of instruction and data caches are all independent design variables, instruction cache block size and fetch size should be the same. for the workload and write-back write policy used in this trace-driven simulation study, the instruction cache block size should be about a factor of two greater than the data cache fetch size, which in turn should equal to or double the data cache block size. the simplest fetch strategy of fetching only on a miss and stalling the cpu until the fetch is complete works well. complicated fetch strategies do not produce the performance improvements indicated by the accompanying reductions in miss ratios because of limited memory resources and a strong temporal clustering of cache misses. for the environments simulated here, the most effective fetch strategy improved performance by between 1.7% and 4.5% over the simplest strategy described above.  steven przybylski
the detection and elimination of useless misses in multiprocessors  in this paper we introduce a new classification of misses in shared-memory multiprocessors based on interprocessor communication. we identify the set of essential misses, i.e., the smallest set of misses necessary for correct execution. essential misses include cold misses and true sharing misses. all other misses are useless misses and can be ignored without affecting the correctness of program execution. based on the new classification we compare the effectiveness of five different protocols which delay and combine invalidations leading to useless misses. in cache-based systems the protocols are very effective and have miss rates close to the essential miss rate. in virtual shared memory systems the techniques are also effective but leave room for improvements.  michel dubois jonas skeppstedt livio ricciulli krishnan ramamurthy per stenström
algorithms to compute bridging fault coverage of i&amp;l; t;/bold>ddq test sets  we present two algorithms, called list-based scheme and tree-based scheme, to compute bridging fault (bf) coverage of i ddq tests. these algorithms use the novel ideal of "indistinguishable pairs," which makes it more efficient and versatile than known fault simulation algorithms. unlike known algorithms, the two algorithms can be used for combinational as well as sequential circuits and for arbitrary sets of bfs. experiments show that the tree-based scheme is, in general, better than the list-based scheme. but the list-based scheme is better for some classes of faults.  paul thadikaran sreejit chakravarty janak patel
the difference-bit cache the difference-bit cache is a two-way set-associative cache with an access time that is smaller than that of a conventional one and close or equal to that of a direct-mapped cache. this is achieved by noticing that the two tags for a set have to differ at least by one bit and by using this bit to select the way. in contrast with previous approaches that predict the way and have two types of hits (primary of one cycle and secondary of two to four cycles), all hits of the difference-bit cache are of one cycle. the evaluation of the access time of our cache organization has been performed using a recently proposed on-chip cache access model. toni juan tomás lang juan j. navarro
a symbolic design system for integrated circuits  as integrated circuit design has become increasingly complex, the need for more effective data description techniques has become critical. design verification from mask artwork data alone can consume vaste amounts of computer time for vlsi circuits, if it can be performed at all. the use of a symbolic design description, which allows the designer or synthesis program to express circuit structure as well as maintain full connectivity information, can reduce dramatically the burden placed on the verification tools: this paper describes a symbolic design system, its associated data manager, its color graphics viewport manager, and its application to a variety of design methods. the data manager can store a variety of representations of the design, including simulation data, geometric layout, symbolic layout, and schematic diagrams. the viewport manager can manage a number of viewports concurrently and the use of a model frame buffer allows it to function easily on a variety of graphics terminals and hard-copy devices. the system is designed with an engineering work station in mind.  k. h. keller a. r. newton s. ellis
plowing: modifying cells and routing 45:9d - layouts  this paper describes a plowing procedure which moves and modifies cells and routing. the plow pushes aside all obstacles one by one, thus penetrating into the layout. the process leads to a compaction at the front side of the plow. the compaction is performed in accordance with the minimum spacing rules and with automatic jog insertion. objects of the layout representation are cells, contacts, and wires. a wire is represented by a path of segments which lie in one of two layers, at angles of multiples of 45 . the generated blank space is used for adding new objects or resizing geometries.  k. m. just w. l. schiele t. kruger