waashk/acm huggingface dataset:
testing functional faults in vlsi  functional testing has become increasingly important due to the advent of vlsi technology. this paper presents a systematic procedure for generating tests for detecting functional faults in digital systems described by the register transfer language. procedures for testing register decoding, instruction decoding, data transfer, data storage and data manipulation function faults in microprocessors are described step-by-step. examples are given to illustrate the procedures.  yinghua min stephen y.h. su
heuristic tradeoffs between latency and energy consumption in register assignment  one of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein one decides on the placement and lifetimes of variables in registers. when there are more live variables than registers, some variables need to be spilled to memory and restored later. in this paper we propose a policy that minimizes the number of spills --- which is critical for portable embedded systems since it leads to a decrease in energy consumption. we argue however, that schedules with a minimal number of spills do not necessarily have minimum latency. accordingly, we propose a class of policies that explore tradeoffs between assignments leading to schedules with low latency versus those leading to low energy consumption and show how to tune them to particular datapath characteristics. based on experimental results we propose a criterion to select a register assignment policy that for 99% of the cases we considered minimizes both latency and energy consumption associated with spills to memory.  r. anand m. jacome g. de veciana
genac: an automatic cell synthesis tool  we present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. in particular, we propose a new hierarchical method for fast and optimal placement of the transistors in a cell. the method minimizes the number of diffusion breaks, and allows a further pursuit of a secondary optimization objective, such as routing channel density. for cells with non- uniform transistor widths, the transistors are folded in such a way as to optimize a cost function which is a good approximation to the area of the final(compacted) layout of the cell. we also analyze the characteristic nature of routing in cell generation problem, and design an algorithm for doing routing over the transistors; such routing reduces the routing channel density in the central region of the cell. the routing in the central region is completed by a new channel router at, or near, the channel density. the algorithms are implemented in a system call genac. the input to genac is a transistor net list, describing the connectivity as well as the size and type of each transistor. the output is a synthesized layout of the cell in symbolic language.  c.-l. ong j.-t. li c.-y. lo
data prefetch mechanisms  the expanding gap between microprocessor and dram performance has necessitated the use of increasingly aggressive techniques designed to reduce or hide the latency of main memory access. although large cache hierarchies have proven to be effective in reducing this latency for the most frequently used data, it is still not uncommon for many programs to spend more than half their run times stalled on memory requests. data prefetching has been proposed as a technique for hiding the access latency of data referencing patterns that defeat caching strategies. rather than waiting for a cache miss to initiate a memory fetch, data prefetching anticipates such misses and issues a fetch to the memory system in advance of the actual memory reference. to be effective, prefetching must be implemented in such a way that prefetches are timely, useful, and introduce little overhead. secondary effects such as cache pollution and increased memory bandwidth requirements must also be taken into consideration. despite these obstacles, prefetching has the potential to significantly improve overall program execution time by overlapping computation with memory accesses. prefetching strategies are diverse, and no single strategy has yet been proposed that provides optimal performance. the following survey examines several alternative approaches, and discusses the design tradeoffs involved when implementing a data prefetch strategy.  steven p. vanderwiel david j. lilja
a new method for verifying sequential circuits  we present an algorithm for deciding whether two given synchronous, logic- level sequential circuits are functionally equivalent. our approach involves a formal symbolic comparison, as opposed to the (often very time-consuming) generation and simulation of numerous test vector sequences. the given circuits need not have the same number of states, nor must they have the same number of inputs --- for example, one circuit may be a parallel implementation and the other serial. although this is an intractable problem in general, we believe that the method is useful on a broad class of practical circuits; our computational experience thus far is encouraging.  kenneth j. supowit steven j. friedman
the inversion algorithm for digital simulation  the inversion algorithm is an event-driven algorithm, whose performance rivals or exceeds that of levelized compiled code simulation, even at activity rates of 50% or more. the inversion algorithm has several unique features, the most remarkable of which is the size of the run-time code. the basic algorithm can be implemented using no more than a page of run-time code, although in practice it is more efficient to provide several different variations of the basic algorithm. the run-time code is independent of the circuit under test, so the algorithm can be implemented either as a compiled code or an interpreted simulator with little variation in performance. because of the small size of the run-time code, the run-time portions of the inversion algorithm can be implemented in assembly language for peak efficiency, and still be retargeted for new platforms with little effort.  peter m. maurer
a model of shared dasd and multipathing  this paper presents a model of an i/o subsystem in which devices can be accessed from multiple cpus and/or via alternative channel and control unit paths. the model estimates access response times, given access rates for all cpu-device combinations. the systems treated are those having the ibm system/370 architecture, with each path consisting of a cpu, channel, control unit, head of string, and device with rotational position sensing. the path selected for an access at seek initiation time remains in effect for the entire channel program.  the computation proceeds in three stages: first, the feasibility of the prescribed access rates is determined by solving a linear programming problem. second, the splitting of access rates among the available paths is determined so as to satisfy the following principle:  the probability of selecting a given path is proportional to the probability that the path is free.  this condition leads to a set of nonlinear equations, which can be solved by means of the newton-raphson method.  third, the rps hit probability, i.e. the probability that the path is free when the device is ready to transmit, is computed in the following manner: from the point of view of the selected path, the system may be viewed as being in one of 25 possible states. there are twelve different subsets of states whose aggregate probabilities can be computed from the (by now) known flow rates over the various paths. the maximum entropy principle is used to calculate the unknown state probabilities, with the known aggregate probabilities acting as constraints. the required rps hit probability can be computed easily once the state probabilities have been determined. explicit formulas are given for all these quantities. empirically derived formulas are used to compute the rps miss probability on subsequent revolutions, given the probability on the first revolution.  the model is validated against a simulator, showing excellent agreement for systems with path utilizations up to 50 percent. the model is also validated against measurements from a real three- cpu system with 31 shared devices. in this validation, the i/o subsystem model acts as a common submodel to three copies of a system model, one for each cpu. estimated end-user transaction response times show excellent agreement with the live measurements.  yonathan bard
evaluation of a high performance code compression method  compressing the instructions of an embedded program is important for cost- sensitive low- power control-oriented embedded computing. a number of compression schemes have been proposed to reduce program size. however, the increased instruction density has an accompanying performance cost because the instructions must be decompressed before execution. in this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in ibm's powerpc 405. this scheme is the first to combine many previously proposed code compression techniques, making it an ideal candidate for study. we find that code compression with appropriate hardware optimizations does not have to incur much performance loss. furthermore, our studies show this holds for architectures with a wide range of memory configurations and issue widths. surprisingly, we find that a performance increase over native code is achievable in many situations.  charles lefurgy eva piccininni trevor mudge
logic simulation for lsi  this paper describes the logic simulation system and the design verification method for logic design, timing analysis, and testing for vlsi. the integrity of test and network data on a logic design stage must be kept in lsi testing in the final verification stage. in dealing with consistency, emphasis is placed on the discrepancy between the real time domain on a simulator and a testing time domain on an lsi tester. the logic simulation system (block integrator and analyzer: binaly) handles a hierarchical structure, a detailed timing model, and a timing alignment method for a testing time domain.  kazuyuki hirakawa noboru shiraki michiaki muraoka
smap: heterogeneous technology mapping for area reduction in fpgas with embedded memory arrays  it has become clear that large embedded configurable memory arrays will be essential in future fpgas. embedded arrays provide high-density high-speed implementations of the storage parts of circuits. unfortunately, they require the fpga vendor to partition the device into memory and logic resources at manufacture-time. this leads to a waste of chip area for customers that do not use all of the storage provided. this chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi- output roms, and used to implement logic.  in order to efficiently use the embedded arrays in this way, a technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array is required. in this paper, we describe such an algorithm. the new tool, called smap, packs as much circuit information as possible into the available memory arrays, and maps the rest of the circuit into four-input lookup-tables. on a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 60 4-luts into a single 2-kbit memory array. if there are 16 arrays available, it can map, on average, 358 4-luts to the 16 arrays.  steven j. e. wilton
memory consistency and event ordering in scalable shared-memory multiprocessors  scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. in addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory and the fast processors. unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. the set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.  this paper introduces a new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models. a framework for classifying shared accesses and reasoning about event ordering is developed. the release consistency model is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. possible performance gains from the less strict constraints of the release consistency model are explored. finally, practical implementation issues are discussed, concentrating on issues relevant to scalable architectures.  kourosh gharachorloo daniel lenoski james laudon phillip gibbons anoop gupta john hennessy
a benchmark suite for evaluating configurable computing systems - status, reflections, and future directions  this paper presents a benchmark suite for evaluating a configurable computing system's infrastructure, both tools and architecture. a novel aspect of this work is the use of stressmarks, benchmarks that focus on a specific characteristic or property of interest. this is in contrast to traditional approaches that utilize functional benchmarks, benchmarks that emphasize measuring end-to-end execution time. this suite can be used to assess a broad range of configurable computing systems, including single configurable devices, multiple configurable devices, and mixed architectures, such as fixed-plus-variable devices and hybrid systems. in addition, aspects that are particularly relevant to the domain of configurable computing, such as run- time reconfiguration and variable precision arithmetic, are considered. the paper provides an overview of the benchmark suite, presents some implementation results on an annapolis micro systems wildforce board, reflects on the benchmark suite developed, and briefly describes future work.  s. kumar l. pires s. ponnuswamy c. nanavati j. golusky m. vojta s. wadi d. pandalai h. spaanenberg
optimal design of synchronous circuits using software pipelining techniques we present a method to optimize clocked circuits by relocating and changing the time of activation of registers to maximize the throughput. our method is based on a modulo scheduling algorithm for software pipelining, instead of retiming. it optimizes the circuit without the constraint on the clock phases that retiming has, which permits to always achieve the optimal clock period. the two methods have the same overall time complexity, but we avoid the computation of all pair-shortest paths, which is a heavy burden regarding both space and time. from the optimal schedule found, registers are placed in the circuit without looking at where the original registers were. the resulting circuit is a multi-phase clocked circuit, where all the clocks have the same period and the phases are automatically determined by the algorithm. edge- triggered flip-flops are used where the combinational delays exactly match that period, whereas level-sensitive latches are used elsewhere, improving the area occupied by the circuit. experiments on existing and newly developed benchmarks show a substantial performance improvement compared to previously published work. françois r. boyer el mostapha aboulhamid yvon savaria michel boyer
big science versus little science - do you have to build it? (panel session)  research can be called big science if projects have numerous researchers, large funding, significant infrastructure, and plans to build complex tools or prototypes. most experimental physicists practice big science, as do computer architects who build prototype software- hardware systems.  conversely, research can be called little science when projects have few researchers, modest funding, little special infrastructure, and no plans to build complex tools or prototypes. most mathematicians practice little science, as do computer architects who study aspects of a design and build confidence in their proposals with models or simulations.  a very simple model contrasting the two approaches is illustrated below, where money flows from governments (gov) to academia (edu) which produce ideas for industry (com) to make better products for all (pop). a key difference is whether governments fund a few, large research projects or many, smaller ones.  the goal of this session is explore whether, when and why universities should do big or little science. panelists may discuss why big science wastes money, exploits graduate students and makes research too short range. they may argue that little science produces results that are too deep and narrow, oblivious to global systems issues, not properly validated, and too out of touch with reality to ever be practical. panelists may also find some advantages to both kinds of science.  panelists include members from government, academia and industry, who are also members of the general population. to keep the discussion lively, nothing said necessarily represents the opinion of any government agency, university or corporation with whom panelists are affiliated.  david r. ditzel john l. hennessy bernie rudin alan jay smith stephen l. squires zeke zalcstein
futurebus+ as an i/o bus: profile b  the ieee futurebus+ is a very fast (3gb/sec.), industry standard backplane bus specification for computer systems. futurebus+ was designed independent of any cpu architecture so it is truly open. with this open architecture futurebus+ can be applied to many different computing applications. profile b is a subset of the ieee 896 futurebus+ standard and targets high performance, general purpose computer i/o applications. this paper describes how and why the functional, electrical, mechanical and environmental characteristics were chosen.  barbara p. aichinger
improving branch predictors by correlating on data values  branch predictors typically use combinations of branch pc bits and branch histories to make predictions. recent improvements in branch predictors have come from reducing the effect of interference, i.e. multiple branches mapping to the same table entries. in contrast, the branch difference predictor (bdp) uses data values as additional information to improve the accuracy of conditional branch predictors. the bdp maintains a history of differences between branch source register operands, and feeds these into the prediction process.  an important component of the bdp is a rare event predictor (rep) which reduces learning time and table interference. an rep is a cache-like structure designed to store patterns whose predictions differ from the norm.  initially, ideal interference-free predictors are evaluated to determine how data values improve correlation. next, execution driven simulations of complete designs realize this potential. the bdp reduces the misprediction rate of five spec95 integer benchmarks by up to 33% compared to gshare and by up to 15% compared to bi-mode predictors.  timothy h. heil zak smith j. e. smith
libra - a library-independent framework for post-layout performance optimization  in this paper we present a post-layout timing optimization framework which (1) is library-independent such that it can take the logic-optimized verilog file as its input netlist, (2) provides a prototype interface which can communicate with any vendor's physical design tools to obtain the accurate timing, topological and physical information, and perform eco placement and routing, and (3) has fast and powerful rewiring routines that offer an extra solution space beyond the existing physical-level optimization methodologies. we conduct the post-layout performance optimization experiments on some benchmark circuits which are originally optimized by synopsys's design compiler, (with high timing effort), followed by avant!'s timing-driven place-and-route tool, apollo. the optimization strategies we used include rewiring, buffer insertion, and cell sizing. to study the trade-offs between these transformations and the benefits of mixing them together, they are applied both separately and closely integrated by some heuristic cost functions. the result shows that by using all these strategies, post-layout timing optimization can further achieve up to 23.9% of improvement after global routing. we also discuss the pros and cons for our proposed procedures applied after global routing versus after detail routing. some factors that can affect the quality of rewiring such as level of recursive learning and type of rewiring will also be addressed.  ric chung-yang huang yucheng wang kwang-ting chen
allocation of fifo structures in rtl data paths  along with functional units, storage and interconnects contribute significantly to data path costs. this paper addresses the issue of reducing the costs of storage and interconnect. in a post-datapath synthesis phase, one or more queues can be allocated and variables bound to it, with the goal of reducing storage and interconnect costs. further, in contrast to earlier work, we support "irregular" cdfgs and multicycle functional units for queue synthesis. initial results on hls benchmark examples have been encouraging, and show the potential of using queue synthesis to reduce datapath cost. a novel feature of our work is the formulation of the problem for a variety of fifo structures with their own "queueing" criteria.  m. balakrishnan heman khanna
multi-stack optimization for data-path chip (microprocessor) layout  as data-path chips such as microprocessors and risc chips become more complex, multiple stacks of data-path macros are required to implement the entire data- path. the physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible. this paper describes a special multi-stack structure, optimization techniques and algorithms to partition, place and wire the data-path macros in the form of the multi-stack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). the overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wireability, including stack to random logic wireability, and (3) to minimize wire lengths for wireability and timing. a tool for automatic multi- stack optimization has been implemented and applied successfully to layout some high density data-path chips.  w. k. luk a. a. dean
vlsi, computer science, and synergetic research  "the lsi and vlsi revolution" has probably become one of the most frequently mentioned phrases in discussions concerning technology trends. microprocessors have entered most of our homes, offices and laboratories. students in universities have begun to learn chip design, and prototype chips are routinely being designed and fabricated for various research projects. what will be the impacts of vlsi to us as computer scientists and to the discipline of computer science in general? i believe that the impacts will be profound and will be much greater than most of us can imagine today. in this talk i will present a simplified view of this matter. in particular, i will suggest a style of synergetic system research as a model to explore the potential of vlsi, an area where impressive advances have been made in recent years and are expected to continue the foreseeable future.  h. t. kung
a comparative study of power efficient sram designs  _this paper investigates the effectiveness of combination of different low power sram circuit design techniques. the divided bit line (dbl), pulsed word line (pwl) and isolated bit line (ibl) strategies have been implemented in a various size sram designs and evaluated using 0.35micron technology and 3.3v vdd at 100mhz frequency. different decoder structures have been investigated for their power efficiency as well. it is observed that the power reduces by 29%, 32% and 52% over an unoptimized sram design when (pwl_+_ibl), (pwl_+_dbl) and (pwl_+_ibl_+_dbl) are implemented in a 256*2 size sram respectively._  jeyran hezavei n. vijaykrishnan m. j. irwin