waashk/acm huggingface dataset:
the yorktown simulation engine: introduction  the yorktown simulation engine (yse) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. it can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the ibm 3081 processor could have been simulated on the yse at a rate of 1000 instructions per second. this is far beyond the capabilities of existing register-level software simulators. the yse has been designed and is being constructed at the ibm t. j. watson research center. this paper introduces the yse and describes its top-level architecture.  gregory f. pfister
power reduction and power-delay trade-offs using logic transformations  we present an efficient technique to reduce the switching activity in a technology-mapped cmos combinational circuit based on local logic transformations. the transformations consist of adding redundant connections or gates so as to reduce switching activity. we describe simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections. additionally, we give procedures that permit the designer to trade-off power and delay after the transformations. results of experiments on both the mcnc benchmark circuits and the circuits of a powerpc microprocessor chip are given. the results indicate that significant power reduction of a cmos combinational circuit can be achieved with very low area overhead, delay penalty, and computational cost.  qi wang sarma b. k. vrudhula gary yeap shantanu ganguly
on testing delay faults in macro-based combinational circuits  we consider the problem of testing for delay faults in macro-based circuits. macro-based circuits are obtained as a result of technology mapping. gate- level fault models cannot be used for such circuits, since the implementation of a macro may not have an accurate gate-level counterpart, or the macro implementation may not be known. two delay fault models are proposed for macro-based circuits. the first model is analogous to the gate-level gross delay fault model. the second model is analogous to the gate-level path delay fault model. we provide fault simulation procedures, and present experimental results.  irith pomeranz sudhakar m. reddy
efficient strategies for software-only protocols in shared-memory multiprocessors the cost, complexity, and inflexibility of hardware-based directory protocols motivate us to study the performance implications of protocols that emulate directory management using software handlers executed on the compute processors. an important performance limitation of such software-only protocols is that software latency associated with directory management ends up on the critical memory access path for read miss transactions. we propose five strategies that support efficient data transfers in hardware whereas directory management is handled at a slower pace in the background by software handlers. simulations show that this approach can remove the directory-management latency from the memory access path. whereas the directory is managed in software, the hardware mechanisms must access the memory state in order to enable data transfers at a high speed. overall, our strategies reach between 60% and 86% of the hardware-based protocol performance. håkan grahn per stenström
microarchitecture description techniques  a procedure is outlined for describing the microarchitecture of a horizontal processor such that a retargetable microprogram compiler system can incorporate the description to generate microcode for that processor. the microarchitecture description methodology is an organized approach to defining a machine's microinstruction formats, fields, and microorders; its hardware elements; its microoperation usage rules; and its behavioral rules. to a large extent, the description procedure can be performed interactively. the link between the microarchitecture description and the microprogram compiler, termed the instruction set interpretation mechanism, is also described. preliminary application of the microarchitecture description methodology to several real processors has shown that, despite some problems, the procedure shows promise for significantly reducing the time required to retarget a microprogram compiler.  john l. gieser robert j. sheraga
analysis and design of low-phase-noise ring oscillators  this paper presents a framework for cmos ring oscillator phase noise analysis for given power consumption specifications. this model considers both linear and nonlinear operations. it indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. our phase noise model is validated via simulation and measurement results. we also present a coupled-ring oscillator whose phase noise is -114 dbc/hz at a 600 khz offset from the 960 mhz carrier frequency.  liang dai ramesh harjani
automatic operator configuration in the synthesis of pipelined architectures  we present an algorithm for automating the choice of operator configurations while synthesizing a pipelined design. the chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g. area, power) of the design. the configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches; then optimally to choose configurations within each stage. some advantages to this new algorithm are that it will allow the designer to specify both the number of stages as well as the latency of each stage, and that it will take arbitrary timing functions.  kristen n. mcnall albert e. casavant
parallel circuit simulation using hierarchical relaxation  this paper describes a class of parallel algorithms for circuit simulation based on hierarchical relaxation that has been implemented on the cedar multiprocessor. the cedar machine is a reconfigurable, general- purpose supercomputer that was designed and implemented at the university of illinois. a hierarchical circuit simulation scheme was developed to exploit the hierarchical organization of cedar. the new algorithm and a number of key issues, such as multilevel circuit partitioning, data partitioning, cluster algorithm selection, and cluster algorithm implementation are described in this paper. performance results on a variety of different configurations of cedar are also presented that illustrate the benefits of the hierarchical approach over the non-hierarchical approach.  g. g. hung y. c. wen k. gallivan r. saleh
cmos system-on-a-chip voltage scaling beyond 50nm  _the limits on cmos energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for cmos generations beyond 50nm at ntrs projected local and global clock rates for high performance processors. physical short-channel mosfet models that consider high-field effects, threshold voltage roll-off and reverse subthreshold swing roll-off are employed in tandem with stochastic interconnect distributions to calculate optimal supply voltage, threshold voltage and gate sizes that minimize total cmos power dissipation by exploiting trade-offs between saturation drive current and subthreshold leakage current and between device size and wiring capacitance. cmos power dissipation at its lower limit, increases exponentially with clock frequency imposing limits on performance set by heat removal. heat removal constraints at high local clock rates, limiting the average wire length and device size within a local zone of synchrony, or macrocell, in a short-wire cellular array architecture are used to project the maximum macrocell size and count for generations beyond 100nm._  azeez j. bhavnagarwala blanca austin ashok kapoor james d. meindl
crosscheck: a cell based vlsi testability solution  a new testability solution is proposed in which externally accessible test points are pre- designed into cells that comprise the vlsi designs. the test points are accessed through an on-chip grid of orthogonal probe and sense lines. the resultant vlsi design consists of a large number of test points through which test signals on every cell on the ic can be measured or modified to a limited extent. the sizable number of test points improves the testability of the designs by a very large factor. additionally, analog measurement and signal injection capabilities allow detection of practical cmos fault modes such as opens, shorts, open or closed fet's and even noise margins.  the large observability of crosscheck based designs reduces the automatic test pattern generation problem to one of providing control only. several iscas benchmark designs are analyzed using crosscheck cell libraries and fault models. the results show that over 97 percent coverage of a broad range of fault modes, such as opens and shorts, can be obtained on vlsi cmos designs without the need for large computing resources.  t. ghewala
a fast and memory-efficient diagnostic fault simulation for sequential circuits  in this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. in it, a two-level optimization technique is developed and used to prompt the processing speed. in the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus the number of diagnostic comparisons is minimized. in the second low level, a bit-parallel comparison is developed to speed up the comparing process. therefore, the different diagnostic measure reports for a given test set can be generated very quickly. in addition, the simulator is extended to diagnose the single stuck-at device fault. experimental results show that this diagnostic simulator achieves a significant speedup compared to previous methods.  jer min jou shung-chih chen
an efficient delay test generation system for combinational logic circuits  this paper presents an efficient delay test generation system for combinational logic circuits. delay testing problems are divided into gross delay fault testing and small delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. complete automatic test pattern generation algorithms are proposed for both gross delay faults and small delay faults. especially for the small delay fault test generation, new search space enumeration techniques are employed so as to bias the search space such that a delay test for relatively long paths can be found. also a novel timing analysis method via functionality check is presented for delay test generation. finally, complete test results are demonstrated for both gross delay faults and small delay faults on several benchmark circuits.  eun sei park m. ray mercer
two-dimensional compaction by "zone refining"  a new technique for 2-dimensional layout compaction of integrated circuits is presented. after a traditional one-dimentional precompaction step, the size of the layout is further reduced with a technique that bears a strong similarity to the technique of 'zone-refining' used in the purification of crystal ingots. individual circuit components or small clusters of components are peeled off row by row from the precompacted layout, moved across an open zone, and reassembled at the other end of this zone in a denser configuration. in this process both coordinates of the moved components are altered and jogs are introduced in the connecting wires between them to produce the needed flexibility for placing components into optimal positions. the constraint graphs in both the x- and y-direction are used and updated concurrently.  hyunchul shin alberto l. sangiovanni-vincentelli carlo h. sequin
partitioning sequential circuits on dynamically reconfiguable fpgas  a fundamental feature of dynamically reconfigurable fp-gas (drfpgas) is that the logic and interconnect is time-multiplexed. thus for a circuit to be implemented on a drfpga, it needs to be partitioned such that each subcircuit can be executed at a different time. in this paper, the partitioning of sequential circuits for execution on a drf-pga is studied. to determine how to correctly partition a sequential circuit, and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. we also introduce an enchanced force directed scheduling (fds) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. we use our algorithm to partition seven large isc as'89 sequential benchmark circuits. the experimental results show that the enhanced fds reduces communication costs by 27.5% with only a 1.1% increase in the gate cost compared to traditional fds.  douglas chang malgorzata marek-sadowska
confidence analysis for defect-level estimation of vlsi random testing  the defect level in circuit testing is the percentage of circuits such as chips, that are defective and shipped for use after testing. our previously published results showed that the defect level of circuit fabrication and testing should be a probability distribution, rather than a single value, and the concept of confidence degree was proposed [gondalia et al. 1993; jone et al. 1995]. in this work, defect level is represented by a confidence interval which is more conventional and easier to interpret. the point estimate of defect level analysis and conditions to avoid meaningless confidence intervals are also investigated. methods for adaptive random test length determination driven by different confidence intervals or interval length are proposed to meet both test requirements and test costs tradeoff. finally, a complete test plan that can direct the test flow from fabrication infancy to maturity is suggested.  wen-ben jone k. s. tsai
algorithmic transforms for efficient energy scalable computation  we introduce the notion of energy scalable computation on general purpose processors. the principle idea is to maximize computational qualityfor a given energy constraint. teh desirable energy-quality behavior of algorithms is discussed. subsequently the energy-quality scalability of three distinct categories of commonly used signal processing algorithms (viz. filtering, frequency domain transforms and classification) are analyzed on the strongarm sa-1100 processor and transformations are described which obtain significant improvements in the energy-quality scalability of the algorithm.  amit sinha alice wang anantha p. chandrakasan
software support for the yorktown simulation engine  the yorktown simulation engine (yse) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. the yse has been designed and is being constructed at the ibm t. j. watson research center. it can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the ibm 3081 processor could have been simulated on the yse at a rate of 1000 instructions per second. this is far beyond the capabilities of existing register-level software simulators. this paper describes the software support for the yse.  e. kronstadt g. pfister
experiments with the slim circuit compactor  experiments performed with the slim symbolic circuit compactor are described. the experiments were designed to compare slim created modules to manually created modules, to attempt to find performance predictors for slim, and to determine how well slim would compact modules created by a "synthesis-by- refinement" program. the results indicate that slim compacts modules which will be created by this program as area efficiently as it compacts modules created by other methods. also, a performance predictor which estimates the area required by slim generated modules was developed. finally, it was found that slim's designs are larger than manual designs by 60% to 90%.  ralph c. mcgarity daniel p. siewiorek
the economics of programmable system components  integrated circuits having complexity levels approaching one million devices per chip (vlsi) present significant problems in the cost of design and use. there are advocates for very capable design automation techniques coupled with rapid turnaround front ends as the path to vlsi. others advocate the use of programmable devices such as microcomputers and gate arrays. this paper presents cost models for these two approaches which demonstrate that the programmable system component (psc) approach is the only viable path in vlsi. this paper will also describe a set of generic pscs which will meet the needs of 70%-80% of the sockets, and perhaps 95% of the production volume for vlsi components. the remaining 20%-30% of the sockets and 5% of the volume will be served by specific, nonprogrammable designs.  harvey g. cragon
an automatic routing system for high density multilayer printed wiring boards  recent advances in the packaging technology of microelectronics have changed the design rules for printed wiring boards (pwb's) such that the number of wiring tracks between adjacent pins of an ordinary dual in line package (dip) is allowed to be two or more, and the number of signal layers to be laminated is often required to be four or more. when the packaging density or scale of a pwb augments to such an extent, conventional routing schemes are confronted with various difficulties.  the present paper describes a new routing system which can cope with such high density pwb's, for which the maximum numbers of layers to be laminated, circuit modules to be mounted, and signal nets are admitted up to 16, 2,000 and 4,000, respectively. the system described operates on a pdp 11/34 computer coupled with a tektronix 4014 graphics terminal. a set of implementation results are also shown to reveal how much the described system contributes to the reduction of time and labor incurred in laying out multilayer pwb's of high density.  ikuo nishioka takuji kurimoto hisao nishida seiji yamamoto toru chiba toshiaki nagakawa takatsugu fujioka masashi uchino
the architecture of a fault-tolerant cached raid controller  raid-5 arrays need 4 disk accesses to update a data block---2 to read old data and parity, and 2 to write new data and parity. schemes previously proposed to improve the update performance of such arrays are the log-structured file system [10] and the floating parity approach [6]. here, we consider a third approach, called fast write, which eliminates disk time from the host response time to a write, by using a non-volatile cache in the disk array controller. we examine three alternatives for handling fast writes and describe a hierarchy of destage algorithms with increasing robustness to failures. these destage algorithms are compared against those that would be used by a disk controller employing mirroring. we show that array controllers require considerably more (2 to 3 times more) bus bandwidth and memory bandwidth than do disk controllers that employ mirroring. so, array controllers that use parity are likely to be more expensive than controllers that do mirroring, though mirroring is more expensive when both controllers and disks are considered.  jai menon jim cortney
virtual-channel flow control  network throughput can be increased by dividing the buffer storage associated with each network channel into several virtual channels [dalsei]. each physical channel is associated with several small queues, virtual channels, rather than a single deep queue. the virtual channels associated with one physical channel are allocated independently but compete with each other for physical bandwidth. virtual channels decouple buffer resources from transmission resources. this decoupling allows active messages to pass blocked messages using network bandwidth that would otherwise be left idle. simulation studies show that, given a fixed amount of buffer storage per link, virtual- channel flow control increases throughput by a factor of 3.5, approaching the capacity of the network.  william j. dally
standard cell placement using simulated sintering  simulated annealing is a powerful optimization technique based on the annealing phenomenon in crystallization. in this paper we propose a simulated sintering technique which is analogous to the sintering process in material processing. in sintering one improves the quality of a processed material by heating it to a temperature close to the melting point. analogously, we show that by starting out with a good initial configuration instead of a random configuration, and restricting uphill moves, we can considerably speed up simulated annealing. we use this idea for a standard cell placement program - grim in ltx2, an at&amp;t; bell labs vlsi layout system. the initial configuration is produced either by changes to a layout the designer had done previously, or else by a fast program like min-cut. we obtain improvements of about 10% in chip area starting from a min-cut placement, in times about 3 times faster than our simulated annealing program (which itself is several times faster than other well known simulated annealing programs).  l. k. grover
an empirical evaluation of two memory-efficient directory methods  this paper presents an empirical evaluation of two memory-efficient directory methods for maintaining coherent caches in large shared memory multiprocessors. both directory methods are modifications of a scheme proposed by censier and feautrier [5] that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. the schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. in the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. in the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-writeable data is not cached. the large block sizes required for the sectored scheme, however, promotes sufficient false sharing that its performance is markedly worse than using a tag cache.  brian w. o'krafka a. richard newton
on routing for custom integrated circuits  this paper presents a novel and effective strategy for routing custom integrated circuits as well as solutions to subproblems associated with this strategy. given an initial placement of rectangular blocks, the routing strategy includes the following major steps: construction of a channel graph, estimation of channel widths (based on a statistical model for signal nets and topological routing of power and ground nets), placement modification to include the estimated channel widths, topological routing for signal nets, and finally track assignment.  besides presenting an overview of our strategy, the following topics will be discussed in some detail: (1) necessary and sufficient conditions and a simple algorithm for single layer topological routing of power and ground nets, (2) a quadratic programming formulation for the placement modification problem, and (3) a fast algorithm for obtaining topological routes for signal nets.  zahir syed abbas el gamal m. a. breuer
on a general property of memory mapping tables  the paper shows that memory mapping tables can be used to implement the display registers used in providing architectural support for block-structured languages such as algol 60\. this allows full lexical level addressing to be implemented on so-called von-neuman machines.  the problems of fragmentation of the paged address space are explored, and machines with memory mapping schemes capable of supporting the proposals identified.  attention is drawn to the similarity between segmented and paged schemes, and it is suggested that the latter may be used to support the former.  karl reed