waashk/acm huggingface dataset:
a flexible vlsi core for an adaptable architecture  two major limitations concerning the design of cost-effective application- specific architectures are the recurrent costs of system-software development and hardware implementation, in particular vlsi implementation, for each architecture.  the scalable architecture experiment (scarce) aims to provide a framework for application-specific processor design. the framework allows scaling of functionality, implementation complexity, and performance. the scarce framework consists and will consist of: an architecture framework defining the constraints for the design of application- specific architectures; tools for synthesizing architectures from application or application-area; vlsi cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;  this paper concentrates on the micro- architecture framework of scarce and outlines the process of generating vlsi processors.  h. mulder p. stravers
a microarchitecture description language for retargeting firmware tools  archi is a microarchitecture description language designed to serve as the underlying language for a retargetable firmware development environment. archi provides a hierarchical, procedural description at the register transfer level of the target microarchitecture. this description can then be utilized by a meta-environment to generate an instantiation of the firmware development environment for a specific target microarchitecture.  archi has been successfully used to generate debugging simulators for the vertical perkin-elmer 3220, and the horizontal vax-11/780. it is shown that if a microarchitecture description language is powerful enough to retarget a debugging simulator then it can be used to retarget almost every tool in a firmware development meta-environment, and that archi accordingly satisfies its design objectives.  j. f. nixon s. r. schach r. i. winner
a new statistical model for gate array routing  a new statistical model for routing of gate arrays is described. the model takes into consideration the effect of gate utilization on wiring area requirement. model computed wiring area estimates suggest that it is better (in terms of area and wire length) to use higher utilization and a relatively large number of tracks than low utilization and smaller number of tracks. this is shown to be consistent with the results of two experiments.  abbas el gamal zahir a. syed
mos current mode logic for low power, low noise cordic computation in mixed- signal environments  in this work, mos current mode logic (mcml) is analyzed for application to low power, mixed signal environments. a small mcml cell library is developed and optimized for several different performance requirements. the cells are then applied to the generation of piplelined cordic structures and compared with equivalent cmos circuits. mcml cordics are designed which can operate from 125mhz to 310mhz with power consumption varying between 4.3mw and 18.6mw. these power results are up to 1.5 times less than cmos cordics with equivalent propagation delays. design was done in a 0.25 m standard cmos process from st microelectronics.  jason m. musicer jan rabaey
the yorktown simulation engine  the yorktown simulation engine (yse) is a high speed special purpose parallel processor designed and built at the i.b.m. thomas j. watson research center to simulate the logical operation of large digital networks. a full yse configuration simulates networks of up to 2,000,000 gates at a rate exceeding 3 billion gate computations per second, doing more simulation in just eight hours than an ibm 370/168 does in an entire year.  this paper reviews gate-level logic simulation and describes the architecture and hardware implementation of the yse. a companion paper by g. pfister and e. kronstadt discusses the yse software.  monty m. denneau
parameterized system design  continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre- designed processing components, but even of entire pre-designed architectures. to be used across a variety of applications, such architectures must be heavily parameterized, so they can adapt to those applications' differing constraints by trading off power, performance and size. we describe several parameterized system design issues, and provide results showing how a single architecture with easily configurable parameters can support a wide range of tradeoffs.  tony d. givargis frank vahid
automatic generation and characterization of cmos polycells  with increasing complexity and size of integrated circuits, computer aids for layout and simulation have begun to play an ever-increasing role. an approach to take advantage of these aids is the polycell design approach. however, thus far, manual procedures have been used in creating the interior of polycells. a layout style in which cmos technology lends itself to automation and design rule updatability has been found and is described here. a program has been implemented which takes as input a symbolic description of polycells and a set of design rules, and outputs a mask description of polycells. this mask description and a command file are then input to a layout characterization and verification software system to automatically generate inputs for a polycell layout system, a circuit simulator, and a timing simulator.  c. m. lee b. r. chawla s. just
algorithmic state machine implementation with hybrid microprocessing/microprogramming scheme  this paper proposes a hybrid microprocessing/microprogramming (hmm) scheme to implement the algorithmic state machines (asm). first, a behavior model of the hmm is defined. this model carries out any task by partitioning it into a microprocessing subtask which is executed by a microprocessor unit and a microprogramming subtask which is executed by a microprogrammed unit. the problems of constructing the microprogrammed unit of hmm are then considered, including the synthesis of control store sequencer, compaction of control store, and microcode generation. finally, an application example using the above method to design a universal floppy disk controller which can accept all kinds of encoding formats is provided.  y. h. kuo l. y. kung
a design verification methodology based on concurrent simulation and clock suppression  this paper outlines a methodology for design verification of very large networks based on concurrent simulation and clock suppression. concurrent simulation is expected to yield a 30:1 to 600:1 speed advantage over conventional (serial) simulation when roughly 5,000 "good machines" are simulated concurrently. this speed advantage increases with the number of concurrent machines.  clock suppression is an auxiliary technique to avoid simulation slowdowns if very large networks with very large clock fanouts must be simulated.  the methodology proposed here for design verification is "concurrent case simulation", i.e., the simultaneous simulation of distinct sets of input patterns. advantages of this method are (1) speed, (2) the fundamental ability to simulate cases concurrently, (3) to observe differences between cases in a more economic, simpler, and more natural style than with serial simulation, (4) to run many more cases than would be possible with serial simulation, (5) and the fact that running cases against each other establishes a powerful design verification philosophy.  ernst ulrich
an efficient retargetable microcode generator  this paper presents a microcode generator, which accepts a source program (algorithm) and a target description (microarchitecture) as input and generates microcode to implement the algorithm on the defined microarchitecture. the target description is similar to the outputs produced by datapath synthesis phase in hardware design packages. thus, it can be incorporated to synthesise a microprogrammed control.  the microcode generator is based on an algorithm which preserves retargetability without sacrificing on design time. this is achieved by implementing the generator in two phases: in the first phase, a set of 'feasible' register transfer operations (called base-set) is generated from the microarchitecture description. in the second phase, translation is carried out by simply searching and matching the source program statements with the base-set.  m. balakrishnan p. c p bhatt b. b. madan
symbolic synthesis of clock-gating logic for power optimization of synchronous controllers  recent results have shown that dynamic power management is effective in reducing the total power consumption of sequential circuits. in this paper, we propose a bottom-up approach for the automatic extraction and synthesis of dynamic power management circuitry starting from structural logic-level specifications. our techniques leverage the compact bdd-based representation of boolean and pseudo-boolean functions to detect idle conditions where the clock can be stopped without compromising functional correctness. moreover, symbolic techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. the results are encouraging, since power savings of up to 34% have been obtained on standard benchmark circuits.  l. benini g. de micheli e. macii m. poncino r. scarsi
a scalable front-end architecture for fast instruction delivery in the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. attaining these targets is a challenging task due to i-cache misses, branch mispredictions, and taken branches in the instruction stream. to further complicate matters, a vlsi interconnect scaling trend is materializing that further limits the performance of front-end designs in future generation process technologies.to counter these challenges, we present a fetch architecture that permits a faster cycle time than previous designs and scales better with future process technologies. our design, called the _fetch target buffer,_ is a multi-level fetch block-oriented predictor. we decouple the ftb from the instruction fetch and decode pipelines to afford it the fastest clock possible. through cycle-based simulation and circuit-level delay analysis, we find that our multi-level ftb design is capable of delivering instructions 25% faster than the best single-level btb-based pipeline configuration. moreover, we show that our design scales better to future process technologies than traditional single-level designs. glenn reinman todd austin brad calder
an educational tool for testing hierarchical multilevel caches in this work we present a simulator for a multilevel cache memory system on a monoprocessor environment. it has incorporated a full graphic interface operating on a pc- dos environment. at first, the simulator was conceived as a tool for applying it to teaching of cache memories. however, the potentiality of the developed system has proved its utility on program analysis and design strategies of memory systems. the above characteristics enable the simulator to be used for designing systems that run optimally a determinate kind of programs and improve the operating mode of a determinate architecture j. a. gomez pulido j. m. sanchez perez j. a. moreno zamora
consistent floorplanning with super hierarchical constraints  sequence-pair based floorplanning has been revealed its limit of usefulness in vlsi physical design. among reasons, the key issue is in its being non- hierarchical and indifferent to the preceding step of partitioning. this paper restructure the algorithm by the idea that the partition algorithm produces the constraint that is imposed on the sequence-pair data. the partition algorithm is the one based on the balanced-bipartition that works hierarchically. thus a new floorplan algorithm that is consistent with the hierarchical partition algorithm is constructed. this is enhanced to include other algorithms that are based on the binary search. here, a clock-tree synthesis by h-tree is shown to be consistent. experiments are given to show better achievements in length and wire-density.  shigetoshi nakatake yukiko kubo yoji kajitani
an sbus monitor board  during the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. it is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin bus connector and hence it is not practical to catch all the bus data required to ensure that such signals are in accordance with the bus specification. hence a given connector specific bus monitor board is a necessary instrument to attach to the system motherboard in order to monitor all bus activities. a connector specific bus monitor board provides an efficient resource with which to study the internal philosophy of system software, the software implementation process for different communication layers, and to provide debugging for hardware developers. the bus monitor board described here is designed to attach to a sun sbus and is similar to the transformable computer, which appeared recently, in that its architecture is reconfigurable via the use of a field programmable gate array (fpga). it can be programmed to customise it to various users' specific needs. it differs from the transformable computer in that although it can be programmed to function as a coprocessor its primary function is dedicated sbus monitoring. it is less costly than a transformable computer.  in this article we describe the prototype of an sbus monitor's architecture and functions, and present the experimental results obtained from a sun sparc work station and an aurora sbox expansion chassis, which demonstrate its ability to capture and display data communication and bus activity. since this prototype board is programmable, it has the potential to provide many special purpose sbus monitors, but also function as a programmable coprocessor.  h. a. xie k. e. forward k. m. adams d. leask
a large scale cellular array processor: aap-1  a simd cellular array processor called the adaptive array processor (aap-1) has been developed. its 256 x 256 array of bit-organized processing elements (pes) is composed of 1024 custom nmos lsis and occupies the small volume of 0.33m3. extensive parallelism offers ultra- high throughout for various types of two-dimensional data processing, together with data-dependent operation capability through the use of control registers in each pe. the processing speed has experimentally exceeded that of a 1 mips sequential computer by a factor of approximately 100 for lsi design automation methods such as logic simulation, wire routing and device placement.  toshio kondo tayoshi nakashima toshio tsuchiya yoshi sugiyama tsuneta sudo
a technology-adaptive allocation of functional units and connections  a new algorithm of allocating functional units and connections in the data path synthesis has been developed. the algorithm determines the types and numbers of both functional units and connections simultaneously based on their cost (i.e., area) obtained from the input technology data. the algorithm performs trade-off between the functional units and connections to produce data paths with minimal cost. the algorithm is adaptive to different technologies: if the cost of a functional unit changes or if a new functional unit becomes available, the algorithm produces a new data path optimized in the new environment. the algorithm has o(n3) timing complexity in the worst case, where n is the number of operations in the input problem. experiments show that costs of data paths constructed by our algorithm are smaller than or as much as those by other published approaches.  n.-s. woo h. shin
modeling concepts for vlsi cad objects  vlsi cad applications deal with design objects that have an interface description and an implementation description. versions of design objects have a common interface but differ in their implementations. a molecular object is a modeling construct which enables a database entity to be represented by two sets of heterogeneous records, one set describes the object's interface and the other describes its implementation. thus a reasonable starting point for modeling design objects is to begin with the concept of molecular objects.  in this paper, we identify modeling concepts that are fundamental to capturing the semantics of vlsi cad design objects and versions in terms of molecular objects. a provisional set of user operations on design objects, consistent with these modeling concepts, is also defined. the modeling framework that we present has been found useful for investigating physical storage techniques and change notification problems in version control.  d. s. batory won kim
using network interface support to avoid asynchronous protocol processing in shared virtual memory systems the performance of page-based software shared virtual memory (svm) is still far from that achieved on hardware-coherent distributed shared memory (dsm) systems. the interrupt cost for asynchronous protocol processing has been found to be a key source of performance loss and complexity.this paper shows that by providing simple and general support for asynchronous message handling in a commodity network interface (ni), and by altering svm protocols appropriately, protocol activity can be decoupled from asynchronous message handling and the need for interrupts or polling can be eliminated. the ni mechanisms needed are generic, not svm-dependent. they also require neither visibility into the node memory system nor code instrumentation to identify memory operations. we prototype the mechanisms and such a _synchronous home-based lrc_ protocol, called genima (general-purpose network interface support in a shared memory abstraction), on a cluster of smps with a programmable ni, though the mechanisms are simple and do not require programmability.we find that the performance improvements are substantial, bringing performance on a small-scale smp cluster much closer to that of hardware-coherent shared memory for many applications, and we show the value of each of the mechanisms in different applications. application performance improves by about 37% on average for reasonably well performing applications, even on our relatively slow programmable ni, and more for others. we discuss the key remaining bottlenecks at the protocol level and use a firmware performance monitor in the ni to understand the interactions with and the implications for the communication layer. angelos bilas cheng liao jaswinder pal singh
measurements of a vlsi design  this paper presents data about three facets of a recently-completed vlsi design containing 45000 transistors. the first set of data describes the mask- level features of the circuit, from which it is seen that almost all features have at least one small dimension. the second set of data analyzes the hierarchical cell structure used by the designers to specify the circuit. the measurements show that composite cells have a different structure from primitive cells, and that, outside of arrays, cells are rarely re-used. the third set of data concerns the usage of an interactive layout program during the circuit's design. in spite of the circuit's size, the most frequently invoked commands were all simple.  john k. ousterhout david m. ungar
access region locality for high-bandwidth processor memory system design  this paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. unlike the traditional temporal and spatial data locality that focuses on individual memory locations and how accesses to the locations are inter-related, the access region locality concerns with each static memory instruction and its range of access locations at run time. we consider program's data, heap, and stack regions in this paper. our experimental study using a set of spec95 benchmark programs shows that most memory reference instructions access a single region at run time. also shown is that it is possible to accurately predict the access region of a memory instruction at run time by scrutinizing the addressing mode of the instruction and the past access region history of it. a simple run-time access region predictor is developed that is similar to a branch predictor in structure. we describe and evaluate a superscalar processor with two distinct sets of memory pipelines, driven by the access region predictor. experimentalresultsindicate that the proposed mechanism is very effective in providing high memory bandwidth to the processor, resulting in comparable or better performance than a conventional memory design with a heavily multi- ported data cache that can lead to much higher hardware complexity.  sangyeun cho pen-chung yew gyungho lee
register estimation in unscheduled dataflow graphs  a method for register number estimation in unscheduled or partially scheduled dataflow graphs is presented. the strategy consists of studying the probability that an edge between two nodes crosses the boundary between two control steps, and its is based on a model that associates probabilities with the different scheduling alternatives of each node. these probabilities are computed by means of an analytic method that takes into account the distribution of operations in the dataflow graph and the hardware modules available in the library. the results highlight that the estimation method is very accurate becaused the error between the estimated value and the real value is always within a narrow margin.  r. moreno r. hermida m. fernández
random pattern testable logic synthesis  previous procedures for synthesis of testable logic guarantee that all faults in the synthesized circuits are detectable. however, the detectability of many faults in these circuits can be very low leading to poor random pattern testability. a new procedure to perform logic synthesis that synthesizes random pattern testable multilevel circuits is proposed. experimental results show that the circuits synthesized by the proposed procedure tstfx are significantly more random pattern testable and smaller than those synthesized using its counterpart fast_extract (fx) in sis. the proposed synthesis procedure design circuits that require only simple random pattern generators in built-in self- test, thereby obviating the need for complex bist circuitry.  chen- huan chiang sandeep k. gupta
a novel approach to accurate timing verification using rtl descriptions  timing verification is a critical part of vlsi circuit design. a new approach to timing verification using register transfer level (rtl) descriptions is presented, which eliminates false paths that occur due to (i) redundancy, (ii) reconvergent fanout or (iii) control signal constraints, and generates a test for the critical paths. high level instructions of the circuit are used to test for any timing violations. an algorithm to identify a minimal set of instructions that tests the circuit for all timing errors in valid paths is proposed. results are presented based on an implementation of the algorithm in lisp programming language on a ti explorer machine.  k. roy j. a. abraham