waashk/acm huggingface dataset:
hci and the 3c convergence we attempt to explore the implications of the "3c convergence" (convergence of content, computers and communications) on the hci research agenda. the interaction between humans and the 3c's is becoming a daily staple as we continue to witness powerful computers unite in a networked environment where wireline and wireless communications enjoy broadening bandwidths that permit the transmission of multimedia content. we draw illustrative examples from the hong kong environment related to the 3c convergence, and we present issues which we believe to be important for the research and development of a universal, useful and usable human-computer interface. helen m. meng
the butterfly satellite imp for the wideband packet satellite network  multiprocessor computer systems have proven effective as high performance switching nodes in packet switched data communications networks. they are well suited to performing the required queuing, routing, and scheduling tasks, and can scale upward to provide higher system throughput when combined with software that exploits the parallelism provided by the hardware. this paper describes the packet switch used in the darpa wideband packet satellite network and the butterfly multiprocessor on which it is based.  w edmond s bumenthal a echenique s storch t calderwood
on refuting the creation theory of computer architecture  there is an enormous body of software implemented on the common cpu architectures of today, such as intel 8080, dec pdp-11, and ibm system/370. for computer vendors in a profit-seeking environment, future products must not only support this existing software, but also exploit hardware and software technologies that are being, and will be, developed. the computer architect must balance the changes made to support new software with the requirement for cost- effective execution of old software. this problem is independent of the execution speed of the processor and the size of the system of which it is a part.  the process of striking a balance between advancement and compatibility will be presented. strengths and weaknesses of various types of solutions will be described using examples from commercial vendors. reasons why certain well- known concepts in computer architecture have not been included in the products of commercial vendors will be discussed. the impact of management-level personnel on changes in computer architecture will also be explored. future computer architectures must be engineered to meet the needs and concepts of those who use and control computers. therefore, the process of its development within the industry must necessarily occur in orderly and constrained steps, rather than random leaps.  kenneth e. mackenzie
analysis of cray-1s architecture  an analysis of the cray-1s architecture based on dataflow graphs is presented. the approach consists of representing the components of a cray-1s system as the nodes of a dataflow graph and the interconnections between the components as the arcs of the dataflow graph. the elapsed time and the resources used in a component are represented by the attributes of the node corresponding to the component. the resulting dataflow graph model is simulated to obtain timing statistics using as input a control stream that represents the instruction and data stream of the real computer system.  the cray-1s architecture is analyzed by conducting several experiments with the model. it is observed that the architecture is a well balanced one and performance improvements are hard to achieve without major changes. significant improvement in performance is shown when parallel instruction issue is allowed with multiple cip/lips in the architecture.  vason p. srini jorge f. asenjo
a template matching algorithm using optically-connected 3-d vlsi architecture  three-dimensional vlsi (in short, 3-d vlsi) is a new device technology that is expected to realize high performance systems. in this paper, we propose an image processing architecture based on 3-d vlsi consisting of optically- connected layers. since the optical inter-layer connection seems to have some of useful functions due to isotropic radiation of the light, we algebraicly formulate them as the picture processing operators. moreover, we show that the operators are available for applications such as template matching. the availability of a proposed template matching algorithm is verified by simulation.  s. fujita r. aibara m. yamashita t. ae
organization of invalidation reports for energy-efficient cache invalidation in mobile environments  in a wireless environment, mobile clients often cache frequently accessed data to reduce contention on the limited wireless bandwidth. however, it is difficult for clients to ascertain the validity of their cache content because of their frequent disconnection. one promising cache invalidation approach is the bit- sequences scheme that organizes invalidation reports as a set of binary bit sequences with an associated set of timestamps. the report is periodically broadcast by the server to clients listening to the communication channel. while the approach has been shown to be effective, it is not energy efficient as clients are expected to examine the entire invalidation report. in this paper, we examine the bit-sequences method and study different organizations of the invalidation report to facilitate clients to selectively tune to the portion of the report that are of interest to them. this allows the clients to minimize the power consumption when invalidating their cache content. we conducted extensive studies based on a simulation model. our study shows that, compared to the bit-sequences approach, the proposed schemes are not only equally effectively in salvaging the cache content but are more efficient in energy utilization.  kian-lee tan
large-grain pipelining on hypercube multiprocessors  a new paradigm, called large-grain pipelining, for developing efficient parallel algorithms on distributed-memory multiprocessors, e.g., hypercube machines, is introduced. large-grain pipelining attempts to maximize the degree of overlapping and minimize the effect of communication overhead in a multiprocessor system through macro-pipelining between the nodes. algorithms developed through large-grain pipelining to perform matrix multiplication are presented. to model the pipelined computations, an analytic model is introduced, which takes into account both underlying architecture and algorithm behavior. through the analytic model, important design parameters, such as data partition sizes, can be determined. experiments were conducted on a 64-node ncube multiprocessor. the measured results match closely with the analyzed results, which establishes the analytic model as an integral part of algorithm design. comparison with an algorithm which does not use large-grain pipelining also shows that large-grain pipelining is an efficient scheme for achieving a greater parallelism.  c-t. king l. m. ni
survivable load sharing protocols: a simulation study the development of robust, survivable wireless access networks requires that the performance of network architectures and protocols be studied under normal as well as faulty conditions where consideration is given to faults occurring within the network as well as within the physical environment. user location, mobility, and usage patterns and the quality of the received radio signal are impacted by terrain, man-made structures, population distribution, and the existing transportation system. the work presented herein has two thrusts. one, we propose the use of overlapping coverage areas and dynamic load balancing as a means to increase network survivability by providing mobiles with multiple access points to the fixed infrastructure. two, we describe our simulation approach to survivability analysis which combines empirical spatial information, network models, and fault models for more realistic analysis of real service areas. we use our simulation approach to compare the survivability of our load balancing protocols to a reference scheme within two diverse geographic regions. we view survivability as a cost-performance tradeoff using handover activity as a cost metric and blocking probabilities as performance metrics. our results illustrate this tradeoff for the protocols studied and demonstrate the extent to which the physical environment and faults therein affect the conclusions that are drawn. t. a. dahlberg j. jung
fast temporary storage for serial and parallel execution  there is an apparent conflict between the hardware requirements for fast parallel execution and the hardware requirements for fast serial execution. for example, fast vector execution is achieved by maintaining high execution concurrency over extended periods of time. with many operations executing in parallel, the time to carry out individual operations is much less important than the average execution concurrency.  fast serial execution, on the other hand, requires rapid execution of relatively few operations at a time; hardware concurrency can be sacrificed in favor of short execution times. fewer registers and memory locations are required, but they must have shorter access times than for parallel execution.  we show how to integrate these seemingly conflicting requirements into a single computer, using asymmetric distribution of hardware, and sometimes using software to allocate variables to appropriate parts of the storage hierarchy.  j. swensen y. patt
towards junking the pbx: deploying ip telephony  we describe the architecture and implementation of our internet teleph ony test-bed intended to replace the departmental pbx (telephone switch). it interworks with the traditional telephone networks via a pstn/ip gateway. it also serves as a corporate or campus infrastructure for existing and future services like web, email, video and streaming media. initially intended for a few users, it will eventually replace the plain old telephones from our offices, due to the cost benefit and new services it offers. we also discuss common inter-operability problems between the pbx and the gateway.  wenyu jiang jonathan lennox henning schulzrinne kundan singh
deriving a protocol converter: a top-down method  a protocol converter mediates the communication between implementations of different protocols, enabling them to achieve some form of useful interaction. the problem of deriving a protocol converter from specifications of the protocols and a desired service can be viewed as the problem of finding the "quotient" of two specifications. we define a class of finite-state specifications and present an algorithm for solving "quotient" problems for the class. the algorithm is applied to an example conversion problem. we also discuss its application in the context of layered network architectures.  k. l. calvert s. s. lam
a hierarchical network approach to project control systems (abstract only)  in pert, cpm, and similar project control systems each task of the project is represented as an art of a network diagram. in the approach presented here each task may be further subdivided into additional tasks, the process continuable indefinitely until reaching "elemental" tasks. a task file is presented with an imbedded data structure which includes both the precedence and hierarchical relationships. this approach may be useful in the display of such a system on a fixed area such as that of a display terminal.  iza goroff
evaluation of retransmission strategies in a local area network environment  we present an evaluation of retransmission strategies over local area networks. expressions are derived for the expectation and the variance of the transmission time of the go-back-n and the selective repeat protocols in the presence of errors. these are compared to the expressions for blast with full retransmission on error (bfre) derived by zwaenepoel [zwa 85]. we conclude that go-back-n performs almost as well as selective repeat and is very much simpler to implement while bfre is stable only for a limited range of messages sizes and error rates. we also present a variant of bfre which optimally checkpoints the transmission of a large message. this is shown to overcome the instability of ordinary bfre. it has a simple state machine and seems to take full advantage of the low error rates of local area networks. we further investigate go-back-n by generalizing the analysis to an upper layer transport protocol, which is likely to encounter among other things, variable delays due to protocol overhead, multiple connections, process switches and operating system scheduling priorities.  a. mukherjee l. h. landweber j. c. strikwerda
estimating the service time of web clients using server logs  this article proposes and evaluates measures for estimating the service time of a web client using server logs, only from the server side without introducing traffic into the network. the http protocol is described as well as the different interactions between the web server, the communication components, and the web client application. the first measure is based on the time it takes for the web server application to deliver an object to its operating system, keeping in mind the buffer effect of the server network. the second measure also considers the inter-arrival times to the server application of the get requests for the objects that are part of a web page. we propose formulas, validated experimentally, that relate the proposed measurements in the server with the different components that take part in a web transaction and the service time experienced by clients. we have carried out several experiments to evaluate the validity of the proposed measurements and the best measure estimates the service time of the client with an error below 20% for 90% of the requests. we observed a cyclic component in the measurements of the server that can simplify the estimation of future values. for this reason, the proposed measures may be used to know what is the service time the client perceives in each visit to a server. it can also be used by content distribution networks to choose between several replica located in different places in the internet.  oscar ardaiz felix freig leandro navarro
improving the start-up behavior of a congestion control scheme for tcp based on experiments conducted in a network simulator and over real networks, this paper proposes changes to the congestion control scheme in current tcp implementations to improve its behavior during the start-up period of a tcp connection.the scheme, which includes slow-start, fast retransmit, and fast recovery algorithms, uses acknowledgments from a receiver to dynamically calculate reasonable operating values for a sender's tcp parameters governing when and how much a sender can pump into the network. during the start-up period, because a tcp sender starts with default parameters, it often ends up sending too many packets and too fast, leading to multiple losses of packets from the same window. this paper shows that recovery from losses during this start-up period is often unnecessarily time-consuming.in particular, using the current fast retransmit algorithm, when multiple packets in the same window are lost, only one of the packet losses may be recovered by each fast retransmit; the rest are often recovered by slow-start after a usually lengthy retransmission timeout. thus, this paper proposes changes to the fast retransmit algorithm so that it can quickly recover from multiple packet losses without waiting unnecessarily for the timeout. these changes, tested in the simulator and on the real networks, show significant performance improvements, especially for short tcp transfers. the paper also proposes other changes to help minimize the number of packets lost during the start-up period. janey c. hoe
comparative analysis of wireless atm channel access protocols supporting multimedia traffic  extension of multimedia services and applications offered by atm networks to wireless and mobile users has captured a lot of recent research attention. research prototyping of wireless atm networks is currently underway at many leading research and academic institutions. various architectures have been proposed depending on the intended application domain. successful implementation of wireless connectivity to atm services is significantly dependent on the medium access control (mac) protocol, which has to provide support for multimedia traffic and for quality-of-service (qos) guarantees. the objective of this paper is to investigate the comparative performance of a set of access protocols, proposed earlier in the literature, with more realistic source traffic models. data traffic is modeled with self- similar (fractal) behavior. voice traffic is modeled by a slow speech activity detector (sad). video traffic is modeled as a h.261 video teleconference, where the number of atm cells per video frame is described by a gamma distribution and a first-order discrete autoregressive process model. a comparison of the protocols based on simulation data is presented. the goal of the paper is to identify appropriate techniques for effectively and efficiently supporting multimedia traffic and qos. simulation results show that boundaries between different types of services are necessary for multimedia traffic. reservation for certain traffic type especially video can significantly improve its quality. reducing the number of collisions is an important issue for wireless networks since contentions lead not only to potentially high delay but also result in high power consumption.  jyh-cheng chen krishna m. sivalingam raj acharya
a distributed overload control algorithm for delay-bounded call setup as communication networks provide newer services, signaling is becoming more and more compute intensive compared to present day networks. it is known that under overload conditions, the call throughput (goodput) and the network revenue drops to zero even when transport resources are available. a distributed overload control algorithm for delay-bounded call setup is proposed in this paper. the end-to-end delay bound is budgeted among the switching nodes involved in call setup, and these nodes apply a local overload control with a deterministic delay threshold and drop call requests experiencing higher delays. this algorithm does not depend on feedback on network conditions and makes use of only parameters that can be instrumented locally by the switching node. using an _m/m/_1 queueing model with first-in- first-out (fifo) service discipline at a switching node, two optimized control schemes are considered for local overload control and compared their performance through analysis: one with arrival rate limit and the other with buffer size limit. though both the schemes minimize the unproductive call processing at heavy load, the latter is found to yield higher call throughput and lower average call setup delays compared to the former. also, the buffer size required for the scheme with buffer size limit is typically small and call throughput close to the server capacity can be achieved during overload. the performance of the distributed overload control algorithm in a network is evaluated through simulation experiments, using the scheme with buffer size limit for the local overload control. it shows that the average end-to-end delay could be much less than the end-to-end delay bound, providing room for overprovisioning of the delay bounds. the tradeoff between the number of nodes, call throughput, and average end-to-end delay needs to be considered while deciding the route budgeting the end-to-end delay bound among different nodes along the route. these performance results are expected to serve as lower bounds to more sophisticated local call rejection mechanisms such as push-out or time-out along with a last-in-first-out (lifo) service discipline. r. radhakrishna pillai
dummynet: a simple approach to the evaluation of network protocols network protocols are usually tested in operational networks or in simulated environments. with the former approach it is not easy to set and control the various operational parameters such as bandwidth, delays, queue sizes. simulators are easier to control, but they are often only an approximate model of the desired setting, especially for what regards the various traffic generators (both producers and consumers) and their interaction with the protocol itself.in this paper we show how a simple, yet flexible and accurate network simulator - **dummynet** \\- can be built with minimal modifications to an existing protocol stack, allowing experiments to be run on a standalone system. **dummynet** works by intercepting communications of the protocol layer under test and simulating the effects of finite queues, bandwidth limitations and communication delays. it runs in a fully operational system, hence allowing the use of real traffic generators and protocol implementations, while solving the problem of simulating unusual environments. with our tool, doing experiments with network protocols is as simple as running the desired set of applications on a workstation.a freebsd implementation of **dummynet**, targeted to tcp, is available from the author. this implementation is highly portable and compatible with other bsd-derived systems, and takes less than 300 lines of kernel code. luigi rizzo
performance analysis of md5 md5 is an authentication algorithm proposed as the required implementation of the authentication option in ipv6. this paper presents an analysis of the speed at which md5 can be implemented in software and hardware, and discusses whether its use interferes with high bandwidth networking. the analysis indicates that md5 software currently runs at 85 mbps on a 190 mhz risc architecture, a rate that cannot be improved more than 20-40%. because md5 processes the entire body of a packet, this data rate is insufficient for current high bandwidth networks, including hippi and fiberchannel. further analysis indicates that a 300 mhz custom vlsi cmos hardware implementation of md5 may run as fast as 256 mbps. the hardware rate cannot support existing ipv4 data rates on high bandwidth links (800 mbps hippi). the use of md5 as the default required authentication algorithm in ipv6 should therefore be reconsidered, and an alternative should be proposed. this paper includes a brief description of the properties of such an alternative, including a sample alternate hash algorithm. joseph d. touch
diva: a reliable substrate for deep submicron microarchitecture design  building a high-performance microprocessor presents many reliability challenges. designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. to further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference.  in this paper, we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. the approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. the functional checker verifies the correctness of the core processor's computation, only permitting correct results to commit. overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit.  we detail the diva checker architecture, a design optimized for simplicity and low cost. using detailed timing simulation, we show that even resource-frugal diva checkers have little impact on core processor performance. to make the case for reduced verification costs, we argue that the diva checker should lend itself to functional and electrical verification better than a complex core processor. finally, future applications that leverage dynamic verification to increase processor performance and availability are suggested.  todd m. austin