waashk/acm huggingface dataset:
a new approach to the design and analysis of peer-to-peer mobile networks  this paper introduces a new model and methodological approach for dealing with the probabilistic nature of mobile networks based on the theory of random graphs. probabilistic dependence between the random links prevents the direct application of the theory of random graphs to communication networks. the new model, termed random network model, generalizes conventional random graph models to allow for the inclusion of link dependencies in a mobile network. the new random network model is obtained through the superposition of kolmogorov complexity and random graph theory, making in this way random graph theory applicable to mobile networks. to the best of the authors' knowledge, it is the first application of random graphs to the field of mobile networks and a first general modeling framework for dealing with ad- hoc network mobility. the application of this methodology makes it possible to derive results with proven properties. the theory is demonstrated by addressing the issue of the establishment of a connected virtual backbone among mobile clusterheads in a peer-to-peer mobile wireless network. using the random network model, we show that it is possible to construct a randomized distributed algorithm which provides connectivity with high probability, requiring exponentially fewer connections (peer-to-peer logical links) per clusterhead than the number of connections needed for an algorithm with a worst case deterministic guarantee.  imrich chlamtac andrás faragó
tetra radio performance evaluated via the software package tetrasim  tetra (terrestrial trunked radio) is a digital mobile radio standard for voice and data transmission. it aims at satisfying the growing request of applications and facilities coming from professional users and emergency services. the system has been standardized by etsi (european telecommunications standards institute) and is provided with an european harmonized frequency band. the first tetra networks appeared on the market in 1997\. this paper reports tetra radio performance evaluated via a simulation software package, named tetrasim, entirely developed at cselt according to tetra specifications. the simulation results have been obtained for some of the traffic and control channels specified by the standard, in terms of ber (bit error rate) and mer (message erasure rate). as far as the simulated receiver scheme is concerned, the characteristics of the equivalent low-pass filters and the adopted synchronization technique are reported. the simulated demodulator uses a differential detection scheme with soft decision outputs in the case of coded channels. performance analyses and results comparison are provided by taking into account the effects of signal-to-noise ratio, co- channel interference, adjacent channel interference, propagation models defined in the standard and mobile unit speed. the simulation results reported in this work have been included in the etr (etsi technical report) "tetra designers" guide part 2: radio and traffic performance".  armando annunziato davide sorbara
an application developer's perspective on reliable multicast for distributed interactive media  in this paper we investigate which characteristics reliable multicast services should have in order to be appropriate for use by distributed interactive media applications such as shared whiteboards, networked computer games, or distributed virtual environments. we take a close look at the communication requirements of these applications and at existing approaches to realize reliable multicast. based on this information we deduce which reliable multicast transport protocols are appropriate for the different aspects of distributed interactive media. furthermore we discuss how the application program interface of a reliable multicast service should be designed in order to support the development of applications for distributed interactive media.  martin mauve volker hilt
an architecture for packet-striping protocols  link-striping algorithms are often used to overcome transmission bottlenecks in computer networks. traditional striping algorithms suffer from two major disadvantages. they provide inadequate load sharing in the presence of variable-length packets, and may result in non-fifo delivery of data. we describe a new family of link-striping algorithms that solves both problems. our scheme applies to any layer that can provide multiple fifo channels. we deal with variable-sized packets by showing how fair-queuing algorithms can be transformed into load- sharing algorithms. our transformation results in practical load-sharing protocols, and shows a theoretical connection between two seemingly different problems. the same transformation can be applied to obtain load-sharing protocols for links with different capacities. we deal with the fifo requirement for two separate cases. if a sequence number can be added to each packet, we show how to speed up packet processing by letting the receiver simulate the sender algorithm. if no header can be added, we show how to provide quasi fifo delivery. quasi fifo is fifo except during occasional periods of loss of synchronization. we argue that quasi fifo is adequate for most applications. we also describe a simple technique for speedy restoration of synchronization in the event of loss. we develop an architectural framework for transparently embedding our protocol at the network level by striping ip packets across multiple physical interfaces. the resulting stripe protocol has been implemented within the netbsd kernel. our measurements and simulations show that the protocol offers scalable throughput even when striping is done over dissimilar links, and that the protocol synchronized quickly after packet loss. measurements show performance improvements over conventional round-robin striping schemes and striping schemes that do not resequence packets. some aspects of our solution have been implemented in cisco's router operating system (ios 11.3) in the context of multilink ppp striping.  adiseshu hari george varghese guru parulkar
a new method for topological design in large, traffic laden packet switched networks  the an/1 network architecture employs compact lans as integrated switching nodes. the multibussed nodal architecture imposes a natural hierarchy to the network interconnection problem. a nodal interconnection method is introduced as a generalization of hierarchical topology design techniques. based on traffic and distance, a flat nodal topology is decomposed into several level, overlapped subnetworks. each subordinate subnetwork communicates with its ordinate subnetwork via two formal gates. the traffic matrix for each subnetwork can be obtained. linear programming techniques are used to determine bandwidth requirements. perturbation procedures are applied to determine the appropriate groupings of lans into subnetworks and the appropriate hierarchy. a flat topology may be returned if it is optimal.  kim-joan chen jerrold f. stach tsong-ho wu
emma-an industrial experience on large multiprocessing architectures  emma (1) is a multiprocessor system designed and built by elsag of genoa, italy, to solve problems of pattern recognition arising in automatic mail sorting.  the resulting architecture is modular, organizable around several levels, and offers a theoretically unlimited possibility of increasing the processor power.  emma runs under a simple distributed operating system, supplying process communication, synchronization primitives and some diagnostic functions that complement analysis and reconfiguration modules residing in the supervisor.  luigi stringa
a fault-tolerant implementation protocol for replicated database systems on bus local area networks  this paper proposes a new protocol for implementing a replicated database system on a bus local network. using the broadcast capability of the bus local network, our protocol handles the database request efficiently with a small number of messages. unlike existing schemes, our implementation protocol provides high resiliency as well as the fast response time. the system continues to service the requests as long as there is at least one site available, and, even when there is no site failure, the overall performance is better than the primary copy approach which is known to be most efficient. simulation results are provided to compare the performance.  junguk l. kim heon yeom
simultaneous multithreading: maximizing on-chip parallelism this paper examines _simultaneous multithreading,_ a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a single cycle. we present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple- issue multiprocessing architectures. our results show that both (single- threaded) superscalar and fine-grain multithreaded architectures are limited their ability to utilize the resources of a wide- issue processor. simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multithreading. we evaluate several cache configurations made possible by this type of organization and evaluate tradeoffs between them. we also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding conventional multiprocessors with similar execution resources.while simultaneous multithreading has excellent potential to increase processor utilization, it can add substantial complexity to the design. we examine many of these complexities and evaluate alternative organizations in the design space. dean m. tullsen susan j. eggers henry m. levy
analysis of a hybrid cutoff priority scheme for multiple classes of traffic in multimedia wireless networks  in this paper, we propose and analyze the performance of a new handoff scheme called hybrid cutoff priority scheme for wireless networks carrying multimedia traffic. the unique characteristics of this scheme include support for n classes of traffic, each may have different qos requirements in terms of number of channels needed, holding time of the connection and cutoff priority. the proposed scheme can handle finite buffering for both new calls and handoffs. futhermore, we take into consideration the departure of new calls due to caller impatience and the dropping of queued handoff calls due to unavailability of channels during the handoff period. the performance indices adopted in the evaluation using the stochastic petri net (spn) model include new call and handoff blocking probabilities, call forced termination probability, and channel utilization for each type of traffic. impact on the performance measures by various system parameters such as queue length, traffic input and qos of different traffic has also been studied.  bo li samuel t. chanson chuang lin
a national trace collection and distribution resource computer systems are modeled before construction to minimize errors and performance bottlenecks. a common modeling approach is to build software models of comptuer system components, and use realistic _trace_ data as input. this methodology is commonly referred to as trace-driven simulation. trace-driven simulation can be very accurate if both the system model and input trace data represent the system under test. the accuracy of the model is typically under the control of the researcher, but so far little or no trace data has been available that accurately represents current or future workloads. to address this issue, we describe the brigham young univ. address collection hardware (bach) and introduce our national trace distribution center and trace collection facility (http://traces.byu.edu). we also illustrate the types of traces we collect and make available to others. niki c. thornock j. kelly flanagan
mu6-g. a new design to achieve mainframe performance from a mini-sized computer  mu6-g is a high performance machine useful for general or scientific applications. its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. innovative features include the unique organisation of the virtual memory mapping hardware and the use of a combined operand and instruction buffer-store, accessed using virtual addresses. fault diagnosis is aided by the inclusion of a microprocessor based diagnostic controller which has read/write access to all bistable devices in the machine and has control of the system clock. the paper includes a description of the various functional units and gives estimates of expected performance.  d. b.g. edwards a. e. knowles j. v. woods
hardware implementation of communication protocols: a formal approach  this paper presents a formal method that permits the development of verified specifications and implementation of communication protocols. a non- executable high level language is introduced for specification purposes. this language permits the concise and unambiguous specification of those characteristics which are normally needed to be modeled in the design of protocols. a simple algorithm for verifying the protocol specifications is indicated. then it is shown how the verified specifications can be transformed into another descriptive model, a processing machine which is more directly related to hardware implementation. the processing machine description resulting from this model simplifies the last stage of protocol design, that of the realization.  miguel garcía hoffmann
specification and verification of collusion-free broadcast networks  for high-speed local area networks that offer integrated services for data, voice, and image traffic, a class of demand-assigned multiple-access protocols have been presented in the literature. these protocols exploit the directionality of signal propagation and enforce time constraints to achieve collision-freedom. a correct implementation of such a protocol requires a careful analysis of time-dependent interactions of event occurrences using a formal method. to date, most protocol verification methods are intended for the analysis of asynchronous communication over point-to-point channels.  we present a model for broadcast bus networks. the novel features of our model include the ability to specify broadcast channels and the specification of real-time behavior. the broadcast characteristics of cables or buses are captured by some simple axioms. real time is modeled as a discrete quantity using clocks and time variables. real-time properties are specified by safety assertions. to illustrate our model and analysis method, we present a specification of the expressnet protocol. we found that to achieve collision- freedom, a small modification to the original expressnet protocol is needed.  p. jain s. s. lam
software implementation strategies for power-conscious systems  a variety of systems with possibly embedded computing power, such as small portable robots, hand-held computers, and automated vehicles, have power supply constraints. their batteries generally last only for a few hours before being replaced or recharged. it is important that all design efforts are made to conserve power in those systems. energy consumption in a system can be reduced using a number of techniques, such as low-power electronics, architecture-level power reduction, compiler techniques, to name just a few. however, energy conservation at the application software-level has not yet been explored. in this paper, we show the impact of various software implementation techniques on energy saving. based on the observation that different instructions of a processor cost different amount of energy, we propose three energy saving strategies, namely (i) assigning live variables to registers, (ii) avoiding repetitive address computations, and (iii) minimizing memory accesses. we also study how a variety of algorithm design and implementation techniques affect energy consumption. in particular, we focus on the following aspects: (i) recursive versus iterative (with stacks and without stacks), (ii) different representations of the same algorithm, (iii) different algorithms - with identical asymptotic complexity - for the same problem, and (iv) different input representations. we demonstrate the energy saving capabilities of these approaches by studying a variety of applications related to power-conscious systems, such as sorting, pattern matching, matrix operations, depth-first search, and dynamic programming. from our experimental results, we conclude that by suitably choosing an algorithm for a problem and applying the energy saving techniques, energy savings in excess of 60% can be achieved.  kshirasagar naik david s. l. wei
a stochastic model of tcp/ip with stationary random losses  we present a technique for identifying repetitive information transfers and use it to analyze the redundancy of network traffic. our insight is that dynamic content, streaming media and other traffic that is not caught by today's web caches is nonetheless likely to derive from similar information. we have therefore adapted similarity detection techniques to the problem of designing a system to eliminate redundant transfers. we identify repeated byte ranges between packets to avoid retransmitting the redundant data.  eitan altman konstantin avrachenkov chadi barakat
efficient wire formats for high performance computing  high performance computing is being increasingly utilized in non-traditional circumstances where it must interoperate with otherapplications. for example, online visualization is being used to monitor the progress of applications, and real-world sensors are used as inputs to simulations. whenever these situations arise, there is a question of what communications infrastructure should be used to link the different components. traditional hpc-style communications systems such as mpi offer relatively high performance, but are poorly suited for developing these less tightly-coupled cooperating applications. object-based systems and meta-data formats like xml offer substantial plug-and-play flexibility, but with substantially lower performance. we observe that the flexibility and baseline performance of all these systems is strongly determined by their "wire format," or how they represent data for transmission in a heterogeneous environment. we examine the performance implications of different wire formats and present an alternative with significant advantages in terms of both performance and flexibility.  fabian e. bustamante greg eisenhauer karsten schwan patrick widener
application performance improvement on the ipsc/2 computer  the performance of concurrent computers depends fundamentally on the capabilities of the individual processing nodes and the characteristics of the interprocessor communication system. the intel ipsc®/2 is significantly better in both categories than the original ipsc (ipsc/1). this paper will briefly compare the hardware of the two machines and then discuss the actual measured performance improvement of several kernels of application codes. the improvements vary from a factor of two and a half to more than a factor of 30.  s. arshi r. asbury j. brandenburg d. scott
architecture of a massively parallel processor  the massively parallel processor (mpp) system is designed to process satellite imagery at high rates. a large number (16,384) of processing elements (pe's) are configured in a square array. for optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. on 8-bit integer data, addition can occur at 6553 million operations per second (mops) and multiplication at 1861 mops. on 32-bit floating-point data, addition can occur at 430 mops and multiplication at 216 mops.  kenneth e. batcher
a retrospective on the dorado, a high-performance personal computer  in late 1975, members of the xerox palo alto research center embarked on the specification of a high-performance successor to the alto personal minicomputer, in use since 1973. after four years, the resulting machine, called the dorado, was in use within the research community at parc. this paper begins with an overview of the design goals, architecture, and implementation of the dorado and then provides a retrospective view and critique of the dorado project as a whole. the major machine architectural features are evaluated, other project aspects such as design automation and management structures are explained, a chronological history with milestones is included, and a variety of accomplishments, red herrings, and shortfalls is discussed. the paper concludes with some speculations on what the project might have done differently and what might be done differently today instead of in the late 1970s.  although more than a dozen scientists and technicians contributed to the project, the evaluative and speculative parts of this paper are the sole responsibility of the author.  kenneth a. pier
switcherland: a qos communication architecture for workstation clusters computer systems have become powerful enough to process continuous data streams such as video or animated graphics. while processing power and communication bandwidth of today's systems typically are sufficient, quality of service (qos) guarantees as required for handling such data types cannot be provided by these systems in adequate ways.we present switcherland, a scalable communication architecture based on crossbar switches that provides qos guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission delays. similar to the atm technology switcherland provides qos guarantees with the help of service classes, that is, data transfers are characterized as variable bit rate traffic or constant bit rate traffic. however, unlike lan technologies, switcherland is optimized for cluster computing in that (i) it serves as a backplane interconnection fabric as well as a lan, (ii) it extends support for service classes by also covering the end nodes of the network, (iii) it provides low latency in the order of one microsecond per switch, and (iv) it uses a communication model based on a global memory to simplify programming. hans eberle erwin oertli
a new atm adaptation layer for tcp/ip over wireless atm networks  this paper describes the design and performance of a new atm adaptation layer protocol aal - t for improving tcp performance over wireless atm networks. the wireless links are characterized by higher error rates and burstier error patterns in comparison with the fiber links for which atm was introduced in the beginning. since the low performance of tcp over wireless atm networks is mainly due to the fact that tcp always responds to all packet losses by congestion control, the key idea in the design is to push the error control portion of tcp to the aal layer so that tcp is only responsible for congestion control. the aal - t is based on a novel and reliable arq mechanism to support quality - critical tcp traffic over wireless atm networks. the proposed aal protocol has been validated using the opnet tool with the simulated wireless atm network. the simulation results show that the aal - t provides higher throughput for tcp over wireless atm networks compared to the existing approach of tcp with aal 5.  ian f. akyildiz inwhee joe