waashk/acm huggingface dataset:
high-level power estimation with interconnect effects  we extend earlier work on high-level average power estimation to include the power due to interconnect loading. the resulting technique is a combination of a rtl- level gate count prediction method and average interconnect estimation based on rent's rule. the method can be adapted to be used with different place and route engines and standard cell libraries. for a number of benchmark circuits, the method is verified by extracting wire lengths from a layout of each circuit and then comparing the predicted (at rtl) power against that measured using spice. an average error of 14.4% is obtained for the average interconnect length, and an average error of 25.8% is obtained for average power estimation including interconnect effects.  kavel m. buyuksahin farid n. najm
dynamic ipc/clock rate optimization current microprocessor designs set the functionality and clock rate of the chip at design time based on the configuration that achieves the best overall performance over a range of target applications. the result may be poor performance when running applications whose requirements are not well-matched to the particular hardware organization chosen. we present a new approach called complexity- adaptive processors (caps) in which the ipc/clock rate tradeoff can be altered at runtime to dynamically match the changing requirements of the instruction stream. by exploiting repeater methodologies used increasingly in deep sub- micron designs, caps achieve this flexibility with potentially no cycle time impact compared to a fixed architecture. our preliminary results in applying this approach to on-chip caches and instruction queues indicate that caps have the potential to significantly outperform conventional approaches on workloads containing both general-purpose and scientific applications. david h. albonesi
extracting schematic-like information from cmos circuit net-lists  a global circuit structure is established from the circuit net-list based on knowledge about cmos circuits. this approach first partitions the circuit network and then assigns signal flow directions accordingly. the information obtained is absent in the net-list but explicitly present in schematic diagrams. such interpretation of a circuit network can provide extra heuristics to assist in various cmos circuit design tasks.  w.-j. lue l. p. mcnamee
evaluating the performance of four snooping cache coherency protocols  write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. in particular, write-invalidate performance can suffer as block size increases; and large cache sizes will hurt write-broadcast. read- broadcast and competitive snooping extensions to the protocols have been proposed to solve each problem.  our results indicate that the benefits of the extensions are limited. read- broadcast reduces the number of invalidation misses, but at a high cost in processor lockout from the cache. the net effect can be an increase in total execution cycles. competitive snooping benefits only those programs with high per-processor locality of reference to shared data. for programs characterized by inter- processor contention for shared addresses, competitive snooping can degrade performance by causing a slight increase in bus utilization and total execution time.  s. j. eggers r. h. katz
behavioral synthesis of combinational logic using spectral-based heuristics  a prototype system developed to convert a behavioral representation of a boolean function in obdd form into an initial structural representation is described and experimental results are given. the system produces a multilevel circuit using heuristic rules based on properties of a subset of spectral coefficients. since the behavioral description is in obdd form, efficient methods are used to quickly compute the small subset of spectral coefficients needed for the application of the heuristics. the heuristics guide subsequent decompositions of the obdd, resulting in an iterative construction of the structural form. at each stage of the translation, the form of the decomposition is chosen in order to achieve optimization goals.  m. a. thornton v. s. s. nair
architectural support for the management of tightly-coupled fine-grain goals in flat concurrent prolog  we propose architectural support for goal management as part of a special- purpose processor architecture for the efficient execution of flat concurrent prolog. goal management operations: halt, spawn, suspend and commit are decoupled from goal reduction, and overlapped in the goal management unit. their efficient execution is enabled using a goal cache. we evaluate the performance of the goal management support using an analytic performance model and program parameters characteristic of the system's development workload. most goal management operations are completely overlapped, resulting in a speedup of 2. higher speedups are obtained for workloads that exhibit greater goal management complexity.  leon alkalaj tomás lang miloš ercegovac
patege: an automatic dc parametric test generation system for series gated ecl circuits  for ecl circuits. dc parametric tests such as input current (iil iih), reference voltage (vbb), and power supply current (icc) tests are executed as well as functional tests.  this paper describes: an automatic dc parametric test generation system patege for the series gated ecl circuits. patege can automatically generate the test patterns and calculate the expected values for iil, iih, vbb and icc tests.  takuji ogihara shuichi saruyama shinichi murai
congestion estimation during top-down placement  congestion is one of the fundamental issues in vlsi physical design. in this paper, we propose two congestion estimation approaches for early placement stages. first, we theoretically analyze the peak congestion value of the design and experimentally validate the estimation approach. second, we estimate regional congestion in the early top-down placement. this is done by combining the wirelength distribution model and inter-region wire estimation. both approaches are based on the well known rent's rule, which is previously used for wirelength estimation. this is the first attempt to predict congestion using rent's rule. the estimation results are compared with the layout after placement and global routing. experiments on large industry circuits show that the early congestion estimation based on rent's rule is a promising approach.  xiaojian yang ryan kastner majid sarrafzadeh
a method of automatic data path synthesis  a method of automatically synthesizing data paths from a behavioral description has been developed. an initial implementation of this method, which is integrated into the carnegie- mellon university design automation system, is presented in this paper. its principles of operation are explained and an evaluation of its performance is given. this method of automatic synthesis surpasses the performance of previous cmu-da approaches. further, a designer can use it in a semi-automatic fashion and complement its abilities with his expert insight.  charles y. hitchcock donald e. thomas
automatic generation of fpga routing architectures from high-level descriptions  in this paper we present a "high- level" fpga architecture description language which lets fpga architects succinctly and quickly describe an fpga routing architecture. we then present an "architecture generator" built into the vpr cad tool [1, 2] that converts this high-level architecture description into a detailed and completely specified flat fpga architecture. this flat architecture is the representation with which cad optimization and visualization modules typically work. by allowing fpga researchers to specify an architecture at a high-level, an architecture generator enables quick and easy "what-if" experimentation with a wide range of fpga architectures. the net effect is a more fully optimized final fpga architecture. in contrast, when fpga architects are forced to use more traditional methods of describing an fpga (such as the manual specification of every switch in the basic file of the fpga), far less experimentation can be performed in the same time, and the architectures experimented upon are likely to be highly similar, leaving important parts of the design space completely unexplored.  this paper describes the automated routing architecture generation problem, and highlights the two key difficulties --- creating an fpga architecture that matches all of an fpga architect's specifications, while simultaneously determining good values for the many unspecified portions of an fpga so that a high quality fpga results. we describe the method by which we generate fpga routing architectures automatically, and present several examples.  vaughn betz jonathan rose
optimizations and oracle parallelism with dynamic translation  we describe several optimizations which can be employed in a dynamic binary translation (dbt) system, where low compilation/translation overhead is essential. these optimizations achieve a high degree of ilp, sometimes even surpassing a static compiler employing more sophisticated, and more time- consuming algorithms [9]. we present results in which we employ these optimizations in a dynamic binary translation system capable of computing oracle parallelism.  kemal ebcioglu erik r. altman michael gschwind sumedh sathaye
verifying sequential equivalence using atpg techniques  in this paper we address the problem of verifying the equivalence of two sequential circuits. state-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. however, the bdd-based approaches for verifying sequential equivalence can easily run into memory explosion for such designs. in an attempt to handle larger circuits, we modify test pattern- generation techniques for verification. the suggested approach utilizes the popular efficient backward-justification technique used in most sequential atpg programs. we present several techniques to enhance the efficiency of this approach by (1) identifying equivalent flip-flop pairs using an induction- based algorithm, and (2) generalizing the idea of exploring the structural similarity between circuits to perform verification in stages. this atpg-based framework is suitable for verifying circuits either with or without a reset state. in order to extend this approach to verify retimed circuits, we introduce a delay-compensation-based algorithm for preprocessing the circuits. the experimental results of verifying the correctness of circuits after sequential redundancy removal and retiming with up to several hundred flip- flops are presented.
layout-driven rtl binding techniques for high-level synthesis using accurate estimators  the importance of effective and efficient accounting of layout effects is well established in high-level synthesis (hls), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. this feature is highly desirable in order to avoid unnecessary iterations through the design process. in this article, we address the problem of layout-driven register-transfer-level (rtl) binding as this step has a direct relevance to the final performance of the design. by producing not only an rtl design but also an approximate physical topology of the chip-level implementation, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process.  min xu fadi j. kurdahi
exploiting ilp in page-based intelligent memory  this study compares the speed, area, and power of different implementations of active pages [ocs98], an intelligent memory system which helps bridge the growing gap between processor and memory performance by associating simple functions with each page of data. previous investigations have shown up to 1000x speedups using a block of reconfigurable logic to implement these functions next to each sub-array on a dram chip.  in this study, we show that instruction-level parallelism, not hardware specialization, is the key to the previous success with reconfigurable logic. in order to demonstrate this fact, an active page implementation based upon a simplified vliw processor was developed. unlike conventional vliw processors, power and area constraints lead to a design which has a small number of pipeline stages. our results demonstrate that a four-wide vliw processor attains comparable performance to that of pure fpga logic but requires significantly less area and power.  mark oskin justin hensley diana keen frederic t. chong matthew farrens aneet chopra
low power sequential circuit design by using priority encoding and clock gating  this paper presents a state assignment technique called priority encoding, which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. the basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. practical design examples are studied and simulated by pspice. experimental results demonstrate that the priority encoding technique can result in sizable power saving.  xunwei wu massoud pedram
computer-aided design of electrical circuits simulation techniques (a tutorial)  one of the very first applications of digital computers was that of simulation. perhaps more computer time has been used over the years in this area than any other. many programs are responsible for the largest computers in existence grinding away, day in and day out, in this general area.  this paper will cover simulation as it applies to the design and development of very large scale integrated (vlsi) circuits. these techniques cover broadly the areas of process and circuit simulation, logic and timing simulation (to include faulted machine performance), and system simulation or simulation at the major block level, sometimes referred to the register transfer level or rtl simulation.  this paper will present numerous references so that the reader can pursue further study as needed. naturally only a summary of each of the major techniques can be presented. it is again noted that this paper covers only the restricted area of simulation as it applies to the development of vlsi although many topics have application far beyond this.  glenn r. case
a high level synthesis tool for mos chip design  this paper describes a design tool called functional design system (fds) that supports high level mos lsi design. designers can build circuits at the register transfer level by using a set of high level fds primitives. fds then automatically produces in seconds an accurate and efficient polycell implementation for these primitives. therefore, the design cycle time can be reduced significantly. fds is an integral part of a larger cad system [1] which supports other aspects of the design cycle, namely, graphical design capture, simulation, test generation, and layout. the system has proved to be highly successful in helping designers to develop extremely reliable chips in a short time frame.  jean dussault chi-chang liaw michael m. tong
verification techniques for cache coherence protocols  in this article we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on state enumeration, (symbolic model checking, and symbolic state models. since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate that state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. to be successful for systems of arbitrary complexity, a verification technique must solve this so- called state space explosion problem. the emphasis of our discussion is onthe underlying theory in each method of handling the state space exposion problem, and formulationg and checking the safety properties (e.g., data consistency) and the liveness properties (absence of deadlock and livelock). we compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. also, we discuss issues of generality, applicability, automaticity, and amenity for existing tools in each class of methods. no method is truly superior because each method has its own strengths and weaknesses. finally, refinements that can further reduce the verification time and/or the memory requirement are also discussed.  fong pong michel dubois
low power self-timed radix-2 division (poster session)  a self-timed radix-2 division scheme for low power consumption is proposed. by replacing dual-rail dynamic circuits in non-critical data paths with single- rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. spice simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% energy reduction compared to afully dual-rail version.  jae-hee won kiyoung choi
technology mapping issues for an fpga with lookup tables and pla-like blocks  in this paper we present new technology mapping algorithms for use in a programmable logic device (pld) that contains both lookup tables (luts) and pla-like blocks. the technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of luts and pla-like blocks. since no other technology mapping algorithm for this problem has been previously published, we cannot compare our approach to others. instead, to illustrate the importance of this problem we use our algorithms to investigate the benefits provided by a pld architecture with both luts and pla-like blocks compared to a traditional lut-based fpga. the experimental results indicate that our mixed pld architecture is more area- efficient than lut-based fpgas by up to 29%, or more depth-efficient by up to 75%.1  alireza kaviani stephen brown
power-optimal encoding for dram address bus (poster session)  this paper presents pyramid code, an optimal code for transmitting sequential addresses over a dram bus. constructed by finding an eulerian cycle on a complete graph, this code is optimal for conventional dram in the sense that it minimizes the switching activity on the time-multiplexed address bus from cpu to dram. experimental results on a large number of testbenches with different characteristics (i.e. sequential vs. random memory access behaviors) are reported and demonstrate a reduction of bus activity by as much as 50%.  wei-chung cheng massoud pedram
an automated system for testing lsi memory chips  this paper describes a software system for testing lsi memory chips. this system achieves complete automation by customizing test data for a given part number design and by creating an overall test program to be used by a computer-controlled tester in a manufacturing environment. this system encompasses dc testing of the memory product and test sites, ac testing under a variety of timing conditions, and generating a complete set of ac functional test patterns.  h. d. schnurmann l. j. vidunas r. m. peters
a new integrated system for pla testing and verification  part is a system for pla testing and verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. to this purpose, it provides several facilities, among which the capability of generating fault population on the basis of layout information. part aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. this is achieved by means of an efficient partitioning algorithm together with powerful heuristics. test minimality is ensured by a simple procedure. in the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.  fabio somenzi silvano gai marco mezzalama paolo prinetto
adaptive software cache management for distributed shared memory architectures  an adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. we contend that, in distributed shared memory systems, adaptive cache coherence mechanisms will outperform static cache coherence mechanisms. we have examined the sharing and synchronization behavior of a variety of shared memory parallel programs. we have found that the access patterns of a large percentage of shared data objects fall in a small number of categories for which efficient software coherence mechanisms exist. in addition, we have performed a simulation study that provides two examples of how an adaptive caching mechanism can take advantage of semantic information.  john k. bennett john b. carter willy zwaenepoel
design issues for dynamic voltage scaling  processors in portable electronic devices generally have a computational load which has time-varying performance requirements. dynamic voltage scaling is a method to vary the processors supply voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. a dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.  thomas d. burd robert w. brodersen
using complete-1-distinguishability for fsm equivalence checking this article introduces the notion of a complete-1-distinguishability (c-1-d) property for simplifying equivalence checking of finite state machines (fsms). when a specification machine has the c-1-d property, the traversal of the product machine can be eliminated. instead, a much simpler check suffices. the check consists of first obtaining a 1-equivalence mapping between the individually reachable states of the specification and the implementation machines, and then checking that it is a bisimulation relation. the c-1-d property can be used directly for specification machines on which it naturally holds---a condition that has not been exploited thus far in fsm verification. we also show how this property can be enforced on an arbitrary fsm by exposing some of its latch outputs as pseudo-primary outputs during synthesis and verification. in this sense, our synthesis/verification methodology provides another point in the trade-off curve between constraints-on-synthesis versus complexity-of- verification. practical experiences with this methodology have resulted in success with several examples for which it is not possible to complete verification using existing implicit state space traversal techniques. pranav ashar aarti gupta sharad malik
systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications  in contrast to current design practice for (programmable) processor mapping, which mainly targets performance, we focus on a systematic trade-off between cycle budget and energy consumed in the background memory organization. the latter is a crucial component in many of todays designs, including multi- media, network protocols and telecom signal processing. we have a systematic way and tool to explore both freedoms and to arrive at pareto charts, in which for a given application the lowest cost implementation of the memory organization is plotted against the available cycle budget per submodule. this by making optimal usage of a parallelized memory architecture. we indicate, with results on a digital audio broadcasting receiver and an image compression demonstrator, how to effectively use the pareto plot to gain significantly in overall system energy consumption within the global real-time constraints.  erik brockmeyer arnout vandecappelle francky catthoor