waashk/acm huggingface dataset:
automating mask layout and specification panel session  it is becoming increasingly important that the photomasks needed for a vlsi circuit be produced correctly the first time. to obtain good masks, both the design of the chips and their arraying onto masks must be correct. much attention has been given to chip design---simulators and design-rule checkers are abundant. in this panel discussion, however, we will be addressing the other aspect--- the layout and specification of the masks themselves.  since a growing number of vlsi designers are turning from traditional optical mask- making to electron-beam (e-beam) mask-making, the emphasis of this discussion will be towards e-beam technology, although many of the concepts apply to all mask making.  robert b. cutler
introducing redundant computations in rtl data paths for reducing bist resources  the need for considering bist requirements during the scheduling and assignment stages of behavioral synthesis has been demonstrated in previous research and techniques for reducing bist resources of a data path during these stages of synthesis have been developed. however, the degree of freedom that can be exploited during scheduling and assignment to minimize these resources is often limited by the data and control dependencies of a behavior. in this paper, we propose transformation of a behavior before scheduling and assignment, namely introducing redundant computations such that the resulting data path is testable using few bist resources. the transformation makes use of spare capacity of modules to add redundancy that enables test paths to be shared among the modules. a technique for identifying potential bist resource sharing problems in a behavior and resolving them by redundant computations is presented. introduiction of redundant computations is performed without compromising the latency and functional resource requirement of the behavior.  ishwar parulkar sandeep k. gupta melvin a. breuer
hierarchical circuit extraction with detailed parasitic capacitance  this paper describes a hierarchical mos layout verification program called iv. iv extracts a circuit netlist from a mos layout and then compares this netlist to a reference circuit netlist obtained from a schematic. the circuit extraction phase of iv is described in detail. a unique characteristic of the program is the treatment of parasitic capacitance. iv is currently being used in a production environment to extract circuits in a variety of nmos and cmos processes.  gary m. tarolli william j. herman
raft191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults  the problem of delay fault- testing and detection of chips with marginal performance has become even more critical than before due to advancing clock speeds. in this paper, a methodology for detection of marginal digital circuits and diagnosis of gate delay failures is developed. a new test application methodology is proposed in which test vectors may be applied to digital combinational circuits at intervals smaller than the critical path delay of the circuit and signal waveform analysis is used to interpret the test results. the resulting tests are called rapid fire tests (for raft) and allow classification of circuits from "good" to "bad" along a continuous scale.  abhijit chatterjee jacob a. abraham
trace preconstruction  trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. consequently, their performance may suffer due to capacity and compulsory misses. trace preconstruction augments a trace cache by performing a function analogous to prefetching. the trace preconstruction mechanism observes the processor's instruction dispatch stream to detect opportunities for jumping ahead of the processor. after doing so, the preconstruction mechanism fetches static instructions from the predicted future region of the program, and constructs a set of traces in advance of when they are needed.  trace preconstruction can significantly increase both the performance of the trace cache and the robustness of the trace cache to varying workloads. all but one of the specint95 benchmarks see a notable reduction in trace cache miss rates from preconstruction. the three benchmarks that have the largest working set (gee, go and vortex) see a 30% to 80% reduction in trace cache misses. we also consider the integration of preconstruction with another trace-specific mechanism (preprocessing) to produce a high performance frontend. when combined, preconstruction and trace preprocessing produce an average speedup of 14% for the specint95 benchmarks.  quinn jacobson james e. smith
dynamic memory disambiguation in the presence of out-of-order store issuing  with the help of the memory dependence predictor the instruction scheduler can speculatively issue load instructions at the earliest possible time without causing significant amounts of memory order violations. for maximum performance, the scheduler must also allow full out- of-order issuing of store instructions since any superfluous ordering of stores results in false memory dependencies which adversely affect the timely issuing of dependent loads. unfortunately, simple techniques of detecting memory order violations do not work well when store instructions issue out-of-order since they yield many false memory order violations. by using a novel memory order violation detection mechanism that is employed in the retire logic of the processor and delaying the checking for memory order violations, we are able to allow full out-of-order issuing of store instructions without causing false memory order violations. in addition, our mechanism can take advantage of data value redundancy. we present an implementation of our technique using the store set memory dependence predictor. an out-of-order superscalar processor that uses our technique delivers an ipc which is within 100, 96 and 85 % of a processor equipped with an ideal memory disambiguator at issue widths of 8, 16 and 32 instructions respectively.  soner onder rajiv gupta
area efficient architectures for information integrity in cache memories information integrity in cache memories is a fundamental requirement for dependable computing. conventional architectures for enhancing cache reliability using check codes make it difficult to trade between the level of data integrity and the chip area requirement. we focus on transient fault tolerance in primary cache memories and develop new architectural solutions, to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code. the underlying idea is to exploit the corollary of reference locality in the organization and management of the code. a higher protection priority is dynamically assigned to the portions of the cache that are more error-prone and have a higher probability of access. the error-prone likelihood prediction is based on the access frequency. we evaluate the effectiveness of the proposed schemes using a trace-driven simulation combined with software error injection using four different fault manifestation models. from the simulation results, we show that for most benchmarks the proposed architectures are effective and area efficient for increasing the cache integrity under all four models. seongwoo kim arun k. somani
estimation of maximum current envelope for power bus analysis and design  in this p ap er we pr esent an inputpattern independent method to compute the maximum current envelope, which is an upper bound over all possible curr ent waveforms drawn by a circuit. the maximum current envelope can be used to compute the worst-c ase rms current and average cur rent dr awn by a set of gates. these current values can be used in the design of the p ower bus to ensure that the power bus interconne cts are not susc eptible to ele ctromigration (em) induced failur e. we also present comparisons with exhaustive/long simulations for mcnc/iscas-85 benchmark circuits to verify the accuracy of the method.  s. bobba i. n. hajj
efficient final placement based on nets-as-points  deterministic optimization programs are coming to be considered as viable alternatives for the placement of very large sea-of-gate, gate array and standard cell designs. a nets-as-points placement program has been described which provides competitive results in comparison with non- deterministic placement, and at a fraction of the run time. a new pseudo steiner tree model for the gate placement about the netpoints, along with a virtual channel snap- to-grid procedure, provides results superior to the original nets-as-points placement program without requiring iterative improvement.  x. zhang t. l. pillage r. a. rohrer
optimal clock period fpga technology mapping for sequential circuits  we study the technology mapping problem for sequential circuits for look-up table (lut) based field programmable gate arrays (fpgas). existing approaches to the problem simply remove the flip-flops (ffs), then map the remaining combinational logic, and finally put the ffs back. these approaches ignore the sequential nature of a circuit and assume the positions of the ffs are fixed. however, ffs in a sequential circuit can be reposistioned by a functionality- preserving transformation called retiming. as a result, existing approaches can only consider a very small portion of the available solution space. we propose in this paper a novel approach to the technology mapping problem. in our approach, retiming is integrated into the technology mapping process so as to consider the full solution space. we then present a polynomial technology mapping algorithm that, for a given circuit, produces a mapping solution with the minimum clock period among all possible ways of retiming. the effectiveness of the algorithm is also demonstrated experimentally.  peichen pan c. l. liu
a spatially-adaptive bus interface for low-switching communication (poster session)  adaptive encoding has shown to be an effective approach to bus power minimization in situations where characterization of the input statistics is not available. in this paper, we propose a novel technique for adaptive bus encoding that, conversely from existing solutions, exploits spatial correlations in the input data being transmitted to increase the accuracy in the dynamic selection of the encoding function. we discuss the encoding algorithm and we describe an architecture for its implementation as bus interface. we present experimental data collected in a realistic simulation framework on a number of meaningful benchmarks, and we compare them to those obtained through the application of existing encoding schemes.adaptive encoding has shown to be an effective approach to bus power minimization in situations where characterization of the input statistics is not available. in this paper, we propose a novel technique for adaptive bus encoding that, conversely from existing solutions, exploits spatial correlations in the input data being transmitted to increase the accuracy in the dynamic selection of the encoding function. we discuss the encoding algorithm and we describe an architecture for its implementation as bus interface. we present experimental data collected in a realistic simulation framework on a number of meaningful benchmarks, and we compare them to those obtained through the application of existing encoding schemes.  andrea acquaviva riccardo scarsi
formal hardware verification by integrating hol and mdg  _in order to overcome the limitations of automated tools and the cumbersome proof process of interactive theorem proving, we adopt a hybrid approach for formal hardware verification which uses the strengths of theorem proving (hol) with powerful mathematical tools such as induction and abstraction, and the advantages of automated tools (mdg) which support equivalence checking and model checking. the mdg system is a decision diagram based verification tool, primarily designed for hardware verification. hol is a theorem prover built on higher-order logic._  v. k. pisini s. tahar p. curzon o. ait-mohamed x. song
multi-level logic synthesis using communication complexity  we present a new multi-level logic synthesis technique based on minimizing communication complexity. intuitively, we believe this approach is viable because for many types of circuits lower bounds on the area needed to implement those circuits have been obtained considering only communication complexity. it performs especially well for functions which are hierarchically decomposable (e.g., adders, parity generators, comparators, etc.). unlike many other multi-level logic synthesis techniques, a lower bound can be computed to determine how well the synthesis was performed. we also present a new multi- level logic synthesis program based on the techniques described for reducing communication complexity.  t.-t. hwang r. m. owens m. j. irwin
timing analysis in a logic synthesis environment  a goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. the design process involves repeated timing analyses followed by appropriate modifications.  we present fast new algorithms for system level timing analysis and for the generation of timing constraints to guide the re-design of portions of combinational logic. our systematic approach correctly models designs that incorporate level sensitive latches controlled by multi-frequency, as well as simple multi-phase, clocks. a new feature is that the minimum number of settling times are evaluated for the nodes of combinational networks with input transitions controlled by different clock signals.  the computer program hummingbird uses the algorithms presented. hummingbird interfaces with other programs in the berkeley synthesis system through the oct data base. for a digital signal processing chip, comprising 3681 standard cells, timing analysis is performed in 14.87 cpu seconds on a vax 8800 running the ultrix operating system.  n. weiner a. sangiovanni-vincentelli
eliminating false loops caused by sharing in control path  in high- level synthesis, resource sharing may result in a circuit containing false loops that create great difficulty in timing validation during the design sign-off phase. it is hence desirable to avoid generating any false loops in a synthesized circuit. previous work [stok 1992; huang et al. 1995] considered mainly data path sharing for false loop elimination. however, for a complete circuit with both data path and control path, false loops can be created due to control logic sharing. in this article, we present a novel approach to detect and eleminate the false loops caused by control logic sharing. an effective filter is devised to reduce the computational complexity of false loop detection, which is based on checking the level numbers that are propagated from data path operators to imputs and outputs of the control path. only the input/output pairs of the control path identified by the filter are further investigated by traversing into the data path for false loop detection. a removal algorithm is then applied to eliminate the detected false loops, followed by logic minimization to further optimize the circuit. experimental results show that for the nine example circuits we tested, the final designs after false loop removal and logic minimization give only slightly larger area than the original ones that contain false loops.  alan su yu-chin hsu ta-yung liu mike tien-chien lee
a field-programmable mixed-analog-digital array  a novel field- programmable mixed-analog-digital array (fpma) is proposed, which contains a field-programmable analog array, a field-programmable digital array, and a mixed-signal interface. this device is intended to be used for the rapid implementation of mixed-signal circuits. the resource and architectural requirements for this array are determined by analyzing a set of sample circuits. the mixed-signal interface is constructed from converter blocks that contain configurable a/d and d/a converters, which gives some flexibility in the specification of the interface. a 1.2 μm cmos prototype ic has been designed to demonstrate the feasibility of fpma technology.  paul chow p. glenn gulak
compressing control rom for vlsi microprogrammed microprocessors  by taking advantage of information redundancy and mos structures, control roms for microprogrammed microprocessors can be considerably reduced. the compressed control rom (ccrom) method for reducing control roms is described in terms of a simple example that compares the fully horizontal (unencoded) approach, the normal partially encoded approach, and the ccrom approach. due to using ccrom, the effective cost of control rom is considerably reduced, and this in turn can have a significant effect on the design approach by making it more cost effective to implement control signals directly from the control rom rather than from random logic decodes.  karl m. guttag
fault diagnosis of bit-slice processor  this paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. a test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array. fault detection and fault location procedures using the generated test sequence are also presented.  using these procedures, a test microprogram and diagnostic system for the bit- sliced processor constructed by the array of four am 2901 bit-slices are developed.  young gil park jung wan cho
zeus: a hardware description language for vlsi  zeus is a technology- independent hardware description language which supports functional and structural (including layout) specifications. among the interesting characteristics of zeus are that type checking is used to prevent accidental power to ground connections and that only four basic type concepts (array, component, boolean and multiplex) and the possibility to instantiate types as signals are used to describe complex hardware. zeus has been tested on a variety of examples like: finite state machines, comparators, multiplexors, adders, pattern matching, am2901, dictionary machines and systolic stacks.  karl j. lieberherr svend e. knudsen
configuration prefetch for single context reconfigurable coprocessors  current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. in order to deal with this overhead, and increase the power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. in this paper we propose one technique for significantly reducing the reconfiguration latency: the prefetching of configurations. by loading a configuration into the reconfigurable logic in advance of when it is needed, we can overlap the reconfiguration with useful computation. we demonstrate the power of this technique, and propose an algorithm for automatically adding prefetch operations into reconfigurable applications. this results in a significant decrease in the reconfiguration overhead for these applications.  scott hauck
mgx  a symbolic layout system for double-metal silicon-gate mos technology in the style of gate matrix is presented. this system provides an integrated layout environment which consists of stick-figure-based graphic editor, a mask artwork generator, a connectivity checker, a circuit parameter extracter and simulator interfaces. all the modules are designed to deal with symbol data, rather than mask artwork, so that fast execution is realized. a method to associate symbol data with actual mask geometry is described along with the data structure employed. also described is network partitioning by signal names taking into account logical equivalence of transistor circuits.  masaru ozaki miho watanabe morio kakinuma mikio ikeda koji sato
a recursive algorithm for low-power memory partitioning  memory- processor integration offers new opportunities for reducing the energy of a system. in the case of embedded systems, one solution consists of mapping the most frequently accessed addresses onto the on-chip sram to guarantee power and performance efficiency. this option is especially effective when memory access patterns can be profiled and studied at design time (as in typical real-time embedded systems).  in this work, we propose an algorithm for the automatic partitioning of on- chip sram in multiple banks that can be independently accessed. starting from the dynamic execution profile of an embedded application running on a givenprocessor core, we synthesize a multi-banked sram architecture optimally fitted to the execution profile. the algorithm provides a globally optimum solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks.  results, collected on a set of embedded applications for the arm processor, have shown average energy savings around 42%.  luca benini alberto macii massimo poncino
irsim: an incremental mos switch-level simulator  this paper describes irsim, an incremental switch-level simulator for mos transistor circuits. in irsim, the circuit under simulation can be modified and then incrementally resimulated. this allows error correction and circuit operation verification to be performed in time proportional to the size of the modifications rather than the size of the entire circuit. to accomplish this incremental simulation, irsim maintains a history of circuit activity during simulation and only resimulates the sections of the circuit that deviate from their history. the program was tested on several corrections to errors that actually occurred in the design of a vlsi microprocessor. these errors were corrected and the circuit was incrementally resimulated 1.6 to 3500 times faster than simulating the entire circuit.  a. salz m. horowitz
modular description/simulation/synthesis using ddl  with the increased complexity of integrated circuits, a true top-down methodology is mandatory in their design. a construct that enables a modular description of a system design is added to ddl. the translator, simulator and synthesis software has been modified to retain this modularity throughout the design cycle. these enhancements allow a multi-level simulation and multi- technology synthesis of an integrated circuit.  s. g. shiva j. a. covington
fpga-based sonar processing  this paper presents the application of time-delay sonar beamforming and discusses a multi-board fpga system for performing several variations of this beamforming method in real-time for realistic sonar arrays. additionally, we show that our proposed fpga system has a six to twelve times performance advantage over an equivalent system created using currently available, high- performance dsps designed for multiprocessing systems. this performance advantage is due to the simplicity of the core calculation, the limitations of the the dsp's address calculation hardware, and the ability to customize the i/o of the fpga to the application.  paul graham brent nelson
verification testing  a new approach to test pattern generation which is particularly suitable for self-test is described. required computation time is much less than for present-day automatic test pattern generation (atpg) programs. fault simulation is not required. more patterns may be obtained than from standard atpg programs. however, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. test length is easily controlled. the test patterns are easily generated algorithmically either by program or hardware.  e. j. mccluskey