waashk/acm huggingface dataset:
filling and slotting: analysis and algorithms  in very deep-submicron vlsi, certain manufacturing steps -- notably optical exposure, resist development and etch, chemical vapor deposition and chemical- mechanical polishing (cmp)-- have varying effects on device and interconnect features depending on local characteristics of the layout. to make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion ("filling") or partial deletion ("slotting") of features in the layout. today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. without an accurate estimate of the filling and slotting, rc extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. therefore, future place-and- route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. we give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. we also present efficient algorithms for density analysis as well as for filling/slotting synthesis. our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.  andrew b. kahng gabriel robins anish singh huijuan wang alexander zelikovsky
a novel technique for sea of gates global routing  we present a novel global routing and cross-point assignment methodology for sea-of-gates (sog) designs. using the proposed congestion driven spanning trees (cdst), and continuously analyzing the congestion at all steps, nets are incrementally globally routed in one of the six well thought of heuristic steps of our methodology. this eliminates the need for rip-up and re-route and enables our approach to achieve good completion rates. we tested our flow on a number of testcases from the industry. the net lengths produced by our flow were compared to the theoretical lower-bound (steiner tree) and were found to be at most 4% worse. we compared the results of creating the net segments by the classical mst verses the cdst and observed an 80% improvement in the number of incomplete nets. completing the detailed routing using a commercially available detailed router validated the results of the proposed global routing and cross-point assignment.  bharat krishna c. y. roger chen naresh k. sehgal
slice-processors: an implementation of operation-based prediction  we describe the slice processor micro-architecture that implements a generalized operation-based prefetching mechanism. operation-based prefetchers predict the series of operations, or the computation slice that can be used to calculate forthcoming memory references. this is in contrast to outcome-based predictors that exploit regularities in the (address) outcome stream. slice processors are a generalization of existing operation-based prefetching mechanisms such as stream buffers where the operation itself is fixed in the design (e.g., address + stride). a slice processor dynamically identifies frequently missing loads and extracts on-the-fly the relevant address computation slices. such slices are then executed in-parallel with the main sequential thread prefetching memory data. we describe the various support structures and emphasize the design of the slice detection mechanism. we demonstrate that a relatively simple organization can significantly improve performance over an aggressive, dynamically-scheduled processor and for a set of pointer-intensive programs and for some integer applications from the spec'95 suite. in particular, a slice processor that can detect slices of up to 8 instructions extracted over of a region of up to 32 instructions improves performance by 11% on the average (even if slice detection requires up to 32 cycles). allowing slices of up to 16 instructions results in an average performance improvement of 15%. finally, we study how our operation-based predictor interacts with an outcome-based one and find them mutually beneficial.  andreas moshovos dionisios n. pnevmatikatos amirali baniasadi
optimization of high-performance superscalar architectures for energy efficiency  in recent years reducing power has become a critical design goal for high- performance microprocessors. this work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. we propose a methodology for power-optimization at the micro- architectural level. first, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy- efficient configurations forming a convex hull in the power- performance space. the energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. application of the developed methodology to a superscalar micro- architecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.  v. zyuban p. kogge
a vertically integrated vlsi design environment  a vlsi design system called vivid is the heart of a newly developed, vertically integrated design environment. this environment provides support for all phases of design from high-level system specification through on-site fabrication to construction of prototype systems. key features already implemented include: the use of a circuit description language at the level of a silicon assembler; a fast, highly interactive combination floor planner and layout editor; fast interactive timing simulation; and layout made free from design-rule constraints by the use of virtual-grid compaction. functional specification and verification, automated routing, standard cell layout, and semi-automated layout from schematics are being built upon the foundation formed by vivid.  jonathan rosenberg david boyer john dallen stephen daniel charles poirier john poulton durward rogers neil weste
a low-power correlator  the complex valued matched filter correlators consume maximum power in the ds/ss cdma receivers. these correlators accumulate 1024 samples lying in the range -7 to +7. this accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. as a ripple carry adder (rca) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a rca. previous incrementers were implemented as ripple counters. in this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. hence, it can be operated at a reduced voltage resulting in considerable power reduction. the incrementer is implemented using multiplexers, and gates and tspc registers. the ripple- counter correlator and the proposed incrementer correlator were laid out in magic using 0.5 cmos technology followed by power estimation using hspice. it is shown that the proposed architecture requires 50% less power than a ripple counter based design.  bibhudatta sahoo martin kuhlmann keshab k. parhi
hmap: a fast mapper for epgas using extended gbdd hash tables  a fast and efficient algorithm for technology mapping of electrically programmable gate arrays (epgas) is proposed. this hmap algorithm covers the boolean network with programmed logic modules bottom-up. the covering operation is based on collapsing the fanins of a node to form a bigger supernode such that fewer clusters are needed to be detected. then boolean matching is used to detect whether the collapsed supernode can be mapped into a logic module by looking up an extended gbdd hash table. the use of this table look-up matching can shorten the matching time significantly. as shown in the experiments, the average running time of hmap is 20 times faster than that of mis- pga2.  cheng-hsing yang chia-chun tsai jan-ming ho sao-jie chen
agents: a distributed client-server system for leaf cell generation  the agents system is a set of programs designed to generate automatically the mask-level layout of full custom cmos, bicmos, and bipolar leaf cells. the system is formed from four sever programs: the placer, router, database, and broker.  the placer places components in a cell, the router wires the circuits sent to it, the database stores all the information that is dependent upon the fabrication process, such as the design rules, and the broker makes the services of the other servers available.  these servers communicate over a computer network using the tcp/ip internet protocol. the placer server receives from its client the description and netlist of the circuit to be generated using edif (electronic design interchange format.) the output to its client is the mask layout of the circuit, again codified in edif. the comcept of agents as software components which have the ability to communicate and cooperate with each other is at the heart of the agents system. this concept is not only used at the higher level, for the four servers, but at a lower level as well, inside the router and placer servers, where small relatively simple agents work together to accomplish complex tasks. these small agents are responsible for all the reasoning carried out by the two servers, as they hold the basic inference routines and the knowledge needed by the servers. the system's philosophy is that competence should emerge out of the collective behavior of a large number of relatively simple agents. in addition and integrated to these small agents, the system uses a genetic algorithm to improve components' placement before routing.  dilvan de abreu moreira les t. walczowski
on computing optimized input probabilities for random tests  self testing of integrated circuits by random patterns has several technical and economical advantages. but there exists a large number of circuits which cannot be randomly tested, since the fault coverage achieved that way would be too low. in this paper we show that this problem can be solved by unequiprobable random patterns, and an efficient procedure is presented computing the specific optimal probability for each primary input of a combinational network.  those optimized random patterns can be produced on the chip during self test or off the chip in order to accelerate fault simulation and test pattern generation.  h.-j. wunderlich
orca a sea-of-gates place and route system  sea-of-gates is becoming an important design style for application specific integrated circuits (asics). the sea-of-gates technology offers more flexible placement and routing options not available in gate arrays. very few systems are available today that can automatically layout sea-of-gates and none of these systems effectively use the features available in sea-of-gates architecture. orca is a place and route system for sea-of-gates, whose objective is to produce the highest density layout by fully exploiting the inherent features of this new design style. the orca system starts with a module generator which preprocesses memory arrays and other logic with a regular structure to form high density macros. the remaining logic is clustered together to form flexible macros, which we call porous. the porous macro-cells allow global routing to pass through the macro instead of detouring around its perimeter. the porous macros are dynamically shaped and resized by interaction with global wiring analysis. finally, a general channelless area router has been developed to address the multiple layers of interconnect and routing areas which will be dominantly over-the-cell. due to the large size of the problem (e.g. 100,000 gates), the placement and routing algorithms are hierarchical.  m. igusa m. beardslee a. sangiovanni- vicentelli
mcnc's vertically integrated symbolic design system  this paper describes the vivid (vertically integrated vlsi design) system developed at the microelectronics center of north carolina. the system is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom vlsi circuits. this methodology has made it possible to provide, in a single integrated system, several unique features: technology independent tools for a wide range of mos processes (cmos, nmos, soi); scale independent circuit designs; open architecture that simplifies both integration with existing tools and creation of new tools; fast layout debugging using symbolic level circuit simulation; and fully automated mask generation and automated chip assembly.  c. durward rogers j. b. rosenberg s. w. daniel
behavioral fault simulation in vhdl  this paper presents two tools which facilitate the fault simulation of behavioral models described using vhdl. the first tool is the behavioral fault mapper (bfm). the bfm algorithm accepts a fault-free vhdl model and a fault list of n faults from which it produces n faulty models. the process of mapping the faults in the fault list onto copies of the original vhdl model is automated. the n faulty models are immediately suitable for fault simulation. the second tool presented is the test bench generator (tbg). the tbg algorithm creates the vhdl testbench and all other files necessary to complete a batch- mode fault simulation of the n faulty models.  p. c. ward j. r. armstrong
power consumption reduction in high-speed bandpass modulators  power consumption is a key point in the design of high-speed switched capacitor (sc) circuits, which allow to efficiently implement a number of analog functions. among them, sc Δ modulators are very popular for a/d conversion: in this kind of circuits, operational amplifiers are the most consuming cells because of their requirements in terms of dc gain and unity- gain frequency. a new amplifier with 110db dc gain and a unity-gain frequency of 250mhz is presented. the large power consumption (20mw) makes critical its use in commercial applications: however, combining this cell with a fast adaptive biasing circuit, high performance may be achieved with a reasonable dissipation.  this approach has been used in the design of a 6th-order bandpass Δ modulator featuring 73db dr and suitable for the conversion at if (10.7mhz) of the fm radio signal.  p. cusinato f. stefani a. baschirotto
low power high speed analog-to-digital converter for wireless communications  a new adc architecture is devised. this architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. the low power dissipation is a vital factor when we consider the chip reliability and integrity. the low energy consumption is a critical factor when we deal with battery operated devices like pcss. this technique may also be used to extend the attainable flash converter resolution by pre-calculating the most significant bits.  a. e. hussein m. i. elmasry
retiming with non-zero clock skew, variable register, and interconnect delay  a retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. these delay components are incorporated into retiming by assigning register electrical characteristics (recs) to each edge in the graph representation of the synchronous circuit. a matrix (called the sequential adjacency matrix or sam) is presented that contains all path delays. timing constraints for each data path are derived from this matrix. vertex lags are assigned ranges rather than single values as in standard retiming algorithms. the approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. the algorithm is demonstrated on modified mcnc benchmark circuits and both increased clock frequencies and elimination of all race conditions are observed.  tolga soyata eby g. friedman
consistency checking for mos/vlsi circuits  a general algorithm is presented for consistency checking between schematics. a transistor level schematic is partitioned into functional blocks by tracing direct current paths. the first level consistency check is performed on the directed graphs constructed from these functional blocks. a recursive, graph matching algorithm is introduced to find signal correspondences in the functional blocks. the second level check is performed within the functional blocks for either identical component connectivity or logic equivalence. performance of the program is demonstrated using an nmos chip.  ning-sang chang ravi m. apte
functional test generation for delay faults in combinational circuits  we propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. the proposed method is most suitable when a gate-level description of the circuit- under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. it is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. in addition, it can potentially be employed to supplement conventional test generators for gate- level circuits to reduce the cost of handling large numbers of paths. a parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. if Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. an appropriate subset of tests can be selected once the implentation is known. the test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. the experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.  irith pomeranz sudhakar m. reddy
taking into account asynchronous signals in functional test of complex circuits  the proposed functional test method for complex circuits presents the following features:  \\- the test problem is studied in the aggregate; a test method, a test environment and automated test program generation are proposed.  \\- the circuit behavior is considered as a whole. including the response to instructions (or commands). and to signals at the same level.  emphasis is put on the signal test: an hardware which allows the test of signals and is compatible with functional testing is defined; a description language for signal timing diagrams is proposed.  c. bellon r. velazco
definition and solution of the memory packing problem for field-programmable systems  this paper defines a new optimization problem that arises in the use of a field-programmable system (fps). an fps consists of a set of field- programmable gate arrays and memories, and is used both for emulation of asics and computation. in both cases the application circuits will include a set of memories which may not match the number and aspect ratio of the physical memories available on the fps. this can often require that the physical memories be time-multiplexed to implement the required memories, in a circuit we call a memory organizer.  we give a precise definition of the packing optimization problem and present an algorithm for its solution. the algorithm has been implemented in a cad tool that automatically produces a memory organizer circuit ready for synthesis by a commercial fpga tool set.  david karchmer jonathan rose
a new min-cut placement algorithm for timing assurance layout design meeting net length constraint  this paper presents a new min-cut placement algorithm for timing assurance layout design. when critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. this algorithm is built into the layout system for gate arrays called galop [1] and has been successfully applied to clock skew control of an ecl 12k-gate gate array.  masayuki terai kazuhiro takahashi koji sato
exploiting a new level of dlp in multimedia applications  this paper proposes and evaluates mom: a novel isa paradigm targeted at multimedia applications. by fusing conventional vector isa approaches together with more recent simd-like (single instruction multiple data) isas (such as mmx), we have developed a new matrix oriented isa which efficiently deals with the small matrix structures typically found in multimedia applications. mom exploits a level of dlp not reachable by neither conventional vector isas nor simd-like media isa extensions. our results show that mom provides a factor of 1.3x to 4x performance improvement when compared with two different multimedia extensions (mmx and mdmx) on several kernels, which translates into up to a 50% of performance gain when measuring full applications (20% in average). furthermore, the streaming nature of mom provides additional advantages for executing multimedia applications, such as a very low fetch pressure or a high tolerance to memory latency, making mom an ideal candidate for the embedded domain.  jesus corbal mateo valero roger espasa
reducing bus transition activity by limited weight coding with codeword slimming  transitions on high capacitance busses in vlsi systems result in considerable power dissipation. various coding schemes have been proposed in literature to encode the input signal in order to reduce the number of transitions. number of transitions can be reduced by introducing redundancy in data transferred over the busses. for a given amount of redundancy there exists a lower bound on the average number of transitions. in this paper we derive a new coding scheme which leads to extremely practical techniques for bus transmission that reduce bus transitions to within 3.96-8.42% of the lower bound depending on the redundancy employed. there is also a net reduction in power dissipation ranging from 8.53-21.88% over an uncoded bus transmission scheme. this savings in power dissipation is identical to that for bus-invert coding per word transmitted the higher efficiency brought about by codeword slimming, however, results in shorter codewords than bus-invert coding which in turn results in higher energy efficiency in word transmission. applications suitable for this new technique include systems relying on bit-serial implementation and systems with bit- parallel implementations where the cost of extra parallel-to-serial and serial-to-parallel data-format converters is marginal compared to the power savings obtained.  vijay sundararajan keshab k. parhi
design and performance evaluation of new massively parallel vlsi mask verification algorithms in jigsaw  this paper describes jigsaw, the massively parallel mask checking system that has evolved from our earlier feasibility study on large-scale, fine-grain parallelism in simple mask checking tasks [1]. unlike previous systems, jigsaw parallelizes all phases of the checking process. we describe new techniques to handle all-angle geometry, the first massively parallel mask flattening and multi-layer netlist extraction algorithms, and measurements made comparing jigsaw, running on a connection machine, against industry-standard tools. end- to-end speedups, (i.e., from cif to errors) range from 19 to 58 over dracula, with larger masks producing larger speedups.  erik c. carlson rob a. rutenbar