waashk/acm huggingface dataset:
issues in ic implementation of high level, abstract designs  with the exponential explosion in chip complexity there is a growing need for high level design aids. a preliminary experiment was conducted in mating a hierarchical, top-down da system for data paths with an existing ic placement and router. nine designs ranging in complexity from 7 to 150 register transfers were synthesized. strong correlations were observed between high level, abstract measures and final placed and routed chip area. it was observed that use of logic primitives of a moderate level abstraction yielded a 50% savings in placed and routed chip area.  jin h. kim daniel p. siewiorek
two-level logic minimization for low power  in this paper we present a complete boolean method for reducing the power consumption in two-level combinational circuits. the two-level logic optimizer performs the logic minimization for low power targeting static pla, general logic gates, and dynamic pla implementations. we modify the espresso algorithm by adding our heuristics, which bias logic minimization toward lowering power dissipation. in our heuristics, signal probabilities and transition densities are two important parameters. the experimental results are promising.  jyh- mou tseng jing-yang jou
an over-cell gate array channel router  a gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels. macro interconnects are loosely assigned to the partially filled horizontal and vertical routing channels during global routing. each loose horizontal channel segment is assigned to a channel track using a maze router. vertical channel segments are completed by a modified dogleg channel router.  howard e. krohn
a deterministic approach to adjacency testing for delay faults  adjacency testing for delay faults is examined in both theory and implementation. we shall show that the necessary and sufficient conditions for adjacency testability yield an efficient method of robust delay test generation. empirical results (including several different cost measurements) are presented which demonstrate that our technique: (1) achieves high fault coverages under both the robust and nonrobust delay fault models and (2) is cost effective.  c. t. glover m. r. mercer
a study of 80x86/80x87 floating-point execution  the evolution of a processor architecture must include enhancements to both the fixed and floating-point units. to increase overall performance, architectural and implementation performance improvements to the floating- point unit must keep pace with the performance enhancements made to the fixed- point unit. in this paper we evaluate the performance enhancements provided by the evolution of the floating-point co-processor for the intel 80x86 family. using a suite of traces, we show how code compiled for predecessor co- processors will perform on current floating-point implementation.  zoran miljanic david r. kaeli
performance verification of circuits  this paper describes a multi-level simulation strategy for verifying and- optimizing vlsi circuit performance. circuit simulation alone is insufficient for ensuring that vlsi designs meet performance targets. to meet vlsi needs, a tri-level family of simulation tools consisting of critical path analyzers, parasitic timing simulators, and circuit simulators is proposed. the relationship and interface between these tools, including how they combine "tops-down" and "bottoms-up" design methodologies, and some results from the initial implementation of this strategy in actual vlsi product designs are also discussed.  jerry mar you-pang wei
abstract routing of logic networks for custom module generation  this paper describes a switchbox-type router for custom vlsi module generation as performed by a module planner. a module is decomposed into abstract cells consisting of global routes and boolean functional specifications. each abstract cell is given to a cell synthesizer which generates the circuit layout and through-the-cell routing. abstract routing for a module planner is in some sense similar to switchbox routing to the degree that all of the routes are generated internally within a rectangular boundary (routes are coming from four sides). the principle difference with respect to standard switchbox routing is at the geometric level, where a cell synthesizer generates the routing conduction layers along with circuit devices for each abstract cell within this rectangular region. the aspects of this paper which are thought to be novel contributions are 1) a relative pin assignment algorithm for the abstract cells; 2) a global routing penalty function which not only considers previous routes, but also considers gate complexity within the cells; 3) an efficient optimization algorithm for minimizing the number of tracks running through the module.  s. t. healey w. j. kubitz
condition graphs for high-quality behavioral synthesis  identifying mutual exclusiveness between operators during behavioral synthesis is important in order to reduce the required number of control steps or hardware resources. to improve the quality of the synthesis result, we propose a representation, the condition graph, and an algorithm for identification of mutually exclusive operators. previous research efforts have concentrated on identifying mutual exclusiveness by examining language constructs such as if- then-else statements. thus, their results heavily depend on the description styles. the proposed approach can produce results independent of description styles and identify more mutually exclusive operators than any previous approaches. the condition graph and the proposed algorithm can be used in any scheduling or binding algorithms. experimental results on several benchmarks have shown the efficiency of the proposed representation and algorithm.  hsiao-ping juan viraphol chaiyakul daniel d. gajski
an over-the-cell router  a program that produces single-layer planar routing over the cells for i2l and lst2l logic arrays is described. this router has been integrated into a layout system which was previously restricted to the layout of standard cell lsi chips. when used in conjunction with a channel router, the complete routing is produced automatically. this paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.  david n. deutsch paul glick
programs for verifying circuit connectivity of mos/lsi mask artwork  this paper describes three programs which perform connectivity rule check, logic gate recognition for logic simulation and circuit connectivity comparison. these programs have been developed for verifying circuit connectivity extracted from mask artwork. powerful algorithms are used in these programs, including a heuristic graph comparison algorithm, to realize highly practical verification aids. through the combined use of these programs, more cost-effective verification is possible.  makoto takashima takashi mitsuhashi toshiaki chiba kenji yoshida
ace: a circuit extractor  this paper describes the design, implementation and performance of a fiat edge-based circuit extractor for nmos circuits. the extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. measurements show that the run time of the edge-based algorithm used is linear in size of the circuit, with low implementation overheads. the extractor is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of cpu time on a vax 11/780. the high performance of the extractor has changed the role that a circuit extractor played in the design process, as it is now possible to extract a chip a number of times during the same session.  anoop gupta
nova: state assignment of finite state machines for optimal two-level logic implementations  the problem of encoding the states of a synchronous finite state machine (fsm), so that the area of a two-level implementation of the combinational logic is minimized, is addressed. as in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible boolean representation. in this paper we present algorithms for their solution, based on a new theoretical framework that offers advantages over previous approaches to develop effective heuristics. the algorithms are part of nova, a program for optimal encoding of control logic. final areas averaging 20% less than other state assignment programs and 30% less than the best random solutions have been obtained. literal counts averaging 30% less than the best random solutions have been obtained.  t. villa a. sangiovanni-vincentelli
behavioral level transformation in the cmu-da system  the carnegie- mellon university design automation system (cmu-da) [2] consists of a set of computer programs whose goal is to produce a complete design in a user- specified device technology, given as input a behavioral description of the piece of hardware to be designed and a set of constraints. this paper describes one of the tools in the cmu-da environment - a software package to perform optimizing transformations at the behavioral level. motivations for these transformations are given, and an example of their use is shown.  robert a. walker donald e. thomas
the standard transistor array (star) (part ii automatic cell placement techniques)  layout of a star device consists of the placement of standard cells (circuit elements) on the array and the routing of conductors between cells. cell placement must be such that routing is not hindered. also, placement procedures must be cost effective and easy to implement on a digital computer. a placement procedure for stars is described in this paper that satisfies these characteristics. the procedure attempts to optimize the placement with respect to several criteria including expected routing channel usage and routing via requirements. computer implementations of the procedure are discussed. experimental results are presented which indicate that the procedure yields near-optimum results in computationally convenient amounts of time.  glenn w. cox b. d. carroll
timing driven floorplanning on programmable hierarchical targets  the goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. the circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. the floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.  s. a. senouci a. amoura h. krupnova g. saucier
minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion  minimum power cmos asic macrocells are designed by minimizing the macrocell area using a new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures. the minimum macrocell area and power dissipation are projected for the 100, 70 and 50 nm technology generations and compared with a n-tier design without using repeaters. repeater insertion and a novel interconnect geometry scaling technique decrease the power dissipation by 58-68% corresponding to a macrocell area reduction of 70-78% for the global clock frequency designs of these three technology generations.  raguraman venkatesan jeffrey a. davis keith a. bowman james d. meindl
software-controlled caches in the vmp multiprocessor  vmp is an experimental multiprocessor that follows the familiar basic design of multiple processors, each with a cache, connected by a shared bus to global memory. each processor has a synchronous, virtually addressed, single master connection to its cache, providing very high memory bandwidth. an unusually large cache page size and fast sequential memory copy hardware make it feasible for cache misses to be handled in software, analogously to the handling of virtual memory page faults. hardware support for cache consistency is limited to a simple state machine that monitors the bus and interrupts the processor when a cache consistency action is required.  in this paper, we show how the vmp design provides the high memory bandwidth required by modern high-performance processors with a minimum of hardware complexity and cost. we also describe simple solutions to the consistency problems associated with virtually addressed caches. simulation results indicate that the design achieves good performance providing data contention is not excessive.  d. r. cheriton g. a. slavenburg p. d. boyle
algorithms for routing and testing routability of planar vlsi layouts  this paper studies the problem of routing wires in a grid among features on one layer of a vlsi chip, when a sketch of the layer is given. a sketch specifies the positions of features and the topology of the interconnecting wires. we give polynomial-time algorithms that (1) determine the routability of a sketch, and (2) produce a routing of a sketch that optimizes both individual and total wire length. these algorithms subsume most of the polynomial-time algorithms in the literature for planar routing and routability testing in the rectilinear grid model. we also provide an explicit construction of a database, called the rubber-band equivalent, to support computation involving the layout topology.  c e leiserson f m maley
read-after-read memory dependence prediction  we identify that typical programs exhibit highly regular read-after-read (rar) memory dependence streams. we exploit this regularity by introducing read- after-read (rar) memory dependence prediction. we also present two rar memory dependence prediction-based memory latency reduction techniques. in the first technique, a load can obtain a value by simply naming a preceding load with which a rar dependence is predicted. the second technique speculatively converts a series of loadi-use ;i,…,loadn-use< subscrpt>n chains into a single loadi-usei…use producer/consumer graph. our techniques can be implemented as surgical extensions to the recently proposed read-after-write (raw) dependence prediction based speculative memory cloaking and speculative memory bypassing. on average, our techniques provide correct values for an additional 20% (integer codes) and 30% (floating-point codes) of all loads. moreover, a combined raw- and rar-based cloaking/bypassing mechanism improves performance by 6.44% (integer) and 4.66% (floating-point) even when naive memory dependence speculation is used. the original raw-based cloaking/bypassing mechanism yields improvements of 4.28% (integer) and 3.20% (floating-point).  andreas moshovos gurindar s. sohi
on reordering instruction streams for pipelined computers  this paper describes a method to reorder the straight line instruction streams for pipelined computers which have one instruction issue unit but may contain multiple function units. the objective is to make the most efficient usage of the pipelines within the computer system. the input to the scheduler is the intermediate code of a compiler, and is represented by a data dependence graph (ddg).  the scheduler is a kind of list scheduler. the data dependence and the pipeline effect of the function units within the system have been considered for finding a most suitable time slot for each node during reordering time.  the scheduler has been implemented and several scientific application programs have been tested. the results show that in most of the cases the scheduler will achieve the optimal result. the average instruction issue rate is over 96%. as a comparison, the issue rate of an ordinary compiler is only 22%; and the issue rate of a compiler with the effect of pipeline but without reordering the instruction stream is about 45%.  j.-j. shieh c. papachristou
intrinsic response for analog module testing using an analog testability bus  a parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. the removal is done by an on- chip test generation technique and an intrinsic response extraction algorithm. on-chip test generation creates test signals on-chip to avoid the parasitic effects of the test application bus. the intrinsic response extraction cross- checks and cancels the parasitic effects of both test application and response observation paths. the tests using both spice simulation and mnabst-1 p1149.4 test chip reveal that the proposed algorthm can not only remove the parasitic effects of the test buses but also tolerate test signal variations. furthermore, it is robust enough to handle loud environmental noise and the nonlinearity of the switching devices.  chauchin su yue-tsang chen shyh-jye jou
evaluating the impact of memory system performance on software prefetching and locality optimizations  software prefetching and locality optimizations are techniques for overcoming the speed gap between processor and memory. in this paper, we evaluate the impact of memory trends on the effectiveness of software prefetching and locality optimizations for three types of applications: regular scientific codes, irregular scientific codes, and pointer-chasing codes. we find for many applications, software prefetching outperforms locality optimizations when there is sufficient memory bandwidth, but locality optimizations outperform software prefetching under bandwidth- limited conditions. the break-even point (for 1 ghz processors) occurs at roughly 2.5 gbytes/sec on today's memory systems, and will increase on future memory systems. we also study the interactions between software prefetching and locality optimizations when applied in concert. naively combining the techniques provides robustness to changes in memory bandwidth and latency, but does not yield additional performance gains. we propose and evaluate several algorithms to better integrate software prefetching and locality optimizations, including a modified tiling algorithm, padding for prefetching, and index prefetching.  abdel-hameed a. badawy aneesh aggarwal donald yeung chau-wen tseng
gala - an automatic layout system for high density cmos gate arrays  this paper describes the automatic layout software system - gala (gate array layout automation) - developed at hughes aircraft company for a high density cmos gate array family with 3u design rules. the system layout and hierarchical decomposition schemes used in gala are presented. the particular design environment and style are discussed. the system has been used in production for the various sizes of the hughes hcmos gate array family for over 2 years. routing results for some designs produced during that period are presented.  b. n. tien b. s. ting j. cheam k. chow s. c. evans
early load address resolution via register tracking  higher microprocessor frequencies accentuate the performance cost of memory accesses. this is especially noticeable in the intel's ia32 architecture where lack of registers results in increased number of memory accesses. this paper presents novel, non-speculative technique that partially hides the increasing load-to-use latency, by allowing the early issue of load instructions. early load address resolution relies on register tracking to safely compute the addresses of memory references in the front-end part of the processor pipeline. register tracking enables decode-time computation of register values by tracking simple operations of the form reg±immediate. register tracking may be performed in any pipeline stage following instruction decode and prior to execution.  several tracking schemes are proposed in this paper:  stack pointer tracking allows safe early resolution of stack references by keeping track of the value of the esp register (the stack pointer). about 25% of all loads are stack loads and 95% of these loads may be resolved in the front-end.  absol ute address tracking allows the early resolution of constant-address loads.< ;/italic>  displace ment-based tracking tackles all loads with addresses of the form reg±immediate by tracking the values of all general-purpose registers. this class corresponds to 82% of all loads, and about 65% of these loads can be safely resolved in the front-end pipeline.  the paper describes the tracking schemes, analyzes their performance potential in a deeply pipelined processor and discusses the integration of tracking with memory disambiguation.  michael bekerman adi yoaz freddy gabbay stephan jourdan maxim kalaev ronny ronen
practical considerations of clock-powered logic  recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a vlsi chip. to accomplish this requires a power source that can efficiently inject and extract energy, and an efficient power delivery system to connect the power source to the circuit nodes. the additional circuitry and timing required to support this process can readily exceed the power-savings benefit. clock-powered logic is a circuit-level, energy-recovery approach that has been implemented in two generations of small-scale microprocessor experiments. the results have shown that it is possible and practical to extract useful amounts of power savings by leveraging the additional circuitry for other compatible purposes. the capabilities and limitations of clock-powered logic as a competitive low-power approach are presented and discussed in this paper.  william athas
a loop optimization technique based on scheduling table  loop optimization is an important aspect of microcode compaction to minimize execution time. in this paper a new loop optimization technique for horizontal microprograms is presented, which makes use of the cyclic regularity of loops.  we have extended the concept of reservation table, which is used to develop a pipeline control strategy, so that both data dependencies and resource conflicts are taken into account. based on the analysis of the extended reservation table, or scheduling table, an optimal schedule can be obtained. the iterations of a loop are then rearranged to form a new loop body, whose length may be greater than that of the original one. but the average initiation latency between iterations is minimal.  d. liu w. k. giloi
reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)  recent studies [mgk 98, tiw 98] have confirmed that a significant amount of energy is dissipated in the process of instruction dispatching and issue in modern superscalar microprocessors. we propose a model for the energy dissipated by instruction dispatching and issuing logic in modern superscalar microprocessors and validate them through register level simulations and spice-measured dissipation coefficients from 0.5 micron cmos layouts of relevant circuits. alternative organizations are studied for instruction window buffers that result in energy savings of about 47% over traditional designs.  kanad ghose