waashk/acm huggingface dataset:
design of an atm switch for handoff support  in a wireless atm system, a network must provide seamless services to mobile users. to support this, mobility function should be added to existing atm networks. through a handoff operation, a mobile user can receive a service from the network without disconnecting the communication. a handoff results in connection path rerouting during an active connection. to avoid cell loss during a handoff, cell buffering and rerouting are required in the network. a handoff switch is a connection breakdown point on an original connection path in the network from which a new connection sub - path is established. it performs cell buffering and rerouting during a handoff. cell buffering and rerouting can introduce a cell out - of - sequence problem. in this paper we propose a handoff switch architecture with a shared memory. the architecture performs cell buffering and rerouting efficiently by managing logical queues of virtual connections in the shared memory and sorting head - of - line cells for transmission, thus achieving in - sequence cell delivery during a handoff. we also present simulation results to understand the impacts of handoffs on switch performance.  heechang kim h. jonathan chao
design and implementation of a prototype optical deflection network  we describe the design and implementation of a packet-switched fiber optic interconnect prototype with a shufflenet topology, intended for use in shared- memory multiprocessors. coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. nodes use deflection routing to resolve contention. each node contains a processor, memory, photonic switch, and packet routing processor. payload remains in optical form from source to final destination. each host processor is a commercial workstation with fifo interfaces between its bus and the photonic switch. a global clock is distributed optically to each node to minimize skew. component costs and network performance figures are presented for various node configurations including bit-per-wavelength and fiber-parallel packet formats. our efforts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experimental work. we summarize obstacles we encountered and discuss future work.  john feehrer jon sauer lars ramfelt
ds/cdma m-ary orthogonal signalling in a shadowed rayleigh channel for mobile communications  in this paper a modified rake receiver is studied for a frequency selective mobile radio channel. the reverse link (mobile to base station) is analysed, assuming lognormal shadowing and rayleigh fading and k asynchronous users, with m orthogonal sequences per user. the analysis is based on the consideration of the quadrature components of the signal and noise, taking advantage of the multipath effects. the performance evaluation is carried out in terms of both the bit error rate and outage probability in order to qualify completely the proposed receiver. the positive results assure the possibility of applying this system in a microcellular mobile radio environment.  panagiotis i. dallas fotini-niovi pavlidou
performance characteristics of two ethernets: an experimental study  local computer networks are increasing in popularity for the interconnection of computers for a variety of applications. one such network that has been implemented on a large scale is the ethernet. this paper describes an experimental performance evaluation of a 3 and a 10 mb/s ethernet. the effects of varying packet length and transmission speed on throughput, mean delay and delay distribution are quantified. the protocols are seen to be fair and stable. these measurements span the range from the region of high performance of the csma/cd protocol to the upper limits of its utility where performance is degraded. the measurements are compared to the predictions of existing analytical models. the correlation is found to range from good to poor, with more sophisticated models yielding better results than a simple one.  timothy a. gonsalves
performance evaluation of a decoded instruction cache for variable instruction-length computers  a decoded instruction cache (dinc) serves as a buffer between the instruction decoder and the other instruction- pipeline stages. in this paper we explain how techniques that reduce the branch penalty based on such a cache, can improve cpu performance. we analyze the impact of some of the design parameters of dincs on variable instruction- length computers, e.g., cisc machines.  our study indicates that tuning the mapping function of the instructions into the cache, can improve the performance substantially. this tuning must be based on the instruction length distribution for a specific architecture. in addition, the associativity degree has a greater effect on the dinc's performance, than on the performance of regular caches. we also discuss the difference between the performance of dincs and other caches, when longer cache lines are used. the results presented were obtained by both analytical study and trace-driven simulations of several integer unix applications.  gideon intrater ilan spillinger
measurement and modeling of computer reliability as affected by system activity  this paper demonstrates a practical approach to the study of the failure behavior of computer systems. particular attention is devoted to the analysis of permanent failures. a number of important techniques, which may have general applicability in both failure and workload analysis, are brought together in this presentation. these include: smeared averaging of the workload data, clustering of like failures, and joint analysis of workload and failures. approximately 17 percent of all failures affecting the cpu were estimated to be permanent. the manifestation of a permanent failure was found to be strongly correlated with the level and type of workload prior to the failure. although, in strict terms, the results only relate to the manifestation of permanent failures and not to their occurrence, there are strong indications that permanent failures are both caused and discovered by increased activity. more measurements and experiments are necessary to determine their respective contributions to the measured workload/failure relationship.  r. k. iyer d. j. rossetti m. c. hsueh
implications of hierarchical n-body methods for multiprocessor architectures  to design effective large-scale multiprocessors, designers need to understand the characteristics of the applications that will use the machines. application characteristics of particular interest include the amount of communication relative to computation, the structure of the communication, and the local cache and memory requirements, as well as how these characteristics scale with larger problems and machines. one important class of applications is based on hierarchical n-body methods, which are used to solve a wide range of scientific and engineering problems efficiently. important characteristics of these methods include the nonuniform and dynamically changing nature of the domains to which they are applied, and their use of long-range, irregular communication. this article examines the key architectural implications of representative applications that use the two dominant hierarchical n-body methods: the barnes-hut method and the fast multipole method.  we first show that exploiting temporal locality on accesses to communicated data is critical to obtaining good performance on these applications and then argue that coherent caches on shared-address-space machines exploit this locality both automatically and very effectively. next, we examine the implications of scaling the applications to run on larger machines. we use scaling methods that reflect the concerns of the application scientist and find that this leads to different conclusions about how communication traffic and local cache and memory usage scale than scaling based only on data set size. in particular, we show that under the most realistic form of scaling, both the communication-to-computation ratio as well as the working-set size (and hence the ideal cache size per processor) grow slowly as larger problems are run on larger machines. finally, we examine the effects of using the two dominant abstractions for interprocessor communication: a shared address space and explicit message passing between private address spaces. we show that the lack of an efficiently supported shared address space will substantially increase the programming complexity and performance overheads for these applications.  jaswinder pal singh john l. hennessy anoop gupta
personal work-stations at the university of waterloo  students and faculty at the university of waterloo are using the ibm personal computer as a powerful workstation to develop programs, and do their applications. the pcs are connected using two different network technologies. in one case, the pcs are connected into a micro-mainframe network called waterloo pc network, which allows both files and software to be located in a centralized file system accessed from any pc. since the language and applications software is portable and runs on both the mainframe or micro the user may choose to run an application on the computer that is appropriate for the size of the job. in the other case, the pcs are connected to another pc which acts as a file and print server. in both cases, the workstations do not have any local file storage. the talk will describe the design goals for pc networks, their design, current applications, and future plans.  sandra ward
router level filtering for receiver interest delivery  delivering data to on-line game participants requires the game data to be "customized" in real-time to each participant's characteristics. using multicast in such an environment might sound contradictory. but multicast is a very efficient communication paradigm to minimize the transmission delays. also, multicast reduces the workload at the sender. content delivery according to receiver interest can be achieved by group management in multicast. but the natural dynamics of the application results in numerous delays because of join/leave latencies. in this paper, we propose the router level filtering as a solution to the above problem.  rlf relies on an extension to the current ip multicast service model. it introduces "filters" in the router forwarding process thereby providing a simple effective mechanism to customize the data delivered to a multicast session receiver while minimizing the number of groups and the related management cost. contrary to other router filtering proposals, the filter semantics is determined by the application. the paper discusses protocol specification and implementation details of rlf, and shows how it may be implemented in routers.  manuel oliveira jon crowcroft christophe diot
projecting the growth of cellular communications  the tremendous success of cellular technology has fundamentally changed the way people communicate and prompted the evolution of a new multibillion dollar wireless communications industry. linking service areas, wireless communications has altered the way business is conducted. for instance, with a laptop computer, a pcmcia modem and a cellular phone, a real estate agent can contact his or her office and clients, check sales listings and arrange appointments while traveling. field service and sales people can, from customer locations, access corporate databases to check inventory status, prepare up-to-the-minute price and delivery quotes, and cut orders directly to the factory. two-way paging services allow a firm's workforce to stay in close contact, even when traditional wired communication services are not available. hand-held hybrids of phone-computer-fax machines feed information to wireless communication networks, allowing an executive to make decisions while watching a little league baseball game.  michael wang william j. kettinger
on the working set concept for data-flow machines  this paper discusses the concept of the working set for data-flow machines in order to establish one of the criteria for the realization of cost effective data-flow machines. the characteristics of program execution in conventional machines and data-flow machines are compared. then, a definition of the working set for data-flow machines is proposed, based on the simultaneity of execution and the principle of locality. several segmentation, fetch, and removal policies are described. evaluation is made in terms of feasibility, efficiency, and performance, through computer simulations.  mario tokoro j. r. jagannathan hideki sunahara
array abstractions using semantic analysis of trapezoid congruences  with the growing use of vector supercomputers, efficient and accurate data structure analyses are needed. what we propose in this paper is to use the quite general framework of cousot's abstract interpretation for the particular analysis of multi-dimensional array indexes. while such indexes are integer tuples, a relational integer analysis is first required. this analysis results of a combination of existing ones that are interval and congruence based. two orthogonal problems are directly concerned with the results of such an analysis, that are the parallelization/vectorization with the dependence analysis and the data locality problem used for array storage management. after introducing the analysis algorithm, this paper describes on a complete example how to use it in order to optimize array storage.  françois masdupuy
reliable broadband communication using a burst erasure correcting code  traditionally, a transport protocol corrects errors in a computer communication network using a simple arq protocol. with the arrival of broadband networks, forward error correction is desirable as a complement to arq. this paper describes a simplified reed-solomon erasure correction coder architecture, adapted for congestion loss in a broadband network. simulations predict it can both encode and decode at rates up to 1 gigabit per second in a custom 1 micron cmos vlsi chip.  a. j. mcauley
visualizing packet traces  this paper describes an environment for visualizing packet traces that greatly simplifies troubleshooting protocol implementations. network management centers routinely collect packet traces to tally traffic statistics and to troubleshoot protocol configuration and implementation problems. previous efforts have focused on the reliable collection of traces and their statistical interpretation. display of packet traces was restricted to a textual representation of the raw headers. our prototype environment interprets the trace as a whole. it identifies conversations across protocol layers, simulates the services offered by lower layers, and hides the lower layer implementation detail from the representation of higher layer conversations. our prototype offers over a dozen different types of diagrams for showing protocol interactions and uses linked highlighting to show the relationships between the objects in different diagrams.  john a. zinky fredric m. white
processor queueing disciplines in distributed systems  a distributed program consists of processes, many of which can execute concurrently on different processors in a distributed system of processors. when several processes from the same or different distributed programs have been assigned to a processor in a distributed system, the processor must select the next process to run. the following two questions are investigated: what is an appropriate method for selecting the next process to run? under what conditions are substantial gains in performance achieved by an appropriate method of selection? standard processor queueing disciplines, such as first- come-first-serve and round-robin-fixed-quantum, are studied. the results for four classes of queueing disciplines tested on three problems are presented. these problems were run on a testbed, consisting of a compiler and simulator used to run distributed programs on user-specified architectures.  elizabeth williams
quantifying loop nest locality using spec'95 and the perfect benchmarks  this article analyzes and quantifies the locality characteristics of numerical loop nests in order to suggest future directions for architecture and software cache optimizations. since most programs spend the majority of their time in nests, the vast majority of cache optimization techniques target loop nests. in contrast, the locality characteristics that drive these optimizations are usually collected across the entire application rather than at the nest level. researchers have studied numerical codes for so long that a number of commonly held assertions have emerged on their locality characteristics. in light of these assertions, we use the spec'95 and perfect benchmarks to take a new look at measuring locality on numerical codes based on references, loop nests, and program locality properties. our results show that several popular assertions are at best overstatements. for example, although most reuse is within a loop nest, in line with popular assertions, most misses are internest capacity misses, and they correspond to potential reuse between nearby loop nests. in addition, we find that temporal and spatial reuse have balanced roles within a loop nest and that most reuse across nests and the entire program is temporal. these results are consistent with high hit rates (80&amp;percent; or more hits), but go against the commonly held assumption that spatial reuse dominates. our locality measurements reveal important differences between loop nests and programs, refute some popular assertions, and provide new insights for the compiler writer and the architect.  kathryn s. mckinley olivier temam
omp: a risc-based multiprocessor using orthogonal-access memories and multiple spanning buses  this paper presents the architectural design and risc based implementation of a prototype supercomputer, namely the orthogonal multiprocessor (omp). the omp system is constructed with 16 intel 1860 risc microprocessors and 256 parallel memory modules, which are 2-d interleaved and orthogonally accessed using custom- designed spanning buses. the architectural design has been validated by a csim-based multiprocessor simulator. the design choices are based on worst- case delay analysis and simulation validation. the current omp prototype chooses a 2-dimensional memory architecture, mainly for image processing, computer vision, and neural network simulation applications. the 16-processor omp prototype is targeted to achieve a peak performance of 400 risc integer mips or a maximum of 640 mflops. this paper presents the architectural design of the omp prototype at system and pc board levels. we are presently entering the fabrication stage of all the pc boards. the system is expected to become operational in late 1991 and benchmarking results will be available in 1992. only hardware design features are reported here. software and simulation results are reported elsewhere.  k. hwang m. dubois d. k. panda s. rao s. shang a. uresin w. mao h. nair m. lytwyn f. hsieh j. liu s. mehrotra c. m. cheng
design principles and performance analysis of sscop: a new atm adaptation layer protocol  the service specific connection oriented protocol (sascop) has been approved recently as a new b-isdn atm adaptation layer (aal) protocol standard, initially for use in the signaling atm adaptation layer (saal), but also for support of certain types of use data transfer. sscop is a new type of protocol, embodying several design principles for high speed link and transport layer protocols. in this paper, the basic operation of sscop is described and the sscop design is compared with other similar protocols. next, the relationships between key protocol parameters (protocol window, control message transmission interval) and maximum achievable throughput effieiency are explored. in particular, approximate performance equations are derived for predicting the maximum throughput efficiency of sscop basedon the selected environment and parameter eettings. the equations can be used to determine how much buffer capacity and/or what protocol timer settings allow sscop to operate at high performance. the analytical results are confirmed through comparison with simulation results. in addition, simulation results illustrate the high throughput performance achievable when using sscop in a highly errored or loosy environment.  thomas r. henderson
the importance of being square  we present a theory that defines performance of packet-switching interconnection networks (delay and capacity) and their cost in terms of their geometry. this is used to prove that square banyan networks have optimal performance/cost ratio. these results, together with some known results on the complexity of routing in multistage networks, show that multistage shuffle- exchange networks are the unique networks with both optimal performance and simple routing. finally, square delta networks are shown to have optimal area complexity.  clyde p. kruskal marc snir
a parallel pipelined data flow coprocessor  a parallel pipelined data flow coprocessor has been developed for the 68000 based commodore amiga workstation. the coprocessor, based on nippon electric corporation's μpd7281 image pipelined processor (impp), was designed as an algorithm processor for numerically intensive applications such as image processing, image synthesis, and numerical analysis. the coprocessor can accomodate up to seven of the 5-mips impp's providing over 30 mips of processing power to dedicated tasks. the impp's act as true coprocessor's providing a multi-processor arrangement consisting of the 68000 and the coprocessor's parallel pipeline. the workstation and parallel processors share all system resources including memory and peripherals. the coprocessor has its own dma capabilities for transferring program code and data between the workstation and the pipeline. the coprocessor is completely programmable via a development environment running native on the amiga, including an assembler, a simulator, and a runtime library. additional programming tools are also being developed.  j. t. canning r. miner
personal imaging and lookpainting as tools for personal documentary and investigative photojournalism  a means and apparatus for covert capture of extremely high-resolution photorealistic images is presented. the apparatus embodies a new form of user- interface -- instead of the traditional "point and click" metaphor which was thought to be the simplest photography had to offer, what is proposed is a "look" metaphor in which images are generated through the natural process of looking around, in a manner that does not require conscious thought or effort. these "lookpaintings" become photographic/videographic memories that may, at times, exceed the quality attainable with even large and cumbersome professional photographic film cameras, yet they may be captured through a device that resembles ordinary sunglasses. the method is based on long-term psychophysical adaptation using a covert sunglass-based reality-mediating apparatus, together with two new results in image processing. the first new result is a means of estimating the true projective coordinate transformation between successive pairs of images, and the second is that of estimating, to within a single unknown scalar constant, the quantity of light arriving at the image plane. furthermore, what is captured is more than just a picture. the resulting environment map may be explored by one or more remote participants who may also correspond and interact with the wearer during the actual shooting process, giving rise to computer supported collaborative (collective) photography, videography, shared photographic/videographic memory, etc.  steve mann