waashk/acm huggingface dataset:
architectural tradeoffs in the design of mips-x  the design of a risc processor requires a careful analysis of the tradeoffs that can be made between hardware complexity and software. as new generations of processors are built to take advantage of more advanced technologies, new and different tradeoffs must be considered. we examine the design of a second generation vlsi risc processor, mips-x.  mips-x is the successor to the mips project at stanford university and like mips, it is a single-chip 32-bit vlsi processor that uses a simplified instruction set, pipelining and a software code reorganizer. however, in the quest for higher performance, mips-x uses a deeper pipeline, a much simpler instruction set and achieves the goal of single cycle execution using a 2-phase, 20 mhz clock. this has necessitated the inclusion of an on-chip instruction cache and careful consideration of the control of the machine. many tradeoffs were made during the design of mips-x and this paper examines several key areas. they are: the organization of the on-chip instruction cache, the coprocessor interface, branches and the resulting branch delay, and exception handling. for each issue we present the most promising alternatives considered for mips-x and the approach finally selected. working parts have been received and this gives us a firm basis upon which to evaluate the success of our design.  p. chow m. horowitz
design of a high-performance atm firewall  a router-based packet- filtering firewall is an effective way of protecting an enterprise network from unauthorized access. however, it will not work efficiently in an atm network because it requires the termination of end-to- end atm connections at a packet-filtering router, which incurs huge overhead of sar (segmentation and reassembly). very few approaches to this problem have been proposed in the literature, and none is completely satisfactory. in this paper we present the hardware design of a high-speed atm firewall that does not require the termination of an end-to-end connection in the middle. we propose a novel firewall design philosophy, called quality of firewalling (qof), that applies security measures of different strength to traffic with different risk levels and show how it can be implemented in our firewall. compared with the traditional firewalls, this atm firewall performs exactly the same packet- level filtering without compromising the performance and has the same "look and feel" by sitting at the chokepoint between the trusted atm lan and untrusted atm wan. it is also easy to manage and flexible to use.  jun xu mukesh singhal
pre-allocation media access control protocols for multiple access wdm photonic networks  media access control protocols for an optically interconnected star-coupled system with pre-allocated wdma channels are introduced and compared. the photonic network is based on a passive star- coupled wdm--based configuration with high topological connectivity and low complexity. the channels are pre- allocated to the nodes with this approach, where each node has a home channel that it uses either for all data packet transmissions or all data packet receptions. a home channel may be shared if the number of nodes exceeds the number of channels in the system. this approach does not require both tunable transmitters and tunable receivers. the performance of a generalized random access protocol is compared to a protocol based on interleaved time multiplexing. both protocols are designed to operate in a multiple-channel multiple-access environment and require each node to possess a tunable transmitter and a fixed (or slow tunable) receiver. semi-markov analytic models are developed to investigate the performance of the two protocols. the analytic models are validated through simulation and performance is evaluated in terms of network throughput and packet delay with variations in system parameters.  krishna m. sivalingam kalyani bogineni patrick w. dowd
a distributed mechanism for power saving in ieee 802.11 wireless lans the finite battery power of mobile computers represents one of the greatest limitations to the utility of portable computers. furthermore, portable computers often need to perform power consuming activities, such as transmitting and receiving data by means of a random-access, wireless channel. the amount of power consumed to transfer the data on the wireless channel is negatively affected by the channel congestion level, and significantly depends on the mac protocol adopted. this paper illustrates the design and the performance evaluation of a new mechanism that, by controlling the accesses to the shared transmission channel of a wireless lan, leads each station to an optimal power consumption level. specifically, we considered the standard ieee 802.11 distributed coordination function (dcf) access scheme for wlans. for this protocol we analytically derived the optimal average power consumption levels required for a frame transmission. by exploiting these analytical results, we define a power save, distributed contention control (ps-dcc) mechanism that can be adopted to enhance the performance of the standard ieee 802.11 dcf protocol from a power saving standpoint. the performance of an ieee 802.11 network enhanced with the ps-dcc mechanism has been investigated by simulation. results show that the enhanced protocol closely approximates the optimal power consumption level, and provides a channel utilization close to the theoretical upper bound for the ieee 802.11 protocol capacity. in addition, even in low load situations, the enhanced protocol does not introduce additional overheads with respect to the standard protocol. luciano bononi marco conti lorenzo donatiello
consistency management in deno  we describe a new replicated - object protocol designed for use in mobile and weakly - connected environments. the protocol differs from previous protocols in combining epidemic information propagation with voting, and in using fixed per - object currencies for voting. the advantage of epidemic protocols is that data movement only requires pair - wise communication. hence, there is no need for a majority quorum to be available and simultaneously connected at any single time. the protocols increase availability by using voting, rather than primary - copy or primary - commit schemes. finally, the use of per - object currencies allows voting to take place in an entirely decentralized fashion, without any server having complete knowledge of group membership. we show that currency allocation can be used to implement diverse policies. for example, uniform currency distributions emulate traditional voting schemes, while allocating all currency to a single server emulates a primary - copy scheme. we present simulation results showing both schemes, as well as the performance advantages of using currency proxies to temporarily reallocate currency during planned disconnections. furthermore, we discuss an initial design of the underlying replicated - object system and present a basic api.  peter j. keleher ugur cetintemel
supporting service discovery, querying and interaction in ubiquitous computing environments  future computing environments will consist of a wide range of network based appliances, applications and services interconnected using both wired and wireless networks. in order to encourage the development of applications in such environments and remove the need for complex administration and configuration tasks, researchers have recently developed a range of service discovery and interaction platforms. examples of such platforms include slp, havi, upnp and jini. while these platforms share a number of common attributes, they each have distinguishing features and hence future networked environments are likely to present developers with a heterogeneous environment composed of multiple specialised support platforms. however, careful analysis of these platforms reveals shortcomings that we believe will inhibit the development of applications that exploit service rich environments. in this paper we discuss these shortcomings and propose a new unifying architecture that brings together the advantages of current service discovery and interaction technologies and provides a new api that we consider to be better suited to the development of service based applications. this work is specifically targeted towards mobile environments, where applications will be required to interact with a wide range of services and devices with minimal user intervention.  adrian friday nigel davies elaine catterall
concert: design of a multiprocessor development system  concert is a shared-memory multiprocessor testbed intended to facilitate experimentation with parallel programs and programming languages. it consists of up to eight clusters, with 4-8 processors in each cluster. the processors in each cluster communicate using a shared bus, but each processor also has a private path to some memory. the novel feature of concert is the ringbus, a segmented bus in the shape of a ring that permits communication between clusters at relatively low cost. efficient arbitration among requests to use the ringbus is a major challenge, which is met by a novel hardware organization, the criss-cross arbiter. simulation of the concert ringbus and arbiter show their performance to lie between that of a crossbar switch and a simple shared intercluster bus.  r. r. halstead t. l. anderson r. b. osborne t. l. sterling
an efficient routing control for the sigma network (4)  when processing vectors on simd computers, the interconnection network may become the bottleneck for performances if it lacks an efficient routing control unit. in the pass, many multistage networks have been designed, but general algorithms to control them cannot be used at execution time : they are too time consuming. this has led many manufacturers to use crossbar networks in the design of simd computers. in [se84a],[se84b], we defined the sigma network (n) and we gave realistic algorithms to control it for performing families of permutations covering standard needs in vector processing. here, we expose the design of a very efficient control unit for the sigma network (4) (16 entries, 16 exits).  a. seznec
performance analysis using the mips r10000 performance counters  tuning supercomputer application performance often requires analyzing the interaction of the application and the underlying architecture. in this paper, we describe support in the mips r10000 for non-intrusively monitoring a variety of processor events -- support that is particularly useful for characterizing the dynamic behavior of multi-level memory hierarchies, hardware-based cache coherence, and speculative execution. we first explain how performance data is collected using an integrated set of hardware mechanisms, operating system abstractions, and performance tools. we then describe several examples drawn from scientific applications that illustrate how the counters and profiling tools provide information that helps developers analyze and tune applications.  marco zagha brond larson steve turner marty itzkowitz
mobile networking in the internet  computers capable of attaching to the internet from many places are likely to grow in popularity until they dominate the population of the internet. consequently, protocol research has shifted into high gear to develop appropriate network protocols for supporting mobility. this introductory article attempts to outline some of the many promising and interesting research directions. the papers in this special issue indicate the diversity of viewpoints within the research community, and it is part of the purpose of this introduction to frame their place within the overall research area.  charles e. perkins
throughput in a counterflow pipeline processor the counterflow pipeline processor, or cfpp, is a unique form of pipelined risc architecture whose goal is to obtain regular and modular performance from a bi-directional pipeline. in this pipeline, instructions and results move in opposite directions in a counterflow fashion. a basic synchronous model of the cfpp was created and used to study configuration options which affect the flow of instructions and results through the pipeline. these options, which varied instruction execution, pipeline movement arbitration, and result movements, were varied in order to find the configuration which maximized throughput for a set of benchmarks. aimee severson brent nelson
development of a tcp/ip for the ibm/370  this paper describes the design and implementation decisions that have been made in developing software to support the darpa tcp/ip protocols for the ibm os/370 environment at the university of california division of library automation. the implementation is designed to support over 100 concurrent tcp connections, all of which are managed by a single program, which acts as a specialized sub-operating system. the system is optimized for line-by-line or screen-by-screen terminal traffic rather than character-by-character traffic. in addition, this tcp is designed to exploit the availability of the large main storage and processor speed available on the ibm/370.  tcp/ip is generally considered to be a mature protocol specification; however, in the course of our implementation we found several parts to be either ambiguous or problematic \--- in particular, error handling and notification, icmp and its relationship to other protocols, and synchronization of data flow with tcp callers.  we also discuss problems encountered in trying to replace hardwired terminals in a public access environment with tcp and telnet, and some protocol changes that would make these protocols more hospitable to our environment.  robert k. brandriff clifford a. lynch mark h. needleman
x.75 internetworking of datapac and telenet  in 1980, agreement was reached by ccitt defining a standard for the interconnection of public data networks. as a result, networks have been able to proceed with the establishment of international services using ccitt recommendation x.75. this paper discusses the methodology used and the operating experience gained by the introduction of an x.75 interface between the gte telenet and datapac public packet switching networks.  mehmet s. unsoy theresa a. shanahan
distributed reconfiguration of metamorphic robot chains  the problem we address is the distributed reconfiguration of a metamorphic robotic system composed of any number of two dimensional hexagonal modules from specific initial to specific goal configurations. we present a distributed algorithm for reconfiguring a straight chain of hexagonal modules at one location to any intersecting straight chain configuration at some other location in the plane. we prove our algorithm is correct, and show that it is either optimal or asymptotically optimal in the number of moves and asymptotically optimal in the time required for parallel reconfiguration. we then consider the distributed reconfiguration of straight chains of modules to a more general class of goal configurations.  jennifer e. walter jennifer l. welch nancy m. amato
an unslotted multichannel channel-access protocol for distributed direct- sequence networks  a multichannel reservation-based channel-access protocol is investigated in this paper. the available system bandwidth is divided into distinct frequency channels. under the protocol, one channel (the control channel) is used to exchange reservation messages and the remaining channels (the traffic channels) are used for information-bearing traffic. the performance of this scheme is compared to that of a single-channel reservation-based protocol. a simple contention-based slotted-aloha protocol is also considered. performance results take into account the effects of multiple-access interference on acquisition and packet errors. results show that the reservation-based approach is advantageous under conditions of high traffic. in addition, a pacing mechanism that mitigates multiple-access interference and promotes fairness is described, and results are presented that demonstrate its effectiveness.  arvind r. raghavan carl w. baum
the gould np1 system interconnecting  the gould np1 is a multicomputer multiprocessing system designed for high performance and parallel processing required in diverse scientific and engineering applications. the np1's basic building block is a dual-processor single bus system which can be expanded up to eight processors over four system buses.  this paper discusses the overall design and implementation of tne np1 system interconnection in particularly the inter-system bus link which interconnects four system buses to form a tightly coupled eight processor system. such interconnectivity provides np1 the flexibility in system expansion capable of addressing full four gigabytes of physical memory with the least communications delay.  index terms - gould np1, dual-cpu, multiprocessor, processor farm, inter- system bus link.  d. j. vianney j. h. thomas v. rabaza
sensitivity analysis of reliability and performability measures for multiprocessor systems  traditional evaluation techniques for multiprocessor systems use markov chains and markov reward models to compute measures such as mean time to failure, reliability, performance, and performability. in this paper, we discuss the extension of markov models to include parametric sensitivity analysis. using such analysis, we can guide system optimization, identify parts of a system model sensitive to error, and find system reliability and performability bottlenecks.  as an example we consider three models of a 16 processor. 16 memory system. a network provides communication between the processors and the memories. two crossbar-network models and the omega network are considered. for these models, we examine the sensitivity of the mean time to failure, unreliability, and performability to changes in component failure rates. we use the sensitivities to identify bottlenecks in the three system models.  j. t. blake a. l. reibman k. s. trivedi
a product location framework for mobile commerce environment  recent advances in wireless networking, mobile technologies, and applications have led to the emergence of mobile commerce. as many of these applications require location tracking of products, users, and services, support for location management has become a major issue in m-commerce. although some progress has been made in adding location support in business to consumer (b2c) m-commerce, very little work has been done towards addressing these issues in the business to business (b2b) environment. in this paper, we discuss location management and present a new location-aware framework for b2b m-commerce environment.  karlene cousins upkar varshney
the effect of mobile ip handoffs on the performance of tcp  mobile ip is a standard for handling routing for hosts that have moved from their home network. this paper studies the costs of the mobile ip handoff that occurs when a mobile host moves between networks. experiments were carried out with mobile ip and tcp over varying network conditions to observe the effect of handoffs on the transmission. this paper shows that although mobile ip may be appropriate for current applications, its long handoff periods make it unsuitable for the future.  anne fladenmuller ranil de silva
a workload characterization pipeline for models of parallel systems  the same application implemented on different systems will necessarily present different workloads to the systems. characterizations of workloads intended to represent the same application, but input to models of different systems, must also differ in analogous ways. we present a hierarchical method for characterizing a workload at increasing levels of detail such that every characterization at a lower level still accurately represents the workload at higher levels.  we discuss our experience in using the method to feed the same application through a workload characterization "pipeline" to two different models of two different systems, a conventional relational database system and a logic-based distributed database system. we have developed programs that partially automate the characterization changes that are required when the system to be modeled changes.  william alexander tom w. keller ellen e. boughter
a robust, optimization-based approach for approximate answering of aggregate queries  the ability to approximately answer aggregation queries accurately and efficiently is of great benefit for decision support and data mining tools. in contrast to previous sampling-based studies, we treat the problem as an _optimization_ problem whose goal is to minimize the error in answering queries in the given workload. a key novelty of our approach is that we can tailor the choice of samples to be robust even for workloads that are "similar" but not necessarily identical to the given workload. finally, our techniques recognize the importance of taking into account the variance in the data distribution in a principled manner. we show how our solution can be implemented on a database system, and present results of extensive experiments on microsoft sql server 2000 that demonstrate the superior quality of our method compared to previous work.  surajit chaudhuri gautam das vivek narasayya
very long instruction word architectures and the eli-512  by compiling ordinary scientific applications programs with a radical technique called trace scheduling, we are generating code for a parallel machine that will run these programs faster than an equivalent sequential machine---we expect 10 to 30 times faster.  trace scheduling generates code for machines called very long instruction word architectures. in very long instruction word machines, many statically scheduled, tightly coupled, fine- grained operations execute in parallel within a single instruction stream. vliws are more parallel extensions of several current architectures.  these current architectures have never cracked a fundamental barrier. the speedup they get from parallelism is never more than a factor of 2 to 3. not that we couldn't build more parallel machines of this type; but until trace scheduling we didn't know how to generate code for them. trace scheduling finds sufficient parallelism in ordinary code to justify thinking about a highly parallel vliw.  at yale we are actually building one. our machine, the eli-512, has a horizontal instruction word of over 500 bits and will do 10 to 30 risc-level operations per cycle [patterson 82]. eli stands for enormously longword instructions; 512 is the size of the instruction word we hope to achieve. (the current design has a 1200-bit instruction word.)  once it became clear that we could actually compile code for a vliw machine, some new questions appeared, and answers are presented in this paper. how do we put enough tests in each cycle without making the machine too big? how do we put enough memory references in each cycle without making the machine too slow?  joseph a. fisher
error control schemes for networks: an overview  in this paper, we investigate the issue of error control in wireless communication networks. we review the alternative error control schemes available for providing reliable end-to-end communication in wireless environments. through case studies, the performance and tradeoffs of these schemes are shown. based on the application environments and qos requirements, the design issues of error control are discussed to achieve the best solution.  hang liu hairuo ma magda el zarki sanjay gupta