waashk/acm huggingface dataset:
a formal protocol conversion method  the need for the protocol conversion has been recognized with the proliferation of heterogeneous networks. from a formal viewpoint, we regard that problem as generating a protocol which satisfies the properties of the conversion. in this paper, we prove that, one can determine whether a converter exists, for some protocol classes, given protocols in the form of communicating finite automata, moreover, we give a construction method for such a converter for those classes, and derive an upper bound of the computational complexity of the construction algorithm.  k okumura
telescience and advanced technologies  space station and its associated laboratories, coupled with the availability of new computing and communications technologies, have the potential of significantly enhancing scientific research. telescience involves the interaction of scientific researchers and equipment on earth with on-board personnel and equipment as well as with other researchers, remote ground-based resources, mission control personnel, and space station developers. to assure that this potential is met, scientists and managers associated with the space station project must gain significant experience with the use of these technologies for scientific research, and this experience must be fed into the development process for space station.  in this talk, a pilot program is described that is attempting to address this problem. university researchers are conducting rapid prototyping testbeds employing new telescience technologies and ideas. these testbeds are specific research experiments within the scientific discipline areas that will use space station laboratories. the experiments are being carried out in a coordinated manner to allow the critical questions to be answered by groups of scientists working with technologists in a rapid prototyping testbed environment.  the rapid prototyping testbeds are not like a typical testbed. rather than being used to evaluate and integrate systems on the way to deployment, the rapid prototyping testbeds constitute a technology evaluation environment (tee), allowing users to interact with advanced technologies in the conduct of scientific research in order to develop the required base of experience to permit development and evaluation of requirements and specifications.  b. m. leiner
an efficient communication protocol for high-speed packet-switched multichannel networks  this paper proposes a new media-access protocol for high-speed packet-switched multichannel networks based on a broadcast topology, for example, optical passive star networks using wavelength-division multiple access. the protocol supports connection-oriented traffic with or without bandwidth reservation as well as datagram traffic, in an attempt to integrate transport-layer functions with the media-access layer. it utilizes the bandwidth efficiently while keeping the processing requirements low by requiring stations to compute their transmission and reception schedules only at the start and end of each connection. a simple analysis shows that we can achieve low blocking probabilities for connections, as well as high network throughput.  pierre a. humblet rajiv ramaswami kumar n. sivarajan
a path-oriented routing strategy for packet switching networks with end-to-end protocols  a path-oriented routing strategy is proposed for packet switching networks with end-to-end internal protocols. it allows switch pairs to communicate over multiple paths (for better network throughput), while maintaining knowledge of user connections at the network's endpoints only. the most significant aspect of this strategy lies in its flow assignment method. a distributed loop-free shortest path algorithm assigns a number to a path at the time it is created and this number remains valid through shortest path changes. consequently, existing traffic can be maintained on existing paths, while new traffic is assigned to the current shortest paths. stable multiple path routing is thus achieved without packet disordering. abnormal conditions such as trunk failure and recovery and trunk congestion are dealt with by tagging routing updates with update causes. simulation of this routing strategy shows that maximum network throughput (under a certain congestion constraint) can be increased substantially compared to a single path routing strategy.  r. aubin p. ng
wisq: a restartable architecture using queues  in this paper, the wisq architecture is described. this architecture is designed to achieve high performance by exploiting new compiler technology and using a highly segmented pipeline. by having a highly segmented pipeline, a very-high-speed clock can be used. since a highly segmented pipeline will require relatively long pipelines, a way must be provided to minimize the effects of pipeline bubbles that are formed due to data and control dependencies. it is also important to provide a way of supporting precise interrupts. these goals are met, in part, by providing a reorder buffer to help restore the machine to a precise state. the architecture then makes the pipelining visible to the programmer/compiler by making the reorder buffer accessible and by explicitly providing that issued instructions cannot be affected by immediately preceding ones. compiler techniques have been identified that can take advantage of the reorder buffer and permit a sustained execution rate approaching or exceeding one per clock. these techniques include using trace scheduling and providing a relatively easy way to "undo" instructions if the predicted branch path is not taken. we have also studied ways to further reduce the effects of branches by not having them executed in the execution unit. in particular, branches are detected and resolved in the instruction fetch unit. using this approach, the execution unit is sent a stream of instructions (without branches) that are guaranteed to execute.  a. r. pleszkun j. r. goodman w. c. hsu r. t. joersz g. bier p. woest p. b. schechter
fragmentation considered harmful  internetworks can be built from many different kinds of networks, with varying limits on maximum packet size. throughput is usually maximized when the largest possible packet is sent; unfortunately, some routes can carry only very small packets. the ip protocol allows a gateway to fragment a packet if it is too large to be transmitted. fragmentation is at best a necessary evil; it can lead to poor performance or complete communication failure. there are a variety of ways to reduce the likelihood of fragmentation; some can be incorporated into existing ip implementations without changes in protocol specifications. others require new protocols, or modifications to existing protocols.  c. a. kent j. c. mogul
performance analysis of a synchronous, circuit-switched interconnection cached network  in many parallel applications, each computation entity (process, thread etc.) switches the bulk of its communication between a small group of other entities. we call this phenomenon switching locality. the interconnection cached network (icn) is a reconfigurable network especially suited for exploiting switching locality. it consists of many small, fast crossbars interconnected by a large, slow switching crossbar. the large crossbar is used for topology reconfiguration and the smaller crossbars for circuit switching. for a large class of communication patterns displaying switching locality (this includes meshes, tori, trees, rings, pyramids, etc.), it is possible to choose appropriate icn configurations and assignments of processes to processors such that all communication paths pass through two or less switching components.  much of the previous work on performance analysis of networks has assumed random, uniformly distributed communication and is inapplicable to many real- life parallel applications that lack this uniformity. we develop a methodology to analyze the performance of synchronous, circuit switched networks under different communication traffic patterns. we employ this methodology to study the performance of the icn in comparison to more popular reconfigurable networks: the delta and the crossbar. we choose two different communication patterns---a 2-d torus representing a high degree of switching locality and a fully connected graph representing complete absence of such locality. we show that in the presence of locality, the icn comes very close to matching the crossbar's performance. this, together with the shorter network cycle period of the icn, makes it more desirable. in the absence of switching locality, the reconfigurability of the icn allows for a graceful degradation in performance.  vipul gupta eugen schenfeld
performance prediction for the horizon super computer  the performance of one horizon processing element can be quantified by user operations per instruction, the instructions per tick, and the basic clock rate. assuming there is sufficient parallelism within a problem, the performance of one pe can be multiplied by the number of pes contained in the horizon system. for a 256-pe horizon the expected sustained performance is in the order of 50 giga user operations per second for problems with sustained parallelism of 8,000 to 12,000 instruction streams.  r. r. glenn
on the performance of bandwidth allocation strategies for interconnecting atm and connectionless networks using atm networks as the switching fabric for interconnecting lans and mans means that a strategy for bandwidth allocation must be developed to map connectionless traffic in the lan/man to the atm network which is essentially connection-oriented. this paper presents a bandwidth allocation algorithm based on bandwidth advertising and burst drop when overflow occurs. the performance is evaluated by simulation and shown to reduce burst loss rate significantly. edward chan victor c. s. lee jim m. ng
performance analysis of local communication loops  the communication loops analyzed here provide an economic way of attaching many different terminals which may be some kilometers away from a host processor. main potential bottlenecks were found to be the loop transmission speed, the loop adapter processing rate, and the buffering capability, all of which are analyzed in detail. the buffer overrun probabilities are found by convolving individual buffer usage densities and by summing over the tail-end of the obtained overall density function. examples of analysis results are given.  kuno m. roehr horst sadlowski
practical trade-offs for open interconnection  there is increasing market pressure to provide support for the open interconnection of systems via general purpose protocol suites such as osi and tcp/ip. the complexity of these protocols means that the achievement of acceptable performance is not easy. indeed, some would claim it is impossible, and advocate lean, closed protocols. a further aspect of communications architectures in the world outside the research laboratory is that they must be well structured and modular, in order to meet the needs of orderly systems development and the provision of configurable products. this paper examines the trade-offs between these three aspects of protocol stack development: conformance to standards, reasonable performance and modularity. it finds that while a considerable amount of work has been carried out in recent times, it is apparent that we do not know yet how to achieve all three.  michael fry
the i860tm 64-bit supercomputing microprocessor  the intel i860tm processor is a risc-based microprocessor incorporating a risc core with memory management, a floating point unit, and caches on a single chip. the 1,000,000 transistors allow a single chip implementation with highly optimized interunit communication and wide internal data buses. the parallelism and pipelining between the execution units, and the innovative cache management techniques are under explicit control of software. vectorizable applications can use the pipelined adder and multiplier units to achieve up to 80 mflops at 40 mhz for the inner loops of common calculations. special instructions allow using the data cache as a flexible vector register and support high data bandwidth from main memory. finally, to support visualization of data, special hardware for 3d graphics is included.  l. kohn n. margulis
evaluation of a fault tolerant distributed broadcast algorithm in hypercube multicomputers  this paper performs a detailed evaluation of a fault- tolerant distributed broadcasting algorithm for cube connected networks. the main areas of evaluation are the following: (1) algorithm effectiveness in the presence of multiple faults, (2) establishing the maximum number of link faults allowed, before the algorithm fails to guarantee 100% effectiveness. the evaluation was done to networks connected in 3-, 4-, 5-, and 6-cube configurations. the results of the simulation were analyzed to establish algorithm characteristics under multiple faults.  jace w. krull jie wu andres m. molina
the current status of map  map is a standard computer networking discipline and a unified set of communications protocols which make it possible to implement a vendor independent network of computers. map provides a complete service to the user or application program. the major facilities, file transfer, process to process messaging, inter-machine messaging, and directory service are supported. virtual terminal protocol support is planned for the near future.  map is a subset of the internationally agreed open systems interconnection computer networking architecture, protocols and supporting standards. the map subset of osi protocols was originally selected by general motors and has been agreed by a map task force comprised of nearly 100 user and vendor corporations. map specifications are also agreed by the nbs/osi implementor's workshop, indicating that the map specifications are osi compatible.  the map system and protocols are described here in sufficient detail to permit the reader to gain a general understanding of map against a background of osi fundamentals. the future growth trends for map conclude this paper.  j s foley y weon- yoon
effects of building blocks on the performance of super-scalar architecture  the inherent low level parallelism of super-scalar architectures plays an important role in the processing power provided by these machines: independent functional units promote opportunities for executing several machine operations simultaneously. from the viewpoint of the hardware designer it is very important to assess the influence of each functional unit, and the way they communicate, on the overall performance of the machine. particularly, it is highly desirable to determine an upper bound in the number of additional functional units which give significant performance improvement ratios.  this work describes experiments that have been carried out to assess the effect of alternative instruction issue mechanisms, multiple functional units, instruction queues, common data bus and other hardware solutions on the performance of super-scalar machines. the assessment was obtained by interpreting non optimized object code fo an actual processor on some basic machine models. the paper outline the main aspects of the research, and shows that speed-up ratios of up to 3.35 times were observed during the interpretation of benchmark programs.  edil s. t. fernandes fernando m. b. barbosa
the convex c240 architecture  the c240, a tightly coupled, shared memory, parallel/multi-processor, supports up to 4, 40-nanosecond ecl/cmos cray-like processors. managed by a fully semaphored unix operating the c240, it can support up to 4 gigabytes of directly addressable physical memory. convex proprietary compiler technology provides automatic vectorization and parallelization for fortran, c, and ada. allocation of parallel threads to physical processors is managed by an innovation approach asap (automatic self- allocating processors). asap dynamically allocates and deallocates parallel threads to the processors.  in creating a second generation supercomputer, several factors were considered prior to commencing design. among these factors are:  performance - scalar/vector/parallel.  parallel processing efficiency.  semiconductor technology.  compiler optimization strategies.  with these factors in mind, the c240 system evolved. the salient features of the c240 are:  tightly coupled, mimd processor system. where each processor, up to 4, is a general purpose scientific processor, with a 4 gigabyte virtual address space. operands are addressed at the byte level.  each processor is a 40 nanosecond, ecl/cmos implementation of the convex c1, cray-like, instruction set architecture (see wallach 85). additional instructions were added, in a super-set manner using pre-existing spare opcodes. these instructions provide vector conversions, vector shifts, vector square root, and fully pipelined operations under mask. additional scalar instructions were added mainly in the area of intrinsics: sin, cos, etc.  a set of parallel processing instructions was also added and will be discussed in more detail later.  a very high bandwidth, 800 mbytes/sec, multiported memory system capable of supporting up to 4 gigabytes of directly addressable physical memory.  revisions of convex's proprietary compiler technology that support automatic parallelism for fortran, c and ada.  a fully semaphored unix kernel. the unix kernel was modified extensively to support multiple simultaneous system calls to different resources and the management of convex's parallel processing paradigm.  lastly, a new and innovative concept for the allocation and scheduling of parallel processes and threads is supported. this unique concept, asap, (automatic self-allocating processors), is a distributed mechanism that permits physical processors to dynamically associate and disassociate themselves from an executing process.  m. chastain g. gostin j. mankovich s. wallach
editorial  it has been a pleasure to undertake the guest-editorship in putting together this special issue of wireless networks. the reason is that it has provided the opportunity to acquaint the wireless networking community with the emerging importance of satellite systems as parts of future wireless networks. in fact, more broadly, the hybrid use of satellites and terrestrial communication resources, wireless or not, is emerging as a practical and efficient way of organizing the world's communication infrastructure. and, it has been so that the development of satellite communications has been traditionally somewhat separated from the development of terrestrial wireless communications and especially from that of communication networks. this issue contributes toward bridging this gap.  a. ephremides f. vatalaro
an analysis model on nonblocking multirate broadcast networks  designing efficient interconnection networks with powerful connecting capability remains a key issue to parallel and distributed computing systems. many progresses have been made in nonblocking broadcast networks which can realize all one-to-many connections between any network input port and a set of output ports without any disturbance (that is, rearrangement) of other existing connections. however, all results obtained so far for broadcast networks are for the circuit switching or single rate communication model. meanwhile, there have been growing interests in large networks operated in a packet switching manner. this type of network can be modeled as a multirate network wherein a single link can be shared by multiple connections with arbitrary data rate. previous work has been done on the blocking behavior of multirate one-to-one connection or permutation networks. however, yet very little is known about the behavior of multirate one-to-many connection or broadcast networks. in this paper, we will determine nonblocking conditions for v(m,n< ;subscrpt>1,r1,n2,r2) networks under which any multirate broadcast connection request from a network input port to a set of network output ports can be satisfied without any disturbance of the existing connection in the network. our results show that more general multirate broadcast networks can be constructed in the same order of hardware complexity as the best available single rate nonblocking broadcast networks. our proofs for the theorems also imply an efficient routing algorithm for such networks. multirate broadcast networks can provide strong support for parallel and distributed computing systems which require to broadcast multirate data in a random-access environment.  yuanyuan yang
mapping data flow programs on a vlsi array of processors  with the advent of vlsi, relatively large processing arrays may be realized in a single vlsi chip. such regularly structured arrays take considerably less time to design and test, and fault-tolerance can easily be introduced into them. however, only a few computational algorithms which can effectively use such regular arrays have been developed so far.  we present an approach to mapping arbitrary algorithms, expressed as programs in a data flow language, onto a regular array of data-driven processors implemented by a number of vlsi chips. each chip contains a number of processors, interconnected by a set of regular paths, and connected to processors in other similar chips to form a large array. this array is thus tailored to perform a specific computational task, as an attached processor in a larger system.  the data flow program is first translated into a graph representation, the data flow graph, which is then mapped onto a finite but (theoretically) unbounded array of identical processors. each node in the graph represents an operation which can be performed by an individual processor in the array. therefore, the mapping operation consists of assigning nodes in the graph to processors in the array, and defining the connections between the processors according to the arcs in the graph. the last step consists of partitioning the unbounded array into a number of segments, to account for the number of processors which fit in a single vlsi chip.  b. mendelson g. m. silberman
a cdma-based radio interface for third generation mobile systems  this paper deals with the use of a cdma-based radio interface in third generation mobile systems (universal mobile telecommunications system---umts, and future public land mobile telecommunications system---fplmts). the paper is not intended as a detailed analysis of the radio interface performance, but as an overview of the main issues arising in a typical cdma-based mobile system, discussing the different available technical solutions. first of all, the basic requirements of the radio interface in a third generation mobile system are outlined. in particular, the support of variable bit rate transmission, the adaptability to the different propagation and service environments and the flexibility are felt to be important topics to be discussed. then, the main characteristics of the cdma access technique are depicted, in relation with the above mentioned requirements, focusing in particular on the ds-cdma radio interface designed within the race ii---codit project. in that context the paper describes some of the technical solutions proposed for the provision of advanced features such as macrodiversity, multibearer transmission and variable bit rate services.  sergio barberis ermanno berruto