{"title": "SoC DRAM Memory Subsystem Validation Engineering Program Manager", "summary": "Come and join the team that crafted the M3/M4! Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years and very significant R&D spending. To make the best use of those employees, time, and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life\u2019s best work in this rare opportunity to help define the next big thing that will surprise and delight the world!", "description": "\u2022 Work on an impactful EPM team responsible for driving technical issue resolution to enable timely silicon to meet daring product schedules.\n\u2022 Make detailed program level plans for memory feature roll-out and align multi-functional teams on the support and validation plans.\n\u2022 Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware and Software.\n\u2022 Drive debug activities in post silicon environments, root-cause problems, and steer the team to the best corrective action to move forward.\n\u2022 Focused issue reporting, bug tracking, organizing and reporting of program risks and status at an executive level.\n\u2022 Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.\n\u2022 Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities.\n\u2022 Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.\n\u2022 Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.\n\u2022 Enable tight collaboration between Design for Test (DFT), Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.\n\u2022 Drive internal program process to guarantee high quality silicon execution.", "key_qualifications": "", "preferred_qualifications": "Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms.\nExperience shipping high volume DRAMs / SoCs.\nExperience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management\nExcellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure.\nAbility to understand complex technical discussions and extract action plans.\nPassionate to own/drive project development using well-defined metrics.\nThrives in dynamic schedule driven development environment.Ability to succinctly summarize complex details for executive reporting.\nExtraordinary leadership skills and ability to encourage team members with a commitment to see the bigger picture.\nPhenomenal leadership and social skills with a reciprocal approach.\nPrevious experience working with major DRAM memory vendors and validation of DRAM device is also a plus", "education_experience": "", "additional_requirements": "", "pay_benefits": "", "company": "apple"}