{"title": "Physical Design Lead \u2013 Custom Silicon Management", "summary": "Are you a leader and want to apply your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. We are looking for a remarkable Physical Design Lead to work with a highly hardworking Custom Silicon team at Apple to design and develop innovative chips for the coolest products. This position focuses specifically on supporting Physical Design and related activities for the chips.", "description": "You will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community. We value your technical understanding of physical design principles. You will be responsible for ensuring the high quality of the chips.", "key_qualifications": "10+ years of experience in Physical Design of SoCs. 5+ years of experience in leading physical design teams. Proven track record of having taped out a number of complex chips - from gates to GDS. Good knowledge of digital design concepts. Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques. In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification. Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech. Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing. Hands-on experience in Power and Signal Integrity analysis. Ability to debug and fix LVS, DRC, Antenna, ERC issues. Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc. Mixed signal SoC tapeouts involving multiple instances of analog IPs. Low power / leakage management methodology and techniques. Extraction and characterization of IP elements.", "preferred_qualifications": "", "education_experience": "BS and 20 plus years of relevant industry experience (MSEE/PhD in Electrical Engineering Preferred)", "additional_requirements": "25-30% Travel Required", "pay_benefits": "At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $165,500 and $293,800, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple\u2019s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple\u2019s Employee Stock Purchase Plan. You\u2019ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses \u2014 including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.", "company": "apple"}