{"title": "Wireless SoC Design Verification Engineer", "summary": "As part of our team, you will have the opportunity to take the lead on and contribute to verifying a set of complex SOCs. This team will allow you to integrate multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a large scale SOC, different types of SOC architecture, many high speed layered protocols, industry\u2019s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Wireless protocol, FW-HW interactions, complexities of multi-chip SOC debug architecture, etc.", "description": "-  Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe , Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes.\n-  Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.\n-  Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level. \n-  Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design.\n-  Work closely with DV methodology architects to improve verification flow.", "key_qualifications": "Dedicated/hands-on ASIC DV experience\nAdvanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM\nSome experience with formal verification is a plus\nProven track record of working full ASIC cycle from concept to tape-out to bring-up\nExperience taping out large SOC systems with embedded processor cores\nHands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.\nIn-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification\nLow Power Verification experience is a plus\nShould be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges", "preferred_qualifications": "", "education_experience": "BS + 10 years of relevant experience required.", "additional_requirements": "", "pay_benefits": "At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $166,600 and $296,300, and your base pay will depend on your skills, qualifications, experience, and location.\nApple employees also have the opportunity to become an Apple shareholder through participation in Apple\u2019s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple\u2019s Employee Stock Purchase Plan. You\u2019ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses \u2014 including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.\nNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.", "company": "apple"}