{"title": "ASIC Design Engineer \u2013 Fabric/Interconnect", "summary": "Imagine what you could do here. At Apple, phenomenal ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Apple is owning the charge in dedication mobile computing with innovative SOC's announced with each of its revolutionary new product offerings. At the core of all Apple mobile SOC's, is an on-chip system interconnect bus that supplies the SOC agents with their requested load and store data from on chip and off chip memories. With every generation the max bandwidth, the lowest latency, the lowest area, and lowest power requirements are more exacting and require sophisticated planning in order to achieve on Apple's schedules! Be part of the team creating the architecture and design for the on-chip system interconnect bus for next generation Apple SOC's!", "description": "As a member of the SoC Design team, you will be responsible for the following:\n\n-  Analyze architectural requirements of next generation of on-chip fabric and define scalable interconnect components\n-  Coding high-quality RTL, with embedded assertions and cover points.\n-  Writing detailed micro-architectural specifications.\n-  Work with multi-functional team to define and implement logic IP.\n-  Collaborating with multi-functional teams to explore solutions to improve performance while minimizing power and area.\n-  Working closely with design verification and formal verification teams to debug and verify functionality and performance.", "key_qualifications": "Extensive experience in front-end ASIC RTL digital logic design using Verilog or System Verilog\nTight-knit collaboration skills with excellent written and verbal communication skills.\nFamiliar with multiple power domains, multiple clock domains and asynchronous interfaces.\nStrong understanding of flow control, arbitration, on-chip interconnects, QoS, topology, and performance analysis\nExperience implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, logic equivalence checks.\nPower and clock management designs desirable\nFamiliarity on flow automation scripts using Perl, Python, Makefile and shell scripts\nExperience in ASIC IP development using extensive flow automation a plus", "preferred_qualifications": "", "education_experience": "Bachelors degree + 10 years of industry experience is required.", "additional_requirements": "", "pay_benefits": "At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.\n\nApple employees also have the opportunity to become an Apple shareholder through participation in Apple\u2019s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple\u2019s Employee Stock Purchase Plan. You\u2019ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses \u2014 including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.\n\nNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.", "company": "apple"}