{"title": "GPU Top Level Physical Design Engineer", "summary": "Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you\u2019ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You\u2019ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means crafting and building the technology that fuels Apple\u2019s devices. Together, we enable our customers to do all the things they love with their devices! This role requires a mix of strategic engineering along with hands-on, technical work, being responsible for implementing complete chip design from netlist to tapeout and having hands-on experience in physical design and large chip integration.", "description": "\u2022    Collaborate with the FE team to understand chip architecture and drive physical aspects early in the design cycle. \n\u2022    Drive innovation with the physical design team, developing methodologies and \u201cbest known methods\u201d to enable the best-in-class GPU design. \n\u2022    Develop PD guidelines and checklists, drive execution, and supervise progress. Be the focal point for place and route integration at the top level. \n\u2022    Drive the work among PnR engineers to set goals, plan short and long-term work comprehending dependencies between different domains like top, STA, block place and route. \n\u2022    Communicate and drive the needs of PD with multi-functional teams that will enable achieving the goals of the back-end design for the project. \n\u2022    Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution. \n\u2022    If you are a confident problem solver who thrives under pressure to find new, creative solutions, we are excited to hear from you!", "key_qualifications": "Deep experience with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning, and hard IP integration.\nDeep knowledge of GPU issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.\nFamiliar with hierarchical design approach, top-down design, budgeting, timing, and physical convergence.\nDepth of expertise on integrating IP from both internal and external vendors and able to specify and drive IP requirements in the physical domain.\nExperience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.\nFamiliar with various process related design issues including design for yield and manufacturability, multi Vt strategies and thermal Mgt.\nExperience in technical project leadership and generating results that have had an impact on project completion and objectives.\nTrack record of applying creative thinking to strategically solve problems that have an impact on a project, group, or organization.\nConsistent track record in solving complex PD and multi-functional problems, driving results directly and/or leading a team of engineers to innovate and execute extraordinary GPU designs.\nFrom a CAD tool perspective, experience with floorplanning tools, P&R flows, timing verification, and physical design verification flows is required.", "preferred_qualifications": "", "education_experience": "We are looking for candidates with a minimum of BS + 10 years of relevant experience.", "additional_requirements": "", "pay_benefits": "", "company": "apple"}