{"title": "Mixed-Signal Verification Engineer", "summary": "Would you like to join Apple\u2019s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests. You will build and execute test plans to meet project schedule and metric requirements, including coverage metrics.", "description": "- Review specifications, extract features, define and execute verification plan.\n- Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests in a UVM framework.\n- Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks.\n- Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage.\n- Write scripts for automation of flow.\n- Improve Mixed Signal verification methodology.", "key_qualifications": "BS and 3+ years of relevant industry experience.\nIndustry verification experience with RF/Mixed-Signal blocks and SOCs.\nExpertise building Mixed-Signal testbenches, checkers and tests using System Verilog.\nExpertise creating and using real-numbered analog behavioral models in System Verilog/Verilog-AMS.\nExperience in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog) for verification.\nStrong verification skills in problem solving, constrained random testing, and debugging.\nUnderstanding of common analog/RF blocks.\nExperience with signal processing using Python or Matlab is a plus.\nExperience with Virtuoso Composer, ADE, and HED is a plus.\nTeam spirit, excellent communication skills and the desire to take on diverse challenges.", "preferred_qualifications": "", "education_experience": "BS and 3+ years of relevant industry experience.", "additional_requirements": "Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.", "pay_benefits": "At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $135,400 and $250,600, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple\u2019s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple\u2019s Employee Stock Purchase Plan. You\u2019ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses \u2014 including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.", "company": "apple"}