{"title": "GPU Physical Design Engineer, STA/Timing", "summary": "Do you love creating elegant solutions to sophisticated challenges? As part of our Silicon Engineering group, you\u2019ll help design and manufacture our next-generation, high-performance, power-efficient processors! You\u2019ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. In this job, you will be responsible for timing closure of highly complex GPU designs that go in every Apple product and will have amazing opportunities to set new standards for the next generation GPU designs. You will gain exposure to different aspects of product development, from concept to post silicon validation! You will collaborate with a variety of fields including Architecture, RTL, Synthesis, Clocking, DFT, Physical design and Post silicon engineering to ensure the best design practices are followed for a smooth timing convergence.", "description": "-  Lead different STA activities at the same time by working with functional collaborators.\n-  Identify dependencies and roadblocks for different STA items very early on and ensure a smooth execution of timing closure.\n-  Participate in analysis leading to the definition of next generation products.\n-  Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows.\n-  Work with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing.\n-  Setting up all DFT modes and making sure all test features are properly timed.\n-  Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports.\n-  Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure.\n-  Run ECO flows on the design and responsible for close timing.\n-  Drive and support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture.\n-  Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows.\n-  Work with post silicon teams and product engineering for silicon debug activities.", "key_qualifications": "We are looking for candidates with 10+ years of hands-on experience in STA and timing closure, including:\n- Able to lead STA efforts by working with multi-disciplinary teams.\n- Drive to identify different things that can affect timing closure and be proactive to develop solutions.\n- Familiar with STA concepts and good understanding of cross-talk, OCV, noise, etc.\n- Experience with analysis of large volume data, identifying and driving fixes, generating and providing ECOs for timing closure.\n- General knowledge in one or more multi-functional areas like DFT, synthesis, PD, clocking is preferable.\n- Be a strong teammate, good communicator and able to work with others driving timing closure and influencing the best design practices to improve efficiency.\n- Have programming skills with TCL and Primetime APIs. Exposure to Python/Perl would be added advantage.\n- STA lead experience would be an added advantage.", "preferred_qualifications": "", "education_experience": "We are looking for candidates with BS + 10 years of relevant experience.", "additional_requirements": "", "pay_benefits": "", "company": "apple"}