{"title": "ASIC Engineer, Design Verification", "level": "", "location": "Sunnyvale, CA", "description": "Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.\n\nAs a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta\u2019s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.", "salary": "US$136,000/year to US$203,000/year + bonus + equity + benefits", "key_qualifications": "Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.\n\n5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification\n\nTrack record of 'first-pass success' in ASIC development cycles.\n\n5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.\n\nExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.\n\nExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.", "preferred_qualifications": "Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.\n\nExperience in development of UVM based verification environments from scratch.\n\nExperience with Design verification of Data-center applications like Video, AI/ML and Networking designs.\n\nExperience with revision control systems like Mercurial(Hg), Git or SVN.\n\nExperience with verification of ARM/RISC-V based sub-systems or SoCs.\n\nExperience with IP or integration verification of high-speed interfaces like PCIe, DDR, HBM, Ethernet.\n\nExperience working across and building relationships with cross-functional design, model and emulation teams.", "responsibilities": "Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.\n\nDevelop functional tests based on verification test plan.\n\nDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.\n\nDebug, root-cause and resolve functional failures in the design, partnering with the Design team.\n\nCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.\n\nDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.", "company": "meta"}