{"title": "SoC Physical Design Engineer, PnR", "summary": "Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!\n\nIn this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.", "description": "\u2022 Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.\n\u2022 Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.\n\u2022 Timing, physical and electrical verification, and driving the signoff closure for the partitions.\n\u2022 Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.\n\u2022 Drive optimization of PnR partitions, to achieve best Power/Performance/Area.", "key_qualifications": "Minimum BS and 10+ years of relevant industry experience.\nKnowledgeable in partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.\nStrong knowledge of physical design construction and analysis flows and methodology.\nShown ability to adhere to stringent schedule and die size requirements.\nStrong communication skills.\nExperienced with industry standard tools, understanding their capabilities and underlying algorithms.\nExperience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.\nFamiliar with typical SOC issues such as multiple voltage and clock domains and mixed signal block integration.\nFamiliar with various process-related design issues including Design for Yield and Manufacturability and multi-vt strategies.\nFrom a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows.", "preferred_qualifications": "", "education_experience": "Minimum BS and 10+ years of relevant industry experience", "additional_requirements": "", "pay_benefits": "At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.\n\nApple employees also have the opportunity to become an Apple shareholder through participation in Apple\u2019s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple\u2019s Employee Stock Purchase Plan. You\u2019ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses \u2014 including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.\n\nNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.", "company": "apple"}