{"title": "Digital Design Methodology Engineer", "summary": "Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you\u2019ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You\u2019ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you\u2019ll be responsible for crafting and building the technology that fuels Apple\u2019s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with Apple Hardware products. Join us to help deliver the next groundbreaking Apple products. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you join us in crafting solutions that do not yet exist?", "description": "As a team member of the Methodology Design team, you will be involved with all aspects of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Provide innovative solutions to customize and improve quality and efficiency of mixed-signal design. Work with RTL and physical design teams to implement and customize design flows that are optimal for different IPs. Provide documentation, training and new- user-support. Responsible for diagnosis, resolution, regression of reported problems. Generate block/ chip level static timing constraints. Create full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock net work guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing design methodologies for correct by construction designs. Assist in flow development for chip integration.", "key_qualifications": "Typically requires 4+ years experience in Synthesis, PNR and Power/Timing flows development. Understanding and exposure to Low Power Design analysis flows. Understand various aspects of partition level Synthesis and PNR including Power/Timing optimization, CTS, routing and UPF. Understand hierarchical Synthesis and P&R issues is a key (UPF, power-distribution, multi-voltage design). Strong TCL/Perl/Python/Makefile scripting knowledge. Proven track record of managing, and regressing Synthesis, P&R and Power/timing flows. We are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirement.", "preferred_qualifications": "", "education_experience": "BS degree in technical discipline with minimum 3 years of relevant experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.", "additional_requirements": "", "pay_benefits": "", "company": "apple"}