the very reason why there are only bits used for addressing in pae mode is that the very first processor using segmentation to address physical memory where segment register such as cs is bit but referring bit long segments after shifting bits to the left keeping this schema if there were bit real mode then bits used for referring segments bits base address bits for logical addresses but this is not the truth but just a guide to draw the reason why in intel and ia architectures software developer's manual it says m is an abbreviation for maxphyaddr which is at most where m is used in pde pte and ppde without further explanation but i don't believe for amd architecture that would be the extreme limit for the physical addressing if further amd processor gets rid of legacy mode completely then there would potentially bits for addressing physical memory rather than bits like it in itanium architecture that might be wrong but just put a stop to end this topic