A 2.8 pJbit 10 Gbs DelayedPhaseSelect 2bit Pulsewidth Modulator in 45nm SOI CMOS This paper presents the design and characterization of a low output jitter and high resolution pulsewidth modulator in 45nm SOI CMOS. The modulator uses a current mode logic (CML) delay line to generate delayed phases of a reference signal. A digital input vector selects a particular delayed phase inside a CML phase selector. The delayed and undelayed phases of the reference are then combined inside a CML OR gate to generate different pulsewidths. The designed 2bit 10 Gbs CML pulsewidth modulator offers the highest time resolution of 10 ps, least output jitter of 0.6 ps, and among the best energy figures of 2.8 p.Jbit in comparison to the reported pulsewidth modulators.

A patterndependent injectionlocked CDR for clockembedded signaling Abstract   This paper presents a CDR architecture for clockembedded signaling. To suppress the effect of datadependent jitter of the conventional DLLbased approach, we propose a patterndependent injectionlocking scheme in a PLLbased clock recovery circuit. It achieves both benefits of PLL and DLL, the input jitter filtering and the clearance of accumulated VCO jitter, respectively. A jitter analysis is also presented to develop a design strategy for the optimal extraction of injection timing from random data stream. The CDR, implemented in a 28xe2x80xafnm CMOS, achieves a data rate of 12.5xe2x80xafGbs with a 13.7xe2x80xafdBloss channel and verifies the validity of the analysis.