The Digital Front End with Dualbox Digital Predistortion in Alldigital Quadrature Transmitter A digital front end of dualbox digital predistortion (DPD) algorithm for fully digital quadrature transmitter is proposed. The DFE consists of an upsample filter bank, a static digital predistortion and a dynamic digital predistortion. To shorten the setup time of static predistortion a 2D lookup table (LUT) based on profile inversion is implemented as static digital predistortion. An adaptive filter based on least mean square (LMS) algorithm is implemented as dynamic digital predistortion to compensate the memory effect of digital transmitter. The digital transmitter has achieved xe2x88x9241.86dBc ACPR and xe2x88x9227.68dB EVM with 80MHz WLAN. The digital front end (DFE) of a multibit alldigital quadrature RF transmitter is implemented in TSMC 28nm CMOS technology.

Optimization of a pruned 2D Digital Predistortion Model Structure for Power Amplifiers Linearization Twodimensional digital predistortion (2D DPD) is one of the most commonly used approaches to linearize the concurrent dualband radio frequency (RF) power amplifiers (PA). This paper explores the use of a hillclimbing optimization heuristic to determine the optimal structure for 2D DPD. To improve convergence and reduce computation time, we propose a new parameterization for the 2D DPD model. The proposed search criterion is based on the generalized information criterion, which represents the tradeoff between the DPD linearization accuracy in both bands and the model complexity. A comparison against a compressedsensingbased method is also made. The effectiveness of the proposed method is validated with two 20 MHz longtermevolution (LTE) signals on two carriers with 100 MHz frequency separation.