Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture In this paper, the hardware implementation of a burst error channel and a burst erasure channel simulator in Cyclone II Field Programmable Gate Array (FPGA) is proposed. In telecommunication, a burst error channel is a data transmission channel in which errors occur in a contiguous sequence of symbols, such that the first and last symbols are in error and there exists no contiguous subsequence of m correctly received symbols within the error burst. An erasure channel is one in which each transmitted symbol is either received correctly or is corrupted so badly as to be considered erased. When the erasures are clustered together we refer to the channel as a burst erasure channel. Although software simulations are easy to set up to simulate a transmission channel behavior, they are very time consuming. In order to speed up the communication system performance evaluation process and the final parameter optimization design, direct hardware emulation is proposed and presented. The implementation can be easily extended to other FPGA architectures.

ImpulseBased Asynchronous Serial Communication Protocol on Optical Fiber Link for AER Systems We developed an ImpulseBased Asynchronous Serial AddressEvent Representation (IBASAER) protocol. It allows for fullduplex communication and explicit flow control, does not require any clock data recovery or accurate clock relationship between the transmitter and receiver. Moreover, the optical fiber communication link, that galvanically isolates the communicating devices, highly improves the robustness to electromagnetic disturbances, reduces the power consumption and allows for high data rate transmissions. In addition, the proposed implementation does not require any specific hardware and can be developed on lowcost FPGAs as well as on fullcustom ASICs. Preliminary tests performed at 100 Mbps raw bit transfer rate confirm a 32 bit maximum event rate of 2.9 Meps.