A Novel Offset and 1f Noise Compensated SingleSlope ADC with Reduced Hardware Effort Process, voltage, temperature variations (PVT), and noise typically influence the conversion accuracy of an ADC. This work presents a new modular concept for reducing offset, 1f noise, and slope errors in single slope analogtodigital converters (ADCs), advantageously applicable in array structures. The proposed concept combines some analog methods known from chopper amplifier techniques with numerical arithmetics at minimal hardware effort. To increase the conversion speed, an extended concept is proposed, where the converted data are automatically corrected in time after each conversion cycle. Since the ramp generator is also susceptible to PVT fluctuations, the proposed ADC concept can be extended by some calibration options using a bandgap voltage reference. For this work the data of a 180 nm CMOS technology was base and the functionality was verified by nominal and statistical simulations.

An Automatic SlopeCalibrated Ramp Generator for SingleSlope ADCs This paper presents a ramp generator with automatic slope calibration which is able to compensate slope deviation due to process and environmental effects. A novel analog feedback circuit is proposed to regulate the stop voltage in successive approximation while fix the start voltage of the ramp automatically without much calibration code input or complicated auxiliary circuits, which reduces the complexity of circuitry and timing, meanwhile, saves area and power. A 12bit singleslope ADC (SSADC), employing the proposed ramp generator, has been implemented in a 0.11xc2xb5m CMOS process. The simulation results show that the offset of the rampu0027s stop voltage is reduced to 0.1 LSB and the nonlinearity of the ramp is 0.034%. Besides, the measurement results verify that this structure can fulfill automatic slope calibration.