3D Vertical RRAM Array and Device Codesign with Physicsbased Spice Model This paper demonstrates the codesign of threedimension (3D) Vertical Resistive Random Access Memory (RRAM) and the RRAM device. It presents a design consideration of 3D Vertical RRAM array in terms of array performance from the device point of view. A physicsbased RRAM Spice model is used to evaluate the performance of 3D RRAM array, including write access voltage, read margin, energy consumption and switching speed. The effects of device parameters, device parasitic capacitance, device variation and the 3D array size are discussed for design consideration. The simulation results show that with carefully choosing the RRAM device material and structure, a fastswitching, low energy consumption 3D RRAM array can be realized.

RRAM Endurance and Retention: Challenges, Opportunities and Implications on Reliable Design We provide an overview of metal oxide RRAM design challenges and opportunities in terms of endurance, retention and variability and the implications on the reliability and security of memory designs. We revise multiple level cell programming, endurance enhancing mechanisms, shortterm memory opportunities and variabilityaware design methods. We study the restore yield of nonvolatile SRAM designs for different endurance enhancing memory windows and device variability ranges citing power, reliability, endurance, and store energy tradeoffs taking into consideration program instability. A resistor window with a low high resistance state, which offers 100x enhanced endurance compared to a full range window, increases the restore power by around 2x while maintaining good yield in the absence of program instability. A resistor window with high low resistance state, which has 10x enhanced endurance, results in low restore power and store energy, and maintains good yield at low device process variations.