GPUBased Decompression for the 842 Algorithm In an age of evergrowing data volumes, lossless data compression is unarguably one of the most relevant techniques to handle vast data sets. To facilitate high throughput compression, modern IBM POWER CPUs provide hardware acceleration for the proprietary 842 compression algorithm. The 842 algorithm is optimized for main memory compression, and a softwarebased implementation of the algorithm is available as a part of the Linux kernel. Even though GPUequipped computers are vital for many of todays data intensive applications, GPUs have thus far been unable to interoperate with 842compressed data due to the lack of GPUbased decompressors. The main contribution of this paper is to fill this gap by providing optimized implementations for 842 decompression in both CUDA and OpenCL. We demonstrate that GPUbased decompression provides 4.59.5x speedup on integrated GPUs and 3034x speedup on dedicated GPUs when compared to softwarebased decompression on CPUs for various test systems. Test systems range from energyefficient SoCbased hardware with integrated GPUs to high end workstations and servers with dedicated GPUs.

ZFPV: HardwareOptimized Lossy Floating Point Compression Lossy floating point compression algorithms are critical components of reducing the cost and improving the performance of many modern applications, including machine learning and scientific computing. Data compression is widely used to reduce data storage requirements and transfer overhead, but traditional dataoblivious lossless compression schemes are very inefficient for floating point data. On the other hand, recently proposed lossy compression algorithms like ZFP and SZ achieve very high rates of compression while controlling the tolerable error margin. To the best of our knowledge, no efficient hardware implementation of ZFP exists yet, partially due to the inherently serial nature of the algorithm. In this paper, we present the design and implementation of ZFPV, which identifies the serial portion of the ZFP algorithm and modifies it for more efficient hardware implementation. ZFPV replaces the group testing part of ZFP with a variablelength header, which allows our hardware implementation to achieve up to 2x performance improvement compared to our besteffort hardware implementation of the original algorithm while using less onchip resources, at a marginal reduction of compression ratio. We evaluate an OpenCL implementation of ZFPV on an Intel Arria 10 FPGA using a variety of realworld scientific datasets, and show a singlepipeline throughput of 1 GBs xe2x80x93 4 GBs compression and 2 GBs xe2x80x93 10 GBs decompression on realworld datasets. Our implementation often outperforms a 32thread software implementation on a highend Intel Xeon CPU, and significantly outperforms a stateoftheart FPGA implementation of SZ.