Continuous Time SigmaDelta Modulator with VCObased integrators and optimized NTF zeros This work presents the architectural concept and circuit simulation of a third order VCObased ContinuousTime SigmaDelta Modulator. The loop filter has a mixed mode resonator built with an RCOTA PI element and a VCObased integrator coupled through a resistor, which helps to optimize SNDR. The quantizer is built with a noise shaping digitally controlled oscillator. A linear model of the system is developed and used to optimize the architecture. The performance of this concept is limited by the linearity of the DCObased quantizer, which can be mitigated by using a set of parallel singlebit switched ring oscillators. As an example, a 60MHz bandwdith ADC is designed and simulated, showing more than 70dB of SNDR with 2GHz sampling clock.

A 0.8 V LowPower 3rd order SigmaDelta Modulator in 22 nm FDSOI CMOS Process for Sensor Interfaces We present the design of a lowpower 3rd order sigmadelta (xcexa3xcex94) modulator targeted for sensor applications. The circuit is implemented in the 22 nm Fully Depleted Silicon on Insulator (FDSOI) CMOS process technology from GlobalFoundries. The modulator features a singleloop feedforward architecture. Lowvoltage operation of the fullydifferential switchedcapacitor based modulator is achieved with enhanced bootstrapped switches for highly linear sampling., and operational transconductance amplifiers (OTAs) operating in weak inversion. The onchip area of the modulator is 0.193 mm2. The measurement results show that operating over a signal bandwidth of 500 Hz at a nominal supply voltage of 0.8 V and a sampling rate of 512 kHz., the modulator achieves a peak signaltonoiseanddistortion ratio (SNDR) of 89 dB and a dynamic range of 94 dB. The total average power consumption of the designed modulator, including that of the auxiliary circuits, is 170 xc2xb5W.