A ZeroGating Processing Element Design for LowPower Deep Convolutional Neural Networks Convolution neural networks (CNNs) have shown great success in many areas such as object detection and pattern recognition. However, the high computational complexity of stateoftheart deep CNNs makes them extreme difficult to be run on resourceconstrained mobile and wearable devices. To address this design challenge, in this paper we first analyzed the filtersu0027 weights of pretrained models from four stateoftheart CNNs. We found that in all the CNNs that we analyzed, from about 20% (AlexNet) to 43% (VGG19) of the weights are zeros, which lead to redundant large amounts of computation. Then, based on this observation, a zerogating processing element (PE) design was proposed for lowpower deep CNNs, in which the vast number of zeros in both activation maps and filter weights are explored to eliminate redundant computation for power reduction. We implemented our proposal with VGG16 using ImageNet dataset. Experiments were conducted for evaluations of area and total power consumption. Compared with the baseline PE design without zerogating, overall the proposed zerogating PE can achieve 37% power saving while the corresponding area overhead is less than 8%.

PowerAware FPGA Mapping of Convolutional Neural Networks With an unprecedented accuracy in numerous AI tasks, convolutional neural networks (CNNs) are rapidly deployed on powerlimited mobile and embedded applications. Existing mapping approaches focus on achieving high performance without explicit consideration of power consumption, leading to suboptimal solutions when power is considered in a subsequent stage. In this context, there is an emerging need for poweraware methodologies for the design of custom CNN engines. In this work, a methodology is presented for modelling the power consumption of FPGAbased CNN accelerators using a highlevel description of modules, together with a powercentric search strategy for exploring powerperformance tradeoffs within the CNNtoFPGA design space. By integrating into an existing CNNtoFPGA toolflow, the proposed power estimation method can yield a prediction accuracy of 93.4% for total system power consumption. Furthermore, it is demonstrated that the associated poweroriented exploration approach can generate CNN accelerators with a 20.1% power reduction over a purely throughputdriven design for AlexNet, maintaining the designu0027s throughput.