A Structured Approach for Rapid Identification of FaultSensitive Nets in Analog Circuits The traditional body of literature on analog testing deals with propagation of faults to the output nets of the circuit. Often the set of detectable faults remains unsatisfactory because suitable stimuli cannot be found for propagating certain faults to the output. Existing technology supports capturing of the state of internal nets of a circuit, thereby enhancing the scope of detecting faults by observing their effect on internal nets. This approach is feasible only if the number of internal nets probed by the builtin test structure is very few. This paper presents a structured approach that identifies the sensitive nets, namely a well chosen small subset of internal nets that are affected by these faults. We utilize the speed of DC analysis and some common behavioral aspects of analog signals to find out this subset. We report dramatic improvement in fault coverage on several circuits including benchmarks.

Innovative BuiltIn SelfTest Schemes for OnChip Diagnosis, Compliant with the IEEE 1149.4 MixedSignal Test Bus Standard This paper presents a testing scheme for analog and mixedsignal circuitry compatible with the IEEE 1149.4 mixedsignal test bus standard. A highspeed dynamic current sensor is described, as well as an innovative selfdiagnostic method called VDDQ. The former is used to measure signature supply currents and to compare them with the footprint of a defectfree circuit. The latter senses the quiescent nodal voltages on several nodes of the circuit under test and compares them to their nominal values. A flag is raised if significant deviations are found. Simulation results are provided for the highspeed dynamic current sensor. Through simulations the VDDQ method has performed at one node test every half millisecond and has potential for much higher speed. It is faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defectfree IC to enter the market in significantly less time than with conventional testing methods.