Automatic Generation of MultiPrecision MultiArithmetic CNN Accelerators for FPGAs Modern deep Convolutional Neural Networks (CNNs) are computationally demanding, yet real applications often require high throughput and low latency. To help tackle these problems, we propose Tomato, a framework designed to automate the process of generating efficient CNN accelerators. The generated design is pipelined and each convolution layer uses different arithmetics at various precisions. Using Tomato, we showcase stateoftheart multiprecision multiarithmetic networks, including MobileNetV1, running on FPGAs. To our knowledge, this is the first multiprecision multiarithmetic autogeneration framework for CNNs. In software, Tomato finetunes pretrained networks to use a mixture of short powersof2 and fixedpoint weights with a minimal loss in classification accuracy. The finetuned parameters are combined with the templated hardware designs to automatically produce efficient inference circuits in FPGAs. We demonstrate how our approach significantly reduces model sizes and computation complexities, and permits us to pack a complete ImageNet network onto a single FPGA without accessing offchip memories for the first time. Furthermore, we show how Tomato produces implementations of networks with various sizes running on single or multiple FPGAs. To the best of our knowledge, our automatically generated accelerators outperform closest FPGAbased competitors by at least 24xc3x97 for lantency and throughput; the generated accelerator runs ImageNet classification at a rate of more than 3000 frames per second.

A BlockFloatingPoint Arithmetic Based FPGA Accelerator for Convolutional Neural Networks Convolutional neural networks (CNNs) have been widely used in computer vision applications and achieved great success. However, largescale CNN models usually consume a lot of computing and memory resources, which makes it difficult for them to be deployed on embedded devices. An efficient blockfloatingpoint (BFP) arithmetic is proposed in this paper. compared with 32bit floatingpoint arithmetic, the memory and offchip bandwidth requirements during convolution are reduced by 50% and 72.37%, respectively. Due to the adoption of BFP arithmetic, the complex multiplication and addition operations of floatingpoint numbers can be replaced by the corresponding operations of fixedpoint numbers, which is more efficient on hardware. A CNN model can be deployed on our accelerator with no more than 0.14% top1 accuracy loss, and there is no need for retraining and finetuning. By employing a series of pingpong memory access schemes, 2dimensional propagate partial multiplyaccumulate (PPMAC) processors, and an optimized memory system, we implemented a CNN accelerator on Xilinx VC709 evaluation board. The accelerator achieves a performance of 665.54 GOPs and a power efficiency of 89.7 GOPsW under a 300 MHz working frequency, which outperforms previous FPGA based accelerators significantly.