MAGIC: A Wearleveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs Many embedded systems such as automotive and industrial MicroController Units (MCUs) use onchip SRAM as main data memory of the embedded processor. However, SRAMs are increasingly susceptible to reliability threats such as Bias Temperature Instability (BTI) due to the continuous trend of technology shrinking. BTI leads to a significant performance degradation, especially in the Sense Amplifiers (SAs) of SRAMs, where failures are fatal, since the data of a whole column is destroyed. As countermeasure, usually guardbands are added to the design to prevent failures of the embedded system before its end of life. In this paper we present the Mitigation of AGIng Circuitry (MAGIC), a lowcost circuitry to effectively mitigate aging in SAs by wearleveling. The circuitry consists of an array of XOR gates and a counter. MAGIC modifies the mapping of SRAM banks to physical addresses. Updating the counter value distributes the stress of highly used addresses, e.g., corresponding to program stack data, onto the complete SRAM array. We evaluate the wearout for onchip SRAM data memory loads of a typical embedded application. MAGIC mitigates SA degradation up to  50% for three years of aging while introducing minimal areaperformance overhead.

Performing MemristorAided Logic (MAGIC) using STTMRAM Modern computers suffer from a limited data transfer rate between the memory and the processing units. One of the attractive potential solutions to overcome this bottleneck is to combine processing and memory by performing computing in the same location where the data is stored. Processinginmemory (PIM) has been demonstrated by memristoraided logic (MAGIC) operations using resistive random access memory (RRAM) memristive devices within crossbar arrays. Nevertheless, RRAM devices are relatively slow and suffer from limited endurance. Spintransfer torque magnetoresistive random access memory (STTMRAM) is another memristive technology, which is faster and has practically unlimited endurance and is therefore considered to be an attractive technology for cachelevel memories. In this paper, we demonstrate MAGIC operations within an STTMRAM array by supplying voltages suitable to achieve the current required for MRAM device switching. The proposed circuit was evaluated in SPICE simulations with the GlobalFoundries 22nm CMOSMRAM process, including Monte Carlo simulations to verify the proposed design in the presence of process variation and device mismatch. The circuit showed more than 90% chance of functioning for the 1 1 and 0 0 input cases while it was about 85% correct for the 0 1 case.