A Study on Switch Block Patterns for Tileable FPGA Routing Architectures Following the rapid growth of Field Programmable Gate Arrays (FPGAs) sizes, the regularity of architectures has become a critical feature, leading to the development of millionofLUT devices. While the routing architecture plays a dominant role in the area, delay and power of modern FPGAs, most of previously published works focus on improving the routability and performance of FPGAs while very few studied tileable (highlyregular) routing architectures. In this paper, we provide a detailed analysis between tileable and popular nontileable FPGAs considering modern routing architectures. First, we upgrade VPR to generate tileable routing architecture, which can support different switch block patterns for (1) the routing tracks that startend in a tile and (2) the routing tracks that pass through a tile. Then, we evaluate the performance of mixed switch blocks patterns in the context of a Stratix IVlike FPGA architecture, by considering the most representative patterns, i.e., Subset, Universal and Wilton. Experimental results show that averaged over the MCNC and VTR benchmarks, when compared to the welloptimized nontileable architectures, the tileable architectures can improve the minimum routable channel width by 13% and areadelay product by 2%. In particular, our results showed that in the context of tileable FPGA, a mix of Universal and Wilton switch block patterns lead to the best tradeoff in area, delay and routability, while Wilton switch block was the best choice in nontileable FPGAs.

An OpenSource Lightweight Timing Model for RapidWright Access to detailed timing information for FPGA resources is essential to achieving the highest performance. Yet, for commercial FPGAs, much of this information is not published or available. At the same time, deploying large, finegrained timing datasets adversely affects the speed of timingdriven place and route algorithms. We propose a nimble timing model for RapidWright that delivers high fidelity timing approximations while enabling faster algorithms through a frugal memory footprint. By leveraging a combination of architectural knowledge, repeating patterns and extensive analysis of Vivado timing reports, we obtain a slightly pessimistic, lumped delay model within 2% average accuracy of Vivado for UltraScale devices. We validate the results with over 240 designs and the proposed model shows high fidelity to Vivado with a Spearmanu0027s value of 0.99. By open sourcing the proposed model and describing the process, we empower the community to leverage and extend this work for customized domains, other device families, and additional accuracy.