Resolution Enhancement of VCObased ADCs by Passive Interpolation and Phase Injection This work describes a simple way to improve the resolution of lowpass voltagecontrolledoscillators based analogtodigital converters (VCObased ADCs) implemented with ringoscillators. We propose to insert a passive resistive network into the differential delay cells of the oscillator to get additional interpolated phases. These interpolated phases are then injected to other similar oscillators. By increasing the number of phases coming from all the oscillators, the effective gain of the system is higher and enhances the resolution of the converter. To validate the idea, a prototype of an openloop VCObased ADC was built in VerilogA language with ringoscillators designed with a 65nm CMOS process. The results of transient simulations were compared to the results of a behavioral ideal model of the system built in MATLAB. As expected, the signaltonoise ratio (SNR) was improved in concordance with the increase in the number of phases. Finally, it was checked that the proposed circuit used to extract and inject the interpolated phases did not penalize the total power consumption. The proposed circuit structure is particularly suitable for highbandwidth applications, where the oversampling ratio (OSR) is strongly restricted and the gain is limited because of the oscillator nonlinearity. Due to the highly digital nature of the VCObased ADC structures, this solution may be of special interest to be implemented in new deepsubmicron CMOS processes.

FirstOrder Recursive CIC Filters in TimeInterleaved VCOBased ADCs for DirectRF Sampling Receivers Digital building blocks operating at gigasamples per second (GSs) rates in direct radio frequency (RF) sampling receivers consume a large amount of the total power of the receivers. The previously reported techniques have not considered the digital blocks in analogtodigital converters (ADCs) and not decreased the power consumption. We first place firstorder recursive cascaded integratorcomb (CIC) filters with decimation factors of two after timeinterleaved ADCs (TIADCs), consisting of voltagecontrolled oscillators (VCOs), samplers, phase detectors, and differentiators. This CIC filter cancels out the differentiators with its integrators and halves the clock frequencies of the samplers to reduce the power consumption of the receiver. We design the digital blocks of a directRF sampling receiver with a 3.6GSs 4channel TI VCObased ADC for SubGHz applications (phase detectors, mixers, and CIC filters) by using a 65nm CMOS process. Simulations show that the placeandrouted circuit operates at a 450MSs rate with 3.6 mW, which is half of the power consumption of a digital circuit without the proposed method.