Efficient Management and Intelligent Fault Tolerance for HPC Interconnect Networks Interconnect Network is the key component in high performance computing system. With the incoming era of ExaScale (10E18 FLOPS) computing, designing large scale interconnect networks is facing with serious challenges in network management and fault tolerance. To construct higher performance and more reliable interconnect networks, we propose an efficient and intelligent network management architecture for indirect interconnect networks. This paper emphatically introduces the network management architecture, the inband management channels in the Network Interface Chips (NIC) and Network Routing Chips (NRC) respectively, efficient centralized network management approach, distributed intelligent faulttolerant routing management, and so on. Based on the prototype system, the Control and Status Registers (CSR) accessing latency performance of inband network management is evaluated. Also based on a customized simulation model for indirect interconnect networks, the typical distributed faulttolerant scenes are tested. The experiment results show the inband network management can averagely achieves 716 times improvements than the out ofband network management. Moreover, by running heuristic algorithms to automatically reconstruct routing tables for failure links or routers, the intellectual network management Engine can achieve faulttolerant routing to maximizing network performance.

MultiObjective Optimization of Channel Mapping for FailOperational Hybrid TDM NoCs Despite their technical and economic advantages, multicore processors are hesitantly adopted in safetycritical embedded application domains. A key issue is to provide hard realtime guarantees and faulttolerance for critical applications as well as isolation between applications of different criticality on shared resources such as the interconnect. To address this, hybrid NoCs that combine configurable TimeDivisionMultiplexing (TDM) for critical traffic with packet switching for BestEffort (BE) traffic have been proposed. More recently, hybrid NoCs with protection switching schemes have been introduced to cope with failoperational applications. Although they can handle failures happening in a NoC and guarantee realtime requirements by design, the problem of providing optimized mapping of critical tasks while considering the properties of protection switching schemes still remains. In this paper, we propose a multiobjective optimization methodology to tackle this matter. We first propose a model to map TDM channels onto a given NoC topology while considering protection switching schemes. The implemented objectives are defined so as to evaluate the behavior of the TDM mapping while still capturing its impact on the BE traffic, since a complete simulation considering BE would be time consuming (hundreds of thousands of NoC cycles with different injection rates). We then show how beneficial simultaneously optimizing several objectives is when using hybrid NoCs. The proposed methodology can indeed enable design space exploration in order to find feasible mappings for application specific scenarios and broad tradeoff analyzes without having to run prohibitively long BE traffic simulations.