An OpenCLBased Hybrid CNNRNN Inference Accelerator On FPGA Recently, Convolution Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and CNNRNN hybrid networks have demonstrated great success in many deep learning scenarios. Although many dedicated FPGA accelerators for a certain kind of network have been proposed, few of them combine CNN and RNN acceleration together. In this paper we propose a highthroughput and resourceefficient CNNRNN fusion accelerator on FPGA with commercial OpenCL to support generalpurpose DNNs. It utilizes a novel streaming architecture and mapping strategy to implement the most computationintensive and resourcedemanding parts in DNNs on the same computation logic. By such a hardware reuse method, it realizes resource efficiency in accelerating CNNs, RNNs and their hybrid networks. Our accelerator follows a layerbylayer, subgraphbysubgraph or subnetworkbysubnetwork execution mode, which facilities it to deploy most DNNs flexibly during runtime with best performance. YOLOv2, LSTM and CRNN are tested with our work on Intel Arria10 GX1150 FPGA. It achieves 646 GOPS throughput on CRNN, which is the best performance on CNNRNN hybrid networks among highlevelsynthesis (HLS) based FPGA accelerators. Moreover, its throughput for CNNs and RNNs is competitive to the stateoftheart specialized FPGA accelerators.

An OpenCLBased FPGA Accelerator for Compressed YOLOv2 Convolutional neural networks (CNNs) are widely used in computer vision applications. GPU has been the mainstream accelerator for CNNs. Compared with GPU, FPGA has the advantages of high flexibility, low power consumption and abundant DSP resources, which make it possible to surpass GPU in some scenarios. The recent progress of high level synthesis tools greatly improves the development efficiency of FPGA. In this paper, an OpenCLbased CNN accelerator is designed for FPGA and a variety of model compression techniques are applied to the YOLOv2 model. The accelerator uses the Winograd algorithm to implement convolution efficiently and solves the unaligned global memory access issue caused by the Winograd algorithm with an alignment stream buffer. This design makes full use of the available memory access bandwidth and utilizes all the available DSP resources. Parallelism is exploited in various dimensions for optimal performance. The performance of our FPGA design can reach 10 ms per image in terms of latency, compared to 15 ms per image with an nVidia P100 GPU. We plan to make our design open source so that the community can benefit from it and contribute to it together.