The Splash 2 software environment Splash 2 is an attached specialpurpose parallel processor in which the computing elements are userprogrammable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems that exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing behavioral descriptions of algorithms in VHDL, which are then iteratively refined and debugged within the Splash 2 simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing.

CompilerBased HighLevel Synthesis of ApplicationSpecific Processors on FPGAs In order to meet tight performance andor energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example FieldProgrammable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern HighLevel Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Softcore processors implemented with FPGAlogic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a generalpurpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compilerbased synthesis methodology that generates networks of ApplicationSpecific Instruction Set Processors (ASIPs) from unmodified CC algorithms. We thereby bridge the gap between traditional softcore processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compilerbased approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)fixed commercial Xilinx MicroBlaze softcores.