A New Hardware Friendly 2DDCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design This paper presents a hardwarefriendly algorithm to maximize the throughput of the Discrete Cosine Transform (DCT) of the High Efficiency Video Coding (HEVC), together with its hardware design. The Fast DCT (FCT) algorithm is based on the CooleyTuckey algorithm for the Fast Fourier Transform (FFT) with pre and postprocessing required to maintain the compliance with the HEVC. The resulting algorithm allows high throughput while maintaining low power dissipation. The designed hardware was synthesized for a 45nm Nangate technology and it reaches a throughput of 81.28GSamples per second when consuming 12.33mW. Such energy efficiency and throughput surpass all related works in the literature.

Maximizing the PowerEfficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors This paper proposes the use of approximate adder compressors for a lowpower 8point Modified Rounded Discrete Cosine Transform (MRDCT10) implementation. The algebraic approximation of the MRDCT was previously introduced in the literature, whose resultant matrix is only composed of 0, 1 and xe2x88x921 values. Therefore, the MRDCT can be efficiently implemented using only adders and subtractors. We present an environment for the synthesis of the MRDCT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of real images as input vectors to obtain valid power results. Our results show that the use of approximate addersubtractor compressors in hardwired stateoftheart 8point approximate MRDCT 10  achieves savings ranging from 26% to 52.54% when compared with the macro function () from the tool.