HighPerformance Implementation of Dynamically Configurable Load Balancing Engine on FPGA Load balancing technology plays an important role in task distribution. At present, mainstream solutions are implemented by software, and the delay introduced is longer; others implemented by hardware do not achieve excellent performance. This article proposes an implementation scheme of a reconfigurable load balancing engine on an FPGA. This engine could distribute network packets to CPU cores over a fivetuple, and the delay brought by balancing algorithm is only about 26 ns. Furthermore, this engine can process all frame sizes of packets at 100 percent line rate and zero packet loss rate, achieving excellent performance. At the same time, this engine supports dynamic configuration and can be set flexibly according to different scenarios.

A highperformance framework for a network programmable packet processor using P4 and FPGA Abstract   The emergence of new network technologies and usersu0027 everincreasing demand necessitates the introduction of highly programmable hardware with high flexibility and performance at the network data plane. The switches at the data plane need to be flexible enough to support protocols and test new ideas for increasing the abstraction of network programming. In most studies, Field Programmable Gate Arrays (FPGA) are applied in making switches flexible and reprogrammable; however, applying FPGAs alone does not meet the required flexibility. Next to applying FPGAs, it is necessary to provide an architecture that would allow developers to forego FPGA implementation hardware details and the complexity of hardware description language (HDL). In this paper, a new architecture of a programmable packet processor with high flexibility and programmability at the network data plane is presented, which supports all three operations required in switches: parsing, classification, and processing of packet data. To implement this architecture, the highlevel P4 language is applied to allow the description of its registertransfer level (RTL) on the FPGA. In order to increase the processing speed, a pipeline approach within the proposed architecture is designed at the SDN data plane through preprocessing in the parse graph, identifying the traffic flow, and applying the hybrid control flow model in the data processing. The results show that our architecture operates at 320xe2x80xafMHz clock speed, which in comparison with NetFPGA10G, NetFPGASUME, and ML605 peer architectures runs 2, 1.28, and 2.9 times faster in terms of processing speed, attesting to its efficiency. In addition, the evaluation on the Virtex7 FPGA VC709 platform shows that our architecture consumes approximately 4.3% of lookup tables, 1.9% of flipflops, and 1.3% of memory blocks, which are less than the hardware resource consumption of peer architectures.