A Comparison of Frequency Synthesizers Up to 25 GHz for 130 nm CMOS Implementation This paper provides a qualitative comparison of three frequency synthesizer schemes implemented in 130 nm CMOS technology, with the aim to select the best architecture to use given the application specs. The presented architectures can generate carrier frequency bands from a maximum frequency down to any lower frequency. All systems are designed based on 130 nm CMOS technology and can reach frequencies up to 25 GHz. We show that the single switched capacitors voltage controlled oscillator (SVCO) architecture is the best choice for frequencies below 6 GHz, and multiple core VCOs (MultiVCO) synthesizers show the best performances for frequencies above 16 GHz. On the other hand, the synthesizer equipped with a single side band mixer (SSBm) is the choice for applications requiring frequencies between 6 GHz and 16 GHz.

A Compact Inductorless 32 GHz Divideby2 CML Frequency Divider on 22 nm FDSOI Technology This paper presents a compact divideby2 frequency divider based on CML Dflipflops suitable for operation in lowpower (LP) or highperformance (HP) mode. In LP mode the divider locks in the 10 xe2x88x9228 GHz range, and in HP mode in the 12.5 xe2x88x9232 GHz range, corresponding to 119% and 118% relative locking ranges. The circuit has been manufactured on a 22 nm FDSOI CMOS process and consumes 3.5 mW and 6 mW from a 0.8 V and a 1 V supply while generating a xe2x88x9221 dBm and xe2x88x9215 dBm output signal in low power and high performance modes, respectively. The divider does not use any peaking inductors, which allowed an active core area occupation of only  255 boldsymbolmumathbfm2 . The small area and the absence of bias inputs allows its seamless integration into frequency synthesizer or clock recovery circuits.