Maximizing the PowerEfficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors This paper proposes the use of approximate adder compressors for a lowpower 8point Modified Rounded Discrete Cosine Transform (MRDCT10) implementation. The algebraic approximation of the MRDCT was previously introduced in the literature, whose resultant matrix is only composed of 0, 1 and xe2x88x921 values. Therefore, the MRDCT can be efficiently implemented using only adders and subtractors. We present an environment for the synthesis of the MRDCT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of real images as input vectors to obtain valid power results. Our results show that the use of approximate addersubtractor compressors in hardwired stateoftheart 8point approximate MRDCT 10  achieves savings ranging from 26% to 52.54% when compared with the macro function () from the tool.

Approximate Subtractor Operator for LowPower Video Coding Hardware Accelerators Video coding requires a massive computational effort leading to large power dissipation and energy consumption. Thus, energy efficiency becomes a significant concern especially under limited energy resources such as in mobile devices. Approximate computing is a promising technique to improve energy efficiency. Therefore, this work presents a new approximate subtractor operator to be used in video coding hardware accelerators. The proposed subtractor reduces power of a Sum of Absolute Differences (SAD) hardware accelerator on approximately 10.39% (on average of different videos) when compared to the use of the subtractor from the synthesis tool. It also presents a power reduction of 18.13% when compared to stateoftheart approximate adder.