LearningBased Design Space Exploration of Emerging 3D NoC Architectures In the absence of Moorexe2x80x99s Law, threedimensiona a promising direction to satisfy the demand from bigdata applications. However, due to the growing heterogeneity, system size, and issues stemming from emerging interconnecl (3D) manycore systems that incorporate both CPUs and GPUs presentsts such as monolithic 3D (M3D), it is difficult to satisfactorily explore the design space in reasonable amounts of time. In this paper, we reinforce the need for multiobjective formulations (optimizing for power, performance, thermals, etc. simultaneously) and present a solution that combines machine learning and local searches to quickly and intelligently explore the design space. In addition, we look at two specific problems (TSVbased 3D heterogeneous manycore systems and M3Dbased NoC) and what considerations need to be made at designtime.

Approximate NoC and Memory Controller Architectures for GPGPU Accelerators High interconnect bandwidth is crucial for achieving better performance in manycore GPGPU architectures that execute highly data parallel applications. The parallel warps of threads running on shader cores generate a high volume of read requests to the main memory due to the limited size of data caches at the shader cores. This leads to a scenarios with rapid arrival of an even larger volume of reply data from the DRAM, which creates a bottleneck at memory controllers (MCs) that send reply packets back to the requesting cores over the networkonchip (NoC). Coping with such high volumes of data requires intelligent memory scheduling and innovative NoC architectures. To mitigate memory bottlenecks in GPGPUs, we first propose a novel approximate memory controller architecture ( AMC ) that reduces the DRAM latency by opportunistically exploiting row buffer locality and bank level parallelism in memory request scheduling, and leverages approximability of the reply data from DRAM, to reduce the number of reply packets injected into the NoC. To further realize high throughput and low energy communication in GPGPUs, we propose a low power, approximate NoC architecture ( Dapper ) that increases the utilization of the available network bandwidth by using single cycle overlay circuits for the reply traffic between MCs and shader cores. Experimental results show that  Dapper  and  AMC  together increase NoC throughput by up to 21 percent; and reduce NoC latency by up to 45.5 percent and energy consumed by the NoC and MC by up to 38.3 percent, with minimal impact on output accuracy, compared to stateoftheart approximate NoCMC architectures.