Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion This paper presents an FPGA implementation of the Real Valued Time Delay Neural Network (RVTDNN) based digital predistortion with a very low resource utilization and high throughput. The implementation exploits efficient utilization of FPGA primitives and approximation of activation functions that can be realized with simple logic operations. The proposed modifications and constraints on the algorithms have been decided and verified based on a closedloop adaptive hardware setup including RFHIC RWP030401H PA as the unit under test together with injected RF impairments. Over 20dB of inband performance gain has been reported with a (4,8,2) RVTDNN configuration utilizing only 52 DSP48 blocks, 224 LUTs and 120 FFs.

Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration Implementations of hardware accelerators for neural networks are increasingly popular on FPGAs, due to flexibility, achievable performance and efficiency gains resulting from network optimisations. The long compilation time required by the backend toolflow, however, makes rapid deployment and prototyping of such accelerators on FPGAs more difficult. Moreover, achieving high frequency of operation requires significant lowlevel design effort. We present a neural network overlay for FPGAs that exploits DSP blocks, operating at near their theoretical maximum frequency, while minimizing resource utilization. The proposed architecture is flexible, enabling rapid runtime configuration of network parameters according to the desired network topology. It is tailored for lightweight edge implementations requiring acceleration, rather than the highest throughput achieved by more complex architectures in the datacenter.