A 307fps 351.7GOPsW Deep Learning FPGA Accelerator for RealTime Scene Text Recognition FPGAbased deep learning accelerator has become important for high throughput and low power inference at edges. In this paper, we have developed a computinginmemory (CIM) accelerator using the binary SegNet (BSEG) for realtime scene text recognition (STR) at edges. The accelerator can perform highly efficient pixelwise character classification under CIM architecture with massive bitlevel parallelism as well as optimized pipeline for low latency at critical path. The BSEG is obtained during training with a small model size of 2.1MB as well as a high classification accuracy over 90% on ICDAR03 and ICDAR13 datasets. The RTLlevel realized FPGAaccelerator can process the STR with an energyefficiency of 351.7 GOPsW and a throughput of 307 fps for processing one frame of 128xc3x9732 pixels in latency of 3.875 ms.

Implementation of Yolov2 Image Recognition and Other Testbenches for a CNN Accelerator An implementation of Yolov2 image recognition and other testbenches for a deep learning accelerator is presented. This chip is the initial version of our ongoing effort for a higher performance accelerator development. The accelerator is based on a systolic array and can handle convolution and maxpooling layer in a combined way or separately using 16 bit floatingpoint data. It also supports innerproduct and LSTM layers. For demonstration and as one of the design verification testbenches, we implemented Yolov2 image recognition for 80 object classes. We converted the Yolov2 software to 16 bit floating point version and used it in the simulation and FPGA experiment during the chip development. Several other testbenches were designed and used to test various networks. In this paper, the acceleratorxe2x80x99s architecture and the Yolov2 implementation on our FPGA board including camera and LCD is explained, including the software implementation. Some analyses on the measured and estimated performance is shown.