ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in HighLevel Synthesis Efficient highlevel synthesis (HLS) of dynamic memory allocation techniques (malloc() and free()) simplifies the compilation of algorithms with runtimevarying memory requirements to hardware designs. Existing HLS memory allocation frameworks often degrade performance and area, while simultaneously introducing even more parameters to optimize (e.g. heap depth, heap assignments to program logic). We address these concerns with ASAP (Automatic Sizing and Partitioning),a dynamic memory allocation framework for HLS tools. ASAP provides (1) automatic heap depth selection through dynamic analysis of an application, (2) automatic heap partitioning (through static analysis) to provide parallelism from program logic to memory, improving performance. We demonstrate that ASAP is able to improve performance and reduce cycle latencies compared with nonheappartitioned designs, with speedups up to  5xc3x97 when applied to common memory patterns, and up to  2xc3x97 improvement when applied to a suite of dynamicmemory intensive applications.

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled highlevel synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rely on loadstore queues (LSQs) to resolve the dependences dynamically, as the circuit runs. However, when employed on reconfigurable platforms, these LSQs are resourceexpensive, slow, and powerconsuming. In this work, we explore techniques for reducing the cost of the memory interface in dataflow designs. Apart from exploiting standard memory analysis techniques, we present a novel approach which relies on the topology of the control and dataflow graphs to infer memory order with the purpose of minimizing the LSQ size and complexity. On benchmarks obtained automatically from C code, we show that our approach results in significant area reductions, as well as increased performance, compared to naive solutions.