A model based approach to design applications for network processor Network Processors (NPs) are an emerging class of embedded systems used in the telecommunication domain for applications like routing and switching. In this paper we introduce the main characteristics of the existing NP architectures and the difficulties intrinsic to their software application design. On the other hand we review the basic principles underlying the wellknown modelbased development (MBD) approach. After motivating the opportunity of applying MBD to the domain of NPs, we outline a framework currently under development for the application of MBD to the design of NP software applications, thus allowing for the early derivation of test plans and for performance analysis.

A highperformance framework for a network programmable packet processor using P4 and FPGA Abstract   The emergence of new network technologies and usersu0027 everincreasing demand necessitates the introduction of highly programmable hardware with high flexibility and performance at the network data plane. The switches at the data plane need to be flexible enough to support protocols and test new ideas for increasing the abstraction of network programming. In most studies, Field Programmable Gate Arrays (FPGA) are applied in making switches flexible and reprogrammable; however, applying FPGAs alone does not meet the required flexibility. Next to applying FPGAs, it is necessary to provide an architecture that would allow developers to forego FPGA implementation hardware details and the complexity of hardware description language (HDL). In this paper, a new architecture of a programmable packet processor with high flexibility and programmability at the network data plane is presented, which supports all three operations required in switches: parsing, classification, and processing of packet data. To implement this architecture, the highlevel P4 language is applied to allow the description of its registertransfer level (RTL) on the FPGA. In order to increase the processing speed, a pipeline approach within the proposed architecture is designed at the SDN data plane through preprocessing in the parse graph, identifying the traffic flow, and applying the hybrid control flow model in the data processing. The results show that our architecture operates at 320xe2x80xafMHz clock speed, which in comparison with NetFPGA10G, NetFPGASUME, and ML605 peer architectures runs 2, 1.28, and 2.9 times faster in terms of processing speed, attesting to its efficiency. In addition, the evaluation on the Virtex7 FPGA VC709 platform shows that our architecture consumes approximately 4.3% of lookup tables, 1.9% of flipflops, and 1.3% of memory blocks, which are less than the hardware resource consumption of peer architectures.