HDCIM: Hyperdimensional Computing InMemory Architecture based on RRAM Braininspired Hyperdimensional Computing (HDC) is a fast and robust classification algorithm, which works by mapping lowdimensional features to highdimensional vectors and comparing distance in a high dimensional space. However, in traditional Von Neumann architecture, HDC causes high energy consumption because of large data movements between processor and memory. In this paper, we propose HDCIM, a Hyperdimensional ComputingInMemory architecture based on Resistive RandomAccess Memory (RRAM), to boost the energy efficiency of HDC. HDCIM puts computations in or near memory, which eliminates most of the data movements, providing a solution to reduce the energy consumption. In addition, to improve the computing parallelism, we use incrossbar RRAMbased logic design to process encoding operation in HDC. The experimental results show that HDCIM provides more than 100xc3x97 speedup and higher energy efficiency compared with HDC on CPU. Moreover, in comparison with existing RRAMbased Neural Network accelerators, HDCIM is more faulttolerant taking into account RRAM device faults, achieving 20% higher accuracy than RRAMbased DNN on ISOLET dataset when 20% RRAM devices suffer from StuckAtFaults (SAFs).

A LowPower HighThroughput InMemory CMOSReRAM Accelerator for LargeScale Deep Residual Neural Networks We present an inmemory accelerator circuit design for ResNet50, a largescale residual neural network with 49 convolutional layers, 2.6 xc3x97 107 parameters and 4.1 xc3x97 109 f1oatingpoint operations (FLOPS). A 4bit quantized ResNet50 is first chosen among various bitwidths for the best tradeoff. It is then trained and fully mapped onto a 4608 xc3x97 512 ReRAM crossbar, yielding a storage reduction from 195.2Mb to 24.3Mb and an 88.1% top5 accuracy on ImageNet, only 2.5% lower than the fullprecision original. Two versatile CMOS 4bit DAC and ADC are designed for input and readout, allowing the proposed CMOSReRAM accelerator to achieve up to 15.2xc3x97 runtime speedup and 498xc3x97 higher energy efficiency versus the stateoftheart CMOSASIC implementation.