Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations Cryptography is a key element to the development of secure communication in embedded environments such as connected cars and IoT. For some specific applications specific Lightweight Block Ciphers (LBC) have emerged. Those algorithms have been designed to be less resource consuming and more flexible than standard cryptographic algorithms. In order to keep a high levels of performance for software implementation of those LBC, we propose to enhance the instruction set of microprocessors by adding custom instructions. This would allow the system designer to find the best compromise between flexibility requirements and efficiency in terms of throughput and latency. This paper first presents a classification of LBC according to their specific operations. Then, based on the open RISCVISA, we propose a set of custom instructions to enhance LBC execution. The comparison of both execution time and throughput between different levels of processor customization is presented. Our results showed a significant gain as the execution time can be reduced by a factor between 20 and 100 for some classes of LBC.

An OpenSource Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers Lightweight implementations of cryptographic algorithms must be evaluated in terms of security, cost, and performance before their deployment in practical applications. The availability of opensource platforms for such evaluation saves researchersu0027 time and increases reproducibility of results. In this work, we improve upon the previous version of the Flexible Opensource workBench fOr Sidechannel analysis (FOBOS) to introduce xe2x80x9cFOBOS2,xe2x80x9d and utilize it to perform such evaluation tasks for hardware implementations of authenticated ciphers, with special focus on candidates submitted to the NIST Lightweight Cryptography standardization process. We perform power measurements on Artix7 FPGA, and countermeasure evaluation of lightweight hardware implementations of selected NIST Lightweight Cryptography Round2 candidates and the current NIST standard AESGCM on the Spartan6 and Artix7 FPGAs. Our results show that Ascon consumes the least power at 50 MHz, and has the lowest change in dynamic power per increase in frequency, while GIFTCOFB consumes the least energyperbit. We also show that sidechannel countermeasures applied to implementations of Ascon and AESGCM are effective using leakage detection tests.