A MemristorCMOS Braun Multiplier Array for Arithmetic Pipelining A multiplier is a core building block in most digital signal and image processing systems and increasingly so in neural processing units. The latter must parallelize very large scale multiplyandaccumulate operations in deep learning with reconfigurable weights to be multiplied with varying input. In light of this, we propose a memristorCMOS hybrid multiplier which uses a Braun structure to enable segmentation of the multiplier array to process various multiplication operations simultaneously with reconfigurable bitwidths by varying a control signal, all on the same multiplier. This enables an increase in computational throughput. Memristors are used as basic logic elements and improve area utilization by fabricating them in the back end of the line before the pad level. The CMOS chip is fabricated in the SK Hynix 180nm process with TiO 2  memristors separately deposited on top. A performance evaluation is undertaken under a 4point Fast Fourier Transform, demonstrating a decrease in area by 17% and power consumption by 35%49% with a 100MHz system clock when compared to similarly behaving CMOS multipliers.

MRL CrossbarBased Full Adder Design Memristor technology has acquired great interest in the field of nonvolatile memories as well as logic computation. The nanoscale structure of memristor and the possibility of its integration with MOSFETs have triggered many efforts to reconstruct basic digital building blocks. Recently, Memristor Ratioed Logic (MRL) has been introduced as a hybrid memristorCMOS logic design style, which has been functionally validated. In this paper, a 1bit full adder is designed by implementing MRL in crossbar array. The new design methodology efficiently integrates memristors at the top of CMOS layer. The corresponding layout and simulation results are performed using Cadence Virtuoso toolset targeting CMOS 65 nm process. The obtained results and their corresponding comparison illustrate promising outcomes in terms of implementation area, energy consumption and speed.