A MemoryBandwidthEfficient Word2vec Accelerator Using OpenCL for FPGA Word2vec is a word embedding method that converts words into vectors in such a way that the semantically and syntactically relevant words are closed to each other in the vector space. FPGAs can be used to design lowpower accelerators for Word2vec. FPGAs use highly parallel computations which require parallel data access. Since FPGAs generally have a small external memory access bandwidth compared to CPUs and GPUs, the processing speed is often restricted. We evaluate the tradeoff between bandwidth and accuracy using different fixedpoint formats, and propose a memorybandwidthefficient FPGA accelerator by utilizing 19bit fixedpoint data. We have implemented the proposed accelerator on an Intel Arria 10 FPGA using OpenCL, and achieved upto 28% bandwidth reduction without any degradation to the computation accuracy. Since the reduced bandwidth allows us to access more data without any data access bottleneck, it is possible to increase the processing speed by increasing the degree of parallelism.

An OpenCLBased Hybrid CNNRNN Inference Accelerator On FPGA Recently, Convolution Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and CNNRNN hybrid networks have demonstrated great success in many deep learning scenarios. Although many dedicated FPGA accelerators for a certain kind of network have been proposed, few of them combine CNN and RNN acceleration together. In this paper we propose a highthroughput and resourceefficient CNNRNN fusion accelerator on FPGA with commercial OpenCL to support generalpurpose DNNs. It utilizes a novel streaming architecture and mapping strategy to implement the most computationintensive and resourcedemanding parts in DNNs on the same computation logic. By such a hardware reuse method, it realizes resource efficiency in accelerating CNNs, RNNs and their hybrid networks. Our accelerator follows a layerbylayer, subgraphbysubgraph or subnetworkbysubnetwork execution mode, which facilities it to deploy most DNNs flexibly during runtime with best performance. YOLOv2, LSTM and CRNN are tested with our work on Intel Arria10 GX1150 FPGA. It achieves 646 GOPS throughput on CRNN, which is the best performance on CNNRNN hybrid networks among highlevelsynthesis (HLS) based FPGA accelerators. Moreover, its throughput for CNNs and RNNs is competitive to the stateoftheart specialized FPGA accelerators.