Improved Model for ESD Failure Caused by Stressing No Connect Pin The degradation of HBM level caused by stressing no connect (NC) pins has been observed. The failed pins follow a statistical regularity whose distribution are adjacent to the NC pins. Two mechanisms, capacitance coupling and air arc, are discussed in details about the fail. Supplement model for the coupling and the C BB , capacitance between NC and signal ball, is introduced. Furthermore, Transmission Line Pulse (TLP) is used to characterize the transient behaviors during the fail and the arc between NC and failed pins, when the stress voltage reached to 1.5 KV. By analyzing the degradation mechanisms, several ways are discussed to overcome this issue.

Study for NOR Flash cell burn out failure improvement in the advanced node below 65nm Flash cell endurance performance is one of the most important index for flash technology, it becomes more and more challenge during the NOR flash cell scaling down. In this paper, it was reported the mechanism analysis and improvement method for NOR Flash cell endurance burn out in the advanced node beyond 65nm. Tunnel oxide, inter poly dielectric(IPD) film, dielectric film between control gate(CG) to active area(AA) have been analyzed through various experiments to explain the mechanism for NOR Flash cell endurance burn out. To be noticed, we found that CG to AA interface defect reduction and optimized chip probing (CP) screen methodology could be extremely good to enhance NOR Flash cell endurance performance.