Using Hypervisor Technology for Safe and Secure Deployment of HighPerformance Multicore Platforms in Future Vehicles Future incar applications such as autonomous driving call for the use of multicore systemonchips (SoCs) together with powerful hardware accelerators. Hypervisor technologies offer the opportunity to partition such platforms and efficiently orchestrate the use of the shared hardware accelerators. Moreover, this allows one to consolidate existing and brand new applications in a single platform and thereby preserve past investments. On the other hand, the use of hypervisortechnology also addresses the need for shielding missioncritical software from uncritical software applications colocated on the same platform. Integrating applications with different safety and security needs into a single platform raises manifold design questions. We, at Elektrobit, believe, that a microkernelbased Hypervisor solution can be a mean to establish spatial and temporal isolation of software stacks and therefore is vital for deploying highperformance SoCs, not only inside vehicles, but also in other domains where software systems have to be shielded from another. As part of Elektrobits contribution to the EPI project, a hypervisor demonstration stack with different virtual machines will be deployed on a performancecentric multicore platform. In this paper, we present our system layout and discuss its key design features.

A Fast and Secure Pipelined Barrel Processor for SafetyCritical Applications for RealTime Operating Systems Security, reliability, and efficiency are crucial traits of the microprocessors used for safety and mission critical applications. Conventional microprocessors are typically not suitable for these applications, mainly because these processors do not support architecturallevel protection including thread isolation, which in turn could lead to security vulnerabilities in embedded systems. In this case, a single erroneous thread could cause catastrophic failure of the whole system. Also, with conventional microprocessors, no specific defense mechanisms are provided to prevent foreign invaders such as viruses from attacking the system. This could become a significant problem especially for safety and mission critical applications that are typically realtime systems. In this paper, we introduce novel and unique pipeline barrel processor (PBP) architecture for safety and mission critical applications for realtime operating systems. Our PBP microprocessor is designed in such a way to alleviate the aforementioned issues, by comprising following features: finegrained multitasking using single pipeline assembly, dynamic allocation of CPU cycles, memory partitioning at the architectural level, execution code regions at the hardware level, and global variables and stack protections. Experiments are performed to evaluate our PBP microprocessor, and to verify the correctness and functionality of the microprocessor design.