Extending the Lifetime of CoarseGrained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage Contemporary coarsegrained runtime reconfigurable architectures (CGRRAs) are increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). To address this, we propose a reliabilityaware floorplanner for CGRRAs based on a mixed Linear Programming (LP) and Integer Linear Programming (ILP) method that extends the Mean Time to Failure (MTTF) of CGRRAs by balancing processing element (PE) usage. We use this as the basis of a design space explorer that generates a variety of configurations, trading off PE displacement vs. MTTF. On average, a 2.4xc3x97 improvement in MTTF was obtained for an average critical path delay increase of under 2 percent (although most benchmarks had no delay increase) compared to the default lifetime unaware floorplan.

A Runtime PowerAware Phase Predictor for CGRAs As computation migrates to the edge, energy efficiency is becoming even more critical in the design of electronic devices. Therefore, new applications for the Internet of Things pose a challenge for designers to find the optimal balance between performance and energy consumption. While Coarse Grained Reconfigurable Architectures (CGRA) have been an alternative to provide the required acceleration, they are far from being the most energyefficient, since their functional units may be underutilized by some applications. In this work, we introduce a novel approach to handle these CGRA resources, which leverages the variable usage of functional units due to the application program phases. By using our new approach and performing powergating of underutilized parts of the CGRA, we demonstrate that it is possible to achieve reductions of up to 52.3% in power dissipation and 75% in energy consumption.