Extended pointers for memory protection in single address space systems Abstract   With reference to a single address space paradigm of memory addressing, we identify a set of mechanisms aimed at preserving the integrity of the virtual space of a given process from erroneous or fraudulent access attempts originated from other processes. These mechanisms guarantee a level of protection that is, in many respects, superior to that of a traditional multiple address space environment. We introduce extended pointers as a generalization of the concept of a memory address, which includes a password and an access authorization. A universally known, parametric oneway function is used to assign passwords. A specialized address translation circuitry supports memory reference and protection at the hardware level. A small set of protection primitives forms the process interface of the protection system. An indication of the flexibility of the proposed protection paradigm is given by applying extended pointers to the solution of a variety of protection problems.

Recruiting Fault Tolerance Techniques for Microprocessor Security The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging microarchitectural side channels such as due to speculative execution to implementing cryptographic accelerators for sidechannel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of u0027security faultsu0027 (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive sidechannels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the repurposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active sidechannel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic subcomponent of a RISCV based secure systemonchip, against a formidable fault attack called SIFA.