Analog Implementation of Reconfigurable Convolutional Neural Network Kernels This paper presents a neuromorphic circuit implementation of a 3x3 CNN convolution kernel that consists of 9 fourquadrant analog multipliers and one ReLU analog circuit unit. The kernel circuit is powered by a single power supply of 1.2V and the inputs can be both negative and positive values centered at VDD2 or 600mV with a dynamic range of xc2xb1 100mV. The multiplier can achieve an equivalent precision of 4bit of a digital multiplier, and the ReLU can achieve the perfect rectification of input values. The complete kernel circuit is designed with SMIC (Semiconductor Manufacturing International Corporation) 55nm CMOS LP process and the power consumption of the multiplier and ReLU is less than 13.2xc2xb5W and 14.4xc2xb5W respectively under full input swing. The analog kernel is also reconfigurable to construct any size of convolution kernel matrix.

Customizing CMOSReRAM Hybrid Hardware Architecture for Spiking CNN Spiking CNN can greatly reduce the computation and accordingly reduces the energy consumption with a small penalty to the accuracy, but the network latency is significantly increased because of the long spike trains. In this paper, we first introduce layer factors in the normalization of the synaptic weights and propose a greedy method to search proper layer factors for improving the network latency. Second, we present a customizable CMOSReRAM hybrid hardware architecture for Spiking CNN. The architecture consists of an array of configurable basic units (CBU), which involves a CMOS adder for neuron operations and a 1T1R memristive crossbar for storing synaptic weights. A column of CBUs can be configured as spiking neurons corresponding to convolutional kernels with various sizes while the whole array can be configured to provide row parallelism for a kernel convolution and interkernel parallelism. The input spike trains are transmitted between CBUs and are reused by different spike neurons when performing parallel computing of rows in spike feature maps. The results show that the network latency can be reduced 42.3% for an accuracy of 98.04% in LeNet5 by introducing layer factors. To our best knowledge, this is the first work to design customizable hardware architecture for Spiking CNNs. The simulation results show that the Spiking CNN consumes only 15.4% of the energy consumption of PipeLayer when processing the MNIST dataset.