Flexible and Adaptive Path Splitting of Simplified Successive Cancellation List Polar Decoding Polar codes are the first channel codes that have been proven to achieve the Shannon limit. In order to achieve satisfactory performance in moderate code length cases, successive cancellation list (SCL) decoding is considered as a promising scheme, which could achieve the performance of maximum likelihood decoding as list size increases. However, it suffers from the long latency in practical application, herein, simplified successive cancellation list (SSCL) can be employed to reduce the latency by parallel decoding of some special constituent nodes. In this paper, we focus on finding a way of path splitting during SSCL decoding. Based on the path metric (PM), an adaptive method is proposed to tighten the exact bound of path splitting without performance degradation. Compared with constant path splitting method, the proposed algorithm shows advantages in both performance and complexity reduction. Also, it avoids any foreknowledge soft information as a threshold stored in memory, which is different from the existing adaptive methods.

Fast Simplified MultiBit SuccessiveCancellation List Decoding of Polar Codes and Implementation Information, signal amplitude and phase change drastically in broadband multimedia communications and broadcasting. Channel coding is a key technology to ensure reliable information transmission in broadband mobile multimedia communication system. Polar codes are the first channel codes that can be proved to achieve channel capacity. In this paper, we propose a fast simplified multibit successive cancellation list (FastSMSCL) decoding method for polar codes. In our proposed FastSMSCL decoding, we take fully use of consecutive information bits and achieve prominent latency reduction of 3% to 58% compared to the existing simplified multibit successive cancellation list decoding. In addition, we also propose an architecture of FastSMSCL decoder, especially path memory unit and partial sum network. Finally, we implement the decoder on FPGA which achieves high throughput of 125Mbps.