Efficient NBIoT and GNSS chipset solution In this paper, an efficient GNSS (Global Navigation Satellite System) integration to NBIoT chipset and its solution for constrained tracking scenario (i.e. time sharing between NBIoT and GNSS) are explained. Considering the infrequent data transfer to network in the target application of NBIoT, it makes sense to constrain tracking scenario in order to optimize system architecture in NBIoT SoC (system on chip) for lowcost GNSS feature support. For efficient SoC design architecture, NBIoT and GNSS may share main hardware resources such like CPU, memory, and system peripherals. However, the time sharing of CPU for such hardware environment requires additional software solution to manage context saverestore, firmware binary switch, and data transfer between NBIoT and GNSS. In NBIoT, long period of eDRX (extended DRX) and PSM (Power Save Mode) modes allow enough spare time for GNSS to run exclusively on the shared resources without missing any paging request during location search operation by GNSS.

NaviSoC: HighAccuracy LowPower GNSS SoC with an Integrated Application Processor A dualfrequency allinone Global Navigation Satellite System (GNSS) receiver with a multicore 32bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a SystemonChip (SoC) in a 110 nm CMOS (complementary metaloxide semiconductor) process. The GNSS RF (radio frequency) frontend with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1E5ab, GPS (US Global Positioning System) L1L1CL5, BeiDou (Chinese Navigation Satellite System) B1B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1L3L5, QZSS (QuasiZenith Satellite System development by the Japanese government) L1L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for highaccuracy positioning. The whole SoC (systemonchip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the xe2x88x9240 to 105 xc2xb0C temperature range with a 1.5 V supply. The assembled testchip takes 100 pins in a QFN (quadflat noleads) package and needs only a quartz crystal for the onchip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1E1 and L5E5 is NF  2.3 dB, G  131 dB, with 121 dBcHz of phase noise  1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dualfrequency singlechip GNSS receiver equipped with a multicore application microcontroller integrated with embedded flash memory for the user application program.