HILL: A Hardware Isolation Framework Against Information Leakage on MultiTenant FPGA LongWires FPGA has recently been deployed in the multitenant cloud to provide highperformance computing capabilities. Such deployment of FPGA creates a new attack surface for adversary. It has been recently demonstrated that the capacitive crosstalk between FPGA longwires can be used as a sidechannel to extract secret information. In this paper, we present HILL: a Hardware Isolation framework against information Leakage on multitenant FPGA Longwires. As a defense framework, HILL can prioritize the placement and routing of securitycritical hardware instances and isolate them from other parts and tenants. For data and communication interfaces that use FPGA longwires, such as UART, PCIe, and AXI4, HILL employs a longwire obfuscation technique to reduce the sidechannel leakage. We evaluate the performance of HILL with Xilinx Artix7 FPGAs using two prevalent FPGA development tools: Xilinx ISE 14.7 and Vivado 2018.3. The experimental results demonstrate that HILL can effectively reduce the crosstalkcaused sidechannel leakage by 138 times. The longwire obfuscation technique reduces the correlation between the sidechannel leakage and secret key from 81.7% to 50.3%, which is close to random guess.

An OpenSource Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers Lightweight implementations of cryptographic algorithms must be evaluated in terms of security, cost, and performance before their deployment in practical applications. The availability of opensource platforms for such evaluation saves researchersu0027 time and increases reproducibility of results. In this work, we improve upon the previous version of the Flexible Opensource workBench fOr Sidechannel analysis (FOBOS) to introduce xe2x80x9cFOBOS2,xe2x80x9d and utilize it to perform such evaluation tasks for hardware implementations of authenticated ciphers, with special focus on candidates submitted to the NIST Lightweight Cryptography standardization process. We perform power measurements on Artix7 FPGA, and countermeasure evaluation of lightweight hardware implementations of selected NIST Lightweight Cryptography Round2 candidates and the current NIST standard AESGCM on the Spartan6 and Artix7 FPGAs. Our results show that Ascon consumes the least power at 50 MHz, and has the lowest change in dynamic power per increase in frequency, while GIFTCOFB consumes the least energyperbit. We also show that sidechannel countermeasures applied to implementations of Ascon and AESGCM are effective using leakage detection tests.