Validating MultiProcessor Cache Coherence Mechanisms under Diminished Observability Modern chip multiprocessors (CMP) inevitably require cache coherence mechanisms for their correct operation. However, exhaustive functional verification of a complex cache coherence mechanism is a challenging task. This leads to bugs escaping to the first silicon and necessitates validation at the post silicon stage. In this work, an onchip signal logging method is proposed which helps in bug detection in case of design errors and softerrors arising out of reliability issues. The logged contents can then be further dumped offline for finegrained bug localization. The proposed methodology utilizes cache coherence protocol specifications to obtain the signal states of coherence transactions and the detector module flags an error once a mismatch is found between observed signal states and correct signal states. The proposed logging mechanism decreases the error detection latency at minimal area and power overheads. Experiments on a four core multiprocessor having a 7stage MIPS pipeline implementing the widely utilized directorybased MESI protocol indicate that the proposed methodology succeeds in detecting design errors. Analysis of soft errors have also been performed and shorter error detection latency is achieved compared to a previously proposed technique in the literature.

Synchronizing OnChip Software and Hardware Traces for HLSAccelerated Programs Complex designs generated from modern highlevel synthesis tools allow users to take advantage of heterogeneous systems, splitting the execution of programs between conventional processors, and hardware accelerators. While modern HLS tools continue to improve in efficiency and capability, debugging these designs has received relatively minor attention. Fortunately, recent academic work has provided the first means to debug these designs using hardware and software traces. Though these traces allow the user to analyze the flow of execution on both the software and hardware individually, they provide no means of synchronization to determine how operations on one device affect the other. We address this challenge by introducing a synchronization technique that keeps track of operations on shared objects. We identify objects shared between hardware and software and their memory operations, and use unique identifiers to synchronize the traces around these operations. We explore the added costs of this technique on execution time and hardware and software resources, and ways to reduce it through multiple synchronization schemes. This is demonstrated in an opensource prototype targeting the hybrid flow of the opensource HLStool LegUp.