FullySynthesizable CurrentInput ADCs for UltraLow Area and Minimal Design Effort A fully synthesizable ADC architecture is proposed for lowend current sensing applications. Being based on standard cells and designed with a fullyautomated flow, the proposed ADC allows very low area, digitallike scaling across CMOS technology generations, technology and design portability, minimal design effort, and immersedin logic design (i.e., low integration effort), compared to traditional analogintensive designs. In addition, it allows direct current readout without requiring a transresistance stage. Testchip measurements show a 5nA to  1boldsymbolmu mathbfA  input range, 6.7bit ENOB and 2.2kSs sample rate, at 940nW power and  4,580boldsymbolmu mathbfm2  area. To the best of the authorsu0027 knowledge, this testchip is the first demonstration of a fullysynthesizable inputcurrent ADC. Along with the analysis of the specific limitations of the presented demonstration, this work aims to pave the way for a new class of currentinput ADCs that can be designed and integrated with logic within hours, and occupy a silicon area in the order of 10kgates.

A Low Voltage CMOS Current Comparator with Offset Compensation Analysis and design of an inverterbased current comparator consisting of 3 cascaded inverters is presented. Ideally, the comparator has almost zero input offset current when all inverters are assumed to be identical. In practice, small amount of threshold voltage or current mismatches may cause the offset current to increase dramatically. A switchedcapacitor inverter is added to the comparator circuit in order to mitigate such effect. During compensation phase, the switched inverter forms a feedback loop to generate a current that will compensate the input offset current. During comparison phase, the generated charge hold in the capacitor decreases the offset current significantly. To keep the loop stable, an RC Milleru0027s frequency compensator is also added. A prototype of the whole circuit using 0.18xc2xb5m process is designed and analyzed to prove this concept. It operates at 1V DC supply with 870nA consumption, 1nA resolution and 50ns delay for xc2xb1100nA step input. Its input offset current is 13pA when there is no mismatch. When the mismatch is accounted, it increases to 164nA. After installation of the compensation circuit, the offset current is cut down to 19pA.