First Order Fully Passive NoiseShaping SAR ADC Architecture with NTF Zero close to One A new noiseshaping architecture for successive approximation register (SAR) analogtodigital converters (ADCs) was proposed. It does not require comparator modification, so the standard comparator can be used. A firstorder noise transfer function with zero located nearly at one can be achieved. This allows the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB). The architecture is fully passive. The architecture was applied to the design of a 9.9bit ENOB SAR ADC in a 65 nm complementary metaloxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6bit DAC was used. The proposed architecture provides 3.9 additional bits in ENOB. Signaltonoise and distortion ratio (SINAD) of 61.4 dBFS was achieved according to simulation results for a signal bandwith of 200 kHz with sampling rate of 4 MSs.

A ComparatorReused DynamicAmplifier for NoiseShaping SAR ADC This paper presents a highspeed highgain dynamic amplifier which can also be reused as a comparator for a noiseshaping (NS) successiveapproximationregister (SAR) analogtodigital converter (ADC). By modifying a strongarm latch, this dynamic amplifier can achieve a high speed of comparison and dynamic amplification, which is crucial to a highperformance NS SAR ADC. The prototype is designed in 28 nm CMOS process. It realizes the comparison speed of 0.2 ns and 8 times dynamic amplification in 0.9 ns with 0.6 pF singleend capacitance load. Meanwhile, the noise floor is 11 nVxe2x88x9aHz and the THD is 76.5 dB with the power consumption of 56 xc2xb5W averagely.