Drift induced rigid current shift in GeRich GST Phase Change Memories in Low Resistance State GeRich GST based Phase Change Memories (PCMs) represent a valid candidate for embedded nonvolatile storage due to hightemperature stability, which enables data retention compatible with automotive applications and data integrity in case of soldering reflow stress. Howeover, GeRich GST based PCMs are affected by resistance drift both for cells programmed in the highresistance state (HRS) and for cells programmed in the lowresistance state (LRS). Our experimental investigation, carried out on a population of 500k cells in a memory array, showed that the variation over time of the LRS cell current is substantially constant for all the cells in the array, regardless of the value of the cell current (and, hence, of the cell resistance) measured just after programming, which results in a rigid cell current shift. Starting from the obtained experimental results, we derived an expression to calculate the drift coefficient in LRS cells as a function of their initial resistance.

PhaseChange Memory Models for Deep Learning Training and Inference Nonvolatile analog memory devices such as phasechange memory (PCM) enable designing dedicated connectivity matrices for the hardware implementation of deep neural networks (DNN). In this inmemory computing approach, the analog conductance states of the memory device can be gradually updated to train DNNs onchip or software trained connection strengths may be programmed onetime to the devices to create efficient inference engines. Reliable and computationally simple models that capture the nonideal programming and temporal evolution of the devices are needed for evaluating the training and inference performance of the deep learning hardware based on inmemory computing. In this paper, we present statistically accurate models for PCM, based on the characterization of more than 10,000 devices, that capture the statedependent nature and variability of the conductance update, conductance drift, and read noise. Integrating the computationally simple device models with deep learning frameworks such as TensorFlow enables us to realistically evaluate training and inference performance of the PCM array based hardware implementations of DNNs.