A Novel Speedup Evaluation for Multicore Architecture Based Topology of OnChip Memory. Speedup is measured as parallel program potential for evaluation in CMP. Researchers made a lot of contributions in evaluating the speedup of multicore, however the specific architecture is not taken into consideration yet. This article presents a novel method ETOM (Evaluation on Topology of Onchip Memory) to evaluate the speedup of multicore. This method obtains the speedup based on the specific architecture and the memory organization. For verifying the legitimacy of this approach, existing speedup laws and our method are compared in this research work. The use of the method can be more easily to obtain the speedup of multicore architecture, especially at the initial phase of designing a new multicore architecture. Using ETOM, a novel multicore architecture TriBA can be obtained which performance is better than 2DMesh. In the processing of experiments, a lot of detailed characteristics of 2DMesh be found, such as different speedup of each core in different locations. However, each core has the same speedup in TriBA by using ETOM and the performance of speedup in it more than in 2DMesh. So the method is very fit for evaluating performance of specific architectures. And the new architecture TriBA has a reasonable topology of onchip memory than 2DMesh.

Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis Memory level parallelism (MLP), which refers to the number of memory requests concurrently held by Miss Status Handling Registers (MSHRs), is an indispensable factor to estimate cache performance. Unfortunately, due to the complexity of obtaining the maximum number of memory instructions or cache misses among all dependence paths, previous works in MLP modeling are very timeconsuming in trace profiling. In this paper, we propose a fast model for evaluating MLP without analyzing all dependence paths in the instruction windows. Instead, we construct a probability model to estimate the maximum number of cache misses among all dependence paths in the instruction windows fed with some easily obtained inputs. By doing so, we greatly reduce the time overhead of the MLP model with a slight drop in accuracy. Twelve benchmarks chosen from Spec2006 are adopted for evaluating the accuracy and time overhead of our model. The average error of our model compared with the results of Gem5 simulations is around 9%, while the time overhead of the MLP evaluation process can be decreased to about half of previous models.