Composable Probabilistic Inference Networks Using MRAMbased Stochastic Neurons Magnetoresistive random access memory (MRAM) technologies with thermally unstable nanomagnets are leveraged to develop an intrinsic stochastic neuron as a building block for restricted Boltzmann machines (RBMs) to form deep belief networks (DBNs). The embedded MRAMbased neuron is modeled using precise physics equations. The simulation results exhibit the desired sigmoidal relation between the input voltages and probability of the output state. A probabilistic inference network simulator (PINSim) is developed to realize a circuitlevel model of an RBM utilizing resistive crossbar arrays along with differential amplifiers to implement the positive and negative weight values. The PINSim is composed of five main blocks to train a DBN, evaluate its accuracy, and measure its power consumption. The MNIST dataset is leveraged to investigate the energy and accuracy tradeoffs of seven distinct network topologies in SPICE using the 14nm HPFinFET technology library with the nominal voltage of 0.8V, in which an MRAMbased neuron is used as the activation function. The software and hardware level simulations indicate that a 784xc3x97 200xc3x97 10 topology can achieve less than 5% error rates with xe2x88xbc400pJ energy consumption. The error rates can be reduced to 2.5% by using a 784xc3x97 500xc3x97 500xc3x97 500xc3x97 10 DBN at the cost of xe2x88xbc10xc3x97 higher energy consumption and significant area overhead. Finally, the effects of specific hardwarelevel parameters on power dissipation and accuracy tradeoffs are identified via the developed PINSim framework.

Neuromorphic Hardware Accelerator for SNN Inference based on STTRAM Crossbar Arrays In this paper, we propose a Spin Transfer Torque RAM (STTRAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the timebased signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of nonvolatile STTRAMs, readwrite peripheral circuits, and digital logic for the spiking neurons. Intercore communication is realized through onchip routing network by sendingreceiving spike packets. Unlike prior works that use multilevel states of nonvolatile memory (NVM) devices for the synaptic weights, we use the technologicallymature STTRAM devices for binary data storage. The design studies are conducted using a compact model for STTRAM devices, tuned to capture the stateoftheart experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STTRAM based neurosynaptic core designed in 28 nm technology node has approximately 6xc3x97 higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves xe2x88xbc 2xc3x97 higher performance per Watt compared to other memristive neural network accelerator designs in the literature.