Evaluation of Partially Constant, FineGrained, Dynamic Partial Reconfigurable Functions in FPGAs Dynamic Partial Reconfiguration (DPR) is a wellestablished technique for changing the functionality of a circuit in an FPGA during runtime. However, DPR can also be used to simplify any given function by replacing one or more inputs or parts of an input of a function by multiple versions of that function. During deployment, depending on the current value of the replaced inputs, a new partial configuration is programmed. This concept of decomposing digital circuits is known as Booleu0027s expansion theorem (also known as Shannonu0027s expansion theorem). Its feasibility in a DPR scheme is investigated in this work and required conditions for its application to finegrained functions are identified. An extension of the Xilinx Vivado design flow is presented to facilitate the efficient generation of large numbers of partial configurations. The proposed DPR scheme is applied to fixedpoint multiplication and division circuits in order to evaluate its performance. Resource utilization, power, and critical path latency are evaluated and compared with conventional FPGA implementations of the same circuits. It is found that the proposed DPR scheme allows for the reduction in power and in criticalpath delay in certain scenarios.

Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration Partial reconfiguration supports virtualisation of applications on FPGAs, enabling compute to dynamically adapt to workloads in distributed infrastructure and datecenters. While the latter often makes use of the PCIe interface and supporting infrastructure to allocate and load compute kernels via a host CPU, FPGAs are becoming increasingly popular as standalone resources in edgecomputing, requiring them to manage accelerators autonomously. This paper presents a platform that supports the managing of accelerator bitstreams over the network interface on a Xilinx Zynq device without intervention by the Arm processor. We compare against traditional vendor provided PR management for both library accelerators and custom accelerators and show that we achieve a 29% decrease in reconfiguration trigger latency using this approach.