CNNGrinder: From Algorithmic to HighLevel Synthesis Descriptions of CNNs for Lowendlowcost FPGA SoCs Abstract   Although HighLevel Synthesis (HLS) tools have been in the scene for almost fifteen years, researchers have been reluctant to use them for accelerating their algorithms on FPGA SoCs. We present CNNGrinder, a templatedriven workflow for converting algorithmic descriptions of mobilefriendly convolutional neural networks (CNNs), such as SqueezeNet v1.1 and ZynqNet, to HLS code which can be used for programming lowendlowcost FPGA SoCs. In contrast to other works, which from the user perspective are acting as a black box, CNNGrinder does not hide its inner workings by automating the procedure of algorithmictoHLS description but it exposes every step in a clear and concise way. CNNGrinder provides the means to developers to map a CNN on an FPGA SoC by providing easy to follow steps and templates which are not constrained to specific CNN architectures and FPGA devices. Our workflow is accompanied by the SqueezeJet2 accelerator, which is used for the acceleration of the convolutional and the maxpooling layers of the SqueezeNet v1.1 and the ZynqNet CNNs making possible to achieve more than 10fps CNN inference at 100MHz using a batch size equal to 1 on a lowendlowcost FPGA SoC such as the Xilinx XC7Z020. Finally, an analytical model of the SqueezeJet2 accelerator is developed and evaluated against related results produced by the Xilinx Vivado HLS tool.

An Efficient Accelerator for Sparse Convolutional Neural Networks In this paper, we propose a sparse convolutional neural network accelerator design on FPGAs. Similar to the DNNWEAVER architecture, our accelerator uses twolevel hierarchy: multiple Processing Units (PUs) and each PU comprises a set of Processing Elements (PEs). To address the irregularity of sparse neural networks, we introduce a novel sparse dataflow for sparse CNN computing as well as weight merging method to balance the computation load on different PUs for better overall efficiency. We implement our design with 32 PUs and 14 PEs in each PU. When compared with DNNWEAVER on VGG16 network, our accelerator achieves 3.49x speedup and 3.05x energy saving on average when running at 150MHz on a Xilinx ZC706 board and reaches the speed of 400 GOPS.