Low Power SPI Design Based on Relative Timing Techniques The Serial Peripheral Interface (SPI) is a specification for serial synchronous communications. It is widely adopted in industry as a solution for communication between system core and peripherals in embedded systems. This work introduces the design and implementation of a SPI using a novel approach to asynchronous circuits: Relative Timing (RT). RT is a technique that provides a formal representation of timing requirements on circuits and can be integrated into a standard ComputerAided Design (CAD) flow with minor additions. It has profound impact on design style and global parameters such as power consumption, area and performance. The obtained results are compared to an industry standard synchronous implementation. The proposed RT design shows a benefit of 2.25xc3x97 in power per transfer for a fully active operation mode that improves with the addition of idle time, and a benefit of 1.35xc3x97 in silicon area.

A Precise BlockBased Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines The impact of process variations on timing has become significant in advanced technology nodes. In this paper, a multivariate adaptive regression splines (MARS) delay model is proposed that considers both global and local process variations to characterize this impact more accurately. In order to obtain MAX operation results, the first three moments of MARS gate delay distribution are calculated, converting the timing distribution to a skewnormal representation. Eventually, based on an approximation MAX operation, the blockbased SSTA propagates the arrival time through the timing diagram. Tested with 10 ISCAS85 benchmark circuits, the average mean squared error and standard deviation error of the path delay calculation are 0.52% and 0.88%.