PostSi Nano Device Technology Ge is one of the promising candidates for use as high mobility channels in future CMOS device. The mobility of an electron and a hole is much higher in the Ge channel than in the Si channel. On the other hand, for 10nmnode CMOS and beyond, a multigate fin structure is utilized to maintain electrostatic controllability of the gate electrode. The Ge FinFET is generally fabricated by Ge epitaxial growth from a SiGeSi substrate 1 and conventional topdown etching by a plasma etching 2. Usually, fin structure formation in Ge Fin FETs is carried out by using ICP (inductively coupled plasma) sources. However, ICP sources cause plasma induced damages owing to the ultraviolet (UV) light generated from the ICP and chargingup phenomena by the irradiation of ionized atoms. One concern is that such etching damage reduces the performance and reliability of Gechannel CMOS. In this work, to breakthrough these plasmainduced damages, we demonstrated defectfree and highly anisotropic Ge etching for Ge FinFET fabricated by C1 neutral beam etching 3.

Performance Investigation of Uniaxially Tensile Stressed Ge nFinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters In this work, we studied the performance enhancement of uniaxially tensile stressed nFinFETs realized on the biaxially strained GeOI (sGOI) wafer and its impact on the performance of a Ge CMOS inverter. Uniaxially strained Ge film with nanoscale film width could be patterned on sGOI substrates and used for the fabrication of strained Ge FinFETs. The performance of this novelly proposed Ge FinFET was compared with the unstrained ones with similar dimensions and fabrication processes. The impact of strain on devices with different geometric parameters are also studied. As the strained FinFETs lead to higher oncurrent, its impact on the circuit speed was simulated. By comparing the output signal of the strained Ge CMOS inverter with the unstrained one, the former shows obvious speed improvement.