Improving Performance Estimation for FPGAbased Accelerators for Convolutional Neural Networks. Fieldprogrammable gate array (FPGA) based accelerators are being widely used for acceleration of convolutional neural networks (CNNs) due to their potential in improving the performance and reconfigurability for specific application instances. To determine the optimal configuration of an FPGAbased accelerator, it is necessary to explore the design space and an accurate performance prediction plays an important role during the exploration. This work introduces a novel method for fast and accurate estimation of latency based on a Gaussian process parametrised by an analytic approximation and coupled with runtime data. The experiments conducted on three different CNNs on an FPGAbased accelerator on Intel Arria 10 GX 1150 demonstrated a 30.7% improvement in accuracy with respect to the mean absolute error in comparison to a standard analytic method in leaveoneout crossvalidation.

PowerAware FPGA Mapping of Convolutional Neural Networks With an unprecedented accuracy in numerous AI tasks, convolutional neural networks (CNNs) are rapidly deployed on powerlimited mobile and embedded applications. Existing mapping approaches focus on achieving high performance without explicit consideration of power consumption, leading to suboptimal solutions when power is considered in a subsequent stage. In this context, there is an emerging need for poweraware methodologies for the design of custom CNN engines. In this work, a methodology is presented for modelling the power consumption of FPGAbased CNN accelerators using a highlevel description of modules, together with a powercentric search strategy for exploring powerperformance tradeoffs within the CNNtoFPGA design space. By integrating into an existing CNNtoFPGA toolflow, the proposed power estimation method can yield a prediction accuracy of 93.4% for total system power consumption. Furthermore, it is demonstrated that the associated poweroriented exploration approach can generate CNN accelerators with a 20.1% power reduction over a purely throughputdriven design for AlexNet, maintaining the designu0027s throughput.