Research on the impact of different benchmark circuits on the representative path in FPGAs The transistorlevel optimization of FPGAs faces a huge challenge due to the programmability. We donu0027t know what kinds of enduseru0027s circuit will be implemented on the FPGA. This means that the critical path is unknown at design time. To handle this issue, academic community creates a representative path which will be used during optimization. This path is the shortest register to register path within an FPGA that contains all unique components. However, no research has analyzed how different reference circuits can affect the representative path. In order to explore this issue, we obtained statistics of subcircuit usage of the critical path of different benchmarks. subcircuit includes interconnect circuits and logic resources. This paper compares the two aspects of the representative path and each critical path: subcircuit utilization rate and the delay of paths. For the first aspect, result shows that the subcircuit utilization rate on the representative path can indicate the subcircuits utilization rate on critical path in different benchmark circuits. For the second aspect, the critical path delay of FPGA fluctuates between 10.6% and 8% of the representative path delay when implementing different benchmark circuits. We found that under the premise of selecting a large number of typical benchmark circuits, the representative path delay can well represent the overall timing performance of FPGAs.

An OpenSource Lightweight Timing Model for RapidWright Access to detailed timing information for FPGA resources is essential to achieving the highest performance. Yet, for commercial FPGAs, much of this information is not published or available. At the same time, deploying large, finegrained timing datasets adversely affects the speed of timingdriven place and route algorithms. We propose a nimble timing model for RapidWright that delivers high fidelity timing approximations while enabling faster algorithms through a frugal memory footprint. By leveraging a combination of architectural knowledge, repeating patterns and extensive analysis of Vivado timing reports, we obtain a slightly pessimistic, lumped delay model within 2% average accuracy of Vivado for UltraScale devices. We validate the results with over 240 designs and the proposed model shows high fidelity to Vivado with a Spearmanu0027s value of 0.99. By open sourcing the proposed model and describing the process, we empower the community to leverage and extend this work for customized domains, other device families, and additional accuracy.