Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor The reconfigurable verylong instruction word (VLIW) cipher processor need a large number of instructions and a long execution period when processing the elliptic curve cryptographic algorithm. By adding a modular operation acceleration unit to the cryptographic processor, the energy efficiency of the cipher processor processing the elliptic curve cryptographic algorithm is improved. After synthesis under the 130nm process standard cell library, the experimental results show that the module operation acceleration unit area is 30 Kgate, accounting for 6% of the processor area, and the 256bit binary domain point multiplication operation time is reduced from 22.8ms to 5.8ms, and the energy efficiency is improved by about 372%.

Crypto Accelerators for PowerEfficient and RealTime onChip Implementation of Secure Algorithms The demand for data exchange is ever growing. Internet of Things (IoT), industry 4.0, smart city and nextgeneration interconnected vehicles are some examples of scenarios in which a high volume of nodes share data across networks. Hence, the data protection plays a fundamental aspect to avoid disclosure or manipulation of sensitive information and disruption of services, particularly in safety critical applications. On the other hand, also the compute power at disposal of possible attackers and hackers is growing, and nextfuture postquantum capabilities will require the usage of longer keys, certificates and digital signatures, to preserve the security level offered by cryptographic functions. This will affect not only the amount of exchange data, but also the computational resources to secure data, increasing processing time, latencies and power consumption, and lowering data rates. In this work, we investigate different implementation strategies to overcome such performance limitations. This work provides a comparison among pure software approach (both on 32b and 64b processors) and hardwarebased solutions we developed for FPGA and ASIC SystemonChip platforms, for the most common symmetrickey and publickey cryptographic algorithms. The proposed hardware accelerators feature one order of magnitude higher throughput (and lower latency) and more than two orders lower power consumption than their software counterparts. A highly configurable cryptographic suite is proposed that can be customized according to the application requirements and thus able to increase as much as possible the efficiency in terms of energy per enciphered bits per second.