A CellBased WideFrequencyRange DLL Supporting Fast Frequency Scaling In this paper, we present a cellbased widefrequencyrange DLL supporting clock frequencies from 10MHz to 1GHz in 90nm. To support fast locking (during frequency scaling), we present novel architecture with a socalled xe2x80x9cfastlocking modexe2x80x9d  in which the control code for the LongRange Delay Block (LRDB) can be quickly determined in a way that the overall delay across the underlying DLL can be roughly one or multiple clock cycle times of the input clock signal. One can use this LRDB as a common building block and integrate it with any arbitrary narrowrange DLL for DVFS (Dynamic Voltage and Frequency Scaling) applications while achieving fast frequency scaling. The functionality is validated by postlayout simulation using a 90nm CMOS process. With the proposed scheme, the longrange locking time can be reduced significantly from 24% to 98%, respectively, for different input clock frequencies.

DNNLibGen: Deep Neural Network Based Fast Library Generator We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is nonlinear, nonmonotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving timetomarket goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required signoff corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a xe2x80x98single modelxe2x80x99 to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed librarygenerator uses a novel intercorner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intracorner model, to generate dense 8x8 delay tables using delays from 10 slewload points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization runtime for early milestones by upto 60%.