Fast search blockmatching motion estimation algorithm using FPGA Many fast search blockmatching motion estimation (BMME) algorithms have been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose a new regular fast search blockmatching motion estimation algorithm named Two Step Search (2SS). The 2SS BMME will then be implemented by 8 Xilinx XC6216 finegrain, seaofgate FPGA chips. The experimental and simulation results show that it can have better algorithmic performance and can be implemented by FPGA chips very costeffectively for video compression applications. Also, the 30 flames per second real time 2SS BMME video compression can be obtained by using eight Xilinx XC6216 FPGAs.

Adaptive Fast Matching Algorithm based on Subblock Ordering In this paper, adaptive fast matching algorithms are proposed based on the subblock ordering. Proposed two algorithms for the lossless fast matching only reduce the unnecessary matching complexity of motion estimation in the video coding. By observing the expectation of the sum of absolute differences between the current subblock and a reference subblock in the pixel domain, we derive an absolute difference model which indicates the relationship between the subblock distortion and the intra subblock complexity. In the same way, we consider the inter complexity among all subblock with the absolute difference model. From the absolute difference model, we derive the transform coefficient model for measuring the subblock complexity in the transform domain based on the Parsevalu0027s theorem. Experimental results show the proposed fast matching algorithms reduce the unnecessary complexity of the full search algorithm about 20% on average without any loss of image quality.