A Coprocessor for Realtime Motion Estimation in HD Video Coding This paper presents a motion estimation coprocessor, supporting realtime high definition (HD) video coding. The proposed coprocessor employs a 2D datareusing processing element array and a multistandard cost comparator for distortion computation of variable size block. An instructionset suitable for performing various ME algorithms is developed, providing the flexibility needed for different coding standards and various applications. In 0.13 xcexbcm CMOS technology, the coprocessor is implemented with 303K gates at operating frequency of 550MHz. A performance comparison to the reference architectures reveals that only the proposed processor can provide the processing capacity for 1920 xc3x97 1080, 60 fps video sequences at 33xc3x9733 search window.

Fast search blockmatching motion estimation algorithm using FPGA Many fast search blockmatching motion estimation (BMME) algorithms have been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose a new regular fast search blockmatching motion estimation algorithm named Two Step Search (2SS). The 2SS BMME will then be implemented by 8 Xilinx XC6216 finegrain, seaofgate FPGA chips. The experimental and simulation results show that it can have better algorithmic performance and can be implemented by FPGA chips very costeffectively for video compression applications. Also, the 30 flames per second real time 2SS BMME video compression can be obtained by using eight Xilinx XC6216 FPGAs.