An Iterative Technique for Runtime Efficient HardwareSoftware Partitioning The increasing popularity of FPGAbased devices for applications of different size and complexity calls for runtime efficient hardwaresoftware partitioning techniques with high levels of accuracy. However, the prohibitively large design space during partitioning makes this task a challenging one, leading to restrictions on the design space at the cost of accuracy. In this work, we propose an iterative technique for runtime efficient hardwaresoftware partitioning based on a divide and conquer algorithm. The proposed techniques have been evaluated using applications from the CHstone benchmark suite with accuracy of 94% and 99% compared to implementation and an exhaustive technique respectively, with significantly low runtimes.

UltraShare: FPGAbased Dynamic Accelerator Sharing and Allocation Despite all the available commercial and opensource frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators, sharing accelerators among multiple applications, and providing a nonblocking congestionfree environment for multiple applications to call multiple accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a nonblocking congestionfree environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.