Design and Analysis of high robustness dual direction SCR with heavily doping in NType Well In this paper, a modified high failure dualdirection siliconcontrolled rectifier (DDSCR) is proposed and fabricated in a 0.5xc2xb5m highvoltage bipolarCMOSDMOS (BCD) technology for ESD protection in 12 V operation voltage application. The operation principle and working mechanism are analyzed by 2D device simulation, and the TLP results are in accord with simulation results. According to the transmission line pulsetesting results, the failure current of the proposed multifinger device is greatly improved from 6.04 A (traditional DDSCR) to 10.02 A (DDSCR_N) or 8.82 A (DDSCR_P). The two structures lead to different current paths, and the influence on the targets of ESD design window is analyzed. DDSCR_N has the best FOM for effectively improving failure current without increasing the area of the layout.

Optimization of High Reliability and Wide SOA 100 V LDMOS Transistor with Low Specific OnResistance We proposed a wide SOA and high reliability 0.35 xc2xb5m CMOS compatible 100 V dual RESURF LDMOS transistor with low switching loss and low specific onresistance for automotive applications. This paper describes how much production tolerances for the mask alignment and the net dose of the gateside Ptype buried layer for dual RESURF of the proposed device affect electrical characteristics. TCAD simulations verified that the mask alignment tolerance is xc2xb1 50 nm, and the net dose tolerance is xc2xb1 40 %, which are possible enough in mass production. Within the range of the tolerances, the device maintains top level characteristics (breakdown voltage BV DS   132 V and specific onresistance R on,sp   150 mxcexa9mm2) with keeping high hot carrier endurance and wide SOA.