A 30MHz DelayLineBased Buck Converter with 5.7%94.8% Switching Duty Cycle As the switching frequency of DCDC converters continues to increase, the influence of circuit delays is also increasing, which poses a great challenge to the design of a comparator. A 30MHz delaylinebased buck converter is proposed in this paper, which eliminates the need for a traditional PWM comparator, simplifies the complexity of the circuit and logic and solves a series of problems caused by comparator delays at high switching frequency. A delaylinebased voltagetodutycycle (V2D) controller is used to replace the traditional rampcomparatorbased V2D controller to achieve a wider duty cycle range. The proposed DCDC converter has been designed and simulated by Cadence software based on the 0.18xc2xb5m mixed signal CMOS process. The tunable duty cycle ranges from 5.7% to 94.8%, allowing the converter to regulate the output from 0.1V to 1.7V with 1.8V input. With a step of 400mA in the load current, the setting time is around 2xc2xb5s. The maximum load current is 1A and the peak efficiency is as high as 94.5% with 1.5V output.

Digital Low Power Mode Control Technique for HighFrequency Synchronous DCDC Buck Converters This paper presents a low power mode control technique for digitally controlled synchronous buck converters optimized for the heavy load regulation. The proposed control mode achieves compact area and low complexity thanks to an efficient logic partitioning and reuse of the digital controller. The inductor peak current is controlled with a predictive algorithm that does not require current sensing. A prototype of a digitally controlled synchronous 5xe2x80x940.9 V, 1.5 A buck DCDC converter that embeds the low power control technique is implemented. A custom IC in a 28nm CMOS process has been designed for the digital controller and the gate drivers. Experimental results indicate that the high efficiency range is extended, obtaining an efficiency improvement up to 43% at light load.