A Tilebased FusedLayer Approach to Accelerate DCNNs on LowDensity FPGAs Accelerating Deep Convolutional Neural Networks on FPGAs is achieving a lot of interest across a wide range of applications such as image recognition and classification. Although memory requirement still represents a challenge for fast and efficient inference workloads, fusedaccelerated layers have been recently proposed to mitigate memory bandwidth problems. In this scenario, we propose a tiledbased fusedlayer approach to exploit temporal and spatial locality in mapping a DCNN to a specialized lowdensity FPGA. In our tilebased approach, we propose applying a fusing depth of two convolutional layers in order to fit into a lowdensity FPGA without affecting the performance, while reducing the memory bandwidth. We demonstrated the effectiveness of our twofused layer approach to accelerate the VGG16 network on a Zynq7020. We achieved an average speedup of 1.44x times, while saving up to 61% of memory transactions with respect to a baseline represented by tiledonly (notfused) version. A tiledbased fullyfused version of VGG16 would not have been feasible to be mapped on a lowdensity Zynq7020.

An OpenCLBased Hybrid CNNRNN Inference Accelerator On FPGA Recently, Convolution Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and CNNRNN hybrid networks have demonstrated great success in many deep learning scenarios. Although many dedicated FPGA accelerators for a certain kind of network have been proposed, few of them combine CNN and RNN acceleration together. In this paper we propose a highthroughput and resourceefficient CNNRNN fusion accelerator on FPGA with commercial OpenCL to support generalpurpose DNNs. It utilizes a novel streaming architecture and mapping strategy to implement the most computationintensive and resourcedemanding parts in DNNs on the same computation logic. By such a hardware reuse method, it realizes resource efficiency in accelerating CNNs, RNNs and their hybrid networks. Our accelerator follows a layerbylayer, subgraphbysubgraph or subnetworkbysubnetwork execution mode, which facilities it to deploy most DNNs flexibly during runtime with best performance. YOLOv2, LSTM and CRNN are tested with our work on Intel Arria10 GX1150 FPGA. It achieves 646 GOPS throughput on CRNN, which is the best performance on CNNRNN hybrid networks among highlevelsynthesis (HLS) based FPGA accelerators. Moreover, its throughput for CNNs and RNNs is competitive to the stateoftheart specialized FPGA accelerators.