Optimized SIKE Round 2 on 64bit ARM In this work, we present the first highlyoptimized implementation of Supersingular Isogeny Key Encapsulation (SIKE) submitted to NISTxe2x80x99s second round of post quantum standardization process, on 64bit ARMv8 processors. To the best of our knowledge, this work is the first optimized implementation of SIKE round 2 on 64bit ARM over SIKEp434 and SIKEp610. The proposed library is explicitly optimized for these two security levels and provides constanttime implementation of the SIKE mechanism on ARMv8powered embedded devices. We adapt different optimization techniques to reduce the total number of underlying arithmetic operations on the filed level. In particular, the benchmark results on embedded processors equipped with ARM CortexA531.536 GHz show that the entire SIKE round 2 key encapsulation mechanism takes only 84 ms at NISTxe2x80x99s security level 1. Considering SIKExe2x80x99s extremely small key size in comparison to other candidates, our result implies that SIKE is one of the promising candidates for key encapsulation mechanism on embedded devices in the quantum era.

Implementing and Benchmarking Three LatticeBased PostQuantum Cryptography Algorithms Using SoftwareHardware Codesign It has been predicted that within the next tenfifteen years, quantum computers will have computational power sufficient to break current publickey cryptography schemes. When that happens, all traditional methods of dealing with the growing computational capabilities of potential attackers, such as increasing key sizes, will be futile. The only viable solution is to develop new standards based on algorithms that are resistant to quantum computer attacks and capable of being executed on traditional computing platforms, such as microprocessors and FPGAs. Leading candidates for new standards include latticebased postquantum cryptography (PQC) algorithms. In this paper, we present the results of implementing and benchmarking three latticebased key encapsulation mechanisms (KEMs) that have progressed to Round 2 of the NIST standardization process. Our implementations are based on a softwarehardware codesign approach, which is particularly applicable to the current stage of the NIST PQC standardization process, where the large number and high complexity of the candidates make traditional hardware benchmarking extremely challenging. We propose and justify the choice of a suitable systemonchip platform and design methodology. The obtained results indicate the potential for very substantial speedups vs. purely software implementations, reaching 28x for encapsulation and 20x for decapsulation.