MultiContext TCAM Based Selective Computing Architecture for a LowPower NN In this paper, we propose an energyefficient hardware architecture that consists of multipliers and a nonvolatile MultiContext Ternary ContentAddressable Memory (MCTCAM), where a CMOSmagnetic tunnel junction (MTJ) deviceshybrid circuit technique is used. If the input data stored in MCTCAMs is appeared, the corresponding multiplication result is obtained from the MCTCAM, resulting in the energyefficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MCTCAM becomes small, which reduces power consumption in the MCTCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65nm CMOS and a MTJ model.

Novel smart card SoC memory architecture based on embedded STTMRAM In the applications of Internet of Things (IoT), the limitations of the common NVM  RAM hybrid memory architecture cannot simultaneously provided the solution of lower power, low resource consumption and nonvolatile which are critical for IoT designing. Spin Transfer Torque Magnetic Random Access Memory (STTMRAM) has become a major candidate for onchip memory because of its ideal memory characteristics, such as nonvolatile, near zero standby leakage power and compatibility with CMOS. Therefore, this paper focuses on the application of STTMRAM in the storage of IoT. We design the eSTTMRAM nonhybrid memory architecture for smart card SoCs. The prototype verification results on Xilinxu0027s ARTIX7 XC7A100T FPGA platform show that the STTMRAMbased memory architecture can greatly improve the operating efficiency of SoC programs and reduce the dynamic power consumption of the system due to data storage.