Machine Learningbased Prediction for Dynamic Architectural Optimizations Embedded system complexity is rapidly evolving, becoming more desktopsystemlike, requiring more complex optimization methods to adhere to more stringent design constraints (e.g., area, thermal pressures, performance, battery lifetime, etc.) given restricted resources, widely varying applications, and environmental stimuli. Configurable architectural parameters (e.g., voltage, frequency, pipeline depth, cache specifics, etc.) can be specialized to meet these applicationspecific constraints and requirements (e.g., available parallelism, cache locality and access patterns, etc.) based on the available resources (e.g., heterogeneous cores with different architectural parameters). Unfortunately, due to this environmentaland applicationdependent information, embedded system designers are challenged with meeting constraints and requirements with no a priori knowledge of this dynamic runtime information, which results in a very large dynamic design space. In this work, we propose a machinelearningbased method to meet these runtime optimization challenges using a fast and reactive methodology. Our methodology uses offline feature selection and neural network training to create a model that can be used online to predict the best configurable parameter values based on unknown runtime applications, environmental stimuli, resource availability, user expectations, etc. Without loss of generality, we propose a cache line size onlinedynamic prediction module. Results show that our prediction module achieves 86% and 91% classification accuracies, comparable to prior work, for predicting the instruction and data cache line sizes, respectively, and achieves average energy consumption optimizations within 1% of the applicationsxe2x80x99 optimal energy consumptions determined using exhaustive simulation.

Exploring the Training and Execution Acceleration of a Neural Network in a Reconfigurable Generalpurpose Processor for Embedded Systems Neural networks are getting more and more present in our daily lives. Whether to classify, optimize, or predict results, the use of neural networks proves to be a great and powerful choice to solve these problems. However, the time spent in the training process can be an issue. Although it can be accelerated by Graphics Processing Units (GPUs), coprocessors or even Field Programmable Gate Array (FPGA), these approaches may not be the best choices to improve training performance in embedded systems due to the large area and power consumption. In this paper, we present a customized instruction set architecture with fixedpoint arithmetic considering a lightweight general purpose processor in order to accelerate the training and execution of neural networks. Cadencexc2xae LX7 Processor and Xtensaxc2xae software are used to identify runtime bottlenecks and optimize specific pieces of hardware. Experimental results show that our proposed architecture achieves about 24X runtime reduction with respect to a floatingpoint implementation, and were compared against other architectures.