Motion estimation performance models with application to hardware error tolerance The progress of VLSI technology towards deep submicron feature sizes, e.g., sub100 nanometer technology, has created a growing impact of hardware defects and fabrication process variability, which lead to reductions in yield rate. To address these problems, a new approach, systemlevel error tolerance (ET), has been recently introduced. Considering that a significant percentage of the entire chip production is discarded due to minor imperfections, this approach is based on accepting imperfect chips that introduce imperceptibleacceptable systemlevel degradation; this leads to increases in overall effective yield. In this paper, we investigate the impact of hardware faults on the video compression performance, with a focus on the motion estimation (ME) process. More specifically, we provide an analytical formulation of the impact of single and multiple stuckatfaults within ME computation. We further present a model for estimating the systemlevel performance degradation due to such faults, which can be used for the error tolerance based decision strategy of accepting a given faulty chip. We also show how different faults and ME search algorithms compare in terms of error tolerance and define the characteristics of search algorithm that lead to increased error tolerance. Finally, we show that different hardware architectures performing the same metric computation have different error tolerance characteristics and we present the optimal ME hardware architecture in terms of error tolerance. While we focus on ME hardware, our work could also applied to systems (e.g., classifiers, matching pursuits, vector quantization) where a selection is made among several alternatives (e.g., class label, basis function, quantization codeword) based on which choice minimizes an additive metric of interest.

A Coprocessor for Realtime Motion Estimation in HD Video Coding This paper presents a motion estimation coprocessor, supporting realtime high definition (HD) video coding. The proposed coprocessor employs a 2D datareusing processing element array and a multistandard cost comparator for distortion computation of variable size block. An instructionset suitable for performing various ME algorithms is developed, providing the flexibility needed for different coding standards and various applications. In 0.13 xcexbcm CMOS technology, the coprocessor is implemented with 303K gates at operating frequency of 550MHz. A performance comparison to the reference architectures reveals that only the proposed processor can provide the processing capacity for 1920 xc3x97 1080, 60 fps video sequences at 33xc3x9733 search window.