Training Deep Neural Networks in LowPrecision with High Accuracy Using FPGAs Lowprecision training for Deep Neural Networks(DNN) has recently become a viable alternative to standard fullprecision algorithms. Crucially, lowprecision computation reduces both memory usage and computational cost, providing more scalability for Field Programmable Gate Arrays (FPGAs) with limited onchip memory. In this paper, we describe and test a prototype training accelerator for Zynq All Programmable System on Chip (APSoC) devices using predominantly 8bit integer numbers. Block floatingpoint quantisation and stochastic weight averaging techniques are applied during training toavoid any degradation in accuracy. Results of an implementation reveal memory savings and 17x speedups over processor only systems on several training tasks including the MNIST and CIFAR10 benchmarks, and online radiofrequency anomaly detection. Moreover, we propose modifications to the stochastic weight averaging lowprecision (SWALP) algorithm to achieve a0.5% accuracy improvement for the abovementioned benchmarks with results within 0.1% of floatingpoint. We suggest that both inference and training can be deployed in the same package for standalone embedded applications.

Static Block FloatingPoint Quantization for Convolutional Neural Networks on FPGA Convolutional neural networks (CNNs) have been widely applied in various computer vision and speech processing applications. However, the algorithmic complexity of CNNs hinders their deployment in embedded systems with limited memory and computational resources. This paper proposes static block floatingpoint (BFP) quantization, an effective approach involving KullbackLeibler divergence, to determine the static shared exponents. Without need for retraining, the proposed approach is able to quantize CNNs to 8 bits with negligible accuracy loss. An FPGAbased hardware design with static BFP quantization is also proposed. Compared with 8bit integer linear quantization, our experiments show that the hardware kernel based on static BFP quantization can achieve over 50% reduction in logic resources on an FPGA. Based on static BFP quantization, a tool implemented in the PyTorch framework is developed, which can automatically generate optimised configuration according to user requirements for given CNN models, where the entire optimization process takes only a few minutes on an Intel Xeon Silver 4110 CPU.