A PreRouting Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network The total wirelength of a circuit implementation is an important metric to evaluate the quality of an FPGA design flow. The wirelengths of all nets of a circuit are determined by routing, but prerouting stages like placement can use a wirelength prediction model to direct the generation of a placement solution with a shorter total wirelength for routing. The conventional VPR employs a wirelength prediction model based on the bounding box size and the number of sinks of a net, which works well for an FPGA of a regular 2D array structure. However, new FPGA architectures like 3DFPGA and hierarchical routing cannot use such a simple model. In this work, we propose a method to build an optimized net wirelength prediction model using a convolutional neural network, which can learn routing features from routed nets without manual tunings. The evaluation results show an optimized CNN model also has higher accuracy than the VPR model.

AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for DNN chips. However, designing DNN chips is nontrivial because: (1) mainstream DNNs have millions of parameters and operations; (2) the large design space due to the numerous design choices of dataflows, processing elements, memory hierarchy, etc.; and (3) an algorithmhardware codesign is needed to allow the same DNN functionality to have a different decomposition, which would require different hardware IPs to meet the application specifications. Therefore, DNN chips take a long time to design and require crossdisciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip  a DNN chip generator that can automatically generate both FPGA and ASICbased DNN chip implementation given DNNs from machine learning frameworks (e.g., PyTorch) for a designated application and dataset. Specifically, AutoDNNchip consists of two integrated enablers: (1) a Chip Predictor, built on top of a graphbased accelerator representation, which can accurately and efficiently predict a DNN acceleratoru0027s energy, throughput, and area based on the DNN model parameters, hardware configuration, technologybased IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selection, block configuration, resource balancing, etc.), optimize chip design via the Chip Predictor, and then generate optimized synthesizable RTL to achieve the target design metrics. Experimental results show that our Chip Predictoru0027s predicted performance differs from realmeasured ones by u003c 10% when validated using 15 DNN models and 4 platforms (edgeFPGATPUGPU and ASIC). Furthermore, accelerators generated by our AutoDNNchip can achieve better (up to 3.86X improvement) performance than that of expertcrafted stateoftheart accelerators.