Optimisation of System Throughput Exploiting Tasks Heterogeneity on Space Shared FPGAs There are challenges in optimising system throughput in FPGAbased cloud computing due to mapping constraints resulting in suboptimal space sharing of resources, as the number of tasks grow and become more heterogeneous. This work proposes a methodology for exploring and optimising their resource utilisation. By identifying highlevel synthesis parameters for each task, machine learning models and intelligent clustering are then employed to define clusters of tasks which will share the FPGA space. Assuming heterogeneity characterisation of tasks and thus static partitioning of the FPGA, it is ensured that each task in a cluster accommodates other tasksu0027 resource requirements resulting in a higher compute density. Using 11 high performance computing tasks, we achieve an average 3.3xc3x97 higher system throughput at 2.8xc3x97 better energy efficiency when compared to existing approaches.

SkyCastle: A ResourceAware MultiLoop Scheduler for HighLevel Synthesis A common optimisation problem in the highlevel synthesis (HLS) of FPGAbased accelerators is to find a microarchitecture that maximises the performance while keeping the utilisation of the deviceu0027s lowlevel resources below certain limits. We propose to tackle it directly as part of the HLS scheduler. To that end, we formalise a general, integrated scheduling and allocation problem for HLS kernels, and present SkyCastle, a novel resourceaware multiloop scheduler using integer linear programming to solve it for a subclass of kernels composed of multiple, nested loops. In order to demonstrate the practical applicability of the approach, we model the scheduler in such a way as to be plugin compatible with the Xilinx Vivado HLS engine, allowing the computed solutions to be fed back into its synthesis flow. We evaluate SkyCastle for three nontrivial kernels from the machine learning, signal processing, and physical simulation domains, on two FPGA devices. Additionally, we investigate the replication of slightly slower, but smaller accelerators as a means to further boost the overall performance. In contrast to Vivado HLSu0027 default settings, which aim at maximum performance but may fail in later synthesis steps, the solutions computed by our scheduler always result in synthesisable designs.