SET sensitivity evaluation, a comparison before and after layout Single Events Transient can be a serious issue in safetycritical applications. Therefore, before the manufacturing process, an evaluation of the sensitivity of the whole circuit must be carried out to diagnose the most sensitive nodes and to assess the global sensitivity of the circuit. In this work we evaluate the importance of layout parasitics on the results of such an evaluation. Relying on a high performance buffer as a case of study, it will be shown that SET simulations at schematic level can be used for diagnosis and hardening purpose but that simulations should include both resistive and capacitive parasitics to reliably assess the global circuit sensitivity.

Low Cost and High Performance Radiation Hardened Latch Design for Reliable Circuits With decreasing device dimension, the susceptibility of transistors and circuits to external noise sources increase especially in radiative environments. In this work, a radiation hardened latch based on NMOS only Schmitt trigger with voltage booster (NSTVB) is proposed. We first analyze the critical charge at the internal nodes of different latch designs to identify the most sensitive node. By doing so our results reveal that the proposed circuits show highest robustness to single event transients, compared to reference designs. Furthermore, the results show that the critical charge decreases with temperature and increases for higher supply voltages, and it is further observed that the critical charge decrement with temperature variation, exhibiting best performance for the NSTVB based latch compared to others circuits. For the validation of proposed latch, a figure of merit, i.e. the charge to power delay area product ratio (QPAR), considering the most important performance parameters is calculated. We clearly observe that the proposed latch exhibits significantly enhanced performance as compared to existing designs.