Hardware Design of Transaction Device based on Contact and Contactless Smart Card In this paper, we design and implement the transaction device based on two operation methods, i.e., with contact and without contact with smart cards. The system can be divided into three parts: hardware (transaction device), software (transaction application), and server. In this work, we focus on the hardware design that comprises smart card reader hardware, LCD display  touch panel, and battery charger circuit. ATMEGA 328P was chosen as a data exchange controller between the smart card and smart card reader. In contrast, the Raspberry Pi 3 Model B (singleboard computer) was utilized as an application processor due to several features offered, such as IO, graph processing unit, and enough memory. Our electronic transaction device can be connected to the thermal printer. Therefore, the transactions report (e.g., Topup, balance check, payment activity, and so on) can be printed out. The developed device has a tiny dimension and lightweight to carry, hence it can be categorized as a portable device (easily moved everywhere).

Novel smart card SoC memory architecture based on embedded STTMRAM In the applications of Internet of Things (IoT), the limitations of the common NVM  RAM hybrid memory architecture cannot simultaneously provided the solution of lower power, low resource consumption and nonvolatile which are critical for IoT designing. Spin Transfer Torque Magnetic Random Access Memory (STTMRAM) has become a major candidate for onchip memory because of its ideal memory characteristics, such as nonvolatile, near zero standby leakage power and compatibility with CMOS. Therefore, this paper focuses on the application of STTMRAM in the storage of IoT. We design the eSTTMRAM nonhybrid memory architecture for smart card SoCs. The prototype verification results on Xilinxu0027s ARTIX7 XC7A100T FPGA platform show that the STTMRAMbased memory architecture can greatly improve the operating efficiency of SoC programs and reduce the dynamic power consumption of the system due to data storage.