An Efficient Cryptosystem based on the LogisticChebyshev Map We utilise the LogisticChebyshev map as a cascade discretetime chaotic system to design a new form of a cryptosystem. Based on the LogisticChebyshev map, we present a novel method for constructing substitution boxes or Sboxes. The performance of the proposed Sbox scheme is investigated. Our results shows that the constructed Sbox has significant qualities for viable applications in security related domains. Additionally, we utilise a new pseudorandom number generator (PRNG) scheme for the purpose of generating keystreams for further encryption. We utilise this technique to demonstrate how a PRNG based chaotic system can be utilsied for image encryption. Our simulation results and analysis show that the proposed scheme has efficient performance for cryptographic based image processing applications.

A Digital Pseudo Random Number Generator Based on a Chaotic Dynamic System Chaotic based Pseudo Random Number Generators (PRNGs) have been very popular due to their unpredictable behavior. Hardware implementations of PRNG is used in many applications including cryptography, security and communication systems. Chaotic systems demonstrate an extreme sensitivity to variations in initial conditions and control parameters which makes it ideal for such applications especially cryptography. Due to this severe sensitivity, it is essential to implement the system with a sufficient accuracy while keeping the hardware cost as low as possible. An efficient and compact digital design is proposed for a PRNG based on a lowdimensional chaotic dynamic system. In this design, CORDIC algorithm has been used to reduce the hardware cost while maintaining the accuracy high. Experimental results and error measurements indicate a maximum error of 0.011 and RMSE of 0.0015 between the proposed digital circuits and the original chaotic system. The circuits have been synthesized for an Altera FPGA board. The results indicate that the circuits are successfully able to mimic the mathematical simulation counterpart. In addition, synthesis results verify that the proposed circuits take less than 1% of the target FPGA resources. Furthermore, Static Timing Analysis demonstrate a maximum frequency of 172.09 MHz for the proposed circuits. The proposed circuits can be employed in cryptography and security applications due to their compactness and high accuracy.