Improving Memory Access Locality for Vectorized BitSerial Matrix Multiplication in Reconfigurable Computing Lowprecision matrix multiplication has gained significant interest in the research community due to its applicability in the quantized neural network domain. As a result, a multitude of variable precision hardware designs have been proposed since fixedprecision hardware causes underutilization of the hardware resources due to the low and varying precision in such applications. Bitserial hardware takes advantage of the frugal nature of bitserial computations that can operate on only as many bits as necessary. A bitserial matrix multiplication consists of a summation of weighted binary matrix multiplications. In this work, we study the inherent locality of bitserial matrix multiplications and propose a localityaware scheduling algorithm that eliminates redundant data fetches from memory. The proposed schedule improves with up to 76% compared to a schedule that computes each binary matrix multiplication in sequence.

Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration Implementations of hardware accelerators for neural networks are increasingly popular on FPGAs, due to flexibility, achievable performance and efficiency gains resulting from network optimisations. The long compilation time required by the backend toolflow, however, makes rapid deployment and prototyping of such accelerators on FPGAs more difficult. Moreover, achieving high frequency of operation requires significant lowlevel design effort. We present a neural network overlay for FPGAs that exploits DSP blocks, operating at near their theoretical maximum frequency, while minimizing resource utilization. The proposed architecture is flexible, enabling rapid runtime configuration of network parameters according to the desired network topology. It is tailored for lightweight edge implementations requiring acceleration, rather than the highest throughput achieved by more complex architectures in the datacenter.