Implementation of Yolov2 Image Recognition and Other Testbenches for a CNN Accelerator An implementation of Yolov2 image recognition and other testbenches for a deep learning accelerator is presented. This chip is the initial version of our ongoing effort for a higher performance accelerator development. The accelerator is based on a systolic array and can handle convolution and maxpooling layer in a combined way or separately using 16 bit floatingpoint data. It also supports innerproduct and LSTM layers. For demonstration and as one of the design verification testbenches, we implemented Yolov2 image recognition for 80 object classes. We converted the Yolov2 software to 16 bit floating point version and used it in the simulation and FPGA experiment during the chip development. Several other testbenches were designed and used to test various networks. In this paper, the acceleratorxe2x80x99s architecture and the Yolov2 implementation on our FPGA board including camera and LCD is explained, including the software implementation. Some analyses on the measured and estimated performance is shown.

An OpenCLBased FPGA Accelerator for Compressed YOLOv2 Convolutional neural networks (CNNs) are widely used in computer vision applications. GPU has been the mainstream accelerator for CNNs. Compared with GPU, FPGA has the advantages of high flexibility, low power consumption and abundant DSP resources, which make it possible to surpass GPU in some scenarios. The recent progress of high level synthesis tools greatly improves the development efficiency of FPGA. In this paper, an OpenCLbased CNN accelerator is designed for FPGA and a variety of model compression techniques are applied to the YOLOv2 model. The accelerator uses the Winograd algorithm to implement convolution efficiently and solves the unaligned global memory access issue caused by the Winograd algorithm with an alignment stream buffer. This design makes full use of the available memory access bandwidth and utilizes all the available DSP resources. Parallelism is exploited in various dimensions for optimal performance. The performance of our FPGA design can reach 10 ms per image in terms of latency, compared to 15 ms per image with an nVidia P100 GPU. We plan to make our design open source so that the community can benefit from it and contribute to it together.