Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels In fields of image processing and neural network, increasing amount of data and complex functions are making circuits precise. This makes errors in circuits relatively large. When upper bits of binary signals flip due to noise, the value will increase or decrease drastically. On the other hand, if stochastic numbers are used, the changes on their values are the same since all the bits have the same weight. Therefore, stochastic computing, a computation method based on stochastic numbers, is attracting interest. Stochastic computing does have error tolerance, but cannot restore the bit stream if the bits are erroneous. Here, we focus on evaluating the errorfree value from the bit error rate and the erroneous value. We have proposed a method to correct errors of stochastic numbers by measuring the bit error rate and filtering the values properly in symmetric channels. In this paper, we propose a method that can also correct errors in Z channels as well as symmetric channels. From experimental evaluations, in environment with high bit error rate, this proposal will give a better peaksignaltonoise ratio compared with a conventional error correction coding.

AreaEfficient Parallel Stochastic Computing with Shared Weighted Binary Generator Stochastic computing (SC), a computing paradigm with strong fault tolerance, draws more attention recently. However, a drawback of SC is its long latency. One straightforward way to reduce the latency is to use parallel bit streams to encode data and apply multiple copies of the circuit to process the bit streams. However, this method multiplies the circuit area. In this work, we propose to share the random numbers sources (RNSs) and part of the probability conversion circuits (PCCs) to reduce the area of the parallel version of the stochastic circuit. In this work, we propose a method to share the weighted binary generatorbased stochastic number generator to reduce the area of the parallel implementation of the stochastic circuit. Our experimental results showed that the accuracy of our design is slightly better than the traditional comparatorbased design. Besides, our design can reduce the arealatency product by 58.5% compared to the serial implementation.