FPNet: Customized Convolutional Neural Network for FPGA Platforms The Convolutional Neural Network (CNN) has been widely adopted in various applications, which include object detection mobile robot vision, image search engine, etc. And due to the computingintensive and memoryintensive features of CNN models, specialized hardware accelerators, like ApplicationSpecificIntegratedCircuit (ASIC) and Field Programmable Gate Arrays (FPGA) have been widely utilized in edge devices. Among all the neural network specialized hardware accelerators, an FPGA accelerator stands out for its flexibility, short timetomarket, and energy efficiency. Previous works about FPGA accelerator designs are mostly changing hardware configuration to fit the CNN model structure. In this paper, we propose an automated neural network architecture search approach utilizing reinforcement learning to design customized convolutional neural network model for specialized FPGA platforms.

PowerAware FPGA Mapping of Convolutional Neural Networks With an unprecedented accuracy in numerous AI tasks, convolutional neural networks (CNNs) are rapidly deployed on powerlimited mobile and embedded applications. Existing mapping approaches focus on achieving high performance without explicit consideration of power consumption, leading to suboptimal solutions when power is considered in a subsequent stage. In this context, there is an emerging need for poweraware methodologies for the design of custom CNN engines. In this work, a methodology is presented for modelling the power consumption of FPGAbased CNN accelerators using a highlevel description of modules, together with a powercentric search strategy for exploring powerperformance tradeoffs within the CNNtoFPGA design space. By integrating into an existing CNNtoFPGA toolflow, the proposed power estimation method can yield a prediction accuracy of 93.4% for total system power consumption. Furthermore, it is demonstrated that the associated poweroriented exploration approach can generate CNN accelerators with a 20.1% power reduction over a purely throughputdriven design for AlexNet, maintaining the designu0027s throughput.