A Hardwareefficient Accelerator for Encoding Stage of Texttospeech Synthesis Texttospeech synthesis is a promising human computer interaction technology. Google launched the TTS model Tacotron, which can directly convert raw text to speech. The encoder module is one of the most important components of Tacotron. It extracts context features in the text and generate time series. The encoder module contains Recurrent Neural Network (RNN) and Convolutional Neural Network (CNN). There are few hardware accelerators to support these hybrid algorithm and the parallel architecture calculations. To this end, we designed a hardwareefficient accelerator to accomplish the complex computing tasks. We quantify the network model to reduce hardware overhead while using parallel hardware structures to increase operating speed. The encoder accelerator can process 2903 bits data per second with 3.627W. Compared to Titan X, the energy efficiency ratio is 71 times higher.

An OpenCLBased Hybrid CNNRNN Inference Accelerator On FPGA Recently, Convolution Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and CNNRNN hybrid networks have demonstrated great success in many deep learning scenarios. Although many dedicated FPGA accelerators for a certain kind of network have been proposed, few of them combine CNN and RNN acceleration together. In this paper we propose a highthroughput and resourceefficient CNNRNN fusion accelerator on FPGA with commercial OpenCL to support generalpurpose DNNs. It utilizes a novel streaming architecture and mapping strategy to implement the most computationintensive and resourcedemanding parts in DNNs on the same computation logic. By such a hardware reuse method, it realizes resource efficiency in accelerating CNNs, RNNs and their hybrid networks. Our accelerator follows a layerbylayer, subgraphbysubgraph or subnetworkbysubnetwork execution mode, which facilities it to deploy most DNNs flexibly during runtime with best performance. YOLOv2, LSTM and CRNN are tested with our work on Intel Arria10 GX1150 FPGA. It achieves 646 GOPS throughput on CRNN, which is the best performance on CNNRNN hybrid networks among highlevelsynthesis (HLS) based FPGA accelerators. Moreover, its throughput for CNNs and RNNs is competitive to the stateoftheart specialized FPGA accelerators.