PowerGating Models for Rapid Design Exploration Power gating (PG) is an effective method to reduce leakage currents in an SoC design during runtime. It dynamically shuts down components using a network of sleep transistors but requires a detailed analysis to scale this network appropriately with respect to area wakeup time inrush currents voltage drops and transition energies. In this paper we present a method to efficiently determine these key parameters for any SoC design and sleep transistor network at gatelevel to enable the rapid exploration of power design alternatives while providing sufficient accuracy for highlevel design exploration. Compared to SPICE our approach achieves a speedup of up to 11457x for two ISCAS circuits a 32bit multiplier and a RISCV core each build for a 90nm PDK. The average error compared to SPICE is 2.6% for peak current and 10% for wakeup energy and delay.

A Machine Learning Approach for Power Gating the FPGA Routing Network Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in routing network into powergating regions. In this paper, we propose a fundamentally different approach based on Kmeans clustering, an algorithm commonly used in machine learning. Experimental results on Titan benchmarks and StratixIV FPGA architecture show that our proposed clustering algorithms outperform the state of the art. For example, for 32 powergating regions in FPGA routing switch matrices, we achieve (on average) almost 1.4xc3x97 higher savings (37.48% vs. 26.94%) in the static power consumption of the FPGA routing resources at lower area overhead than the most efficient heuristic published so far.