A 34fJbit 20Gbs 18rate ChargeSteering DFE for IoT Applications The need for receiver equalization in wireline communication systems has increased with the large increase in data rates. There are two main categories for equalizers; continuoustime linear equalizers and nonlinear equalizers implemented as decision feedback equalizers (DFE). Most DFEs use halfrate or quarterrate architectures. The DFE proposed in this paper, however, uses a 18rate architecture to relax the timing constraints and reduce power consumption. This paper presents the design of a 1tap 20Gbs chargesteering 18rate DFE in a 65nm CMOS technology. The proposed DFE consumes 0.68mW from a 1V supply and compensates for 7dB channel loss at Nyquist when processing 20Gbs data.

A 32Gbs 3.53mWGbs Adaptive Receiver AFE Employing a Hybrid CTLE, EdgeDFE and Merged DataDFECDR in 65nm CMOS A 32Gbs adaptive receiver analog frontend (AFE) with a hybrid continuoustime linear equalizer (CTLE), a halfrate distributed edge and data decision feedback equalizer (DFE) and a clock data recovery (CDR) is presented. The hybrid CTLE counters the lowfrequency as well as the highfrequency loss of 21 dB at Nyquist. Further postcursors can be solved by using a half rate, distributed 3tap edgeDFE and 2tap dataDFE, which is partially embedded in the CDR. The distributed DFE scheme addresses the inter symbol interference (ISI) at the edge and reduces the data jitter while dataDFE guarantees the vertical opening of the data eye. Fabricated in 65nm CMOS, occupying an active area of 0.3 mm2, the proposed prototype demonstrates an improvement of 0.15 UI in the horizontal eye opening of the data output at a receiver AFE with the conventional 5tap dataDFE at BER10xe2x88x9212, under a pseudorandom binary sequence (PRBS) of 2311. The competitive power efficiency of 3.53 mWGbs is measured with a supply voltage of 1.2 V.