Efficient Testing of Physically Unclonable Functions for Uniqueness Physically unclonable functions (PUFs) have emerged as lightweight hardware security primitives for implementing secure authentication. Strong PUFs rely on random manufacturing process variation to create unique Boolean mappings from input (challenge) to output (output). For secure authentication, challenge to response mappings are required to be unique for each device. However, uniqueness is not guaranteed by design or manufacturing. Testing for uniqueness and weeding out nonunique parts are the only way to ensure uniqueness of devices. Uniqueness testing can be expensive in time as the challengeresponses of the N th device undertest, must be proven to be different from previously tested N  1 devices, or the device must be discarded. To reduce the time complexity of uniqueness testing, MultiIndex hashing (MIH) was proposed for online testing in high volume manufacturing. Database search using MIH was shown to be fast, but it suffers from high memory cost. In this paper, we address the memory problem of MIH based uniqueness testing by proposing alternative MIH strategies. Our results indicate that the proposed search strategies can significantly reduce the memory cost without sacrificing performance, requiring xe2x89x88 3.35xc3x97 less memory with just a 17% performance overhead when testing the uniqueness of 1 million PUFs.

Extensive Examination of XOR Arbiter PUFs as Security Primitives for ResourceConstrained IoT Devices Communication security is essential for the proper functioning of the Internet of Things. Traditional approaches that rely on cryptographic keys are vulnerable to sidechannel attacks. Physical Unclonable Functions (PUFs), leveraging unavoidable and irreproducible variations of integrated circuits to produce responses unique for individual PUF devices, are emerging as promising candidates as security primitives to provide keyless solutions. Before a PUF can be adopted for real applications, the PUF must be thoroughly examined to understand its various properties for its application feasibility. In this paper, we study XOR PUFs for broad ranges of values for circuit architecture parameters. XOR PUFs have been extensively studied, and have been shown to be unable to withstand machine learning attacks for 64bit XOR PUFs with less than ten component PUFs. Attack methods employed in existing studies need a large number of challengeresponse pairs (CRPs), which are obtainable only if the PUF has an open access interface. When PUFembedded devices equipped with mutual authentication or response obfuscating techniques, it is difficult for attackers to accumulate large numbers of CRPs. With only a small number of accumulated CRPs available to attackers, small size PUFs, like XOR PUFs with a small number of component PUFs and stages, may become resistant to machine learning attacks. Since smaller sizes mean less resourcedemanding, it is worthwhile to examine such PUFs which have usually been considered unsafe against attacks. Such are thoughts that have been motivating us in this paper to explore the PUF performances for a wide range of values of the PUF architecture parameters.