Evolved Binary Neural Networks Through Harnessing FPGA Capabilities The exponential progress of semiconductor technologies has enabled the proliferation of deep learning as a prominent area of research, where neural networks have demonstrated its effectiveness to solve very hard multi dimensional problems. This paper focuses on one in particular, Binary Neural Networks (BNN), which use fixed length bits in its connections and logic functions to perform excitation operations. Exploiting those characteristics, hardware accelerators that integrate fieldprogrammable gate arrays (FPGAs) have been adopted to hasten inference of deep learning networks, given its proficiency to maximize parallelism and energy efficiency. This work will show how the algorithm Binary Spectrumdiverse Unified Neuroevolution Architecture (BiSUNA) can perform training and inference on FPGA without the need of gradient descent. Source code can be found in github.comrval735bisunaocl

HBUNN  Hybrid BinaryUnary Neural Network: Realizing a Complete CNN on an FPGA Most modern neural networks use the basic MultiplyAccumulate (MAC) Operation in some form or another, and as networks get larger, the computational needs for these larger networks grow rapidly. Typically neural networks implemented on FPGAs use variable multipliers so that any weight can be used in the MAC, but this also forces the accelerator designer to store the weights of the model in offchip memory (DRAM). Moreover, because of high computational power and high memory bandwidth requirements of todayu0027s CNNs, it is harder for FPGA platforms to deliver the best performance. In this paper, we propose a fully parallelpipeline Hybrid BinaryUnary Neural Network (HBUNN) architecture to implement a lowcost and highperformance ResNet18 convolutional neural network. We use a hybrid binaryunary method to implement constantcoefficient multipliers and batch normalization units. These two units reduce hardware cost by 30.7% and 47.97% on average compared to the conventional binary equivalent, respectively. Moreover, we propose a novel training scheme using our hardware costaware regularizers that not only improves the area cost of the proposed architecture and the conventional binary architecture by 59.3% and 76.7% respectively, but also maintains the same accuracy. Finally, we have implemented three trained networks using different regularizers. The proposed HBUNN architectures reduce the area cost by 30%, and the area xc3x97 delay cost by 69% on average compared to the conventional binary architectures. The error rate of the proposed work is 12.93%, while its throughput is 278 Kfps.