An Efficient Accelerator for Sparse Convolutional Neural Networks In this paper, we propose a sparse convolutional neural network accelerator design on FPGAs. Similar to the DNNWEAVER architecture, our accelerator uses twolevel hierarchy: multiple Processing Units (PUs) and each PU comprises a set of Processing Elements (PEs). To address the irregularity of sparse neural networks, we introduce a novel sparse dataflow for sparse CNN computing as well as weight merging method to balance the computation load on different PUs for better overall efficiency. We implement our design with 32 PUs and 14 PEs in each PU. When compared with DNNWEAVER on VGG16 network, our accelerator achieves 3.49x speedup and 3.05x energy saving on average when running at 150MHz on a Xilinx ZC706 board and reaches the speed of 400 GOPS.

A Tilebased FusedLayer Approach to Accelerate DCNNs on LowDensity FPGAs Accelerating Deep Convolutional Neural Networks on FPGAs is achieving a lot of interest across a wide range of applications such as image recognition and classification. Although memory requirement still represents a challenge for fast and efficient inference workloads, fusedaccelerated layers have been recently proposed to mitigate memory bandwidth problems. In this scenario, we propose a tiledbased fusedlayer approach to exploit temporal and spatial locality in mapping a DCNN to a specialized lowdensity FPGA. In our tilebased approach, we propose applying a fusing depth of two convolutional layers in order to fit into a lowdensity FPGA without affecting the performance, while reducing the memory bandwidth. We demonstrated the effectiveness of our twofused layer approach to accelerate the VGG16 network on a Zynq7020. We achieved an average speedup of 1.44x times, while saving up to 61% of memory transactions with respect to a baseline represented by tiledonly (notfused) version. A tiledbased fullyfused version of VGG16 would not have been feasible to be mapped on a lowdensity Zynq7020.