OpenCL Implementation of Cannonxe2x80x99s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannonu0027s matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a twolevel block algorithm, where the lower level submatrices are multiplied using our Cannonu0027s algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.

Benchmarks for FPGATargeted HighLevelSynthesis Recently, highlevel synthesis (HLS) tools such as Intel FPGA SDK for OpenCLu0027 and Xilinx SDAccel have been introduced to design FPGA accelerators. Those HLS tools use C language based environment to significantly reduce the design time. However, it is also important to know how much performance we can achieve using HLS tools. FPGA is a highly reconfigurable hardware and the performances are extremely different depending on the architecture. Performances also depend on the FPGA board, HLS software and firmware such as BSP (board support package). Therefore, benchmarking FPGAs is an extremely challenging task. This paper proposes a method to design benchmarks for FPGAtargeted HLS. The benchmarks are highly scalable and can be used for different FPGAs and compilers to obtain most of the potential performance. Evaluating four different FPGAs, we found that the singleprecision floatingpoint computation performance varies from 17 GFLOPS to 3,955 GFLOPS depending on the operation and the FPGA. We have obtained 64% and 43% of the peak performance of singleprecision computation for Arria 10 and Stratix 10 FPGAs respectively. The fixedpoint computation performance heavily depends on the bit size and varies from 8 GOPS to 12,800 GOPS.