SpWMM: A HighPerformance SparseWinograd MatrixMatrix Multiplication Accelerator for CNNs In recent years, many CNN accelerators are proposed to exploit the sparsity of the networks to enjoy the benefits of both computation and memory reduction. However, these accelerators either cannot exploit the sparsity of both activations and weights, or cannot achieve stable performance with a static scheduling strategy, which is vulnerable to the sparsity distribution. This paper proposes a dynamic scheduling strategy and a balanced compressed sparse row (BCSR) format to efficiently address these two issues. A setassociate structure is presented to tradeoff the load balance and logic overhead. We propose SpWMM to accelerate the CNN inference, which is the first work to implement both sparse Winograd convolution and sparse fullyconnected (FC) layers. On contemporary neural networks, this work achieves: (1) 2.6Tops for Winograd convolution and 525Gops for 1xc3x971 convolution and FC layers in the 4way association design on Xilinx ZC706 platform, (2) 6.5 Tops for Winograd convolution and 1.2Tops for 1xc3x971 convolution and FC layers in the 16way association design on Xilinx VCU1525 platform. Compared with the stateoftheart works on the same platform, the 4way design achieves 2.0xc3x97 speedup.

An Efficient Accelerator for Sparse Convolutional Neural Networks In this paper, we propose a sparse convolutional neural network accelerator design on FPGAs. Similar to the DNNWEAVER architecture, our accelerator uses twolevel hierarchy: multiple Processing Units (PUs) and each PU comprises a set of Processing Elements (PEs). To address the irregularity of sparse neural networks, we introduce a novel sparse dataflow for sparse CNN computing as well as weight merging method to balance the computation load on different PUs for better overall efficiency. We implement our design with 32 PUs and 14 PEs in each PU. When compared with DNNWEAVER on VGG16 network, our accelerator achieves 3.49x speedup and 3.05x energy saving on average when running at 150MHz on a Xilinx ZC706 board and reaches the speed of 400 GOPS.