SkyCastle: A ResourceAware MultiLoop Scheduler for HighLevel Synthesis A common optimisation problem in the highlevel synthesis (HLS) of FPGAbased accelerators is to find a microarchitecture that maximises the performance while keeping the utilisation of the deviceu0027s lowlevel resources below certain limits. We propose to tackle it directly as part of the HLS scheduler. To that end, we formalise a general, integrated scheduling and allocation problem for HLS kernels, and present SkyCastle, a novel resourceaware multiloop scheduler using integer linear programming to solve it for a subclass of kernels composed of multiple, nested loops. In order to demonstrate the practical applicability of the approach, we model the scheduler in such a way as to be plugin compatible with the Xilinx Vivado HLS engine, allowing the computed solutions to be fed back into its synthesis flow. We evaluate SkyCastle for three nontrivial kernels from the machine learning, signal processing, and physical simulation domains, on two FPGA devices. Additionally, we investigate the replication of slightly slower, but smaller accelerators as a means to further boost the overall performance. In contrast to Vivado HLSu0027 default settings, which aim at maximum performance but may fail in later synthesis steps, the solutions computed by our scheduler always result in synthesisable designs.

CompilerBased HighLevel Synthesis of ApplicationSpecific Processors on FPGAs In order to meet tight performance andor energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example FieldProgrammable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern HighLevel Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Softcore processors implemented with FPGAlogic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a generalpurpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compilerbased synthesis methodology that generates networks of ApplicationSpecific Instruction Set Processors (ASIPs) from unmodified CC algorithms. We thereby bridge the gap between traditional softcore processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compilerbased approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)fixed commercial Xilinx MicroBlaze softcores.