Low Cost and High Performance Radiation Hardened Latch Design for Reliable Circuits With decreasing device dimension, the susceptibility of transistors and circuits to external noise sources increase especially in radiative environments. In this work, a radiation hardened latch based on NMOS only Schmitt trigger with voltage booster (NSTVB) is proposed. We first analyze the critical charge at the internal nodes of different latch designs to identify the most sensitive node. By doing so our results reveal that the proposed circuits show highest robustness to single event transients, compared to reference designs. Furthermore, the results show that the critical charge decreases with temperature and increases for higher supply voltages, and it is further observed that the critical charge decrement with temperature variation, exhibiting best performance for the NSTVB based latch compared to others circuits. For the validation of proposed latch, a figure of merit, i.e. the charge to power delay area product ratio (QPAR), considering the most important performance parameters is calculated. We clearly observe that the proposed latch exhibits significantly enhanced performance as compared to existing designs.

Novel Radiation Hardened Latch Design with CostEffectiveness for SafetyCritical Terrestrial Applications To meet the requirements of both costeffectiveness and high reliability for safetycritical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a singlenodeupset selfrecoverable cell, a 3input Celement, and an inverter. If any two inputs of the Celement suffer from a doublenodeupset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a highspeed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delaypowerarea product on average, compared with stateoftheart DNU hardened latch designs.