Lina: TimingConstrained HighLevel Synthesis Performance Estimator for Fast DSE The adoption of FieldProgrammable Gate Array (FPGA) for general use in the HighPerformance Computing scenario has been limited by its complex development flow required to get optimised designs coupled with a timeconsuming compilation. HighLevel Synthesis (HLS) tools are adopted to improve programmability, however the developer must perform several iterations of optimisation schemes in order to achieve reasonable performance results, which is tedious and not trivial. Several works employ Design Space Exploration (DSE) through different optimisation possibilities, coupled with fast performance estimators to avoid the unacceptable compilation times. This paper presents Lina, an expansion of the LinAnalyzer fast peformance estimator for CC HLS including timingconstrained scheduling and an extended analysis for nested loops. Results over the PolyBench benchmark show that the average relative error dropped from 8.85% to 3.02% when loop unrolling and pipelining directives were considered. As a result Lina becomes a better estimator for nonperfect loop nests and for different timing constraints, which can be adopted as an additional design space exploration knob.

Benchmarks for FPGATargeted HighLevelSynthesis Recently, highlevel synthesis (HLS) tools such as Intel FPGA SDK for OpenCLu0027 and Xilinx SDAccel have been introduced to design FPGA accelerators. Those HLS tools use C language based environment to significantly reduce the design time. However, it is also important to know how much performance we can achieve using HLS tools. FPGA is a highly reconfigurable hardware and the performances are extremely different depending on the architecture. Performances also depend on the FPGA board, HLS software and firmware such as BSP (board support package). Therefore, benchmarking FPGAs is an extremely challenging task. This paper proposes a method to design benchmarks for FPGAtargeted HLS. The benchmarks are highly scalable and can be used for different FPGAs and compilers to obtain most of the potential performance. Evaluating four different FPGAs, we found that the singleprecision floatingpoint computation performance varies from 17 GFLOPS to 3,955 GFLOPS depending on the operation and the FPGA. We have obtained 64% and 43% of the peak performance of singleprecision computation for Arria 10 and Stratix 10 FPGAs respectively. The fixedpoint computation performance heavily depends on the bit size and varies from 8 GOPS to 12,800 GOPS.