Accurate and Efficient Interdependent Timing Model for FlipFlop in Wide Voltage Region The interdependency of the setup and hold constraints and clocktoq (c2q) delay for flipflops (FF) has been studied in static timing analysis (STA) to facilitate timing closure and improve circuit performance. However circuits operating in nearthreshold voltage (NTV) region pose severe challenge to the interdependent timing modelling due to its significant nonlinear relation and much wider constraint range compared with superthreshold voltage (STV) region. In this paper an accurate and efficient modelling approach is proposed by employing artificial neuron network (ANN) to characterize the interdependency among the setup time hold time and c2q delay of FF in wide voltage region. Experimental results show the prediction errors of c2q delay with varied setup and hold constraints are lower than 2.1% and 1.8% in NTV and STV regions with 3.51x and 1.09x accuracy improvement compared with the prior work. Besides the modelling efficiency is validated by 1.41 x1.10x simulation cost reduction and 21.08x4.14x library storage saving for NTVSTV domain with accuracy advantage.

DNNLibGen: Deep Neural Network Based Fast Library Generator We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is nonlinear, nonmonotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving timetomarket goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required signoff corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a xe2x80x98single modelxe2x80x99 to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed librarygenerator uses a novel intercorner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intracorner model, to generate dense 8x8 delay tables using delays from 10 slewload points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization runtime for early milestones by upto 60%.