DiameterASPLBased Mapping of Applications with Uncertain Communication over Random Interconnection Networks The steadily increasing number of compute nodes in highperformance computing (HPC) systems calls for more efficient interconnection networks and application mapping strategies. Traditionally, the user applications are mapped onto a regular network with nearby compute nodes to reduce the network distances. However, it is likely that the rigid mapping limitation on regular topologies may largely delay the dispatch time when the workload is heavy at a short period. In this work, we target the applications with unknown communication patterns over random interconnection networks, which have drawn increasing attention in the HPC world due to their low diameter and low average shortest path length (ASPL). We propose to use topology embedding metrics, i.e., diameter and ASPL, for application mapping to overcome the rigid limitation on regular topologies. We investigate the timespace tradeoff among several application mapping algorithms using a compound application workload. Evaluation results show that, when compared to the baseline random connected topology mapping, the proposed diameterASPLbased topology mapping algorithms reduce up to 48.0% makespan and up to 78.1% average turnaround time and improve up to 1.9X system utilization when the instantaneous workload is heavy over random interconnection networks.

Log Diameter Rounds Algorithms for 2Vertex and 2Edge Connectivity. Many modern parallel systems, such as MapReduce, Hadoop and Spark, can be modeled well by the MPC model. The MPC model captures well coarsegrained computation on large data  data is distributed to processors, each of which has a sublinear (in the input data) amount of memory and we alternate between rounds of computation and rounds of communication, where each machine can communicate an amount of data as large as the size of its memory. This model is stronger than the classical PRAM model, and it is an intriguing question to design algorithms whose running time is smaller than in the PRAM model.  :103,this paper, we study two fundamental problems, 2edge connectivity and 2vertex connectivity (biconnectivity). PRAM algorithms which run in O(log n) time have been known for many years. We give algorithms using roughly log diameter rounds in the MPC model. Our main results are, for an nvertex, medge graph of diameter D and bidiameter Du0027, 1) a O(log Dloglog_mn n) parallel time 2edge connectivity algorithm, 2) a O(log Dlog2log_mnnlog Du0027loglog_mnn) parallel time biconnectivity algorithm, where the bidiameter Du0027 is the largest cycle length over all the vertex pairs in the same biconnected component. Our results are fully scalable, meaning that the memory per processor can be O(ndelta) for arbitrary constant deltau003e0, and the total memory used is linear in the problem size. Our 2edge connectivity algorithm achieves the same parallel time as the connectivity algorithm of Andoni et al. (FOCS 2018). We also show an Omega(log Du0027) conditional lower bound for the biconnectivity problem.