Multirate DAG Scheduling Considering Communication Contention for NoCbased Embedded Manycore Processor Computing platforms for embedded systems are increasingly being transformed into multimanycore platforms because embedded systems have become extensive, complex, and automated. In the case of an autonomous driving system, various applications are simultaneously running, and low power consumption and largescale calculation are required. Manycore processors with a multiple instruction, multiple data (MIMD) architecture can meet these requirements. This paper proposes a scheduling algorithm for an automotive driving system expressed in a directed acyclic graph (DAG) and we use Kalray MPPA256 as the target manycore processor. On the basis of the architecture of Kalray MPPA256, task processing that requires largescale calculation and intercore communication is performed while avoiding communication contention by using a proposed grouping computational resource. In addition, we propose a scheduling method for a multirate DAG which is a DAG with multiple periods. This method generates a DAG task in a hyperperiod and schedules the DAG with dependency on tasks that have been released closely. The formulas for prioritization and processor selection are proposed for various generated tasks in a hyperperiod. Evaluation results show that the proposed algorithm is superior to existing DAG scheduling algorithms with regard to schedulability and deadline miss ratio.

Isomorphic Subgraphbased Problem Reduction for Resource Minimal Modulo Scheduling Modulo scheduling is a powerful method to increase throughput in highlevel synthesis for digital hardware design. When facing large designs, optimal approaches are likely to time out and heuristics fail to provide satisfying throughput and latency. We propose an isomorphic subgraphbased reduction of the input dataflow graph (DFG) that is applied before scheduling, in order to solve the modulo scheduling problem faster without changing the optimal initiation interval (II) and allocated hardware. Our results show a solving time speedup of 5xc3x97 on average and up to 102xc3x97 for large designs. Using the proposed preprocessing step, the II achieved could be reduced by 33% on average for SDCbased modulo schedulers. And in ILPbased scheduling, we could classify 15% more solutions as optimal within the same time compared to solutions provided without applying our transformation.