An UWB 18.5 GSs Sampling FrontEnd for a 74 GSs 5bit ADC in 22nm FDSOI This paper presents the design of an ultrawideband buffered frontend sampler (Tu0026H) operating at 18.5 GSs. The linear sampler, intended for a 5bit 4x timeinterleaved (TI) flash ADC, is realized in a 22 nm FDSOI (FDX) CMOS process. It comprises an ultralow jitter limiting clock path and a PMOSNMOS source follower Tu0026H maximizing the linearity and isolation as well as enhancing the effective sampling bandwidth. The frontend takes advantage of the flippedwell forwardbiasing process option lowing the transistor threshold voltage by 75 mVV to achieve a differential input range of 600 mV pp,diff  while using a dual 1.2 V and 0.9 V supply voltage. The frontend exhibits asampling bandwidth of more than 40 GHz across corners (worst case SS, T  120xc2xb0C), achieving a SFDR and SNDR of better than 41 dBc and 38 dB respectively at the fourth Nyquist zone (fin  37GHz). The total power consumption is only 75mW of which 10 mW is consumed by the entire clock path.

FirstOrder Recursive CIC Filters in TimeInterleaved VCOBased ADCs for DirectRF Sampling Receivers Digital building blocks operating at gigasamples per second (GSs) rates in direct radio frequency (RF) sampling receivers consume a large amount of the total power of the receivers. The previously reported techniques have not considered the digital blocks in analogtodigital converters (ADCs) and not decreased the power consumption. We first place firstorder recursive cascaded integratorcomb (CIC) filters with decimation factors of two after timeinterleaved ADCs (TIADCs), consisting of voltagecontrolled oscillators (VCOs), samplers, phase detectors, and differentiators. This CIC filter cancels out the differentiators with its integrators and halves the clock frequencies of the samplers to reduce the power consumption of the receiver. We design the digital blocks of a directRF sampling receiver with a 3.6GSs 4channel TI VCObased ADC for SubGHz applications (phase detectors, mixers, and CIC filters) by using a 65nm CMOS process. Simulations show that the placeandrouted circuit operates at a 450MSs rate with 3.6 mW, which is half of the power consumption of a digital circuit without the proposed method.