WINNER: a high speed high energy efficient Neural Network implementation for image classification Nowadays, Neural Networks are often used in many applications to solve very complex tasks like speech recognition or image classification. In applications like image recognition, time is a critical constraint and a Neural Network must be able to correctly classify an image in a very short time: in these cases, hardware accelerators are necessary. In this work, a hardware implementation of a Neural Network is proposed. As a reference model, AlexNet has been chosen and implemented as an ASIC, by adopting an InMemory computing design. The concept of InMemory is based on the idea of placing small computational units near the memory element. This choice brings to relevant benefits, reducing the bottlenecks coming from a Von Neumannu0027s system (such as fetching latency and energy inefficiency due to the communication between logic and memory). The architecture has been synthesized on a 45nm CMOS technology and highlights remarkable results, with very high framepersecond (FPS) (comparable to binary neural network implementations) combined with low values of EnergyFPS and a maximum operating frequency of 281MHz. The system is also partially reconfigurable, enabling the mapping of different kind of neural networks.

A LowPower HighThroughput InMemory CMOSReRAM Accelerator for LargeScale Deep Residual Neural Networks We present an inmemory accelerator circuit design for ResNet50, a largescale residual neural network with 49 convolutional layers, 2.6 xc3x97 107 parameters and 4.1 xc3x97 109 f1oatingpoint operations (FLOPS). A 4bit quantized ResNet50 is first chosen among various bitwidths for the best tradeoff. It is then trained and fully mapped onto a 4608 xc3x97 512 ReRAM crossbar, yielding a storage reduction from 195.2Mb to 24.3Mb and an 88.1% top5 accuracy on ImageNet, only 2.5% lower than the fullprecision original. Two versatile CMOS 4bit DAC and ADC are designed for input and readout, allowing the proposed CMOSReRAM accelerator to achieve up to 15.2xc3x97 runtime speedup and 498xc3x97 higher energy efficiency versus the stateoftheart CMOSASIC implementation.