Optimizing FPGABased Streaming Applications for Throughput Using Pipelining In this paper, we present an automated flow for insertion of pipeline stages in FPGAbased streaming applications in order to increase the throughput. The proposed approach involves the utilization of Xilinxu0027s Automated Pipeline Analysis tool to estimate the number of pipeline stages, while the RapidWright framework incorporate these stages into a synthesized design. The Vivado Design Suite is then used to place and route the modified netlist. Furthermore, a recycling approach has also been proposed to reduce excess registers. The results show a significant improvement in the maximum operating frequency for designs without any sequential loops (51%) with a moderate resource overhead, while slight gains (12%) were also observed for designs containing feedback loops.

HighLevel Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing Recent Intel FPGAs Intel have bypassable registers in the routing switches, permitting deeper pipelining and more flexible retiming. We investigate highlevel synthesis (HLS) approaches to leverage these interconnect registers. We alter LegUp, an academic HLS tool, to insert extra registers within the datapaths, and at the inputsoutputs of memory blocks. Initially, one or more registers are inserted after every computational and memory instruction to assess the maximum reachable frequency (Fmax). Subsequently, we apply a more judicious approach, profiling applications in software to gather statistics on the execution frequency of code segments. Guided by profiling, we insert additional pipeline registers in subcircuits corresponding to infrequently executed code segments. This permits F max improvements to be realized with modest impact to cycle latency.