ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes Combined with cyclic redundancy check (CRC), SC list (SCL) decoder can achieve outstanding error correction performance, which is more obvious with increasing list size. However, the corresponding decoding complexity and latency increase with the list size. To this end, the selection of list size becomes essential for practical applications. A new artificial neural network (ANN) based framework is proposed in this paper to design a hardwarefriendly adaptive SCL (DLASCL) decoder. First, the list size at each stage is predicted by an ANN predictor. The performance achieved based on the proposed DLASCL algorithm is close to the optimal SCL decoder with the same list size, especially in the high signaltonoise ratio (SNR) region. Meanwhile, the computational complexity is significantly reduced compared with the conventional ones. Numerical results have demonstrated that the proposed deep learning based adaptive SCL decoder can achieve 56% computational complexity reduction compared with the conventional SCL decoder for the polar code with length 128 and rate 12. The hardware architecture of the adaptive SCL decoder based on the predicted list size is proposed and the folding technique is also adopted, which helps reduce the hardware cost by about 25%.

Polar Decoding Hardware Implementation This paper presents hardware implementations of two principle polar decoding algorithms: Successive Cancellation Decoding (SCD) and Successive Cancellation List Decoding (SCL). The proposed designs are compliant with 3GPP specifications in terms of block length and frozenset mapping. Moreover, this generic architecture allows block length  N  and rate  R  to be configured onthefly. The implementations significantly improved decoding throughput with hardware optimization, especially with the SCD, thanks to parallelblock decoding technique. Additionally, the SCL with a list size  Lgeq 8  considerably outperforms the BitErrorRate (BER), as well as the FrameErrorRate (FER) curve compared to SCD. The paper provides a comparison of the two algorithms, especially the tradeoff between performance and complexity. The results of implementations and testing are carried out on FPGA platform and compared with StateOfTheArt (SOTA).