Synchronous or Alternating? : LTL BlackBox Checking of Mealy Machines by Combining the LearnLib and LTSmin Mealy machines transduce inputs to outputs, based on finite memory. They are often used to model reactive systems. The requirements on their behaviour can be specified by formulas in Lineartime Temporal Logic. We will study two interpretations of LTL for Mealy machines: the synchronous semantics, where inputs and outputs occur simultaneously; and the alternating semantics, where inputs and outputs strictly alternate. We define and study Mealyrobust LTL properties, which are insensitive to which of these interpretations is chosen. The motivating application is in the context of blackbox checking: Given the interface to some reactive system, one would like to test that a particular LTL property holds. To this end, we combine active automata learning with model checking into sound blackbox checking. Here the LTL properties are already checked on intermediate hypotheses, in order to speed up the learner. Finally, we perform an experiment on the Mealy machines provided by the RERS challenge (Rigorous Examination of Reactive Systems). We investigate how many LTL properties from the RERS challenges in 2016 and 2017 are actually robust.

Relative Liveness: From Intuition to Automated Verification We define a new liveness condition for asynchronous circuits. Although finitary (finiteexecution) descriptions are not powerful enough to express general liveness properties, those liveness properties needed in practice appear to be related in a unique manner to finitary descriptions. Our liveness condition exploits this observation and is defined directly on finitary descriptions, in two forms: one on finite trace structures and the other on finite automata. We prove the equivalence of these two forms. We also introduce a safety condition and derive theorems for the modular and hierarchical verification theorems of both safety and liveness. Finally, we give an algorithm for verifying our liveness condition.