CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM As CPU frequency and computing power grow fast, conventional Von Neumann architecture is suffering from more and more severe data transfer latency and power consumption between CPU and DRAM, known as memory wall problem. In this paper, we propose a novel near memory architecture based on the Htree architecture of DRAM to decrease the data transfer latency. There are three work modes in the proposed CoDRAM, GMM (General Main Memory Mode), ACM (Auxiliary Computing Mode) and PCM (Parallel Computing Mode). Compared with conventional CPUDRAM architecture, the experiment shows that the proposed CoDRAM computing framework can improve about 20% and 33% performance on matrix addition and integral image computing in ACM mode. And in PCM mode, the improvement is about 15xc3x97 and 3xc3x97 in matrix addition and integral image computing. Meanwhile, the overhead in GMM mode is only about 1%.

Testing ComputationinMemory Architectures Based on Emerging Memories Todayu0027s computing architectures and device technologies are incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel postCMOS computing architectures are being explored. One of these is a ComputationinMemory (CIM) architecture based on memristive devices; it integrates the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computationinmemory bitwise logical operations.