A PreEmphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time A preemphasis pulse generator is proposed which can provide minimal wordline or columnline delay time in a large memory array or panel display without calibration even under a large process variation. The optimum preemphasis pulse width is theoretically identified by monitoring the farend of the delay line to reach a certain value which does not include the parasitic resistance and capacitance of the delay line but only includes an amount of overdrive. The circuit was fabricated together with the delay line in 0.18 xcexbcm 3V CMOS. Even with RC variation of 20%, the proposed circuit reduced the delay time by 60% with 60% overdrive in comparison with a fixed preemphasis pulse width without any calibration prior user operation or any special test sequence in die test. Sensitivity of a variation in a reference voltage and a comparator offset on the delay time is also discussed. Furthermore, the optimum detection level is presented in case that the resistance of driver and switch is as high as that of the delay line.

Buffer Sizing for NearThreshold Clock Tree using Improved Genetic Algorithm Comparing with superthreshold designs, clock tree design in nearthreshold voltage (NTV) region is more susceptive to signal slew, and timing violations occur much more often due to slew degradation at sink nodes and difference among sink nodes. However, when optimizing clock tree in superthreshold region, signal slew is merely considered as transition constraint with an upper bound. Little concern is taken about slew at sink nodes, which is particularly important in NTV region and system performance would be badly weakened if it is not controlled properly. Here, we propose an innovative formulation for optimization of buffer size in nearthreshold clock tree using improved genetic algorithm combined with nonlinear programming. With slew at sink nodes considered, we are able to minimize a combination of skew, slew and area cost. On average, skew is improved by 23.8%, and max slew at sink nodes and slew difference among sink nodes are reduced by 24.6% and 47.8% separately. At the same time, area cost of buffer is also reduced by 8.5%. The optimal solution can set as buffer sizes directly without any subsequent discretization procedure.