An Open Source FPGAOptimized OutofOrder RISCV Soft Processor Highperformance soft processors in fieldprogrammable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An outoforder (OoO) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics. Hence, we propose the RSD processor: a new, opensource OoO RISCV soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a nonblocking cache. While the RSD supports such aggressive features, it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well. We first introduce the end result of the RSD microarchitecture design and then describe several novel optimization techniques. The RSD achieves up to 2.5times higher Dhrystone MIPS while using 60% fewer registers and 64% fewer lookup tables (LUTs) as compared to stateoftheart, opensource OoO processors.

CompilerBased HighLevel Synthesis of ApplicationSpecific Processors on FPGAs In order to meet tight performance andor energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example FieldProgrammable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern HighLevel Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Softcore processors implemented with FPGAlogic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a generalpurpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compilerbased synthesis methodology that generates networks of ApplicationSpecific Instruction Set Processors (ASIPs) from unmodified CC algorithms. We thereby bridge the gap between traditional softcore processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compilerbased approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)fixed commercial Xilinx MicroBlaze softcores.