Assessment of STTMRAMs based on doublebarrier MTJs for cache applications by means of a devicetosystem level simulation framework Abstract   This paper explores nonvolatile cache memories implemented by spintransfer torque magnetic random access memories (STTMRAMs) based on stateoftheart perpendicular magnetic tunnel junctions (MTJs) and FinFETs. The use of doublebarrier MTJs with two reference layers (DMTJs) is benchmarked against solutions relying on singlebarrier MTJs (SMTJs) at different technology nodes (from 28nm down to 20nm). Our study is carried out through a crosslayer simulation platform, starting from the device up to the systemlevel. Our results point out that, thanks to the reduced switching currents, DMTJbased STTMRAMs allow decreasing write access time of about 63% as compared to their SMTJbased counterparts. This is achieved while assuring reduced energy consumption under both write (xe2x88x9242%) and read (xe2x88x9228%) accesses, lower area occupancy (xe2x88x9240%) and smaller leakage power (xe2x88x9225%), at the only cost of worsened read access time. This makes DMTJbased STTMRAM a promising candidate to replace conventional semiconductorbased cache memory for the nextgeneration of lowpower microprocessors with onchip nonvolatility.

Novel smart card SoC memory architecture based on embedded STTMRAM In the applications of Internet of Things (IoT), the limitations of the common NVM  RAM hybrid memory architecture cannot simultaneously provided the solution of lower power, low resource consumption and nonvolatile which are critical for IoT designing. Spin Transfer Torque Magnetic Random Access Memory (STTMRAM) has become a major candidate for onchip memory because of its ideal memory characteristics, such as nonvolatile, near zero standby leakage power and compatibility with CMOS. Therefore, this paper focuses on the application of STTMRAM in the storage of IoT. We design the eSTTMRAM nonhybrid memory architecture for smart card SoCs. The prototype verification results on Xilinxu0027s ARTIX7 XC7A100T FPGA platform show that the STTMRAMbased memory architecture can greatly improve the operating efficiency of SoC programs and reduce the dynamic power consumption of the system due to data storage.