Make Page Coloring more Efficient on SliceBased ThreeLevel Cache On modern multicore machines, page coloring has been used to alleviate the competition at Last Level Cache (LLC). However, the latest development of CPU architecture has brought new issues to page coloring. Firstly, in the case of threelevel cache, previous works about page coloring did not discuss the impact on L2 cache of color allocation and the competition for L2 cache is not considered concurrently under hyperthreading. In addition, as the last level cache structure is changed from shared to slicebased and undocumented hash function is applied, page coloring is more complex and slice information is also not fully utilized. This paper presents solutions to these issues. Firstly, by making small changes to the traditional page coloring, the problem that page coloring may waste L2 cache is alleviated. At the same time, we rethink the vertical allocation of L2 cache and LLC in page coloring under hyperthreading, and discuss the impact of color allocation on programs, especially those with different sensitivity to L2 cache and LLC. Finally, we make full use of slice information and propose Partial Conflict Color (PCC). At the same time, we also propose a fast method to obtain PCC. Experiments show that using PCC can improve system performance when the number of colors is insufficient.

A DataSharing Aware and Scalable Cache Miss Rates Model for MultiCore Processors with MultiLevel Cache Hierarchies To mitigate the ever worsening Power wall and Memory wall problems, multicore architectures with multilevel cache hierarchies have been widely used in modern processors. However, data sharing caused by the concurrent threads running on different cores and the filter effects of multilevel caches make the analytical cache modeling of such systems extremely complex. Prior models either ignore the data sharing or evaluate its effect with large simulation costs. In this paper, we propose a datasharing aware and scalable analytical model for estimating the miss rates of the downstream shared cache in a multicore environment. Our model uses probability derivations to quantify the data sharing effects based on the information of access address distributions for each core. Moreover, the proposed model can also be scalably integrated with upstream cache models without the timeconsuming simulations of the cache architecture. We validate our analytical model against gem5 simulation results under 13 benchmarks from PARSEC benchmark suites. We compare the L2 cache miss rates with the results from gem5 under 8 hardware configurations including dualcore and quadcore architectures. The average absolute error is less than 2% for all configurations.