Memristor Hardware Accelerator of Quantum Computations Quantum computing and quantum computers are a major part of the second quantum revolution. Existing quantum algorithms can natively solve complex problems, such as the prime number factorization and searching of unstructured databases, in a fast and efficient way. The main obstacle towards building large and efficient quantum computers is decoherence, which produces errors that have to be continuously corrected using quantum error correcting codes. Beyond the realisation of quantum computing systems with actual quantum hardware, quantum algorithms have been developed based on quantum logic gates that can be described and utilised by classical computers and proper interfaces based on linear algebra operations. Furthermore, memristive grids have been proposed as novel nanoscale and lowpower hardware accelerators for the timeconsuming matrixvector multiplication and tensor products. In this work, given that for quantum computations simulation, the matrixvector multiplication is the dominant algebraic operation, we utilize the unprecedented characteristics of memristive grids to implement circuitlevel quantum computations. Since all quantum computations can be mapped to quantum circuits, memristive grids can also be used as efficient quantum simulators, as classicalquantum interfaces and also as accelerators in mixed classicalquantum computing systems.

A MemristorCMOS Braun Multiplier Array for Arithmetic Pipelining A multiplier is a core building block in most digital signal and image processing systems and increasingly so in neural processing units. The latter must parallelize very large scale multiplyandaccumulate operations in deep learning with reconfigurable weights to be multiplied with varying input. In light of this, we propose a memristorCMOS hybrid multiplier which uses a Braun structure to enable segmentation of the multiplier array to process various multiplication operations simultaneously with reconfigurable bitwidths by varying a control signal, all on the same multiplier. This enables an increase in computational throughput. Memristors are used as basic logic elements and improve area utilization by fabricating them in the back end of the line before the pad level. The CMOS chip is fabricated in the SK Hynix 180nm process with TiO 2  memristors separately deposited on top. A performance evaluation is undertaken under a 4point Fast Fourier Transform, demonstrating a decrease in area by 17% and power consumption by 35%49% with a 100MHz system clock when compared to similarly behaving CMOS multipliers.