AllDigital PhaseLocked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping In this paper, we study the propagation of timing error in a synchronous AllDigital PhaseLocked Loop network. The architecture of the network represents a linear array of oscillators, where the first oscillator is considered as the reference oscillator, and the others are implemented as digitally controlled oscillators. The synchronisation of the network is achieved through interactions between a controlled oscillator and its closest neighbours. Using FPGA prototyping, we have shown that the jitter of a controlled oscillator saturates with the distance from the reference oscillators and that the bidirectional topology has better performance than the unidirectional topology. A comparison of measurements with a theoretical model is carried out to verify our FPGA prototyping framework.

FPGAbased TriggerSynchronizer for low FrameJitter Signal Generation Commercial waveform function generators can be set to produce signal bursts that start when a trigger pulse is applied. Unfortunately, the delay between trigger pulse and the effective burst generation is not constant, but it is affected by a jitter in the order of some hundreds of ps or more. In sensitive applications, like ultrasound Doppler, this jitter affects negatively the measurements, limiting the use of the generators in the experiments. In this paper, an FPGA resynchronization circuit is presented that is able to rephase an internal clock to the edge of a trigger pulse. Unlike other commercial resynchronization devices, the trigger can be an arbitrary pulse sequence, not necessarily a clock. The circuit measures the phase between the trigger edge and its internal clock by the means of a TappedDelayLine, and rephase accordingly a second internal clock. Experiments show that when the proposed circuit is used for generating signal bursts triggered by an external signal, the framejitter is below 100 ps rms.