Polar Decoding Hardware Implementation This paper presents hardware implementations of two principle polar decoding algorithms: Successive Cancellation Decoding (SCD) and Successive Cancellation List Decoding (SCL). The proposed designs are compliant with 3GPP specifications in terms of block length and frozenset mapping. Moreover, this generic architecture allows block length  N  and rate  R  to be configured onthefly. The implementations significantly improved decoding throughput with hardware optimization, especially with the SCD, thanks to parallelblock decoding technique. Additionally, the SCL with a list size  Lgeq 8  considerably outperforms the BitErrorRate (BER), as well as the FrameErrorRate (FER) curve compared to SCD. The paper provides a comparison of the two algorithms, especially the tradeoff between performance and complexity. The results of implementations and testing are carried out on FPGA platform and compared with StateOfTheArt (SOTA).

RateFlexible Fast Polar Decoders Polar codes have gained extensive attention during the past few years and recently they have been selected for the next generation of wireless communications standards (5G). Successivecancellationbased (SCbased) decoders, such as SC list (SCL) and SC flip (SCF), provide a reasonable error performance for polar codes at the cost of low decoding speed. Fast SCbased decoders, such as FastSSC, FastSSCL, and FastSSCF, identify the special constituent codes in a polar code graph offline, produce a list of operations, store the list in memory, and feed the list to the decoder to decode the constituent codes in order efficiently, thus increasing the decoding speed. However, the list of operations is dependent on the code rate and as the rate changes, a new list is produced, making fast SCbased decoders not rateflexible. In this paper, we propose a completely rateflexible fast SCbased decoder by creating the list of operations directly in hardware, with low implementation complexity. We further propose a hardware architecture implementing the proposed method and show that the area occupation of the rateflexible fast SCbased decoder in this paper is only 38% of the total area of the memorybased baseline decoder when 5G code rates are supported.