Reliability and Accelerated Testing of 14nm FinFET Ring Oscillators Accelerated lifetime tests are necessary for reliability evaluation of circuits and systems, but the parameters for choosing the test conditions are often unknown. Furthermore, reliability testing is generally performed on test structures that have different properties than actual circuits and systems, which may create inconsistencies in how circuits and systems work in reality. To combat this problem, we use ring oscillators, which are similar to circuits, based on the 14nm FinFET node as the circuit vehicle to extract wearout data. We explore the effects of testing time, sample size, and number of stages on the ability to detect failures for various test conditions, focusing on frontend time dependent dielectric breakdown, which is one of the most dominant wearout mechanisms.

Performance Comparison of a StrongArm Latch in Different UltraScaled Technologies This paper compares the performance achievable in different scaled technologies by analog circuits, using a strongarm latch as an example. The performance analysis has been carried out in a 7nm and a 16nm FinFET technologies, and in a 28nm FDSOI technology, considering different input signal amplitudes, input commonmode voltage levels, process corners, and temperatures. The circuit used for the comparison has been optimized for the 7nm technology with a supply voltage of 0.9 V and a clock frequency of 1 GHz and scaled, maintaining the same transistor aspect ratio in the other technologies. In typical cases, the 7nm technology is slower than the 16nm technology, but it has better performance in terms of powerdelay product (PDP). The 16nm technology features lower delay when the input commonmode voltage is higher than 750 mV, but with larger PDP. The 28nm technology in all the cases is the slowest in speed and achieves the worst PDP.