A language for describing boundary scan devices Boundary scan (IEEE Standard 1149.11990) technology is beginning to be embraced in chip and board designs. One key need is a way to simply and effectively describe the feature set of a boundary scan compliant device in a manner both user friendly and suitable for software to utilize. A language subset of VHDL is proposed here for this purpose. As with any new standard, the industry is learning how to apply its rules and mistakes will occur. A derivative effect of the language proposed here is that if a device is not describable by the language, then that device does not comply with the 1149.1 standard. While the converse is not true, the language still allows a syntactic check for compliance as well as a number of semantic checks.

Synthesizing Efficient Hardware from HighLevel Functional Hardware Description Languages Functional hardware description languages (FHDL) provide powerful tools for building new abstractions that enable sophisticated hardware system to be constructed by composing small reusable parts. Raising the level of abstractions in hardware designs means the programmer can focus on highlevel circuit structure rather than mundane lowlevel details. The language features that facilitate this include highorder functions, rich static type system with type inference, and parametric polymorphism. We use handwritten structural and behavioral VHDL, Simulink, and the Kansas Lava FHDL to reimplement several components taken from a Simulink model of an orthogonal frequencydivision multiplexing (OFDM) physical layer (PHY). Our development demonstrates that an FHDL can require fewer lines of code than traditional design languages without sacrificing performance.