A Compact Inductorless 32 GHz Divideby2 CML Frequency Divider on 22 nm FDSOI Technology This paper presents a compact divideby2 frequency divider based on CML Dflipflops suitable for operation in lowpower (LP) or highperformance (HP) mode. In LP mode the divider locks in the 10 xe2x88x9228 GHz range, and in HP mode in the 12.5 xe2x88x9232 GHz range, corresponding to 119% and 118% relative locking ranges. The circuit has been manufactured on a 22 nm FDSOI CMOS process and consumes 3.5 mW and 6 mW from a 0.8 V and a 1 V supply while generating a xe2x88x9221 dBm and xe2x88x9215 dBm output signal in low power and high performance modes, respectively. The divider does not use any peaking inductors, which allowed an active core area occupation of only  255 boldsymbolmumathbfm2 . The small area and the absence of bias inputs allows its seamless integration into frequency synthesizer or clock recovery circuits.

A 22xe2x80x9329 GHz VoltageBiased LCVCO with Suppressed Flicker Noise over Tuning Range in 22nm FDSOI This paper presents a 22xe2x80x9329 GHz voltage biased LCVCO in 22nm FDSOI achieving a figureofmerit (FOM) of 188190 dBcHz over the tuning range. Thanks to the noise filtering tank formed by decoupling capacitor and source side coupled inductor, the flicker noise upconversion can be suppressed significantly without degrading the phase noise (PN) at 1f2 region. To obtain a consistent low 1f3 corner along with the frequency tuning, a common centroid layout technique is used for switched capacitor bank (SCB) implementation. The post layout simulation shows that the 1f3 corner is well below 50kHz over the tuning range in different process corners. The PN1MHz is xe2x88x92110.2 dBcHz at center frequency with a power consumption of 8.8mW.