Adoption of 2T2C ferroelectric memory cells for logic operation A 2T2C ferroelectric memory cell consisting of a select transistor, a read transistor and two ferroelectric capacitors that can be operated either in FeRAM mode or in memristive ferroelectric tunnel junction mode is proposed. The two memory devices can be programmed individually. By performing a combined readout operation, the two stored bits of the memory cells can be combined to perform inmemory logic operation. Moreover, additional input logic signals that are applied as external readout voltage pulses can be used to perform logic operation together with the stored logic states of the ferroelectric capacitors. Electrical characterization results of the logicinmemory (LiM) functionality is presented.

Dynamics of Ferroelectric and Ionic Memories: Physics and Applications Ferroelectric (FE) and solid polymer electrolytes (SPEs) are being explored for memory and for a variety of purposes in transistors. While considering the dynamics of emerging memories, we note some interesting implications for transistors and transistor memories. In this paper we consider the dynamics of subthreshold swing (SS) in transistors and show that under certain conditions SS can be lowered due to the delay associated with their complex impedance. We show that even a conventional metal oxide semiconductor fieldeffect transistor (MOSFETs) can exhibit a dynamic SS, lowered by introducing a series resistance in the gate. We show that the when the gate dielectric has a complex response, SS can be decomposed into static and dynamic factors with the static factor given by the usual thermal SS and the dynamic factor related to dynamic gate amplification. In the measurement of SS, slew rate and slew direction can be readily utilized to reveal the SS dependence on dynamics.