DTCAssisted AllDigital PhaseLocked Loop Exploiting Hybrid TimeVoltage Phase Digitization This paper proposes a hybrid timevoltage phase digitization technique in an alldigital phaselocked loop (ADPLL). To cover the required dynamic range of one oscillator period to measure the phase difference between clock edges of reference and feedback from a highfrequency oscillator, a digitaltotime converter (DTC) is used to reduce the required range of a timetodigital converter (TDC). Further, a time error is first converted to voltage through a timetovoltage converter (TVC) and further quantized to digital bits by a SARADC. This results in a highresolution phase detection which can help reducing the inband phase noise while consuming low power. The system has been modeled and verified based on an eventdriven approach in 28 nm CMOS.

A MultiPhase TimetoDigital Converter Differential Vernier Ring Oscillator This paper reports the development of an adjustable, TimetoDigital Converter (TDC) based on two vernier Ring Oscillators (RO). The TDC aims to measure timing in Resistive Plate Chamber (RPC) detector for CMS experiment. Considering previous designs, the contribution from power supply noise and intrinsic transistor noise had been minimizing with differential stages and proper transistor sizing. To reduce the timing resolution and deadtime inherent to Vernier TDC architecture, as many Phase Detector (PD) as possible had been implemented. Such functionality permits to choose whether reducing the dead time or measuring redundantly the startstop time difference for an improved precision. The prototype TDC fabricated in a 130nm technology consumes 8.5 mW power under 1.2V supply. The measurement of this chip shown a timing accuracy of 5.48 ps at a timing resolution of 8 ps for the first data allowed by the first phase detection.