Hardware Security for and beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges. As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges.

Recruiting Fault Tolerance Techniques for Microprocessor Security The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging microarchitectural side channels such as due to speculative execution to implementing cryptographic accelerators for sidechannel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of u0027security faultsu0027 (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive sidechannels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the repurposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active sidechannel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic subcomponent of a RISCV based secure systemonchip, against a formidable fault attack called SIFA.