Assessing the Effectiveness of the Test of Power Devices at the Board Level Power devices have an increasing relevance in many applications, including some safetycritical ones. In the latter case, the effectiveness of the test performed at the end of the manufacturing, when the device is already mounted on the final board, is crucial. Unfortunately, assessing such effectiveness is not trivial, since it requires defining a metric that could be measured in an objective manner. Following a trend that is common to the whole world of analog components, in a previous paper we proposed a fault model based on the availability of the electrical model of the power device. Using this fault model, the test engineer can assess and possibly improve the quality of the developed test solution, and optimize the overall test plan so that a given fault coverage is achieved with minimum cost. The proposed fault requires the availability of the electrical model of the power device. In this paper we adopt this approach on a case of study using a power device, and analyze the effectiveness provided by a set of functional tests and an incircuit one. Results are reported and discussed, showing the advantages and limitations of the approach.

A Structured Approach for Rapid Identification of FaultSensitive Nets in Analog Circuits The traditional body of literature on analog testing deals with propagation of faults to the output nets of the circuit. Often the set of detectable faults remains unsatisfactory because suitable stimuli cannot be found for propagating certain faults to the output. Existing technology supports capturing of the state of internal nets of a circuit, thereby enhancing the scope of detecting faults by observing their effect on internal nets. This approach is feasible only if the number of internal nets probed by the builtin test structure is very few. This paper presents a structured approach that identifies the sensitive nets, namely a well chosen small subset of internal nets that are affected by these faults. We utilize the speed of DC analysis and some common behavioral aspects of analog signals to find out this subset. We report dramatic improvement in fault coverage on several circuits including benchmarks.