Test Architecture for Fine Grained Capture Power Reduction Excessive power during inxe2x80x93field testing can cause multiple issues, including invalidation of the test results, over heating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reductionapproaching 100% for multiple patterns.

Targeted PartialShift For Mitigating Shift Switching Activity HotSpots During Scan Test Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IRdrop that may invalidate the test by corrupting the contents of scan flipflops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hotspots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITCu002799 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partialshift for mitigating test data corruption risk with minimal impact on test time.