MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. With BNNs, multiplyaccumulate (MAC) operations can be simplified to XnorPopcount operations, leading to massive reductions in both memory and computation resources. Furthermore, multiple efficient implementations of BNNs have been reported on fieldprogrammable gate array (FPGA) implementations. This paper proposes a smaller, faster, more energyefficient approximate replacement for the XnorPopcount operation, called XNorMaj, inspired by stateoftheart FPGA lookup table schemes which benefit FPGA implementations. We show that XNorMaj is up to 2x more resourceefficient than the XnorPopcount operation. While the XNorMaj operation has a minor detrimental impact on accuracy, the resource savings enable us to use larger networks to recover the loss.

HBUNN  Hybrid BinaryUnary Neural Network: Realizing a Complete CNN on an FPGA Most modern neural networks use the basic MultiplyAccumulate (MAC) Operation in some form or another, and as networks get larger, the computational needs for these larger networks grow rapidly. Typically neural networks implemented on FPGAs use variable multipliers so that any weight can be used in the MAC, but this also forces the accelerator designer to store the weights of the model in offchip memory (DRAM). Moreover, because of high computational power and high memory bandwidth requirements of todayu0027s CNNs, it is harder for FPGA platforms to deliver the best performance. In this paper, we propose a fully parallelpipeline Hybrid BinaryUnary Neural Network (HBUNN) architecture to implement a lowcost and highperformance ResNet18 convolutional neural network. We use a hybrid binaryunary method to implement constantcoefficient multipliers and batch normalization units. These two units reduce hardware cost by 30.7% and 47.97% on average compared to the conventional binary equivalent, respectively. Moreover, we propose a novel training scheme using our hardware costaware regularizers that not only improves the area cost of the proposed architecture and the conventional binary architecture by 59.3% and 76.7% respectively, but also maintains the same accuracy. Finally, we have implemented three trained networks using different regularizers. The proposed HBUNN architectures reduce the area cost by 30%, and the area xc3x97 delay cost by 69% on average compared to the conventional binary architectures. The error rate of the proposed work is 12.93%, while its throughput is 278 Kfps.