An areaefficient VLSI architecture for AVS intra frame encoder In this paper, we propose a VLSI architecture for AVS intra frame encoder. Reconstruction loop hinders the parallelism exploration and becomes the critical path in an intra frame encoder. A First Selection Then Prediction (FSTP) method is proposed to break the loop and enable the parallel process of intra mode selection and reconstruction on neighboring blocks. In addition, areaefficient modules were developed. Configurable intra predictor can support all the intra prediction modes. A CA2DVLC engine with an areaefficient ExpGolomb encoder was developed to meet the encoding speed demand with comparably low hardware cost. Synthesized with 0.18 xcexbcm CMOS standardcell library, the overall hardware cost of the proposed intra frame encoder is 89k logic gates at the clock frequency constraint of 125MHz. Proposed encoder can satisfy real time encoding of 720 X 576 4:2:0 25fps video at the working frequency of 54MHz.

Intra Frame Prediction for Video Coding Using a Conditional Autoencoder Approach Intra prediction is a vital component of most modern image and video codecs. State of the art video codecs like High Efficiency Video Coding (HEVC) or the upcoming Versatile Video Coding (VVC) use a high number of directional modes. With the recent advances in deep learning, it is now possible to use artificial neural networks for intra frame prediction. Previously published approaches usually add additional ANN based modes or replace all modes by training several networks. In our approach, we use a single autoencoder network to first compress the original with help of already transmitted pixels to four parameters. We then use the parameters together with this support area to generate a prediction for the block. This way, we are able to replace all angular intra modes by a single ANN. In the experiments we compare our method with the intra prediction method currently used in the VVC Test Model (VTM). Using our method, we are able to gain up to 0.85 dB prediction PSNR with a comparable amount of side information or reduce the amount of side information by 2 bit per prediction unit with similar PSNR.