Insertion lossaware application mapping onto the optical CubeConnected Cycles architecture Abstract   Optical onchip network provides a highperformance onchip communication platform, while several reliability challenges, such as insertion loss and crosstalk noise may limit their scalability. In this paper, we propose an insertion lossaware task mapping on the novel nanophotonic networkonchip architecture based on the Cube Connected Cycles topology. A contentionfree quasiDimensionorderRouting algorithm along with areaefficient router structure and 2Dlayout are the main advantages of the proposed optical architecture. The efficiency of the proposed architecture, in terms of systemlevel parameters, such as throughput, average packet latency, and scalability is discussed based on several simulation scenarios. The insertion loss parameter of the proposed network, along with the reliability parameter of signal to noise ratio, are evaluated through optimized application mapping. The experimental results based on Genetic Algorithm show that our proposed network outperforms by about 5.2% and 3.9% in all benchmark applications in comparison with Mesh, and Torus topologies, respectively.

A Survey of Multicast Communication in Optical NetworkonChip (ONoC). Optical NetworkonChip (ONoC) is an emerging chiplevel optical interconnection technology to realise highperformance and powerefficient intercore communication for manycore processors. For onchip networks, multicast communication is an important communication pattern, which is not only widely used in parallel computing applications in Chip MultiProcessors (CMPs), but also commonly adopted in emerging areas such as neuromorphic computing. However, the optimisation of multicast communication in an ONoC is not well studied and there is a significant room to improve the performance. In this paper, we present a comprehensive survey of the multicast communication in an ONoC, covering the development of both architecture design and networking design as well as our recent research outcomes. Moreover, we propose the design challenges and future research directions for optimising multicast in an ONoC, which can provide guidance and insight for the future researchers and chip developers.