A 2.5GHz LTE Doherty Power Amplifier in SOICMOS Technology The need for RF FrontEnds Module (FEM) with reduced size and cost is driving research towards highly integrated Power Amplifiers (PA) with challenging linearity and efficiency requirements. To overcome efficiency challenges, the Doherty PA (DPA) architecture represents an attractive solution because of its high backoff efficiency and relatively simple structure. This paper presents a stateofthe art SOI CMOS DP A design implemented in a 0.13um SOI CMOS industrial process. At 2.5GHz, the 2stage SOI CMOS DPA achieves a measured peak PAE of 57% at 32.7dBm output power under 3.4V voltage supply. At IdB compression point, output power and PAE are 32.4dBm and 56% respectively. With a 10MHz LTE uplink signal, a linear output power of 29.4dBm is measured with a PAE of 48.8% at an ACLR level of xe2x88x9233dBc without using DPD.

Power Amplifiers Load Modulation Techniques for 5G in GaNonSi Techonology A Doherty power amplifier (DPA) and a Chireix power amplifier for 5th Generation (5G) wireless applications are presented in this paper. The power amplifiers are integrated in OMMIC 100 nm GaNonSi process. In both amplifiers, the xcexbb4 TLine are replaced with lumpedelements to reduce its area. The DPA presents a P sat  of 34 dBm (u003e2.5 W), a peak PAE of 41 % and a 9.4 dB gain at 3.6 GHz. At 7 dB output backoff (OBO) it exhibits a 34.2 % PAE. On the other hand, the Chireix outphasing PA provides a P sat  of 32 dBm (u003e1.5 W), a peak PAE of 54.9%, a gain of 10.4 dB and a 25 % PAE at 7 dB OBO. The occupied area of the DPA and Chireix amplifiers are 3.26 mm2and 3.2 mm2, respectively, including pads.