Evaluation of a Chained Systolic Array with HighSpeed Links A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalableeasytoestimate performance is increasing. The former improves the yield ratio and the latter eliminates the margin for performance guarantee. Consequently, both of these directions reduce the cost of hardware. In this paper, we propose a chained systolic array that connects small systolic array chips with peertopeer AXI interfaces, and evaluate the scalability of several types of topologies such as star, tree and daisy chain with some models implemented on FPGAs connected by aurora links. As a result, we found the star structured 4chip configuration provides maximum 2.9 x performance of 1chip configuration, and daisy chain can provide moderate scalability.

TwoDimensional SystolicArray Architecture for PixelLevel Vision Tasks This paper presents ongoing work on the design of a twodimensional (2D) systolic array for image processing. This component is designed to operate on a multiprocessor systemonchip. In contrast with other 2D systolicarray architectures and many other hardware accelerators, we investigate the applicability of executing multiple tasks in a timeinterleaved fashion on the Systolic Array (SA). This leads to a lower external memory bandwidth and better load balancing of the tasks on the different processing tiles. To enable the interleaving of tasks, we add a shadowstate register for fast task switching. To reduce the number of accesses to the external memory, we propose to share the communication assist between consecutive tasks. A preliminary, nonfunctional version of the SA has been synthesized for an XV4S25 FPGA device and yields a maximum clock frequency of 150 MHz requiring 1,447 slices and 5 memory blocks. Mapping tasks from video contentanalysis applications from literature on the SA yields reductions in the execution time of 12 orders of magnitude compared to the software implementation. We conclude that the choice for an SA architecture is useful, but a scaled version of the SA featuring less logic with fewer processing and pipeline stages yielding a lower clock frequency, would be sufficient for a video analysis systemonchip.