Approximate NoC and Memory Controller Architectures for GPGPU Accelerators High interconnect bandwidth is crucial for achieving better performance in manycore GPGPU architectures that execute highly data parallel applications. The parallel warps of threads running on shader cores generate a high volume of read requests to the main memory due to the limited size of data caches at the shader cores. This leads to a scenarios with rapid arrival of an even larger volume of reply data from the DRAM, which creates a bottleneck at memory controllers (MCs) that send reply packets back to the requesting cores over the networkonchip (NoC). Coping with such high volumes of data requires intelligent memory scheduling and innovative NoC architectures. To mitigate memory bottlenecks in GPGPUs, we first propose a novel approximate memory controller architecture ( AMC ) that reduces the DRAM latency by opportunistically exploiting row buffer locality and bank level parallelism in memory request scheduling, and leverages approximability of the reply data from DRAM, to reduce the number of reply packets injected into the NoC. To further realize high throughput and low energy communication in GPGPUs, we propose a low power, approximate NoC architecture ( Dapper ) that increases the utilization of the available network bandwidth by using single cycle overlay circuits for the reply traffic between MCs and shader cores. Experimental results show that  Dapper  and  AMC  together increase NoC throughput by up to 21 percent; and reduce NoC latency by up to 45.5 percent and energy consumed by the NoC and MC by up to 38.3 percent, with minimal impact on output accuracy, compared to stateoftheart approximate NoCMC architectures.

HighPerformance Adaptive MPI Derived Datatype Communication for Modern MultiGPU Systems The recent advent of the NVLink interconnect and Peripheral Component Interconnect express (PCIe) switch has resulted in the creation of extremely dense Graphics Processing Unit (GPU) systems like Cray CSStorm and NVIDIA DGX. In addition to the extremely high computational capability and communication capacity within a single machine, these systems expose novel capabilities like performing loadstore operations from remote GPU memory across interconnects. While researchers have proposed solutions that take advantage of loadstore semantics to provide support for highperformance datatype processing on CPUs, there exists no scholarly work on how one can orchestrate such highperformance datatypebased communication for GPUresident data. In this paper, we take up this challenge and propose highperformance and architectureaware designs for GPUbased noncontiguous datatype processing that uses the loadstore semantics exposed by modern dense GPU systems. We demonstrate that the proposed solutions can reduce the overhead of datatype processing by up to 4.7X compared to the stateoftheart schemes for GPUbased MILC communication kernel on an NVLink2enabled dense GPU system. For a weather forecast application kernel, the proposed designs demonstrate up to 9.9X faster HaloExchange kernel among 64 GPUs over stateoftheart designs. The proposed adaptive scheme also reports 10% higher throughput than existing designs for a 2D Jacobi solver on 16 GPUs. To the best of our knowledge, this is the first scholarly work that takes advantage of the zerocopy based loadstore semantics to perform highperformance GPU to GPU derived datatype communication on modern dense GPU systems.