A Low Voltage CMOS Current Comparator with Offset Compensation Analysis and design of an inverterbased current comparator consisting of 3 cascaded inverters is presented. Ideally, the comparator has almost zero input offset current when all inverters are assumed to be identical. In practice, small amount of threshold voltage or current mismatches may cause the offset current to increase dramatically. A switchedcapacitor inverter is added to the comparator circuit in order to mitigate such effect. During compensation phase, the switched inverter forms a feedback loop to generate a current that will compensate the input offset current. During comparison phase, the generated charge hold in the capacitor decreases the offset current significantly. To keep the loop stable, an RC Milleru0027s frequency compensator is also added. A prototype of the whole circuit using 0.18xc2xb5m process is designed and analyzed to prove this concept. It operates at 1V DC supply with 870nA consumption, 1nA resolution and 50ns delay for xc2xb1100nA step input. Its input offset current is 13pA when there is no mismatch. When the mismatch is accounted, it increases to 164nA. After installation of the compensation circuit, the offset current is cut down to 19pA.

An Ultra Lowpower Lowoffset Doubletail Comparator In double tail comparators, the preamplifier amplifies the input differential voltage and when the output V cm  of the preamplifier becomes larger than V th  of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the preamplification delay is fixed to a value and cannot be set at the minimum required delay, to save power and improve offset. In fact, when the latch is activated the preamplifier output differential voltage is still growing but the latch finishes the comparison before the maximum differential gain is formed and applied to the latch. In this paper, a comparator is proposed in which the preamplifier is turned off when the maximum gain is achieved so that always the maximum possible gain is applied to the latch. Therefore, not only the input referred offset is improved but also the power consumption of the preamplifier is saved. Simulations in 0.18xc2xb5m technology show with an appropriate preamplification delay the average power is saved by up to 75% while the offset voltage is reduced by about 30%.