Deep Learning Based Diagnostics for Rowhammer Protection of DRAM Chips Modern day DRAM chips have been shown to have a reliability issue which can lead to erratic bit flips, a phenomenon which is called Rowhammer. Although current DRAM modules come with inbuilt countermeasures, recent attacks have shown they are still vulnerable. The Rowhammer vulnerability has been used in conjunction with other sidechannels to lead to devastating attacks. In this work, we take a novel approach by training a deep learning model based on several successful and unsuccessful attempts to conduct Rowhammer. The objective of the model is to analyze the access patterns of the DRAM by reverse engineering the physical address to pinpoint exact DRAM location and in turn use them for early prediction of a potential Rowhammer flip. We showed that our approach could detect a probable Rowhammer attempt with considerably high accuracy and even before the completion of the attack. In a more general context, this work shows that suitable combinations of deep learning and reverse engineering of physical address space can help to enhance both the reliability and security of systems.

Reinforce Memory Error Protection by Breaking DRAM Disturbance Correlation Within ECC Words Rowhammering attack is increasingly a concern to computer security and reliability, particularly for computer servers using chipkill correct memories, which are vulnerable to rowhammering attack because of disturbance correlation within ECC words. Probabilistic Adjacent Row Activation (PARA) can effectively lower the probability of successful rowhammering attack, but its strength can be significantly weakened by simultaneous attacks on many rows. This paper presents a novel hardware design to reinforce the chipkill correct memory by breaking the disturbance correlation within individual ECC words. It uses an XORbased, devicespecific row remapping such that a single PARA breach can only disturb any ECC word on at most one memory device. A rowhammering attack has to breach the PARA defense twice to cause uncorrectable or undetectable errors, which is much more challenging than before. A case of evaluation shows that the solution increases the memory MTTF from 0.144 to over 300,000 years. The design incurs negligible performance and energy overheads.