DNNLibGen: Deep Neural Network Based Fast Library Generator We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is nonlinear, nonmonotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving timetomarket goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required signoff corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a xe2x80x98single modelxe2x80x99 to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed librarygenerator uses a novel intercorner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intracorner model, to generate dense 8x8 delay tables using delays from 10 slewload points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization runtime for early milestones by upto 60%.

AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for DNN chips. However, designing DNN chips is nontrivial because: (1) mainstream DNNs have millions of parameters and operations; (2) the large design space due to the numerous design choices of dataflows, processing elements, memory hierarchy, etc.; and (3) an algorithmhardware codesign is needed to allow the same DNN functionality to have a different decomposition, which would require different hardware IPs to meet the application specifications. Therefore, DNN chips take a long time to design and require crossdisciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip  a DNN chip generator that can automatically generate both FPGA and ASICbased DNN chip implementation given DNNs from machine learning frameworks (e.g., PyTorch) for a designated application and dataset. Specifically, AutoDNNchip consists of two integrated enablers: (1) a Chip Predictor, built on top of a graphbased accelerator representation, which can accurately and efficiently predict a DNN acceleratoru0027s energy, throughput, and area based on the DNN model parameters, hardware configuration, technologybased IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selection, block configuration, resource balancing, etc.), optimize chip design via the Chip Predictor, and then generate optimized synthesizable RTL to achieve the target design metrics. Experimental results show that our Chip Predictoru0027s predicted performance differs from realmeasured ones by u003c 10% when validated using 15 DNN models and 4 platforms (edgeFPGATPUGPU and ASIC). Furthermore, accelerators generated by our AutoDNNchip can achieve better (up to 3.86X improvement) performance than that of expertcrafted stateoftheart accelerators.