Exploring the Training and Execution Acceleration of a Neural Network in a Reconfigurable Generalpurpose Processor for Embedded Systems Neural networks are getting more and more present in our daily lives. Whether to classify, optimize, or predict results, the use of neural networks proves to be a great and powerful choice to solve these problems. However, the time spent in the training process can be an issue. Although it can be accelerated by Graphics Processing Units (GPUs), coprocessors or even Field Programmable Gate Array (FPGA), these approaches may not be the best choices to improve training performance in embedded systems due to the large area and power consumption. In this paper, we present a customized instruction set architecture with fixedpoint arithmetic considering a lightweight general purpose processor in order to accelerate the training and execution of neural networks. Cadencexc2xae LX7 Processor and Xtensaxc2xae software are used to identify runtime bottlenecks and optimize specific pieces of hardware. Experimental results show that our proposed architecture achieves about 24X runtime reduction with respect to a floatingpoint implementation, and were compared against other architectures.

A BlockFloatingPoint Arithmetic Based FPGA Accelerator for Convolutional Neural Networks Convolutional neural networks (CNNs) have been widely used in computer vision applications and achieved great success. However, largescale CNN models usually consume a lot of computing and memory resources, which makes it difficult for them to be deployed on embedded devices. An efficient blockfloatingpoint (BFP) arithmetic is proposed in this paper. compared with 32bit floatingpoint arithmetic, the memory and offchip bandwidth requirements during convolution are reduced by 50% and 72.37%, respectively. Due to the adoption of BFP arithmetic, the complex multiplication and addition operations of floatingpoint numbers can be replaced by the corresponding operations of fixedpoint numbers, which is more efficient on hardware. A CNN model can be deployed on our accelerator with no more than 0.14% top1 accuracy loss, and there is no need for retraining and finetuning. By employing a series of pingpong memory access schemes, 2dimensional propagate partial multiplyaccumulate (PPMAC) processors, and an optimized memory system, we implemented a CNN accelerator on Xilinx VC709 evaluation board. The accelerator achieves a performance of 665.54 GOPs and a power efficiency of 89.7 GOPsW under a 300 MHz working frequency, which outperforms previous FPGA based accelerators significantly.