An efficient faulttolerant arithmetic logic unit using a novel faulttolerant 5input majority gate in quantumdot cellular automata Abstract   This paper proposes a novel faulttolerant 5input majority gate using 28 simple and rotated cells in Quantumdot Cellular Automata (QCA) technology. The proposed gate is evaluated against cell omission, extracell deposition, and cell displacement defects to check the stability. The simulation results using QCADesigner 2.0.3 software show that the proposed gate is 59% and 100% faulttolerant against singlecell omission and extracell deposition defects, respectively. It also shows good tolerance against cell displacement defects. Moreover, the functionality of the proposed structure is confirmed by physical proofs. QCAPro tool is used to analyze the power consumption of the proposed structure. Faulttolerant versions of basic gates including 2input AND, 2input XOR, and 3input XOR are suggested using the proposed gate. Moreover, a faulttolerant 2:1 multiplexer, a 4bit even parity generator, and an Arithmetic Logic Unit (ALU) are developed and implemented using the proposed faulttolerant basic gates.

Loop abort Faults on LatticeBased FiatShamir & Hashn Sign signatures As the advent of generalpurpose quantum computers appears to be drawing closer, agencies and advisory bodies have started recommending that we prepare the transition away from factoring and discrete logarithmbased cryptography, and towards postquantum secure constructions, such as latticebased schemes. Almost all primitives of classical cryptography (and more!) can be realized with lattices, and the efficiency of primitives like encryption and signatures has gradually improved to the point that key sizes are competitive with RSA at similar security levels, and fast performance can be achieved both in software and hardware. However, little research has been conducted on physical attacks targeting concrete implementations of postquantum cryptography in general and latticebased schemes in particular , and such research is essential if lattices are going to replace RSA and elliptic curves in our devices and smart cards. In this paper, we look in particular at fault attacks against some instances of the FiatShamir family of signature scheme on lattices (BLISS, GLP, TESLA and PASSSign) and on the GPV scheme, member of the Hashu0027n Sign family. Some of these schemes have achieved recordsetting efficiency in software and hardware. We present several possible fault attacks, one of which allows a full key recovery with as little as a single faulty signature, and discuss possible countermeasures to mitigate these attacks.