A 0.93 pJbit Controlled CapacitorCharge 2bit Pulsewidth Demodulator in 45nm RFSOI CMOS This paper presents the design and characterization of a unique lowpower pulsewidth demodulator (PWDM) which works by controlling the total amount of charge stored on a capacitor. The proposed PWDM consists of a timetovoltage converter (TVC) and a flash architecture based 2bit analogtodigital converter (ADC). The TVC operates in two phases: the charge phase and the discharge phase. During the charge phase an input pulsewidthmodulated (PWM) signal charges a capacitor to a certain value. The larger the width of the PWM signal, the higher the voltage developed across the charged capacitor. This capacitor voltage, which is unique to each pulsewidth, is then digitized inside a 2bit ADC. During the discharge phase, the capacitor is allowed to completely discharge to ground. Designed in the 45nm RFSOI CMOS, the PWDM occupies an active area of 70 xc3x97 80 xc2xb5m2, achieves data rates upto 8 Gbs, and dissipates only 7.25 mW of power. To the best of the authorsu0027 knowledge, the proposed PWDM offers the best energy figure compared to the existing pulsewidth demodulator designs.

A 2.8 pJbit 10 Gbs DelayedPhaseSelect 2bit Pulsewidth Modulator in 45nm SOI CMOS This paper presents the design and characterization of a low output jitter and high resolution pulsewidth modulator in 45nm SOI CMOS. The modulator uses a current mode logic (CML) delay line to generate delayed phases of a reference signal. A digital input vector selects a particular delayed phase inside a CML phase selector. The delayed and undelayed phases of the reference are then combined inside a CML OR gate to generate different pulsewidths. The designed 2bit 10 Gbs CML pulsewidth modulator offers the highest time resolution of 10 ps, least output jitter of 0.6 ps, and among the best energy figures of 2.8 p.Jbit in comparison to the reported pulsewidth modulators.