An FPGAbased logstructure Flash memory system for space exploration In space exploration, the flash memory system on the detector needs to retrieve the recorded data and transmit it to the Earth. In order to make better use of valuable transmission time, researchers hope that the system has more accurate retrieval capabilities. In previous spaceborne flash memory system designs, the indexing accuracy of the system was limited by the limited RAM capacity. In this paper, we propose an FPGAbased system design method. This method uses a mechanism of the log structure to manage the flash to save RAM capacity. It can achieve very small data granularity, and each data particle has expandable index information, which improves the system index accuracy with limited RAM capacity. The experimental results show that the proposed system implements a 512Gb flash memory system with pagescale data granularity. It only requires 2.7Mb of RAM capacity overhead for indexing. The system has an average write rate of 329.3 Mbps and an average index latency of 39.3 us.

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA For efficient acceleration on FPGA, it is essential for external memory to match the throughput of the processing pipelines. However, the usable DRAM bandwidth decreases significantly if the access pattern causes frequent row conflicts. Memory controllers reorder DRAM commands to minimize row conflicts; however, generalpurpose controllers must also minimize latency, which limits the depth of the internal queues over which reordering can occur. For latencyinsensitive applications with irregular access pattern, nonblocking caches that support thousands of inflight misses (missoptimized memory systems) improve bandwidth utilization by reusing the same memory response to serve as many incoming requests as possible. However, they do not improve the irregularity of the access pattern sent to the memory, meaning that row conflicts will still be an issue. Sending out bursts instead of single memory requests makes the access pattern more sequential; however, realistic implementations trade high throughput for some unnecessary data in the bursts, leading to bandwidth wastage that cancels out part of the gains from regularization. In this paper, we present an alternative approach to extend the scope of DRAM row conflict minimization beyond the possibilities of general purpose DRAM controllers. We use the thousands of future memory requests that spontaneously accumulate inside the missoptimized memory system to implement an efficient largescale reordering mechanism. By reordering single requests instead of sending bursts, we regularize the memory access pattern in a way that increases bandwidth utilization without incurring in any data wastage. Our solution outperforms the baseline missoptimized memory system by up to 81% and has better worst, average, and best performance than DynaBurst across 15 benchmarks and 30 architectures.