Performance Analysis of Chaotic Symbol Dynamics DecisionBased 8APSK with Enhanced Security for Broadcasting Applications This paper is on the analysis of BER performance of 8ary amplitude phase shift keying (8APSK) using a decision rule called chaotic symbol dynamics that can adjust the Euclidean distance of signal constellation towards optimum BER and enhanced level of security for the transmitted multimedia data. To this regard, an iterative chaotic map is utilized to partition the decision regions of 8APSK. With a control parameter p, it is possible to dynamically adjust the minimum Euclidean distance between two adjacent symbols in the same region. Along with the analytically calculated BER using the proposed decision rule, simulation results confirm that this decision rule based chaotic 8APSK can yield almost identical error performance of 8APSK (both coded and uncoded cases) under AWGN with negligible degradation. Simultaneously it can effectively prevent unauthorized demodulation without prior knowledge of the chaotic map and value of parameter p, hence thus maximizes the information security.

A Digital Pseudo Random Number Generator Based on a Chaotic Dynamic System Chaotic based Pseudo Random Number Generators (PRNGs) have been very popular due to their unpredictable behavior. Hardware implementations of PRNG is used in many applications including cryptography, security and communication systems. Chaotic systems demonstrate an extreme sensitivity to variations in initial conditions and control parameters which makes it ideal for such applications especially cryptography. Due to this severe sensitivity, it is essential to implement the system with a sufficient accuracy while keeping the hardware cost as low as possible. An efficient and compact digital design is proposed for a PRNG based on a lowdimensional chaotic dynamic system. In this design, CORDIC algorithm has been used to reduce the hardware cost while maintaining the accuracy high. Experimental results and error measurements indicate a maximum error of 0.011 and RMSE of 0.0015 between the proposed digital circuits and the original chaotic system. The circuits have been synthesized for an Altera FPGA board. The results indicate that the circuits are successfully able to mimic the mathematical simulation counterpart. In addition, synthesis results verify that the proposed circuits take less than 1% of the target FPGA resources. Furthermore, Static Timing Analysis demonstrate a maximum frequency of 172.09 MHz for the proposed circuits. The proposed circuits can be employed in cryptography and security applications due to their compactness and high accuracy.