Accelerating generalized linear models with MLWeaving: a onesizefitsall system for anyprecision learning Learning from the data stored in a database is an important function increasingly available in relational engines. Methods using lower precision input data are of special interest given their overall higher efficiency but, in databases, these methods have a hidden cost: the quantization of the real value into a smaller number is an expensive step. To address the issue, in this paper we present MLWeaving, a data structure and hardware acceleration technique intended to speed up learning of generalized linear models in databases. MLWeaving provides a compact, inmemory representation enabling the retrieval of data at any level of precision. MLWeaving also takes advantage of the increasing availability of FPGAbased accelerators to provide a highly efficient implementation of stochastic gradient descent. The solution adopted in MLWeaving is more efficient than existing designs in terms of space (since it can process any resolution on the same design) and resources (via the use of bitserial multipliers). MLWeaving also enables the runtime tuning of precision, instead of a fixed precision level during the training. We illustrate this using a simple, dynamic precision schedule. Experimental results show MLWeaving achieves up to16 performance improvement over lowprecision CPU implementations of firstorder methods.

ResourceEfficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs FPGAs have been successfully used for the implementation of dedicated accelerators for a wide range of machine learning problems. The inference in socalled SumProduct Networks can also be accelerated efficiently using a pipelined FPGA architecture. However, as SumProduct Networks compute exact probability values, the required arithmetic precision poses different challenges than those encountered with Neural Networks. In previous work, this precision was maintained by using doubleprecision floatingpoint number formats, which are expensive to implement in FPGAs. In this work, we propose the use of a logarithmic number system format tailored specifically towards the inference in SumProduct Networks. The evaluation of our optimized arithmetic hardware operators shows that the use of logarithmic number formats allows to save up to 50% hardware resources compared to doubleprecision floating point, while maintaining sufficient precision for SPN inference at almost identical performance.