Binarydecisiondiagrambased decomposition of Boolean functions into reversible logic elements Abstract   A binary decision diagram (BDDs) is a compact data structure used to represent a Boolean function, which facilitates scalable constructions of Boolean functions using reversible logic gates. Motivated by the scalable synthesis approach, this paper proposes an effective scheme for transforming the BDD representation of a Boolean function into a reversible circuit composed by reversible logic elements. Unlike a logic gate, a reversible logic element carries a memory to record a finite number of states. Especially, logic circuits composed by reversible elements can operate in asynchronous mode, thereby no need of a clock signal to drive all elements operating simultaneously.

Synthesis of Approximate Logic on Memristive Crossbars The realization of extremely low power compact devices is critical for ubiquitous computing. In that context, approximate computing is one approach towards improving computing efficiency in errortolerant applications that may endure a small loss in accuracy in exchange for better efficiency. In this paper, we present a framework for automated synthesis of crossbar designs that implement approximate versions of compute kernels using flowbased computing. We propose Approximate Free Binary Decision Diagrams (AFBDDs) using a relaxed function equality criterion in node merging. We create AFBDD representations of kernels which are then mapped onto crossbars. These crossbars can compute an approximation of the original compute kernel. Our framework allows us to easily tune the accuracyefficiency tradeoff for an approximate design. We generate designs for RevLib and MCNC benchmarks, and basic image processing kernels. Our designs are up to 80% more compact than exact designs while retaining xe2x89x88 90% accuracy.