Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller Big data which is collected by IoT devices is utilized in various businesses. For security and privacy, some data must be encrypted. IoT devices for encryption require not only to tamper resistance but also low latency and low power. PRINCE is one of the lowest latency cryptography. A glitch canceller reduces power consumption, although it affects tamper resistance. Therefore, this study evaluates the tamper resistance of dedicated hardware with glitch canceller for PRINCE by statistical power analysis and Ttest. The evaluation experiments in this study performed on fieldprogrammable gate array (FPGA), and the results revealed the vulnerability of dedicated hardware implementation with glitch canceller.

Design Tradeoffs in Threshold Implementations With the expansion of the IoT and the emergence of vast amounts of remote hardware devices sidechannel attacks pose a serious threat, requiring adequate protection. Among the hardware countermeasures, Threshold Implementations (TI) is one of the most used ones. It is designed to avoid the leakage of sensitive data from hardware designs. In this work, we examine the cost of applying TI to the block cipher PRINCE with respect to the latency, powerenergy consumption, occupied area. We explore different versions of TI with respect to the security order and TI variations, and compare the strengths and weaknesses of each approach.