A Novel Signed Bitserial Fixedpoint Accumulator with Configurable OverflowProtection Precision In the design of digital signal arithmetic circuits, the serial structure is widely used because of its high clock frequency, low power and area consumption. The bitserial accumulator is the basic arithmetic unit used in the serial systems, and also the key unit for the performance of the whole system. For the requirements of a bitserial accumulator for general digital signal processing (DSP) systems and machine learning (ML) algorithms, a novel scheme of the signed bitserial fixedpoint accumulator is proposed in this paper. For the overflow issue, an overflowprotection circuit with configurable precision is provided as the main contribution of the proposed scheme, which can achieve the tradeoff between accuracy and latency for the signed system design. In the case study, the proposed scheme is applied to the convolution operations in convolutional neural networks (CNNs). The experimental results show that the proposed scheme can achieve a good implementation performance with reconfigurability.

SelfChecking Residue Number System for LowPower Reliable Neural Network Neural Network suffers four major issues including acceleration, power consumption, area overhead and fault tolerance. In this paper we develop a systematic approach to design a lowpower, compact, fast and reliable neural network based on a redundant residue number system. Residue number systems have been applied in designing neural network except the CORDICbased activation functions including hypertangent, logistic and softmax functions. This issue results in that the entire neural network cannot be totally selfchecked and extra operations make the time, power and area reductions wasted. In our systematic approach we propose some design rules for ensuring the checking rate without loss of reductions in time, area and power consumption. From experiments on three neural network with 24bit fixedpoint operations for the MNIST handwritten digit data set, 3, 4, and 5 moduli are separately employed for achieving all balanced improvements in powersaving, areareduction, speedacceleration and reliability promotion. Experimental results show that all the power, time and area can be reduced to only about one third, and the entire network in any combination of software and hardware can be selfchecked in an aliasing rate of only 0.39% and TMRcorrectable under the singleresidue fault model.