Lowcorrelation Lowcost Stochastic Number Generators for Stochastic Computing Stochastic computing provides lowarea and fault tolerant computing circuits. However, the required stochastic number generators (SNGs) in these circuits are area consuming and can diminish their overall saving in hardware size, particularly if several SNGs are required. A SNG circuit consists of two parts: a random number source (RNS), e.g., a linear feedback shift register (LFSR), and a probability converter circuit (PCC), e.g., a comparator. In this paper, we propose areaefficient SNGs by sharing the permuted output of one RNS among several SNGs. With no hardware overhead, the proposed architecture generates random bit streams with minimum stochastic computing correlation (SCC). Compared to the circular shifting approach presented in recent prior work, our approach produces stochastic bit streams with 52% and 67% less average SCC when a 8bit and a 10bit LFSR are shared between two SNGs, respectively. We evaluated the proposed method for several applications. The results show that, compared to prior work, our approach yields lower MSE values with the same (or even lower) areacost.

AreaEfficient Parallel Stochastic Computing with Shared Weighted Binary Generator Stochastic computing (SC), a computing paradigm with strong fault tolerance, draws more attention recently. However, a drawback of SC is its long latency. One straightforward way to reduce the latency is to use parallel bit streams to encode data and apply multiple copies of the circuit to process the bit streams. However, this method multiplies the circuit area. In this work, we propose to share the random numbers sources (RNSs) and part of the probability conversion circuits (PCCs) to reduce the area of the parallel version of the stochastic circuit. In this work, we propose a method to share the weighted binary generatorbased stochastic number generator to reduce the area of the parallel implementation of the stochastic circuit. Our experimental results showed that the accuracy of our design is slightly better than the traditional comparatorbased design. Besides, our design can reduce the arealatency product by 58.5% compared to the serial implementation.