SoCFPGABased Implementation of Iris Recognition Enhanced by QCLDPC Codes Introducing error correction codes into an iris recognition system to solve the intrinsic fuzziness, like variability and noise in iris codes is a research area that hasnu0027t catch massive attention, but the positive effect brought by error correction should not be underestimated. Rather than theoretical analysis and simulation that have been wellunderstood and deeply explored, in this paper, we focus on an iris recognition system implementation with an error correction scheme, namely QCLDPC and the whole system is based on a compact SoCFPGA platform which is a DE10 nano Cyclone V SOC evaluation board by Intel. Every iris information bit as the input data in this platform will be stored after they are encoded as QCLDPC codes which make the whole system more feasible than normal LDPC codes and loaded to improve the acceptance rate when a verification request is invoked with a new series of iris information. Moreover, the fundamental modules, such as iris processing, LDPC encoding and decoding in the system are reorganized and distributed to which section (HPS or FPGA) they are more suitable to be employed into, leading to a single chip design.

A ResourceEfficient Embedded Iris Recognition System Using Fully Convolutional Networks Applications of Fully Convolutional Networks (FCN) in iris segmentation have shown promising advances. For mobile and embedded systems, a significant challenge is that the proposed FCN architectures are extremely computationally demanding. In this article, we propose a resourceefficient, endtoend iris recognition flow, which consists of FCNbased segmentation, contour fitting, followed by Daugman normalization and encoding. To attain accurate and efficient FCN models, we propose a threestep SWHW codesign methodology consisting of FCN architectural exploration, precision quantization, and hardware acceleration. In our exploration, we propose multiple FCN models, and in comparison to previous works, our bestperforming model requires 50X less FLOPs per inference while achieving a new stateoftheart segmentation accuracy. Next, we select the most efficient set of models and further reduce their computational complexity through weights and activations quantization using 8bit dynamic fixedpoint (DFP) format. Each model is then incorporated into an endtoend flow for true recognition performance evaluation. A few of our endtoend pipelines outperform the previous stateoftheart on two datasets evaluated. Finally, we propose a novel DFP accelerator and fully demonstrate the SWHW codesign realization of our flow on an embedded FPGA platform. In comparison with the embedded CPU, our hardware acceleration achieves up to 8.3X speedup for the overall pipeline while using less than 15% of the available FPGA resources. We also provide comparisons between the FPGA system and an embedded GPU showing different benefits and drawbacks for the two platforms.