A LowPower, HighSpeed Readout for Pixel Detectors Based on an Arbitration Tree In this article, a lowpower, highspeed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a positiondependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zerosuppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65nm LPCMOS process for the readout of a    64times64    pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of 50 kfps, achieved with a dedicated output for every (   32times32   ) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

A full functional Monolithic Active Pixel Sensor prototype for the CEPC vertex detector The proposed Circular ElectronPositron Collider (CEPC) presents new challenges for pixel detectors in terms of cell size and functionality. A high data rate digital design and readout architecture of a Monolithic Active Pixel Sensor (MAPS) prototype for the CEPC vertex detector is presented. The MAPS prototype, together with the column drain based readout architecture, benefiting from the ALPIDE (ALice PIxel DEtector) and FEI3 approaches, has been implemented to achieve high spatial resolution, fast readout, and low power consumption. The simulation results indicate the readout logic works properly with input data rates of 120MHz; while both analog frontend and inpixel readout logic meet the 25ns bunch spacing constraint.