IP Core Identification in FPGA Configuration Files using Machine Learning Techniques In modern day industry and scientific research, pertaining to experimental scenarios, real world applications or consumer electronics, Field Programmable Gate Arrays (FPGAs) are becoming a popular choice. The very distinctive nature of FPGAs enables reconfigurability, scalability and adaptivity of the associated embedded design which makes it a remarkable alternative to traditional hardware. An FPGA is able to dynamically reconfigure itself during runtime, entirely or partially, by way of unloading and loading bitstreams. In this paper, an approach is introduced to analyze and inspect FPGA bitstreams by making use of supervised machine learning. By exploiting machine learning, we demonstrate how neural networks can be trained to identify and trace a certain hardware module or an IP core (Intellectual Property core) with some known functionality in FPGA bitstreams. We perform an analysis of FPGA bitstreams by incorporating Artificial Neural Networks (ANNs) based classification ranging from Multiple Layer Perceptrons (MLPs) or to modern Convolutional Neural Networks (CNNs).

Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration Implementations of hardware accelerators for neural networks are increasingly popular on FPGAs, due to flexibility, achievable performance and efficiency gains resulting from network optimisations. The long compilation time required by the backend toolflow, however, makes rapid deployment and prototyping of such accelerators on FPGAs more difficult. Moreover, achieving high frequency of operation requires significant lowlevel design effort. We present a neural network overlay for FPGAs that exploits DSP blocks, operating at near their theoretical maximum frequency, while minimizing resource utilization. The proposed architecture is flexible, enabling rapid runtime configuration of network parameters according to the desired network topology. It is tailored for lightweight edge implementations requiring acceleration, rather than the highest throughput achieved by more complex architectures in the datacenter.