A 96kb, 0.36V, EnergyEfficient 8TSRAM with ColumnSelection and Shared BufferFoot Techniques for EEG Processor In previous standard singleended (SE) 8TSRAM design, rare research effort has been made to address a major issue related to columnselection. This work proposes a shared dataaware write technique which facilitates bitinterleaving architecture for the SE8T SRAM. In addition, a shared bufferfoot scheme is also presented to achieve bitline leakage reduction. A 96kb SE8T SRAM with the proposed techniques, aimed to be applied to an electroencephalogram (EEG) processor, is implemented using a 65nm CMOS. Measured results show that it achieves a VDDmin of 0.36V, and a minimal power of 5.1xcexbc W, as well as an optimal total energy consumption of 25.6pJ0.5V.

Neuromorphic Hardware Accelerator for SNN Inference based on STTRAM Crossbar Arrays In this paper, we propose a Spin Transfer Torque RAM (STTRAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the timebased signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of nonvolatile STTRAMs, readwrite peripheral circuits, and digital logic for the spiking neurons. Intercore communication is realized through onchip routing network by sendingreceiving spike packets. Unlike prior works that use multilevel states of nonvolatile memory (NVM) devices for the synaptic weights, we use the technologicallymature STTRAM devices for binary data storage. The design studies are conducted using a compact model for STTRAM devices, tuned to capture the stateoftheart experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STTRAM based neurosynaptic core designed in 28 nm technology node has approximately 6xc3x97 higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves xe2x88xbc 2xc3x97 higher performance per Watt compared to other memristive neural network accelerator designs in the literature.