Controller redesign for delay margin improvement Abstract   Two important design objectives in feedback control are steadystate error minimization and delay margin maximization. For many practical systems it is not possible to have infinite delay margin and zero steady state error for unit step reference input. This paper proposes a redesign method for controllers initially designed to satisfy the steadystate error requirement. The objective is to make structural changes in the controller so that a lower bound of the delay margin is improved without affecting the steadystate error. The order of the new controller is     (  xcexbd    1  )     higher than the order of the original controller, where    xcexbd    is the number of unstable poles of the plant.

On Stability of Current Controlled Drives with Delay in Feedback Path Mechatronic systems nowadays heavily depend on current regulated electromechanical actuators. The current regulation is achieved with proportional and integral controllers that execute every PWM period. However, growing embedded algorithm complexity is causing feedback sampling to be delayed inadvertently. This research paper demonstrates the impact of delayed sampling on the stability of the closedloop system from a discrete control system perspective. A currentcontrolled DC motor drive system with increasing delay in the feedback path is evaluated under varying system parameters are studied. Analysis, simulation, and experimental results are presented with good correlation on the effect of delayed sampling in the feedback system of a current regulated drive.