Design of Integrated Control Circuits for mmWave Phased Arrays in 55nm BiCMOS This paper presents the design of different control circuits for integrated Dband phasedarray transceivers, implemented using a 55nm BiCMOS process. An SPI slave controller is first presented, which is able to control a bank of sixteen 8bit registers. The design of an integrated ringoscillator based clock generator is then described, which oscillates at 44 MHz. Finally, a currentsteering 8bit DAC is presented, which provides a current of 01.8 mA with a DNL lower than 0.9 LSB. The DAC can be used to generate bias currents for mmwave phase shifters and amplifiers, as well as to generate selftest signals at a sampling frequency of up to 100 MSPS. The clock and DAC have been implemented on a test chip that occupies 0.5 mm xe2xa8xaf 0.4 mm.

A 60GHz DigitallyControlled Differential Reflectiontype Phase Shifter in 65nm CMOS with Low Phase Error In this paper, a 60GHz digitallycontrolled passive reflectiontype phase shifter (RTPS) is presented for mmWave phased array communication applications. The RTPS consists of two 3dB quadrature couplers and four znetworks loads. To enhance the channel isolation of the phased array system, a transformer based quadrature coupler and differential topology is used. The RTPS is fabricated in a 65nm CMOS process with a size of 475.0xc3x97434.3um2, while consuming zero power consumption. With a 4bit digital switchedcapacitor array, test results shows that a 90xc2xb0 phase range is achieved. From 57 to 64GHz, the phase shifter rms phase error is below 4.7xc2xb0, and its total insertion loss is 8.7xc2xb11.1 dB at 61GHz.