CCP: Configuration Context based Prefetching to Improve CoarseGrained Reconfigurable Array Performance Coarsegrained reconfigurable arrays (CGRA) with high performance cache prefetching can mitigate offchip memory latency. Taking advantage of the iteration number of configuration context running on CGRA, this paper proposes a configuration context based prefetching (CCP) mechanism for CGRA. CCP utilizes the first 256 memory accesses to obtain best offset of demand addresses to base address, and then associates it with configuration context to generate prefetching addresses on a cache miss. Moreover, to reduce bandwidth consumption caused by inaccurate prefetching, CCP dynamically adjusts prefetch degree according to configuration context and the current accuracy. Choosing 13 dwarfs as benchmarks, experimental results show that the proposed CCP mechanism can effectively improve CGRA performance, averagely improving by 35.23% compared to LRU (noprefetching baseline), by 12.98% compared to PACMan and by 10.41% compared to SBP, respectively.

A CoarseGrained Reconfigurable Architecture with a Fault Tolerant NonVolatile Configurable Memory Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse Grain Reconfigurable Arrays (CGRAs) are suitable because of their high energy efficiency. However, even in CGRAs, the leakage power for its configuration memory must be reduced. Although the power gating is a popular technique, the data in flipflops and memory are lost so they must be retrieved after the wakeup. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Nonvolatile Cool Mega Array (NVCMA), a CGRA providing nonvolatile flipflops (NVFFs) with spin transfer torque type nonvolatile memory (NVM) technology has been developed. However, in general, nonvolatile memory technologies have problems with reliability. Some NVFFs are stackedat01, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Then, we also propose a method to add an errorcorrecting code (ECC) mechanism to NVFFs used for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the 99.4% availability ratio is achieved with 0.1% probability of faulty FFs, while almost no chips are available without using them. The energy for storing data becomes about 2.28 times because of the hardware overhead of ECC but the proposed method can save 11.1% of the storing energy on average.