MRL CrossbarBased Full Adder Design Memristor technology has acquired great interest in the field of nonvolatile memories as well as logic computation. The nanoscale structure of memristor and the possibility of its integration with MOSFETs have triggered many efforts to reconstruct basic digital building blocks. Recently, Memristor Ratioed Logic (MRL) has been introduced as a hybrid memristorCMOS logic design style, which has been functionally validated. In this paper, a 1bit full adder is designed by implementing MRL in crossbar array. The new design methodology efficiently integrates memristors at the top of CMOS layer. The corresponding layout and simulation results are performed using Cadence Virtuoso toolset targeting CMOS 65 nm process. The obtained results and their corresponding comparison illustrate promising outcomes in terms of implementation area, energy consumption and speed.

Crossbar Memory Architecture Performing Memristor Overwrite Logic The nonvolatile resistive state of memristor and the ease of controlling this state have triggered its usage in the design of nonvolatile memories as well as logic design applications. The memristor based material implication (IMPLY) and memristor aided logic (MAGIC) have been recently presented as new methods to achieve logic computations inside memristive memory architectures. However, these methods are still surrounded by several design constraints. In this context, we present new design for memristive memories with an added computational capabilities. These capabilities are exclusively based on our proposed logic design style, namely Memristor Overwrite Logic (MOL) which is fully digital and tolerant against memristor technology variations.