OpenMPL: An Open Source Layout Decomposer: Invited Paper Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decomposition (MPLD) is critical to design closure. Due to the  mathcalNP hardness of the general decomposition problem, various efficient algorithms have been proposed with high quality solutions. However, with increasingly complicated design flow and peripheral processing steps, developing a highquality layout decomposer becomes more and more difficult, slowing down the further advancement in this field. This paper presents OpenMPL 1, an opensource layout decomposition framework, with wellseparated peripheral processing and the core solving steps. We demonstrate the flexibility of the framework with efficient implementations of various stateoftheart algorithms, which enable us to reproduce most of the recent results on widelyrecognized benchmarks. We believe OpenMPL can pave the road for developing layout decomposition engines and stimulate further researches on this problem.

FBM: A Simple and Fast Algorithm for Placement Legalization In VLSI physical design, the legalization step has to deal with thousands of logic cells that need to provide a placement solution with all cells aligned within the rows and overlapfree, while preserving the global placement solution, i.e., displacement should minimize. We present an algorithm for VLSI placement legalization that minimizes the impact of wirelength in highdensity circuits. Our approach is based first on sorting the cells according to their positions and legalizing each pair of overlapping cells. The algorithm moves the second overlap cell to the right until it finds a legalized placement with the lowest movement. Our experimental results show that our algorithm can reduce the runtime with a minimum impact on wirelength when compared to another legalization tool.