Recruiting Fault Tolerance Techniques for Microprocessor Security The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging microarchitectural side channels such as due to speculative execution to implementing cryptographic accelerators for sidechannel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of u0027security faultsu0027 (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive sidechannels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the repurposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active sidechannel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic subcomponent of a RISCV based secure systemonchip, against a formidable fault attack called SIFA.

Improving Softwarebased Techniques for Soft Error Mitigation in OoO Superscalar Processors Highperformance superscalar processors have been developed to satisfy the growing demand for processing modern applications. However, as the transistor size shrinks, the increase in vulnerability to soft errors poses a great challenge, since these effects have been proven to also affect groundlevel safetycritical applications. Considering that vulnerability strategies may span across different layers of the system stack, we propose a mixed SWHWbased designtime methodology aiming to achieve the best tradeoff between vulnerability and areaenergy for superscalar processors. By injecting over 10 million faults in 12 significant microarchitectural structures to different versions of the complex BOOM OoO superscalar processor modeled with RTL accuracy, we show that SWbased protection techniques always reach an upper bound that may not be satisfactory. Then, we propose to insert extra lowlevel HWbased DMR protection at strategic microarchitectural points by reducing this task to the Knapsack Problem. In one of the evaluated cases, we optimally find the best structures to be protected with 55% area overhead to achieve a 95% vulnerability improvement for a quadissue processor.