xc2xb5W Preprocessing Unit for Virtual Sensors Based on Triaxial Smart Accelerometers In this paper, for the first time in the literature, a custom circuit is proposed to process the heavy calculations needed to change in realtime the reference coordinate system of vectors measured by triaxial accelerometers, in order to make a preprocessing stage for the building of virtual sensors like linear and gravity accelerometers. To this purpose, a new xe2x80x9chardware friendlyxe2x80x9d algorithm has been derived which can be implemented in a more compact iterative structure to combine high accuracy and low power consumption, in order to conveniently integrate it into the circuitry of smart accelerometers. Synthesis with 65 nm CMOS std_cells returns a power dissipation of 0.89 xc2xb5W and an area of about 0.024 mm2. Results are the current stateoftheart for this kind of applications and they are very promising for the future integration in smart sensors for wearable applications.

Design and Implementation of an OnChip LowPower and HighFlexibility System for Data Acquisition and Processing of an Inertial Measurement Unit For signal processing of a MicroElectroMechanical System (MEMS) Inertial Measurement Unit (IMU), a digitalanalog hybrid systemonchip (SoC) with small area and low power consumption was designed and implemented in this paper. To increase the flexibility of the processing circuit, the designed SoC integrates a lowpower processor and supports three startup or debugging modes for different application scenarios. An applicationspecific computing module and communication interface are designed in the circuit to meet the requirements of IMU signal processing. The configurable clock allows users to dynamically balance computing speed and power consumption in their applications. The chip was taped out under SMIC 180 nm CMOS technology and tested for performance. The results show that the chipu0027s maximum running frequency is 105 MHz. The total area is 33.94 mm2. The dynamic and static power consumption are 0.65 mWMHz and 0.30 mWMHz, respectively. When the system clock is 25 MHz, the dynamic and static power consumption of the chip is 76 mW and 66 mW, and the dynamic and static power consumption of the FPGA level are 634 mW and 520 mW. The results verify the superiority of the application specific integrated circuit (ASIC) solution in terms of integration and low power consumption.