An FPGA based verification platform for pipeline ADC digital calibration technology In fine line technology, pipeline ADC performance improvement is difficult and power consumption becomes more considerable. In this context, digital calibration algorithm is applied to improve system performance and reduce power consumption. In order to verify pipeline ADC digital calibration technology before chip verification, to evaluate power consumption and hardware overhead, an FPGA based verification platform is established. In this platform, ADC digital model is established to simulate the actual ADC, digital calibration algorithm is described by digital calibration module, and the ideal ADC is used to provide input signal for the system. Applying this platform, simulation is carried out in a deterministic digital calibration technique. The simulation results show that, by applying of the platform, the correctness and reliability of the design of pipeline ADC digital calibration system can be effectively improved, and the system developing cycle can be shortened.

An Automatic SlopeCalibrated Ramp Generator for SingleSlope ADCs This paper presents a ramp generator with automatic slope calibration which is able to compensate slope deviation due to process and environmental effects. A novel analog feedback circuit is proposed to regulate the stop voltage in successive approximation while fix the start voltage of the ramp automatically without much calibration code input or complicated auxiliary circuits, which reduces the complexity of circuitry and timing, meanwhile, saves area and power. A 12bit singleslope ADC (SSADC), employing the proposed ramp generator, has been implemented in a 0.11xc2xb5m CMOS process. The simulation results show that the offset of the rampu0027s stop voltage is reduced to 0.1 LSB and the nonlinearity of the ramp is 0.034%. Besides, the measurement results verify that this structure can fulfill automatic slope calibration.