A High Performance FPGABased Accelerator Design for EndtoEnd Speaker Recognition System Speaker recognition technique is significant for identification applications. Xvectors, a robust textindependent speaker recognition system, spends plenty of time on extracting voiceprint features due to massive neural network computation and scoring with all the people registered in the database to find the best match person. In this paper, an FPGAbased highperformance accelerator for this endtoend speaker recognition system is proposed, which contains three parts: Mel Frequency Cepstral Coefficients (MFCC), time delay neural network (TDNN) and probabilistic linear discriminant analysis (PLDA) classifier. A quantitative analysis is presented to balance the bit width and the recognition accuracy. In addition, an optimization strategy to make a tradeoff between the system parallelism and the FPGA resource utilization is introduced. As a comparison, the proposed accelerator running on Xilinx XCVU9P FPGA of UltraScale VCU118 board can achieve a peak performance of 1.067 TOPs and 1.30xc3x97105 voice frames per second (vFPS) with 200MHz, which can obtain 1296xc3x97 speedup compared with Xvectors software implementation running on a 2.5GHz Intel Xeon E52620 processor and 6.42xc3x97 energy efficiency than Nvidia TITAN Xp GPU solution.

A High EnergyEfficiency FPGABased LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear Quantization LSTM (Long ShortTerm Memory) is an artificial recurrent neural network (RNN) architecture and has been successfully applied to the areas where sequences of data need to be dealt with such as Natural Language Processing (NLP), speech recognition, etc. In this work, we explore an avenue to minimization of the LSTM inference part design based on FPGA for high performance and energyefficiency. First, the model is pruned to create structured sparse features for the hardwarefriendly purpose by using permuted block diagonal mask matrices. To further compress the model, we quantize the weights and activations following a normalized linear quantization approach. As a result, computational activities of the network are significantly deducted with an egligible loss on accuracy. Then a hardware architecture design has been devised to fully exploit the benefits of regular sparse structure. Having been implemented on Arria 10 (10AX115U4F45I3SG) FPGA running at 150 MHz, our accelerator demonstrates a peak performance of 2.22 TOPS at a power dissipation of 1.679 Watts. In comparison to the other FPGAbased LSTM accelerator designs previously reported, our approach achieves a 1.172.16x speedup in processing.