A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA Implementation of fast semantic segmentation in an embedded system is necessary due to the increasing interest in automatic driving and energyefficiency is a fundamental metric in such a scenario. Because highresolution images are required to achieve high segmentation accuracy, its accelerator must prepare large buffers for the corresponding feature maps, and it is not suitable for the limited onchip memory of an FPGA. To address this, we propose a tile segmentation algorithm and develop an FPGAbased accelerator for a sparse MobileNetbased PSPNet. To reduce the buffer size, the tile segmentation algorithm splits incoming images into the numbers determined by the stride on an FPGA. The PSPNet then performs many split tiles. Moreover, we propose a pipelined sparse convolutional circuit to compute multiple tiles with highspeed. We compared the proposed FPGAbased system with the NVIDIA RTX 2080 Ti using the Cityscapes benchmark. The FPGA achieved 139 FPS with 24 W power consumption for a 1024xc3x97512 image, and its accuracy (mIoU) was 64.2%. Compared with the GPU, it was 1.5 times faster, its power consumption was 9.3 times lower, and its performance per power consumption was 13.8 times better.

A Tilebased FusedLayer Approach to Accelerate DCNNs on LowDensity FPGAs Accelerating Deep Convolutional Neural Networks on FPGAs is achieving a lot of interest across a wide range of applications such as image recognition and classification. Although memory requirement still represents a challenge for fast and efficient inference workloads, fusedaccelerated layers have been recently proposed to mitigate memory bandwidth problems. In this scenario, we propose a tiledbased fusedlayer approach to exploit temporal and spatial locality in mapping a DCNN to a specialized lowdensity FPGA. In our tilebased approach, we propose applying a fusing depth of two convolutional layers in order to fit into a lowdensity FPGA without affecting the performance, while reducing the memory bandwidth. We demonstrated the effectiveness of our twofused layer approach to accelerate the VGG16 network on a Zynq7020. We achieved an average speedup of 1.44x times, while saving up to 61% of memory transactions with respect to a baseline represented by tiledonly (notfused) version. A tiledbased fullyfused version of VGG16 would not have been feasible to be mapped on a lowdensity Zynq7020.