On the Implementation of a Rotated Chaotic Lorenz System on FPGA Recent advances in engineering applications of chaos include multimedia security, disturbance modeling in power systems and performance enhancement of electronic circuits among others. This paper discusses the implementation of a rotated Lorenz chaotic system on a Field Programmable Gate Array (FPGA). Unlike most published work, we do not rely on Hardware Description Language (HDL) code generated from MATLABSIMULINK using general code conversion tools like HDL coder. Instead, we code the system and all of its modules using the Verilog HDL and highlight the benefits of taking this approach in allowing for a systematic design procedure that tends to minimize the complexity of the design, the number of design errors and simplifies the debugging process. We anticipate that by using Verilog HDL and not relying on convertersgenerated code, we can improve on hardware resource utilization, synthesis frequency, accuracy, and throughput. The platform used is the DE2115 development board equipped with Altera Cyclone IV FPGA device.

A Digital Pseudo Random Number Generator Based on a Chaotic Dynamic System Chaotic based Pseudo Random Number Generators (PRNGs) have been very popular due to their unpredictable behavior. Hardware implementations of PRNG is used in many applications including cryptography, security and communication systems. Chaotic systems demonstrate an extreme sensitivity to variations in initial conditions and control parameters which makes it ideal for such applications especially cryptography. Due to this severe sensitivity, it is essential to implement the system with a sufficient accuracy while keeping the hardware cost as low as possible. An efficient and compact digital design is proposed for a PRNG based on a lowdimensional chaotic dynamic system. In this design, CORDIC algorithm has been used to reduce the hardware cost while maintaining the accuracy high. Experimental results and error measurements indicate a maximum error of 0.011 and RMSE of 0.0015 between the proposed digital circuits and the original chaotic system. The circuits have been synthesized for an Altera FPGA board. The results indicate that the circuits are successfully able to mimic the mathematical simulation counterpart. In addition, synthesis results verify that the proposed circuits take less than 1% of the target FPGA resources. Furthermore, Static Timing Analysis demonstrate a maximum frequency of 172.09 MHz for the proposed circuits. The proposed circuits can be employed in cryptography and security applications due to their compactness and high accuracy.