Research on Area Modeling Methodology for FPGA Interconnect Circuits Area models were proposed to estimate the implementation area in the early stage of chip design, and it is widely used in architectural exploration of advanced FPGA blocks and transistor sizing of FPGA interconnect circiuts. Models in previous works have been proven to significantly overestimate the implementation area. This paper aims to propose area models more applicable to interconnect in FPGA, considering the features of actual layout more. Also, this paper compared the estimated area with the layout area of actual interconnect circuits in FPGA to check whether area models proposed are of high accuracy. The results showed that model errors of area models proposed in this paper for nine kinds of interconnect subcircuits were all within xc2xb1 10% and much better than area models proposed in previous papers. It is concluded that this area model is more suitable for modern FPGA interconnect circuits.

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures Following the rapid growth of Field Programmable Gate Arrays (FPGAs) sizes, the regularity of architectures has become a critical feature, leading to the development of millionofLUT devices. While the routing architecture plays a dominant role in the area, delay and power of modern FPGAs, most of previously published works focus on improving the routability and performance of FPGAs while very few studied tileable (highlyregular) routing architectures. In this paper, we provide a detailed analysis between tileable and popular nontileable FPGAs considering modern routing architectures. First, we upgrade VPR to generate tileable routing architecture, which can support different switch block patterns for (1) the routing tracks that startend in a tile and (2) the routing tracks that pass through a tile. Then, we evaluate the performance of mixed switch blocks patterns in the context of a Stratix IVlike FPGA architecture, by considering the most representative patterns, i.e., Subset, Universal and Wilton. Experimental results show that averaged over the MCNC and VTR benchmarks, when compared to the welloptimized nontileable architectures, the tileable architectures can improve the minimum routable channel width by 13% and areadelay product by 2%. In particular, our results showed that in the context of tileable FPGA, a mix of Universal and Wilton switch block patterns lead to the best tradeoff in area, delay and routability, while Wilton switch block was the best choice in nontileable FPGAs.