A Configurable Architecture of ANN in Hardware with ResourceEfficient Reusable Neuron Artificial Neural Network (ANN) is one of the most important structure of machine learning and it has been widely used in various areas such as medical diagnosis, image classification and signal processing. The large area and resource cost make it difficult for the realization of ANN in hardware. This paper presents a flexible architecture of ANN with resourceefficient reusable neuron. The dynamical activation method of neurons is proposed and utilized to make the ANN more flexible and configurable. The designed structure of neuron supports multiple calculation modes which is reused in both feedforward and backpropagation. The approach of multiplexing layer is adopted to reduce the number of physical layers to 1. The simulation results show the proposed method can achieve the function of ANN while significantly reducing the resource cost and area.

WINNER: a high speed high energy efficient Neural Network implementation for image classification Nowadays, Neural Networks are often used in many applications to solve very complex tasks like speech recognition or image classification. In applications like image recognition, time is a critical constraint and a Neural Network must be able to correctly classify an image in a very short time: in these cases, hardware accelerators are necessary. In this work, a hardware implementation of a Neural Network is proposed. As a reference model, AlexNet has been chosen and implemented as an ASIC, by adopting an InMemory computing design. The concept of InMemory is based on the idea of placing small computational units near the memory element. This choice brings to relevant benefits, reducing the bottlenecks coming from a Von Neumannu0027s system (such as fetching latency and energy inefficiency due to the communication between logic and memory). The architecture has been synthesized on a 45nm CMOS technology and highlights remarkable results, with very high framepersecond (FPS) (comparable to binary neural network implementations) combined with low values of EnergyFPS and a maximum operating frequency of 281MHz. The system is also partially reconfigurable, enabling the mapping of different kind of neural networks.