Adaptive FIR filter design and implementation empowered by reconfigurable FPGAs This paper explores the design and implementation of an adaptive Finite Impulse Response (FIR) Filter on Reconfigurable Computing Technology (RCT). RCT deploys Field Programmable Gate Array (FPGA) technology as a flexible platform for implementing and improving digital systems design. Filters are used in data conditioning environments between transducers and digital systems for many industrial applications such as aerospace, telecommunications, and computers. They are one of the most demanding applications for changing operation requirements, in terms of data size, functionality and noise ratio. This study takes advantage of the flexibility and adaptability of the emerging FPGAs technology for such applications. The deployment of an FPGA for filter design and implementation represents the most promising solution for changing operation requirements as compared to other solutions including the use of dedicated DSP processors. The paper describes the methodology followed throughout the analysis, design, verification, simulation, and implementation of the filter. It also elaborates on the scalability of the proposed design to more complex functions, higher resolution data, and variations in building arithmetic functions.

Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion This paper presents an FPGA implementation of the Real Valued Time Delay Neural Network (RVTDNN) based digital predistortion with a very low resource utilization and high throughput. The implementation exploits efficient utilization of FPGA primitives and approximation of activation functions that can be realized with simple logic operations. The proposed modifications and constraints on the algorithms have been decided and verified based on a closedloop adaptive hardware setup including RFHIC RWP030401H PA as the unit under test together with injected RF impairments. Over 20dB of inband performance gain has been reported with a (4,8,2) RVTDNN configuration utilizing only 52 DSP48 blocks, 224 LUTs and 120 FFs.