UltraLow Power Silicon Neuron Circuit for ExtremeEdge Neuromorphic Intelligence Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for cloudless edge computing applications. In an effort to reduce power consumption even further, we propose beyond vonNeumann inmemory computing architectures that can process the signals at the sensor side using ultralow power mixedsignal analogdigital circuits which have properly matched dynamics and timeconstants. In this paper, we propose one of the main computing elements of such architectures, namely the silicon neuron, designed using analog circuits in an advanced FDSOI 22 nm node. Here we optimize the design of an Adaptive Exponential Integrate and Fire (AdExp IF) neuron model for producing neural dynamics with biologically plausible time constants. We explore the options of the 22 nm FDSOI technology to address the analog design issues that arise from advanced scaling (such as leakage) and minimize power consumption by using a novel current comparator circuit with currentdriven positive feedback. We present circuit simulation results which reproduce biologically plausible responses and compare the circuit energy per spike with stateoftheart architectures. The proposed neuron design consumes one order of magnitude less power compared to the stateoftheart and two orders of magnitude less compared to a pure digital implementation.

Enabling EnergyEfficient and Reliable Neural Network via NeuronLevel Voltage Scaling As the application scope of deep neural networks (DNNs) moves from largescale data centers to smallscale mobile devices, power wall has become one of the most important obstacles. Voltage scaling is a typical technique enables power saving, but it causes reliability and performance challenges. Therefore, an energyefficient and reliable scheme for NNs is required to balance above three aspects according to usersu0027 requirements for excellent user experience. In this paper, we innovatively propose neuronlevel voltage scaling framework called NNAPP to model the impact of supply voltages on NNs from output accuracy (A), power (P), and performance (P) perspectives. We analyze the error propagation in NNs and precisely model the impact of voltage scaling on the final output accuracy at neuronlevel. Multiobjective optimization and clustering method are combined to find the optimal voltage islands. Finally, we conduct experiment to demonstrate the efficacy of the proposed technique.