Onechannel ZeroIF Multimode GNSS Receiver with Selfadaptive Digitallyassisted Calibration A onechannel ZeroIF multimode GNSS receiver is presented for GPSGalileoBDSIII signals in 130 nm CMOS, which can be switched between two different working bands: 1.6 GHz including GPSL1GalileoE1 BDSB1iBDSB1c and 1.2 GHz including GPSL5 GalileoE5aBDSL2a. Selfadaptive digitallyassisted calibration schemes are integrated to ensure the receiver shows a strong robustness for PVT variation. While drawing about 34.5 mA current from a 1.8 V supply, this GNSS receiver achieves a minimum noise figure (NF) of less than 1.8 dB, a maximum channel gain of 122 dB with 82 dB dynamic range and 2 dB precision, an inputreferred P1dB of about xe2x88x9240 dBm, and a coherent demodulation requirement (E b N 0 ) of less than 10 dB with BER of 10xe2x88x925 for BPSK modulation after IQMC.

NaviSoC: HighAccuracy LowPower GNSS SoC with an Integrated Application Processor A dualfrequency allinone Global Navigation Satellite System (GNSS) receiver with a multicore 32bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a SystemonChip (SoC) in a 110 nm CMOS (complementary metaloxide semiconductor) process. The GNSS RF (radio frequency) frontend with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1E5ab, GPS (US Global Positioning System) L1L1CL5, BeiDou (Chinese Navigation Satellite System) B1B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1L3L5, QZSS (QuasiZenith Satellite System development by the Japanese government) L1L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for highaccuracy positioning. The whole SoC (systemonchip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the xe2x88x9240 to 105 xc2xb0C temperature range with a 1.5 V supply. The assembled testchip takes 100 pins in a QFN (quadflat noleads) package and needs only a quartz crystal for the onchip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1E1 and L5E5 is NF  2.3 dB, G  131 dB, with 121 dBcHz of phase noise  1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dualfrequency singlechip GNSS receiver equipped with a multicore application microcontroller integrated with embedded flash memory for the user application program.