A design flow for an optimized congestionaware applicationspecific wireless networkonchip architecture Abstract   Wireless NetworksonChip (WiNoC) architecture has emerged as an alternative communication infrastructure for the conventional wireline NoC to achieve higher performance and low energy dissipation in onchip communications. However, as realistic applications have different communication requirements, applicationspecific platforms are attractive to guarantee a specific level of performance. Moreover, the congestion probability over wireless routers is high, because each wireless router is shared by a group of cores. Therefore, we propose a novel methodology for designing an optimized congestionaware applicationspecific WiNoC architecture. This methodology utilizes a novel meshoftree (MoT) topology as a communication infrastructure to exploit the benefits of both mesh and tree topologies. Then, for a given application, the longdistance wirewireless links are inserted into the MoT topology by considering the optimization of system cost and performance simultaneously. Furthermore, a congestionaware layered routing is presented to reduce the congestion probability. Through cycleaccurate simulations, the performance of the proposed architecture has been evaluated and compared with stateoftheart works under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption. Moreover, the area overhead associated with the proposed WiNoC architecture is investigated. The experimental results confirmed that the proposed MoTbased WiNoC architecture is a very competitive architecture among the alternative WiNoC architectures.

Data Conversion in AreaConstrained Applications: the Wireless NetworkonChip Case NetworkonChip (NoC) is currently the paradigm of choice to interconnect the different components of SystemonChips (SoCs) or Chip Multiprocessors (CMPs). As the levels of integration continue to grow, however, current NoCs face significant scalability limitations and have prompted research in novel interconnect technologies. Among these, wireless intrachip communications have been under intense scrutiny due to their low latency broadcast and architectural flexibility. Thus far, the practicality of the idea has been studied from the RF frontend and the network interface perspectives, whereas little to no attention has been placed on another essential component: the data converters. This article aims to fill this gap by providing a comprehensive analysis of the requirements of the scenario, as well as of the current performance and cost trends of AnalogtoDigital Converters (ADCs). Based on Murmannxe2x80x99s data, we demonstrate that ADCs will not be a roadblock for the realization of wireless intrachip communications although current designs do not meet their demands fully.