FBM: A Simple and Fast Algorithm for Placement Legalization In VLSI physical design, the legalization step has to deal with thousands of logic cells that need to provide a placement solution with all cells aligned within the rows and overlapfree, while preserving the global placement solution, i.e., displacement should minimize. We present an algorithm for VLSI placement legalization that minimizes the impact of wirelength in highdensity circuits. Our approach is based first on sorting the cells according to their positions and legalizing each pair of overlapping cells. The algorithm moves the second overlap cell to the right until it finds a legalized placement with the lowest movement. Our experimental results show that our algorithm can reduce the runtime with a minimum impact on wirelength when compared to another legalization tool.

A System for Standard Cell Routability Checking and Placement Routability Improvements As semiconductor process technologies continue to advance, routability and pin accessibility of standard cells have become major concerns while physical layouts of standard cells are being designed. Although analyticalbased methodologies have been proposed in the literature for rapid computations of cell routability andor pin accessibility scores, physical synthesis tools are still needed in the verification of cell routability andor pin accessibility since different physical synthesis tools can have very dissimilar Pu0026R (placement and routing) behaviors and capabilities. In this paper, therefore, we propose techniques adopted in a software system, which uses a physical synthesis tool, for measuring the routability of individual and abutted standard cells, so that cells which have routability andor pin accessibility issues for the tool can be detected. Moreover, the system is capable of generating cell spacing constraints for celledge pairs in order to improve routability of placed standard cell instances. Our system has been used in the detection of routability issues for many industrial standard cell libraries and for improving routability of placed designs. Experimental results show that DRC (design rule checking) violations in routed designs can be reduced after generated cell spacing constraints are applied.