FIR Feedback in Continuous Time Incremental SigmaDelta ADCs In this paper, we present a new method to include finiteimpulseresponse (FIR) feedback digitaltoanalog converters (DACs) in continuoustime (CT) Incremental SigmaDelta (Ixcexa3xcex94) analogtodigital converters (ADC), which minimizes transient overshoots and thereby maximizes the modulatoru0027s stability. More specifically, it can be shown that increasing the number of FIR taps in Ixcexa3xcex94 feedback DACs could lead to instability or a reduced maximum stable amplitude (MSA), even when using a proper compensation path. However, by presetting the FIR feedback to a voltage close to the input signal, a larger number of FIR taps can be used, increasing the jitter robustness of the CT Ixcexa3xcex94. This presetting is achieved using a low resolution Nyquist rate ADC to preset the FIR taps. Moreover, presetting the FIR feedback slightly increases the modulatoru0027s MSA and signaltonoise ratio compared to a nonreturntozero (NRZ) feedback. To validate the proposed presetting approach, a thirdorder Ixcexa3xcex94ADC employing a 12tap FIR DAC with presetting using a 4bit flash ADC is compared against a conventional NRZ DAC and a conventional FIR DAC without presetting in MATLABSimulink.

Continuous Time SigmaDelta Modulator with VCObased integrators and optimized NTF zeros This work presents the architectural concept and circuit simulation of a third order VCObased ContinuousTime SigmaDelta Modulator. The loop filter has a mixed mode resonator built with an RCOTA PI element and a VCObased integrator coupled through a resistor, which helps to optimize SNDR. The quantizer is built with a noise shaping digitally controlled oscillator. A linear model of the system is developed and used to optimize the architecture. The performance of this concept is limited by the linearity of the DCObased quantizer, which can be mitigated by using a set of parallel singlebit switched ring oscillators. As an example, a 60MHz bandwdith ADC is designed and simulated, showing more than 70dB of SNDR with 2GHz sampling clock.