Synthesizing Efficient Hardware from HighLevel Functional Hardware Description Languages Functional hardware description languages (FHDL) provide powerful tools for building new abstractions that enable sophisticated hardware system to be constructed by composing small reusable parts. Raising the level of abstractions in hardware designs means the programmer can focus on highlevel circuit structure rather than mundane lowlevel details. The language features that facilitate this include highorder functions, rich static type system with type inference, and parametric polymorphism. We use handwritten structural and behavioral VHDL, Simulink, and the Kansas Lava FHDL to reimplement several components taken from a Simulink model of an orthogonal frequencydivision multiplexing (OFDM) physical layer (PHY). Our development demonstrates that an FHDL can require fewer lines of code than traditional design languages without sacrificing performance.

HighLevel Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing Recent Intel FPGAs Intel have bypassable registers in the routing switches, permitting deeper pipelining and more flexible retiming. We investigate highlevel synthesis (HLS) approaches to leverage these interconnect registers. We alter LegUp, an academic HLS tool, to insert extra registers within the datapaths, and at the inputsoutputs of memory blocks. Initially, one or more registers are inserted after every computational and memory instruction to assess the maximum reachable frequency (Fmax). Subsequently, we apply a more judicious approach, profiling applications in software to gather statistics on the execution frequency of code segments. Guided by profiling, we insert additional pipeline registers in subcircuits corresponding to infrequently executed code segments. This permits F max improvements to be realized with modest impact to cycle latency.