From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI Ambipolar transistors have emerged recently and are presented on device and cell level. The ability to conduct both electrons and holes is often provided by the use of silicon nanowires, carbon nanotubes or similar gateallaround topologies. Large scale integration of these devices is difficult due to the complex manufacturing process. In this paper we present an ambipolar xe2x80x9cDehancement Mode Field Effect Transistor (DeFET)xe2x80x9d which is an electrostatically doped planar device. After introducing the device itself, we show its performance by analyzing it in the TCAD simulation of a digital inverter configuration. We present characteristics of our full output swing CMOSstyle inverter and compare it to an inverter which consists of MOSFETs from a similar 180 nm SOI technology. The bias for the electrostatic doping of the DeFETs is provided by the cell supply voltages, therefore no additional voltage has to be provided to reconfigure our ambipolar DeFET as ntype or ptype with performance similar to 180 nm SOI MOSFETs.

BodyBias Techniques in CMOS 22FDXxc2xae for MixedSignal Circuits and Systems 22FDXxc2xae, a 22nm CMOS fullydepleted silicon on insulator technology (FDSOI), provides both, a unique wideband bodybias tuning range, as well as reduced junction capacitances, enabling new circuit architectures across analog and mixedsignal platforms. With a threshold voltage sensitivity of around 70mV per Volt and a bodybias tuning range of xe2x88x922V, 22FDXxc2xae gives designers a competitive additional degree of freedom while incorporating transistor transit frequencies exceeding 400GHz. After briefly introducing 22FDXxc2xae, this paper provides an overview of the most recent FDSOI design techniques in the field of mixedsignal circuits utilizing static and or dynamic bodybiasing approaches. Given the strong threshold voltage tuning, bodybiasing allows e.g. to compensate process, voltage and temperature variations. This paper focuses on 22FDXxc2xae being a strong innovation catalyst in data converter architectures. First, a 5bit 18.5GSs flash ADC is presented, omitting the powerhungry resistive ladder by generating accurate thresholdvoltage offsets within the comparators. Then, the capability of dynamic bodybiasing is evaluated based on a 10GSs track and hold circuit (obtaining 49dBc SFDR at fs2) simultaneously improving both, a low onresistance and a high offresistance. Furthermore, a 28GHz ring oscillator utilizing a single, shared well for pMOS and nMOS devices is presented. Here, bodybiasing allows to fully compensate temperature effects. Finally, a bodybiasing controlled DAC linearization technique for SigmaDelta modulators, as well as a DAC driver termination impedance control for a 6GSs 10bit automotive Ethernet SSTDACDriver are presented.