Proposal of Scalable Vector Extension for Embedded RISCV SoftCore Processor Recently, the opportunity to use FPGA in the field of embedded computer system has increased. The cost for development of system using FPGA is quite high. Therefore, to easily develop the embedded system using FPGA, the development cost should be reduced, and it can be reduced by limiting the development of the dedicated circuit to the truly required part of the system and by using softcore processor. If the performance of the softcore processor improves, the development cost can be suppressed, since we can expect that the amount of the dedicated circuit can be reduced. Furthermore, even in the field of embedded system, the opportunity for data parallel processing such as image processing is increasing. We consider that it is important merit of softcore processor with SIMD extension that the computation performance can be optimized to the system by changing the number of parallel computing units according to the application. However, when optimizing the performance of softcore processor, it is an obstacle that the software for softcore processor needs to be changed every time we change the number of computing units. Thus, vector processing facility should provide the scalability that means the number of computing units can be changed without changing the program code. In this paper, we propose a scalable vector extension for RISCV ISA and its programming method.

An Open Source FPGAOptimized OutofOrder RISCV Soft Processor Highperformance soft processors in fieldprogrammable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An outoforder (OoO) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics. Hence, we propose the RSD processor: a new, opensource OoO RISCV soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a nonblocking cache. While the RSD supports such aggressive features, it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well. We first introduce the end result of the RSD microarchitecture design and then describe several novel optimization techniques. The RSD achieves up to 2.5times higher Dhrystone MIPS while using 60% fewer registers and 64% fewer lookup tables (LUTs) as compared to stateoftheart, opensource OoO processors.