A Implementation for Builtin SelfTesting of RapidIO by JTAG With the development of integrated circuit manufacturing process, the transmission rate of highspeed interface circuit is rapidly increasing. Highspeed interface develops from traditional digital circuit to mixedsignal circuit. The testing of mixedmode highspeed circuits in mass production is difficult, timeconsuming and costly. This paper realizes the testability design of builtin selftest(BIST) in a typical highspeed interface circuitRapidIO through JTAG, and completes the verification of internal loop and external loop tests both on simulation phase and product test phase. Comparing with the traditional method using core program to access RapidIO and testing the product with a bit error ratio tester, the design method in this paper has the advantage of operating simply and implementing easily. It completely saves the time of main PLLu0027s locking and the time of loading program from outside the chip. And the configuration time for RapidIO can be saved by onethirds. Whatu0027s more, the reliability of configuration through JTAG on ATE is more guaranteed than running function program. It has reduced test time and test cost effectively in the phase of mass production test.

Innovative BuiltIn SelfTest Schemes for OnChip Diagnosis, Compliant with the IEEE 1149.4 MixedSignal Test Bus Standard This paper presents a testing scheme for analog and mixedsignal circuitry compatible with the IEEE 1149.4 mixedsignal test bus standard. A highspeed dynamic current sensor is described, as well as an innovative selfdiagnostic method called VDDQ. The former is used to measure signature supply currents and to compare them with the footprint of a defectfree circuit. The latter senses the quiescent nodal voltages on several nodes of the circuit under test and compares them to their nominal values. A flag is raised if significant deviations are found. Simulation results are provided for the highspeed dynamic current sensor. Through simulations the VDDQ method has performed at one node test every half millisecond and has potential for much higher speed. It is faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defectfree IC to enter the market in significantly less time than with conventional testing methods.