Fractalbased gradient match and side match vector quantization for image coding In this paper, we propose the fractalbased gradient match vector quantizers (FGMVQs) and the fractalbased side match vector quantizers (FSMVQs) for the image coding framework. The proposed schemes are based upon the noniterative fractal block coding (FBC) technique and the concepts of the gradient match vector quantizers (GMVQs) and the side match vector quantizers (SMVQs). Unlike the ordinary GMVQs and SMVQs, the super codebooks in the proposed FGMVQs and FSMVQs are generated from the affinetransformed domain blocks in the noniterative FBC technique. The codewords in the state codebook are dynamically extracted from the super codebook with the sidematch and gradientmatch criteria. The redundancy in affinetransformed domain blocks is greatly reduced and the compression ratio can be significantly increased. Our simulation results show that about 10%  20% bit rates in the noniterative FBC techniques are saved by using the proposed FGMVQs and FSMVQs.

VHDL design for hardware assistance of fractal image compression Fractal image compression has several useful properties, including resolution independence, high compression ratios, rapid decoding, and subjectively good image quality. Despite this, its adoption has been limited, largely because of the very high computational burden of compression. In this paper, an original ASIC design is described which performs the comparisons required for fractal image compression of grayscale images. The design is based around a pipeline of many individual block comparison units through which the set of domain blocks are propagated. Each unit performs the required comparisons between a single range block and the series of domain blocks, and stores the best possible match. The ASIC is designed using synthesizable VHDL, allowing it to be targeted to virtually any digital technology. The small portions of the design which are specific to a particular application or technology, such as the bus interfaces and memory blocks, have been kept separate from the applicationindependent portions of the design. Simulations of the design suggests that an actual hardware implementation would be about one thousand times faster than a general purpose microprocessor based on similar IC technology, reducing the time required to optimally compress a 256 x 256 image using 8 xc3x97 8 range blocks from a few minutes to a fraction of a second.