Efficient OS Hardware Accelerators Preemption Management in FPGA The management of reconfiguration in FPGAs constitutes a hot topic in a lot of domains. In such devices, a reconfigurable fabric is generally combined with a processor to guarantee high computing performance with a limited amount of hardware resources. Most of these devices generally feature an operating system (OS) that interacts with hardware Intellectual Property (IP) resources. Software tasks (managed by the OS) may then access hardware resources concurrently and dedicated mechanisms have to be provided to manage resource sharing efficiently. The problem is even bigger if hardware resources are localized in a reconfigurable area. In this paper, we deal with the problem of sharing hardware resources in a reconfigurable device. We propose a preemption mechanism for hardware resources that may reduce the reconfiguration time overhead to be compatible with the timing constraints of most embedded applications.

Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration Partial reconfiguration supports virtualisation of applications on FPGAs, enabling compute to dynamically adapt to workloads in distributed infrastructure and datecenters. While the latter often makes use of the PCIe interface and supporting infrastructure to allocate and load compute kernels via a host CPU, FPGAs are becoming increasingly popular as standalone resources in edgecomputing, requiring them to manage accelerators autonomously. This paper presents a platform that supports the managing of accelerator bitstreams over the network interface on a Xilinx Zynq device without intervention by the Arm processor. We compare against traditional vendor provided PR management for both library accelerators and custom accelerators and show that we achieve a 29% decrease in reconfiguration trigger latency using this approach.