Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder Nonbinary lowdensityparitycheck (NBLDPC) code outperforms their binary counterpart in terms of errorcorrecting performance and errorfloor property when the code length is moderate. However, the drawback of NBLDPC decoders is high complexity and the complexity increases considerably when increasing the Galoisfield order. In this paper, a simplified basicset trellis minmax (sBSTMM) algorithm that is especially efficient for highorder Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NBLDPC code over GF(32). The implementation results using 90nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar errorcorrecting performance, compared to the uptodate works.

RedundancyAided Iterative ReliabilityBased MajorityLogic Decoding for NBLDPC Codes Nonbinary lowdensity paritycheck (NBLDPC) codes tend to exhibit much better performance than their binary counterparts while suffering from very high computational complexity. As a type of harddecision NBLDPC decoding algorithm, the iterative reliabilitybased majoritylogic decoding (IRBMLGD) algorithms are attractive for their low computation complexity, coming with obvious performance degradation. Aiming at improving the errorcorrection performance, in this paper, we introduce few redundant bits to the original NBLDPC encoding and the corresponding checksum operations to the improved iterative soft reliabilitybased (IISRB)MLGD. Based on the joint coding and decoding method, the obtained redundancyaided (RA)IISRB decoding algorithm shows significant performance improvement while maintaining the lowcomplexity property. Simulation results demonstrate that the proposed algorithm can achieve a more than 1.0dB extra coding gain over the original IISRB with a slight decrease of code rate.