Parallel Global Placement on CPU via Parallel Reduction Quick design is attracting considerable interests as the IC design scale increases. In this paper, we propose a generic parallel global placement strategy on CPU for the acceleration of VLSI placement. Analytical placement methods with nonlinear wirelength model achieve highquality placements while involve numerous arithmetic computations. We decompose the essential operations including objective function and its gradients evaluation into subtasks and parallelize them using thread pool. Parallel reduction is introduced to avoid resource contention and thus further improves parallel efficiency. The combination of the two techniques leads to a significant speedup with respectable scalability. Experimental results demonstrate that the proposed algorithm can achieve 24xc3x97 speedup on 32 CPU cores without significant wirelength degradation.

FBM: A Simple and Fast Algorithm for Placement Legalization In VLSI physical design, the legalization step has to deal with thousands of logic cells that need to provide a placement solution with all cells aligned within the rows and overlapfree, while preserving the global placement solution, i.e., displacement should minimize. We present an algorithm for VLSI placement legalization that minimizes the impact of wirelength in highdensity circuits. Our approach is based first on sorting the cells according to their positions and legalizing each pair of overlapping cells. The algorithm moves the second overlap cell to the right until it finds a legalized placement with the lowest movement. Our experimental results show that our algorithm can reduce the runtime with a minimum impact on wirelength when compared to another legalization tool.