A Resource Consumption and Performance Overhead Optimized Reduction Circuit on FPGAs Many scientific and engineering applications involve massive vector operations (such as dot product and matrix multiplication) which can be calculated efficiently by using reduction circuit. However, the low performance and large resource consumption of the reduction circuit limit the ability of the system. In this paper, an optimized reduction circuit with high performance and low resource consumption is proposed, which can handle multiple sets of arbitrary size without pipeline stalling. A new reduction scheduling algorithm is proposed, which consumes fewer cycles and buffer size compared with other methods. Moreover, in order to achieve a high clock frequency, the reduction circuit implements novel status and buffer management modules. The proposed design using a deeply pipelined doubleprecision floatingpoint adder as reduction operator is implemented on FPGAs, which achieves at least 1.59 times improvement on areatime product compared with the reported methods.

SkyCastle: A ResourceAware MultiLoop Scheduler for HighLevel Synthesis A common optimisation problem in the highlevel synthesis (HLS) of FPGAbased accelerators is to find a microarchitecture that maximises the performance while keeping the utilisation of the deviceu0027s lowlevel resources below certain limits. We propose to tackle it directly as part of the HLS scheduler. To that end, we formalise a general, integrated scheduling and allocation problem for HLS kernels, and present SkyCastle, a novel resourceaware multiloop scheduler using integer linear programming to solve it for a subclass of kernels composed of multiple, nested loops. In order to demonstrate the practical applicability of the approach, we model the scheduler in such a way as to be plugin compatible with the Xilinx Vivado HLS engine, allowing the computed solutions to be fed back into its synthesis flow. We evaluate SkyCastle for three nontrivial kernels from the machine learning, signal processing, and physical simulation domains, on two FPGA devices. Additionally, we investigate the replication of slightly slower, but smaller accelerators as a means to further boost the overall performance. In contrast to Vivado HLSu0027 default settings, which aim at maximum performance but may fail in later synthesis steps, the solutions computed by our scheduler always result in synthesisable designs.