A Lowdelay Configurable Register for FPGA A lowdelay configurable register for FPGA is designed in this paper. This design is based on the basic masterslave D flipflop, uses transmission gates on key nodes to control the register into four modes: register mode, latch mode, synchronous overwrite mode and asynchronous overwrite mode, then inputs desired signals to complete the functions of registers, latches, global initialization, synchronous reset, asynchronous reset, capture and writeback. The control signals and the D input are separated so that control circuit will not affect the registeru0027s timing parameters. A presimulation is carried out under the 28nm process and the results show that the configurable registeru0027s various functions are correct. The timing parameters are equivalent to the nonconfigurable masterslave D flipflops, which proves that the control circuit does not affect the timing parameters. In this paper, configurable register has a 41ps delay of CK to Q, a 7ps setup time and a 0ps hold time.

OnChip Delay Measurement for InField Test of FPGAs Avoidance of delayrelated failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aginginduced delay increase. This paper proposes a delay measurement method using BIST (BuiltIn SelfTest) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BISTbased delay measurement, and correction of the measured delay with reflecting temperature variance in field. In onchip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper.