Digital Low Power Mode Control Technique for HighFrequency Synchronous DCDC Buck Converters This paper presents a low power mode control technique for digitally controlled synchronous buck converters optimized for the heavy load regulation. The proposed control mode achieves compact area and low complexity thanks to an efficient logic partitioning and reuse of the digital controller. The inductor peak current is controlled with a predictive algorithm that does not require current sensing. A prototype of a digitally controlled synchronous 5xe2x80x940.9 V, 1.5 A buck DCDC converter that embeds the low power control technique is implemented. A custom IC in a 28nm CMOS process has been designed for the digital controller and the gate drivers. Experimental results indicate that the high efficiency range is extended, obtaining an efficiency improvement up to 43% at light load.

Variable offTime Peak Current Mode Control (VoTPCMC) as method for average current regulation in Buck Converter Drivers In automotive industry, every electronic device is driven by power switches. Indeed, the energy source is the car battery and it cannot, for instance, limit the output maximum voltage level. Consequently it could be higher than that supported by the load. The DCDC Buck converter acts by limiting the output variables, according with the load specifications thereby ensuring its correct operation. The overall circuit will be composed of a power stage, the basic DCDC converter, and a control loop, to provide a target output current value. This paper presents a control algorithm derived from an improved Peak Current Mode Control. The proposed algorithm defined Variable offTime Peak Current Mode Control (VoTPCMC) allows to contemporarily control in a DCDC converter the ripple and the average current values, leading to a reliable load driver. The algorithm operation is simulated and then tested on hardware using dSpace, a Rapid Control Prototyping setup.