SORN Arithmetic for MIMO Symbol Detection  Exploration of the Type2 Unum Format In this paper a new approach for a fast and lowprecision number format is explored. The SORN representation uses a fixed set of exact values and open intervals in between to represent real numbers on the digital layer. With SORN arithmetic operations can be carried out using simple lookup tables which results in a very fast and lowcomplex way of computing. The new arithmetic is applied to an exhaustive search algorithm for maximum likelihood symbol detection in a MIMO transmission environment. The algorithm is implemented in hardware and executed on a Zynq7000 FPGA. It is shown that the amount of possible solutions for the symbol detection can be reduced by up to 80% using the fast SORN architecture as a preprocessing stage for classic solvers.

Polar Decoding Hardware Implementation This paper presents hardware implementations of two principle polar decoding algorithms: Successive Cancellation Decoding (SCD) and Successive Cancellation List Decoding (SCL). The proposed designs are compliant with 3GPP specifications in terms of block length and frozenset mapping. Moreover, this generic architecture allows block length  N  and rate  R  to be configured onthefly. The implementations significantly improved decoding throughput with hardware optimization, especially with the SCD, thanks to parallelblock decoding technique. Additionally, the SCL with a list size  Lgeq 8  considerably outperforms the BitErrorRate (BER), as well as the FrameErrorRate (FER) curve compared to SCD. The paper provides a comparison of the two algorithms, especially the tradeoff between performance and complexity. The results of implementations and testing are carried out on FPGA platform and compared with StateOfTheArt (SOTA).