Collaborative Implementation of HardwareOriented GBDT Compress Algorithm Based on DSPFPGA GBDT (Gradient Boosting Decision Tree) is an algorithm that builds multiple decision trees by iteratively updating. Due to its strong generalization ability and fast operation speed, it is widely used in the realization of classification and regression. However, the GBDT classification model occupies large storage resources; its application on the mobile multimedia platform is greatly limited. To solve this problem, we come up with a new GBDT compression algorithm for hardware implementation 1. And based on this algorithm, we designed a DSPFPGA system to achieve four classifications of sixdimensional samples. DSP is responsible for classification control, while the FPGA implements the classification calculation process. This classification system not only occupies small hardware resources but also guarantee accuracy and speed.

FPGAAccelerated Decision Tree Classifier for RealTime Supervision of Bluetooth SoC Wireless communication protocols are used in all smart devices and systems. This work proposes an FPGAaccelerated supervisory system that classifies the operation of a communication systemonchip (SoC). In this work, the selected communication protocol is Bluetooth (BT). The input supply current to the transceiver block of the SoC is monitored and sampled at 50 kHz. We extract simple descriptive features from the transceiver input power signal and use them to train a machine learning (ML) model to classify two different BT operation modes. We implemented ADC sampling, feature extraction, and a realtime decision tree classifier on an Intel MAX 10 FPGA. The measured classification accuracy is 97.4%.