A Fast and Secure Pipelined Barrel Processor for SafetyCritical Applications for RealTime Operating Systems Security, reliability, and efficiency are crucial traits of the microprocessors used for safety and mission critical applications. Conventional microprocessors are typically not suitable for these applications, mainly because these processors do not support architecturallevel protection including thread isolation, which in turn could lead to security vulnerabilities in embedded systems. In this case, a single erroneous thread could cause catastrophic failure of the whole system. Also, with conventional microprocessors, no specific defense mechanisms are provided to prevent foreign invaders such as viruses from attacking the system. This could become a significant problem especially for safety and mission critical applications that are typically realtime systems. In this paper, we introduce novel and unique pipeline barrel processor (PBP) architecture for safety and mission critical applications for realtime operating systems. Our PBP microprocessor is designed in such a way to alleviate the aforementioned issues, by comprising following features: finegrained multitasking using single pipeline assembly, dynamic allocation of CPU cycles, memory partitioning at the architectural level, execution code regions at the hardware level, and global variables and stack protections. Experiments are performed to evaluate our PBP microprocessor, and to verify the correctness and functionality of the microprocessor design.

Recruiting Fault Tolerance Techniques for Microprocessor Security The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging microarchitectural side channels such as due to speculative execution to implementing cryptographic accelerators for sidechannel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of u0027security faultsu0027 (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive sidechannels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the repurposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active sidechannel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic subcomponent of a RISCV based secure systemonchip, against a formidable fault attack called SIFA.