VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash Lowdensity paritycheck (LDPC) codes have been widely adopted in NAND flash in recent years to improve data reliability. However, their errorcorrection capability degrades due to inaccurate loglikelihood ratio (LLR). To improve LLR accuracy of LDPC decoding, this paper proposes a threshold voltage distribution aware LLR optimization scheme, called VaLLR. Firstly, we build a threshold voltage distribution model for 3D triplelevel cell (TLC) NAND flash. Then, by exploiting the model, we introduce the VaLLR scheme to quantize LLR during softdecision decoding. And by amplifying a portion of small LLRs, which is essential in the layer minsum decoder, more precise LLR can be obtained. Finally, we study the influence of the reference voltage arrangement on LLR calculation and apply the VaLLR scheme during decoding. The simulation shows that the proposed approach can improve the FER performance for several orders of magnitude.

Read Threshold Calibration for NonVolatile Flash Memories The introduction of multi level cell (MLC) and triple level cell (TLC) technologies reduced the reliability of flash memories significantly compared with single level cell (SLC) flash. The reliability of the flash memory suffers from various errors causes. Programerase cycles, read disturb, and cell to cell interference impact the threshold voltages. With predefined fixed read thresholds a voltage shift increases the bit error rate (BER). This work proposes a read threshold calibration method that aims on minimizing the BER by adapting the read voltages. The adaptation of the read thresholds is based on the number of errors observed in the codeword protecting a small amount of metadata. Simulations based on flash measurements demonstrate that this method can significantly reduce the BER of TLC memories.