SPASSD: Exploit Heterogeneity and Parallelism of 3D SLCTLC Hybrid SSD to Improve Write Performance To address the write performance problem suffered by MLCTLC flash, researchers have proposed hybrid SSD that aims to combine the strengths of SLC flash, used as the writebuffer zone for its superior write performance, and MLCTLC flash, as the capacity zone for its high storage density. While leveraging SLC as a physical writebuffer zone is proven effective in traditional 2D hybrid SSDs, how to effectively incorporate SLC into a 3Dstacked TLC to form a hybrid SSD has not been studied to the best of our knowledge. Yet this is a timely and important performance issue for 3Dstacked TLC given its oneshot programming scheme that results in much worse write performance than the programming scheme in 2D TLC where pages are associated with different bits of a cell and programmed in sequence separately. We believe that naively adopting the twophysicalzone approach to 3D hybrid SSD will miss a great opportunity for performance optimization because it ignores the inherent fourlevel parallelism (channelchipdieplane) of the flash chip array. To this end, we propose in this paper an SLC and Parallelism Aware hybrid SSD (SPASSD) to take full advantages of SLCu0027s superior write performance, the internal multilevel parallelism of SSD, and the high storage density of 3Dstacked TLC flash. Two novel techniques enable SPASSD to be highly effective: (1) TypeParallelism Joint Page Allocation (TPJPA), which allocates pages for write transactions according to not only available SLC pages but also parallelism to maximize resource utilization within the hybrid SSD, and (2) Queuelength and Parallelism Constrained Data Migration (QPCDM), which triggers data migration without degrading user write performance by analyzing the device queue length and available flash resources. To evaluate performance of SPASSD, a hybrid SSD simulator, called HybridSim, is developed based on MQSim. Experimental results on HybridSim show that TPJPA improves write throughput by 60%, while QPCDM improves write throughput by up to 10 times. Besides, tracedriven experiments on HybridSSD demonstrate that SPASSD improves the write latency to the flash by up to two orders of magnitude over the stateoftheart designs.

Hybrid Storage System to Achieve Efficient Use of Fast Memory Area Hybrid storage techniques are useful methods to improve the cost performance for inputoutput (IO) intensive workloads. These techniques choose areas of concentrated IO accesses and migrate them to an upper tier to extract as much performance as possible through greater use of upper tier areas. Automated tiered storage with fast memory and slow flash storage (ATSMF) is a hybrid storage system situated between nonvolatile memories (NVMs) and solidstate drives (SSDs). ATSMF aims to reduce the average response time for IO accesses by migrating areas of concentrated IO access from an SSD to an NVM. When a concentrated IO access finishes, the system migrates these areas from the NVM back to the SSD. Unfortunately, the published ATSMF implementation temporarily consumes much NVM capacity upon migrating concentrated IO access areas to NVM, because its algorithm executes NVM migration with high priority. As a result, it often delays evicting areas in which IO concentrations have ended to the SSD. Therefore, to reduce the consumption of NVM while maintaining the average response time, we developed new techniques for making ATSMF more practical. The first is a queue handling technique based on the number of IO accesses for NVM migration and eviction. The second is an eviction method that selects only writeaccessed partial regions in finished areas. The third is a technique for variable eviction timing to balance the NVM consumption and average response time. Experimental results indicate that the average response times of the proposed ATSMF are almost the same as those of the published ATSMF, while the NVM consumption is drastically lower.