DecisionTree Based Pixel Classification for Realtime Citrus Segmentation on FPGA According to Food and Agriculture Organization, Mexico is one of the top five citrus producers in the world. In order to achieve the required quality control to export their products, citrus producers require sorting machines able to classify millions of fruits according to certain characteristics, as their size and color. Computer vision provides image processing tools, as image segmentation, that could be used as first stage in a classification process. Fruit classification must be fast in order to be able to process as much fruits per second as possible. In this paper, an FPGA architecture for image segmentation of orange images based on decisiontree models is proposed. A decisiontree model is proposed as an alternative to global thresholding and adaptive thresholding algorithms. It was observed that in this scenario, global thresholding fails due to the noise produced by the fast moving fruits in a classification line, and adaptive thresholding algorithms are not suitable for realtime applications, because of their high requirements in computing power and memory. A decisiontree model requires less hardware compared to both algorithms. The proposed model can achieve realtime segmentation because it is based on pixel serialization, and not on pixel neighborhood processing. The proposed architecture was implemented in a Spartan6 FPGA. It runs at 60 fps and attains an accuracy of 97.1% of correct segmented pixels, compared to an offline manual segmentation of the frames.

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA Implementation of fast semantic segmentation in an embedded system is necessary due to the increasing interest in automatic driving and energyefficiency is a fundamental metric in such a scenario. Because highresolution images are required to achieve high segmentation accuracy, its accelerator must prepare large buffers for the corresponding feature maps, and it is not suitable for the limited onchip memory of an FPGA. To address this, we propose a tile segmentation algorithm and develop an FPGAbased accelerator for a sparse MobileNetbased PSPNet. To reduce the buffer size, the tile segmentation algorithm splits incoming images into the numbers determined by the stride on an FPGA. The PSPNet then performs many split tiles. Moreover, we propose a pipelined sparse convolutional circuit to compute multiple tiles with highspeed. We compared the proposed FPGAbased system with the NVIDIA RTX 2080 Ti using the Cityscapes benchmark. The FPGA achieved 139 FPS with 24 W power consumption for a 1024xc3x97512 image, and its accuracy (mIoU) was 64.2%. Compared with the GPU, it was 1.5 times faster, its power consumption was 9.3 times lower, and its performance per power consumption was 13.8 times better.