Latency Minimal Scheduling with Maximum Instruction Parallelism High Level Synthesis (HLS) is to synthesize circuits from algorithmic level descriptions. There is a strong need to deploy HLS in high performance computing for data center and edge computing. In this paper, we propose a new scheduling algorithm based on an instructionlevel Dependency Graph (DG) for latency minimization. Unlike existing scheduling algorithms assuming a sequential execution order of Basic Blocks (BBs), we can identify instruction parallelism across BBs and schedule them parallelly for smaller circuit latency. Our test results show that we can significantly improve the circuit latency when compared with the stateoftheart SDCbased LegUp and even outperform PandA with sophisticated code motion heuristics by 8% on average.

Isomorphic Subgraphbased Problem Reduction for Resource Minimal Modulo Scheduling Modulo scheduling is a powerful method to increase throughput in highlevel synthesis for digital hardware design. When facing large designs, optimal approaches are likely to time out and heuristics fail to provide satisfying throughput and latency. We propose an isomorphic subgraphbased reduction of the input dataflow graph (DFG) that is applied before scheduling, in order to solve the modulo scheduling problem faster without changing the optimal initiation interval (II) and allocated hardware. Our results show a solving time speedup of 5xc3x97 on average and up to 102xc3x97 for large designs. Using the proposed preprocessing step, the II achieved could be reduced by 33% on average for SDCbased modulo schedulers. And in ILPbased scheduling, we could classify 15% more solutions as optimal within the same time compared to solutions provided without applying our transformation.