qCG: A LowPower MultiDomain SFQ Logic Design and Verification Framework In this paper, we propose qCG, a multidomain design and verification framework, which utilizes clock gating and frequency scaling to optimize dynamic power dissipation. SFQ circuits are ultradeep pipelined at the logic level, resulting in large clock distribution networks which account for a considerable part of overall power dissipation. We have shown that qCG significantly increases power efficiency, not only for SFQ circuits, but also their clock networks and inherently cooling systems. The verification engine of qCG learns to increase the quality of results in terms of verification time and coverage. Datapath and coverage meters are embedded to verify the pulse integrity of clock signals, SFQ fanout, and pathbalancing properties. Our experiments on several SFQ benchmark circuits show that qCG provides 3X power reductions for the chip. Results also confirm that when compared to a traditional randombased coveragedriven approach, qCG provides significant verification quality improvement including 2.33X verification speedup.

PowerGating Models for Rapid Design Exploration Power gating (PG) is an effective method to reduce leakage currents in an SoC design during runtime. It dynamically shuts down components using a network of sleep transistors but requires a detailed analysis to scale this network appropriately with respect to area wakeup time inrush currents voltage drops and transition energies. In this paper we present a method to efficiently determine these key parameters for any SoC design and sleep transistor network at gatelevel to enable the rapid exploration of power design alternatives while providing sufficient accuracy for highlevel design exploration. Compared to SPICE our approach achieves a speedup of up to 11457x for two ISCAS circuits a 32bit multiplier and a RISCV core each build for a 90nm PDK. The average error compared to SPICE is 2.6% for peak current and 10% for wakeup energy and delay.