A Buffer and Splitter Insertion Framework for Adiabatic QuantumFluxParametron Superconducting Circuits Adiabatic QuantumFluxParametron (AQFP) logic is an adiabatic superconductor logic that has been proposed as alternative to CMOS logic with extremely high energy efficiency. In AQFP technology, gates are driven by ACpower, which also serves as clock signal to synchronize the outputs of all gates in the same clock phase. As a matter of fact, AQFP circuits may require huge amount of buffers and splitters to be inserted to allow inputs to any gate having equal delay. Existing buffer and splitter insertion method does not deliver optimization, which could lead to huge space and delay overhead. A better automated buffer and splitter framework is imminent for more efficient AQFP circuits design. In this paper, we propose an automated buffer and splitter insertion method that is capable of adding optimized amount of buffers and splitters to any given gatelevel netlist to achieve equal delay for all gates. The proposed method achieve equal delay by inserting buffers and splitters with any library limitation on the size of splitters. Experimental results suggest that the proposed method can deliver better results compared with the existing method, with upto 40.84% less in size and 3.13% less in delay when splitter fanout size is limited to four.

qCG: A LowPower MultiDomain SFQ Logic Design and Verification Framework In this paper, we propose qCG, a multidomain design and verification framework, which utilizes clock gating and frequency scaling to optimize dynamic power dissipation. SFQ circuits are ultradeep pipelined at the logic level, resulting in large clock distribution networks which account for a considerable part of overall power dissipation. We have shown that qCG significantly increases power efficiency, not only for SFQ circuits, but also their clock networks and inherently cooling systems. The verification engine of qCG learns to increase the quality of results in terms of verification time and coverage. Datapath and coverage meters are embedded to verify the pulse integrity of clock signals, SFQ fanout, and pathbalancing properties. Our experiments on several SFQ benchmark circuits show that qCG provides 3X power reductions for the chip. Results also confirm that when compared to a traditional randombased coveragedriven approach, qCG provides significant verification quality improvement including 2.33X verification speedup.