A Design Framework for Hardware Approximation of Deep Neural Networks For realtime edge AI applications, there is a need to implement deep neural networks (DNNs) in hardware for high speed. The tradeoff between computing accuracy and hardware cost must be made during the implementation of hardware approximation. In this paper, we propose a design framework for DNN hardware approximation. The proposed framework provides a behavior model library of approximate logic circuits (e.g., approximate multipliers) for the designers to utilize them. Moreover, the proposed framework also supports the dynamic fixedpoint arithmetic for hardware simulation. To save the required total bit width, we develop an integer length tuning method in the framework to maximize the computing accuracy under a constraint on the total bit width. Experimental results on ICNet show that the proposed framework can achieve high computing accuracy with small hardware cost.

Enabling EnergyEfficient and Reliable Neural Network via NeuronLevel Voltage Scaling As the application scope of deep neural networks (DNNs) moves from largescale data centers to smallscale mobile devices, power wall has become one of the most important obstacles. Voltage scaling is a typical technique enables power saving, but it causes reliability and performance challenges. Therefore, an energyefficient and reliable scheme for NNs is required to balance above three aspects according to usersu0027 requirements for excellent user experience. In this paper, we innovatively propose neuronlevel voltage scaling framework called NNAPP to model the impact of supply voltages on NNs from output accuracy (A), power (P), and performance (P) perspectives. We analyze the error propagation in NNs and precisely model the impact of voltage scaling on the final output accuracy at neuronlevel. Multiobjective optimization and clustering method are combined to find the optimal voltage islands. Finally, we conduct experiment to demonstrate the efficacy of the proposed technique.