INTSDN: Evaluation of various P4 parameters using optical telemetry having reconfigurable data plane on 40 Gbps line rate Ethernet packet communication is the old established protocol of data transfer in networks. Ethernet devices transmit the data from a source to a receiver while the receiver has no statistics regarding the transmission channel. In this era of global transmission where the upcoming communication technology will be equipped with self optimized transmission under which there will be minimum errors. The need to gather information related to the transmission path arises. The primary objective of this research paper is to evaluate the different P4 parameters on optical media. P4 enabled NICxe2x80x99s, corresponding FPGA Images and traditional Ethernet switches were used for the results. INT SDN P4 packets were transmitted and the comprehensive test traces were captured and examined. DPDK was used which provides the foundation for P4 packet forwarding. Data, as well as the control plane were fully configurable in the hardware setup which resulted in speedier data transmission and also enhanced the packet efficiency at higher data rates. Metrics such as latency, throughput, data rates and efficiency were accumulated, compared and analyzed on P4 based optical network having a 40 Gbps data transmission rate. Moreover, the inside story of the optical channel was gathered which will provide further insights related to the P4 transmission medium.

A highperformance framework for a network programmable packet processor using P4 and FPGA Abstract   The emergence of new network technologies and usersu0027 everincreasing demand necessitates the introduction of highly programmable hardware with high flexibility and performance at the network data plane. The switches at the data plane need to be flexible enough to support protocols and test new ideas for increasing the abstraction of network programming. In most studies, Field Programmable Gate Arrays (FPGA) are applied in making switches flexible and reprogrammable; however, applying FPGAs alone does not meet the required flexibility. Next to applying FPGAs, it is necessary to provide an architecture that would allow developers to forego FPGA implementation hardware details and the complexity of hardware description language (HDL). In this paper, a new architecture of a programmable packet processor with high flexibility and programmability at the network data plane is presented, which supports all three operations required in switches: parsing, classification, and processing of packet data. To implement this architecture, the highlevel P4 language is applied to allow the description of its registertransfer level (RTL) on the FPGA. In order to increase the processing speed, a pipeline approach within the proposed architecture is designed at the SDN data plane through preprocessing in the parse graph, identifying the traffic flow, and applying the hybrid control flow model in the data processing. The results show that our architecture operates at 320xe2x80xafMHz clock speed, which in comparison with NetFPGA10G, NetFPGASUME, and ML605 peer architectures runs 2, 1.28, and 2.9 times faster in terms of processing speed, attesting to its efficiency. In addition, the evaluation on the Virtex7 FPGA VC709 platform shows that our architecture consumes approximately 4.3% of lookup tables, 1.9% of flipflops, and 1.3% of memory blocks, which are less than the hardware resource consumption of peer architectures.