Does the ISA Really Matter? A Simulation Based Investigation Prior studies on the performance and energy impacts of ISAs are normally based on the measurements of real hardware platforms. However, the extremely diverse hardware implementations make the comparisons among different platforms difficult and indirect, not mention the difficulties of the analyses of microarchitectural metrics. In this paper, we conduct an investigation of ARM, RISCV and X86 ISAs based on the gem5 cycleaccurate simulations, in which the target implementations of these ISAs are simulated with the same three hardware configurations, namely the InOrder, OutofOrder1 and OutofOrder2. Fifteen benchmarks chosen from SPEC2006 and BEEBS are used to conduct the simulations. Meanwhile, the power and energy consumption of the target implementations is evaluated by McPAT. Our simulation results suggest that although ARM ISA outperforms RISCV and X86 ISAs in performance and energy consumption, the differences between ARM and RISCV are very subtle, while the performance gaps between ARM and X86 are possibly caused by the relatively low hardware configurations used in this paper and could be narrowed or even reversed by more aggressive hardware approaches. Our study confirms that one ISA is not fundamentally more efficient.

An Open Source FPGAOptimized OutofOrder RISCV Soft Processor Highperformance soft processors in fieldprogrammable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An outoforder (OoO) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics. Hence, we propose the RSD processor: a new, opensource OoO RISCV soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a nonblocking cache. While the RSD supports such aggressive features, it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well. We first introduce the end result of the RSD microarchitecture design and then describe several novel optimization techniques. The RSD achieves up to 2.5times higher Dhrystone MIPS while using 60% fewer registers and 64% fewer lookup tables (LUTs) as compared to stateoftheart, opensource OoO processors.