PostModel Validation of Victim DRAM Caches Formal modeling and analysis of a victim DRAM cache has already been discussed in the existing literature. These works use interacting state machines to model states and transitions of a victim DRAM cache. In this work, we address modelcode conformance between a formal model of the victim DRAM cache and a simulator obtained from it. Our work focuses on a twostep approach to validate a DRAM cache implementation. In the first step, we use a technique based on it FeedbackDirected Random Testing to reverse engineer the state models from the execution traces. This process helps us to match the implementation with the state machines associated with the formal model and to verify some of the statebased properties. In the second step, we instrument the implementation with monitors and validate the liveness and safety properties (during runtime) which have been proved earlier in the formal model.

To Update or Not To Update?: BandwidthEfficient Intelligent Replacement Policies for DRAM Caches This paper investigates intelligent replacement policies for improving the hitrate of gigascale DRAM caches. Cache replacement policies are commonly used to improve the hitrate of onchip caches. The most effective replacement policies often require the cache to track and update perline reuse state to inform their decision. A fundamental challenge on DRAM caches, however, is that stateful policies would require significant bandwidth to maintain perline DRAM cache state. As such, DRAM cache replacement policies have primarily been stateless policies, such as alwaysinstall or probabilistic bypass. Unfortunately, we find that stateless policies are often too coarsegrain and become ineffective at the size and associativity of DRAM caches. Ideally, we want a replacement policy that can obtain the hitrate benefits of stateful replacement policies, but keep the bandwidthefficiency of stateless policies. We perform our study on a DRAM cache design similar to the one in Knights Landing, and find that tracking perline reuse state can enable an effective replacement policy that can mitigate the common thrashing patterns seen in gigascale caches. We propose a stateful replacementbypass policy called RRIP AgeOnBypass (RRIPAOB), that tracks reuse state for highreuse lines, protects such lines by bypassing other lines, and Ages the state On cache Bypass. Unfortunately, such a stateful technique requires significant bandwidth to update state. To this end, we propose Efficient Tracking of Reuse (ETR). ETR makes state tracking efficient by accurately tracking the state of only one line from a region, and using the state of that line to guide the replacement decisions for other lines in that region. ETR reduces the bandwidth for tracking replacement state by 70%, and makes stateful policies practical for DRAM caches. Our evaluations with a 2GB DRAM cache, show that our RRIPAOB and ETR techniques provide 18% speedup while needing u003c1KB SRAM.