A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double AutoZeroing Technique For a complementary metaloxidesemiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The inpixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in singleslope analogtodigital converter topology for a complementary metaloxidesemiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double autozeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double autozeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.

An Automatic SlopeCalibrated Ramp Generator for SingleSlope ADCs This paper presents a ramp generator with automatic slope calibration which is able to compensate slope deviation due to process and environmental effects. A novel analog feedback circuit is proposed to regulate the stop voltage in successive approximation while fix the start voltage of the ramp automatically without much calibration code input or complicated auxiliary circuits, which reduces the complexity of circuitry and timing, meanwhile, saves area and power. A 12bit singleslope ADC (SSADC), employing the proposed ramp generator, has been implemented in a 0.11xc2xb5m CMOS process. The simulation results show that the offset of the rampu0027s stop voltage is reduced to 0.1 LSB and the nonlinearity of the ramp is 0.034%. Besides, the measurement results verify that this structure can fulfill automatic slope calibration.