FPGAbased Implementation of HOG Algorithm: Techniques and Challenges Histogram of Oriented Gradients (HOG) is a method for extracting features from an image, which has many applications in Computer Vision. Due to the complexity and high amount of computations of this algorithm, softwarebased implementations of HOG cannot meet the realtime criterion. Therefore, many researchers have implemented HOG algorithm on hardware platforms such as FPGAs. This paper presents an extensive review of FPGAbased implementations of the HOG algorithm, that have been published from 2010 to 2019. Different techniques for hardware implementation of HOG are classified into three groups: methods which improve a certain stage of the algorithm, methods which optimize the whole algorithm, and methods which make minor simplification on the algorithm. In this paper, these three classes of techniques are reviewed. Finally, the speed and resource utilization of the surveyed papers are compared to each other in order to present a comprehensive conclusion on FPGAbased HOG implementation.

An FPGAbased Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points RANSAC algorithm is a powerful algorithm which is widely used to reject erroneous data in the field of automated image analysis and computer vision. In RANSAC, its iterative property leads to higher computation complexity. Therefore, the hardware implementations of RANSAC that have been proposed consume a large amount of resources. In this paper, an FPGAbased resourceefficient RANSAC hardware accelerator is proposed to eliminate false matches of feature points between two adjacent image frames. The proposed design adopts a singleline systolic array structure causing its lower onchip resource consumption. It can work along with image feature points detection and matching modules on FPGA. The proposed design is evaluated on a ZYNQ XC7Z045 FPGA at 100MHz clock frequency. Processing 128 matching pairs, only needs 4,718 clock cycles. Experimental results demonstrate that its outstanding capability for screening matching pairs, our design can support realtime video processing.