A LowPower 10bit 160MSamples DAC in 40nm CMOS for Baseband Wireless Transmitter A lowpower 10bit 160MSamples digital to analog converter (DAC) for baseband wireless transmitter is proposed and demonstrated. The design considerations of architecture and floorplan have been discussed, aiming to minimize power consumption without degradation of static linearity and spurious free dynamic range (SFDR). An optimized layout reduces parasitic and mismatch effects. The simulation result shows that the SFDR is more than 70 dB (67 dB) for input signals up to 8.75 MHz (70 MHz) and the power consumption is 0.43 mW with a 1.1 V power supply. The proposed DAC has been verified in 40nm CMOS and has an active area of 0.036 mm2.

A 0.8 V LowPower 3rd order SigmaDelta Modulator in 22 nm FDSOI CMOS Process for Sensor Interfaces We present the design of a lowpower 3rd order sigmadelta (xcexa3xcex94) modulator targeted for sensor applications. The circuit is implemented in the 22 nm Fully Depleted Silicon on Insulator (FDSOI) CMOS process technology from GlobalFoundries. The modulator features a singleloop feedforward architecture. Lowvoltage operation of the fullydifferential switchedcapacitor based modulator is achieved with enhanced bootstrapped switches for highly linear sampling., and operational transconductance amplifiers (OTAs) operating in weak inversion. The onchip area of the modulator is 0.193 mm2. The measurement results show that operating over a signal bandwidth of 500 Hz at a nominal supply voltage of 0.8 V and a sampling rate of 512 kHz., the modulator achieves a peak signaltonoiseanddistortion ratio (SNDR) of 89 dB and a dynamic range of 94 dB. The total average power consumption of the designed modulator, including that of the auxiliary circuits, is 170 xc2xb5W.