SCFlip Decoding of Polar Codes with High Order Error Correction Based on Error Dependency The successive cancellation flip (SCFlip) decoding algorithm arose as a valid lowcomplexity decoding algorithm for polar codes, however its decoding capabilities are still far away from list based decoders. In this paper, we propose an improved SCFlip multiple error decoding framework based on error dependency, and specialize it for the twoerror correction case. We propose to generate different lists of second error locations based on the index of the expected first errors. The inherent flexibility of this approach allows it to be modified for a desired tradeoff between performance and complexity. Two second errors list construction approaches are presented, and are shown to yield gains over the original SCFlip decoder at the same decoding complexity.

RateFlexible Fast Polar Decoders Polar codes have gained extensive attention during the past few years and recently they have been selected for the next generation of wireless communications standards (5G). Successivecancellationbased (SCbased) decoders, such as SC list (SCL) and SC flip (SCF), provide a reasonable error performance for polar codes at the cost of low decoding speed. Fast SCbased decoders, such as FastSSC, FastSSCL, and FastSSCF, identify the special constituent codes in a polar code graph offline, produce a list of operations, store the list in memory, and feed the list to the decoder to decode the constituent codes in order efficiently, thus increasing the decoding speed. However, the list of operations is dependent on the code rate and as the rate changes, a new list is produced, making fast SCbased decoders not rateflexible. In this paper, we propose a completely rateflexible fast SCbased decoder by creating the list of operations directly in hardware, with low implementation complexity. We further propose a hardware architecture implementing the proposed method and show that the area occupation of the rateflexible fast SCbased decoder in this paper is only 38% of the total area of the memorybased baseline decoder when 5G code rates are supported.