Generating Reduced Tests for FSMs using a SearchBased Testing Approach Ideally, in FSMbased testing, a test suite should have as few input symbols and sequences as possible, speeding up its execution, and being able to reveal as many faulty implementations as possible in a given fault domain. Unfortunately, in general, it is an NPhard problem. Several test generation methods have been proposed to generate a test suite with full fault detection capability. However, they usually generate large test suites with many sequences. In this paper, we propose a searchbased software testing method aiming to generate test suites that represent a good tradeoff between its cost and its fault coverage. A new encoding, called Nodedepthoutdegree Encoding (NDOE) and its mutation and initialization operators are proposed. Also, a new fitness function is presented. The proposed fitness is composed of three objectives: minimize the test suite length, minimize the number of test sequences, and maximize the fault coverage, which analysis is based on mutation score. The experimental results show that the proposed method is able to generate lower cost test suites, with high mutation score, than literature test generation methods.

ReinforcementLearningBased Test Program Generation for SoftwareBased SelfTest Softwarebased Selftest (SBST) has been recognized as a promising complement to scanbased structural Builtin Selftest (BIST), especially for infield selftest applications. In response to the everincreasing complexities of the modern CPU designs, machine learning algorithms have been proposed to extract processor behavior from simulation data and help constrain ATPG to generate functionallycompatible patterns. However, these simulationbased approaches in general suffer sample inefficiency, i.e., only a small portion of the simulation traces are relevant to fault detection. Inspired by the recent advances in reinforcement learning (RL), we propose an RLbased test program generation technique for transition delay fault (TDF) detection. During the training process, knowledge learned from the simulation data is employed to tune the simulation policy; this closeloop approach significantly improves data efficiency, compared to previous openloop approaches. Furthermore, RL is capable of dealing with delayed responses, which is common when executing processor instructions. Using the trained RL model, instruction sequences that bring the processor to the faultsensitizing states, i.e., TDF test patterns, can be generated. The proposed test program generation technique is applied to a MIPS32 processor. For TDF, the fault coverage is 94.94%, which is just 2.57% less than the fullscan based approach.