Adaptive Masking: a Dynamic Tradeoff between Energy Consumption and Hardware Security As the Internet of Things (IoT) devices process and communicate an increasing amount of sensitive data, the confidentiality of these data is a growing concern. Hardware sidechannel attacks pose a threat against the physical implementation of encryption, which is commonly used to ensure this confidentiality. Traditional hardware countermeasures against such sidechannel attacks, like masking, usually introduce a high energy overhead. However, IoT devices are typically resourceconstrained and have a small energy budget. Furthermore, the energy or security constraints may vary between devices or over time, depending on, e.g., the remaining battery level or data sensitivity. Therefore, a dynamic tradeoff has to be found between security, power consumption and performance. In this paper, we introduce a new paradigm whereby hardware masking is applied on demand to increase the energy efficiency. We illustrate this concept by applying it to the stream cipher Trivium. We demonstrate that compared to a reference masked implementation, this solution ensures a high level of security when necessary while significantly reducing the power consumption (by up to 76.2%) the rest of the time, with a small area overhead (13.5%) and no impact on the performance.

Crypto Accelerators for PowerEfficient and RealTime onChip Implementation of Secure Algorithms The demand for data exchange is ever growing. Internet of Things (IoT), industry 4.0, smart city and nextgeneration interconnected vehicles are some examples of scenarios in which a high volume of nodes share data across networks. Hence, the data protection plays a fundamental aspect to avoid disclosure or manipulation of sensitive information and disruption of services, particularly in safety critical applications. On the other hand, also the compute power at disposal of possible attackers and hackers is growing, and nextfuture postquantum capabilities will require the usage of longer keys, certificates and digital signatures, to preserve the security level offered by cryptographic functions. This will affect not only the amount of exchange data, but also the computational resources to secure data, increasing processing time, latencies and power consumption, and lowering data rates. In this work, we investigate different implementation strategies to overcome such performance limitations. This work provides a comparison among pure software approach (both on 32b and 64b processors) and hardwarebased solutions we developed for FPGA and ASIC SystemonChip platforms, for the most common symmetrickey and publickey cryptographic algorithms. The proposed hardware accelerators feature one order of magnitude higher throughput (and lower latency) and more than two orders lower power consumption than their software counterparts. A highly configurable cryptographic suite is proposed that can be customized according to the application requirements and thus able to increase as much as possible the efficiency in terms of energy per enciphered bits per second.