ReNEW: Enhancing Lifetime for ReRAM Crossbar Based Neural Network Accelerators With analog current accumulation feature, resistive memory (ReRAM) crossbars are widely studied to accelerate neural network applications. The ReRAM crossbar based accelerators have many advantages over conventional CMOSbased accelerators, such as high performance and energy efficiency. However, due to the limited cell endurance, these accelerators suffer from short programming cycles when weights that stored in ReRAM cells are frequently updated during the neural network training phase. In this paper, by exploiting the wearing out mechanism of ReRAM cell, we propose a novel comprehensive framework, ReNEW, to enhance the lifetime of the ReRAM crossbar based accelerators, particularly for neural network training. Evaluation results show that, our proposed schemes reduce the total effective writes to ReRAM crossbar based accelerators by up to 500.3x, 50.0x, 2.83x and 1.60x over two MLC ReRAM crossbar baselines, one SLC ReRAM crossbar baseline and an SLC ReRAM crossbar design with optimal timing, respectively.

A LowPower HighThroughput InMemory CMOSReRAM Accelerator for LargeScale Deep Residual Neural Networks We present an inmemory accelerator circuit design for ResNet50, a largescale residual neural network with 49 convolutional layers, 2.6 xc3x97 107 parameters and 4.1 xc3x97 109 f1oatingpoint operations (FLOPS). A 4bit quantized ResNet50 is first chosen among various bitwidths for the best tradeoff. It is then trained and fully mapped onto a 4608 xc3x97 512 ReRAM crossbar, yielding a storage reduction from 195.2Mb to 24.3Mb and an 88.1% top5 accuracy on ImageNet, only 2.5% lower than the fullprecision original. Two versatile CMOS 4bit DAC and ADC are designed for input and readout, allowing the proposed CMOSReRAM accelerator to achieve up to 15.2xc3x97 runtime speedup and 498xc3x97 higher energy efficiency versus the stateoftheart CMOSASIC implementation.