A Method to Design 5Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in Memories Space applications face severe challenges from soft errors caused by cosmic rays. Soft errors can change the storage state of memories used in electronic system, leading to system failure. To avoid the system corruption, error correction codes (ECCs) as the general mitigation strategy in system level are utilized to eliminate the soft error influence. As the feature size goes down, more memory cells are integrated in the energy deposited range of radiation particles and MBU becomes the main error patterns. In this paper, we propose a new method to design 5bit burst error correction code against more complex burst error. To achieve that, a technique to design a code with unequal correction ability and a customized interleaving plan combined with the proposed code is presented. The experiment result implies that this method is efficient for MBUs mitigation and a potential option for system designers.

Radiation Hardened Design of Pipeline and Register File in Processor With the development of aerospace technology and integrated circuit (IC) technology, the processor, as the core component of the spacecraft electronic device, is highly susceptible to the space highenergy particle radiation that can generate single event upset (SEU), Therefore, it is of great significance for the research of processor radiation hardened design. Considering the processoru0027s speed, area and power overhead and the final hardened performance, based on the OR1200 processor platform, this paper proposes a technique to protect most signals by using the interleaved parity codes combined with the pipeline restart and partial signals by using the Triple Modular Redundancy (TMR) for the pipeline in processor. As multiple bits upsets (MBU) have become an serious issue for memory reliability, this paper also protects the register file in processer by using error correction codes with four adjacent errors correction and refreshing the register file with an exception trigger. Finally, both proposed techniques are verified and evaluated effectively. The result indicates that the SEU in pipeline and the MBU in register file can be effectively mitigated.