Harmonic Distortion Optimization for SigmaDelta Modulators Interface Circuit of TMR Sensors The tunneling magnetoresistance microsensors (TMR) developed by magnetic multilayer material has many advantages, such as high sensitivity, high frequency response, and good reliability. It is widely used in military and civil fields. This work presents a highperformance interface circuit for TMR sensors. Because of the nonlinearity of signal conversion between sensitive structure and interface circuit in feedback loop and forward path, large harmonic distortion occurs in output signal spectrum, which greatly leads to the reduction of SNDR (signal noise distortion rate). In this paper, we analyzed the main source of harmonic distortion in closedloop detection circuit and establish an accurate harmonic distortion model in TMR microsensors system. Some factors are considered, including nonlinear gain of operational amplifier unit, effective gain bandwidth, conversion speed, nonlinearity of analog transmission gate, and nonlinearity of polycrystalline capacitance in highorder sigmadelta system. We optimized the CMOS switch and firststage integrator in the switchedcapacitor circuit. The harmonic distortion parameter is optimally designed in the TMR sensors system, aiming at the mismatch of misalignment of frontend system, nonlinearity of quantizer, nonlinearity of capacitor, and nonlinearity of analog switch. The digital output is attained by the interface circuit based on a lownoise frontend interface circuit and a thirdorder sigmadelta modulator. The digital interface circuit is implemented by 0.35xcexbcm CMOS (complementary metal oxide semiconductor) technology. The highperformance digital TMR sensors system is implemented by double chip integration and the active interface circuit area is about 3.2 xc3x97 2 mm. The TMR sensors system consumes 20 mW at a single 5 V supply voltage. The TMR sensors system can achieve a linearity of 0.3% at full scale range (xc2xb1105 nT) and a resolution of 0.25 nTHz12(1Hz).

A 0.8 V LowPower 3rd order SigmaDelta Modulator in 22 nm FDSOI CMOS Process for Sensor Interfaces We present the design of a lowpower 3rd order sigmadelta (xcexa3xcex94) modulator targeted for sensor applications. The circuit is implemented in the 22 nm Fully Depleted Silicon on Insulator (FDSOI) CMOS process technology from GlobalFoundries. The modulator features a singleloop feedforward architecture. Lowvoltage operation of the fullydifferential switchedcapacitor based modulator is achieved with enhanced bootstrapped switches for highly linear sampling., and operational transconductance amplifiers (OTAs) operating in weak inversion. The onchip area of the modulator is 0.193 mm2. The measurement results show that operating over a signal bandwidth of 500 Hz at a nominal supply voltage of 0.8 V and a sampling rate of 512 kHz., the modulator achieves a peak signaltonoiseanddistortion ratio (SNDR) of 89 dB and a dynamic range of 94 dB. The total average power consumption of the designed modulator, including that of the auxiliary circuits, is 170 xc2xb5W.