CSMNN: Current Source Model Based Logic Circuit Simulation  A Neural Network Approach The miniaturization of transistors down to 5nm and beyond, plus the increasing complexity of integrated circuits, significantly aggravate short channel effects, and demand analysis and optimization of more design corners and modes. Simulators need to model output variables related to circuit timing, power, noise, etc., which exhibit nonlinear behavior. The existing simulation and signoff tools, based on a combination of closedform expressions and lookup tables are either inaccurate or slow, when dealing with circuits with more than billions of transistors. In this work, we present CSMNN, a scalable simulation framework with optimized neural network structures and processing algorithms. CSMNN is aimed at optimizing the simulation time by accounting for the latency of the required memory query and computation, given the underlying CPU and GPU parallel processing capabilities. Experimental results show that CSMNN reduces the simulation time by up to 6xc3x97 compared to a stateoftheart current source model based simulator running on a CPU. This speedup improves by up to 15xc3x97 when running on a GPU. CSMNN also provides high accuracy levels, with less than 2% error, compared to HSPICE.

DNNLibGen: Deep Neural Network Based Fast Library Generator We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is nonlinear, nonmonotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving timetomarket goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required signoff corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a xe2x80x98single modelxe2x80x99 to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed librarygenerator uses a novel intercorner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intracorner model, to generate dense 8x8 delay tables using delays from 10 slewload points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization runtime for early milestones by upto 60%.