Buffer Sizing for NearThreshold Clock Tree using Improved Genetic Algorithm Comparing with superthreshold designs, clock tree design in nearthreshold voltage (NTV) region is more susceptive to signal slew, and timing violations occur much more often due to slew degradation at sink nodes and difference among sink nodes. However, when optimizing clock tree in superthreshold region, signal slew is merely considered as transition constraint with an upper bound. Little concern is taken about slew at sink nodes, which is particularly important in NTV region and system performance would be badly weakened if it is not controlled properly. Here, we propose an innovative formulation for optimization of buffer size in nearthreshold clock tree using improved genetic algorithm combined with nonlinear programming. With slew at sink nodes considered, we are able to minimize a combination of skew, slew and area cost. On average, skew is improved by 23.8%, and max slew at sink nodes and slew difference among sink nodes are reduced by 24.6% and 47.8% separately. At the same time, area cost of buffer is also reduced by 8.5%. The optimal solution can set as buffer sizes directly without any subsequent discretization procedure.

A Statistical Timing Model for CMOS Inverter in Nearthreshold Region Considering Input Transition Time The increasing performance variation poses remarkable challenges to timing analysis for circuits operating in nearthreshold voltage (NTV) region in spite of attractive energy efficiency advantage. Few researches were devoted to the statistical timing model for NTV design especially when input transition time was considered. In this paper, a statistical timing model for CMOS inverter is proposed in NTV region under process variation considering fast and slow input, which is derived analytically with a novel segmented step approximation method to overcome the integral issue of drain current equation for ramp input. The mean and variance of inverter delay distribution are derived as a function of the supply voltage, inverter size, load capacitance, and input transition time with the statistical characteristics of process variation. Experimental results under 40nm process show that the proposed inverter delay model is highly fitted with Monte Carlo (MC) simulation results at the supply voltage of 0.4V, where the mean and variance error are less than 5.35% and 8.36% for fast input and 10.89% and 13.07% for slow input respectively.