HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools With the dramatic increase in utilization of FPGAs for hardware designs in various application domains, CAD tools play a vital role in the development and implementation of FPGAbased designs. Although CAD tools are typically designed to optimize FPGAbased designs to enhance certain performance metrics during the synthesistoimplementation process, in this work, we illustrate that CAD tools are susceptible to HDL coding style; thus, minor difference in HDL constructscodes, lead to significantly different final hardware implementations, which in turn impacts the areaefficiency and speedperformance. By utilizing simple hardware circuitry, we analyze and demonstrate the impact of code optimizations, i.e., how the code optimizations (i.e., varying HDL constructscodes) impact the way the FPGAbased CAD tools, and their associated algorithmstechniques, interpret and implement the final hardware circuitry on the FPGA. Our experimental results and analysis ascertain that by performing minor modifications to the HDL constructscodes (with minor code optimizations), we can significantly enhance certain performance metrics of the corresponding hardware implementations in terms of areaefficiency and speedperformance, without changing the underlying hardware circuitry.

HighLevel Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing Recent Intel FPGAs Intel have bypassable registers in the routing switches, permitting deeper pipelining and more flexible retiming. We investigate highlevel synthesis (HLS) approaches to leverage these interconnect registers. We alter LegUp, an academic HLS tool, to insert extra registers within the datapaths, and at the inputsoutputs of memory blocks. Initially, one or more registers are inserted after every computational and memory instruction to assess the maximum reachable frequency (Fmax). Subsequently, we apply a more judicious approach, profiling applications in software to gather statistics on the execution frequency of code segments. Guided by profiling, we insert additional pipeline registers in subcircuits corresponding to infrequently executed code segments. This permits F max improvements to be realized with modest impact to cycle latency.