GroundTruth Prediction to Accelerate SoftError Impact Analysis for Iterative Methods Understanding the impact of soft errors on applications can be expensive. Often, it requires an extensive error injection campaign involving numerous runs of the full application in the presence of errors. In this paper, we present a novel approach to arriving at the ground truththe true impact of an error on the final outputfor iterative methods by observing a small number of iterations to learn deviations between normal and errorimpacted execution. We develop a machine learning based predictor for three iterative methods to generate groundtruth results without running them to completion for every error injected. We demonstrate that this approach achieves greater accuracy than alternative prediction strategies, including three existing soft error detection strategies. We demonstrate the effectiveness of the ground truth prediction model in evaluating vulnerability and the effectiveness of soft error detection strategies in the context of iterative methods.

Improving Softwarebased Techniques for Soft Error Mitigation in OoO Superscalar Processors Highperformance superscalar processors have been developed to satisfy the growing demand for processing modern applications. However, as the transistor size shrinks, the increase in vulnerability to soft errors poses a great challenge, since these effects have been proven to also affect groundlevel safetycritical applications. Considering that vulnerability strategies may span across different layers of the system stack, we propose a mixed SWHWbased designtime methodology aiming to achieve the best tradeoff between vulnerability and areaenergy for superscalar processors. By injecting over 10 million faults in 12 significant microarchitectural structures to different versions of the complex BOOM OoO superscalar processor modeled with RTL accuracy, we show that SWbased protection techniques always reach an upper bound that may not be satisfactory. Then, we propose to insert extra lowlevel HWbased DMR protection at strategic microarchitectural points by reducing this task to the Knapsack Problem. In one of the evaluated cases, we optimally find the best structures to be protected with 55% area overhead to achieve a 95% vulnerability improvement for a quadissue processor.