CompilerBased HighLevel Synthesis of ApplicationSpecific Processors on FPGAs In order to meet tight performance andor energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example FieldProgrammable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern HighLevel Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Softcore processors implemented with FPGAlogic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a generalpurpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compilerbased synthesis methodology that generates networks of ApplicationSpecific Instruction Set Processors (ASIPs) from unmodified CC algorithms. We thereby bridge the gap between traditional softcore processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compilerbased approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)fixed commercial Xilinx MicroBlaze softcores.

HighLevel Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing Recent Intel FPGAs Intel have bypassable registers in the routing switches, permitting deeper pipelining and more flexible retiming. We investigate highlevel synthesis (HLS) approaches to leverage these interconnect registers. We alter LegUp, an academic HLS tool, to insert extra registers within the datapaths, and at the inputsoutputs of memory blocks. Initially, one or more registers are inserted after every computational and memory instruction to assess the maximum reachable frequency (Fmax). Subsequently, we apply a more judicious approach, profiling applications in software to gather statistics on the execution frequency of code segments. Guided by profiling, we insert additional pipeline registers in subcircuits corresponding to infrequently executed code segments. This permits F max improvements to be realized with modest impact to cycle latency.