RateFlexible Fast Polar Decoders Polar codes have gained extensive attention during the past few years and recently they have been selected for the next generation of wireless communications standards (5G). Successivecancellationbased (SCbased) decoders, such as SC list (SCL) and SC flip (SCF), provide a reasonable error performance for polar codes at the cost of low decoding speed. Fast SCbased decoders, such as FastSSC, FastSSCL, and FastSSCF, identify the special constituent codes in a polar code graph offline, produce a list of operations, store the list in memory, and feed the list to the decoder to decode the constituent codes in order efficiently, thus increasing the decoding speed. However, the list of operations is dependent on the code rate and as the rate changes, a new list is produced, making fast SCbased decoders not rateflexible. In this paper, we propose a completely rateflexible fast SCbased decoder by creating the list of operations directly in hardware, with low implementation complexity. We further propose a hardware architecture implementing the proposed method and show that the area occupation of the rateflexible fast SCbased decoder in this paper is only 38% of the total area of the memorybased baseline decoder when 5G code rates are supported.

Fast Simplified MultiBit SuccessiveCancellation List Decoding of Polar Codes and Implementation Information, signal amplitude and phase change drastically in broadband multimedia communications and broadcasting. Channel coding is a key technology to ensure reliable information transmission in broadband mobile multimedia communication system. Polar codes are the first channel codes that can be proved to achieve channel capacity. In this paper, we propose a fast simplified multibit successive cancellation list (FastSMSCL) decoding method for polar codes. In our proposed FastSMSCL decoding, we take fully use of consecutive information bits and achieve prominent latency reduction of 3% to 58% compared to the existing simplified multibit successive cancellation list decoding. In addition, we also propose an architecture of FastSMSCL decoder, especially path memory unit and partial sum network. Finally, we implement the decoder on FPGA which achieves high throughput of 125Mbps.