Design of High Throughput FPGABased Testbed for Accelerating Error Characterization of LDPC Codes We present a modular FPGAbased testbed to accelerate the study of lowdensity paritycheck codes (LDPC). This testbed is composed of controller, codeword generator, noise generator, random number generator, LDPC decoder, and statistical analysis modules. The LDPC decoder module is replaceable to enable development or study of new or existing harddecisionbased decoders. We demonstrate our testbedu0027s ability to reduce the timescale of error correction and error pattern analysis through case studies involving the Gallager B (GaB) and Probabilistic Gallager B (PGaB) algorithms. We contextualize the throughput and execution time performance of our framework, running on a Xilinx Zynq XC7Z020 FPGA, with reference CPU (Intel Xeon) and GPGPU (Tesla K40) implementations of the PGaB algorithm. While the single threaded CPUbased testbed and the reference GPU testbed achieve throughputs of 219 Kbs and 3608 Kbs respectively, the FPGAbased testbed achieves 9172 Mbs. This corresponds to reducing the time scale of error correction analysis on PGaB, at previously untested error resolutions, to less than a day from an estimated 199 years on a single general purpose processor and 12 years on the GPU. We finally demonstrate the utility of our testbed by completing the first simulation on identifying all possible codewords with four errors that are not correctable by GaB. We reduce the time scale of this simulation, which requires processing 117 billion codewords, to 4.5 hours from an estimated 488 days on the GPU and 7803 days on CPU. Our opensource, modular and parameterized testbed allows researchers rapidly evaluate error correction performance of the target decoder algorithm and collect statistical data essential to exploring algorithmic improvement opportunities.

The Probabilistic Finite Alphabet Iterative Decoder for LowDensity ParityCheck Codes We propose in this paper a new approach of applying the NonSurjective Finite Alphabet Iterative Decoder (NSFAID) for the LowDensity ParityCheck (LDPC) decoding. Differently from the NSFAID which applies a fixed nonlinear function by using a fixed LookUpTable (LUT) on the variable node messages, the proposed method, called Probabilistic FAID (PFAID), uses more than one LUT in a probabilistic way. By using the density evolution, we show that this method provides a significant improvement in performance compared to the NSFAID and the traditional MS. The advantage of PFAID is shown by the fact that, a PFAID with low message quantization level can reach or even surpass the performance of the higher level quantization MS decoder. Furthermore, we show that PFAID can be efficiently implemented with no hardware overhead compared to MinSum (MS) or NSFAID with the same message quantization level. The hardware complexity analysis and decoding simulation performance are provided as superiority evidences of PFAID over the referenced benchmarks.