WiXI: An InterChip Wireless Bus Interface for ShapeChangeable ChipletBased Computers Herein, we propose a wireless bus interface that can connect multiple chips to form a flexible system. In the proposed bus interface, onchip coils are formed along the outer periphery of each chip, and highspeed wireless communication between multiple chips is enabled via horizontal inductive coupling between coils. Using the proposed interface, embedded computer systems can be realized by simply combining small chips with different functions as needed and arranging them in an adjacent manner. The proposed bus interface enables variation in the relative angle between adjacent chips during operation, can be implemented in complicated shapes, and facilitates chip replacement post fabrication to achieve flexible and robust computer systems; such systems can be applied in microrobots and wearable interfaces. In this paper, we present a theoretical analysis of electromagnetic coupling between coils, electromagnetic field simulation results, and circuit simulation results of transmitter and receiver circuits. Through the simulation conducted using 45 nm CMOS technology, we realized highspeed communication of 14.3 Gbs with a power efficiency of 0.55 pJb using the proposed bus interface. We also verified the data collision detection ability of the proposed bus interface using a collision detection circuit and packet transfer based on a SerDes circuit.

Data Conversion in AreaConstrained Applications: the Wireless NetworkonChip Case NetworkonChip (NoC) is currently the paradigm of choice to interconnect the different components of SystemonChips (SoCs) or Chip Multiprocessors (CMPs). As the levels of integration continue to grow, however, current NoCs face significant scalability limitations and have prompted research in novel interconnect technologies. Among these, wireless intrachip communications have been under intense scrutiny due to their low latency broadcast and architectural flexibility. Thus far, the practicality of the idea has been studied from the RF frontend and the network interface perspectives, whereas little to no attention has been placed on another essential component: the data converters. This article aims to fill this gap by providing a comprehensive analysis of the requirements of the scenario, as well as of the current performance and cost trends of AnalogtoDigital Converters (ADCs). Based on Murmannxe2x80x99s data, we demonstrate that ADCs will not be a roadblock for the realization of wireless intrachip communications although current designs do not meet their demands fully.