A 20GSs TrackandHold Amplifier based on InP DHBT Process Based on f T u003e210GHz InP DHBT process, a highspeed fully differential TrackandHold amplifier (THA) with 10GH 3dB bandwidth was realized on a 1.9xc3x972.3mm2 chip. Operating from a 6 V power supply, the TrackandHold amplifier using switchedemitterfollower has a 840mW total power consumption. Spectral measurements exhibit 31dBc of total harmonic distortion (THD) and give a SFDR of 31.2dBc when sampling a singleended input signal of 8GHz at a sampling rate of 20GSs. Time domain measurements show the waveform of the THA sampling at 20GSs with 8GHz singleended input sinusoidal signal. The TrackandHold amplifier capable of 20GSs presented in this paper is suitable for use with a analogue to digital converter of 6bit resolution. In this paper, the present InP THA demonstrates the fabricating superiority of InP DHBT process in term of bandwidth, highspeed sampling and linearity.

An UWB 18.5 GSs Sampling FrontEnd for a 74 GSs 5bit ADC in 22nm FDSOI This paper presents the design of an ultrawideband buffered frontend sampler (Tu0026H) operating at 18.5 GSs. The linear sampler, intended for a 5bit 4x timeinterleaved (TI) flash ADC, is realized in a 22 nm FDSOI (FDX) CMOS process. It comprises an ultralow jitter limiting clock path and a PMOSNMOS source follower Tu0026H maximizing the linearity and isolation as well as enhancing the effective sampling bandwidth. The frontend takes advantage of the flippedwell forwardbiasing process option lowing the transistor threshold voltage by 75 mVV to achieve a differential input range of 600 mV pp,diff  while using a dual 1.2 V and 0.9 V supply voltage. The frontend exhibits asampling bandwidth of more than 40 GHz across corners (worst case SS, T  120xc2xb0C), achieving a SFDR and SNDR of better than 41 dBc and 38 dB respectively at the fourth Nyquist zone (fin  37GHz). The total power consumption is only 75mW of which 10 mW is consumed by the entire clock path.