A Memetic Algorithm Based PVT VariationAware Robust Transistor Sizing Scheme for PowerDelay Optimal Digital Standard Cell Design Higher yield, climbing transistor counts and shrinking dimensions of a single Integrated Circuit (IC) have always been the demands in the fabrication market. However, this increased complexity and miniaturization of transistors present a challenge, due to high critical process variations combined with a ubiquitous presence of temperature and supply voltage variations, to achieve the required specification bounds on the desired performance of the circuits. Since optimization has become a very crucial task in IC design, the paper presents an efficient transistor sizing based optimization technique of the CMOS circuits to achieve low power, high performance and high yield design goals. The proposed memetic algorithm judiciously utilizes a threshold based local search procedure to improve convergence in its inherent genetic nature. The algorithm optimizes with the effect of temperature 55 to 125xc2xb0C and supply voltage xc2xb110% variations and in addition a number of statistically sampled sets generated as Gaussian, Latin Hypercube and Correlation Screened schemes of process variations. The proposed technique is applicable to any technology node and has been tested over several standard singlestage and some complex multistage digital circuits designed using a MultiGate highK dielectric (MGK) 22nm CMOS model. The reduction in leakage power with propagation delay goes as high as 53% with 9% respectively, as observed across the various digital circuits.

Buffer Sizing for NearThreshold Clock Tree using Improved Genetic Algorithm Comparing with superthreshold designs, clock tree design in nearthreshold voltage (NTV) region is more susceptive to signal slew, and timing violations occur much more often due to slew degradation at sink nodes and difference among sink nodes. However, when optimizing clock tree in superthreshold region, signal slew is merely considered as transition constraint with an upper bound. Little concern is taken about slew at sink nodes, which is particularly important in NTV region and system performance would be badly weakened if it is not controlled properly. Here, we propose an innovative formulation for optimization of buffer size in nearthreshold clock tree using improved genetic algorithm combined with nonlinear programming. With slew at sink nodes considered, we are able to minimize a combination of skew, slew and area cost. On average, skew is improved by 23.8%, and max slew at sink nodes and slew difference among sink nodes are reduced by 24.6% and 47.8% separately. At the same time, area cost of buffer is also reduced by 8.5%. The optimal solution can set as buffer sizes directly without any subsequent discretization procedure.