Seiba: An FPGA OverlayBased Approach to Rapid Application Development Although highlevel synthesis (HLS) improves designer productivity through abstraction, FPGA highlevel synthesis stills suffers from lengthy compilation that limits the number of design iterations a developer can achieve per day. One method of minimizing these compile times is compiling designs with innate programmability, aka FPGA overlays, and using their runtime configuration to implement functional changes, as opposed to recompiling the design. In this paper, we introduce Seiba, an application development approach that integrates HLS circuits with FPGA overlays to create reconfigurable platforms that are rapidly configured to reduce development time. As a duallayer compilation approach, Seiba enables users to choose an appropriate tradeoff between productivity and overhead by implementing incremental changes quickly through overlay configuration or efficiently through FPGA recompilation. To handle this integration, our approach uses a novel overlay architecture that offers flexible overlay configuration which can xe2x80x9cpatchxe2x80x9d and redirect execution from an application circuit to runtime configurable overlay functional units. Our results show that by leveraging the overlayu0027s runtime configurability, our development flow can significantly reduce the number of FPGA compilations in a development cycle.

Automatic Generation of ApplicationSpecific FPGA Overlays with RapidWright Overlay architectures implemented on FPGA devices have been proposed as a means to increase FPGA adoption in generalpurpose computing. They provide the benefits of software such as flexibility and programmability, thus making it easier to build dedicated compilers. However, existing overlays are generic, resource and power hungry with performance usually an order of magnitude lower than bare metal implementations. As a result, FPGA overlays have been confined to research and some niche applications. In this paper, we introduce ApplicationSpecific FPGA Overlays (ASOverlays), which can provide baremetal performance to FPGA overlays, thus opening doors for broader adoption. Our approach is based on the automatic extraction of hardware kernels from data flow applications. Extracted kernels are then leveraged for applicationspecific generation of hardware accelerators. Reconfiguration of the overlay is done with RapidWright which allows to bypass the HDL design flow. Through prototyping, we demonstrated the viability and relevance of our approach. Experiments show a productivity improvement up to 20x compared to the state of the art FPGA overlays, while achieving over 1.33x higher Fmax than direct FPGA implementation and the possibility of lower resource and power consumption compared to bare metal.