Gate Stack Optimization Toward DisturbFree Operation of Ferroelectric HSO based FeFET for NAND Applications The utilization of FeFET technology in NAND based architectures is dependent on the role of pass voltage disturb of pass cells during the readout of selected cells. This disturb effect becomes dependent on the FeFET stack parameters and potential optimization for a disturb free operation. In this paper, the impact of pass voltage on the disturb properties of a standard 10 nm Sidoped hafnium oxide (HSO) based FeFETs in a twin gate NAND string is reported. This shows a rather low margin between the pass voltage and strong disturb of pass cells and suggests FeFET stack optimization. A laminate HSO based FE stack (2 xc3x97 10nm) with an optimized interface layer (IL) is proposed in benchmark to the standard one to achieve a higher pass window for disturb free operation of the NAND cells. textAsim 2textx pass window is obtained on the laminated FeFET stack compared to the standard one without jeopardizing the optimal write conditions of the FeFET. The pass voltage disturb properties of unselected NAND cells is reported with emphasis on the potential of an optimized laminate based stack to reduce the pass disturb effect.

Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model Negative capacitance FET (NCFET) is one of the most promising steepsubthreshold slope (SS) transistors. Thanks to the discovery of ferroelectric HfO 2  (FEHfO 2 ), NCFET has been getting more attentions as a highly manufacturable solution. Since the proposal of NCFET and discovery of FEHfO2, there have been many experimental demonstrations of steep SS with NCFET. However, the physical mechanism of steep SS has not been fully understood yet, and confident explanations have not been given to these experimental results. In this paper, we report our recent progress of theoretical and experimental studies toward comprehensive understanding of NCFET regarding steep SS behavior, reverse DIBL and negative differential resistance (NDR). Transient NC theory that we explore is able to consistently explain some class of previously reported experimental results. This paper will help to guide further NCFET research activities.