An FPGAbased Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points RANSAC algorithm is a powerful algorithm which is widely used to reject erroneous data in the field of automated image analysis and computer vision. In RANSAC, its iterative property leads to higher computation complexity. Therefore, the hardware implementations of RANSAC that have been proposed consume a large amount of resources. In this paper, an FPGAbased resourceefficient RANSAC hardware accelerator is proposed to eliminate false matches of feature points between two adjacent image frames. The proposed design adopts a singleline systolic array structure causing its lower onchip resource consumption. It can work along with image feature points detection and matching modules on FPGA. The proposed design is evaluated on a ZYNQ XC7Z045 FPGA at 100MHz clock frequency. Processing 128 matching pairs, only needs 4,718 clock cycles. Experimental results demonstrate that its outstanding capability for screening matching pairs, our design can support realtime video processing.

TwoDimensional SystolicArray Architecture for PixelLevel Vision Tasks This paper presents ongoing work on the design of a twodimensional (2D) systolic array for image processing. This component is designed to operate on a multiprocessor systemonchip. In contrast with other 2D systolicarray architectures and many other hardware accelerators, we investigate the applicability of executing multiple tasks in a timeinterleaved fashion on the Systolic Array (SA). This leads to a lower external memory bandwidth and better load balancing of the tasks on the different processing tiles. To enable the interleaving of tasks, we add a shadowstate register for fast task switching. To reduce the number of accesses to the external memory, we propose to share the communication assist between consecutive tasks. A preliminary, nonfunctional version of the SA has been synthesized for an XV4S25 FPGA device and yields a maximum clock frequency of 150 MHz requiring 1,447 slices and 5 memory blocks. Mapping tasks from video contentanalysis applications from literature on the SA yields reductions in the execution time of 12 orders of magnitude compared to the software implementation. We conclude that the choice for an SA architecture is useful, but a scaled version of the SA featuring less logic with fewer processing and pipeline stages yielding a lower clock frequency, would be sufficient for a video analysis systemonchip.