Volcan: System Integration of HLS and HMC on FPGAs HighLevel Synthesis (HLS) is a process that translates traditional software languages (CCJava) into either a hardware description language representation or a netlist representation that, ultimately, can be implemented on an FPGA device, for example. The original goal was to make advanced computing accelerators accessible to embedded computing systems programmers. However, the technology has attracted the interest of highperformance computing (HPC) programmers as well. This would be a huge benefit because labor statistics suggest that every year 10x as many software programmers graduate for every hardware designer 1. However, HPC programmers use large incore datasets versus the transient, streaming data sets that are common in embedded systems. Looking forward, it is appropriate to explore the behavior of HLS with nextgeneration memory technologies, like the Hybrid Memory Cube (HMC).

CompilerBased HighLevel Synthesis of ApplicationSpecific Processors on FPGAs In order to meet tight performance andor energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example FieldProgrammable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern HighLevel Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Softcore processors implemented with FPGAlogic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a generalpurpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compilerbased synthesis methodology that generates networks of ApplicationSpecific Instruction Set Processors (ASIPs) from unmodified CC algorithms. We thereby bridge the gap between traditional softcore processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compilerbased approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)fixed commercial Xilinx MicroBlaze softcores.