A 10b 250MSs SAR ADC with SpeedEnhanced SAR Logic and Free Time More Than a Half of Sampling Period A 10b SAR ADC which can be used as the last stage in a highspeed and highresolution pipelinedSAR ADC is proposed. With the presented highspeed SAR logic, more than half of time in a sampling period is unused, which is a benefit for other stages in pipelinedSAR ADC with tighter timing. A unit capacitor with low parasitic effect is also presented. Together with redundancy and carefully placement in layout, the linearity of CDAC is improved. The noise of highspeed comparator is decreased because of the enlarged size in the input MOSFETs. The prototype ADC is implemented in UMC 28nm process. At 250MSs and 1.05V supply, the ADC consumes 3.23mW and achieves 9.34b ENOB with an SFDR of 79.9 dB and an SNDR of 58.0 dB. The FoM w  is 22.46 fJconv.step.

A 7.6nW 1kSs 10bit SAR ADC for Biomedical Applications This paper presents a 10bit successive approximation register analoguetodigital converter with energyefficient switching scheme for biomedical applications. The energyefficient switching scheme achieves an average digitaltoanalog converter switching energy of 63.56  CV_ref2 , achieving an reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of  V_cm  and complexity of digital control logic and DAC driver circuit. Moreover, dynamic circuits are used to reduce power consumption of comparator and SAR digital logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 xc2xb5m x 300 xc2xb5m (0.15 mm2). It consumes 7.6 nW at 1 kSs sampling rate and 1.8V supply with an achieved signaltonoiseand distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJconv.step.