An AreaEfficient MultiRate Digital Decimator A digital decimation filter is presented in this paper. Consisting of a CIC filter, a compensation filter and a halfband filter, the design can meet various frequency band requirements. The maximum input sampling frequency is 153.6MHz and decimation factors are 12, 24, 48 and 96. The 5section CIC filter down samplings rate by 6, 12, 24 and 48. A simple singlerate compensation filter is qualified for compensating the passband attenuation in all sampling situations. An areaefficient 48tap halfband FIR filter with no multiplier is designed with high passband and stopband performance. The decimator efficiently completes downsampling and filtering while taking up small IC area.

FirstOrder Recursive CIC Filters in TimeInterleaved VCOBased ADCs for DirectRF Sampling Receivers Digital building blocks operating at gigasamples per second (GSs) rates in direct radio frequency (RF) sampling receivers consume a large amount of the total power of the receivers. The previously reported techniques have not considered the digital blocks in analogtodigital converters (ADCs) and not decreased the power consumption. We first place firstorder recursive cascaded integratorcomb (CIC) filters with decimation factors of two after timeinterleaved ADCs (TIADCs), consisting of voltagecontrolled oscillators (VCOs), samplers, phase detectors, and differentiators. This CIC filter cancels out the differentiators with its integrators and halves the clock frequencies of the samplers to reduce the power consumption of the receiver. We design the digital blocks of a directRF sampling receiver with a 3.6GSs 4channel TI VCObased ADC for SubGHz applications (phase detectors, mixers, and CIC filters) by using a 65nm CMOS process. Simulations show that the placeandrouted circuit operates at a 450MSs rate with 3.6 mW, which is half of the power consumption of a digital circuit without the proposed method.