An EnergyEfficient Systolic Pipeline Architecture for Binary Convolutional Neural Network Memory and computation cost limit the applications of Convolutional Neural Networks (CNN) on mobile devices. Binary CNN (BCNN) is a quantized neural network, which can reduce memory requirement and achieve multiplicationfree computation. This paper focuses on BCNN. First, we proposed a hardware friendly CNN model to decrease the inference accuracy loss by eliminating the decimal part of each floating number. Second, we presented a fully pipelined onchip BCNN architecture. The architecture has systolic data flow and an interlayer pipeline, which ensures weights reuse and high throughputs. The results show that we achieve an inference accuracy of 99.04% for the MNIST dataset on the Pytorch platform and 98.91% in the hardware architecture, which means the inference accuracy loss is only 0.13%; the inference accuracy loss without this model is 0.41%. Besides, this architecture can achieve 23.08k: qfps and 353.5 GOPsW at 120MHz with small resource use while processing the BCNN.

HBUNN  Hybrid BinaryUnary Neural Network: Realizing a Complete CNN on an FPGA Most modern neural networks use the basic MultiplyAccumulate (MAC) Operation in some form or another, and as networks get larger, the computational needs for these larger networks grow rapidly. Typically neural networks implemented on FPGAs use variable multipliers so that any weight can be used in the MAC, but this also forces the accelerator designer to store the weights of the model in offchip memory (DRAM). Moreover, because of high computational power and high memory bandwidth requirements of todayu0027s CNNs, it is harder for FPGA platforms to deliver the best performance. In this paper, we propose a fully parallelpipeline Hybrid BinaryUnary Neural Network (HBUNN) architecture to implement a lowcost and highperformance ResNet18 convolutional neural network. We use a hybrid binaryunary method to implement constantcoefficient multipliers and batch normalization units. These two units reduce hardware cost by 30.7% and 47.97% on average compared to the conventional binary equivalent, respectively. Moreover, we propose a novel training scheme using our hardware costaware regularizers that not only improves the area cost of the proposed architecture and the conventional binary architecture by 59.3% and 76.7% respectively, but also maintains the same accuracy. Finally, we have implemented three trained networks using different regularizers. The proposed HBUNN architectures reduce the area cost by 30%, and the area xc3x97 delay cost by 69% on average compared to the conventional binary architectures. The error rate of the proposed work is 12.93%, while its throughput is 278 Kfps.