Evaluation of an OpenMP Parallelization of LucasKanade on a NUMAManycore LucasKanade algorithm is a wellknown optical flow estimator widely used in image processing for motion detection and object tracking. As a typical image processing algorithm, the procedure is a series of convolution masks followed by 22 linear systems for the optical flow vectors. Since we are dealing with a stencil computation for each stage of  the :55,overhead from memory accesses is expected to stand as a serious scalability bottleneck, especially on a NUMA manycore configuration. The objective of this study is therefore to investigate an OpenMP parallelization of Lucaskanade algorithm on a NUMA manycore, including the performance impact of NUMAaware settings at runtime.  Experimental results on a dualsocket INTEL BroadwellEEP is provided together with the corresponding technical  discussions

TwoDimensional SystolicArray Architecture for PixelLevel Vision Tasks This paper presents ongoing work on the design of a twodimensional (2D) systolic array for image processing. This component is designed to operate on a multiprocessor systemonchip. In contrast with other 2D systolicarray architectures and many other hardware accelerators, we investigate the applicability of executing multiple tasks in a timeinterleaved fashion on the Systolic Array (SA). This leads to a lower external memory bandwidth and better load balancing of the tasks on the different processing tiles. To enable the interleaving of tasks, we add a shadowstate register for fast task switching. To reduce the number of accesses to the external memory, we propose to share the communication assist between consecutive tasks. A preliminary, nonfunctional version of the SA has been synthesized for an XV4S25 FPGA device and yields a maximum clock frequency of 150 MHz requiring 1,447 slices and 5 memory blocks. Mapping tasks from video contentanalysis applications from literature on the SA yields reductions in the execution time of 12 orders of magnitude compared to the software implementation. We conclude that the choice for an SA architecture is useful, but a scaled version of the SA featuring less logic with fewer processing and pipeline stages yielding a lower clock frequency, would be sufficient for a video analysis systemonchip.