Research and Implementation of TPC Coding In High Bit Rate Telemetry System With the amount and complexity of telemetry data increasing, channel coding is designed to improve the coding gain of signals to make sure the transmission is reliable. In this paper, a TPC channel coding application method is designed according to the requirement of comprehensive gain and realtime performance. Considering the hardware resources and the complexity of implementation, the method is implemented based on FPGA which is suitable for high bit rate telemetry system. Taking BPSK for example, the results show that the TPC coding system provides about 7 dB coding gain compared with the traditional system at bit error rates of 10xe2x88x926, which improves the performance of the telemetry system.

Design and implementation of Serial ATA pbysical layer on FPGA An increasing number of highperformance computing system developed on FPGA devices need access to mass storage devices for storing data, the serial ATA protocol is widely used in the modern computer systems for transferring data between the host and hard disks or solidstate drives. This paper describes the design and implementation of serial ATA physical layer core based on the Xilinx GTX transceiver. With the method of cyclically changing the GTX line rate, the SATA hard disk with different line rate can be automatically identified and linked, realizing backward compatibility. An embedded system has also been developed for validating the functionality of our SATA physical layer core. We test our physical layer core with connecting our core to both SATA3 and SATA2 hard disks. The experimental result has indicated our core can not only provide the whole functionality required by the SATA physical layer, but also utilize very few logic resources on FPGA.