A Platform with Exquisite Film Profile Engineering in OxideBased ThinFilm Transistors for MorethanMoore Applications Recently we proposed and developed a unique film profile engineering (FPE) scheme for the fabrication of highperformance submicron oxidesemiconductor TFTs. In this scheme, profiles of the three pivotal thin films contained in a device, including gate oxide, oxidesemiconductor channel, and sourcedrain metal films, can be effectively tailored by selecting proper deposition tools with tunable process conditions. The fabricated IGZO, ZnO, and ZnON devices show decent performance in terms of high onoff current ratio (u003e 108) and steep subthreshold swing (u003c100 mVdec). Since the lowtemperature and the mature processes involved are highly compatible to the modern IC manufacturing, the fabricated devices can be readily integrated into the backendofline (BEOL) of an advanced chip, making the FPE scheme useful and potential for a number of emerging applications in the morethanMoore era.

Process Design Kit and Design Automation for Flexible Hybrid Electronics Highperformance lowcost flexible hybrid electronics (FHE) are desirable for internet of things (IoT). Carbonnanotube (CNT) thinfilm transistor (TFT) is a promising candidate for highperformance FHE because of its high carrier mobility   :32,superior mechanical flexibilitystretchability, and material compatibility with lowcost printing and solution processes. Flexible sensors and peripheral CNTTFT circuits, such as decoders, drivers and sense amplifiers, can be printed and integrated with thinned (u003c;50xcexbcm) silicon chips on soft, thin, and flexible substrates for appealing product designs and form factors. Here we report: 1) process design kit (PDK) to enable FHE design automation, from device modeling to physical verification, and 2) opensource and solutionprocess proven intellectual property (IP) blocks, including PseudoCMOS 1 digital logic and analog amplifiers on flexible substrates, as shown in Figure 1. The proposed FHEPDK and circuit design IP are fully compatible with silicon design EDA tools, and can be readily used for codesign with both CNTTFT circuits and silicon chips.