Adaptive Clock and Data Recovery for Asymmetric Triangular Frequency Modulation Profile Clock and Data Recovery (CDR) is an important block in SerializerDeserializer (SerDes) systems used to recover the clock from the bitstream. With high data rates, the effect of Electromagnetic Interference (EMI) is increased. Several spreading spectrum profiles are able to reduce the effect of EMI. Asymmetric spreading spectrum profile is one of the types that can be implemented easily and can make a significant reduction on EMI. The challenge in CDR design is increased with asymmetric spreading profiles as the slewrate is high with respect to the other profiles. Many researches provided several architectures for adaptive CDR with symmetric spreading profiles. In this research, a new architecture is proposed to detect the large phase error to reach suitable CDR controller parameters needed to recover the clock with high slewrate profiles. The proposed architecture is able to get locking with the incoming data in shorttime even with an initial large difference between transmitter and receiver clock frequency and at the same time achieve minimum jitter. A white Gaussian noise with 30 dB Signal to Noise Ratio (SNR) is used on a channel model to simulate the actual behavior on SIMULINK. Also, a search algorithm is proposed to find the best CDR settings in the proposed architecture. Results obtained from MATLAB shows the efficiency of the proposed architecture to track the data with largest slewrate using sudden step change on transmitter clock frequency.

A patterndependent injectionlocked CDR for clockembedded signaling Abstract   This paper presents a CDR architecture for clockembedded signaling. To suppress the effect of datadependent jitter of the conventional DLLbased approach, we propose a patterndependent injectionlocking scheme in a PLLbased clock recovery circuit. It achieves both benefits of PLL and DLL, the input jitter filtering and the clearance of accumulated VCO jitter, respectively. A jitter analysis is also presented to develop a design strategy for the optimal extraction of injection timing from random data stream. The CDR, implemented in a 28xe2x80xafnm CMOS, achieves a data rate of 12.5xe2x80xafGbs with a 13.7xe2x80xafdBloss channel and verifies the validity of the analysis.