HighSpeed ASIC Implementation of Paillier Cryptosystem with Homomorphism Recently, compatibility between privacy protection and information utilization has been considered to be a major challenge. Hence, researches on homomorphic cryptosystem which can realize secure computation draw growing attention. The Paillier encryption with additive homomorphism is widely used in fields such as electronic voting and secure biometrics. At the same time, the large amount of data in the database and the requirements of Paillier security require computationally expensive processes each authentication and comparison, so the improvement of computational efficiency is particularly important. In this research, in order to reduce the computation time of Paillier, we design an ASIC based hardware architecture dedicated to Paillier encryption, and realize highspeed encryption and decryption by using high radix arithmetic core and the parallelism in the decryption process.

HEAX: An Architecture for Computing on Encrypted Data With the rapid increase in cloud computing, concerns surrounding data privacy, security, and confidentiality also have been increased significantly. Not only cloud providers are susceptible to internal and external hacks, but also in some scenarios, data owners cannot outsource the computation due to privacy laws such as GDPR, HIPAA, or CCPA. Fully Homomorphic Encryption (FHE) is a groundbreaking invention in cryptography that, unlike traditional cryptosystems, enables computation on encrypted data without ever decrypting it. However, the most critical obstacle in deploying FHE at largescale is the enormous computation overhead.  :89,this paper, we present HEAX, a novel hardware architecture for FHE that achieves unprecedented performance improvement. HEAX leverages multiple levels of parallelism, ranging from ciphertextlevel to finegrained modular arithmetic level. Our first contribution is a new highlyparallelizable architecture for numbertheoretic transform (NTT) which can be of independent interest as NTT is frequently used in many latticebased cryptography systems. Building on top of NTT engine, we design a novel architecture for computation on homomorphically encrypted data. We also introduce several techniques to enable an endtoend, fully pipelined design as well as reducing onchip memory consumption. Our implementation on reconfigurable hardware demonstrates 164268x performance improvement for a wide range of FHE parameters.