A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate Power consumption is one of the main challenges nowadays. Dynamic power is a challenging source of power dissipation for dynamic logic. Dynamic power is affected by output transition rate. The more the output transition rate, the more the dynamic power is consumed. This paper proposes a new technique to reduce dynamic power based on reducing output transition rate. The new proposed technique permits only one output transition for similar consecutive input patterns. The proposed technique is proved to be very effective when input patterns are fixed for consecutive number of clock cycles as in grey code. An isolator is used to isolate last valid output to avoid output corruption due to reducing output transition rate. Experimental results on TSMC 65 nm at 1 GHZ show the effectiveness of the proposed technique in reducing output transition rate, providing isolated valid output, and reducing dynamic power up to 60% of the original consumed power.

Power optimization for FPRM logic using approximate computing technique A power optimization algorithm based on approximate computing technique was proposed for FPRM logic circuits. The algorithm includes FPRM logic circuits dynamic power estimation model based on signal probability and transition density, a genetic algorithm for RM logic power optimization using polarity searching and error rate (ER) calculation for RM logic using double sharp product operation. Under the constraint of ER, some product terms are selectively deleted to reduce power consumption. The proposed algorithm is implemented in C and tested under MCNC benchmarks. Experimental results show that by using the approximate computing technique, the average dynamic power can be reduced by 22.77% with the average ER of 3.21%.