Testing ComputationinMemory Architectures Based on Emerging Memories Todayu0027s computing architectures and device technologies are incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel postCMOS computing architectures are being explored. One of these is a ComputationinMemory (CIM) architecture based on memristive devices; it integrates the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computationinmemory bitwise logical operations.

Performing MemristorAided Logic (MAGIC) using STTMRAM Modern computers suffer from a limited data transfer rate between the memory and the processing units. One of the attractive potential solutions to overcome this bottleneck is to combine processing and memory by performing computing in the same location where the data is stored. Processinginmemory (PIM) has been demonstrated by memristoraided logic (MAGIC) operations using resistive random access memory (RRAM) memristive devices within crossbar arrays. Nevertheless, RRAM devices are relatively slow and suffer from limited endurance. Spintransfer torque magnetoresistive random access memory (STTMRAM) is another memristive technology, which is faster and has practically unlimited endurance and is therefore considered to be an attractive technology for cachelevel memories. In this paper, we demonstrate MAGIC operations within an STTMRAM array by supplying voltages suitable to achieve the current required for MRAM device switching. The proposed circuit was evaluated in SPICE simulations with the GlobalFoundries 22nm CMOSMRAM process, including Monte Carlo simulations to verify the proposed design in the presence of process variation and device mismatch. The circuit showed more than 90% chance of functioning for the 1 1 and 0 0 input cases while it was about 85% correct for the 0 1 case.