A New Approximate Multiplier Design for Digital Signal Processing In this paper, a new approximate multiplier is proposed, which can decrease the multiplication complexity with the improved area and power performance by using OR and AND gates. To evaluate the efficiency of the proposed approximate multiplier, design parameters are compared with exact multiplier and recently proposed approximate designs. Experiment results reveal that the power consumption of the proposed approximate multiplier is only 32% of that in the exact multiplier. The proposed approximate multipliers are further evaluated in image sharpening and edge detection applications. The peak signal to noise ratio (PSNR) and structural similarity (SSIM) of our proposed approximate multipliers show that it can be used in image processing.

Approximate Multiplier Using Reordered 4xe2x80x932 Compressor with ORbased Error Compensation Today, the approximate circuits have become an efficient solution for low power design on human related errortolerant applications, such as multimedia, recognition and several signal processing. Approximate multipliers are believed to be an important key to make approximate arithmetic systems, and more area efficient multiplier is expected. The paper proposes a new areaefficient 4xe2x80x932 compressor based on input reordering and ORbased error compensation. By the reordering, we can focus on just 2 of 4 inputs, and the compressor becomes very simple and less gates. Two multipliers are proposed with different accuracy based on reordered compressors with ORbased error compensation. The experimental results show that the proposed multipliers achieve high accuracy (98.7% and 97.39%) while reduce power consumption (by 44.72% and 45.95%) and area (by 31.72% and 34.85%). The proposed approximate multipliers are applied on image sharpening process and show high PSNR and SSIM.