Customizing CMOSReRAM Hybrid Hardware Architecture for Spiking CNN Spiking CNN can greatly reduce the computation and accordingly reduces the energy consumption with a small penalty to the accuracy, but the network latency is significantly increased because of the long spike trains. In this paper, we first introduce layer factors in the normalization of the synaptic weights and propose a greedy method to search proper layer factors for improving the network latency. Second, we present a customizable CMOSReRAM hybrid hardware architecture for Spiking CNN. The architecture consists of an array of configurable basic units (CBU), which involves a CMOS adder for neuron operations and a 1T1R memristive crossbar for storing synaptic weights. A column of CBUs can be configured as spiking neurons corresponding to convolutional kernels with various sizes while the whole array can be configured to provide row parallelism for a kernel convolution and interkernel parallelism. The input spike trains are transmitted between CBUs and are reused by different spike neurons when performing parallel computing of rows in spike feature maps. The results show that the network latency can be reduced 42.3% for an accuracy of 98.04% in LeNet5 by introducing layer factors. To our best knowledge, this is the first work to design customizable hardware architecture for Spiking CNNs. The simulation results show that the Spiking CNN consumes only 15.4% of the energy consumption of PipeLayer when processing the MNIST dataset.

Neuromorphic Hardware Accelerator for SNN Inference based on STTRAM Crossbar Arrays In this paper, we propose a Spin Transfer Torque RAM (STTRAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the timebased signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of nonvolatile STTRAMs, readwrite peripheral circuits, and digital logic for the spiking neurons. Intercore communication is realized through onchip routing network by sendingreceiving spike packets. Unlike prior works that use multilevel states of nonvolatile memory (NVM) devices for the synaptic weights, we use the technologicallymature STTRAM devices for binary data storage. The design studies are conducted using a compact model for STTRAM devices, tuned to capture the stateoftheart experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STTRAM based neurosynaptic core designed in 28 nm technology node has approximately 6xc3x97 higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves xe2x88xbc 2xc3x97 higher performance per Watt compared to other memristive neural network accelerator designs in the literature.