An FPGA Implementation of GCN with Sparse Adjacency Matrix Deep learning has revolutionized many machine learning tasks in recent years, ranging from image classification and video processing to speech recognition and natural language understanding. The data in these tasks are typically represented in the Euclidean space. However, there is an increasing number of applications where data are generated from nonEuclidean domains and are represented as graphs with complex relationships and interdependency between objects. The complexity of graph data has approaches for graph data have emerged. Graph convolution networks (GCNs) in particular, try to replicate the success of CNN in graph data by defining graph convolutions via graph spectral theory or spatial locality. This paper presents a new GCN accelerator for the graph convolution layers of STGCN 1, which is successfully applied in action recognition. The accelerator breaks down the graph convolution into convolution and matrix multiplication with adjacency matrix. To optimize the power efficiency, the dataflow of the convolution is designed properly and a sparse matrixvector multiplication is proposed to make use of the sparsity of the adjacency matrix. The accelerator is implemented on NSA.241 accelerator and can reach its peak performance of 46.0GOPs under 188MHz with about 220 DSP, which achieves high DSP efficiency.

GraphACT: Accelerating GCN Training on CPUFPGA Heterogeneous Platforms. Graph Convolutional Networks (GCNs) have emerged as the stateoftheart deep learning model for representation learning on graphs. It is challenging to accelerate training of GCNs, due to (1) substantial and irregular data communication to propagate information within the graph, and (2) intensive computation to propagate information along the neural network layers. To address these challenges, we design a novel accelerator for training GCNs on CPUFPGA heterogeneous systems, by incorporating multiple algorithmarchitecture cooptimizations. We first analyze the computation and communication characteristics of various GCN training algorithms, and select a subgraphbased algorithm that is well suited for hardware execution. To optimize the feature propagation within subgraphs, we propose a lightweight preprocessing step based on a graph theoretic approach. Such preprocessing performed on the CPU significantly reduces the memory access requirements and the computation to be performed on the FPGA. To accelerate the weight update in GCN layers, we propose a systolic array based design for efficient parallelization. We integrate the above optimizations into a complete hardware pipeline, and analyze its loadbalance and resource utilization by accurate performance modeling. We evaluate our design on a Xilinx Alveo U200 board hosted by a 40core Xeon server. On three large graphs, we achieve an order of magnitude training speedup with negligible accuracy loss, compared with stateoftheart implementation on a multicore platform.