Highspeed Classification of AER Data Based on a Lowcost Hardware System This paper proposes a lowcost hardware system for rapid classification of visual objects encoded in the addressevent representation (AER) format. A lightweight statistical inference algorithm is implemented in the proposed hardware to process the asynchronous pixel address streams from an AER visual sensor. The algorithm involves only a few simple operations for patchbased binary feature extraction and Random Ferns inference, which are highly parallelized and accelerated by our dedicated hardware architecture. Simulation results suggested that our hardware system was able to process as many as 50M address events per second and achieved 75% classification accuracy for the popular MNISTDVS dataset. Compared to other AER classification systems, our lowcost FPGA implementation is more plausible for embedded applications because of its similar accuracy and higher system throughput.

An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron At present, the neuromorphic hardware with analog neuron is widely studied by researchers. Address event representation (AER) is an event protocol, which usually used for interchip communication between neuromorphic chips. Fixed priority arbiter often results in unfair allocation of bus resource to only the high priority neuron, thus introducing fixed noise in the neural network. In this paper, we propose an asynchronous AER circuits with rotation priority tree arbiter to alleviate this issue. Moreover, to match the different delay between AERu0027s handshake signal and neuronu0027s handshake signal, a special handshake circuits is designed. Simulation results show that the 64 channels AER circuits can perform up to 143M events. The design is designed with SMIC180 process for fabricating RRAM based neuromorphic chip.