Architecture considerations of LTEWCDMA wideband power amplifier for efficiency improvement An enhanced architecture for a broadband power amplifier (PA) for LTE and WCDMA handsets using InGaPGaAs heterojunction bipolar transistor (HBT) process is presented. A twostage PA solution adopting switchable driverstage amplifier without employing input switch is proposed to reduce loss and help with power efficiency improvement. Furthermore, in order to enhance the poweradded efficiency (PAE) at the low output power level, a twochain amplifying structure in parallel has been implemented. For wideband 1.711.98GHz, the fabricated PA shows u003e27dB of Gain and u003e38% of PAE with  16dB of Gain and u003e13% of PAE with u003c20mA of Icq at the Pout of 17dBm for lowpower mode operation. The system power usage efficiency are obviously enhanced with the presented twostage dualchain PA architecture.

A 2.5GHz LTE Doherty Power Amplifier in SOICMOS Technology The need for RF FrontEnds Module (FEM) with reduced size and cost is driving research towards highly integrated Power Amplifiers (PA) with challenging linearity and efficiency requirements. To overcome efficiency challenges, the Doherty PA (DPA) architecture represents an attractive solution because of its high backoff efficiency and relatively simple structure. This paper presents a stateofthe art SOI CMOS DP A design implemented in a 0.13um SOI CMOS industrial process. At 2.5GHz, the 2stage SOI CMOS DPA achieves a measured peak PAE of 57% at 32.7dBm output power under 3.4V voltage supply. At IdB compression point, output power and PAE are 32.4dBm and 56% respectively. With a 10MHz LTE uplink signal, a linear output power of 29.4dBm is measured with a PAE of 48.8% at an ACLR level of xe2x88x9233dBc without using DPD.