Sampling Rate Enhancement for SARADCs Using Adaptive Reset Approach for FOG Systems In this investigation, an adaptive reset strategy of a 10bit SARADC particularly designed for the applications in FOG (fiber optic gyroscope) systems is demonstrated with TSMC 40 nm CMOS technology. The proposed adaptive reset approach takes advantage of high correlation of the phase shift generated by continuous FOG signals such that MSB bits of two consecutive samples likely remain the same, which implies there is no need to reconverted. By replacing conventional allreset method with the adaptivereset strategy, the throughput of the SAR ADC is theoretically increased up to around 100%. The sampling rate is increased by 2 times compared with the conventional counterpart.

A 7.6nW 1kSs 10bit SAR ADC for Biomedical Applications This paper presents a 10bit successive approximation register analoguetodigital converter with energyefficient switching scheme for biomedical applications. The energyefficient switching scheme achieves an average digitaltoanalog converter switching energy of 63.56  CV_ref2 , achieving an reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of  V_cm  and complexity of digital control logic and DAC driver circuit. Moreover, dynamic circuits are used to reduce power consumption of comparator and SAR digital logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 xc2xb5m x 300 xc2xb5m (0.15 mm2). It consumes 7.6 nW at 1 kSs sampling rate and 1.8V supply with an achieved signaltonoiseand distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJconv.step.