20, 000fps Visual Motion Magnification on Pixelparallel Vision Chip This paper proposes a pixelparallel Eulerian Video Magnification (EVM) algorithm for vision chips. The proposed algorithm is optimized for the stereotyped programmable pixelparallel array processor architecture favored by highspeed vision chips. We also propose an improved pixelparallel array processor with alternative image border padding modes to satisfy various algorithm requirements. We implemented an FPGA prototype of an improved 128 xc3x97 128 pixelparallel array processor to run the proposed optimized EVM algorithm with a 120 MHz clock. Experimental results show that our pixelparallel system can magnify subtle motion clues at a very high speed up to 20, 000 frames per second (fps).

TwoDimensional SystolicArray Architecture for PixelLevel Vision Tasks This paper presents ongoing work on the design of a twodimensional (2D) systolic array for image processing. This component is designed to operate on a multiprocessor systemonchip. In contrast with other 2D systolicarray architectures and many other hardware accelerators, we investigate the applicability of executing multiple tasks in a timeinterleaved fashion on the Systolic Array (SA). This leads to a lower external memory bandwidth and better load balancing of the tasks on the different processing tiles. To enable the interleaving of tasks, we add a shadowstate register for fast task switching. To reduce the number of accesses to the external memory, we propose to share the communication assist between consecutive tasks. A preliminary, nonfunctional version of the SA has been synthesized for an XV4S25 FPGA device and yields a maximum clock frequency of 150 MHz requiring 1,447 slices and 5 memory blocks. Mapping tasks from video contentanalysis applications from literature on the SA yields reductions in the execution time of 12 orders of magnitude compared to the software implementation. We conclude that the choice for an SA architecture is useful, but a scaled version of the SA featuring less logic with fewer processing and pipeline stages yielding a lower clock frequency, would be sufficient for a video analysis systemonchip.