Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number System We describe a signal highfrequency estimation circuit using multiple lowfrequency sampling circuits following an analog Hilbert filter and analogtodigital converters (ADCs); here the sampling frequencies are relatively prime. Our proposed system is based on aliasing phenomena in frequency domain in waveform sampling and the residue number theory. A high frequency sampling circuit can directly estimate a high frequency input signal. However, handling of high frequency signals in electronic circuits is difficult and hence the proposed circuit is relatively easy to implement. Cosine wave with high frequency is provided as an input signal. Then cosine and sine signals with the same frequency are generated with an analog Hilbert filter (such as an RC polyphase filter) and they are fed into sampling circuits with different (relatively prime) and low sampling frequencies. Their analog outputs are analogtodigital converted and for their digital outputs, complex FFTs are performed. Since the high frequency signal is sampled with low frequency clocks, the aliasing (spectrum folding) occurs. However, each aliased frequency is different because each sampling clock frequency is different in sampling circuits. Then according to the Chinese remainder theorem, the input frequency can be estimated. Notice that usage of the analog Hilbert filter is new in this paper; if the analog Hilbert filter is not used and the cosine input is directly sampled, the residue frequency cannot be obtained.

FirstOrder Recursive CIC Filters in TimeInterleaved VCOBased ADCs for DirectRF Sampling Receivers Digital building blocks operating at gigasamples per second (GSs) rates in direct radio frequency (RF) sampling receivers consume a large amount of the total power of the receivers. The previously reported techniques have not considered the digital blocks in analogtodigital converters (ADCs) and not decreased the power consumption. We first place firstorder recursive cascaded integratorcomb (CIC) filters with decimation factors of two after timeinterleaved ADCs (TIADCs), consisting of voltagecontrolled oscillators (VCOs), samplers, phase detectors, and differentiators. This CIC filter cancels out the differentiators with its integrators and halves the clock frequencies of the samplers to reduce the power consumption of the receiver. We design the digital blocks of a directRF sampling receiver with a 3.6GSs 4channel TI VCObased ADC for SubGHz applications (phase detectors, mixers, and CIC filters) by using a 65nm CMOS process. Simulations show that the placeandrouted circuit operates at a 450MSs rate with 3.6 mW, which is half of the power consumption of a digital circuit without the proposed method.