The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT Processor In this paper, a new hybrid radices reconfigurable FFT processor is proposed, which supports computing modes of radixes 248 and their combination, satisfying 2n(n6,7 xe2x80xa6, 15) point FFT calculation. This processor provides a sharing for different radices FFT, and proposes the radix48 address conflictfree rule from radix2 FFT address conflictfree rule. The data prefetching ensures uninterrupted operationflow and improves the calculation speed. This design performs functional verification on Xilinx XC7V2000T FPGA, and performs the layout under the TSMC 28nm process with a working frequency above 800MHz and an area of 1.15 mm 2. The calculation speed approaches the theoretical value of the given the number of butterfly units, and the calculation accuracy reaches 10xe2x88x925.

FPGAbased Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption Homomorphic encryption (HE) is an important cryptographic primitive which allows privacy preserving computations. Current HE schemes are all based on modular arithmetic. Modular multiplication (ModMult) is one of the most frequently used modular operations, but in practice it is often prohibitively slow due to a reduction operation with high computational complexity. To address this speed problem, we demonstrate a set of novel FPGAbased accelerators for fully pipelined ModMults in this paper. For a highthroughput integer multiplier (IntMult) in the ModMult designs, digital signal processing (DSP) slices on FPGAs are efficiently exploited with optimized IntMult designs. For the full RNSHEAAN scheme, which is our target HE scheme, our proposed Barrett ModMult design is optimized using specific moduli and extended to the Shoup ModMult algorithm. Our proposed Barrett and Shoup ModMult designs implemented on a Xilinx Virtex UltraScale FPGA show a 2 xc3x97 shorter delay, 14xc3x97 higher throughput at the same frequency, and 3xc3x97 higher throughputDSP than the previous nonfully pipelined Barrett ModMult design on average. In particular, our Barrett ModMult design with the specific moduli shows the highest throughputDSP value although precomputation required in the Shoup ModMult design is not used. Compared with a reference software implementation, our ModMult designs show 679xc3x97 faster average processing speeds when we deploy multiple ModMult cores that fully use DSP slices on our target FPGA.