A Low Complexity DDS Based On Optimized CORDIC Algorithm Aiming at the highspeed and low complexity of Direct Digital Frequency Synthesizer (DDS), this paper presents an improved structure of CORDIC algorithm (the excessfour algorithm). The mathematical approximate calculation is used to optimize the circuit structure of the rotating module in the excessfour algorithm, which reduces the adder in the rotating module and the hardware consumption of the circuit effectively. By removing the carryover operation of the phase accumulating module, all the threelevel rotating modules have the same structure, which ensures the same delay in all rotating units. The approach makes more advantages in the design of highspeed DDS circuits. Using the improved rotating structure, this paper implements the design of a highspeed DDS digital unit up to 6Gsps, with the SFDR above 88dBc, up to 104dBc. The single DDS core area is approximately 0.14 mm2 and the power consumption is 0.01mW MHz, using the Synopsysu0027 SMIC 65nm process library tool to complete ASIC backend design. In the case of SFDR that meets most of the highspeed DDS digital parts, the area and power consumption in this paper are greatly improved, compared with the conventional implementation method.

A Digital Pseudo Random Number Generator Based on a Chaotic Dynamic System Chaotic based Pseudo Random Number Generators (PRNGs) have been very popular due to their unpredictable behavior. Hardware implementations of PRNG is used in many applications including cryptography, security and communication systems. Chaotic systems demonstrate an extreme sensitivity to variations in initial conditions and control parameters which makes it ideal for such applications especially cryptography. Due to this severe sensitivity, it is essential to implement the system with a sufficient accuracy while keeping the hardware cost as low as possible. An efficient and compact digital design is proposed for a PRNG based on a lowdimensional chaotic dynamic system. In this design, CORDIC algorithm has been used to reduce the hardware cost while maintaining the accuracy high. Experimental results and error measurements indicate a maximum error of 0.011 and RMSE of 0.0015 between the proposed digital circuits and the original chaotic system. The circuits have been synthesized for an Altera FPGA board. The results indicate that the circuits are successfully able to mimic the mathematical simulation counterpart. In addition, synthesis results verify that the proposed circuits take less than 1% of the target FPGA resources. Furthermore, Static Timing Analysis demonstrate a maximum frequency of 172.09 MHz for the proposed circuits. The proposed circuits can be employed in cryptography and security applications due to their compactness and high accuracy.