Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis Memory level parallelism (MLP), which refers to the number of memory requests concurrently held by Miss Status Handling Registers (MSHRs), is an indispensable factor to estimate cache performance. Unfortunately, due to the complexity of obtaining the maximum number of memory instructions or cache misses among all dependence paths, previous works in MLP modeling are very timeconsuming in trace profiling. In this paper, we propose a fast model for evaluating MLP without analyzing all dependence paths in the instruction windows. Instead, we construct a probability model to estimate the maximum number of cache misses among all dependence paths in the instruction windows fed with some easily obtained inputs. By doing so, we greatly reduce the time overhead of the MLP model with a slight drop in accuracy. Twelve benchmarks chosen from Spec2006 are adopted for evaluating the accuracy and time overhead of our model. The average error of our model compared with the results of Gem5 simulations is around 9%, while the time overhead of the MLP evaluation process can be decreased to about half of previous models.

A DataSharing Aware and Scalable Cache Miss Rates Model for MultiCore Processors with MultiLevel Cache Hierarchies To mitigate the ever worsening Power wall and Memory wall problems, multicore architectures with multilevel cache hierarchies have been widely used in modern processors. However, data sharing caused by the concurrent threads running on different cores and the filter effects of multilevel caches make the analytical cache modeling of such systems extremely complex. Prior models either ignore the data sharing or evaluate its effect with large simulation costs. In this paper, we propose a datasharing aware and scalable analytical model for estimating the miss rates of the downstream shared cache in a multicore environment. Our model uses probability derivations to quantify the data sharing effects based on the information of access address distributions for each core. Moreover, the proposed model can also be scalably integrated with upstream cache models without the timeconsuming simulations of the cache architecture. We validate our analytical model against gem5 simulation results under 13 benchmarks from PARSEC benchmark suites. We compare the L2 cache miss rates with the results from gem5 under 8 hardware configurations including dualcore and quadcore architectures. The average absolute error is less than 2% for all configurations.