Design of HighSpeed Drivers for 56Gbs PAM4 Optical Communications in CMOS As the optical module bandwidth fastly developing towards 400Gbs, the singlechannel datarate reaches 56Gbs. This leads to both architectural and bottomlevel components change in the transceiver modules. More significant bandwidth shortage, nonlinearity, as well as noises are experienced by the optical devices. This paper reviews the challenges and key techniques in the design of laser and modulator drivers in CMOS. The solutions for 400G Ethernet are firstly introduced, which is then detailed in topology and core chips organization. Then, the circuits design for PAM4 modulation are discussed and demonstrated, respectively in a CMOS 50Gbs VCSEL driver and a CMOS 50Gbs Siphotonic MZM driver. The clock and data recovery (CDR) technique for direct PAM4 modulation is studied, which is then utilized to build the high integrity transmitters in CMOS.

ISI Sensitivity of PAM Signaling for Very HighSpeed ShortReach Copper Links This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation highspeed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to intersymbol interference (ISI), using four different channels (with their loss gradually increased) running at 28 Gbs, 56 Gbs, 112 Gbs and 224 Gbs. Each case is examined with and without equalization to properly assess the inherent limitations of the modulation schemes in the presence of ISI. This study shows that although higher order PAM offer a better spectral efficiency, this does not translate into the best performance in terms of signal integrity. Depending on the severity of ISI and the data rate, a lower order PAM can outperform a higher order PAM, especially for the lowloss cases.