A PowerAreaEfficient LowDropout Regulator With Enhanced Buffer Impedance Attenuation This paper proposed a lowdropout regulator (LDO) with a dynamicbiasing super buffer technique and a 2stage error amplifier (EA). The 2stage EA provides a high loop gain and wide output swing so as to implement an ultra small load regulation and line regulation. The dynamicbiasing super buffer technique, made of super source follower, ultra lowoutput impedance buffer and dynamic biasing technique, ensures the stability of the LDO with a 1xc2xb5F output capacitance and adjusts the quiescent current (Iq) of the LDO in different load current so that an ultra low I q  is achieved by the proposed LDO structure. Based on Global Foundry 0.18xc2xb5m CMOS process, the circuit can drive up to 200mA load current at 1.2V output voltage in 1.4V 2V supply voltage (Vs). In 1.4Vs, Iq is 26.3xc2xb5A in no load and 57.7xc2xb5A in full load. In 2Vs, Iq is 26.4xc2xb5A in no load and 246.2xc2xb5A in full load. The load regulation is 1.12xc2xb5VmA in 1.4Vs and the line regulation is 0.50mVV in 200mA full load.

A 1.26psFoM OutputCapacitorless LDO with DualPath ActiveFeedback Frequency Compensation and CurrentReused Dynamic Biasing in 65nm CMOS Technology An outputcapacitorless lowdropout regulator (OCLLDO) using dynamic biasing with crosssummed error current to enhance transient response has been presented in this paper. Compared to the conventional OCLLDO with commonsource differential input stage, a crosscoupled commongate (CG) differential pair has been adopted to be the input stage of the error amplifier (EA), so that both the equivalent transconductance and the unitygainfrequency (UGF) can be doubled. As a result, it reduces the input resistance of the EA and improves the stability of the proposed LDO. Moreover, the crosssummed error currents boost the slew rate at the gate of power transistor and further improve the transient response. The proposed OCLLDO is designed in 65nm CMOS technology. The input voltage range is 0.951.2V, and output voltage is 0.8V. It can work stably in a load range of 0xe2x80x93100 mA under output capacitance of 0xe2x80x93100 pF. A simulated FigureofMerit (FOM) of 1.26 ps is achieved with 13.9xc2xb5A quiescent current only.