A Fast Reduction Method for Path Process Variations Without TimeConsuming Training In deeply nanoscaled technology nodes, the number of process variations of the circuits will be up to thousands. Although dimensionality reduction can reduce the complexity for circuit modeling, it always needs SPICE and Monte Carlo simulations. In this paper, a weight model of process variations for each individual cell is proposed, which is fed with the operation conditions. After that, a path process variation reduction method is proposed by considering the influence of the cell delay deviations and their weights. The proposed method is verified under ISCAS85 benchmark suite. When selecting the top 20% critical variations, the mean and standard deviation errors of the delay distribution in our method are merely 0.06% and 0.56% compared with the results from SPICE simulations. The model realizes a fast quantification of the process variation effects on any circuit without timeconsuming training processes.

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit With the technology node scaling down, aging effect and process variations have become the most critical reliability issues for integrated circuit. In this paper, the influence of BTI effect and process variation on threshold voltage is analyzed. Then, the delay of logic gate and the change of subthreshold current are deduced from the change of threshold voltage. Finally, the logic gate and ISCAS85 circuit are simulated by HSPICE in PTM 45nm model. Simulation results show the relationship between delay and subthreshold current with aging time, which can be used to predict the degradation of circuit parameters. The change of circuit delay can be quickly monitored by measuring subthreshold current.