Fully Differential Touch Screen Controller with Wide Input Dynamic Range for Thin Displays As todayxe2x80x99s smartphone displays become thinner, the coupling capacitance between the display electrodes and touch screen panel (TSP) electrodes is increasing significantly. The increased capacitance easily introduces timevarying display signals into the TSP, deteriorating the touch performance. In this research, we demonstrate that the maximum peak display noise in the time domain is approximately 30% of the maximum voltage difference of the display grayscale through analysis of the structure and operation of displays. Then, to mitigate display noise, we propose a circuit solution that uses a fully differential charge amplifier with an input dynamic range wider than the maximum peak of the display noise. A test chip was fabricated using a 0.35 xcexbcm CMOS process and achieved a signaltonoise ratio of 41 dB for a 6mmdiameter metal pillar touch when display pulses with 5V swing were driven at 100 kHz.

A PreEmphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time A preemphasis pulse generator is proposed which can provide minimal wordline or columnline delay time in a large memory array or panel display without calibration even under a large process variation. The optimum preemphasis pulse width is theoretically identified by monitoring the farend of the delay line to reach a certain value which does not include the parasitic resistance and capacitance of the delay line but only includes an amount of overdrive. The circuit was fabricated together with the delay line in 0.18 xcexbcm 3V CMOS. Even with RC variation of 20%, the proposed circuit reduced the delay time by 60% with 60% overdrive in comparison with a fixed preemphasis pulse width without any calibration prior user operation or any special test sequence in die test. Sensitivity of a variation in a reference voltage and a comparator offset on the delay time is also discussed. Furthermore, the optimum detection level is presented in case that the resistance of driver and switch is as high as that of the delay line.