Hardware Implementation of Convolutional Neural Network for Face Feature Extraction As an important feedforward neural network in the field of deep learning, convolutional neural network (CNN) has been widely used in image classification, face recognition, natural language processing and document analysis in recent years. CNN has a large amount of data and many multiply and accumulate (MAC) operations. With the diversity of application files, the channel sizes and kernel sizes of CNN are diverse, while the existing hardware platform mostly adopts the average optimization technology, which causes the waste of computing resources. In this paper, a special configurable convolution computing array is designed, which contains 15 convolution units, each PE contains 6xc3x976 MAC operations, it can be configured to calculate three different kernel sizes of 5xc3x975, 3xc3x973 and 1xc3x971. At the same time, pipeline structure is used to synchronize convolution and pooling operations, which reduces the storage of intermediate results. We design the special hardware structure to optimize DeepID network. Tested on Altera Cyclone V FPGA, the peak performance of each convolution layer at 50 MHz is 27 GOPS, and the average utilization of the MAC is 92%.

FPNet: Customized Convolutional Neural Network for FPGA Platforms The Convolutional Neural Network (CNN) has been widely adopted in various applications, which include object detection mobile robot vision, image search engine, etc. And due to the computingintensive and memoryintensive features of CNN models, specialized hardware accelerators, like ApplicationSpecificIntegratedCircuit (ASIC) and Field Programmable Gate Arrays (FPGA) have been widely utilized in edge devices. Among all the neural network specialized hardware accelerators, an FPGA accelerator stands out for its flexibility, short timetomarket, and energy efficiency. Previous works about FPGA accelerator designs are mostly changing hardware configuration to fit the CNN model structure. In this paper, we propose an automated neural network architecture search approach utilizing reinforcement learning to design customized convolutional neural network model for specialized FPGA platforms.