Synthesizable InjectionLocked PhaseLocked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays A synthesizable injectionlocked phaselocked loop with multiphase interlocking digitally controlled oscillator arrays (SILPLLIDCOS) is proposed. By doing interlocking of two digitally controlled oscillators (DCOs), the number of phase provided can be double and the oscillation frequency can be as fast as the original DCO. Moreover, it also adopts frequency tracking loop to isolate the injection path from the traditional PLL path in the ILPLL, so the race condition in the traditional ILPLL can be resolved. The chip has been designed and implemented in TSMC 40 nm GP 1P10M CMOS process technology. In the proposed synthesizable ILPLL, all logic cells and circuit components are using standard cell provided by foundry and our group. The total area of the synthesizable ILPLL core is only 0.01876 mm2 and provides 8 phase output. The postlayout simulated RMS jitter from a 5.024 GHz output frequency is 0.048 %UI. The total measured power consumption is 10.97 mW at 5.024 GHz output frequency and 78.5 MHz reference clock.

AllDigital PhaseLocked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping In this paper, we study the propagation of timing error in a synchronous AllDigital PhaseLocked Loop network. The architecture of the network represents a linear array of oscillators, where the first oscillator is considered as the reference oscillator, and the others are implemented as digitally controlled oscillators. The synchronisation of the network is achieved through interactions between a controlled oscillator and its closest neighbours. Using FPGA prototyping, we have shown that the jitter of a controlled oscillator saturates with the distance from the reference oscillators and that the bidirectional topology has better performance than the unidirectional topology. A comparison of measurements with a theoretical model is carried out to verify our FPGA prototyping framework.