A GrainAdaptive Computing Structure for FPGA CNN Acceleration In recent years, because of its superior performance and outstanding accuracy, convolutional neural networks (CNNs) are widely used in hightech applications such as image classification and speech recognition. But it is more and more difficult to implement CNN in hardware platform due to the scale of CNN is increasing rapidly. FPGA attracts more attention compared with other processors for its excellent balance of flexibility and efficiency. There are many FPGAbased CNN accelerators proposed by previous work. However, in previous work the computing resource (especially DSP) is not fully utilized, either explicitly or covertly, which affects the CNN acceleratoru0027s overall performance seriously. In this work, we propose a new formula that provides a more accurate and comprehensive analysis to evaluate computing resource utilization, which can provide guidance for CNN accelerator design optimization. Then we propose a grainadaptive computing structure for FPGAbased CNN acceleration, which can change flexibly to suit to and optimally utilize the available DSP resource. Due to the improvement of DSP utilization, we can achieve a more satisfactory result for both overall throughput performance and power efficiency. This architecture is implemented on Xilinx xcku115 based on AlexNet, the frequency is 150MHz and the peak power consumption is 30.05W. The overall performance is 1292.40 GOPS, 43.01 GOPsW, resulting in 2.28X and 1.94X, 9.44X and 3.02X improvement compared to previous work 6, 9 correspondingly.

PowerAware FPGA Mapping of Convolutional Neural Networks With an unprecedented accuracy in numerous AI tasks, convolutional neural networks (CNNs) are rapidly deployed on powerlimited mobile and embedded applications. Existing mapping approaches focus on achieving high performance without explicit consideration of power consumption, leading to suboptimal solutions when power is considered in a subsequent stage. In this context, there is an emerging need for poweraware methodologies for the design of custom CNN engines. In this work, a methodology is presented for modelling the power consumption of FPGAbased CNN accelerators using a highlevel description of modules, together with a powercentric search strategy for exploring powerperformance tradeoffs within the CNNtoFPGA design space. By integrating into an existing CNNtoFPGA toolflow, the proposed power estimation method can yield a prediction accuracy of 93.4% for total system power consumption. Furthermore, it is demonstrated that the associated poweroriented exploration approach can generate CNN accelerators with a 20.1% power reduction over a purely throughputdriven design for AlexNet, maintaining the designu0027s throughput.