Power optimization for FPRM logic using approximate computing technique A power optimization algorithm based on approximate computing technique was proposed for FPRM logic circuits. The algorithm includes FPRM logic circuits dynamic power estimation model based on signal probability and transition density, a genetic algorithm for RM logic power optimization using polarity searching and error rate (ER) calculation for RM logic using double sharp product operation. Under the constraint of ER, some product terms are selectively deleted to reduce power consumption. The proposed algorithm is implemented in C and tested under MCNC benchmarks. Experimental results show that by using the approximate computing technique, the average dynamic power can be reduced by 22.77% with the average ER of 3.21%.

Area Optimization of MPRM Circuits Using Approximate Computing Approximate computing is a novel paradigm design of Integrated Circuits (ICs). By introducing an acceptable amount of inaccuracy, the area, power, and delay of a circuit can be significantly reduced. In this paper, an approximate logic synthesis (ALS) method target for circuit area optimization is proposed for mixedpolarity ReedMuller (MPRM) circuits. The proposed algorithm mainly consists of the method of the error rate(ER) computing of ReedMuller (RM) functions using disjointed products and the approach of the approximate MPRM functions searching for more compacted forms under the given error rate constraint. The experiments on benchmarks showed that our method is better than those which only use bitwise operation without introducing any errors to the functions. And by using the proposed algorithm, the average circuitsu0027 area can be reduced by 49.71% with the average error rate of 1.73%. Furthermore, it can work fast and it is more efficient for large functions.