High Parallel VLSI Architecture Design of BPC in JPEG2000 Embedded block coding with optimized truncation (EBCOT) is the most computationally intensive part of JPEG2000 image coding standard. In order to improve the encoding efficiency, in this paper, we design a high parallel VLSI architecture of bit plane coding (BPC). Based on this proposed architecture, each encoding pass and each bit plane are encoded in parallel. Moreover, this proposed BPC can be connected with multiple MQ encoders during a coding session, which increase the encoding throughput furthermore. Logic synthesis results based on SIMC 0.25xc2xb5m technology library and the throughput analysis results based on several standard test images show that the proposed architecture can work at a higher frequency and complete the encoding process with lower clock cycles compared with the available designs.

VHDL design for hardware assistance of fractal image compression Fractal image compression has several useful properties, including resolution independence, high compression ratios, rapid decoding, and subjectively good image quality. Despite this, its adoption has been limited, largely because of the very high computational burden of compression. In this paper, an original ASIC design is described which performs the comparisons required for fractal image compression of grayscale images. The design is based around a pipeline of many individual block comparison units through which the set of domain blocks are propagated. Each unit performs the required comparisons between a single range block and the series of domain blocks, and stores the best possible match. The ASIC is designed using synthesizable VHDL, allowing it to be targeted to virtually any digital technology. The small portions of the design which are specific to a particular application or technology, such as the bus interfaces and memory blocks, have been kept separate from the applicationindependent portions of the design. Simulations of the design suggests that an actual hardware implementation would be about one thousand times faster than a general purpose microprocessor based on similar IC technology, reducing the time required to optimally compress a 256 x 256 image using 8 xc3x97 8 range blocks from a few minutes to a fraction of a second.