Design and implementation of Serial ATA pbysical layer on FPGA An increasing number of highperformance computing system developed on FPGA devices need access to mass storage devices for storing data, the serial ATA protocol is widely used in the modern computer systems for transferring data between the host and hard disks or solidstate drives. This paper describes the design and implementation of serial ATA physical layer core based on the Xilinx GTX transceiver. With the method of cyclically changing the GTX line rate, the SATA hard disk with different line rate can be automatically identified and linked, realizing backward compatibility. An embedded system has also been developed for validating the functionality of our SATA physical layer core. We test our physical layer core with connecting our core to both SATA3 and SATA2 hard disks. The experimental result has indicated our core can not only provide the whole functionality required by the SATA physical layer, but also utilize very few logic resources on FPGA.

Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture In this paper, the hardware implementation of a burst error channel and a burst erasure channel simulator in Cyclone II Field Programmable Gate Array (FPGA) is proposed. In telecommunication, a burst error channel is a data transmission channel in which errors occur in a contiguous sequence of symbols, such that the first and last symbols are in error and there exists no contiguous subsequence of m correctly received symbols within the error burst. An erasure channel is one in which each transmitted symbol is either received correctly or is corrupted so badly as to be considered erased. When the erasures are clustered together we refer to the channel as a burst erasure channel. Although software simulations are easy to set up to simulate a transmission channel behavior, they are very time consuming. In order to speed up the communication system performance evaluation process and the final parameter optimization design, direct hardware emulation is proposed and presented. The implementation can be easily extended to other FPGA architectures.