A Simple Steady Timing Resilient Sample Based on Delay Data Sense Detection The performance and reliability of integrated circuits are susceptible to PVTA variations. Conventional designs reserve certain timing margin and consider the worstcase to avoid these side effects. Timing resilient circuits can reduce the timing safe margin with the cost of excessive energy overhead and an unsteady state under a low voltage. In this study, we exploit a simple steady timing resilient sample by expanding previous works to save considerable extra power overhead. This sample executes timing errors detection based on the delay data sense detection and is implemented both on latches and data strobe flipflops to recover errors with merely four extra transistors. The effectiveness and efficiency are evaluated by the design of a systolic array CNN accelerator in the 40nm process. Simulation results demonstrate that the accelerator can achieve a stable performance without any accuracy loss, with the voltage scaled to 0.57V.

DNNLibGen: Deep Neural Network Based Fast Library Generator We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is nonlinear, nonmonotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving timetomarket goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required signoff corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a xe2x80x98single modelxe2x80x99 to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed librarygenerator uses a novel intercorner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intracorner model, to generate dense 8x8 delay tables using delays from 10 slewload points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization runtime for early milestones by upto 60%.