Design of Asynchronous High Throughput SHA256 Hardware Accelerator in 40nm CMOS One of the major issues in implementation of hash functions algorithm is how to decrease the critical path delay and required area effectively. How to expand flexibility, generality and integrity are also important issues as well. As more information are stored and processed on the generalpurpose microcontroller in the edge of internet of things (IoT), more efficient data encryption must be ensured. Before encryption of large data sets, it is preferred that the encryption is adapt to asynchronous operation for different volume and arrival data rate. In this paper, an asynchronous SHA256 hardware accelerator with 32 computation clock cycles for each block is proposed and is at liberty to buffer intermediate hash values, which provides high throughput, robust transmission, adjustable computation frequency and is also easily integrated to microcontroller. The proposed design was implemented in SMIC 40nm technology and performed simulation and verification with Synopsys VCS. The results of postsynthesis simulation show the throughput up to 3.6Gbps.

Crypto Accelerators for PowerEfficient and RealTime onChip Implementation of Secure Algorithms The demand for data exchange is ever growing. Internet of Things (IoT), industry 4.0, smart city and nextgeneration interconnected vehicles are some examples of scenarios in which a high volume of nodes share data across networks. Hence, the data protection plays a fundamental aspect to avoid disclosure or manipulation of sensitive information and disruption of services, particularly in safety critical applications. On the other hand, also the compute power at disposal of possible attackers and hackers is growing, and nextfuture postquantum capabilities will require the usage of longer keys, certificates and digital signatures, to preserve the security level offered by cryptographic functions. This will affect not only the amount of exchange data, but also the computational resources to secure data, increasing processing time, latencies and power consumption, and lowering data rates. In this work, we investigate different implementation strategies to overcome such performance limitations. This work provides a comparison among pure software approach (both on 32b and 64b processors) and hardwarebased solutions we developed for FPGA and ASIC SystemonChip platforms, for the most common symmetrickey and publickey cryptographic algorithms. The proposed hardware accelerators feature one order of magnitude higher throughput (and lower latency) and more than two orders lower power consumption than their software counterparts. A highly configurable cryptographic suite is proposed that can be customized according to the application requirements and thus able to increase as much as possible the efficiency in terms of energy per enciphered bits per second.