Balance of memory footprint and runtime for highdensity routing in largescale FPGAs The scale of modern FPGAs is expanding and applications on FPGA are becoming more and more complex. Applications requiring highdensity routing in largescale FPGA determine that CAD tools not only require large memory consumption, but also require long routing runtime. This paper proposes a method to describe the regularity of interconnect resources in CBSB structure, and then applies a twolevel template method to store the routing resource graph (RRG) which describes the detailed FPGA interconnect resources. This algorithm fully considers the high regularity of interconnect resources in largescale FPGAs with CBSB structure, memory footprint could be reduced. At the same time, RRG created by this method does not affect the routing search space, thus routing runtime will not change significantly. Implementation of the algorithm on VPR platform shows a memory reduction of 1.83X could be achieved at a routing runtime penalty of 1.07X.

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures Following the rapid growth of Field Programmable Gate Arrays (FPGAs) sizes, the regularity of architectures has become a critical feature, leading to the development of millionofLUT devices. While the routing architecture plays a dominant role in the area, delay and power of modern FPGAs, most of previously published works focus on improving the routability and performance of FPGAs while very few studied tileable (highlyregular) routing architectures. In this paper, we provide a detailed analysis between tileable and popular nontileable FPGAs considering modern routing architectures. First, we upgrade VPR to generate tileable routing architecture, which can support different switch block patterns for (1) the routing tracks that startend in a tile and (2) the routing tracks that pass through a tile. Then, we evaluate the performance of mixed switch blocks patterns in the context of a Stratix IVlike FPGA architecture, by considering the most representative patterns, i.e., Subset, Universal and Wilton. Experimental results show that averaged over the MCNC and VTR benchmarks, when compared to the welloptimized nontileable architectures, the tileable architectures can improve the minimum routable channel width by 13% and areadelay product by 2%. In particular, our results showed that in the context of tileable FPGA, a mix of Universal and Wilton switch block patterns lead to the best tradeoff in area, delay and routability, while Wilton switch block was the best choice in nontileable FPGAs.