A FT Trimming Circuit Based on EPROM and Pin Multiplexing A Final Test (FT) trimming circuit with 4x8 bit singlelayer polysilicon EPROM and Pin multiplexing is presented in this paper. The main part of the proposed circuit consists of Pin multiplexing circuit, power circuit of IP core, IIC logic and EPROM. The onetime programmable IP core is designed and implemented by IIC bus drive technology and FT trimming technology so as to achieve chip trimming and functional mode differentiation. The trimming circuit can effectively increase the programmability of the chip so as to reduce the influence of process offset and fluctuation, improving the yield and reliability of the chip. The proposed circuit has been successfully applied to a Liion battery protection integrated circuits (ICs) with a 0.18xcexbc  m  BCD process. The experimental results verify the reliability of the circuit and meet the performance requirements of circuit design.

OnChip Power Stage and Gate Driver for Fast Switching Applications The demand for lowcost integrated circuits for automotive applications is increasing, while their cost must remain low to keep the product competitive. In this scenario, a highspeed monolithic integrated circuit to control a load current is here proposed. It is composed by a level shifter and a gate driver for a high power switch in a DCDC Buck converter to be realized in a low cost technology. For chip area reduction, an nchannel vertical power transistor is chosen as power transistor. High switching frequency (up to 1MHz) can be used to reduce external components size. The device is optimized to achieve 94.4% efficiency. Implementation concept, schematic and layout will be shown.