A Precise BlockBased Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines The impact of process variations on timing has become significant in advanced technology nodes. In this paper, a multivariate adaptive regression splines (MARS) delay model is proposed that considers both global and local process variations to characterize this impact more accurately. In order to obtain MAX operation results, the first three moments of MARS gate delay distribution are calculated, converting the timing distribution to a skewnormal representation. Eventually, based on an approximation MAX operation, the blockbased SSTA propagates the arrival time through the timing diagram. Tested with 10 ISCAS85 benchmark circuits, the average mean squared error and standard deviation error of the path delay calculation are 0.52% and 0.88%.

DNNLibGen: Deep Neural Network Based Fast Library Generator We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is nonlinear, nonmonotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving timetomarket goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required signoff corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a xe2x80x98single modelxe2x80x99 to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed librarygenerator uses a novel intercorner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intracorner model, to generate dense 8x8 delay tables using delays from 10 slewload points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization runtime for early milestones by upto 60%.