A CMOS Random Number Generator with NoiseCoupled VoltageControlled Oscillators This paper presents a hardware random number generator (RNG) based on oscillator circuitry. A reference circuit generates a bias voltage for controlling the frequencies of ring oscillators. Noise is coupled to the bias voltage so that manifest timing jitters are formed at the oscillator outputs. The outputs are multiplexed to a chaotic signal which is subsequently sampled by a faster clock for generating a random bit stream. The RNG circuit is verified by using standard 0.35xcexbcm CMOS process. The quality of the randomness is evaluated by using the NIST statistical tests. The circuit requires 0.089nJ for generating a random bit with chip area of 0.049mm2.

A Robust Random Number Generator Based on Chaotic Ring Oscillators A robust chaosbased random number generator (RNG) system is newly proposed. Output bitstreams generated from this new RNG system is tested on NIST80022 test suite. Proposed RNG circuit fulfill all fifteen randomness tests of NIST80022 without undergoing any postprocessing implementations except for the X OR operation. While classical ring oscillator based RNG systems needs at least 25 rings, each of them containing 13 inverters, and 25 D flipflops to pass all the tests, newly designed RNG system pass all the tests successfully with 10 chaotic new subcells containing 20 ring oscillators with 13 inverters and each subcell includes two resistors, a capacitor and two diodes. These are enough for the new system to generate sufficient randomness without any D flipflops. Experimental results are demonstrated and comparisons are made among the new design, classical ring oscillator based RNGs and another chaotic ring oscillator based RNG. Noise analysis of the new RNG is also performed to show that the system has a nondeterministic entropy source which secures the system against possible synchronization attacks.