LowDropout Regulator design with a simple structure for good high frequency PSRR performance based on Bandgap Circuit This paper describes an opamp free lowdropout regulator with a high PSRR over a broad frequency range. The design merges the high PSRR bandgap and LDO without opamp involved and thus greatly reduces the silicon area. As no high impedence node engaged in the circuit, it is easy to achieve a good high frequency PSRR performance by using a locally regulated supply voltage. The opamp free LDO is then developed by embedding replica technique in the bandgap. The circuit is evaluated with HHGrace 0.35xc2xb5m CMOS technology. It generates a reference voltage of 1.152V and has a temperature coefficient of 0.01mVK at 27C. LDO has a PSRR of xe2x88x9296dB at DC and still xe2x88x9248.5dB at 1MHz.

A PowerAreaEfficient LowDropout Regulator With Enhanced Buffer Impedance Attenuation This paper proposed a lowdropout regulator (LDO) with a dynamicbiasing super buffer technique and a 2stage error amplifier (EA). The 2stage EA provides a high loop gain and wide output swing so as to implement an ultra small load regulation and line regulation. The dynamicbiasing super buffer technique, made of super source follower, ultra lowoutput impedance buffer and dynamic biasing technique, ensures the stability of the LDO with a 1xc2xb5F output capacitance and adjusts the quiescent current (Iq) of the LDO in different load current so that an ultra low I q  is achieved by the proposed LDO structure. Based on Global Foundry 0.18xc2xb5m CMOS process, the circuit can drive up to 200mA load current at 1.2V output voltage in 1.4V 2V supply voltage (Vs). In 1.4Vs, Iq is 26.3xc2xb5A in no load and 57.7xc2xb5A in full load. In 2Vs, Iq is 26.4xc2xb5A in no load and 246.2xc2xb5A in full load. The load regulation is 1.12xc2xb5VmA in 1.4Vs and the line regulation is 0.50mVV in 200mA full load.