A ComparatorReused DynamicAmplifier for NoiseShaping SAR ADC This paper presents a highspeed highgain dynamic amplifier which can also be reused as a comparator for a noiseshaping (NS) successiveapproximationregister (SAR) analogtodigital converter (ADC). By modifying a strongarm latch, this dynamic amplifier can achieve a high speed of comparison and dynamic amplification, which is crucial to a highperformance NS SAR ADC. The prototype is designed in 28 nm CMOS process. It realizes the comparison speed of 0.2 ns and 8 times dynamic amplification in 0.9 ns with 0.6 pF singleend capacitance load. Meanwhile, the noise floor is 11 nVxe2x88x9aHz and the THD is 76.5 dB with the power consumption of 56 xc2xb5W averagely.

A 10b 250MSs SAR ADC with SpeedEnhanced SAR Logic and Free Time More Than a Half of Sampling Period A 10b SAR ADC which can be used as the last stage in a highspeed and highresolution pipelinedSAR ADC is proposed. With the presented highspeed SAR logic, more than half of time in a sampling period is unused, which is a benefit for other stages in pipelinedSAR ADC with tighter timing. A unit capacitor with low parasitic effect is also presented. Together with redundancy and carefully placement in layout, the linearity of CDAC is improved. The noise of highspeed comparator is decreased because of the enlarged size in the input MOSFETs. The prototype ADC is implemented in UMC 28nm process. At 250MSs and 1.05V supply, the ADC consumes 3.23mW and achieves 9.34b ENOB with an SFDR of 79.9 dB and an SNDR of 58.0 dB. The FoM w  is 22.46 fJconv.step.