Reconfigurable RF Power Amplifier in 5G4G with RFSOI CMOS The modern communication technology, due to the everincreasing demands from the both industries and consumers, has been advanced with an astonishing speed. Although the 4G technology has just been fully embraced by the consumers, 5G technology is already at their door step. Since 5G system is putting even more stringent demands on both device and circuit, new concepts and ideas are needed at device, circuit and module integration levels. This paper will introduce a reconfigurable architecture to the RF power amplifierfrontendmodule design for both 4G and 5G applications. The reconfigurable architecture, by taking advantages of RFSOI CMOS, is not only suitable for wideband operation, but also adaptive to complicated operational modes which is essential for 5G applications. In addition, the reconfigurable architecture also provides tremendous advantages in both size reduction and cost saving.

New Design Opportunities exploiting FDSOI technology for RF Power Amplifier and LNA design To demonstrate the capacity of FullyDepleted SiliconOnInsulator (FDSOI) technology, this paper presents two radio frequency designs taking benefit of the key advantages of the FDSOI. Specific process opportunities and body biasing are used to simultaneously reduce silicon area and improve radio frequency performance. First, a WiFi Power Amplifier (PA) fabricated in 28nm UTBB FDSOI process with 1.8v thick oxide MOS is presented. This PA exhibits a 23dBm Psat output power and l8dBm, 8% PAE under low distortion with a 3.7v power supply. This makes this PA suitable for 802.11ac WiFi standard requirements. Then an Ultra Low Power (ULP) inductorless Low Noise Amplifier (LNA) is presented using the same 28nm UTBB FDSOI technology. Based on a boosted common gate architecture, this LNA has been implemented reaching 16dB of voltage gain (G v ), 7.3dB Noise Figure (NF) for a total power consumption of only 300xc2xb5W under 0.6v power supply. This structure points out the potential of back biasing to reduce the power consumption of more than 30% compared to classical CMOS design with similar RF performances.