Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling Capacitance With scaling down of CMOS circuit technology, the size of CMOS metal interconnect line is getting thinner. After researching of the linetoline coupling capacitance and line crosstalk mechanism, a crosstalk gate circuit design scheme based on interconnect coupling capacitance is proposed. Firstly, the influence factors of the coupling capacitance among the mental lines are analyzed. Then, the gate capacitance of the CMOS transistor is used to simulate the coupling capacitance among the interconnection lines. Finally, the NAND gate circuit is designed based on the interconnect crosstalk logic. Under the TSMC 65nm technology, the SPECTRE simulation result shows that the crosstalk gate logic function is correct.

Design of HVCMOS Detectors in BCD Technology with Noise and Crosstalk Measurements This paper presents the design and implementation of a particle detector in a BipolarCMOSDMOS (BCD) 180 nm technology. The design has a substrate potential of xe2x80x94 50 V and supply voltage of 1.8 V. Size of the unit pixel sensor is  250times 50 mumathbfm2 . The chip consists of an array of  47times 6  pixels including the signal processing circuitry. The total chip area is  3.3 times 4.4 mathbfmm2 . The complete signal processing circuitry is hosted inside the diode sensor to achieve 100% fill factor. The chip consists of 106 inputoutput pads, including the pads for supplies viz. xe2x80x94 50 V, 0 V and 1.8 V. The measurement results are presented to validate the noise and crosstalk models of the designed detector. The comparison shows an average mismatch of 2.65  mumathbfV  for the crosstalk voltages in a range of 3000 to 7000 injected electrons. The circuit noise has an average mismatch of  1.23times 1010 mathbfV2mathbfHz  between the analytical and the measurement results for a frequency range of 100 kHz to 22 MHz. The analog processing circuitry provides a measured voltage gain of 33.3 dB at 100 kHz of input frequency.