An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit SM2 public key cryptography, proposed by China, is widely used to ensure the security in communication. In this paper, based on the module arithmetic logic unit, SM3 unit, verify unit and XOR unit, we implemented a dualfield processor over SM2 public key cryptography, which can complete digital signature, verification, information encryption and decryption. In addition, the SM2 processor is described by Verilog HDL, and synthesized in CMOS 55nm process. Experimental results show that the SM2 processor runs at high frequency of 476 MHz with area of 245K gates. Whatu0027s more, the processor requires only 0.56ms to compute a 256bit point multiplication in GF(p), and 0.59ms in GF(2m).

Crypto Accelerators for PowerEfficient and RealTime onChip Implementation of Secure Algorithms The demand for data exchange is ever growing. Internet of Things (IoT), industry 4.0, smart city and nextgeneration interconnected vehicles are some examples of scenarios in which a high volume of nodes share data across networks. Hence, the data protection plays a fundamental aspect to avoid disclosure or manipulation of sensitive information and disruption of services, particularly in safety critical applications. On the other hand, also the compute power at disposal of possible attackers and hackers is growing, and nextfuture postquantum capabilities will require the usage of longer keys, certificates and digital signatures, to preserve the security level offered by cryptographic functions. This will affect not only the amount of exchange data, but also the computational resources to secure data, increasing processing time, latencies and power consumption, and lowering data rates. In this work, we investigate different implementation strategies to overcome such performance limitations. This work provides a comparison among pure software approach (both on 32b and 64b processors) and hardwarebased solutions we developed for FPGA and ASIC SystemonChip platforms, for the most common symmetrickey and publickey cryptographic algorithms. The proposed hardware accelerators feature one order of magnitude higher throughput (and lower latency) and more than two orders lower power consumption than their software counterparts. A highly configurable cryptographic suite is proposed that can be customized according to the application requirements and thus able to increase as much as possible the efficiency in terms of energy per enciphered bits per second.