Patent application EP21156290A (EP), filed 2021-02-10
Publication number: EP3929725A1
Title: METHOD AND APPARATUS PERFORMING OPERATIONS USING CIRCUITS
Abstract: A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.
IPC codes: G06N   3/   063            A I
G06F   7/   544            A I
G06N   3/   065            A I
G11C  11/    54            A I
G11C  13/    00            A I
Claims: number: 1
text: A method of performing a predetermined operation for a circuit that includes a resistor group comprising a plurality of resistors that are connected in series, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between the plurality of resistors, the method comprising:
number: 2
text: The method of claim 1, wherein
the first reference voltage is reduced by a predetermined percentage ratio from a direct current, DC, voltage supplied to the power supply unit, and
the second reference voltage is reduced by 100 minus the predetermined percentage ratio from the DC voltage supplied to the power supply unit.
number: 3
text: The method of claim 1 or 2, wherein the predetermined operation comprises a multiply-accumulate, MAC, operation or calculating a total resistance value of the resistor group, based on the end time.
number: 4
text: The method of claim 3, wherein weighted inputs transmitted between nodes of a neural network is determined by the MAC operation.
number: 5
text: An apparatus comprising a circuit for performing a predetermined operation, the apparatus comprising:
number: 6
text: The apparatus of claim 5, wherein the reference voltage is reduced by a predetermined percentage ratio from a direct current, DC, voltage supplied to the power supply unit.
number: 7
text: The apparatus of claim 5 or 6, wherein the predetermined operation is a multiply-accumulate, MAC, operation or calculation of a total resistance value of the resistor group, based on the time information, and
wherein weighted inputs transmitted between nodes of a neural network is determined by the MAC operation.
number: 8
text: A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, configure the one or more processors to perform a method of performing a predetermined operation for a circuit that includes a resistor group comprising a plurality of resistors that are connected in series, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, a parasitic capacitance existing at each node between the plurality of resistors, the resistor group being divided into a first resistor group and a second resistor group, the first resistor group and the second resistor group being connected in parallel to each other, and a resistor arrangement order of the first resistor group being opposite to a resistor arrangement order of the second resistor group,
the method comprising:
number: 9
text: The non-transitory computer-readable storage medium of claim 8, wherein the reference voltage is reduced by a predetermined percentage ratio from a direct current, DC, voltage supplied to the power supply unit.
number: 10
text: The non-transitory computer-readable storage medium of claim 8 or 9, wherein the predetermined operation comprises a multiply-accumulate, MAC, operation or calculating a total resistance value of the resistor group, based on the end time.
number: 11
text: The non-transitory computer-readable storage medium of claim 10, wherein weighted inputs transmitted between nodes of a neural network is determined by the MAC operation.
number: 12
text: An apparatus for performing a predetermined operation for a circuit, the apparatus comprising:
number: 13
text: The apparatus of claim 12, wherein
the first reference voltage is reduced by a predetermined percentage ratio from a direct current, DC, voltage supplied to the power supply unit, and
the second reference voltage is reduced by 100 minus the predetermined percentage ratio from the DC voltage supplied to the power supply unit.
number: 14
text: The apparatus of claim 12 or 13, wherein the predetermined operation is a multiply-accumulate, MAC, operation or calculation of a total resistance value of the resistor group, based on the second time information.
number: 15
text: The apparatus of claim 14, wherein weighted inputs transmitted between nodes of a neural network is determined by the MAC operation.
Office action: search_report, dated 2021-12-29
Prior art cited: ref_id: WO2020075272A1
ref_type: patent
severity: background
ref_id: - BAVANDPOUR MOHAMMAD: "Toward Efficient Mixed-Signal Neural Processors Using Non-Volatile Memory Devices", 1 March 2020 (2020-03-01), XP055822059, Retrieved from the Internet <URL:https://escholarship.org/content/qt3548k39r/qt3548k39r.pdf> [retrieved on 20210707]
ref_type: npl
severity: background
ref_id: WO2020075272
ref_type: patent
severity: background
ref_id: - Bavandpour Mohammad, "Toward Efficient Mixed-Signal Neural Processors Using Non-Volatile Memory Devices", (20200301), URL: https://escholarship.org/content/qt3548k39r/qt3548k39r.pdf, (20210707), XP055822059 [A] 1-15 * the whole document *
ref_type: npl
severity: background
Final disposition: pending (2021-12-29)