Patent application EP20215320A (EP), filed 2020-12-18
Publication number: EP3920068A1
Title: DATA PROTECTION WITH DYNAMIC RESOURCE ISOLATION FOR DATA PROCESSING ACCELERATORS
Abstract: Embodiments of the disclosure discloses a method and system of a virtualization environment for a data processing (DP) accelerator. In one embodiment, a data processing (DP) accelerator includes a resource management unit and one or more dynamically isolated resources managed by the resource management unit. The DP accelerator includes one or more virtual functions (VFs) each associated with one of the one or more dynamically isolated resources, where a virtual machine (VM) of a host is assigned one of the one or more VFs to access the dynamically isolated resources associated with the assigned VF, and where the VM has no access to the rest of the one or more dynamically isolated resources.
IPC codes: G06F  21/    60            A I
G06F   9/   455            A I
G06F   9/    50            A I
G06N  20/    00            A I
H04L  29/    06            A I
Claims: number: 1
text: A data processing, DP, accelerator (107), comprising:
number: 2
text: The DP accelerator (107) of claim 1, wherein the DP accelerator (107) includes a single root input output virtualization, SR-IOV, pass through device.
number: 3
text: The DP accelerator (107) of claim 1 or 2, wherein the VM (201B) transmits data packets directly to the VF (237) via hardware access to the VF (237) using a VF driver (205B) running on the VM (201B).
number: 4
text: The DP accelerator (107) of any one of claims 1 to 3, wherein the resource management unit (507) includes a table mapping the one or more VFs (237) to the one or more resources (227).
number: 5
text: The DP accelerator (107) of any one of claims 1 to 4, wherein the resources (227) are dynamically configured based on a request size for the resources (227).
number: 6
text: The DP accelerator (107) of any one of claims 1 to 5, wherein the VF (237) transmits data packets to the VM (201B) via a queue for the corresponding VF (237).
number: 7
text: The DP accelerator (107) of any one of claims 1 to 6, wherein the data packets are transmitted from the VF (237) to the VM (201B) via direct memory access, DMA, independent of a processing unit of the host.
number: 8
text: The DP accelerator (107) of any one of claims 1 to 7, wherein a virtual machine manager (209), VMM, of the host assigns VM (201B) of the host to communicate with the VF (237).
number: 9
text: The DP accelerator (107) of any one of claims 1 to 8, wherein data packets are transmitted directly between the VM (201B) and the VF (237) assigned to the VM (201B) without passing through a VMM (209).
number: 10
text: A data processing, DP, system, comprising:
number: 11
text: A computer-implemented method, comprising:
number: 12
text: The computer-implemented method of claim 11, wherein the request includes a request to train an AI model.
number: 13
text: The computer-implemented method of claim 11 or 12, wherein the hardware I/O information of the VF is located at a driver of the VM at a host hosting the application, wherein the DP accelerator preferably includes a single root input output virtualization, SR-IOV, pass through device.
number: 14
text: The computer-implemented method of any one of claims 11 to 13, wherein the VM of the host is initially assigned with the VF by a virtual machine manager, VMM, of the host, wherein data packets are preferably transmitted directly between the VM and the VF assigned to the VM without passing through the VMM.
number: 15
text: The computer-implemented method of any one of claims 11 to 14, wherein data packets are transmitted between the VM and the VF corresponding to the VM via direct memory access, DMA, independent of a processing unit of the host.
Office action: search_report, dated 2021-12-08
Prior art cited: ref_id: WO2018176393A1
ref_type: patent
severity: background
ref_id: US2015370595A1
ref_type: patent
severity: background
ref_id: US2013042240A1
ref_type: patent
severity: background
ref_id: US2019107965A1
ref_type: patent
severity: background
ref_id: - PATRICK  KUTCH: "PCI-SIG SR-IOV Primer An Introduction to SR-IOV Technology Intel ? LAN Access Division", 1 January 2011 (2011-01-01), pages 1 - 28, XP055297475, Retrieved from the Internet <URL:http://www.intel.com/content/dam/doc/application-note/pci-sig-sr-iov-primer-sr-iov-technology-paper.pdf> [retrieved on 20160824]
ref_type: npl
severity: background
ref_id: - JIANPING ZHU ET AL: "Enabling Privacy-Preserving, Compute- and Data-Intensive Computing using Heterogeneous Trusted Execution Environment", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 9 April 2019 (2019-04-09), XP081167169
ref_type: npl
severity: background
ref_id: US2013042240
ref_type: patent
severity: background
ref_id: US2015370595
ref_type: patent
severity: background
ref_id: WO2018176393
ref_type: patent
severity: background
ref_id: US2019107965
ref_type: patent
severity: background
ref_id: - Patrick Kutch, "PCI-SIG SR-IOV Primer An Introduction to SR-IOV Technology Intel ? LAN Access Division", (20110101), pages 1 - 28, URL: http://www.intel.com/content/dam/doc/application-note/pci-sig-sr-iov-primer-sr-iov-technology-paper.pdf, (20160824), XP055297475 [A] 1-15 * pages  13,14,20  - page  21 *
ref_type: npl
severity: background
Final disposition: pending (2021-12-08)