Patent application EP20214184A (EP), filed 2020-12-15
Publication number: EP3920501A1
Title: DATA PROTECTION WITH STATIC RESOURCE PARTITION FOR DATA PROCESSING ACCELERATORS
Abstract: Embodiments of the disclosure disclose a method and system for a virtualization environment for a data processing, DP, accelerator. In one embodiment, a data processing, DP, accelerator includes one or more statically partitioned resources and one or more virtual functions, VFs, each associated with one of the one or more statically partitioned resources. A virtual machine, VM, of a host is assigned one of the one or more VFs to access the statically partitioned resources associated with the assigned VF. The VM has no access to the rest of the one or more statically partitioned resources of the DP accelerator.
IPC codes: H04L  29/    06            A I
G06F  21/    60            A I
G06F   9/    50            A I
G06N  20/    00            A I
H04L   9/    40            A I
Claims: number: 1
text: A data processing, DP, accelerator (105, 106, 107), comprising:
number: 2
text: The DP accelerator of claim 1, further comprising a single root input output virtualization, SR-IOV, pass through device.
number: 3
text: The DP accelerator of claim 1 or 2, wherein the VM (201) transmits data packets directly to the VF (235, 237) via hardware access to the VF (235, 237) using a VF driver (205) running on the VM (201).
number: 4
text: The DP accelerator of any one of claims 1-3, wherein the VF (235, 237) transmits data packets to the VM (201) via an I/O queue (301, 501) for the VF (235, 237).
number: 5
text: The DP accelerator of any one of claims 1-4, wherein a virtual machine manager, VMM, (209) of the host assigns VM (201) of the host to communicate with the VF (235, 237).
number: 6
text: The DP accelerator of claim 5, wherein VMM (209) of the host assigns at most one VF (235, 237) to the VM (201), and wherein if none of the one or more VFs (235, 237) are available for assignment, the VMM (209) waits for a next of the one or more VFs (235, 237) to become available for assignment, or the VMM (209) denies the assignment, or the VMM (209) migrates the VM (201) to another host to be assigned to a VF (235, 237) of the another host.
number: 7
text: The DP accelerator of any one of claims 1-6, wherein data packets are transmitted directly between the VM (201) and the VF (235, 237) assigned to the VM (201) without passing through the VMM (209).
number: 8
text: A data processing, DP, system, comprising:
number: 9
text: A computer-implemented method, comprising:
number: 10
text: The computer-implemented method of claim 9, wherein the instruction is an instruction to train an AI model or to perform an inference based on an AI model.
number: 11
text: The computer-implemented method of claim 9 or 10, wherein the hardware I/O information of the VF (235, 237) is located at a driver of the VM (201) at a host hosting the application running on the VM (201).
number: 12
text: The computer-implemented method of any one of claims 9-11, wherein the DP accelerator (105, 106, 107) includes a SR-IOV pass through device.
number: 13
text: The computer-implemented method of any one of claims 9-12, wherein the VM (201) of the host is initially assigned the VF (235, 237) by a virtual machine manager, VMM, (209) of the host.
number: 14
text: The computer-implemented method of claim 13, wherein data packets are transmitted between the VM (201) and the virtual function corresponding to the VM (201) without passing through the VMM (209).
number: 15
text: The computer-implemented method of any one of claims 9-14, wherein data packets are transmitted between the VM (201) and the VF (235, 237) corresponding to the VM (201) via direct memory access, DMA, independent of a processing unit of the host.
Office action: search_report, dated 2021-12-08
Rejection reasons: novelty_epc_54
Prior art cited: ref_id: WO2018176393A1
ref_type: patent
severity: background
ref_id: US2015370595A1
ref_type: patent
severity: background
ref_id: US2018321985A1
ref_type: patent
severity: background
ref_id: - PATRICK  KUTCH: "PCI-SIG SR-IOV Primer An Introduction to SR-IOV Technology Intel ? LAN Access Division", 1 January 2011 (2011-01-01), pages 1 - 28, XP055297475, Retrieved from the Internet <URL:http://www.intel.com/content/dam/doc/application-note/pci-sig-sr-iov-primer-sr-iov-technology-paper.pdf> [retrieved on 20160824]
ref_type: npl
severity: background
ref_id: US2015370595
ref_type: patent
severity: background
ref_id: WO2018176393
ref_type: patent
severity: novelty_destroying
ref_id: US2018321985
ref_type: patent
severity: background
ref_id: - Patrick Kutch, "PCI-SIG SR-IOV Primer An Introduction to SR-IOV Technology Intel ? LAN Access Division", (20110101), pages 1 - 28, URL: http://www.intel.com/content/dam/doc/application-note/pci-sig-sr-iov-primer-sr-iov-technology-paper.pdf, (20160824), XP055297475 [A] 1-15 * pages  13,14,20  - page  21 *
ref_type: npl
severity: background
Final disposition: pending (2021-12-08)