Patent application EP20209682A (EP), filed 2020-11-25
Publication number: EP3923204A2
Title: NEURAL NETWORK APPARATUS PERFORMING FLOATING-POINT OPERATION AND OPERATING METHOD OF THE SAME
Abstract: [0001]    A neural network apparatus performs multiply-accumulate (MAC) operations with respect to fractions of weights and input activations in a block floating-point format by using an analog crossbar array, performs addition operations with respect to shared exponents of weights and input activations in a block floating-point format by using a digital computing circuit, and outputs a partial sum of floating-point output activations by combining the result of the MAC operations and the result of the addition operations.
IPC codes: G06N   3/   063            A I
G06N   3/    04            A I
Claims: number: 1
text: An operating method of a neural network apparatus performing a floating-point operation, the operating method comprising:
number: 2
text: The operating method of claim 1, further comprising
storing the first fraction corresponding to each of the weights included in the respective weight kernel in memory cells arranged along a column line corresponding to the respective weight kernel among a plurality of column lines of the analog crossbar array; and
inputting the second fraction corresponding to each of the input activations included in the respective input stripe to a plurality of row lines of the analog crossbar array.
number: 3
text: The operating method of claim 2, further comprising, in a case in which the analog crossbar array supports a signed input, inputting a sign bit of the second block floating-point input activation to the plurality of row lines together with the second fraction.
number: 4
text: The operating method of claim 2 or 3, further comprising:
number: 5
text: The operating method of claim 4, further comprising:
number: 6
text: The operating method of claim 4 or 5, further comprising:
number: 7
text: The operating method of claim 2,
in a case in which the analog crossbar array supports signed weights, storing the first fraction comprises:
storing a sign bit of a weight of the first block floating-point format in the memory cells together with the first fraction.
number: 8
text: The operating method of claim 2, further comprising:
number: 9
text: The operating method of claim 1, wherein the outputting the partial sum comprises:
number: 10
text: The operating method of claim 9, further comprising:
number: 11
text: A neural network apparatus comprising:
number: 12
text: The neural network apparatus of claim 11, wherein the first shared exponent is a maximum value among existing exponents of the weights.
number: 13
text: The neural network apparatus of claim 11 or 12, wherein the in-memory computing circuit comprises an analog crossbar array configured to perform the MAC operations and an analog-digital converter, ADC, configured to convert the result of the MAC operations into the digital signal.
number: 14
text: The neural network apparatus of one of claims 11 to 13, further comprising an accumulator configured to combine first digital signals corresponding to positive input activations and second digital signals corresponding to negative input activations.
number: 15
text: The neural network apparatus of claim 14, wherein the accumulator is an analog accumulator included in the in-memory computing circuit, or
wherein the accumulator is a digital accumulator included in the digital computing circuit.
Office action: search_report, dated 2021-12-15
Rejection reasons: novelty_epc_54
inventive_step_epc_56
Prior art cited: ref_id: EP3267355
ref_type: patent
severity: obviousness
ref_id: US2018157465
ref_type: patent
severity: novelty_destroying
ref_id: US2019042199
ref_type: patent
severity: background
ref_id: US2019205741
ref_type: patent
severity: obviousness
ref_id: - ATHREYAS NIHAR ET AL, "Memristor-CMOS Analog Co-Processor for Acceleration of High Performance Computing Applications", 2018 INTERNATIONAL CONFERENCE ON CURRENT TRENDS TOWARDS CONVERGING TECHNOLOGIES (ICCTCT), IEEE, (20180301), doi:10.1109/ICCTCT.2018.8551115, pages 1 - 7, XP033458142 [Y] 1-3,5-9,13,15 * abstract; figure 1 * * sections I. and II. *
ref_type: npl
severity: obviousness
Final disposition: pending (2021-12-15)