Patent application EP19180963A (EP), filed 2019-06-18
Publication number: EP3754367A1
Title: CIRCUIT AND METHOD FOR COMBINING SPAD OUTPUTS
Abstract: The present disclosure relates to a combining network for an array of SPAD (single-photon avalanche diode) devices, the combining network comprising: a plurality of synchronous sampling circuits (602), each synchronous sampling circuit being coupled to the output of a corresponding SPAD device (104) and being configured to generate a pulse or an edge each time an event is detected; and a summation circuit (604) coupled to an output of each of the synchronous sampling circuits and configured to count the number of pulses or edges to generate a binary output value (SST).
IPC codes: G01S  17/    10            A I
G01S  17/    32            A I
G01S   7/  4863            A I
G01S   7/  4865            A I
G01S   7/  4914            A I
G01S   7/  4915            A I
H01L  27/   144            A I
H03K   5/  1534            A I
Claims: number: 1
text: A combining network for an array of SPAD (single-photon avalanche diode) devices, the combining network comprising:
number: 2
text: The combining network of claim 1, wherein the summation circuit (604) comprises an adder tree (1400) configured to convert an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log<2>N or L=log<2>N+1.
number: 3
text: The combining network of claim 1 or 2, wherein each of the plurality of synchronous sampling circuits (602, 902) comprises a flip-flop (602, 1002) having its data input (D) coupled to the output of the corresponding SPAD device (104), the flip-flops (602, 1002) being clocked by a clock signal (CLK).
number: 4
text: The combining network of claim 3, wherein the event is in the form of a pulse of a first duration (tp) on the output of the corresponding SPAD device (104), and the clock signal (CLK) has a period of less than half the first duration.
number: 5
text: The combining network of claim 1 or 2, wherein each of the plurality of synchronous sampling circuits (602, 902) comprises an edge detection device (902) configured to detect an edge of a pulse generated by the corresponding SPAD device (104).
number: 6
text: The combining network of claim 5, wherein each edge detection device (902) comprises:
number: 7
text: A ranging device comprising:
number: 8
text: A method of detecting events in a SPAD (single-photon avalanche diode) array (102), the method comprising:
number: 9
text: The method of claim 8, further comprising converting, using an adder tree (1400) of the summation circuit (604), an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log<2>N or L=log<2>N+1.
number: 10
text: The method of claim 8 or 9, wherein generating the pulse or edge each time an event is detected at an output of the corresponding SPAD device comprises sampling, using a flip-flop (602, 1002), the output of the corresponding SPAD device (104) based on a clock signal (CLK).
Office action: search_report, dated 2020-12-23
Rejection reasons: novelty_epc_54
inventive_step_epc_56
Prior art cited: ref_id: US2018372538A1
ref_type: patent
severity: background
ref_id: [XAY]     - ALMER OSCAR ET AL: "From linear to geiger mode avalanche detectors for ADC-less VLC receiver architectures", 2017 IEEE PHOTONICS CONFERENCE (IPC), IEEE, 1 October 2017 (2017-10-01), pages 31 - 32, XP033261575, DOI: 10.1109/IPCON.2017.8115992
ref_type: npl
severity: background
ref_id: US2018372538
ref_type: patent
severity: novelty_destroying
ref_id: - ALMER OSCAR ET AL, "From linear to geiger mode avalanche detectors for ADC-less VLC receiver architectures", 2017 IEEE PHOTONICS CONFERENCE (IPC), IEEE, (20171001), doi:10.1109/IPCON.2017.8115992, pages 31 - 32, XP033261575 [X] 1,2,5,8-10 * chapter II * * figures 1(a), 1(b) * [A] 3,4,6,7 [Y] 2,9
ref_type: npl
severity: novelty_destroying
Final disposition: pending (2020-12-23)