Patent application EP18172000A (EP), filed 2018-05-14
Publication number: EP3407633A1
Title: A METHOD OF MANAGING INTEGRATED CIRCUIT CARDS, CORRESPONDING CARD AND APPARATUS
Abstract: Integrated circuit cards such as UICC's or eUICC's in mobile communication equipment including memory space locations for storing user profile data of plural user profiles (PI, P2, .., PN) are managed by: - partitioning the memory space (PH) in segments (Segment 1, ..., Segment N) of memory space locations, - providing a segment map (SM) including segment map memory locations with the memory space locations in the memory space (PH) coupled to respective segment map memory locations in the segment map (SM), - allocating the memory space locations in the memory space (PH) to the user profile data by recording in the respective segment map memory locations in the segment map (SM) one profile in the plurality of user profiles (PI, P2, .., PN) to which the memory space locations in the memory space (PH) are reserved.
IPC codes: H04W  12/    00            A I
H04W   4/    00            A I
H04W   4/    60            A I
G06F   3/    06            A I
H04W   8/    18            A I
Claims: number: 1
text: A method, including:
number: 2
text: The method of claim 1, including partitioning the memory space (PH) in segments with a flash page memory granularity.
number: 3
text: The method of claim 1 or claim 2 wherein the segment map memory locations in the segment map (SM) have one byte size.
number: 4
text: The method of any of the previous claims, including writing in the memory space locations in the memory space (PH) reserved to a certain one of said user profiles (P1, P2, .., PN) only user profile data pertaining to said certain one of said user profiles (P1, P2, ..., PN) .
number: 5
text: The method of any of the previous claims, wherein the segments of the memory space locations (PH) include respective sets of memory blocks, the method including maintaining the allocations of the segments of memory space locations in the memory space (PH) to a certain one of said user profiles (P1, P2,..., PN) until all the blocks therein are deleted.
number: 6
text: The method of any of the previous claims, wherein the segments of the memory space locations in the memory space (PH) include respective sets of memory blocks, wherein the method includes allocating the blocks in one segment of memory locations in the memory space (PH) or in a plurality of adjacent segments of memory space locations in the memory space (PH) which are either reserved to a certain one of said user profiles (P1, P2, .. PN) or empty.
number: 7
text: The method of any of the previous claims, including allocating the memory space locations in the memory space (PH) to the user profile data of the plurality of user profiles (P1, P2,.., PN) with avoidance of writes in the segment map (SM) as a target.
number: 8
text: The method of any of the previous claims, including:
number: 9
text: An integrated circuit card including:
number: 10
text: Apparatus (UE) for use according to a plurality of user profiles (P1, P2, .., PN), the apparatus including an integrated circuit card (10) according to claim 9.
number: 11
text: Apparatus (UE) according to claim 10, including an operating system configured for managing the integrated circuit card (10) with the method of one of claims 1 to 8.
number: 12
text: Apparatus according to claim 10 or claim 11, the apparatus including a mobile communications apparatus (UE).
Office action: search_report, dated 2018-11-28
Prior art cited: ref_id: US2014308991A1
ref_type: patent
severity: background
ref_id: WO9420906A1
ref_type: patent
severity: background
ref_id: US2010185874A1
ref_type: patent
severity: background
ref_id: EP3099045A1
ref_type: patent
severity: background
ref_id: - ERAN GAL ET AL: "Algorithms and data structures for flash memories", ACM COMPUTING SURVEYS, ACM, NEW YORK, NY, US, US, vol. 37, no. 2, 1 June 2005 (2005-06-01), pages 138 - 163, XP058219316, ISSN: 0360-0300, DOI: 10.1145/1089733.1089735
ref_type: npl
severity: background
ref_id: WO9420906
ref_type: patent
severity: background
ref_id: US2010185874
ref_type: patent
severity: background
ref_id: US2014308991
ref_type: patent
severity: background
ref_id: EP3099045
ref_type: patent
severity: background
ref_id: - ERAN GAL ET AL, "Algorithms and data structures for flash memories", ACM COMPUTING SURVEYS, ACM, NEW YORK, NY, US, US, (20050601), vol. 37, no. 2, doi:10.1145/1089733.1089735, ISSN 0360-0300, pages 138 - 163, XP058219316 [A] 1-12 * Abstract Sections 1 and 2 *
ref_type: npl
severity: background
Final disposition: pending (2018-11-28)