Patent application EP17173986A (EP), filed 2017-06-01
Publication number: EP3252594A1
Title: SYSTEM AND METHODS FOR GENERATING CODE FROM EXECUTABLE MODELS WITH FLOATING POINT DATA
Abstract: Many programmable devices do not include Floating Point Units (FPUs). As a result, before generating code for such devices, the model may need to be converted from using floating point data types to using only integer and/or fixed-point data types. This can be a time-consuming and error prone process. In addition, the designer may not know the particular programmable device onto which the generated code is to be deployed.  System and methods are presented for generating code for a model, the model comprising at least one substructure, wherein the at least one substructure comprises an operator to operate on one or more inputs, at least one of the one more inputs having a floating point data type, the method comprising: interpreting at least one of the one or more first inputs as a sign, a mantissa, and an exponent, and generating instructions for the model, the generated instructions comprising: instructions for the one of the one or more inputs, wherein the instructions comprise variables representing the sign, the mantissa, and/or the exponent; and instructions for a function that performs functionalities on the variables when the instructions are executed, the function having equivalent behaviour as the operator operating on the one or more inputs.
IPC codes: G06F  17/    50            A I
G06F   7/   483            A I
G06F   9/    44            A I
H03M   7/    24            A I
Claims: number: 1
text: A method for generating code for a model, the model comprising at least one substructure, wherein the at least one substructure comprises an operator to operate on one or more inputs, at least one of the one more inputs having a floating point data type, the method comprising:
number: 2
text: The method according to claim 1, wherein the method further comprises receiving at least one design objective and/or constraint, the at least one design objective and/or constraint imposing constraints on code generated from the model;
number: 3
text: The method according to any of the preceding claims, in particular according to claim 2, wherein the method further comprises determining that code generated for the at least one substructure violates an/the at least one design objective.
number: 4
text: The method according to any of the previous claims, wherein the at least one design objective comprises hardware performance constraints, including:
number: 5
text: The method according to any of the previous claims, wherein the method further comprises:
number: 6
text: The method according to any of the previous claims, wherein the generated code comprises C code, C++ code, HDL code, VHDL code Verilog, System Verilog, PLC code, assembly code or executable binary code.
number: 7
text: The method according to any of the previous claims, wherein the operator is a multiplication of at least two inputs, wherein the instructions for the function comprise instructions for:
number: 8
text: The method according to any of the previous claims, wherein the one or more inputs are interpreted based on IEEE standard 754.
number: 9
text: The method according to any of the previous claims, further comprising:
number: 10
text: The method according to claim 9, wherein compiling generates executable code from an instruction set for an architecture without a Floating Point Unit (FPU).
number: 11
text: The method of claim 9 or 10, wherein compiling generates executable code for programmable hardware or embedded hardware comprises integer-only micro controllers, FPGA (field-programmable gate array) units without floating point cores, or PLC units without floating point support.
number: 12
text: A computer-readable medium storing instructions that when executed by at least one processor cause the at least one processor to implement a method according to any of the previous claims.
number: 13
text: A data processing apparatus for generating code for a model, the model comprising at least one substructure, wherein the at least one substructure comprises an operator to operate on one or more inputs, at least one of the one more inputs having a floating point data type, the apparatus in particular for carrying out the method of any of the claims 1 to 11, comprising:
Office action: search_report, dated 2017-12-06
Rejection reasons: inventive_step_epc_56
Prior art cited: ref_id: US1907398176A
ref_type: patent
severity: background
ref_id: WO2008027590A2
ref_type: patent
severity: background
ref_id: - SANGHAMITRA ROY ET AL: "An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design", ACM INTERNATIONAL CONFERENCE PROCEEDING SERIES; PROCEEDINGS OF THE TWENTY-FIRST INTERNATIONAL CONFERENCE ON MACHINE LEARNING, ACM, NEW YORK, US, 7 June 2004 (2004-06-07), pages 484 - 487, XP058234229, ISBN: 978-1-58113-828-3, DOI: 10.1145/996566.996701
ref_type: npl
severity: background
ref_id: - ANONYMOUS: "Floating-point arithmetic - Wikipedia", 26 May 2016 (2016-05-26), XP055390118, Retrieved from the Internet <URL:https://en.wikipedia.org/w/index.php?title=Floating-point_arithmetic&oldid=722188619#Addition_and_subtraction> [retrieved on 20170712]
ref_type: npl
severity: background
ref_id: - MARCUS G ET AL: "A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use", DEVICES, CIRCUITS AND SYSTEMS, 2004. PROCEEDINGS OF THE FIFTH IEEE INT ERNATIONAL CARACAS CONFERENCE ON PUNTA CANA, DOMINICAN REPUBLIC NOVEMBER 3-5,2004, PISCATAWAY, NJ, USA,IEEE, vol. 1, 3 November 2004 (2004-11-03), pages 319 - 323, XP010767774, ISBN: 978-0-7803-8777-5, DOI: 10.1109/ICCDCS.2004.1393405
ref_type: npl
severity: background
ref_id: - ANJANASASIDHARAN ET AL: "VHDL implementation of IEEE 754 floating point unit", INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES2014), 1 February 2014 (2014-02-01), pages 1 - 5, XP055390231, ISBN: 978-1-4799-3835-3, DOI: 10.1109/ICICES.2014.7033999
ref_type: npl
severity: background
ref_id: - MARCUS GUILLERMO: "VHDL Entity FPadd.single_cycle", 1 January 2004 (2004-01-01), XP055390564, Retrieved from the Internet <URL:https://opencores.org/download,fpuvhdl> [retrieved on 20170713]
ref_type: npl
severity: background
ref_id: WO2008027590
ref_type: patent
severity: background
ref_id: - SANGHAMITRA ROY ET AL, "An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design", ACM INTERNATIONAL CONFERENCE PROCEEDING SERIES; PROCEEDINGS OF THE TWENTY-FIRST INTERNATIONAL CONFERENCE ON MACHINE LEARNING, ACM, NEW YORK, US, (20040607), doi:10.1145/996566.996701, ISBN 978-1-58113-828-3, pages 484 - 487, XP058234229 [I] 1,12,13 * pages  484-485 * [Y] 2-11
ref_type: npl
severity: obviousness
ref_id: - Anonymous, "Floating-point arithmetic - Wikipedia", (20160526), URL: https://en.wikipedia.org/w/index.php?title=Floating-point_arithmetic&oldid=722188619#Addition_and_subtraction, (20170712), XP055390118 [A] 1-13 * pages  14-15 *
ref_type: npl
severity: background
ref_id: - MARCUS G ET AL, "A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use", DEVICES, CIRCUITS AND SYSTEMS, 2004. PROCEEDINGS OF THE FIFTH IEEE INT ERNATIONAL CARACAS CONFERENCE ON PUNTA CANA, DOMINICAN REPUBLIC NOVEMBER 3-5,2004, PISCATAWAY, NJ, USA,IEEE, (20041103), vol. 1, doi:10.1109/ICCDCS.2004.1393405, ISBN 978-0-7803-8777-5, pages 319 - 323, XP010767774 [Y] 2-11 * pages  319,320 * * tables 1,2 *
ref_type: npl
severity: obviousness
ref_id: - ANJANASASIDHARAN ET AL, "VHDL implementation of IEEE 754 floating point unit", INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES2014), (20140201), doi:10.1109/ICICES.2014.7033999, ISBN 978-1-4799-3835-3, pages 1 - 5, XP055390231 [Y] 2-11 * page  2 * * page  4 *
ref_type: npl
severity: obviousness
ref_id: - Marcus Guillermo, "VHDL Entity FPadd.single_cycle", (20040101), URL: https://opencores.org/download,fpuvhdl, (20170713), XP055390564 [Y] 5 * page  7 *
ref_type: npl
severity: obviousness
Final disposition: pending (2017-12-06)