Patent application EP17174833A (EP), filed 2017-06-07
Publication number: EP3258401A1
Title: SEMICONDUCTOR LSI DESIGN DEVICE AND DESIGN METHOD
Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.
IPC codes: G06F  17/    50            A I
Claims: number: 1
text: A semiconductor LSI design device, comprising:
number: 2
text: A semiconductor LSI design device, comprising:
number: 3
text: The semiconductor LSI design device according to claim 1 or 2,
wherein the unit that converts the combinational circuit into the sequence circuit which uses the functional block twice or more in a time division manner includes
a unit that converts the combinational circuit into a sequence circuit, the sequence circuit including:
number: 4
text: The semiconductor LSI design device according to claim 2,
wherein the unit that determines the equivalence between the combinational circuit and the sequential circuit is a unit that applies the same input signal to the combinational circuit and the sequential circuit, compares output signals of the circuits after a certain time, and determines that the circuits are equivalent when comparison results for all input patterns coincide with each other.
number: 5
text: The semiconductor LSI design device according to claim 1 or 2,
wherein a functional block to be used is selected from the function block library in a sequence circuit HDL outputted from the unit that converts into the sequential circuit.
number: 6
text: The semiconductor LSI design device according to claim 1, further comprising:
number: 7
text: A semiconductor LSI design method, comprising:
number: 8
text: The semiconductor LSI design method according to claim 7, further comprising,
a step of determining equivalence between the combinational circuit and the sequential circuit instead of the step of extracting the operation order at a time of execution of the sequential circuit and the step of determining whether the operation order allocated to the combinational circuit coincide with the extracted operation order.
number: 9
text: The semiconductor LSI design method according to claim 7, further comprising,
a step of executing logical synthesis and arrangement wiring for mounting on an ASIC or a FPGA on a sequence circuit HDL output in the step of converting into the sequential circuit; and
a step of determining logical equivalence of a sequence circuit netlist generated by executing the logical synthesis and the arrangement wiring on the sequence circuit HDL.
Office action: search_report, dated 2017-12-20
Rejection reasons: novelty_epc_54
inventive_step_epc_56
Prior art cited: ref_id: JP4371856B2
ref_type: patent
severity: background
ref_id: US2007067751A1
ref_type: patent
severity: background
ref_id: US8352505B1
ref_type: patent
severity: background
ref_id: - "Digital Integrated Circuit Design - Chapter 2", 1 January 2008, CAMBRIDGE UNIVERSITY PRESS, ISBN: 978-0-511-45537-7, article HUBERT KAESTLIN: "Digital Integrated Circuit Design - Chapter 2", XP055419008
ref_type: npl
severity: background
ref_id: - "Digital Integrated Circuit Design - Chapter 3", 1 January 2008, CAMBRIDGE UNIVERSITY PRESS, ISBN: 978-0-511-45537-7, article HUBERT KAESTLIN: "Digital Integrated Circuit Design - Chapter 3", pages: 136 - 174, XP055501693
ref_type: npl
severity: background
ref_id: - "Digital Integrated Circuit Design - Chapter 1", 1 January 2008, CAMBRIDGE UNIVERSITY PRESS, ISBN: 978-0-511-45537-7, article HUBERT KAESTLIN: "Digital Integrated Circuit Design - Chapter 1", pages: 1 - 43, XP055573850
ref_type: npl
severity: background
ref_id: US2007067751
ref_type: patent
severity: obviousness
ref_id: US8352505
ref_type: patent
severity: obviousness
ref_id: - Hubert Kaestlin, "Digital Integrated Circuit Design - Chapter 2", Digital Integrated Circuit Design - Chapter 2, Cambridge University Press, (20080101), ISBN 978-0-511-45537-7, XP055419008 [X] 7 * section 2.3.2 * * section 2.4.5 *;; figure 2.19 * * section 2.6.4 *;; figure 2.26 * * section 2.4.2 *;; figure 2.13 * [I] 1-6,8,9
ref_type: npl
severity: novelty_destroying
Final disposition: pending (2017-12-20)