Patent application EP17171944A (EP), filed 2017-05-19
Publication number: EP3261001A1
Title: METHODS FOR SPECIFYING PROCESSOR ARCHITECTURES FOR PROGRAMMABLE INTEGRATED CIRCUITS
Abstract: A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.
IPC codes: G06F  17/    50            A I
Claims: number: 1
text: A method of using processor generator tools (702) implemented on computing equipment (700) to generate a processor on a programmable integrated circuit (100), the method comprising:
number: 2
text: The method of claim 1, further comprising:
number: 3
text: The method of any preceding claim, wherein generating the processor for the programmable integrated circuit comprises generating a reduced instruction set computing (RISC) processor for the programmable integrated circuit (100).
number: 4
text: The method of any preceding claim, wherein receiving the processor parameters comprises receiving (712) a data word size for a given data path in the processor.
number: 5
text: The method of any preceding claim, wherein receiving the processor parameters comprises receiving different data word sizes for multiple data paths in the processor.
number: 6
text: The method of any preceding claim, wherein receiving the processor parameters comprises receiving (714) an instruction word size for the processor.
number: 7
text: The method of any preceding claim, wherein receiving the processor parameters comprises receiving (718) a number of registers for the processor.
number: 8
text: The method of any preceding claim, wherein receiving the processor parameters comprises receiving (720) a number of interrupts that is supported by the processor.
number: 9
text: The method of any preceding claim, wherein receiving the processor parameters comprises receiving (722) a set of instructions for the processor.
number: 10
text: The method of claim 9, further comprising:
number: 11
text: The method of claim 10, further comprising:
number: 12
text: Processor generator tools (702) implemented on computing equipment (700) for generating a processor on a programmable integrated circuit (100), comprising:
number: 13
text: The processor generator tools (702) of claim 12, further comprising:
number: 14
text: The processor generator tools (702) of claim 13, further comprising:
number: 15
text: The processor generator tools (702) of any one of claims 12-14, further comprising:
Office action: search_report, dated 2017-12-27
Rejection reasons: novelty_epc_54
Prior art cited: ref_id: WO03091914A1
ref_type: patent
severity: background
ref_id: US2006259878A1
ref_type: patent
severity: background
ref_id: - DAVID SHELDON ET AL: "Conjoining soft-core FPGA processors", COMPUTER-AIDED DESIGN; [IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN], IEEE PRESS, 445 HOES LANE PO BOX 1331 PISCATAWAY, NJ 08855-1331 USA, 5 November 2006 (2006-11-05), pages 694 - 701, XP058136811, ISSN: 1092-3152, ISBN: 978-0-7803-7607-6, DOI: 10.1145/1233501.1233645
ref_type: npl
severity: background
ref_id: WO03091914
ref_type: patent
severity: novelty_destroying
ref_id: US2006259878
ref_type: patent
severity: novelty_destroying
Final disposition: pending (2017-12-27)