{"name": "raid6_sse22_gen_syndrome", "code": "void __fastcall raid6_sse22_gen_syndrome ( int @@a1@@ , unsigned __int64 @@a2@@ , __int64 @@a3@@ ) { __m128i @@v3@@ ; __m128i v4 ; __m128i v5 ; __m128i @@v7@@ ; __m128i @@v8@@ ; __m128i v9 ; __m128i v10 ; __m128i v12 ; __m128i v13 ; __m128i v14 ; __m128i v15 ; __int64 @@v16@@ ; __int64 @@v17@@ ; int @@v18@@ ; int @@j@@ ; int @@i@@ ; @@v18@@ = @@a1@@ - Number ; @@v17@@ = * ( _QWORD * ) ( Number * ( @@a1@@ - Number + Number L ) + @@a3@@ ) ; @@v16@@ = * ( _QWORD * ) ( Number * ( @@a1@@ - Number + Number L ) + @@a3@@ ) ; kernel_fpu_begin ( ) ; @@v3@@ = _mm_load_si128 ( ( const __m128i * ) & raid6_sse_constants ) ; v4 = Number L ; v5 = Number L ; for ( @@i@@ = Number ; @@a2@@ > @@i@@ ; @@i@@ += Number ) { @@_RAX@@ = ( const __m128i * ) ( * ( _QWORD * ) ( Number L * @@v18@@ + @@a3@@ ) + @@i@@ ) ; __asm { prefetchnta byte ptr [ rax ] } @@v7@@ = _mm_load_si128 ( @@_RAX@@ ) ; @@v8@@ = _mm_load_si128 ( ( const __m128i * ) ( @@i@@ + Number L + * ( _QWORD * ) ( Number L * @@v18@@ + @@a3@@ ) ) ) ; v9 = @@v7@@ ; v10 = @@v8@@ ; for ( @@j@@ = @@a1@@ - Number ; @@j@@ >= Number ; -- @@j@@ ) { @@_RAX@@ = ( const __m128i * ) ( * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) + @@i@@ ) ; __asm { prefetchnta byte ptr [ rax ] } v12 = _mm_xor_si128 ( _mm_add_epi8 ( v9 , v9 ) , _mm_and_si128 ( _mm_cmpgt_epi8 ( v4 , v9 ) , @@v3@@ ) ) ; v13 = _mm_xor_si128 ( _mm_add_epi8 ( v10 , v10 ) , _mm_and_si128 ( _mm_cmpgt_epi8 ( v5 , v10 ) , @@v3@@ ) ) ; v14 = _mm_load_si128 ( @@_RAX@@ ) ; v15 = _mm_load_si128 ( ( const __m128i * ) ( @@i@@ + Number L + * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) ) ) ; @@v7@@ = _mm_xor_si128 ( @@v7@@ , v14 ) ; @@v8@@ = _mm_xor_si128 ( @@v8@@ , v15 ) ; v9 = _mm_xor_si128 ( v12 , v14 ) ; v10 = _mm_xor_si128 ( v13 , v15 ) ; v4 = Number L ; v5 = Number L ; } _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + @@v17@@ ) , @@v7@@ ) ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v17@@ ) , @@v8@@ ) ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + @@v16@@ ) , v9 ) ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v16@@ ) , v10 ) ; } _mm_sfence ( ) ; kernel_fpu_end ( ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "v3", "t": {"T": 8}, "location": "r496"}, {"n": "v7", "t": {"T": 8}, "location": "r528"}, {"n": "v8", "t": {"T": 8}, "location": "r544"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r64"}, {"n": "_RAX", "t": {"T": 3, "t": "const __m128i"}, "location": "r8"}, {"n": "v18", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}, {"n": "v17", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}, {"n": "v16", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s40"}, {"n": "j", "t": {"T": 1, "n": "int", "s": 4}, "location": "s8"}]}