{"name": "raven_set_irq", "code": "__int64 __fastcall raven_set_irq ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { return qemu_set_irq ( * ( _QWORD * ) ( Number L * @@a2@@ + @@a1@@ ) , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
{"name": "raven_pcihost_realizefn", "code": "__int64 __fastcall raven_pcihost_realizefn ( __int64 @@a1@@ , __int64 @@a2@@ ) { int @@i@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v4@@ = object_dynamic_cast_assert ( @@a1@@ , String , String , Number L , String ) ; @@v5@@ = object_dynamic_cast_assert ( @@v4@@ , String , String , Number L , String ) ; @@v6@@ = object_dynamic_cast_assert ( @@v4@@ , String , String , Number L , String ) ; @@v7@@ = get_system_memory ( ) ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) sysbus_init_irq ( @@v4@@ , @@v6@@ + Number * ( @@i@@ + Number L ) ) ; qdev_init_gpio_in ( @@a1@@ , raven_change_gpio , Number L ) ; pci_bus_irqs ( @@v6@@ + Number , raven_set_irq , raven_map_irq , @@v6@@ + Number , Number L ) ; memory_region_init_io ( @@v5@@ + Number , @@v5@@ , & pci_host_conf_le_ops , @@v6@@ , String , Number L ) ; memory_region_add_subregion ( @@v6@@ + Number , Number L , @@v5@@ + Number ) ; memory_region_init_io ( @@v5@@ + Number , @@v5@@ , & pci_host_data_le_ops , @@v6@@ , String , Number L ) ; memory_region_add_subregion ( @@v6@@ + Number , Number L , @@v5@@ + Number ) ; memory_region_init_io ( @@v5@@ + Number , @@v6@@ , raven_pci_io_ops , @@v6@@ , String , Number ) ; memory_region_add_subregion ( @@v7@@ , Number L , @@v5@@ + Number ) ; memory_region_init_io ( @@v6@@ + Number , @@v6@@ , raven_intack_ops , @@v6@@ , String , Number L ) ; memory_region_add_subregion ( @@v7@@ , Number L , @@v6@@ + Number ) ; return object_property_set_bool ( @@v6@@ + Number , Number L , String , @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}