{"name": "raid6_sse24_gen_syndrome", "code": "void __fastcall raid6_sse24_gen_syndrome ( int @@a1@@ , unsigned __int64 @@a2@@ , __int64 @@a3@@ ) { __m128i @@v3@@ ; __m128i @@v4@@ ; __m128i @@v5@@ ; __m128i v6 ; __m128i v7 ; __m128i v8 ; __m128i v9 ; __m128i @@v10@@ ; __m128i @@v11@@ ; __m128i v12 ; __m128i v13 ; __m128i v14 ; __m128i v15 ; __m128i v18 ; __m128i v19 ; __m128i v20 ; __m128i v21 ; __m128i v22 ; __m128i v23 ; __m128i v24 ; __m128i v25 ; __int64 @@v26@@ ; __int64 @@v27@@ ; int @@j@@ ; int @@i@@ ; @@v27@@ = * ( _QWORD * ) ( Number * ( @@a1@@ - Number + Number L ) + @@a3@@ ) ; @@v26@@ = * ( _QWORD * ) ( Number * ( @@a1@@ - Number + Number L ) + @@a3@@ ) ; kernel_fpu_begin ( ) ; @@v3@@ = _mm_load_si128 ( ( const __m128i * ) & raid6_sse_constants ) ; @@v4@@ = Number L ; @@v5@@ = Number L ; v6 = Number L ; v7 = Number L ; v8 = Number L ; v9 = Number L ; @@v10@@ = Number L ; @@v11@@ = Number L ; v12 = Number L ; v13 = Number L ; v14 = Number L ; v15 = Number L ; for ( @@i@@ = Number ; @@a2@@ > @@i@@ ; @@i@@ += Number ) { for ( @@j@@ = @@a1@@ - Number ; @@j@@ >= Number ; -- @@j@@ ) { _RAX = * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) + @@i@@ ; __asm { prefetchnta byte ptr [ rax ] } _RAX = ( const __m128i * ) ( @@i@@ + Number L + * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) ) ; __asm { prefetchnta byte ptr [ rax ] } v18 = _mm_xor_si128 ( _mm_add_epi8 ( v6 , v6 ) , _mm_and_si128 ( _mm_cmpgt_epi8 ( v7 , v6 ) , @@v3@@ ) ) ; v19 = _mm_xor_si128 ( _mm_add_epi8 ( v8 , v8 ) , _mm_and_si128 ( _mm_cmpgt_epi8 ( v9 , v8 ) , @@v3@@ ) ) ; v20 = _mm_xor_si128 ( _mm_add_epi8 ( v12 , v12 ) , _mm_and_si128 ( _mm_cmpgt_epi8 ( v13 , v12 ) , @@v3@@ ) ) ; v21 = _mm_xor_si128 ( _mm_add_epi8 ( v14 , v14 ) , _mm_and_si128 ( _mm_cmpgt_epi8 ( v15 , v14 ) , @@v3@@ ) ) ; v22 = _mm_load_si128 ( ( const __m128i * ) ( * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) + @@i@@ ) ) ; v23 = _mm_load_si128 ( ( const __m128i * ) ( @@i@@ + Number L + * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) ) ) ; v24 = _mm_load_si128 ( _RAX ) ; v25 = _mm_load_si128 ( ( const __m128i * ) ( @@i@@ + Number L + * ( _QWORD * ) ( Number L * @@j@@ + @@a3@@ ) ) ) ; @@v4@@ = _mm_xor_si128 ( @@v4@@ , v22 ) ; @@v5@@ = _mm_xor_si128 ( @@v5@@ , v23 ) ; @@v10@@ = _mm_xor_si128 ( @@v10@@ , v24 ) ; @@v11@@ = _mm_xor_si128 ( @@v11@@ , v25 ) ; v6 = _mm_xor_si128 ( v18 , v22 ) ; v8 = _mm_xor_si128 ( v19 , v23 ) ; v12 = _mm_xor_si128 ( v20 , v24 ) ; v14 = _mm_xor_si128 ( v21 , v25 ) ; v7 = Number L ; v9 = Number L ; v13 = Number L ; v15 = Number L ; } _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + @@v27@@ ) , @@v4@@ ) ; @@v4@@ = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v27@@ ) , @@v5@@ ) ; @@v5@@ = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v27@@ ) , @@v10@@ ) ; @@v10@@ = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v27@@ ) , @@v11@@ ) ; @@v11@@ = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + @@v26@@ ) , v6 ) ; v6 = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v26@@ ) , v8 ) ; v8 = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v26@@ ) , v12 ) ; v12 = Number L ; _mm_stream_si128 ( ( __m128i * ) ( @@i@@ + Number L + @@v26@@ ) , v14 ) ; v14 = Number L ; } _mm_sfence ( ) ; kernel_fpu_end ( ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "v3", "t": {"T": 8}, "location": "r496"}, {"n": "v4", "t": {"T": 8}, "location": "r528"}, {"n": "v5", "t": {"T": 8}, "location": "r544"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r64"}, {"n": "v10", "t": {"T": 8}, "location": "r656"}, {"n": "v11", "t": {"T": 8}, "location": "r672"}, {"n": "v27", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}, {"n": "v26", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s40"}, {"n": "j", "t": {"T": 1, "n": "int", "s": 4}, "location": "s8"}]}