{"name": "gen_arm_shift_reg", "code": "unsigned __int64 __fastcall gen_arm_shift_reg ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ ) { unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; if ( @@a4@@ ) { if ( @@a2@@ == Number ) { gen_helper_ror_cc ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { gen_helper_sar_cc ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) gen_helper_shr_cc ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else { gen_helper_shl_cc ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } } } else if ( @@a2@@ == Number ) { tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , Number ) ; tcg_gen_rotr_i32 ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { gen_helper_sar ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) gen_helper_shr ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else { gen_helper_shl ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } } dead_tmp ( @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}