{"name": "gen_shift_rm_T1", "code": "unsigned __int64 __fastcall gen_shift_rm_T1 ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned int @@v9@@ ; unsigned int @@v10@@ ; int @@v11@@ ; __int64 @@v12@@ ; unsigned __int64 @@v13@@ ; @@v13@@ = __readfsqword ( Number ) ; if ( @@a2@@ == Number ) @@v12@@ = Number L ; else @@v12@@ = Number L ; if ( @@a3@@ == Number ) gen_op_ld_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a2@@ ) ; else gen_op_mov_TN_reg ( @@a2@@ , Number , @@a3@@ ) ; tcg_gen_andi_i64 ( dword_2E2A4 , dword_2E2A4 , @@v12@@ ) ; tcg_gen_addi_i64 ( cpu_tmp5 , dword_2E2A4 , Number ) ; if ( @@a4@@ ) { if ( @@a5@@ ) { gen_exts ( @@a2@@ , cpu_T [ Number ] ) ; tcg_gen_sar_i64 ( cpu_T3 , cpu_T [ Number ] , cpu_tmp5 ) ; tcg_gen_sar_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; } else { gen_extu ( @@a2@@ , cpu_T [ Number ] ) ; tcg_gen_shr_i64 ( cpu_T3 , cpu_T [ Number ] , cpu_tmp5 ) ; tcg_gen_shr_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; } } else { tcg_gen_shl_i64 ( cpu_T3 , cpu_T [ Number ] , cpu_tmp5 ) ; tcg_gen_shl_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; } if ( @@a3@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a2@@ ) ; else gen_op_mov_reg_T0 ( @@a2@@ , @@a3@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) gen_op_set_cc_op ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v9@@ = tcg_temp_local_new_i64 ( ) ; @@v10@@ = tcg_temp_local_new_i64 ( ) ; tcg_gen_mov_i64 ( @@v9@@ , cpu_T [ Number ] ) ; tcg_gen_mov_i64 ( @@v10@@ , cpu_T3 ) ; @@v11@@ = gen_new_label ( ) ; tcg_gen_brcondi_i64 ( Number , dword_2E2A4 , Number L , @@v11@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src , @@v10@@ ) ; tcg_gen_mov_i64 ( cpu_cc_dst , @@v9@@ ) ; if ( @@a4@@ ) tcg_gen_movi_i32 ( cpu_cc_op , @@a2@@ + Number ) ; else tcg_gen_movi_i32 ( cpu_cc_op , @@a2@@ + Number ) ; gen_set_label ( @@v11@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_temp_free_i64 ( @@v9@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v13@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v12", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v11", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "v13", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
{"name": "gen_set_label", "code": "unsigned __int64 __fastcall gen_set_label ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_br", "code": "unsigned __int64 __fastcall tcg_gen_br ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1i ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_movi_i32", "code": "unsigned __int64 __fastcall tcg_gen_movi_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_mov_i64", "code": "unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_andi_i64", "code": "unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_shl_i64", "code": "unsigned __int64 __fastcall tcg_gen_shl_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_shr_i64", "code": "unsigned __int64 __fastcall tcg_gen_shr_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_sar_i64", "code": "unsigned __int64 __fastcall tcg_gen_sar_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_addi_i64", "code": "unsigned __int64 __fastcall tcg_gen_addi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_add_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_brcondi_i64", "code": "unsigned __int64 __fastcall tcg_gen_brcondi_i64 ( unsigned int @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_brcond_i64 ( @@a1@@ , @@a2@@ , @@v6@@ , @@a4@@ ) ; tcg_temp_free_i64 ( @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_mov_reg_T0", "code": "unsigned __int64 __fastcall gen_op_mov_reg_T0 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; gen_op_mov_reg_v ( @@a1@@ , @@a2@@ , cpu_T ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_mov_TN_reg", "code": "unsigned __int64 __fastcall gen_op_mov_TN_reg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; gen_op_mov_v_reg ( @@a1@@ , cpu_T [ @@a2@@ ] , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_set_cc_op", "code": "unsigned __int64 __fastcall gen_op_set_cc_op ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i32 ( cpu_cc_op , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_ld_T0_A0", "code": "unsigned __int64 __fastcall gen_op_ld_T0_A0 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; gen_op_ld_v ( @@a1@@ , cpu_T [ Number ] , cpu_A0 ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_st_T0_A0", "code": "unsigned __int64 __fastcall gen_op_st_T0_A0 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; gen_op_st_v ( @@a1@@ , cpu_T [ Number ] , cpu_A0 ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_extu", "code": "unsigned __int64 __fastcall gen_extu ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { tcg_gen_ext32u_i64 ( @@a2@@ , @@a2@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ ) { if ( @@a1@@ == Number ) tcg_gen_ext16u_i64 ( @@a2@@ , @@a2@@ ) ; } else { tcg_gen_ext8u_i64 ( @@a2@@ , @@a2@@ ) ; } } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_exts", "code": "unsigned __int64 __fastcall gen_exts ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { tcg_gen_ext32s_i64 ( @@a2@@ , @@a2@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ ) { if ( @@a1@@ == Number ) tcg_gen_ext16s_i64 ( @@a2@@ , @@a2@@ ) ; } else { tcg_gen_ext8s_i64 ( @@a2@@ , @@a2@@ ) ; } } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op", "code": "unsigned __int64 __fastcall gen_op ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; if ( @@a4@@ == Number ) gen_op_ld_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_TN_reg ( @@a3@@ , Number , @@a4@@ ) ; switch ( @@a2@@ ) { case Number : gen_op_addl_T0_T1 ( ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; gen_op_update2_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : tcg_gen_or_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ == Number ) goto LABEL_32 ; goto LABEL_28 ; case Number : if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) gen_op_set_cc_op ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; gen_compute_eflags_c ( cpu_tmp4 ) ; tcg_gen_add_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; tcg_gen_add_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , cpu_tmp4 ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src , dword_2E2A4 ) ; tcg_gen_mov_i64 ( cpu_cc_dst , cpu_T [ Number ] ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp2_i32 , cpu_tmp4 ) ; tcg_gen_shli_i32 ( cpu_tmp2_i32 , cpu_tmp2_i32 , Number ) ; tcg_gen_addi_i32 ( cpu_cc_op , cpu_tmp2_i32 , @@a3@@ + Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) gen_op_set_cc_op ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; gen_compute_eflags_c ( cpu_tmp4 ) ; tcg_gen_sub_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; tcg_gen_sub_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , cpu_tmp4 ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src , dword_2E2A4 ) ; tcg_gen_mov_i64 ( cpu_cc_dst , cpu_T [ Number ] ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp2_i32 , cpu_tmp4 ) ; tcg_gen_shli_i32 ( cpu_tmp2_i32 , cpu_tmp2_i32 , Number ) ; tcg_gen_addi_i32 ( cpu_cc_op , cpu_tmp2_i32 , @@a3@@ + Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : tcg_gen_sub_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; gen_op_update2_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : tcg_gen_xor_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ != Number ) goto LABEL_28 ; goto LABEL_32 ; case Number : gen_op_cmpl_T0_T1_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; default : tcg_gen_and_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ == Number ) LABEL_32 : gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else LABEL_28 : gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; gen_op_update1_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; } }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_shift", "code": "unsigned __int64 __fastcall gen_shift ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; if ( @@a5@@ != Number ) gen_op_mov_TN_reg ( @@a3@@ , Number , @@a5@@ ) ; switch ( @@a2@@ ) { case Number : gen_rot_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number ) ; break ; case Number : gen_rot_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number ) ; break ; case Number : gen_rotc_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number ) ; break ; case Number : gen_rotc_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number ) ; break ; case Number : case Number : gen_shift_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number , Number ) ; break ; case Number : gen_shift_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number , Number ) ; break ; case Number : gen_shift_rm_T1 ( @@a1@@ , @@a3@@ , @@a4@@ , Number , Number ) ; break ; default : return __readfsqword ( Number ) ^ @@v8@@ ; } return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}