{"name": "DecodeSPRRegisterClass", "code": "__int64 __fastcall DecodeSPRRegisterClass ( __int64 @@a1@@ , unsigned int @@a2@@ ) { if ( @@a2@@ > Number ) return Number L ; MCOperand_CreateReg0 ( @@a1@@ , ( unsigned __int16 ) SPRDecoderTable [ @@a2@@ ] ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}]}
{"name": "DecodeSPRRegListOperand", "code": "__int64 __fastcall DecodeSPRRegListOperand ( __int64 @@a1@@ , unsigned int @@a2@@ ) { int v2 ; int v3 ; unsigned int v4 ; unsigned int v6 ; unsigned int @@v7@@ ; int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@i@@ ; @@v7@@ = Number ; @@v9@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v8@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; if ( ! @@v8@@ || @@v9@@ + @@v8@@ > Number ) { if ( @@v9@@ + @@v8@@ <= Number ) v2 = @@v8@@ ; else v2 = Number - @@v9@@ ; @@v8@@ = v2 ; if ( v2 ) v3 = @@v8@@ ; else v3 = Number ; @@v8@@ = v3 ; @@v7@@ = Number ; } v4 = DecodeSPRRegisterClass ( @@a1@@ , @@v9@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v7@@ , v4 ) != Number ) return Number L ; for ( @@i@@ = Number ; @@i@@ < @@v8@@ - Number ; ++ @@i@@ ) { v6 = DecodeSPRRegisterClass ( @@a1@@ , ++ @@v9@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v7@@ , v6 ) != Number ) return Number L ; } return @@v7@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "i", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]} {"name": "DecodeVMOVSRR", "code": "__int64 __fastcall DecodeVMOVSRR ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; __int64 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned int @@v11@@ ; unsigned int @@v12@@ ; @@v8@@ = Number ; @@v12@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v11@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v10@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v9@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v10@@ |= Number * fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; if ( @@v12@@ == Number || @@v11@@ == Number || @@v10@@ == Number ) @@v8@@ = Number ; v2 = DecodeSPRRegisterClass ( @@a1@@ , @@v10@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v2 ) != Number ) return Number L ; v4 = DecodeSPRRegisterClass ( @@a1@@ , @@v10@@ + Number ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v4 ) != Number ) return Number L ; v5 = DecodeGPRRegisterClass ( @@a1@@ , @@v12@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v5 ) != Number ) return Number L ; v6 = DecodeGPRRegisterClass ( @@a1@@ , @@v11@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v6 ) != Number ) return Number L ; v7 = DecodePredicateOperand ( @@a1@@ , @@v9@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v7 ) != Number ) result = Number L ; else result = @@v8@@ ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v12", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}, {"n": "v11", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]} {"name": "DecodeVMOVRRS", "code": "__int64 __fastcall DecodeVMOVRRS ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; __int64 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned int @@v11@@ ; unsigned int @@v12@@ ; @@v8@@ = Number ; @@v12@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v11@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v10@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v9@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v10@@ |= Number * fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; if ( @@v12@@ == Number || @@v11@@ == Number || @@v10@@ == Number ) @@v8@@ = Number ; v2 = DecodeGPRRegisterClass ( @@a1@@ , @@v12@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v2 ) != Number ) return Number L ; v4 = DecodeGPRRegisterClass ( @@a1@@ , @@v11@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v4 ) != Number ) return Number L ; v5 = DecodeSPRRegisterClass ( @@a1@@ , @@v10@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v5 ) != Number ) return Number L ; v6 = DecodeSPRRegisterClass ( @@a1@@ , @@v10@@ + Number ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v6 ) != Number ) return Number L ; v7 = DecodePredicateOperand ( @@a1@@ , @@v9@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v8@@ , v7 ) != Number ) result = Number L ; else result = @@v8@@ ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v12", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s4"}, {"n": "v11", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}