{"name": "gen_rot_rm_im", "code": "unsigned __int64 __fastcall gen_rot_rm_im ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { int @@v8@@ ; int @@v10@@ ; unsigned int @@v11@@ ; unsigned int @@v12@@ ; unsigned int @@v13@@ ; int @@v14@@ ; int @@v15@@ ; unsigned __int64 @@v16@@ ; @@v16@@ = __readfsqword ( Number ) ; @@v11@@ = tcg_temp_local_new_i64 ( ) ; @@v12@@ = tcg_temp_local_new_i64 ( ) ; @@v13@@ = tcg_temp_local_new_i64 ( ) ; if ( @@a2@@ == Number ) @@v10@@ = Number ; else @@v10@@ = Number ; if ( @@a3@@ == Number ) { tcg_gen_mov_i64 ( @@v13@@ , cpu_A0 ) ; gen_op_ld_v ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a2@@ , @@v11@@ , @@v13@@ ) ; } else { gen_op_mov_v_reg ( @@a2@@ , @@v11@@ , @@a3@@ ) ; } gen_extu ( @@a2@@ , @@v11@@ ) ; tcg_gen_mov_i64 ( @@v12@@ , @@v11@@ ) ; @@v8@@ = @@v10@@ & @@a4@@ ; @@v14@@ = Number << @@a2@@ ; if ( @@v8@@ ) { @@v15@@ = @@v8@@ & ( ( Number << ( @@a2@@ + Number ) ) - Number ) ; if ( @@a5@@ ) { tcg_gen_shri_i64 ( cpu_tmp4 , @@v11@@ , @@v15@@ ) ; tcg_gen_shli_i64 ( @@v11@@ , @@v11@@ , @@v14@@ - @@v15@@ ) ; } else { tcg_gen_shli_i64 ( cpu_tmp4 , @@v11@@ , @@v15@@ ) ; tcg_gen_shri_i64 ( @@v11@@ , @@v11@@ , @@v14@@ - @@v15@@ ) ; } tcg_gen_or_i64 ( @@v11@@ , @@v11@@ , cpu_tmp4 ) ; } if ( @@a3@@ == Number ) gen_op_st_v ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a2@@ , @@v11@@ , @@v13@@ ) ; else gen_op_mov_reg_v ( @@a2@@ , @@a3@@ , @@v11@@ ) ; if ( @@v8@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) gen_op_set_cc_op ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; gen_compute_eflags ( cpu_cc_src ) ; tcg_gen_andi_i64 ( cpu_cc_src , cpu_cc_src , Number ) ; tcg_gen_xor_i64 ( cpu_tmp0 , @@v12@@ , @@v11@@ ) ; tcg_gen_lshift ( cpu_tmp0 , cpu_tmp0 , Number - @@v14@@ ) ; tcg_gen_andi_i64 ( cpu_tmp0 , cpu_tmp0 , Number L ) ; tcg_gen_or_i64 ( cpu_cc_src , cpu_cc_src , cpu_tmp0 ) ; if ( @@a5@@ ) tcg_gen_shri_i64 ( @@v11@@ , @@v11@@ , @@v14@@ - Number ) ; tcg_gen_andi_i64 ( @@v11@@ , @@v11@@ , Number L ) ; tcg_gen_or_i64 ( cpu_cc_src , cpu_cc_src , @@v11@@ ) ; tcg_gen_discard_i64 ( cpu_cc_dst ) ; tcg_gen_movi_i32 ( cpu_cc_op , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_temp_free_i64 ( @@v11@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; return __readfsqword ( Number ) ^ @@v16@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v15", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v14", "t": {"T": 1, "n": "int", "s": 4}, "location": "s16"}, {"n": "v13", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v12", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}, {"n": "v11", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "v10", "t": {"T": 1, "n": "int", "s": 4}, "location": "s32"}, {"n": "v8", "t": {"T": 1, "n": "int", "s": 4}, "location": "s52"}, {"n": "v16", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
{"name": "tcg_gen_movi_i32", "code": "unsigned __int64 __fastcall tcg_gen_movi_i32 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_mov_i64", "code": "unsigned __int64 __fastcall tcg_gen_mov_i64 ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ != @@a2@@ ) tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_andi_i64", "code": "unsigned __int64 __fastcall tcg_gen_andi_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_or_i64", "code": "unsigned __int64 __fastcall tcg_gen_or_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_xor_i64", "code": "unsigned __int64 __fastcall tcg_gen_xor_i64 ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a2@@ == @@a3@@ ) tcg_gen_movi_i64 ( @@a1@@ , Number L ) ; else tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_shli_i64", "code": "unsigned __int64 __fastcall tcg_gen_shli_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shl_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_shri_i64", "code": "unsigned __int64 __fastcall tcg_gen_shri_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a3@@ ) { @@v4@@ = tcg_const_i64 ( @@a3@@ ) ; tcg_gen_shr_i64 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } else { tcg_gen_mov_i64 ( @@a1@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_discard_i64", "code": "unsigned __int64 __fastcall tcg_gen_discard_i64 ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_op1_i64 ( Number , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_mov_reg_v", "code": "unsigned __int64 __fastcall gen_op_mov_reg_v ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int v5 ; unsigned int v6 ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { tcg_gen_mov_i64 ( cpu_regs [ @@a2@@ ] , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; } if ( @@a1@@ > Number ) goto LABEL_13 ; if ( @@a1@@ ) { if ( @@a1@@ != Number ) { LABEL_13 : tcg_gen_ext32u_i64 ( cpu_regs [ @@a2@@ ] , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; } v6 = tcg_temp_new_i64 ( ) ; tcg_gen_ext16u_i64 ( v6 , @@a3@@ ) ; tcg_gen_andi_i64 ( cpu_regs [ @@a2@@ ] , cpu_regs [ @@a2@@ ] , Number ) ; tcg_gen_or_i64 ( cpu_regs [ @@a2@@ ] , cpu_regs [ @@a2@@ ] , v6 ) ; tcg_temp_free_i64 ( v6 ) ; } else { v5 = tcg_temp_new_i64 ( ) ; tcg_gen_ext8u_i64 ( v5 , @@a3@@ ) ; if ( @@a2@@ <= Number || @@a2@@ > Number || x86_64_hregs ) { tcg_gen_andi_i64 ( cpu_regs [ @@a2@@ ] , cpu_regs [ @@a2@@ ] , Number ) ; tcg_gen_or_i64 ( cpu_regs [ @@a2@@ ] , cpu_regs [ @@a2@@ ] , v5 ) ; } else { tcg_gen_shli_i64 ( v5 , v5 , Number L ) ; tcg_gen_andi_i64 ( cpu_regs [ @@a2@@ - Number ] , cpu_regs [ @@a2@@ - Number ] , Number ) ; tcg_gen_or_i64 ( cpu_regs [ @@a2@@ - Number ] , cpu_regs [ @@a2@@ - Number ] , v5 ) ; } tcg_temp_free_i64 ( v5 ) ; } return __readfsqword ( Number ) ^ @@v7@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_mov_v_reg", "code": "unsigned __int64 __fastcall gen_op_mov_v_reg ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a1@@ || @@a3@@ <= Number || @@a3@@ > Number || x86_64_hregs ) { tcg_gen_mov_i64 ( @@a2@@ , cpu_regs [ @@a3@@ ] ) ; } else { tcg_gen_shri_i64 ( @@a2@@ , cpu_regs [ @@a3@@ - Number ] , Number L ) ; tcg_gen_ext8u_i64 ( @@a2@@ , @@a2@@ ) ; } return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_set_cc_op", "code": "unsigned __int64 __fastcall gen_op_set_cc_op ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; tcg_gen_movi_i32 ( cpu_cc_op , @@a1@@ ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_ld_v", "code": "unsigned __int64 __fastcall gen_op_ld_v ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = ( @@a1@@ >> Number ) - Number ; if ( ( @@a1@@ & Number ) == Number ) { tcg_gen_qemu_ld32u ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } else if ( ( @@a1@@ & Number ) > Number ) { tcg_gen_qemu_ld64 ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } else if ( ( @@a1@@ & Number ) != Number ) { tcg_gen_qemu_ld16u ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } else { tcg_gen_qemu_ld8u ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op_st_v", "code": "unsigned __int64 __fastcall gen_op_st_v ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { int @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = ( @@a1@@ >> Number ) - Number ; if ( ( @@a1@@ & Number ) == Number ) { tcg_gen_qemu_st32 ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } else if ( ( @@a1@@ & Number ) > Number ) { tcg_gen_qemu_st64 ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } else if ( ( @@a1@@ & Number ) != Number ) { tcg_gen_qemu_st16 ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } else { tcg_gen_qemu_st8 ( @@a2@@ , @@a3@@ , @@v4@@ ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_extu", "code": "unsigned __int64 __fastcall gen_extu ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; if ( @@a1@@ == Number ) { tcg_gen_ext32u_i64 ( @@a2@@ , @@a2@@ ) ; } else if ( @@a1@@ <= Number ) { if ( @@a1@@ ) { if ( @@a1@@ == Number ) tcg_gen_ext16u_i64 ( @@a2@@ , @@a2@@ ) ; } else { tcg_gen_ext8u_i64 ( @@a2@@ , @@a2@@ ) ; } } return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_compute_eflags", "code": "unsigned __int64 __fastcall gen_compute_eflags ( int @@a1@@ ) { unsigned __int64 @@v2@@ ; @@v2@@ = __readfsqword ( Number ) ; gen_helper_cc_compute_all ( cpu_tmp2_i32 , cpu_cc_op ) ; tcg_gen_extu_i32_i64 ( @@a1@@ , cpu_tmp2_i32 ) ; return __readfsqword ( Number ) ^ @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_op", "code": "unsigned __int64 __fastcall gen_op ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; if ( @@a4@@ == Number ) gen_op_ld_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_TN_reg ( @@a3@@ , Number , @@a4@@ ) ; switch ( @@a2@@ ) { case Number : gen_op_addl_T0_T1 ( ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; gen_op_update2_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : tcg_gen_or_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ == Number ) goto LABEL_32 ; goto LABEL_28 ; case Number : if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) gen_op_set_cc_op ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; gen_compute_eflags_c ( cpu_tmp4 ) ; tcg_gen_add_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; tcg_gen_add_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , cpu_tmp4 ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src , dword_2E2A4 ) ; tcg_gen_mov_i64 ( cpu_cc_dst , cpu_T [ Number ] ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp2_i32 , cpu_tmp4 ) ; tcg_gen_shli_i32 ( cpu_tmp2_i32 , cpu_tmp2_i32 , Number ) ; tcg_gen_addi_i32 ( cpu_cc_op , cpu_tmp2_i32 , @@a3@@ + Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) gen_op_set_cc_op ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; gen_compute_eflags_c ( cpu_tmp4 ) ; tcg_gen_sub_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; tcg_gen_sub_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , cpu_tmp4 ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; tcg_gen_mov_i64 ( cpu_cc_src , dword_2E2A4 ) ; tcg_gen_mov_i64 ( cpu_cc_dst , cpu_T [ Number ] ) ; tcg_gen_trunc_i64_i32 ( cpu_tmp2_i32 , cpu_tmp4 ) ; tcg_gen_shli_i32 ( cpu_tmp2_i32 , cpu_tmp2_i32 , Number ) ; tcg_gen_addi_i32 ( cpu_cc_op , cpu_tmp2_i32 , @@a3@@ + Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : tcg_gen_sub_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ == Number ) gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; gen_op_update2_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; case Number : tcg_gen_xor_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ != Number ) goto LABEL_28 ; goto LABEL_32 ; case Number : gen_op_cmpl_T0_T1_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; default : tcg_gen_and_i64 ( cpu_T [ Number ] , cpu_T [ Number ] , dword_2E2A4 ) ; if ( @@a4@@ == Number ) LABEL_32 : gen_op_st_T0_A0 ( * ( _DWORD * ) ( @@a1@@ + Number ) + @@a3@@ ) ; else LABEL_28 : gen_op_mov_reg_T0 ( @@a3@@ , @@a4@@ ) ; gen_op_update1_cc ( ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a3@@ + Number ; return __readfsqword ( Number ) ^ @@v7@@ ; } }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "tcg_gen_lshift", "code": "unsigned __int64 __fastcall tcg_gen_lshift ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; if ( @@a3@@ < Number ) tcg_gen_shri_i64 ( @@a1@@ , @@a2@@ , - @@a3@@ ) ; else tcg_gen_shli_i64 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_shifti", "code": "unsigned __int64 __fastcall gen_shifti ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; switch ( @@a2@@ ) { case Number : gen_rot_rm_im ( @@a1@@ , @@a3@@ , @@a4@@ , @@a5@@ , Number ) ; break ; case Number : gen_rot_rm_im ( @@a1@@ , @@a3@@ , @@a4@@ , @@a5@@ , Number ) ; break ; case Number : case Number : gen_shift_rm_im ( @@a1@@ , @@a3@@ , @@a4@@ , @@a5@@ , Number , Number ) ; break ; case Number : gen_shift_rm_im ( @@a1@@ , @@a3@@ , @@a4@@ , @@a5@@ , Number , Number ) ; break ; case Number : gen_shift_rm_im ( @@a1@@ , @@a3@@ , @@a4@@ , @@a5@@ , Number , Number ) ; break ; default : gen_op_movl_T1_im ( @@a5@@ ) ; gen_shift ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , Number ) ; break ; } return __readfsqword ( Number ) ^ @@v8@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v8", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}