{"name": "ARM_AM_getAM2Opc", "code": "__int64 __fastcall ARM_AM_getAM2Opc ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { return @@a2@@ | ( ( @@a1@@ == Number ) << Number ) | ( @@a3@@ << Number ) | ( unsigned int ) ( @@a4@@ << Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
{"name": "DecodeAddrMode2IdxInstruction", "code": "__int64 __fastcall DecodeAddrMode2IdxInstruction ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; __int64 result ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; bool v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int @@v13@@ ; int @@v14@@ ; unsigned int @@v15@@ ; bool @@v16@@ ; int @@v17@@ ; int @@v18@@ ; int @@v19@@ ; unsigned int @@v20@@ ; unsigned int @@v21@@ ; unsigned int @@v22@@ ; unsigned int @@v23@@ ; unsigned int @@v24@@ ; int @@v25@@ ; int @@v26@@ ; int @@v27@@ ; @@v13@@ = Number ; @@v24@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v23@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v22@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v21@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v20@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v19@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v18@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v17@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v25@@ = Number ; v2 = MCInst_getOpcode ( @@a1@@ ) ; if ( v2 > Number ) { if ( v2 - Number > Number ) goto LABEL_7 ; } else if ( v2 < Number ) { goto LABEL_7 ; } v3 = DecodeGPRRegisterClass ( @@a1@@ , @@v24@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v13@@ , v3 ) != Number ) return Number L ; LABEL_7 : v5 = DecodeGPRRegisterClass ( @@a1@@ , @@v23@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v13@@ , v5 ) != Number ) return Number L ; v6 = MCInst_getOpcode ( @@a1@@ ) ; if ( v6 > Number ) { if ( v6 - Number > Number ) goto LABEL_15 ; } else if ( v6 < Number ) { goto LABEL_15 ; } v7 = DecodeGPRRegisterClass ( @@a1@@ , @@v24@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v13@@ , v7 ) != Number ) return Number L ; LABEL_15 : v8 = DecodeGPRRegisterClass ( @@a1@@ , @@v24@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v13@@ , v8 ) != Number ) return Number L ; @@v27@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) != Number ; v9 = ! @@v18@@ || @@v17@@ == Number ; @@v16@@ = v9 ; if ( @@v18@@ && @@v16@@ ) { @@v25@@ = Number ; } else if ( ! @@v18@@ && @@v16@@ ) { @@v25@@ = Number ; } if ( @@v16@@ && ( @@v24@@ == Number || @@v24@@ == @@v23@@ ) ) @@v13@@ = Number ; if ( @@v19@@ ) { v10 = DecodeGPRnopcRegisterClass ( @@a1@@ , @@v22@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v13@@ , v10 ) != Number ) return Number L ; @@v26@@ = Number ; v11 = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; if ( v11 == Number ) { @@v26@@ = Number ; } else { if ( v11 > Number ) return Number L ; if ( v11 == Number ) { @@v26@@ = Number ; } else if ( v11 ) { @@v26@@ = Number ; } else { @@v26@@ = Number ; } } @@v14@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; if ( @@v26@@ == Number && ! @@v14@@ ) @@v26@@ = Number ; @@v21@@ = ARM_AM_getAM2Opc ( @@v27@@ , @@v14@@ , @@v26@@ , @@v25@@ ) ; MCOperand_CreateImm0 ( @@a1@@ , @@v21@@ ) ; } else { MCOperand_CreateReg0 ( @@a1@@ , Number L ) ; @@v15@@ = ARM_AM_getAM2Opc ( @@v27@@ , @@v21@@ , Number , @@v25@@ ) ; MCOperand_CreateImm0 ( @@a1@@ , @@v15@@ ) ; } v12 = DecodePredicateOperand ( @@a1@@ , @@v20@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v13@@ , v12 ) != Number ) result = Number L ; else result = @@v13@@ ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v25", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v24", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v23", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v22", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s24"}, {"n": "v21", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "v20", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s32"}, {"n": "v19", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "v27", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}, {"n": "v18", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "v17", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "v16", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s45"}, {"n": "v15", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s52"}, {"n": "v14", "t": {"T": 1, "n": "int", "s": 4}, "location": "s56"}, {"n": "v13", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s60"}, {"n": "v26", "t": {"T": 1, "n": "int", "s": 4}, "location": "s8"}]} {"name": "DecodeSORegMemOperand", "code": "__int64 __fastcall DecodeSORegMemOperand ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v4 ; unsigned int @@v5@@ ; int @@v6@@ ; int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; unsigned int @@v10@@ ; unsigned int @@v11@@ ; int @@v12@@ ; @@v5@@ = Number ; @@v10@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v9@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v8@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v7@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v6@@ = fieldFromInstruction_4 ( @@a2@@ , Number , Number ) ; @@v12@@ = Number ; if ( @@v8@@ == Number ) { @@v12@@ = Number ; } else if ( @@v8@@ <= Number ) { if ( @@v8@@ == Number ) { @@v12@@ = Number ; } else if ( @@v8@@ ) { @@v12@@ = Number ; } else { @@v12@@ = Number ; } } if ( @@v12@@ == Number && ! @@v7@@ ) @@v12@@ = Number ; v2 = DecodeGPRRegisterClass ( @@a1@@ , @@v10@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v5@@ , v2 ) != Number ) return Number L ; v4 = DecodeGPRRegisterClass ( @@a1@@ , @@v9@@ ) ; if ( ( unsigned __int8 ) Check ( & @@v5@@ , v4 ) != Number ) return Number L ; if ( @@v6@@ ) @@v11@@ = ARM_AM_getAM2Opc ( Number , @@v7@@ , @@v12@@ , Number ) ; else @@v11@@ = ARM_AM_getAM2Opc ( Number , @@v7@@ , @@v12@@ , Number ) ; MCOperand_CreateImm0 ( @@a1@@ , @@v11@@ ) ; return @@v5@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v10", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v7", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "v6", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s32"}, {"n": "v12", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}, {"n": "v11", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]}