{"name": "tcg_gen_st_i64", "code": "unsigned __int64 __fastcall tcg_gen_st_i64 ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
{"name": "tcg_gen_ldst_op_i64", "code": "unsigned __int64 __fastcall tcg_gen_ldst_op_i64 ( __int16 @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { _WORD * v4 ; _QWORD * v5 ; _QWORD * v6 ; _QWORD * v7 ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; v4 = ( _WORD * ) gen_opc_ptr ; gen_opc_ptr += Number L ; * v4 = @@a1@@ ; v5 = ( _QWORD * ) gen_opparam_ptr ; gen_opparam_ptr += Number L ; * v5 = @@a2@@ ; v6 = ( _QWORD * ) gen_opparam_ptr ; gen_opparam_ptr += Number L ; * v6 = @@a3@@ ; v7 = ( _QWORD * ) gen_opparam_ptr ; gen_opparam_ptr += Number L ; * v7 = @@a4@@ ; return __readfsqword ( Number ) ^ @@v9@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "neon_store_reg64", "code": "unsigned __int64 __fastcall neon_store_reg64 ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "gen_mov_vreg_F0", "code": "unsigned __int64 __fastcall gen_mov_vreg_F0 ( int @@a1@@ , int @@a2@@ ) { __int64 v2 ; __int64 v3 ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; if ( @@a1@@ ) { v2 = vfp_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i64 ( cpu_F0d , cpu_env , v2 ) ; } else { v3 = vfp_reg_offset ( Number , @@a2@@ ) ; tcg_gen_st_i32 ( cpu_F0s , cpu_env , v3 ) ; } return __readfsqword ( Number ) ^ @@v5@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]} {"name": "iwmmxt_store_reg", "code": "unsigned __int64 __fastcall iwmmxt_store_reg ( int @@a1@@ , int @@a2@@ ) { unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; tcg_gen_st_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}