Wright etch
The Wright etch (also Wright-Jenkins etch) is a preferential etch for revealing defects in <100>- and <111>-oriented, p- and n-type silicon wafers used for making transistors, microprocessors, memories, and other components. Revealing, identifying, and remedying such defects is essential for progress along the path predicted by Moore's Law. It was developed by Margaret Wright Jenkins (1936-2018) in 1976 while working in research and development at Motorola Inc. in Phoenix, AZ. It was published in 1977. This etchant reveals clearly defined oxidation-induced stacking faults, dislocations, swirls and striations with minimum surface roughness  or extraneous pitting. These defects are known causes of shorts and current leakage in finished semiconductor devices (such as transistors) should they fall across isolated junctions. A relatively low etch rate (~1 micrometre per minute) at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in large quantities. Etch formula. The composition of the Wright etch is as follows: In mixing the solution, the best results are obtained by first dissolving the copper nitrate in the given amount of water; otherwise the order of mixing is not critical. Etch mechanism. The  Wright etch consistently produces well-defined etch figures of common defects on silicon surfaces. This attribute is attributed to the interactions of the selected chemicals in the formula. Robbins and Schwartz described chemical etching of silicon in detail using an HF, HNO and HO system; and an HF, HNO, HO and CHCOOH (acetic acid) system. Briefly, the etching of silicon is a two-step process. First, the top surface of the silicon is converted into a soluble oxide by a suitable oxidizing agent(s). Then the resulting oxide layer is removed from the surface by dissolution in a suitable solvent, usually  HF. This is a continuous process during the etch cycle. In order to delineate a crystal defect, the defect area must be oxidized at a slower or faster rate than the surrounding area thereby forming a mound or pit during the preferential etch process. In the present system, the silicon is oxidized with HNO, CrO solution (which in this case contains the CrO dichromate ion, since the pH is low - see the phase diagram in chromic acid) and Cu (NO). The dichromate ion, a strong oxidizing agent, is considered to be the principal oxidizing agent. The ratio of HNO to  CrO solution stated in the formula produces a superior etched surface. Other ratios produce less desirable finishes. With the addition of a small amount of Cu (NO), the definition of the defect was enhanced. Therefore, it is believed that the Cu (NO) affects the localized differential oxidation rate at the defect site. The addition of the acetic acid gave the background surface of the etched silicon a smooth finish. It is theorized that this effect is attributed to the wetting action of the acetic acid which prevents the formation of bubbles during etching. All experimental preferential etching to show defects  was done on cleaned and oxidized wafers. All oxidations were performed at 1200 °C in steam for 75 minutes. Figure 1 (a) shows oxidation-induced stacking faults in <100>-oriented wafers after 30 minutes Wright etch, (b) and (c) show dislocation pits on <100>- and <111>-oriented wafers respectively after 20 minutes Wright etch. Figure 1 (a) shows oxidation-induced stacking faults on a <100>-oriented, 7-10 Ω-cm, boron-doped wafer after 30 minutes Wright etch (the A arrow in this figure points to the shape of faults that intersect the surface, while B points to  bulk faults). Figure 1 (b) and (c) show dislocation pits on <100>- and <111>-oriented wafers respectively after 20 minutes Wright etch. Summary. This etch process is a quick and reliable method of determining the integrity of pre-processed polished silicon wafers or to reveal defects that may be induced at any point during wafer processing. It has been demonstrated that Wright etch is superior in revealing stacking faults and dislocation etch figures when compared with those revealed by Sirtl and Secco etchings. This etch is widely used in failure analysis of electrical devices at various wafer processing stages . In comparison, the Wright etch was often the preferred etchant to reveal defects in silicon crystals. Figure 2 shows a comparison of oxidation-induced stacking fault delineation on <100>-oriented wafers after Wright etch, Secco and Sirtl etch respectively. Figure 3 shows a comparison of dislocation pits delineation on <100>-oriented wafers after Wright etch, Secco and Sirtl etch. The final figure 4 shows a comparison of dislocation pits revealed on a <111>-oriented wafer after etching with Wright etch, Secco and Sirtl etch respectively. Figure 3 shows a comparison of dislocation delineation on a <100>-oriented, 10-20 Ω -cm, boron doped wafer after oxidation and preferential etching. (a) After 20 minutes Wright etch, (b) 10 minutes Secco etch and (c) 6 minutes Sirtl etch. Figure 4 shows a comparison of dislocation delineation on a <111>-oriented, 10-20 Ω-cm, boron-doped wafer after oxidation and preferential etching. (a) After 10 minutes Wright etch, (b) 10 minutes Secco etch and (c) 3 minutes Sirtl etch. The arrows indicate slip direction.