Amber (processor)
The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects. Overview. The Amber core is fully compatible with the ARMv2a instruction set and is thus supported by the GNU toolchain. This older version of the ARM instruction set is supported because it is not covered by patents, and so can be implemented with no license from ARM Holdings, unlike some prior open source projects (e.g., nnARM). The  cores were developed in Verilog 2001 and are optimized for field-programmable gate array (FPGA) synthesis. For example, there is no reset logic: all registers are reset as part of FPGA initialization. The Amber project provides a complete embedded field-programmable gate array (FPGA) system incorporating the Amber core and several peripherals, including universal asynchronous receiver/transmitters (UARTs), timers, and an Ethernet MAC. The Amber project provides two versions of the core. Both cores implement the same instruction set architecture (ISA) and are fully software compatible. Both cores have been verified by booting a Linux 2.4 kernel. Versions of the  Linux kernel from the 2.4 branch and earlier contain configurations for the supported ISA. Versions of the Linux kernel 2.6 and later do not explicitly support the ARM v2a ISA and so need more modifications to run. The cores do not contain a memory management unit (MMU) so they can only run a non-virtual memory variant of Linux, such as μClinux. Further reading. For a description of the ARMv2a ISA, see "Archimedes Operating System: A Dabhand Guide", or "Acorn RISC Machine Family Data Manual".