Ferroelectric RAM
Ferroelectric RAM (FeRAM, F-RAM or FRAM) is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory. An F-RAM chip contains a thin film of ferroelectric material, often lead zirconate titanate, commonly referred to as PZT. The atoms in the PZT layer change polarity in an electric field, thereby producing a power-efficient binary switch. However, the most important aspect  of the PZT is that it is not affected by power disruption or magnetic interference, making F-RAM a reliable nonvolatile memory. FeRAM's advantages over Flash include: lower power usage, faster write performance and a much greater maximum read/write endurance (about 10 to 10 cycles). FeRAMs have data retention times of more than 10 years at +85 °C (up to many decades at lower temperatures). Market disadvantages of FeRAM are much lower storage densities than flash devices, storage capacity limitations and higher cost. Like DRAM, FeRAM's read process is destructive, necessitating a write-after-read architecture . History. Ferroelectric RAM was proposed by MIT graduate student Dudley Allen Buck in his master's thesis, "Ferroelectrics for Digital Information Storage and Switching," published in 1952. This was during an era of sharing research between members of the scientific community as a means to rapidly propel technological innovation during a rapid buildup of computing power in the Cold War era. In 1955, Bell Telephone Laboratories was experimenting with ferroelectric-crystal memories. Following the introduction of metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) chips in the early 1970s, development of FeRAM began in the late 1980s. Work was  done in 1991 at NASA's Jet Propulsion Laboratory (JPL) on improving methods of read out, including a novel method of non-destructive readout using pulses of UV radiation. FeRAM was commercialized in the late 1990s. In 1996, Samsung Electronics introduced a 4Mb FeRAM chip fabricated using NMOS logic. In 1998, Hyundai Electronics (now SK Hynix) also commercialized FeRAM technology. The earliest known commercial product to use FeRAM is Sony's PlayStation 2 Memory Card (8MB), released in 2000. The Memory Card's microcontroller (MCU) manufactured by Toshiba contained 32kb (4 kB) embedded FeRAM fabricated using a 500  nm complementary MOS (CMOS) process. A major modern FeRAM manufacturer is Ramtron, a fabless semiconductor company. One major licensee is Fujitsu, who operates one of the largest semiconductor foundry production lines with FeRAM capability. Since 1999 they have been using this line to produce standalone FeRAMs, as well as specialized chips (e.g. chips for smart cards) with embedded FeRAMs. Fujitsu produced devices for Ramtron until 2010. Since 2010 Ramtron's fabricators have been TI (Texas Instruments) and IBM. Since at least 2001 Texas Instruments has collaborated with Ramtron to develop FeRAM test chips in a modified 130 nm process. In  the fall of 2005, Ramtron reported that they were evaluating prototype samples of an 8-megabit FeRAM manufactured using Texas Instruments' FeRAM process. Fujitsu and Seiko-Epson were in 2005 collaborating in the development of a 180 nm FeRAM process. In 2012 Ramtron was acquired by Cypress Semiconductor. FeRAM research projects have also been reported at Samsung, Matsushita, Oki, Toshiba, Infineon, Hynix, Symetrix, Cambridge University, University of Toronto, and the Interuniversity Microelectronics Centre (IMEC, Belgium). Description. Conventional DRAM consists of a grid of small capacitors and their associated wiring and signaling transistors. Each storage element, a "cell", consists of one  capacitor and one transistor, a so-called "1T-1C" device. It is typically a type of MOS memory, fabricated using CMOS technology. DRAM cells scale directly with the size of the semiconductor fabrication process being used to make it. For instance, on the 90 nm process used by most memory providers to make DDR2 DRAM, the cell size is 0.22 μm², which includes the capacitor, transistor, wiring, and some amount of "blank space" between the various parts — it appears 35% utilization is typical, leaving 65% of the space empty (for separation). DRAM data is stored as the presence or lack of  an electrical charge in the capacitor, with the lack of charge in general representing "0". Writing is accomplished by activating the associated control transistor, draining the cell to write a "0", or sending current into it from a supply line if the new value should be "1". Reading is similar in nature; the transistor is again activated, draining the charge to a "sense amplifier". If a pulse of charge is noticed in the amplifier, the cell held a charge and thus reads "1"; the lack of such a pulse indicates a "0". Note that this process is "destructive", once the  cell has been read. If it did hold a "1," it must be re-charged to that value again. Since a cell loses its charge after some time due to leak currents, it must be actively refreshed at intervals. The 1T-1C storage cell design in a FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor. In a DRAM cell capacitor, a linear dielectric is used, whereas in a FeRAM cell capacitor the dielectric structure includes ferroelectric material, typically lead zirconate titanate (PZT). A ferroelectric  material has a nonlinear relationship between the applied electric field and the apparently stored charge. Specifically, the ferroelectric characteristic has the form of a hysteresis loop, which is very similar in shape to the hysteresis loop of ferromagnetic materials. The dielectric constant of a ferroelectric is typically much higher than that of a linear dielectric because of the effects of semi-permanent electric dipoles formed in the crystal structure of the ferroelectric material. When an external electric field is applied across a dielectric, the dipoles tend to align themselves with the field direction, produced by small shifts in the positions  of atoms and shifts in the distributions of electronic charge in the crystal structure. After the charge is removed, the dipoles retain their polarization state. Binary "0"s and "1"s are stored as one of two possible electric polarizations in each data storage cell. For example, in the figure a "1" is encoded using the negative remnant polarization "-Pr", and a "0" is encoded using the positive remnant polarization "+Pr". In terms of operation, FeRAM is similar to DRAM. Writing is accomplished by applying a field across the ferroelectric layer by charging the plates on either side of it, forcing  the atoms inside into the "up" or "down" orientation (depending on the polarity of the charge), thereby storing a "1" or "0". Reading, however, is somewhat different than in DRAM. The transistor forces the cell into a particular state, say "0". If the cell already held a "0", nothing will happen in the output lines. If the cell held a "1", the re-orientation of the atoms in the film will cause a brief pulse of current in the output as they push electrons out of the metal on the "down" side. The presence of this pulse means the cell  held a "1". Since this process overwrites the cell, reading FeRAM is a destructive process, and requires the cell to be re-written. In general, the operation of FeRAM is similar to ferrite core memory, one of the primary forms of computer memory in the 1960s. However, compared to core memory, FeRAM requires far less power to flip the state of the polarity and does so much faster. Comparison with other memory types. Density. The main determinant of a memory system's cost is the density of the components used to make it up. Smaller components, and fewer of them , means that more cells can be packed onto a single chip, which in turn means more can be produced at once from a single silicon wafer. This improves yield, which is directly related to cost. The lower limit to this scaling process is an important point of comparison. In general, the technology that scales to the smallest cell size will end up being the least expensive per bit. In terms of construction, FeRAM and DRAM are similar, and can in general be built on similar lines at similar sizes. In both cases, the lower limit seems to be defined by  the amount of charge needed to trigger the sense amplifiers. For DRAM, this appears to be a problem at around 55 nm, at which point the charge stored in the capacitor is too small to be detected. It is not clear whether FeRAM can scale to the same size, as the charge density of the PZT layer may not be the same as the metal plates in a normal capacitor. An additional limitation on size is that materials tend to stop being ferroelectric when they are too small. (This effect is related to the ferroelectric's "depolarization field".) There is  ongoing research on addressing the problem of stabilizing ferroelectric materials; one approach, for example, uses molecular adsorbates. To date, the commercial FeRAM devices have been produced at 350 nm and 130 nm. Early models required two FeRAM cells per bit, leading to very low densities, but this limitation has since been removed. Power consumption. The key advantage to FeRAM over DRAM is what happens "between" the read and write cycles. In DRAM, the charge deposited on the metal plates leaks across the insulating layer and the control transistor, and disappears. In order for a DRAM to store data for anything  other than a very short time, every cell must be periodically read and then re-written, a process known as "refresh". Each cell must be refreshed many times every second (typically 1000/64 round 0 times per second) and this requires a continuous supply of power. In contrast, FeRAM only requires power when actually reading or writing a cell. The vast majority of power used in DRAM is used for refresh, so it seems reasonable to suggest that the benchmark quoted by STT-MRAM researchers is useful here too, indicating power usage about 99% lower than DRAM. The destructive read aspect  of FeRAM may put it at a disadvantage compared to MRAM, however. Another non-volatile memory type is flash, and like FeRAM it does not require a refresh process. Flash works by pushing electrons across a high-quality insulating barrier where they get "stuck" on one terminal of a transistor. This process requires high voltages, which are built up in a charge pump over time. This means that FeRAM could be expected to be lower power than flash, at least for writing, as the write power in FeRAM is only marginally higher than reading. For a "mostly-read" device the  difference might be slight, but for devices with more balanced read and write the difference could be expected to be much higher. Reliability. Data reliability is guaranteed in F-RAM even in a high magnetic field environment compared to MRAM. Cypress Semiconductor's F-RAM devices are immune to the strong magnetic fields and do not show any failures under the maximum available magnetic field strengths (3,700 Gauss for horizontal insertion and 2,000 Gauss for vertical insertion). In addition, the F-RAM devices allow rewriting with a different data pattern after exposure to the magnetic fields. Performance. DRAM performance is  limited by the rate at which the charge stored in the cells can be drained (for reading) or stored (for writing). In general, this ends up being defined by the capability of the control transistors, the capacitance of the lines carrying power to the cells, and the heat that power generates. FeRAM is based on the physical movement of atoms in response to an external field, which is extremely fast, averaging about 1 ns. In theory, this means that FeRAM could be much faster than DRAM. However, since power has to flow into the cell for reading and writing, the  electrical and switching delays would likely be similar to DRAM overall. It does seem reasonable to suggest that FeRAM would require less charge than DRAM, because DRAMs need to "hold" the charge, whereas FeRAM would have been written to before the charge would have drained. However, there is a delay in writing because the charge has to flow through the control transistor, which limits current somewhat. In comparison to flash, the advantages are much more obvious. Whereas the read operation is likely to be similar in performance, the charge pump used for writing requires a considerable time to "build up