Compute Express Link
Compute Express Link (CXL) is an open standard for high-speed central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the PCI Express (PCIe) physical and electrical interface and includes PCIe-based block input/output protocol (CXL.io) and new cache-coherent protocols for accessing system memory (CXL.cache) and device memory (CXL.mem). History. The standard was primarily developed by Intel. The CXL Consortium was formed in March 2019 by founding members Alibaba Group, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, Intel and Microsoft , and officially incorporated in September 2019. As of January 2022, AMD, NVidia, Samsung and Xilinx joined the founders on the board of directors, while ARM, Broadcom, Ericsson, IBM, Keysight, Kioxia, Marvell, Mellanox, Microchip, Micron, Oracle, Qualcomm, Rambus, Renesas, Seagate, SK Hynix, Synopsys, and Western Digital, among others, joined as contributing members. Industry partners include the PCI-SIG, Gen-Z, SNIA, and DMTF. On April 2, 2020, the Compute Express Link and Gen-Z Consortiums announced plans to implement interoperability between the two technologies, with initial results presented in January 2021. On November 10, 2021, Gen-Z specifications and assets were  transferred to CXL, to focus on developing a single industry standard moving forward. At the time of this announcement, 70% of Gen-Z members already joined the CXL Consortium, which now includes companies behind memory coherent interconnect technologies such as OpenCAPI (IBM), CCIX (Xilinx), and Gen-Z (HPE) open standards, and proprietary InfiniBand / RoCE (Mellanox), Infinity Fabric (AMD), Omni-Path and QuickPath/Ultra Path (Intel), and NVLink/NVSwitch (Nvidia) protocols. Specifications. On March 11, 2019, the CXL Specification 1.0 based on PCIe 5.0 was released. It allows host CPU to access shared memory on accelerator devices with a cache coherent  protocol. The CXL Specification 1.1 was released in June, 2019. On November 10, 2020, the CXL Specification 2.0 was released. The new version adds support for CXL switching, to allow connecting multiple CXL 1.x and 2.0 devices to a CXL 2.0 host processor, and/or pooling each device to multiple host processors, in distributed shared memory and disaggregated storage configurations; it also implements device integrity and data encryption. There is no bandwidth increase from CXL 1.x, because CXL 2.0 still utilizes PCIe 5.0 PHY. Next version of CXL specifications is expected in H1 2022, to be based on PCIe 6.0 PHY . Implementations. On April 2, 2019, Intel announced their family of Agilex FPGAs featuring CXL. On May 11, 2021, Samsung announced a DDR5 based memory expansion module that allows for terabyte level memory expansion along with high performance for use in data centres and potentially next generation PCs. In 2021, CXL 1.1 support was announced for Intel Sapphire Rapids processors and AMD Zen 4 EPYC "Genoa" and "Bergamo" processors. CXL devices were shown at the SC21 conference by Intel, Astera, Rambus, Synopsys, Samsung, and Teledyne LeCroy, among others. Protocols. The CXL standard defines three separate protocols: CXL.cache and CXL.mem protocols operate  with a common link/transaction layer, which is separate from the CXL.io protocol link and transaction layer. These protocols/layers are multiplexed together by an Arbitration and Multiplexing (ARB/MUX) block before being transported over standard PCIe 5.0 PHY using fixed-width 528 bit (66 byte) Flow Control Unit (FLIT) block consisting of four 16-byte data 'slots' and a two-byte cyclic redundancy check (CRC) value. CXL FLITs encapsulate PCIe standard Transaction Layer Packet (TLP) and Data Link Layer Packet (DLLP) data with a variable frame size format. Device types. CXL is designed to support three primary device types : Type 2 devices implement two memory coherence modes, managed by device driver. In device bias mode, device directly accesses local memory and no caching is performed by the CPU; in host bias mode, the host CPU's cache controller handles all access to device memory. Coherence mode can be set individually for each 4 KB page, stored in a translation table in local memory of Type 2 devices. Unlike other CPU-to-CPU memory coherency protocols, this arrangement only requires the host CPU memory controller to implement the cache agent; such asymmetric approach reduces implementation complexity and reduces latency. Compute