EnCore Processor
The EnCore microprocessor family is a "configurable" and "extendable" implementation of a compact 32-bit RISC instruction set architecture - developed by the PASTA Research Group at the University of Edinburgh School of Informatics. The following are key features of the EnCore microprocessor family: All of the EnCore test chips are named after hills in Edinburgh; Calton, being the smallest, is the first of these. The second, Castle, is named after the rock on which Edinburgh Castle is built. EnCore Calton. The first silicon implementation of the EnCore processor is a test-chip code-named Calton, fabricated in a  generic 130nm CMOS process using a standard ASIC flow. EnCore Castle. The second silicon implementation of an extended EnCore processor is a test-chip codenamed Castle, fabricated in a generic 90nm CMOS process. The Castle chip contains an extended version of the EnCore processor, together with a 32KB 4-way set-associative Instruction Cache, and a 32KB 4-way set-associative Data Cache. It is embedded within a system-on-chip (SoC) design that provides a generic 32-bit memory interface, as well as interrupt, clocks and reset signals.