Assertion: semiconductor | /r/HasProperty | common test terminal
Facets:
Source sentences:
text: In an aspect of this disclosure, there is provided a semiconductor device comprising a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias; a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via; and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.