Assertion: reset | /r/HasProperty | asserted
Facets:
Source sentences:
text: When reset is asserted, it propagates to all designs; brings them to reset state whether or not clock is toggling; i.e. assertion should be asynchronous When reset is deasserted, wait for a clock edge, and then, move the system to next state as per the FSM (Finite State Machine)
text: The circuit that manipulates the asynchronous reset to have asynchronous assertion and synchronous deassertion is referred as: When the reset is asserted, it first propagates to reset synchronizer flops.