Assertion: ram's data | /r/CapableOf | come out in same cycle
Facets:
value: in separate cycles
type: TEMPORAL
Source sentences:
text: Eventually the simple processor will put the address on the edge of the processor core, with a write strobe and data, each processors bus is different than other processor families, but it is roughly the same the address and data can come out in the same cycle or in separate cycles.