Assertion: interrupt | /r/HasProperty | set
Facets:
Source sentences:
text: All these interrupts can be set or cleared by bit in some special function register that is Interrupt Enabled (IE), and this in turn depends on the priority, which is executed by IP interrupt priority register.
text: All the interrupts can be set or cleared by some special function register that is also known as interrupt enabled (IE), and it is totally depends on the priority, which is executed by using interrupt priority register.
text: So if, for example, PORT1 has its interrupt enabled and pin P1_2 changed its value so its flag was set in the GPIO peripheral and the PORT1 interrupt flag was also set, the interrupt controller would interrupt the CPU to handle that interrupt.
text: The higher priority interrupt flag is set after the CPU has started handling the lower priority interrupt.