Assertion: priority interrupt | /r/HasProperty | occurred to the processor
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Source sentences:
text: they are Maskable Interrupt: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor.
text: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor.
text: Maskable Interrupt: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor.
text: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor.