Assertion: interrupt | /r/HasProperty | masked
Facets:
value: automatically
type: MANNER
Source sentences:
text: FIQ and IRQ interrupts are automatically masked by setting the CPSR.F and CPSR.I bits when an FIQ occurs.
text: It's also important to have your ISR complete quickly as while the CPU is servicing one ISR other interrupts will be masked, which means if the CPU can't get to them quickly enough data can be lost.
text: When an interrupt is masked, it still gets detected.