Assertion: interrupt | /r/HasProperty | allowed
Facets:
Source sentences:
text: This is for good reason: further interrupts are allowed only when enough of the processor context has been saved onto the interrupt stack.
text: If BASEPRI is zero, then the priority feature is disabled and all interrupts are allowed.
text: Here is a simple example of handling the interrupts from TMR0 (if no other interrupts are allowed):
text: So, you proceed to the next place where an interrupt is allowed - any instruction boundary, typically - and THEN throw away all of the instructions in the pipeline.