Assertion: instruction | /r/HasProperty | introduced by amd
Facets:
value: with the sse4a instruction set
type: OTHER
Source sentences:
text: These instructions operate on integer rather than SSE registers, because they are not SIMD instructions, but appear at the same time and although introduced by AMD with the SSE4a instruction set, they are counted as separate extensions with their own dedicated CPUID bits to indicate support.