Assertion: multiplexer's input | /r/HasProperty | blocked
Facets:
Source sentences:
text: From the truth table above, we can see that when the data select input, A is LOW at logic 0, input I 1 passes its data through the NAND gate multiplexer circuit to the output, while input I 0 is blocked.
text: In this scenario, the MUX will allow only D2 to pass through it and other input will be blocked.