Assertion: latch's output | /r/CapableOf | get stored in the latch
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text: Now if R goes back to 0, the circuit remains in the Reset state i.e in another word if we remove the inputs i.e. S=0 and R= 0, then let if Q’ =1 then again by using the property of NOR gate Q becomes 0, it seems we get the previous output which gets stored in the latch, therefore S=0 and R=0 are called as memory condition.