Assertion: latch | /r/HasProperty | created
Facets:
value: from if statements
type: OTHER
value: from incomplete case
type: OTHER
Source sentences:
text: Latches are created when you create a combinational process or conditional assignment (in VHDL) or a combinational always block (in Verilog) with an output that is not assigned under all possible input conditions.
text: Latches may be generated from incomplete case or if statements.