Assertion: interrupt | /r/HasProperty | handled
Facets:
value: correctly
type: MANNER
value: currently
type: TEMPORAL
value: mostly
type: DEGREE
value: efficiently
type: DEGREE
value: effectively
type: MANNER
Source sentences:
text: Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate physical conductor, many more distinct interrupts can be efficiently handled.
text: Edge-triggered interrupts keep the firmware's code complexity low, reduce the number of conditions for firmware, and provide more flexibility when interrupts are handled.
text: An interrupt vector is the memory location of an interrupt handler, which prioritizes interrupts and saves them in a queue if more than one interrupt is waiting to be handled.
text: Interrupt numbers 0 to 15 contain the faults, software interrupt and SysTick; these interrupts will be handled differently from interrupts 16 and up.
text: If interrupts are disabled, then that interrupt will be handled when they are enabled again, in priority order.
text: These interrupts are handled mostly as I/O interrupts; we discuss the peculiar characteristics of timer interrupts in Chapter 6 .
text: Indeed, the IRQ_PENDING , IRQ_INPROGRESS , and IRQ_DISABLED flags ensure that interrupts are correctly handled even when the hardware is misbehaving.
text: Every interrupt service routine returns the value 1 if the interrupt has been effectively handled, that is, if the signal was raised by the hardware device handled by the interrupt service routine (and not by another device sharing the same IRQ); it returns the value 0 otherwise.
text: When the interrupt has been handled, the CPU's state is restored and the interrupt is dismissed.
text: While an interrupt is being handled, nothing else will happen.
text: The common interrupt handler code changes the interrupt level to disable all low priority interrupts than the interrupt currently being handled.
text: A short IRQ is one which is expected to take a very short period of time, during which the rest of the machine will be blocked and no other interrupts will be handled.
text: If interrupts are disabled, then that interrupt will be handled when they are enabled again, in priority order.