Assertion: interrupt's priority | /r/HasProperty | represented in the sfr ipcy
Facets:
Source sentences:
text: With interrupts enabled, the CPU jumps to an ISR when three conditions are satisfied: (1) the specific IRQ has been enabled by setting a bit to 1 in the SFR IECx (one of three Interrupt Enable Control SFRs, with x equal to 0, 1, or 2); (2) an event causes a 1 to be written to the corresponding bit of the SFR IFSx (Interrupt Flag Status); and (3) the priority of the interrupt vector, as represented in the SFR IPCy (one of 16 Interrupt Priority Control SFRs, y = 0 to 15), is greater than the current priority of the CPU.