Assertion: multiplexer's output | /r/HasProperty | the inverse of this input
Facets:
Source sentences:
text: Gate 3 will therefore always have one of its inputs held at logic 1, because either gate 1 or gate 2 is disabled, whilst the other input to gate 3 will be either A or B. Gate 3 output will be the inverse of this input, so the result at the output X will be either A or B depending on the state of the control line, as can be seen from Table 4.2.2.
text: From the truth table for a NAND gate shown in Table 4.2.1 it can be seen that if one of the inputs (e.g. input A) is kept at logic 1, then the output will be the inverse of the other input.