Assertion: fet's gate | /r/HasProperty | applied
Facets:
Source sentences:
text: When the Large negative bias is applied: When the large negative gate to source voltage is applied, then this large negative electric field will contribute to increment of the width of the depletion region.
text: " RESISTANCE r DS(on) is the DC resistance between the Drain and Source terminals when a specified gate to source voltage is applied to bias the FET to the on-state.