Assertion: flop's d | /r/CapableOf | fall below 50% of v dd
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text: For example, the time between point (a) in Fig.5.3.9, where D initially falls below 50% of V DD and the time when CK rises to its trigger threshold of 50% V DD (point b) is called the set up time (t setup or t su ), and in 74HC series ICs this will typically be between 5ns and 15ns.