Assertion: flop's output | /r/HasProperty | high
Facets:
value: for those few milliseconds
type: TEMPORAL
Source sentences:
text: Because the inputs aren’t both HIGH, the output from the NAND gate at point 2 is HIGH.
text: However, it takes a few milliseconds for the inverter to respond, so for those few milliseconds, the output from the inverter is still HIGH.
text: The output from the edge detector is high so Q changes to match D.
text: both S and R are high causing the non-allowed state where both outputs are high.
text: When the Clock pulse is high the output of master is high and remains high till the clock is low because the state is stored.
text: The difference with a real edge-triggered D -flip-flop is that the output will change with the input as long as \$CLK\$ is high.