Assertion: flop's input | /r/AtLocation | logic
Facets:
value: similarly
type: DEGREE
value: during the change
type: TEMPORAL
value: until time
type: TEMPORAL
value: in row
type: LOCATION
value: normally
type: DEGREE
Source sentences:
text: When both the J and K input are at logic
text: In row 6 both inputs are at logic 1 and the outputs are shown as ‘indeterminate’, this means that although Q and Q will be at opposite logic states it is not certain whether Q will be 1 or 0,
text: Notice however that in the absence of any input pulses, both inputs are normally at logic 1.
text: During this time S returns to logic 1, therefore both inputs will be at logic 1 until time
text: Although, during the change over of SW1 both inputs are at logic 1, this does not produce the indeterminate state described in Table 5.2.1, as one or other of the inputs is always at logic 0 before both inputs become logic 1.
text: If both inputs are at logic 1, Q is the same as Q (the non-allowed state).
text: Similarly if a D input is at logic 0 the output of the left hand NAND gate of the pair will be Logic 0 and the right hand gate output will be logic 1, which will clear the Q output of the flip-flop.
text: Both the inputs of the NAND gates X are at logic