Assertion: flop's input | /r/HasProperty | low
Facets:
value: in storage mode
type: OTHER
value: normally
type: DEGREE
value: at the beginning of the diagram
type: OTHER
Source sentences:
text: The inverter causes the first input to the NAND gate (marked 1) to be HIGH, while the second input is LOW.
text: At the beginning of the diagram, the inputs to the D and CLK pins are LOW, and the Q output also happens to be LOW.
text: In "D", we now force U1-1 low while leaving U2-2 high, which will drive Q high and SET the latch, and since the inputs of U1 are now both lows, its output will go high and force U2-1 high assuring the latch will stay SET no matter what U2-2 does.
text: While the R and S inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
text: When both inputs are low, the current state is retained.
text: When both inputs are low, the latch "latches" – it remains in its previously set or reset state.
text: When the Enable input is low, then the outputs from the AND gates must also be low, thus the Q and Q outputs remain latched to the previous data.
text: Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low even after R returns low.
text: Now, even when \$/S\$ goes high again, the other input will be low, so the output \$Q\$ retains its state.
text: If \$CLK\$ is low both inputs of the SR flip-flop are high, and it retains its output state.
text: Where I am running into problems is knowing when CLRN, PRN, and the input will be high or low.