Assertion: fet's gate | /r/CapableOf | operate in linear region
Facets:
Source sentences:
text: Logic families built in older processes that did not support depletion-mode transistors were retrospectively referred to as enhancement-load logic, or as saturated-load logic, since the enhancement-mode transistors were typically connected with gate to the V DD supply and operated in the saturation region (sometimes the gates are biased to a higher V GG voltage and operated in the linear region, for a better power–delay product (PDP), but the loads then take more area).