Assertion: flop's input | /r/Causes | master latch
Facets:
value: to transition
type: PURPOSE
Source sentences:
text: Assuming the use of a positive edge triggered "D" type flip-flop, when the rising edge of the flip-flop clock occurs at a point in time when the D input to the flip-flop is causing its master latch to transition, the flip-flop is highly likely to end up in a quasi-stable state.