Assertion: flop's output | /r/HasProperty | low
Facets:
value: like the clock input
type: OTHER
Source sentences:
text: so the final output from the circuit at point 3 is LOW, just like the clock input.
text: The output from the edge detector in this diagram is low
text: When the device is powered up, a similar condition occurs, because both outputs, Q and Q, are low.
text: When the Enable input is low, then the outputs from the AND gates must also be low, thus the Q and Q outputs remain latched to the previous data.
text: When the output of NAND gate is low, the flip flops will reset so does the counter output.