Assertion: cpu | /r/HasAspect | fpu
Facets:
value: typically
type: DEGREE
Source sentences:
text: While processor architectures differ between models, each processor within a CPU typically has its own ALU, FPU, register, and L1 cache.
text: While processor architectures differ between models, each processor within a CPU typically has its own ALU, FPU, register, and L1 cache.