Assertion: cpu | /r/HasAspect | l1 cache
Facets:
value: typically
type: DEGREE
value: on multi-core systems
type: LOCATION
Source sentences:
text: While processor architectures differ between models, each processor within a CPU typically has its own ALU, FPU, register, and L1 cache.
text: Some processors might have two L1 caches, one for instructions and one for data.
text: On multi-core systems, each processor typically has its own L1 cache.
text: While processor architectures differ between models, each processor within a CPU typically has its own ALU, FPU, register, and L1 cache.