  In this paper, we propose an image compression algorithm called Microshift.
We employ an algorithm hardware co-design methodology, yielding a
hardware-friendly compression approach with low power consumption. In our
method, the image is first micro-shifted, then the sub-quantized values are
further compressed. Two methods, the FAST and MRF model, are proposed to
recover the bit-depth by exploiting the spatial correlation of natural images.
Both methods can decompress images progressively. Our compression algorithm
compresses images to 1.25 bits per pixel on average with PSNR of 33.16 dB,
outperforming other on-chip compression algorithms. Then, we propose a hardware
architecture and implement the algorithm on an FPGA and ASIC. The results on
the VLSI design further validate the low hardware complexity and high power
efficiency, showing our method is promising, particularly for low-power
wireless vision sensor networks.
