  This paper presents an extension to an existing instruction set architecture,
which gains considerable reduction in power consumption. The reduction in power
consumption is achieved through coding of the most commonly executed
instructions in a short format done by the compiler based on a profile of
previous executions. This leads to fewer accesses to the instruction cache and
that more instructions can fit in the cache. As a secondary effect, this turned
out to be very beneficial in terms of power. Another major advantage, which is
the main concern of this paper is the reduction in the number of instruction
fetch cycles which will also contribute significantly towards reduction in
power consumption. The work involves implementing the new processor
architecture in ASIC and estimation of power-consumption compared to the normal
architecture.
