  The increasing complexity in today's systems and the limited market times
demand new development tools for FPGA. Currently, in addition to traditional
hardware description languages (HDLs), there are high-level synthesis (HLS)
tools that increase the abstraction level in system development. Despite the
greater simplicity of design and testing, HLS has some drawbacks in describing
harware. This paper presents a comparative study between HLS and HDL for FPGA,
using a Sobel filter as a case study in the image processing field. The results
show that the HDL implementation is slightly better than the HLS version
considering resource usage and response time. However, the programming effort
required in the HDL solution is significantly larger than in the HLS
counterpart.
