  Data are presented on inductance of various features used in superconductor
digital integrated circuits such as microstrip and stripline inductors with
linewidths down to 120 nm and different combinations of ground plane layers,
effect of perforations of various sizes in the ground planes and their distance
to the inductors on inductance, inductance of vias of various sizes between
adjacent layers and composite vias between distant superconducting layers.
Effects of magnetic flux trapping in ground plane moats on coupling to nearby
inductors are discussed for circuit cooling in a residual field of several
configurations. Test circuits used for the measurements were fabricated in a
new 150-nm node of a fully planarized process with eight niobium layers, SC2
process, developed at MIT Lincoln Laboratory for superconductor electronics and
in its 250-nm node SC1, as well as in the standard fabrication process SFQ5ee.
The SC2 process utilizes 193-nm photolithography in combination with plasma
etching and chemical mechanical planarization of interlayer dielectrics to
define inductors with linewidth down to about 100 nm on critical layers. All
other processes use 248 nm photolithography. Effects of variation of process
parameters on circuit inductors are discussed. The measured data are compared
with the results of inductance extraction using software packages InductEx and
wxLC. Part II is devoted to mutual inductance of various closely spaced
features in integrated circuits, meanders, and transformers.
