  This paper presents TULIP, a new architecture for a binary neural network
(BNN) that uses an optimal schedule for executing the operations of an
arbitrary BNN. It was constructed with the goal of maximizing energy efficiency
per classification. At the top-level, TULIP consists of a collection of unique
processing elements (TULIP-PEs) that are organized in a SIMD fashion. Each
TULIP-PE consists of a small network of binary neurons, and a small amount of
local memory per neuron. The unique aspect of the binary neuron is that it is
implemented as a mixed-signal circuit that natively performs the inner-product
and thresholding operation of an artificial binary neuron. Moreover, the binary
neuron, which is implemented as a single CMOS standard cell, is reconfigurable,
and with a change in a single parameter, can implement all standard operations
involved in a BNN. We present novel algorithms for mapping arbitrary nodes of a
BNN onto the TULIP-PEs. TULIP was implemented as an ASIC in TSMC 40nm-LP
technology. To provide a fair comparison, a recently reported BNN that employs
a conventional MAC-based arithmetic processor was also implemented in the same
technology. The results show that TULIP is consistently 3X more
energy-efficient than the conventional design, without any penalty in
performance, area, or accuracy.
