  V$_3$Si thin films are known to be superconducting with transition
temperatures up to 15 K, depending on the annealing temperature and the
properties of the substrate underneath. Here we investigate the film structural
properties with the prospect of further integration in silicon technology for
quantum circuits. Two challenges have been identified: (i) the large difference
in thermal expansion rate between V$_3$Si and the Si substrate leads to large
thermal strains after thermal processing, and (ii) the undesired silicide phase
VSi$_2$ forms when V$_3$Si is deposited on silicon. The first of these is
studied by depositing layers of 200 nm V$_3$Si on wafers of sapphire and
oxidized silicon, neither of which react with the silicide. These samples are
then heated and cooled between room temperature and 860{\deg}C, during which
in-situ XRD measurements are performed. Analysis reveals a highly non-linear
stress development during heating with contributions from crystallization and
subsequent grain growth, as well as the thermal expansion mismatch between
silicide and substrate, while the film behaves thermoelastically during
cooling. The second challenge is explored by depositing films of 20, 50, 100
and 200 nm of V$_3$Si on bulk silicon. For each thickness, six samples are
prepared, which are then annealed at temperatures between 500 and 750{\deg}C,
followed by measurements of their resistivity, residual resistance ratio and
superconducting critical temperature. A process window is identified for
silicide thicknesses of at least 100 nm, within which a trade-off needs to be
made between the quality of the V$_3$Si film and its consumption by the
formation of VSi$_2$.
