  Hyperdimensional computing (HDC) is a brain-inspired computing paradigm based
on high-dimensional holistic representations of vectors. It recently gained
attention for embedded smart sensing due to its inherent error-resiliency and
suitability to highly parallel hardware implementations. In this work, we
propose a programmable all-digital CMOS implementation of a fully autonomous
HDC accelerator for always-on classification in energy-constrained sensor
nodes. By using energy-efficient standard cell memory (SCM), the design is
easily cross-technology mappable. It achieves extremely low power, 5 $\mu W$ in
typical applications, and an energy-efficiency improvement over the
state-of-the-art (SoA) digital architectures of up to 3$\times$ in post-layout
simulations for always-on wearable tasks such as EMG gesture recognition. As
part of the accelerator's architecture, we introduce novel hardware-friendly
embodiments of common HDC-algorithmic primitives, which results in 3.3$\times$
technology scaled area reduction over the SoA, achieving the same accuracy
levels in all examined targets. The proposed architecture also has a fully
configurable datapath using microcode optimized for HDC stored on an integrated
SCM based configuration memory, making the design "general-purpose" in terms of
HDC algorithm flexibility. This flexibility allows usage of the accelerator
across novel HDC tasks, for instance, a newly designed HDC applied to the task
of ball bearing fault detection.
