  Crossbar resistive memory with the 1 Selector 1 Resistor (1S1R) structure is
attractive for nonvolatile, high-density, and low-latency storage-class memory
applications. As technology scales down to the single-nm regime, the increasing
resistivity of wordline/bitline becomes a limiting factor to device
reliability. This paper presents write/read communication channels while
considering the line resistance and device variabilities by statistically
relating the degraded write/read margins and the channel parameters. Binary
asymmetric channel (BAC) models are proposed for the write/read operations.
Simulations based on these models suggest that the bit-error rate of devices
are highly non-uniform across the memory array. These models provide
quantitative tools for evaluating the trade-offs between memory reliability and
design parameters, such as array size, technology nodes, and aspect ratio, and
also for designing coding-theoretic solutions that would be most effective for
crossbar memory. Method for optimizing the read threshold is proposed to reduce
the raw bit-error rate (RBER). We propose two schemes for efficient channel
coding based on Bose-Chaudhuri-Hocquenghem (BCH) codes. An interleaved coding
scheme is proposed to mitigate the non-uniformity of reliability and a location
dependent coding framework is proposed to leverage this non-uniformity. Both of
our proposed coding schemes effectively reduce the undetected bit-error rate
(UBER).
