  The analog front-end for the Low Gain Avalanche Detector (LGAD) based
precision timing application in the CMS Endcap Timing Layer (ETL) has been
prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first
prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the
performance of the analog frontend, with the goal to achieve 40 to 50 ps time
resolution per hit with LGAD (therefore reach about 30ps per track with two
detector-layer hits per track). ETROC0 consists of preamplifier and
discriminator stages, which amplifies the LGAD signal and generates digital
pulses containing time of arrival and time over threshold information. This
paper will focus on the design considerations that lead to the ETROC front-end
architecture choice, the key design features of the building blocks, the
methodology of using the LGAD simulation data to evaluate and optimize the
front-end design. The ETROC0 prototype chips have been extensively tested using
charge injection and the measured performance agrees well with simulation. The
initial beam test results are also presented, with time resolution of around 33
ps observed from the preamplifier waveform analysis and around 41 ps from the
discriminator pulses analysis. A subset of ETROC0 chips have also been tested
to a total ionizing dose of 100 MRad with X-ray and no performance degradation
been observed.
