  With the growing number of data-intensive workloads, GPU, which is the
state-of-the-art single-instruction-multiple-thread (SIMT) processor, is
hindered by the memory bandwidth wall. To alleviate this bottleneck, previously
proposed 3D-stacking near-bank computing accelerators benefit from abundant
bank-internal bandwidth by bringing computations closer to the DRAM banks.
However, these accelerators are specialized for certain application domains
with simple architecture data paths and customized software mapping schemes.
For general purpose scenarios, lightweight hardware designs for diverse data
paths, architectural supports for the SIMT programming model, and end-to-end
software optimizations remain challenging.
  To address these issues, we propose MPU (Memory-centric Processing Unit), the
first SIMT processor based on 3D-stacking near-bank computing architecture.
First, to realize diverse data paths with small overheads while leveraging
bank-level bandwidth, MPU adopts a hybrid pipeline with the capability of
offloading instructions to near-bank compute-logic. Second, we explore two
architectural supports for the SIMT programming model, including a near-bank
shared memory design and a multiple activated row-buffers enhancement. Third,
we present an end-to-end compilation flow for MPU to support CUDA programs. To
fully utilize MPU's hybrid pipeline, we develop a backend optimization for the
instruction offloading decision. The evaluation results of MPU demonstrate
3.46x speedup and 2.57x energy reduction compared with an NVIDIA Tesla V100 GPU
on a set of representative data-intensive workloads.
