  Specialized hardware accelerators are becoming important for more and more
applications. Thanks to specialization, they can achieve high performance and
energy efficiency but their design is complex and time consuming. This problem
is exacerbated when large amounts of data must be processed, like in modern big
data and machine learning applications. The designer has not only to optimize
the accelerator logic but also produce efficient memory architectures. To
simplify this process, we propose a multi-level compilation flow that
specializes a domain-specific memory template to match data, application, and
technology requirements.
