  The continuous scaling of semiconductor technology has pushed the footprint
of logic devices below 50 nm. Currently, logic standard cells with one single
fin are being investigated to increase the integration density, although such
options could severely limit the performance of individual devices. In this
letter, we present a novel Trench (T-) FinFET device, composed of a monolayer
two-dimensional (2D) channel material. The device characteristics of a
monolayer WS$_2$-based T-FinFET are studied by combining the first-principles
calculations and quantum transport (QT) simulations. These results serve as
inputs to a predictive analytical model. The latter allows to benchmark the
T-FinFET with strained (s)-Si FinFETs in both quasi-ballistic and diffusive
transport regimes. The circuit-level evaluation highlights that WS$_2$
T-FinFETs exhibit a competitive energy-delay performance compared to s-Si
FinFET and WS$_2$ double-gate transistors, assuming the same mobility and
contact resistivity at small footprints.
