  This paper introduces two architectures for the inference of convolutional
neural networks (CNNs). Both architectures exploit weight sparsity and
compression to reduce computational complexity and bandwidth. The first
architecture uses multiply-accumulators (MACs) but avoids unnecessary
multiplications by skipping zero weights. The second architecture exploits
weight sparsity at the level of their bit representation by substituting
resource-intensive MACs with much smaller Bit Layer Multiply Accumulators
(BLMACs). The use of BLMACs also allows variable precision weights as variable
size integers and even floating points. Some details of an implementation of
the second architecture are given. Weight compression with arithmetic coding is
also discussed as well as bandwidth implications. Finally, some implementation
results for a pathfinder design and various technologies are presented.
