  The experiment of the future electron-positron colliders has unprecedented
requirements on the vertex resolution, such as around 3micron single point
resolution for the inner most detector layer, with fast readout, and very low
power-consumption density and material budget. Significant efforts have been
put into the development of monolithic silicon pixel sensors, but there have
been some challenges to combine all those stringent specifications in a small
pixel area. This paper presents a compact prototype pixel sensor fabricated in
LAPIS 200nm SOI process and focuses on the characterization of low capacitance
of the sensing node with a pinned depleted diode structure adopting a novel
method of forward bias voltage and AC coupling on the diode. Three PDD
structures with 16 micron by 20 micron pixel size were designed and compared
using radioactive sources and injected charge. The measured result shows that
the designed PDD structure has very low leakage current and around 3.5fF of
equivalent input capacitance.
