  The search for a compatible application of memristor-CMOS logic gates has
remained elusive, as the data density benefits are offset by slow switching
speeds and resistive dissipation. Active microdisplays typically prioritize
pixel density (and therefore resolution) over that of speed, where the most
widely used refresh rates fall between 25-240 Hz. Therefore, memristor-CMOS
logic is a promising fit for peripheral IO logic in active matrix displays. In
this paper, we design and implement a ternary 1-3 line decoder and a ternary
2-9 line decoder which are used to program a seven segment LED display. SPICE
simulations are conducted in a 50-nm process, and the decoders are synthesized
on an Altera Cyclone IV field-programmable gate array (FPGA) development board
which implements a ternary memristor model designed in Quartus II. We compare
our hardware results to a binary coded decimal (BCD)-to-seven segment display
decoder, and show our memristor-CMOS approach reduces the total IO power
consumption by a factor of approximately 6 times at a maximum synthesizable
frequency of 293.77MHz. Although the speed is approximately half of the native
built-in BCD-to-seven decoder, the comparatively slow refresh rates of typical
microdisplays indicate this to be a tolerable trade-off, which promotes data
density over speed.
