  In this paper, we present the design of a new chaotic map circuit with a 65nm
CMOS process. This chaotic map circuit uses a dynamic parameter-control
topology and generates a wide chaotic range. We propose two designs of dynamic
parameter-controlled chaotic map (DPCCM)-based pseudo-random number generators
(PRNG). The randomness of the generated sequence is verified using three
different statistical tests, namely, NIST SP 800-22 test, FIPS PUB 140-2 test,
and Diehard test. Our first design offers a throughput of 200 MS/s with an
on-chip area of 0.024mm2 and a power consumption of 2.33mW. The throughput of
our second design is 300 MS/s with an area consumption of 0.132mm2 and power
consumption of 2.14mW. The wider chaotic range and lower-overhead, offered by
our designs, can be highly suitable for various applications such as, logic
obfuscation, chaos-based cryptography, re-configurable random number
generation,and hard-ware security for resource-constrained edge devices like
IoT.
