  This paper discusses a detailed design approach to determine the optimal
input impedance (Rin) and bandwidth (BW) for current preamplifiers in Front End
Electronics (FEE) of high-accuracy time measurement systems used in particle
detection. Our study shows the effect of the input impedance Rin including the
parasitic interconnection inductances of bonding wires between the detector and
the FEE. We explain also the development of a new mathematical model for the
estimation of the timing jitter of the current preamplifier in the case of
using a low capacitor detector (Cd) as diamond. Different simulations based on
developed MATLAB Simulink behavioral models are done in addition to an electric
simulation of a transimpedance amplifier (TIA) designed in a 130 nm 1P8M CMOS
technology which demonstrates the accuracy of the design approach and the
timing jitter estimation model.
