  3D NAND flash memory with advanced multi-level cell techniques provides high
storage density, but suffers from significant performance degradation due to a
large number of read-retry operations. Although the read-retry mechanism is
essential to ensuring the reliability of modern NAND flash memory, it can
significantly increase the read latency of an SSD by introducing multiple retry
steps that read the target page again with adjusted read-reference voltage
values. Through a detailed analysis of the read mechanism and rigorous
characterization of 160 real 3D NAND flash memory chips, we find new
opportunities to reduce the read-retry latency by exploiting two advanced
features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ
command and 2) strong ECC engine. First, we can reduce the read-retry latency
using the advanced CACHE READ command that allows a NAND flash chip to perform
consecutive reads in a pipelined manner. Second, there exists a large
ECC-capability margin in the final retry step that can be used for reducing the
chip-level read latency. Based on our new findings, we develop two new
techniques that effectively reduce the read-retry latency: 1) Pipelined
Read-Retry (PR$^2$) and 2) Adaptive Read-Retry (AR$^2$). PR$^2$ reduces the
latency of a read-retry operation by pipelining consecutive retry steps using
the CACHE READ command. AR$^2$ shortens the latency of each retry step by
dynamically reducing the chip-level read latency depending on the current
operating conditions that determine the ECC-capability margin. Our evaluation
using twelve real-world workloads shows that our proposal improves SSD response
time by up to 31.5% (17% on average) over a state-of-the-art baseline with only
small changes to the SSD controller.
