  Recently there has been increasing activity to build dedicated Ising Machines
to accelerate the solution of combinatorial optimization problems by expressing
these problems as a ground-state search of the Ising model. A common theme of
such Ising Machines is to tailor the physics of underlying hardware to the
mathematics of the Ising model to improve some aspect of performance that is
measured in speed to solution, energy consumption per solution or area
footprint of the adopted hardware. One such approach to build an Ising spin, or
a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a
low-barrier nanomagnet based design that uses a single magnetic tunnel junction
(MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic
resistor (1SR). Such a compact unit can drastically reduce the area footprint
of BSNs while promising massive scalability by leveraging the existing Magnetic
RAM (MRAM) technology that has integrated 1T-1MTJ cells in ~Gbit densities. The
3T-1SR design however can be realized using different materials or devices that
provide naturally fluctuating resistances. Extending previous work, we evaluate
hardware BSNs from this general perspective by classifying necessary and
sufficient conditions to design a fast and energy-efficient BSN that can be
used in scaled Ising Machine implementations. We connect our device analysis to
systems-level metrics by emphasizing hardware-independent figures-of-merit such
as flips per second and dissipated energy per random bit that can be used to
classify any Ising Machine.
