  Gate-all-around nanowire transistor, due to its extremely tight electrostatic
control and vertical integration capability, is a highly promising candidate
for sub-5 nm technology node. In particular, the junctionless nanowire
transistors are highly scalable with reduced variability due to avoidance of
steep source/drain junction formation by ion implantation. Here we demonstrate
a dual-gated junctionless nanowire \emph{p}-type field effect transistor using
tellurium nanowire as the channel. The dangling-bond-free surface due to the
unique helical crystal structure of the nanowire, coupled with an integration
of dangling-bond-free, high quality hBN gate dielectric, allows us to achieve a
phonon-limited field effect hole mobility of $570\,\mathrm{cm^{2}/V\cdot s}$ at
270 K, which is well above state-of-the-art strained Si hole mobility. By
lowering the temperature, the mobility increases to
$1390\,\mathrm{cm^{2}/V\cdot s}$ and becomes primarily limited by Coulomb
scattering. \txc{The combination of an electron affinity of $\sim$4 eV and a
small bandgap of tellurium provides zero Schottky barrier height for hole
injection at the metal-contact interface}, which is remarkable for reduction of
contact resistance in a highly scaled transistor. Exploiting these properties,
coupled with the dual-gated operation, we achieve a high drive current of
$216\,\mathrm{\mu A/\mu m}$ while maintaining an on-off ratio in excess of
$2\times10^4$. The findings have intriguing prospects for alternate channel
material based next-generation electronics.
