  Modern SoC design relies on the ability to separately verify IP blocks
relative to their own specifications. Formal verification (FV) using
SystemVerilog Assertions (SVA) is an effective method to exhaustively verify
blocks at unit-level. Unfortunately, FV has a steep learning curve and requires
engineering effort that discourages hardware designers from using it during RTL
module development. We propose AutoSVA, a framework to automatically generate
FV testbenches that verify liveness and safety of control logic involved in
module interactions. We demonstrate AutoSVA's effectiveness and efficiency on
deadlock-critical modules of widely-used open-source hardware projects.
