  Recent advances in reprogrammable hardware (e.g., FPGAs) and memory
technology (e.g., DDR4, HBM) promise to solve performance problems inherent to
graph processing like irregular memory access patterns on traditional hardware
(e.g., CPU). While several of these graph accelerators were proposed in recent
years, it remains difficult to assess their performance and compare them on
common graph workloads and accelerator platforms, due to few open source
implementations and excessive implementation effort.
  In this work, we build on a simulation environment for graph processing
accelerators, to make several existing accelerator approaches comparable. This
allows us to study relevant performance dimensions such as partitioning schemes
and memory technology, among others. The evaluation yields insights into the
strengths and weaknesses of current graph processing accelerators along these
dimensions, and features a novel in-depth comparison.
