  Emerging non-volatile memory (NVM) technologies promise memory speed
byte-addressable persistent storage with a load/store interface. However,
programming applications to directly manipulate NVM data is complex and
error-prone. Applications generally employ libraries that hide the low-level
details of the hardware and provide a transactional programming model to
achieve crash-consistency. Furthermore, applications continue to expect
correctness during concurrent executions, achieved through the use of
synchronization. To achieve this, applications seek well-known ACID guarantees.
However, realizing this presents designers of transactional systems with a
range of choices in how to combine several low-level techniques, given target
hardware features and workload characteristics.
  In this paper, we provide a comprehensive evaluation of the impact of
combining existing crash-consistency and synchronization methods for achieving
performant and correct NVM transactional systems. We consider different
hardware characteristics, in terms of support for hardware transactional memory
(HTM) and the boundaries of the persistence domain (transient or persistent
caches). By characterizing persistent transactional systems in terms of their
properties, we make it possible to better understand the tradeoffs of different
implementations and to arrive at better design choices for providing ACID
guarantees. We use both real hardware with Intel Optane DC persistent memory
and simulation to evaluate a persistent version of hardware transactional
memory, a persistent version of software transactional memory, and undo/redo
logging. Through our empirical study, we show two major factors that impact the
cost of supporting persistence in transactional systems: the persistence domain
(transient or persistent caches) and application characteristics, such as
transaction size and parallelism.
