  The lack of an easily realizable complementary circuit technology offering
low static power consumption has been limiting the utilization of other
semiconductor materials than silicon. In this publication, a novel depletion
mode JFET based complementary circuit technology is presented and herein after
referred to as Complementary Semiconductor (CS) circuit technology. The fact
that JFETs are pure semiconductor devices, i.e. a carefully optimized Metal
Oxide Semiconductor (MOS) gate stack is not required, facilitates the
implementation of CS circuit technology to many semiconductor materials, like
e.g. germanium and silicon carbide. Furthermore, when the CS circuit technology
is idle there are neither conductive paths between nodes that are biased at
different potentials nor forward biased p-n junctions and thus it enables low
static power consumption. Moreover, the fact that the operation of depletion
mode JFETs does not necessitate the incorporation of forward biased p-n
junctions means that CS circuit technology is not limited to wide band-gap
semiconductor materials, low temperatures, and/or low voltage spans. In this
paper the operation of the CS logic is described and proven via simulations.
