  We present Calyx, a new intermediate language (IL) for compiling high-level
programs into hardware designs. Calyx combines a hardware-like structural
language with a software-like control flow representation with loops and
conditionals. This split representation enables a new class of hardware-focused
optimizations that require both structural and control flow information which
are crucial for high-level programming models for hardware design. The Calyx
compiler lowers control flow constructs using finite-state machines and
generates synthesizable hardware descriptions.
  We have implemented Calyx in an optimizing compiler that translates
high-level programs to hardware. We demonstrate Calyx using two DSL-to-RTL
compilers, a systolic array generator and one for a recent imperative
accelerator language, and compare them to equivalent designs generated using
high-level synthesis (HLS). The systolic arrays are $4.6\times$ faster and
$1.1\times$ larger on average than HLS implementations, and the HLS-like
imperative language compiler is within a few factors of a highly optimized
commercial HLS toolchain. We also describe three optimizations implemented in
the Calyx compiler.
