  This paper presents a new \b{eta}-Ga2O3 junctionless double gate
Metal-Oxide-Field-Semiconductor-Effect-Transistor (\b{eta}DG-JL-FET) that a P+
packet embedded in the oxide layer (PO-\b{eta}DG-JL-FET) for high-voltage
applications. Our goal is to achieve an efficient volume depletion region by
placing a P+ layer of silicon. We show that the proposed structure has a
subthreshold swing ~ 64 mV/decade and it suppressed the band to band tunneling
(BTBT) phenomenon. Also, the PO-\b{eta}DG-JL-FET structure has a high Ion/Ioff
~ 1.3e15. The embedded layer reduces the off-current (IOFF) by ~ 10-4, while
the on-current (ION) reduces slightly. Besides, we show that the proposed
structure has acceptable Ioff value in a range of gate work functions which
help us to the optimization of designs in terms of area, power gain, and
leakage current. The leakage current of the proposed structure is ~ 7e-17 A in
400 K temperature. Furthermore, the fabrication process steps of the proposed
structure will be investigated.
