  We describe via simulation novel optimization algorithms for a Hopfield
neural network constructed using manufacturable three-terminal
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic devices. We first present
a computationally-light, memristor-based, highly accurate compact model for the
SONOS. Using the compact model, we describe techniques of simulated annealing
in Hopfield networks by exploiting imperfect problem definitions, current
leakage, and the continuous tunability of the SONOS to enable transient chaotic
group dynamics. We project improvements in energy consumption and latency for
optimization relative to the best CPUs and GPUs by at least 4 orders of
magnitude, and also exceeding the best projected memristor-based hardware;
along with a 100-fold increase in error-resilient hardware size (i.e., problem
size).
