  Stencil computation is one of the most important kernels in various
scientific and engineering applications. A variety of work has focused on
vectorization techniques, aiming at exploiting the in-core data parallelism.
Briefly, they either incur data alignment conflicts or hurt the data locality
when integrated with tiling. In this paper, a novel transpose layout is devised
to preserve the data locality for tiling in the data space and reduce the data
reorganization overhead for vectorization simultaneously. We then propose an
approach of temporal computation folding designed to further reduce the
redundancy of arithmetic calculations by exploiting the register reuse,
alleviating the increased register pressure, and deducing generalization with a
linear regression model. Experimental results on the AVX-2 and AVX-512 CPUs
show that our approach obtains a competitive performance.
