  Recently, there has been an emergence of useful applications for noisy
intermediate-scale quantum (NISQ) devices notably, though not exclusively, in
the fields of quantum machine learning and variational quantum algorithms. In
such applications, circuits of various depths and composed of different sets of
gates are run on NISQ devices. Therefore, it is crucial to find practical ways
to capture the general performance of circuits on these devices. Motivated by
this pressing need, we modified the standard Clifford randomized benchmarking
(RB) and interleaved RB schemes targeting them to hardware limitations. Firstly
we remove the requirement for, and assumptions on, the inverse operator, in
Clifford RB by incorporating a tehchnique from quantum verification. This
introduces another figure of merit by which to assess the quality of the NISQ
hardware, namely the acceptance probability of quantum verification. Many
quantum algorithms, that provide an advantage over classical algorithms, demand
the use of Clifford as well as non-Clifford gates. Therefore, as our second
contribution we develop a technique for characterising a variety of
non-Clifford gates, by combining tools from gate synthesis with interleaved RB.
Both of our techniques are most relevant when used in conjunction with RB
schemes that benchmark generators (or native gates) of the Clifford group, and
in low error regimes.
