  Stereo matching is a critical task for robot navigation and autonomous
vehicles, providing the depth estimation of surroundings. Among all stereo
matching algorithms, Efficient Large-scale Stereo (ELAS) offers one of the best
tradeoffs between efficiency and accuracy. However, due to the inherent
iterative process and unpredictable memory access pattern, ELAS can only run at
1.5-3 fps on high-end CPUs and difficult to achieve real-time performance on
low-power platforms. In this paper, we propose an energy-efficient architecture
for real-time ELAS-based stereo matching on FPGA platform. Moreover, the
original computational-intensive and irregular triangulation module is reformed
in a regular manner with points interpolation, which is much more
hardware-friendly. Optimizations, including memory management, parallelism, and
pipelining, are further utilized to reduce memory footprint and improve
throughput. Compared with Intel i7 CPU and the state-of-the-art CPU+FPGA
implementation, our FPGA realization achieves up to 38.4x and 3.32x frame rate
improvement, and up to 27.1x and 1.13x energy efficiency improvement,
respectively.
