  The advanced complex electronic systems increasingly demand safer and more
secure hardware parts. Correspondingly, fault injection became a major
verification milestone for both safety- and security-critical applications.
However, fault injection campaigns for gate-level designs suffer from huge
execution times. Therefore, designers need to apply early design evaluation
techniques to reduce the execution time of fault injection campaigns. In this
work, we propose a method to represent gate-level Single-Event Transient (SET)
faults by multiple Single-Event Upset (SEU) faults at the Register-Transfer
Level. Introduced approach is to identify true and false logic paths for each
SET in the flip-flops fan-in logic cones to obtain more accurate sets of
flip-flops for multiple SEUs injections at RTL. Experimental results
demonstrate the feasibility of the proposed method to successfully reduce the
fault space and also its advantage with respect to state of the art. It was
shown that the approach is able to reduce the fault space, and therefore the
fault-injection effort, by up to tens to hundreds of times.
