  With the growing demands of consumer electronic products, the computational
requirements are increasing exponentially. Due to the applications'
computational needs, the computer architects are trying to pack as many cores
as possible on a single die for accelerated execution of the application
program codes. In a multiprocessor system-on-chip (MPSoC), striking a balance
among the number of cores, memory subsystems, and network-on-chip parameters is
essential to attain the desired performance. In this paper, we present
ANDROMEDA, a RISC-V based framework that allows us to explore the different
configurations of an MPSoC and observe the performance penalties and gains. We
emulate the various configurations of MPSoC on the Synopsys HAPS-80D Dual FPGA
platform. Using STREAM, matrix multiply, and N-body simulations as benchmarks,
we demonstrate our framework's efficacy in quickly identifying the right
parameters for efficient execution of these benchmarks.
