  We simulated our nanomagnet reservoir computer (NMRC) design on benchmark
tasks, demonstrating NMRC's high memory content and expressibility. In support
of the feasibility of this method, we fabricated a frustrated nanomagnet
reservoir layer. Using this structure, we describe a low-power, low-area system
with an area-energy-delay product $10^7$ lower than conventional RC systems,
that is therefore promising for size, weight, and power (SWaP) constrained
applications.
