  We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon
channel with endurance exceeding $10^{10}$ cycles. The ferroelectric
transistors (FeFETs) incorporate a high-$\kappa$ interfacial layer (IL) of
thermally grown silicon nitride (SiN$_x$) and a thin 4.5 nm layer of Zr-doped
FE-HfO$_2$ on a $\sim$30 nm SOI channel. The device shows a $\sim$ 1V memory
window in a DC sweep of just $\pm$ 2.5V, and can be programmed and erased with
voltage pulses of $V_G= \pm$ 3V at a pulse width of 250 ns. The device also
shows very good retention behavior. These results indicate that appropriate
engineering of the IL layer could substantially improve FeFET device
performance and reliability.
