  Analytical formulas are presented for simplified but useful qubit geometries
that predict surface dielectric loss when its thickness is much less than the
metal thickness, the limiting case needed for real devices. These formulas can
thus be used to precisely predict loss and optimize the qubit layout.
Surprisingly, a significant fraction of surface loss comes from the small wire
that connects the Josephson junction to the qubit capacitor. Tapering this wire
is shown to significantly lower its loss. Also predicted are the size and
density of the two-level state (TLS) spectrum from individual surface
dissipation sites.
