  The outsourced manufacturing of integrated circuits has increased the risk of
intellectual property theft. In response, logic locking techniques have been
developed for protecting designs by adding programmable elements to the
circuit. These techniques differ significantly in both overhead and resistance
to various attacks, leaving designers unable to discern their efficacy. To
overcome this critical impediment for the adoption of logic locking, we propose
two metrics, key corruption and minimum corruption, that capture the goals of
locking under different attack scenarios. We develop a flow for approximating
these metrics on generic locked circuits and evaluate several locking
techniques.
