  This paper introduces the processing element architecture of the second
generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the
chip features adaptive body biasing for near-threshold operation, and dynamic
voltage-and-frequency scaling driven by spiking activity. On system level,
processing is centered around an ARM M4 core, similar to the processor-centric
architecture of the first generation SpiNNaker. To speed operation of subtasks,
we have added accelerators for numerical operations of both spiking (SNN) and
rate based (deep) neural networks (DNN). PEs communicate via a dedicated,
custom-designed network-on-chip. We present three benchmarks showing operation
of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.
