Patent Document:

as described above , the present invention may be employed in the measurement of both pacing and cardioversion lead and electrode impedances in single or dual chamber pacemakers as well as in pacemaker - cardioverter - defibrillators or in other body tissue stimulators . in the case of a cardiac pacemaker , the impedance testing routine may be entered into either periodically or by physician initiation with an external programmer by initiating a temporary asynchronous pacing mode of operation having a fixed escape interval wherein the output capacitor may be first discharged into a precision resistor load part way through the escape interval and the measurement of the time that it takes to discharge from vdd to vdd / 2 can be conducted without having any effect on the patient thereafter , at the end of the temporary escape interval ( which is preferably set at a lower than normal test pacing rate , such as 60 beats per minute ) the output capacitor may be discharged into the patient &# 39 ; s pacing lead and heart in order to measure the time that it takes for the output capacitor to again discharge from vdd to vdd2 . the two elapsed times may be stored in memory and processed to develop the current lead impedance value . however , when testing the impedance of a cardio version / defibrillation electrode system , it is undesirable to shock the patient just to obtain the impedance value . therefore , advantage is taken of the fact that periodically the function of the cardioverter / defibrillator output shock generating circuit is tested by the physician who initiates charging and discharging of the high voltage output capacitors into a test load in order to reform the capacitors which , by their nature , tend to lose their ability to charge if not charged and discharged periodically . in the course of that testing , the present invention may be practiced by measuring the time that it takes for the output capacitor voltage to decrease from a first reference value to a second reference value through the known impedance test load , where the first and second reference voltages are chosen to be at levels which are insufficient in and of themselves to cardiovert the patient . then , the same procedure may be repeated by recharging the output capacitor and causing it to discharge from the first reference voltage to the second reference voltage through the electrode system and measuring the elapsed time in order to compare the two elapsed times and measure the cardioversion / defibrillation lead impedance . alternatively , the physician may elect to conduct a test of the system &# 39 ; s ability to cardiovert the patient in an electrophysiologic study and , in the course of that procedure , the physician may first program the implanted device to charge up its high voltage output capacitors and discharge them into the test impedance , obtain the aforementioned elapsed time measurement , initiate stimulation to induce a tachyarrhythmia and program the device to both cardiovert or defibrillate the enduced tachyarrhythmia and to conduct the elapsed time measurement in accordance with the method of the present invention . turning now to fig1 the overall impedance of a pacing or cardioversion lead and electrode system in contact with a patient &# 39 ; s heart and as presented at the output circuit of either the pacemaker or the cardioverter / defibrillator shock generator is depicted as a series of resistances and capacitances . since the output circuit in either case is viewing the remainder of the system through a feedthrough terminal , connector block connection , lead conductor system and electrode - tissue interface , each of those components may possess a discrete electrical series resistance . it will be understood that the normal resistances of the feedthrough , connector block and connector pin connection , lead conductor and its connections with the connector pin and electrode should remain relatively low and stable . in pacing , employing relatively small pace / sense electrode surface areas , impedances at the electrode - tissue interface would be expected to range between 500 and 1000 ohms while total impedance of the remainder of the system , employing highly conductive alloys , would range between 10 and 20 ohms . similarly , with cardioversion lead systems , the impedance of the electrical components would be expected to fall between 10 and 20 ohms , whereas the electrode - tissue interface impedance may range between 20 and 200 ohms . a relatively large surface area of the typical cardioversion / defibrillation electrode contributes to a lower electrode - tissue interface impedance . fig1 illustrates the effective series and parallel connected impedances of the components listed above where r ft represents the feedthrough resistance : r cb represents the connector block impedance : r lc represents the lead conductor and connection joint impedances of the lead conductor and its connections with the proximal conductor pin and the distal electrode ; and wherein the electrode - tissue interface impedance which can be represented through an electrical impedance which comprises a series resistor r s in series electrically with a parallel combination of a faraday resistor r f and a helmholtz capacitor c h . the entire series resistance of r ft , r cb , r lc and r s has a nominal value of about 10 to 200 ohms , the capacitor c h has a nominal value of about 5 to 50 microfarads , and the resistor r f has a nominal value of 2k to 100k ohms . these values apply for the impedance measured in gross terms across the output terminals of the pulse generator . turning now to fig2 it depicts in simplified form a typical pulse generator output circuit for either a pacemaker or a cardioverter wherein the output capacitor 10 of either such device is typically adapted to be charged to a programmed battery voltage vdd through a charging switch 12 and the lead system which is shown diagrammatically as r lead representing the impedance depicted in fig1 . at the appropriate time following the charging of capacitor 10 , the switch 12 is opened and the switches 14 and 28 are closed in order to discharge capacitor 10 through r lead for the time duration or pulse width set by the closure of switch 14 . the remaining elements of fig2 may be incorporated into each embodiment and employed in the lead impedance measurement method and apparatus of the present invention . in the pacing context , the output circuit of fig2 may take the form of the circuit depicted , for example , in u . s . pat . no . 4 , 498 , 478 to bourgeois or u . s . pat . no . 4 , 476 , 868 to thompson , or u . s . pat . no . 4 , 406 , 286 to stein , all incorporated by reference herein in their entirety . the switches 28 and 30 may take the form of transistor switches in a fashion taught by the above - incorporated &# 39 ; 478 , &# 39 ; 868 and &# 39 ; 286 patents . additional elements to the prior art output circuits by which the method and apparatus of the present invention may be implemented to include the first differential amplifier 20 coupled across the capacitor 10 by conductor 22 , a second differential amplifier 24 , the counter 26 , the switches 28 , 30 , and the known precision resistor 32 all coupled as depicted in fig2 . the operation of the lead impedance measuring system is explained in conjunction with the waveform diagram of fig3 and the flowchart diagram of fig4 . very generally , the lead impedance method follows the steps of charging the capacitor 10 to vdd , discharging the capacitor 10 through r known resistance 32 , while at the same time enabling the counter 26 to start counting clock pulses , and to freeze the count in the counter 26 when the voltage across the capacitor 10 decreases to vdd / 2 , as determined by the first and second op amps 20 and 24 thereafter , the process is repeated through the lead impedance presented to the output terminal of the pulse generator at switch 28 , representing the discharge time of the capacitor 10 between the same starting and ending voltage . the first and second counts reflect the discharge time corresponding to a discrete number of clock pulse intervals denoted t cap and t lead , respectively . r known remains constant and vdd should be a repeatable constant voltage for the two successive discharges of capacitor 10 , the only variable in the time t cap from one pulse generator to another and over the life of the pulse generator in question should be the condition of the switches 14 and 30 and capacitor c . in practice , capacitor tolerances vary from one pulse generator to the next , and the repetitive cycling , particularly of high voltage electrolytic capacitors , causes the capacitance to change over time . therefore , since the rc time constant of the capacitor 10 and precision resistor 32 may vary , the first discharge time is denoted t cap , and it is measured and stored in memory at least on the first occasion that the lead impedance is calculated or , preferably , each time that it is calculated . the relationship between the capacitance c of the capacitor 10 and the resistances r known of the precision resistor 32 and r lead for the combined lead impedance are expressed as follows : since the resistance r known is known , it may be used as a constant , and the determination of the variable lead impedance r lead reduces to : ## equ1 ## and results in known switch impedances for switches 14 and 28 may be subtracted or ignored if insignificant . this approach eliminates the need to use natural log functions or approximations thereof . in the calculation of r lead , the two counts are compared to one another and the ratio of the t lead to the t cap multiplied by the r known resistance yields the current r lead value in a manner to be described in conjunction with fig4 . the above - described method may be employed also in the context of a cardioverter - defibrillator , where the capacitor 10 may take the form of the high voltage output capacitor and the voltage source vdd may take the form of the output of the dc - dc converter , as shown , for example in u . s . pat . nos . 4 , 595 , 009 and 4 , 548 , 209 , filed in the names of lebindors and wielders . in that context , the r lead impedance constitutes the same impedance elements as depicted in fig1 but in regard to a cardioversion / defibrillation lead system , rather than the pacing lead system previously described . moreover , the fixed r known impedance element may take the form of the internal discharge resistor which is usually provided at 1 - 3k ohms . the switches 12 , 14 , 28 and 30 may constitute the high voltage silicone controlled switches and power fets commonly employed in the output circuits of such devices . turning now to fig3 and 4 , they describe the practice of a method of the present invention implemented in pacing context wherein it will be understood that the pacemaker is normally operating to repetitively timeout escape intervals which may be fixed at a previously programmed value or vary between preset upper and lower escape intervals in relation to a pacing rate control signal established by physiologic sensor , as is well known in the pacing art . at some point , either upon receipt of an external programmed - in command , the occurrence of a particular event or upon an internally timed - out self test command , the pacing logic or software commences a subroutine to initiate the successive measurement of the t lead and t cap time intervals turning now to fig3 the successive discharge of the capacitor 10 into the r known and r lead impedances is depicted along the time line t and in relation to the starting voltage vdd and ending voltage vdd / 2 . once the impedance measurement algorithm is entered into , at start block 100 of fig4 the pacing mode is changed to a temporary fixed rate mode at a preset escape interval for at least one escape interval denoted t 2x . escape interval t 2x may be selected to be in the range of 1 , 000 ms to allow for the successive charge and discharge of the capacitor 10 through both the r known and r lead impedances and still allow adequate time for the capacitor 10 to recharge . fig3 illustrates the discharge of the capacitor 10 through the r known impedance at the end of the interval t x to develop the reference time period t cap and to subsequently allow the discharge of the capacitor 10 through the r lead impedance at the end of the escape interval t 2x to develop the pulse width interval t lead . turning now to fig4 the testing subroutine starts at start block 100 , which may precede the end of a current escape interval reflecting the receipt of a programmed - in command , for example . when the next pace or sensed event occurs , the escape interval is set to 2 × ms , switches 12 and 28 are closed and switches 14 and 30 are opened in block 104 to provide for the recharge of the capacitor 10 through the r lead impedance in the normal pacing fashion . during this time , the counter 26 is not enabled and as capacitor 10 charges up to vdd , its voltage is presented across the positive or negative input terminals of the unity gain differential to single - ended op amp 20 , which in turn presents that voltage to the positive input terminal of differential amplifier 24 . differential amplifier 24 compares the voltage at its positive input terminal against a reference voltage , in this case one - half the vdd voltage or vdd / 2 , and provides an output signal at its output terminal whenever the presented voltage across the capacitor 10 exceeds the reference voltage vdd / 2 less any offset voltages . the output of the differential amplifier 24 operates to freeze and transfer the contents of the counter 26 into memory when that presented voltage falls below the reference voltage vdd / 2 as described hereinafter . in block 108 , and in reference to fig3 at the end of the interval t x as timed out by decision block 108 , the counter 26 is enabled , the switches 12 and 28 are opened and the switches 14 and 30 are closed . at that instant , the voltage vdd across the capacitor 10 is presented to the positive input terminal of the differential amplifier 24 and also begins to discharge through the r known impedance 32 in a fashion depicted by the capacitive discharge pulse having a width t cap depicted in fig3 . as long as the voltage on capacitor 10 is greater than vdd / 2 , counter 26 continues to count clock pulses . as soon as the voltage on the capacitor 10 falls below vdd / 2 , the output from the differential amplifier 24 switches from high to low , and the counter 26 receives a command to freeze the count , transfer it to a memory location or a separate register , and to disable itself . at the same time , this accumulated count may be reset to zero . at the same time , the switches 14 and 30 are set open and switches 12 and 28 are set closed to terminate the discharge of the capacitor 10 and commence its recharge . the stored time interval t cap is held awaiting the measurement of the time t lead , whereupon the mathematical comparison and multiplication steps take place . thereafter , the fixed escape interval t 2x times out in block 116 , and the counter 26 is again enabled in block 118 . at the same time , the switches 12 and 30 are opened , and the switches 14 and 28 are closed . thus , the discharge of the capacitor 10 through the r lead impedance commences at the end of the escape interval . again , the voltage on the capacitor 10 is monitored by the differential amplifiers 20 and 24 and when it again falls below vdd / 2 , the contents of the counter 26 are frozen , transferred to a separate register and the counter cleared in blocks 122 and 124 . at the same time , the switches 14 and 30 are opened , and the switches 12 and 28 are closed to commence the recharge . once the count representing the time t lead is stored in block 124 , the subroutine is exited in block 126 , thus returning control of the pacing mode and rate to the normal operating pacing system . since the clock pulses have predetermined pulse widths , the accumulated counts transferred into memory at registers representing the time intervals t cap and t lead are fairly representative of the actual rc discharge times . moreover , since the ratio of the two times are employed in the calculation of the current lead impedance , any voltage reference drift or other component value or operating parameter drift cancel one another out . over the impedance range of 100 to 1000 ohms , the error tolerance is dependent upon the following factors : counter resolution vs . minimum decay time 30 . 5 us / 693 us ( 100 ohm , 10 uf ) 4 . 4 % counter resolution vs . nominal decay time 30 . 5 us / 3 . 53 ms ( 510 ohm , 10 uf ) 0 . 9 % known load decay time ± 2 . 7 % ( sum of errors in calculation of t cap ) in theory , the measurement accuracy meets the goal of ± 5 - 10 % in the specified load range . the comparator and op amp errors are consistent between the known impedance pulse and the unknown impedance pulse effectively eliminating them from the overall summation of error terms . in the cardioversion - defibrillation context , the method of fig4 may be modified by eliminating the decision block 102 and setting an overall time interval in block 104 that may encompass 30 to 60 seconds to assure adequate charging to full program voltage . although technically not an escape interval , the time - out of the set interval is necessary to assure that the output capacitor is fully charged . alternately , if the cardioverter - defibrillator is provided with a circuit for monitoring the achievement of full charge on the output capacitor or capacitors , then the initial discharge through the r known impedance 32 and then the subsequent discharge through the r lead impedance 16 may take place upon confirmation of the capacitor output voltage vdd . in either case , the excessive charging and discharging of the capacitor 10 to develop the time intervals t cap and t lead occurs in the same fashion as described above . in those instances where it is undesirable to discharge full output capacitor voltage through the r lead impedance on the patient , a smaller sub threshold voltage vdd may be selected or the reference voltage vdd / 2 ( i . e ., 0 . 5 vdd ) may be set at a higher value , such as 0 . 95 vdd . in either case , the method and appartus of the present invention finds particular utility in the pacemaker - cardioverter - defibrillator context , inasmuch as the condition of the capacitors may change over time by virtue of their being repetitively subjected to high voltage charge and discharge cycles . in accordance with the present invention , changes in the applied voltage vdd , the capacitor 10 and the various switches are all taken into account and offset one another in the calculation . other modifications of the embodiments of the method and apparatus of the present invention will become readily apparent to those skilled in the art in light of the foregoing disclosure . therefore the scope of the present invention should be interpreted from the following claims interpreted in light of the above - described preferred embodiments and other modifications and embodiments thereof .

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