Question: why nmos is used as pull down?
Answer: Here pull up is nMOS transistor and pull down is pMOS transistor. When logic 1 is applied as input, nMOS transistor turns ON and PMOS transistor turns OFF. ... But due to threshold voltage effect, nMOS is not capable of passing Vdd/ good logical 1 at the output. Hence, the output will be Vdd-Vth.