A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple
Authors: Yue Chen, Jiang Gong, Robert Bogdan Staszewski, and Masoud Babaie
Published in: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Publication type: article
Subject areas: Engineering
SJR best quartile: Q1