Spreadsheet: 69b211d2-8cea-4d6a-baa8-8a1055ea7044
Sheet: Sheet1

Paper Number | Paper Title | Paper Authors
1 | Efficient Routing Implementation in Complex Systems-on-Chip Designs | [NAME] [1],  [NAME] [1],  [NAME] [1],  [NAME] [2],  [NAME] [2]
2 | Analysis of Application-Aware On-Chip Routing under Traffic Uncertainty | [NAME],  [NAME],  [NAME],  [NAME],  [NAME]
3 | HOPE: Hotspot Congestion Control for Clos Network On Chip | [NAME],  [NAME],  [NAME],  [NAME]
4 | Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching | Freek [NAME] [1] and [NAME] [2]
5 | Deadlock-Free Fine-Grained Thread Migration | [NAME],  [NAME],  [NAME],  Keun Sup Shim,  [NAME]
6 | Prevention Flow-Control for Low Latency Torus Networks-on-Chip | [NAME] and Madhu [NAME]
7 | A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs | [NAME] [1],  [NAME] [2],  [NAME] [2],  [NAME] [2],  [NAME] [2],  Yukinori Nishiyama [2],  Michihiro Koibuchi [3],  [NAME] [2],  Hideharu Amano [2]
8 | Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks | [NAME] [1],  [NAME] [1],  Dinesh Pamunuwa [1],  [NAME] [2],  Awet Yemane Weldezion [2]
9 | Congestion Aware, Fault Tolerant, and Thermally Optimal Inter-Layer Communication Scheme for Hybrid NoC-Bus 3D Architectures | [NAME] [1],  [NAME] [1],  [NAME] [1],  [NAME] [2],  [NAME] [2],  [NAME] [1]
10 | Exploring Partitioning Methods for 3D Networks-on-Chip Utilizing Adaptive Routing Model | [NAME],  [NAME],  [NAME]
11 | BLOCON: A Bufferless Photonic [NAME]Chip Architecture | [NAME] and [NAME]
12 | Two-Hop Free-Space Based Optical Interconnects for Chip Multiprocessors | [NAME],  [NAME],  [NAME]
13 | All-optical wavelength-routed NoC based on a novel hierarchical topology | [NAME],  [NAME],  [NAME]
14 | Exploiting Inherent Information Redundancy to Manage Transient Errors in NoC Routing Arbitration | [NAME],  [NAME],  [NAME]
15 | A Distributed and Topology-Agnostic Approach for On-line NoC Testing | [NAME] [1],  [NAME] [2],  [NAME] [1]
16 | Energy and Reliability Oriented Mapping for Regular Networks-on-Chip | Cristinel Ababei [1],  Hamed Sajjadi Kia [1],  Om Prakash Yadav [1],  [NAME] [2]
17 | Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors | [NAME],  [NAME],  [NAME]
18 | FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations | [NAME] [1],  [NAME] [2],  [NAME] [2]
19 | DART: Fast and Flexible NoC Simulation using FPGAs | Danyao Wang [1],  [NAME] Jerger [2],  [NAME] [2]
20 | Inferring Packet Dependencies to Improve Trace Based Simulation of On-Chip Networks | [NAME],  [NAME],  [NAME],  [NAME]
21 | Delay Analysis of Wormhole Based Heterogeneous NoC | [NAME],  [NAME],  [NAME]
22 | [NAME] Inspired Fault-Tolerant NoC Architectures with Wireless Links | Amlan Ganguly [1],  [NAME] [2],  [NAME] [2],  Partha Pande [2]
23 | Design of Multi-Channel Wireless NoC to Improve On-Chip Communication Capacity | Danella Zhao [1],  [NAME] [1],  [NAME] [2],  [NAME] [3]
24 | Link Pipelining Strategies for an Application-Specific Asynchronous NoC | [NAME],  [NAME],  [NAME]
25 | A Low-Latency Adaptive Asynchronous Interconnection Network Using Bi-Modal Router Nodes | [NAME],  [NAME],  [NAME],  [NAME]
26 | Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures | [NAME],  [NAME],  [NAME]
27 | Cross Clock-Domain TDM Virtual Circuits for Networks on Chips | [NAME]
28 | VLSI Micro-Architectures for High-Radix Crossbar Schedulers | Giorgos Passas,  [NAME],  [NAME]
29 | Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip Interconnect for Cryptographic Accelerators | [NAME] and [NAME]
30 | [NAME]-on-Chip Energy Consumption Through Spatial Locality Speculation | [NAME] [1],  [NAME] [1],  [NAME] [2],  [NAME] [1],  [NAME] [3]
31 | Curbing Energy Cravings in Networks: A Cross-Sectional View Across the Micro-Macro Boundary | Amlan Ganguly; [NAME]; Pradip Bose
32 | Challenges and Promises of Nano and Bio Communication Networks | [NAME]; [NAME]; [NAME]; [NAME]
33 | XMOS XMP-64 Demonstration | [NAME]
34 | Dynamic Power Management of Voltage-Frequency Island Partitioned Networks-on-Chip using Intel Sing-Chip Cloud Computer | [NAME]; [NAME]; [NAME]; [NAME]
35 | A Software Framework for Trace Analysis Targeting Multicore Platforms Design | Guopeng (Daniel) Wei; [NAME]; [NAME]
36 | Reconfiguration of a 3GPP-LTE telecommunication application on a 23-core NoC-based System-on-Chip | [NAME]
37 | A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations | [NAME]; [NAME]; [NAME]
38 | NoCs Simulation Framework for OMNeT++ | [NAME]; [NAME]; Israel Cidon; Avinoam Kolodny
39 | Spidergon STNoC Design Flow | [NAME]; [NAME]; [NAME]; [NAME]; [NAME]