Von Neumann & Harvard Architectures
Tags: computerscience, todayilearned
Published: 2021-04-12 08:10:25

Considering the problem of how to access memory in CPU level, There are two popular designs: Von Neumann and Harvard architectures.

<html><center><img src="https://yetkinakyuz.com/wp-content/uploads/2021/03/Von-Neumann.png" alt="Von Neumann Architecture" width="70%" height="70%"><p style="font-size: 11px">Figure 1: Von Neumann Architecture [2]</p></center></html>

The Von Neumann architecture, created by John Von Neumann in 1945, is a computer architecture in which data and instruction memories share a single storage unit. There is only one bus each for memory addresses and data transmission.

<img src="https://dev-to-uploads.s3.amazonaws.com/uploads/articles/s4nx302hg3lj5xyyd51a.png" alt="Harvard Architecture" width="70%" height="70%"><center><p style="font-size: 11px">Figure 2: Harvard Architecture [3]</p></center>

In the Harvard architecture, which takes its name from Harvard Mark I, the computer for which it is used for the first time, data and instruction memories are physically separated from each other. Both have separate memory address bus and data bus. When a program runs, instruction flow and data flow take place over separate sets of buses.



### The Von Neumann Bottleneck

The fact that a single bus transmits both instructions and data leads to a problem called The Von Neumann Bottleneck. Because a single bus can only access one class of memory at a time, the throughput is lower than the speed at which the CPU can run. Therefore, the CPU has to constantly wait for the required data to be transported, resulting in a drastic drop in processing speed.

<img src="https://dev-to-uploads.s3.amazonaws.com/uploads/articles/ib7fcvio7owdoxm9kgui.png" alt="Performance of processor and memory" width="70%" height="70%"><center><p style="font-size: 11px">Figure 3: Performance of processor and memory [4]</p></center>

The most logical solution is to use a cache, which holds the last data used by the processor. In this way, the processor does not need to access memory and the expected time is compensated.

The problem is experienced in general today, rather than only in Von Neumann architecture. Memory technology, which cannot keep up with the development of processor technology, greatly increases this problem.




### The Modified Harvard Architecture

<img src="https://dev-to-uploads.s3.amazonaws.com/uploads/articles/j5dtkthxovlk9802talo.jpg" alt="Modified Harvard Architecture" width="50%" height="50%"><center><p style="font-size: 11px">Figure 4: Modified Harvard Architecture [6]</p></center>

The Modified Harvard architecture is a variation of the Harvard computer architecture that allows the contents of the instruction memory to be accessed as data, unlike the pure Harvard architecture. It supports higher performance concurrent data and instruction access of Harvard architecture. It also loosens the distinction between commands and data. Two separate caches are used, supported by the same memory address, one for commands and the other for data. In short, while Harvard architecture is used on the cache side, Von Neumann architecture is used on the main memory side.

Most of the modern computers described as Harvard architecture are actually modified Harvard architecture.




### References

1. Zhu, Y. (Jun 2018). Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C
2. [Wikipedia. Von Neumann Architecture](https://en.wikipedia.org/wiki/Von_Neumann_architecture)
3. [Wikipedia. Harvard Architecture](https://en.wikipedia.org/wiki/Harvard_architecture)
4. [Nowak, A. (2014). Opportunities and choice in a new vector era](https://iopscience.iop.org/article/10.1088/1742-6596/523/1/012002/pdf)
5. [Wikipedia. Modified Harvard Architecture](https://en.wikipedia.org/wiki/Modified_Harvard_architecture)
6. [Blocksandfiles. (2019). Back to the future with persistent memory](https://blocksandfiles.com/2019/08/20/back-to-the-future-with-persistent-memory/)