About Makefiles – Part I
Published: 2022-04-22 17:16:50


Hello,

Today I will briefly dissert about `Makefiles` and `make`, an efficient automation tool to compiles many programs at once.

I am writing this because when doing my SPO600 Project, I encountered many `Makefiles` with different functions and I was curious on how they work.

What I noticed first is that not all the `Makefiles` compiles things, most of them just have flags and configurations like this:
A common use of `Makefiles` is to set variables to be included in other `Makefiles`:
 
![A1](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/8q277d2bbzg37elh098s.png)
 


But first, lets understand how hey work from the beginning:

## Whats the purpose of `Makefile`?

A `Makefile` is a set of instructions that will be read when the `make` command is called.

`Make`, then will read the `Makefile`  follow its instructions and compile and link the program it wants to do. 

A function of the `Makefile` is to create several `make` scripts like:
-	`make`: will run the `Makefile`
-	`make clean`: will erase the binaries compiled by the `Makefile` and others
-	`make install` will create and install tar packages and others
-	`make distclean` and `make realclean` will remove same files as make clean but  TAGS, makefiles and config.status files, `make realclean` also removes info files generated by .texinfo


```
The makefile can also tell make how to run miscellaneous commands when explicitly asked (for example, to remove certain files as a clean-up operation).
```
Source: [GNU]( https://www.gnu.org/software/make/manual/html_node/Introduction.html)

## How `Make` works?
The command `make` will read the directory and search for a `Makefile`. Then it will start processing the first rule. A rule is a instruction with a target, a prerequisite and a recipe.

```
A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as ‘clean’ (see Phony Targets).
A prerequisite is a file that is used as input to create the target. A target often depends on several files.
A recipe is an action that make carries out. A recipe may have more than one command, either on the same line or each on its own line. Please note: you need to put a tab character at the beginning of every recipe line! This is an obscurity that catches the unwary. If you prefer to prefix your recipes with a character other than tab, you can set the .RECIPEPREFIX variable to an alternate character (see Special Variables).
```
Source: [GNU] (Rule Introduction (GNU make))

Looking easy right?
Lets take a look at this next screenshot and change our minds:

![A2](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/pmrxpa8zvm2hjcjejhme.png)
 
 
As we can see, it is really hard to understand what’s going on because there is a lot of variables being used.
## Can we use Variables to make our life easier?
Yes we can, to avoid duplication and reduce redundancy we can set  a variable.
If we take a look at the screenshot above, we can see that the second line is declaring a variable and assigning a value to it.
```
SKIPHEADERS = compat/s32pthreads.h
```
This way, everytime we want to use it we just need to do `$(SKIPHEADERS)`.

For example: 

![A3](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/tn2e3pq8ie7pow93hkaa.png)
 
`TESTOOLS` is being declared and right away its being used in `HOSTPROGS`.

---

I will continue explaining about `Makefiles` and `make` in the next post!
See you there and Thank you for Reading!