Basics of SPI communication protocol (Part 2)
Published: 2023-12-04 09:56:11

Hello Readers,
My name is Rakshith M working as a junior software engineer at Luxoft India. now I am continuing my previous article of Basics of SPI communication protocol. So, let's do it.

**SPI Hardware’s**
The hardware requirement for imposing SPI is very simple when compared to UART and I2C. Consider a Master and an unmarried Slave are connected the use of SPI bus. The following figure shows the minimal device requirements for each the devices.

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/5532pghxtsyu8of1w3bx.png)

The Master tool consists of a Shift Register, a records latch, and a clock generator. The slave consists of similar hardware: a shift registers and a statistics latch. Both the shift registers are connected to shape a loop. Usually, the size of the check in is 8 – bits however higher length registers of sixteen – bits are also common.
During the nice edge of the clock signal, each the devices (grasp and slave) read input bit into LSB of the sign up. During the terrible cycle of the clock signal, each the master and slave locations a bit on its corresponding output from the MSB of the shift check in.
Hence, for every clock cycle, a piece of facts is transferred in each path i.e. From grasp to slave and slave to grasp. So, for a byte of records to be transmitted from each device, it'll take eight clock cycles.

**SPI Modes of Operation**
We have already visible that it is the job of the Master tool to generate the clock sign and distribute it to the slave so that you can synchronize the statistics among master and slave. The work of grasp doesn’t quit at generating clock signal at a particular frequency.
The grasp and slave must agree on positive synchronization protocols. For this, functions of the clock i.e. The Clock Polarity (CPOL or CKP) and Clock Phase (CPHA) come into picture.
Clock Polarity determines the country of the clock. When CPOL is LOW, the clock generated through the Master i.e., SCK is LOW while idle and toggles to HIGH at some point of lively kingdom (at some stage in a transfer). Similarly, whilst CPOL is HIGH, SCK is HIGH during idle and LOW at some stage in lively country.
Clock Phase determines the clock transition i.e., Growing (LOW to HIGH) or falling (HIGH to LOW), at which the statistics is transmitted. When CPHA is zero, the information is transmitted at the growing fringe of the clock. Data is transmitted at the falling facet whilst CPHA is 1.

Depending on the values of Clock Polarity (CPOL) and Clock Phase (CPHA), there are 4 modes of operation of SPI: Modes 0 through three.
**Mode 0:**
Mode 0 takes place while Clock Polarity is LOW and Clock Phase is zero (CPOL = zero and CPHA = 0). During Mode 0, data transmission occurs at some stage in rising edge of the clock.

**Mode 1:**
Mode 1 takes place while Clock Polarity is LOW and Clock Phase is 1 (CPOL = 0 and CPHA = 1). During Mode 1, statistics transmission occurs throughout falling fringe of the clock.

**Mode 2:**
Mode 2 occurs while Clock Polarity is HIGH and Clock Phase is 0 (CPOL = 1 and CPHA = zero). During Mode 2, information transmission occurs all through growing fringe of the clock.

**Mode 3:**
Mode 3 takes place while Clock Polarity is HIGH and Clock Phase is 1 (CPOL = 1 and CPHA = 1). During Mode 3, facts transmission occurs while growing fringe of the clock.

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/0j41ft09xx5fnpxn05f9.png)


**Dual and Quad SPI**
There are also versions on SPI called Dual and Quad SPI, wherein multiple information line may be used to transmit records in a single course on the identical time (technically in parallel), which similarly increasing information throughput (common verbal exchange pace). These variations are famous with e.g., FLASH reminiscence chips wherein excessive records throughput may be required. With Dual SPI conversation starts off as per regular (like Single SPI) but can be modified to Dual mode after a command is despatched to the slave tool (the details of this may be available inside the slave device datasheet). In Dual mode the MISO and MOSI strains every come to be bi-directional (half of-duplex) verbal exchange traces called SIO0 (Serial I/O zero) and SIO1; the even bits of each byte are transmitted on SIO0, and the strange bits of every byte are transmitted on SIO1.

Quad SPI is comparable, except that there are a further verbal exchange strains – SIO2 and SIO3, and half of-a-byte is transmitted at a time.
Sequence of Operations:

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/n44toxfmctfet6zgiylg.png)


**Slave Selection:**
The master activates the SS/CS line for the target slave.

**Clock Configuration:**
The grasp defines clock polarity (CPOL) and clock segment (CPHA).

**Data Transfer:**
For each clock pulse, one little bit of information is transferred.
Data is often transferred MSB first.

**Slave Deselection:**
The master deactivates the SS/CS line, indicating the end of the communication with that slave.

**Advantages and disadvantages of I2C**
**The positives of SPI are:**
•	It doesn’t want to address bits, making transmission simpler.
•	Higher transmission charge than I2C.
•	Two-manner communication (complete-duplex). While I2C is 1/2-duplex, it’s two-way additionally, however the facts flux in a route must attend until the transmission in the opposite path ends.
•	Has decrease energy consumption.
**The negative aspects:**
•	This interface requires four wires for each peripheral, at the same time as I2C only wishes.
•	Only one master is possible.
•	There’s no mistakes connection.
•	There’s no verification of information reception.

**Conclusion**
With this I am concluding that the SPI communication protocol is widely used in automotive industry so have written based on my knowledge please let me know if any improvements or queries are there thank you