light sensor interface using I2C bus.
Published: 2023-08-24 09:28:40

Hi, I'm Rakshith M working as a junior software engineer at luxoft India LLP. In this article I made my best effort to provide some of the aspects in interfacing of light sensor with FPGA using I2C bus and this is one of my interests

**I. INTRODUCTION**
In this contemporary era, the digital mild sensors have all kinds of practical makes use of maximum drastically in gadgets with auto-brightness adjustment digital instruments and in digital cameras to modify publicity. The maximum commonplace use of digital light sensor is in non-public transportable digital devices which include mobile phones and tablets to regulate brightness, such that if the tool is inside the darkish area, then digital device should turn down the display brightness to keep power and make cushy the screen viewing experience. Another not unusual place for the usage of digital light sensor is avenue lightning and automobiles for automatic controlling lighting.
The virtual light sensor BH1750FVI measures illuminance which is a degree of the total amount of visible light emitted through a source divided with the aid of area in square meters. This sensor offers output in phrases of Lux i.e. 1 lux = 1 lm/m^2. The virtual light sensor BH1750FVI recognizes mild with wavelengths inside the range of 400 – seven hundred nm, which more or less covers the entire spectrum of visible mild. Here the virtual mild sensor is interfaced to FPGA thru I2C interface as it's miles the maximum common bus for interfacing a lot of sensors with only two wires.

**II.I2C CONTROLLER CORE**
**A. I2C BUS PROTOCOLS**
The I2C bus communique protocol is a two-twine interface (TWI) which makes use of handiest sign lines i.e., serial statistics (SDA) and serial clock (SCL) to set up synchronous serial verbal exchange between a master and an unmarried or a couple of slave device. The I2C bus protocols are explained in-element with graphical illustration as shown within the discern 1.
![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/itl1pln4d183fsgsukvg.png)

**Fig 1. List of I2C bus communication protocols.**

 ** START and STOP BIT**
• The I2C communication is initiated via grasp tool with transmission of begin command and terminated with the aid of grasp device with the transmission of forestall command to the slave device. The begin command represents a high-to-low transition at the serial information SDA line while the serial clock SCL line is high, and the forestall command represents a low to-excessive transition on serial statistics SDA line at the same time as the serial clock SCL line is excessive [6]. Both start and prevent instructions are represented pictorially as shown in the discern 1.

**ADDRESS and R/ܹW BIT**
• After the begin command, right away the 7-bit cope with accompanied with the aid of R/ܹഥ bit is transmitted over the bus with MSB first by way of grasp device and all of the slave devices at the bus shift-in serially transmitted bits. The one device whose deal with suits with transmitted address acknowledges master via energetic low on serial records SDA line while serial clock SCL line is excessive. I2C bus supports 7-bit and 10-bit addressing with 7-bit addressing the master device can address up-to 2^7=128 devices on the bus and with 10- bit addressing up-to 2^10=1024 gadgets at the bus but 7-bit addressing is most extensively accepted and used [6]. 
•The R/ܹഥ bit represents route of facts switch between the grasp and slave device over the bus, if R/ܹഥ =0 i.e., active low, the master tool transmits a byte of information to the slave device if R/ܹഥ =1 i.e., energetic excessive the grasp device gets a byte of statistics from slave.

**DATA BYTE**
• I2C bus supports data transfer in terms of bytes only that is one byte comprised of 8-bits on the serial data SDA line. This byte may either be a device address, register address, data written to or read from slave device, here one data bit is transferred during each clock pulse of SCL with MSB first. Any number of data bytes can be transferred from master to slave between the start and stop command, only condition is that the data on the SDA line must remain stable during the high phase of clock period, as changes in the SDA line when the clock is high is interpreted as start or stop command.

**ACK AND NACK BITS**
• In I2C communication, after successful transmission of each data byte the receiver acknowledges the transmitter with an acknowledge signal that is the receiver will pull down the serial data SDA line during low phase of serial clock SCL line before subsequent clock pulse becomes high. While NACK is interpreted as a serial data SDA line remains high during the low phase of serial clock SCL line before subsequent clock pulse, it represents that the master receiver is done reading data from slave and it cannot receive any more data bytes.
**B. Finite State Machine (FSM) design**
In order, to obtain measured digital data from light sensor BH1750FVI a sequence of protocol must be generated sequentially in specified order as provided in the data sheet. The sequence of I2C protocol for write and read operation are represented as shown in the figure 3 and figure 4 respectively.
![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/6ftcrg81eqak1kxpd7hi.png)
**Fig 3. Write frame representing I2C protocol sequence for mode configuration.**
![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/rzg78af6sidkxu3t18os.png)
**Fig 4. Read frame representing I2C protocol sequence for data acquisition from light sensor BH1750FVI.**

The finite state machine (FSM) is programming structure to follow the read and write frame in the specified sequence to send and receive data to and from the light sensor BH1750FVI. FSM is written in VHDL hardware description language, the operation of FSM is expressed in terms of flowchart to explicitly understand the working with diagrammatic representation as shown in the figure 5.
![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/0dgy7yrrqjx5omvmzrte.png)
**Fig 5. The flowchart of FSM of master I2C controller for communicating with light sensor.**
As represented in the figure 5, the communication with light sensor BH1750FVI is initiated through start bit then 7-bit address matching with internally stored address of sensor is transmitted along with the R/ܹഥ bit as 8th bit. If the transmitted address matches with address stored inside sensor, it responds with an acknowledge bit to the I2C master controller. If R/ܹഥ represents a write operation then 8-bit configuration byte is transmitted, further the successful reception is revealed by sensor through an acknowledge bit to master I2C controller. Next the master I2C controller generates immediately stop bit to terminate the communication with sensor.
**IV. CONCLUSION** 
From the experimental results, interfacing of light sensor BH1750FVI with I2C master controller implemented on FPGA is successfully validated through debugging SCL and SDA signal using hardware I2C analyzer.