CPU Cache Basics
Tags: cpu, cache, ram
Published: 2023-10-09 09:21:00

---
title: CPU Cache Basics
published: true
description: L1, L2, and sometimes L3 cache are small, high-speed memory areas built into your computer's CPU (Central Processing Unit) that help it run faster by storing frequently used data and instructions.
tags: #cpu #cache #ram
cover_image: https://dev-to-uploads.s3.amazonaws.com/uploads/articles/71trgwudrv54p5tjcp73.png
# Use a ratio of 100:42 for best results.
published_at: 2023-10-09 11:21 +0200
---

CPU caches are the unsung heroes of modern computing, silently speeding up your computer's performance. These small but incredibly fast memory storage areas play a vital role in ensuring that your CPU can access frequently used data and instructions with lightning speed. In this article, we'll explore the world of CPU caches, uncovering their design, optimization strategies, and their indispensable role in enhancing the performance of software and systems.

Here's what you should know as a software engineer:

**L1 Cache (Level 1 Cache):**

* L1 cache is the smallest but fastest cache located closest to the CPU cores.
* It's divided into two parts: L1i (instruction cache) and L1d (data cache). L1i stores instructions, and L1d stores data.
* The purpose of L1 cache is to store the most frequently used instructions and data to speed up the CPU's operations.
* It has low latency (the time it takes to access data) and is usually separate for each CPU core.

**L2 Cache (Level 2 Cache):**

* L2 cache is larger than L1 cache but slightly slower.
* It is shared among CPU cores in many multi-core processors.
* Its role is to store additional frequently used data and instructions that couldn't fit in L1 cache.
* L2 cache is still faster than accessing data from RAM (main memory).

**L3 Cache (Level 3 Cache, if available):**

* L3 cache is even larger but slightly slower than L2 cache.
* It is shared across all CPU cores in a multi-core processor.
* L3 cache acts as a backup storage for frequently used data and instructions that couldn't fit in L1 or L2 cache.
* Having an L3 cache can help reduce bottlenecks when multiple CPU cores are accessing memory simultaneously.

### How it works:

* When the CPU needs data or instructions, it first checks if they are in the L1 cache.
* If the needed information is in the L1 cache (or L2 cache if not found in L1), it's called a cache hit, and the CPU can quickly retrieve it.
* If the data is not in the cache, it's called a cache miss. In this case, the CPU has to fetch the data from slower main memory (RAM), which takes more time.
* The goal of the cache hierarchy is to reduce the number of cache misses by storing the most frequently used data and instructions in the faster, smaller caches.

### When it is used:

* L1, L2, and L3 caches are used constantly as the CPU executes programs.
* They are especially beneficial for speeding up frequently executed code and data access patterns.
* The cache hardware manages what gets stored in the cache, so as a software engineer, you generally don't interact with it directly.

![CPU cache schema](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/d14ya22r75jwo7mvn25h.png)

### Optimization principles

Caches like L1, L2, and L3 are _**managed by the hardware**_, and as a software engineer, _you don't have direct control over which programs or data are stored in them_. However, you can follow certain programming and optimization principles to increase the likelihood that your program benefits from cache usage. Here's how:

1. **Locality of Reference:** Caches work best when your program exhibits good locality of reference. There are two types of locality:
    * **Temporal Locality:** This means that if you access a piece of data once, you're likely to access it again in the near future. To leverage temporal locality, try to reuse data that you've recently accessed.
    * **Spatial Locality:** This refers to the tendency to access data located near recently accessed data. To benefit from spatial locality, try to access data in a sequential or predictable pattern.

2. **Cache-Friendly Data Structures:** Use data structures and algorithms that are cache-friendly. For example, when iterating over an array, processing elements that are stored close to each other in memory is more cache-efficient than jumping around in memory.

3. **Cache Line Awareness:** Cache systems typically work with fixed-size cache lines (e.g., 64 bytes). Be aware of this when designing your data structures. If you only need a small portion of a cache line, avoid loading the entire line to reduce cache pollution.

4. **Compiler and Compiler Flags:** Compilers can optimize code to improve cache locality. Use compiler flags (e.g., **-O2** or **-O3** in GCC) to enable optimizations. Additionally, understand how your compiler optimizes code for your target architecture.

5. **Profiling and Benchmarking:** Use profiling tools to analyze cache behavior in your program. Tools like perf (on Linux) or performance analyzers in integrated development environments (IDEs) can help you identify cache-related issues.

6. **Thread Affinity:** If you're working with multi-threaded programs, consider using thread affinity techniques to bind threads to specific CPU cores. This can help minimize cache contention between threads.

### Cache sizes

Regarding the sizes of cache levels, they can vary widely depending on the CPU architecture. However, here's a rough estimate:

* L1 Cache: Typically ranges from 16KB to 128KB per core.
* L2 Cache: Can range from 256KB to 1MB per core or be shared among multiple cores.
* L3 Cache: Usually shared among multiple cores and can range from 2MB to 32MB or more in high-end processors.

Keep in mind that these numbers can change with different CPU models and generations. You can usually find the specific cache sizes for your CPU in its documentation or by checking the manufacturer's website. Understanding cache sizes can help you make informed decisions when optimizing your code for specific hardware.

### Cache latencies

Let's compare the latencies of different memory levels, including CPU caches and RAM (main memory):

**L1 Cache Latency:**

- L1 cache is the fastest and has the lowest latency among all memory levels.
- Typical latency ranges from 1 to 3 cycles, which is extremely fast.
- Accessing data from L1 cache is significantly faster than any other memory level.

**L2 Cache Latency:**

- L2 cache has slightly higher latency compared to L1 cache.
- Typical latency ranges from 4 to 10 cycles, depending on the CPU architecture.
- It is still much faster than accessing RAM.

**L3 Cache Latency:**

- L3 cache has higher latency compared to L2 and L1 caches.
- Typical latency ranges from 10 to 40 cycles, depending on the CPU and cache design.
- While slower than L1 and L2, it is still much faster than RAM.

**RAM (Main Memory) Latency:**

- Accessing data from RAM is significantly slower than accessing any level of cache.
- RAM latency can vary widely, but it typically ranges from 60 to 100 cycles or more.
- RAM access times are several orders of magnitude slower than L1 cache.

Assuming a CPU clock speed of 3 GHz (3 billion cycles per second):

* L1 cache access time:
    - Fastest case (1 cycle): 1 / 3 * 10^9 = 0.33 nanoseconds
    - Slowest case (3 cycles): 3 / 3 * 10^9 = 1 nanosecond
* L2 cache access time:
    - Fastest case (4 cycles): 4 / 3 * 10^9 = 1.33 nanoseconds
    - Slowest case (10 cycles): 10 / 3 * 10^9 = 3.33 nanoseconds
* L3 cache access time:
    - Fastest case (10 cycles): 10 / 3 * 10^9 = 3.33 nanoseconds
    - Slowest case (40 cycles): 40 / 3 * 10^9 = 13.33 nanoseconds
* RAM access time:
    - Fastest case (60 cycles): 60 / 3 * 10^9 = 20 nanoseconds
    - Slowest case (100 cycles): 100 / 3 * 10^9 = 33.33 nanoseconds

![Latency numbers you should know - from bytebytego](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/d25ip368jj9z5tcp566t.jpeg)

To put these numbers into perspective, accessing data from L1 cache can be over 10 times faster than accessing the same data from L2 cache, and it can be more than 100 times faster than accessing it from RAM.

Efficient use of CPU caches is crucial for optimizing software performance because minimizing cache misses and utilizing cache-friendly algorithms can help reduce the impact of slower RAM access times. This is why understanding cache behavior and optimizing for cache locality is a key consideration in high-performance computing and software development.

### Summary

The importance of CPU caches in modern computing cannot be overstated. These small, high-speed memory storage areas play a pivotal role in enhancing software performance by reducing the latency of data access. Cache-aware programming, which involves optimizing code and data structures to maximize cache utilization, has a profound impact on software performance.

In summary, caches like L1, L2, and L3 are crucial for optimizing CPU performance by reducing memory access times. As a software engineer, understanding the basics of how caches work can help you write more efficient code, such as optimizing data access patterns and minimizing cache thrashing (when cache contents change frequently). However, the specifics of cache management are typically handled by the hardware and the operating system.