Ethernet-PHY, MAC, MII and network card
Tags: programming, beginners, python
Published: 2023-07-26 09:32:32

A Network Interface Card (NIC for short), also known as a network adapter, is a device that connects a computer to a local area network.As long as you connect to the local area network, you need a network card.A network card mainly includes the bottom two layers of OSI, the physical layer and the data link layer.The chip at the physical layer is called the PHY, and the chip at the data link layer is called the MAC controller.

The purpose of this article is to learn the basic MAC and PHY knowledge of Ethernet, summarize the system framework and physical hardware composition principles, and understand various interfaces.
PHY & MAC & MII

PHY

PHY is a physical interface transceiver, which implements the physical layer.It includes the MII/GMII (media independent interface) sublayer, PCS (physical coding sublayer), PMA (physical media additional) sublayer, PMD (physical media related) sublayer, and MDI sublayer.Defines the electrical and optical signals, line status, clock reference, data coding, and circuits required for data transmission and reception, and provides a standard interface to the data link layer equipment.The chip at the physical layer is called PHY.

MAC

MAC is an abbreviation for Media Access Control, which is the media access control sublayer protocol.This protocol is located in the lower half of the data link layer in the OSI Layer 7 protocol, and is mainly responsible for controlling and connecting the physical media of the physical layer.

When sending data, the MAC protocol can determine in advance whether the data can be sent. If it can be sent, some control information will be added to the data, and finally the data and control information will be sent to the physical layer in a specified format; when receiving data, the MAC protocol first determines whether the input information has a transmission error, if there is no error, then the control information is removed and sent to the LLC layer.Ethernet MAC is defined by the IEEE-802.3 Ethernet standard.

MII

MII is the media independent interface, also known as the media independent interface.It is the Ethernet industry standard defined by IEEE-802.3.It includes a data interface and a management interface between MAC and PHY.The data interface includes two independent channels for the transmitter and receiver, respectively.Each channel has its own data, clock, and control signals.

The MII data interface requires a total of 16 signals.The management interface is a dual-signal interface: one is a clock signal and the other is a data signal.Through the management interface, the upper layer can monitor and control the PHY.


![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/ipa8qx9h0ea8vtoxbur1.png)

It can be seen that MAC and PHY, one is the data link layer and the other is the physical layer; both transmit data through MII.

System composition

From the perspective of hardware, the circuit interface of Ethernet is generally composed of CPU, MAC (Media Access Control) controller, and physical layer interface PHY.：
picture
For the above three parts, not all of them are independent chips, there are mainly the following situations：
(1) MAC and PHY are integrated inside the CPU, which is more difficult；
(2) The CPU integrates the MAC internally, and the PHY adopts an independent chip (mainstream solution)；
(3) The CPU does not integrate MAC and PHY, and MAC and PHY use independent chips or integrated chips (high-end use).

PHY integrates a large amount of analog hardware, and MAC is a typical all-digital device. The reason for the chip area and the analog/digital hybrid architecture is that the MAC is integrated into the microcontroller and the PHY is left off-chip.More flexible and denser chip technology can already realize the single-chip integration of MAC and PHY.

Taking the commonly used CPU internally integrates the MAC, and the PHY adopts an independent chip scheme as an example. The dotted line indicates that the CPU and the MAC are integrated together, and the PHY chip is interconnected with the MAC on the CPU through the MII interface.


![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/ismtk7ckvvpjayavbc1z.png)

For this scheme, the hardware scheme is simpler than the independent one. There are the following two important hardware interfaces between PHY and MAC.：
(1) The MDIO bus interface is mainly to complete the register configuration of the CPU for the PHY chip.；
(2) MII is the media independent interface, also known as the media independent interface.The common ones are MII, RMII, GMII, RGMII, etc."Media independence" indicates that ANY type of PHY device can work properly without redesigning or replacing the MAC hardware.The MII data interface requires a total of 16 signals, including:
transmit data - TXD[3:0]
transmit strobe - TX_EN
transmit clock - TX_CLK
transmit error - TX_ER/TXD4
receive data - RXD[3:0]
receive strobe - RX_DV
receive clock - RX_CLK
receive error - RX_ER/RXD4
collision indication - COL
carrier sense - CRS
Generally speaking, it includes a set of signals used by the IC to read and write PHY: MDC (clock), MDIO (data) as two sets of clocks for data sampling reference, the frequency should be 25MHz (TX_CLK, RX_CLK) each 4-bit output and input Bus (TX[0:3], RX[0:3]); notify the other party to prepare the output of the input data, the input start signal (TX_EN); the output and input error notification signal (TX_ER, RX_ER); a notification signal (RX_DV) to obtain valid input data; a colision signal (Col) for network congestion.
As a signal (CRS) for carrier recovery, the potential can be +5V or +3.3V.

MII transmits data in both directions in 4bit, that is, nibble mode, with a clock rate of 25MHz and an operating rate of up to 100Mb/S.MII transmits all the data and data control of the network, while the MAC determines the working status of the PHY and controls the PHY by using the SMI (Serial Management Interface) interface to read and write the PHY's registers.Some of the registers in the PHY are defined by IEEE, so that the PHY reflects its current status in the register, and the MAC continuously reads the status register of the PHY through the SMI bus to know the current status of the PHY, such as connection speed, duplex capability, etc.Of course, you can also set the PHY register through SMI to achieve the purpose of control, such as flow-controlled opening and closing, self-negotiation mode or forced mode, etc.

Whether it is the physically connected MII bus and SMI bus, or the status register and control register of the PHY, there are IEEE specifications, so the MAC and PHY of different companies can coordinate their work.Of course, in order to match some of the unique functions of different companies' PHYS, the driver needs to be modified accordingly.

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/nfioma6zb7a4awu4z0it.jpg)

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