ARM EMBEDDED SYSTEM AND ARM PROCESSOR FUNDAMENTALS - PART 2
Published: 2024-01-24 18:36:24

Hello Readers,
My name is Sana, and I’m working at Luxoft India as a Junior Software Developer. Luxoft has given me several opportunities to work on numerous projects, which has stimulated me to discuss the crucial strategies concerned in ARM Embedded system. Here we will speak about the in-detail ARM Embedded system part 2.

**Introduction**
The ARM processor core is a key component of most successful 32-bit embedded systems. ARM cores are widely used in mobile phones, organizers, and a multitude of other everyday portable consumer devices.
The first ARM1 prototype was designed in 1985. Over 1 billion ARM processors had been delivered worldwide by the end of 2001. The ARM Company bases their success on a simple and powerful original design, which continues to improve today through the constant technical innovation. In fact, the ARM core is not a single core, but a whole family of designs sharing similar design principle and a common instruction set.
In this Article we discuss initially an overview of ARM design philosophy, an example of embedded device and its typical hardware and software technologies that surrounded an ARM processor. Then we discuss a brief description of ARM core model with its registers, mode and pipeline.

**ARM Core Data Flow Model**
The block diagram of an ARM core has functional units such as ALU, Address registers, Register file, Barrel shifter, MAC and Instruction decoder. All these functional blocks are connected by data buses, as shown in Figure, where the arrows represent the flow of data, the lines represent the buses, and the blocks represent either an function unit or a storage area. The figure shows not only the flow of data but also the abstract component that makes up an ARM core.
Data enter the processor core through the Data bus. The data may be instruction to be executed or a data element. Figure shows a Von Neumann implementation of the ARM in which the data item and instruction share the same bus. In contrast, Harvard implementation of the ARM use two separate buses, one for the data items and other for the instructions.
The instruction decoder translates the instructions into the binary form (execute form) before they are executed. One and all instruction executed be connected to a particular instruction set.
The ARM processor uses Load-Store architecture. This means it hold two instruction types for transferring data in and out of the processor. They are

- Load 
- Store

The load-store architecture is used on the ARM processor. Load instructions copy data from memory to register in the core, and conversely the store instruction copy data from register to memory. There are no data processing instructions that directly operate data in memory. Thus, data processing is carried out merely in registers.



![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/8tqkpp36qntjli1ac7sm.png)

**Operation:**

- Data items are set in the register file called as storage bank made up of 32-bit registers. Since the ARM core is a 32-bit processor, most of the instruction treat the register as holding signed or unsigned 32- bit values. The sign extends hardware transform signed 8-bit or 16-bit numbers to 32-bit values as they are read from memory and arranged in register.

- ARM instruction typically have two source register i.e., Rn and Rm, and Single result or destination register Rd. Source operands are read from register file using internal buses A and B respectively. The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn and Rm from the A and B buses and evaluates a result.

- Data processing instruction write the result to Rd directly to the register file. Load and Store instructions use ALU to generate an address to be hold in the address register and broadcast on the address bus.

- One important feature of the ARM is that register Rm alternately can be preprocessed in barrel shifter before it enters the ALU. Together barrel shifter and ALU is used to calculate a wide range of expression and addresses. 

- After passing through the functional elements, the result in the Rd is written back to register file using the result bus.
For Load and Store instruction the incrementer updates the address register before the core reads or writes next register value from or to next sequential memory location. The processor continues executing instruction until an exception or interrupt changes normal execution flow.

**ARM Registers**
General purpose registers carry either data or an address.
They are identified with the letter ‘r’ prefixed to register number. For example, register 4 is represent as r4. The processor can work in seven different modes. The below figure shows the active registers obtain in the user mode.


![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/ohr2tg7xirnbxq9d24su.png)

- All registers are shown are 32 bit in size.

● There are totally 18 active registers
● 16 data registers – r0 to r15
● 2 process status registers
● r13, r14, r15 have special functions
 
● r13 – stack pointer (sp) used as the stack pointer and stores the top of the stack in the current processor mode
● r14 – link register (lr) where the core holds the return address whenever it calls a subroutine.
● r15 – program counter (pc) and contains the address of the next instruction to be that needs to be executed.
● r13 and r14 can also be used as general purpose register which can be particularly useful since these registers are banked during processor mode change.
● the registers r0 to r13 are orthogonal. Any instruction that you can apply to r0, you can equally apply other registers.
●there are instructions that treat as r14 and r15 in a special way.

In addition to 16 data registers, there are two type of program status registers. They are;

- CPSR (current program status register)
- SPSR (saved program status register)
The register file contains all the register available to a programmer. Which registers are visible to the programmer relate to the current mode of the processor.