LPC 2148 ARM CPU
Published: 2024-01-27 15:49:41

Hello Readers,
My name is Sana, and I’m working at Luxoft India as a Junior Software Developer. Luxoft has given me several opportunities to work on numerous projects, which has stimulated me to discuss the crucial strategies concerned in ARM Embedded system. Here we will speak about the in-detail LPC 2148 ARM CPU.

**Introduction**
The LPC2148 microcontrollers are based on a 32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combines the microcontroller with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit memory interface and special accelerator architecture enable 32-bit code execution on maximum clock rate. For censorious code size applications, alternative 16-bit Thumb mode decrease code by more than 30 % with minimal performance penalty. Due to the small size and low power consumption, LPC2148 is perfect for applications where miniaturization is an essential requirement, like that access control and point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full Speed device, multiple UARTs, SPI, SSP to I2Cs, on-chip SRAM of 8 kB up to 40 kB, make these devices very good suitable fit for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and big processing power.  several 32-bit timers, single / dual 10-bit ADC(s) and DAC, PWM channels and 45 fast GPIO lines with up to 9 edge or level sensitive external interrupt pins build these microcontrollers particularly fitted for industrial control and medical systems.



**Features of LPC2148 Microcontroller**

- 16/32-bit ARM7TDMI-S microcontroller in a small QFP64 package.

- 8 to 40 KB of on-chip static RAM and 32 to 512 KB on-chip flash program memory.128 bit broad interface/accelerator enables high speed 60 MHz operation.

- In-System or In-Application Programming (ISP/IAP) through on-chip boot-loader software. One flash sector or full chip erase 400 ms and programming of 256 bytes in 1 ms.

- USB 2.0 Full Speed controllable1 Device Controller with 2 KB of endpoint RAM.  LPC2148 provides 8 KB of on-chip RAM available to USB by DMA.

- Two 10-bit A/D converters provide a complete of 6/14 analog inputs, with exchange times as low as 2.44 micros per channel.
- Single 10-bit D/A converter allocate variable analog output.

- Two 32-bit timers/external event counters (with 4 captures and 4 compare channels each), PWM unit (six outputs) watchdog.

- Low power real-time clock with independent power and allocated 32 kHz clock input.

- Multiple serial interfaces which includes two UARTs (16C550), two Fast I2C-buses (400 Kbit/s), 

- SPI and SSP with buffering variables data length capabilities.

- Vectored interrupt controller (VIC) with configurable priorities along with vector addresses.
- Up to 45 of 5 V tolerant fast general purpose I/O pins in a small LQFP64 package.
- Processor wake-up from power-down mode through external interrupt or BOD.
- Single power supply chip by POR and BOD circuits

- 60 MHz maximum CPU clock accessible from programmable on-chip PLL with settling time of 100us.


**Block Diagram of LPC 2148 Microcontroller**
As shown in the below figure the LPC2148 consist of an ARM7TDMIS CPU with emulation support,
- The ARM7 Local Bus connected to on-chip memory controllers.

- The AMBA Advanced High-performance Bus (AHB) for connected to the    interrupt controller, and

- The ARM Peripheral Bus (APB, a compatible superset of ARM's AMBA Advanced Peripheral Bus) purposed for connection to on-chip peripheral task.

The LPC2148 configure the ARM7TDMI-S processor in little-endian byte order. AHB peripherals assign a 2-megabyte range of addresses at the extremely top of the 4 gigabyte ARM memory space. Every AHB peripheral is assign a 16 KB address space inside the AHB address space. LPC2148 peripheral functions (other than the interrupt controller) are connected to APB bus. The AHB to APB bridge connected the APB bus to the AHB bus. APB peripherals are also all assign a 2 megabyte range of addresses, start at the 3.5 gigabyte address point. Each one APB peripheral is assign a 16 kB address space inside the APB address space.

The connection of on-chip peripheral to device pins is controlled by a pin connect block. This should be configured on software to fit particular application requirements for the use of peripheral function and pins.


![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/6mzsy5lxinc8prhoapmr.png)

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which provide high level performance and very low power utilization. The ARM architecture is build on Reduced Instruction Set Computer (RISC) principles, and the instruction set and associated decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simple results in a high instruction throughput and expert real-time interrupt feedback from a small and cost-effective processor core.

Pipeline techniques are in work so that all parts of the processing and memory systems can work continuously. Typically, while instruction is being executed, its successor being decoded, and a third instruction is being get from memory.

The ARM7TDMI-S processor also employs a special architectural strategy called as THUMB, which makes it ideally suitable to high-volume applications with memory limitation or applications where code density is a problem.

The crucial character behind THUMB is that of a super-reduced instruction set. Basically, the ARM7TDMI-S processor has two type of instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length permit it to arrive at twice the density of standard ARM code while retaining almost all of the ARM’s performance benefit over a traditional 16-bit processor using 16-bit registers. This is achievable because THUMB code operates on same 32-bit register set as ARM code.