Apple M1 Ultra is a mistake
Tags: m1, chip, apple, cpu
Published: 2024-04-26 12:31:57

Apple M1 Ultra use "dispatch center (virtual global unified warehouse, integration layer or platform, the parent company of the enterprise group)" model, which is a variant of my [warehouse/workshop model](https://github.com/linpengcheng/PurefunctionPipelineDataflow). It has two warehouse/workshop models (M1 Max) managed by a single dispatch center.

This model can avoid the complexity of hardware scale too large, It's a simple and fast implementation.

2022-03-14, I read in the Chinese news (["Apple'S M1 Ultra chip assembly secret found in patent"](https://www.cnbeta.com/articles/tech/1245843.htm)) that M1 Ultra uses UltraFusion encapsulation architecture based on TSMC Cowos-S5 architecture. I saw from the news and Cowos-S5 paper’s abstract (2021-06-01, [Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2](https://ieeexplore.ieee.org/document/9501649)) that it is similar to "AMD Infinity Fabric Architecture" and "Intel UCIe" technology, with only chip interconnection function and no scheduler function. reference: 2021-06-01, P. K. Huang; C. Y. Lu; W. H.
Wei R&D, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, R.O.C.; [Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2](https://ieeexplore.ieee.org/document/9501649)

I think:

- TSMC's approach doesn't have a scheduler because it lacks a complete base ecology, but Apple can use MacOS as a scheduler.

- Apple & TSMC's chip interconnection method is a mistake. The correct method should be memory interconnection, splicing the memory of two M1 Max into one large memory (or virtual large memory). Then M1 Ultra is not only A fractal system of M1 chip (standard warehouse/workshop model), but also a bigger M1 chip (standard warehouse/workshop model).

Apple has forgotten their previous slogan: "Bigger is Better" and "Bigger than bigger".

It is also a simple and high-performance approach. It can be used as solution of future M1 Supercomputing. It maintains the consistency of the Architecture of the Apple M Series chips, so it can maintain the simplicity, uniformity and compatibility of the system.

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/q1jom48j5qetaxkiyi7h.jpg)

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/ln5voe7f39xq0bz8qph8.jpg)

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/y3207njbhi53as5w1cj5.png)

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/uz3ii67vszdwb0ux9wc4.png)

![Image description](https://dev-to-uploads.s3.amazonaws.com/uploads/articles/dcocv6cli1oy8zq8vd2u.png)
		
- In the future, Apple must implement my dispatching center technology and implement OS kernel as DBMS-like ASIC. Currently, only Apple has a complete basic ecosystem. So it's the only one that can do that. reference: 2021.11.15, OS kernel as DBMS-like ASIC: The future OS kernel will be a data-oriented scheduler (with Computer hardware and software integration architecture diagram)

- MS windows + Intel (AMD), Google android + ARM can also be combined to have a complete base ecosystem, but the coordination takes a long time.

- ThrudTheBarbarian, a member of r/chipdesign (a chip design forum) who has worked at Apple for almost a couple of decades, commented on my post on r/chipdesign on 2022-03-15 22:07:28(UTC+8)

> Uh huh. Maybe you’re right. Maybe some of the highest-paid, and certainly one of the best silicon design teams on the planet are wrong, but extraordinary claims require extraordinary evidence.

> The chip, from advance talks and benchmarks, seems to perform fairly well. We’ll find out soon.
Apple are not beholden to any particular internal architecture, as a founder of ARM, they have a perpetual license that allows them to do whatever they want internally, so I could see different internal design for the M2 (or whatever is put into the Mac Pro). They only need to remain compatible at the ABI/Instruction-set interface.

I don't agree with him, the M1 Ultra perform fairly well because it has two M1 Max spliced together, I really can't imagine how bad architecture would make it perform worse than a M1 Max, this is a really low standard for evaluation.

The Apple M1 Ultra's architecture is a complex solution, It destroys the simplicity and unity of my warehouse/workshop model which M1 adopts as architecture, Therefore, the scalability and compatibility are extremely poor, which brings about the complexity of the system, and the manufacturing cost, process complexity and difficulty are all high.

My architecture conforms to the two basic principles of simplicity and unity in scientific research, mathematics, and industry. It has excellent scalability and compatibility. Simplicity is the foundation of high performance and high reliability. It can be judged and concluded by obvious scientific common sense: my architecture is far superior to the architecture of the Apple M1 Ultra.

r/chipdesign has deleted my post and banned me permanently, I can only post screenshots.

[ThrudTheBarbarian's commend full screenshot](https://github.com/linpengcheng/PurefunctionPipelineDataflow/blob/master/doc/image/ThrudTheBarbarian_comments_M1Ultra_is_a_mistake_2022_03_15.png)

[ThrudTheBarbarian work at Apple full screenshot](https://github.com/linpengcheng/PurefunctionPipelineDataflow/blob/master/doc/image/ThrudTheBarbarian_work_at_apple_2022_03_15.png)
	
Conclusion:

- Apple's understanding of my theory is not good enough.

- My warehouse/workshop model will definitely be the architecture of all computers (including supercomputers) in the future.

[2022-03-14, a discussion at r/programming](https://www.reddit.com/r/programming/comments/tdx4nc/m1_ultra_is_a_mistake/)