Timing- and crosstalk-driven area routing
We present a timing- and crosstalk-driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. The new approach fits between global routing and detailed muting along the physical design flow It is the first to address the timing- and crosstalk-driven area routing problem using crosspoint assignment prior to the detailed routing stage, in contrast to the most previous approaches applied in the post-detailed routing stage. Our new approach enjoys a larger optimization solution space than the previous approaches whose solution space is highly Limited by routed geometric constraints, Based on the global routing information, our graph-based optimizer preroutes wires on the global routing grids incrementally, The graph-based optimizer has two stages, net order assignment and space relaxation, A quick capacitance extraction and Elmore delay calculator considering signal switching activities are implemented to find the timing of critical nets and to provide the timing slack database of critical nets. As the graph-based algorithm proceeds, the path delay of critical nets and the timing slack database are updated, During the optimization process, it only optimizes the timing critical paths with negative slack values, The experimental results show a 5%-16% delay reduction for MCNC macrocell benchmark circuits far a 0.25-mum process for wire geometric ratio (height/width) = 1.0, against a 25% delay reduction if there is infinite space around each metal,Fire on the same layer. it shows a remarkable 8.4%-25% delay reduction for MCNC benchmarks for wire geometric ratio = 2.0, against a 33% delay reduction if there is infinite space around each metal wire. its experimental results indicate, our new approach overall achieves an average 46% reduction on intralayer coupling capacitance. Therefore, the delay reduction by our optimizer is more significant when the minimum feature size continuously shrinks and the wire geometric ratio increases.
crosstalk area routing net order timing driven