Power Optimization With Power Islands Synthesis
With the migration to Deep Sub-Micron process technologies, the power consumption of a circuit has come to the forefront of concerns, and as a result, the power has become a critical design parameter. This paper presents a novel high-level synthesis methodology, called Power Islands Synthesis, that eliminates the spurious switching activity and the leakage in a great portion of the resulting circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independently from the rest of the circuit and hence can be completely powered down when all of the logic it contains is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. By powering down an island during its idle cycles, the following occur: 1) The spurious switching that results from the broadcast to idle components is silenced and 2) the power consumption due to leakage in inactive components is eliminated. Experiments conducted on several synthesis benchmarks implemented at the layout level with a 65-nm process technology and simulated using a transistor-level simulator showed power savings ranging from 5% to 20% due to our methodology. The reported savings were entirely from the power down of combinational elements (functional resources) of the data path.
power optimization power islands power islands synthesis spurious switching activity partitioning clustering behavioral synthesis dynamic power high level synthesis leakage power