A dynamic and differential CMOS lookup table with data-independent power consumption for cryptographic a
Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic functions for implementation on chip cards. In this paper, a dynamic and differential lookup table (LUT) is presented and evaluated on a case study simulation. The proposed circuit shows a power consumption independent from the input data and can be employed to implement combinatorial functions in cryptographic processors when a high resistance against tampering is required. A typical application is the design of nonlinear functions ( for example, substitution boxes) since protecting them with less expensive countermeasures ( for example, random masking) implies a significant overhead. In the adopted case study, a 1.02 percent spread in the power consumption has been obtained when parasitic capacitances are taken into account. Moreover, a comparison with a static complementary metal-oxide semiconductor implementation shows an acceptable overhead in terms of area and power consumption.
differential power analysis power analysis dpa chip cards differential logic dual-rail logic cryptography