A Novel VLSI Architecture of SPIHT Using Breadth First Search for Real-Time Applications
A bit-plane parallel architecture for a modified set partitioning in hierarchical trees (SPIHT) without lists algorithm, which uses breadth first search scheme, is proposed. The breadth first search scheme is suitable for very large scale integration (VLSI) implementation based on the analysis of SPIHT algorithm. The architecture has advantages of high parallelism, no intermediate buffer as a single tree is scanned. After field programmable gate arrays (FPGAs) synthesis and simulation, the throughput of the proposed architecture can reach 60 MSample/Sec. As the breadth first search scheme is very similar to that of SPIHT with lists, the quality of reconstructed images is almost the same with that of SPIHT with lists.
spiht image compression bit plane-parallel