Optimal instruction set design through adaptive database generation
This paper proposes a new method to design an optimal pipelined instruction set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partitioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive database approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.
adaptive database generation asip hw/sw partitioning performance estimation