hybrid latch flip-flop with improved power efficiency
An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20\%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.
hybrid latch flip-flop hybrid flip-flops power efficiency power design power consumption delays circuits power-delay-product improvement soft-clock edge properties keeper elements feedback path feedback transit circuit feedback product delay reduction clock low-power electronics precharge technique logic design power consumption reduction power efficiency improvement