hierarchical partitioning for field-programmable systems
This paper presents a new recursive bipartitioning algorithm for a hierarchical field-programmable system. It draws new insights into relating the quality of the bipartitioning algorithm to circuit structures by the use of the partitioning tree (Hagen et al., 1994). The final algorithm proposed not only forms the basis for the partitioning solution of a 1-million gate field programmable system (Lewis et al., 1997) but can also be applied to general VLSI or multiple-FPGA partitioning problems.
hierarchical partitioning field-programmable systems recursive bipartitioning algorithm quality circuit structures partitioning tree vlsi logic cad field programmable gate arrays fpga partitioning problems