A new reasoning scheme for efficient redundancy addition and removal
Redundancy addition and removal is a rewiring technique which, for a given target wire w(t), finds a redundant alternative wire w(a). The addition of w(a) makes w(t) redundant and, hence, removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, in the earlier methods, the search for valid alternative wires required trial-and-error redundancy testing of a potentially large set of candidate wires. Here, we study the fundamental theory behind this technique and propose a new reasoning scheme (RAMFIRE), which directly identifies alternative wires without performing trial-and-error tests. Experimental results show speedup of up to 15 times than that of the best techniques in the literature.
logic restructuring logic synthesis physical synthesis timing optimization