system-level exploration of run-time clusterization for energy-efficient on-chip communication
System-level exploration of run-time power clusterization for energy-efficient on-chip communication is presented. Facilitated by multiple on-chip power-delivery-networks, areas of heavy or low traffics can be dynamically identified and adaptively supplied with new power schemes. This method is superior to design-time voltage island partitioning, in dealing with unpredictable spatial and temporal variations of communication traffics in large NoCs. Architectural design of the platform and online iterative configuration process are presented. The effectiveness of the proposed approach is demonstrated quantitatively on a NoC simulator with 65 nm power models. With synthetic traffic traces characterizing various communication patterns, run-time power clusterization achieves considerable energy benefits compared to existing energy-efficient architectures (9\%--42\% lower). The latency penalty is predictable and moderately bounded with minimal area overhead. The proposed architecture presents an ideal tradeoff, prioritizing energy efficiency, for massively parallel on-chip computing.
run-time clusterization energy-efficiency on-chip communication system-level design network-on-chip