seu mitigation for sram-based fpgas through dynamic partial reconfiguration
This paper presents a methodology for designing reliable systems implemented on Field Programmable Gate Arrays (FPGAs), able to cope with the effects of Single Event Upset (SEU) faults, causing bit-flips in SRAM memory. The approach exploits FPGAs' partial dynamic re-configuration capability to mitigate the effects of SEUs, affecting either the user SRAM memory or the configuration memory itself. The goal is to detect the occurrence of faults and either to restart computation or to trigger a reconfiguration of part of the device in order to recover from them. The proposal allows the exploration of different solutions, characterized byvarying costs and benefits, allowing the designer to select the most convenient trade-off. Results of the application of the methodology to a case study are reported to evaluate the proposed approach.
seu partial dynamic reconfiguration fault detection