Joint equalization and coding for on-chip bus communication
In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mu m CMOS technology show that 1.28 X speedup is achievable by equalization alone and 2.30 X speedup is achievable by joint equalization and coding.
equalization coding delay crosstalk avoidance interconnection networks on-chip buses system-on-chip (soc)