Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening
This paper describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gao's algorithm by resolving its bottleneck related to generation of fan-shaped forbidden regions along a wire. We also describe a method for simultaneous wire-spreading and wire-fattening, which consists of enlarging forbidden regions generated by the detailed routing algorithm as long as there remains any space through which wires can pass, From the experiments me obtained the result that the average CPU time of the detailed routing algorithm is almost linear to the length of a wire. Since the curvilinear detailed routing is efficient in terms of space usage, the proposed algorithm is important especially for densely mired printed circuit boards such as pin grid array packages, ball grid array packages, and multichip modules. We can also expect improvements on the electrical characteristics and the production yield by applying wire-spreading and mire-fattening to them.
detailed routing physical routing yield improvement