CMOS zero-temperature-coefficient point voltage reference with variable-output-voltage level
A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-mum CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94ppm/degreesC over the temperature range from -100degreesC to 150degreesC at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.
cmos zero-temperature-coefficient point voltage reference substrate bias variable-reference-voltage level