power-efficient and scalable load/store queue design via address compression
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fully-associative CAM structure to search the address for collision and consequently poses scalability challenges of power consumption and area cost. Using the proposed approach, the LSQ can reduce the area cost ranging from 32\% to 66\% and power consumption ranging from 38\% to 71\%, depending on the compression parameter. The approach can provide 3.08\% overall processor energy reduction and causes only 0.22\% performance loss at an optimal configuration.
power-efficient address compression scalable design load-store queue