A Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking: Part 2: Motion compensation
This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. In Part 1, the motion estimation part of the proposed architecture is presented. Here in Part 2, a new C-RAM mesh-based motion compensation architecture is presented. The input data to the architecture is the mesh nodes motion vectors and the reference frame and the output data is the compensated (i.e., predicted) frame. The architecture uses the affine transformation for warping the deformed patches in the reference frame into the undeformed patches in the current frame. The architecture computes the affine parameters using a multiplication-free algorithm. The reference and current frames are stored in embedded S-RAMs generated with Virage (TM) Memory Compiler. The proposed motion compensation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 mu m CMOS technology. Using 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352 x 288 pixels) in 0.59-ms, which means it can process up to 1694 frames per second. The core area of the proposed motion compensation architecture is 28.04 mm(2) and it consumes 31.15 mW.
motion compensation computational ram mesh-based architectures video coding