Partial product reduction by using look-up tables for MN multiplier
In this paper we present a new technique for partial product reduction in multiplication operations. The method is based on the construction of counter elements by means of look-up tables. The organization of these counters into reduction trees takes advantage of the inherent benefits of the integration of the memories and provides an alternative to classic operation methods. We show several reduction schemes that illustrate the proposed technique and describe hybrid examples that combine stored logic with classic combinational counters in order to adapt them better to each scheme. Our approach outperforms other schemes used for comparison. In this sense, not only an independent technology model has been established, but also an FPGA approximation has been implemented to measure such factors in a real-life technology platform.
multiplication computer arithmetic arithmetic and logic structures high speed arithmetic