Intermediate representations for design automation of multiprocessor DSP systems
Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidance of over-constrained synchronization, and its simplified clocking requirements. However, analysis and optimization of self-timed systems under real-time constraints is challenging due to the complex, irregular dynamics of self-timed operation. In this paper, we review a number of high-level intermediate representations for compiling dataflow programs onto self-timed DSP platforms, including representations for modeling the placement of interprocessor communication (IPC) operations; separating synchronization from data transfer during IPC; modeling and optimizing linear orderings of communication operations; performing accurate design space exploration under communication resource contention; and exploring alternative processor assignments during the synthesis process. We review the structure of these representations, and discuss efficient techniques that operate on them to streamline scheduling, communication synthesis, and power management of multiprocessor DSP implementations.
self-timed scheduling interprocessor communication dataflow graphs embedded systems digital signal processing