clock even suppression algorithm of velvet and its application to s-820 development
An advanced clock event suppression algorithm for high-speed logic simulation is described. A new signal value Cn and a current clock (CC), which indicates the current status of clock signals, has been introduced to realize this algorithm. This algorithm suppresses about 60\% of the total events, and eliminates 40\% of CPU time. No overhead is needed to incorporate this algorithm using hardware support of VELVET (vectorized processing system for logic verification). Hitachi's latest supercomputer S-820 has been developed using VELVET. The development period has been shortened to 3/4 that of the S-810.
clock algorithm applications developer event logic simulation signaling value timing hardware support process systems verification supercomputer