Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability
In this work, we proposed a single-ended read disturb-free 9T SRAM cell for bit-interleaving application. A column-aware feedback-cutoff write scheme is employed in the cell to achieve higher write margin and non-intrusive bit-interleaving configuration. And a dynamic read-decoupled assist scheme is utilized by cutting loop to relax the interdependence between stability and read current, resulting in robust read operation and better read performance simultaneously. Moreover, the lower write and leakage energy consumptions are also achieved. We compared area, stability, SNM sensitivity and energy consumption between proposed 9T and standard 6T bit-cells. The write ability of 9T cell is 1.40 higher that of 6T cell at 1.0V, and 8.16 higher at 0.3V. The write and leakage energy dissipations are 26% and 13% lower than that of 6T at 1.0V. In addition, robust read and better process variation tolerance are provided for proposed design with area penalty.
9t sram bit-interleaving disturb-free sram loop-cutting