High voltage degradation of GaN High Electron Mobility Transistors on silicon substrate
We have electrically stressed GaN High Electron Mobility Transistors on Si substrate at high voltages. We observe a pattern of device degradation that differs markedly from previous reports in GaN-on-SiC HEMTs. Similarly to these devices, the gate leakage current of GaN-on-Si HEMTs increases by several orders of magnitude at a certain critical voltage and this increase is irreversible. However, in contrast with devices on SiC, the critical voltage varies substantially across the wafer, even over short distances, with values as high as 75V being observed. In addition, for voltages below the critical voltage, we observe a prominent degradation in the drain current and the source and drain resistances, something not observed in devices on SiC. This degradation is almost completely recoverable under UV illumination. We attribute these results to the high mismatch that exists between GaN and Si that leads to a large concentration of electrically active traps and a lower and non-uniform initial strain in the AlGaN barrier. This is evidenced by observed correlations between threshold voltage and maximum drain current in fresh devices and their corresponding critical voltages.
degradation critical voltage trapping gan on si hemt reliability