Design of a nanopower current reference with reduced process variability
In this paper we present the design of a 0.18 mu m CMOS current reference based on a variability-aware approach, in such a way to obtain a very low process sensitivity of the reference current. Its relative standard deviation is 1.4 % based on measurements performed over 23 samples from a single batch. The requirement of low process sensitivity is met together with the very low power consumption of 290 nW, at the cost of a large area occupation of 0.245 mm(2). Key to obtain this result are the use of the "classical" bipolar bandgap topology, which can be optimized for low-power/low-spread operation so as to outperform MOS-based bandgap circuits, and the use of devices that are intrinsically more stable towards process, such as diffusion resistors.
reference current generator variability-aware design analog design low power cmos circuits