Clock recovery based on packet inter-arrival time averaging
Accurate source clock recovery is an important element of circuit emulation services (CES) over packet networks. A well-known and widely implemented technique for clock recovery in CES is the one that is based on packet inter-arrival time (sometimes called time difference of arrival (TDOA)) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has not been fully characterized analytically in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyze the effects of correlation of the PDV experienced by the constant bit rate (CBR) traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the PDV produces a large variance of the recovered clock. The paper also describes simple all-digital implementations of the clock recovery scheme using standard digitally controlled oscillators (DCOs). (c) 2005 Elsevier B.V. All rights reserved.
clock recovery circuit emulation packet networks packet delay variation pdv digitally controlled oscillator dco tdm timing recovery clock synchronization phase-locked loop jitter