Design and verification of peripheral control circuits in Esterel
We present a case study showing how an existing concurrent programming language can be used to produce either efficient control-oriented circuits or embedded software from the same description. This description is also amenable to fully automatic formal verification and can be used to produce pairs of reconfigurable components which can be dynamically scheduled into either hardware or software resources. By using an existing concurrent language we increase the productivity because we can make use of readily available tools for debugging, analysis and verification. We believe that a language and a system that generates good software and hardware is a promising starting point for helping mainstream software developers target future manycore systems which will comprise a mixture of software and hardware components as well as provide a valuable technique for producing interchangeable reconfigurable components for run-time reconfigurable FPGAs. Copyright (C) 2007 S. Singh. [Correction made here after initial online publication]
formal verification circuit synthesis synchronous hardware descriptions