fast hazard detection in combinational circuits
In designing asynchronous circuits it is critical to ensure that cir-cuits are free of hazards in the specified set of input transitions. In this paper, two new algorithms are proposed to determine if a com-binational circuit is hazard-free without exploring all its gates, thus providing more efficient hazard detection. Experimental results in-dicate that the best new algorithm on average visits only 20.7\% of the original gates, with an average runtime speedup of 1.69 and best speedup of 2.27 (for the largest example.
hazards asynchronous circuits logic design