A novel dual-modulus 2.8 GHz divide-by-127/128 prescaler using pull down transistor in 0.35 mu m CMOS technology
Design of high divide-by-value dual-modulus prescaler remains a challenge in CMOS realization for high speed operation. Prior arts for dual modulus prescaler either divide by a low divide-by-value or cannot operate at high speed. The proposed topology is suitable for high divide-by-value operation at high speed.
dual-modulus prescaler cmos filp-flop pll counter