Enhancement of gettering efficiencies of different silicon substrates during a 0.18 ?m LTB CMOS process simulation : Stratigraphy by a novel chemical ultra-trace depth-profiling
We have performed a gettering efficiency (GE) test at different stages in a 0.18 ?m LTB CMOS process simulation with maximal temperatures of 1000C. Four sorts of wafer substrates (epi, polished) were processed to the point before the step to be studied and then contaminated with 51012 atoms/cm2 Cu or Ni with a spin-on technique that was optimized for reproducibility. Afterwards, the wafers were process simulated and analyzed by ICP-MS in combination with a novel chemical depth-profiling procedure. Although none of the wafers showed detectable BMDs by preferential etching and FTIR measurements, BMDs could be found by LST measurements. Epitaxial p/p+ wafers exhibited an outstandingly high GE for Cu at each studied process step due to segregation gettering by the heavily boron doped substrate. Polished wafers showed a lower GE which increased with the process time. Thus, Cu gettering was a function of the size of oxygen precipitates. On the contrary, Ni gettering was not enhanced in epi wafers compared to the polished wafers. Also, no segregation gettering is assumed for Ni, however, a higher initial oxygen concentration led to a higher GE. Thus, Ni gettering is strongly influenced by the oxygen precipitate size, too. A more stable Cu and Ni gettering was found with BMD-densities of 109 cm?3, measured by LST, although preferential etching and FTIR measurements were below the detection limit.
gettering efficiency gettering mechanisms copper (cu) nickel (ni) silicon (si) low-thermal-budget (ltb) cmos process