fast dual-vdd buffering based on interconnect prediction and sampling
This paper presents fast algorithms for power-optimal interconnect synthesis based on interconnect prediction and sampling considering dual V dd buffers. We present three pruning techniques including interconnect prediction based pruning ( pre-buffer slack pruning and predictive min-delay pruning ) and sampling ( 3D sampling ), of which 3D sampling is effective but the other two improve both efficiency and accuracy of sampling. We also show that the key to runtime reduction is to reduce the number of propagated options, while the sophisticated data-structures which have good amortized complexity do not necessarily reduce runtime. We obtain an empirically linear time algorithm with less than 1\% of delay and power increase but over 50x speedup compared with the most efficient algorithm for dual V dd buffer insertion. In addition, we further enhance the power-optimal buffered tree construction by introducing routing grid reduction. We apply our speedup techniques to buffered tree construction algorithm. Experimental results show that we obtain over 100x speedup compared with the most efficient existing algorithms for dual V dd buffered tree construction.
interconnect buffer insertion routing dual-v dd  low power