Low-power mixed-signal CVNS-based 64-bit adder for media signal processing
In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-mu m technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250 mu m(2).
64-bit adder media signal processing continuous valued number system (cvns) analog digits mixed signal adder reconfigurable adder