branch merge reduction of rlcm networks
In this paper we consider the problem of finding asmaller RLCM circuit that approximately replicates thebehavior (up to a certain frequency) of a given RLCM circuit.Targeted at parasitic extractors for verification of VLSIdesigns, the proposed algorithm uses a branch merge, nodeelimination methodology, with the choice of nodes forelimination being guided by time-constant criteria.Reliable,accurate, easy to code, the algorithm works well for coupledbuses and clocks, strongly inductive networks, and low-losstransmission lines, as well as for lossy RLC networks.
parasitic extraction model order reduction gaussian elimination transmission-line modeling