"It's a small world after all": NoC performance optimization via long-range link insertion
Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.
design automation multiprocessor system-on-chip (mp-soc) network-on-chip (noc) performance analysis