Standby supply voltage minimization for deep sub-micron SRAM
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13?m technology. Due to a large on-chip variation, DRV of the 4KB SRAM module ranges between 60 and 390mV. Measurements taken at 100mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.
sram data retention drv variation leakage suppression state preservation