minimizing bank selection instructions for partitioned memory architecture
Bank switching is a technique that increases the code and data memory in microcontrollers without extending the address buses. Given a program in which variables have been assigned to data banks, we present a novel optimization technique that minimizes the overhead of bank switching through cost-effective placement of bank selection instructions. The optimal placement is controlled by a variety of different objectives, such as runtime, low power, small code size or a combination of these parameters. We have formulated the problem as a form of Partitioned Boolean Quadratic Programming (PBQP).We implemented the optimization as part of a PIC Micro-chip backend and evaluated the approach for several optimization objectives. Our benchmark suite comprises programs from MiBench and DSPStone plus a microcontroller real-time kernel and drivers for microcontroller hardware devices. Our optimization achieved a reduction of program memory space between 2.7\% and 18.2\%, and an overall improvement with respect to instruction cycles between 5.1\% and 28.8\%. Our optimization achieved an optimal solution for all benchmark programs.
partitioned memory architecture microcontrollers bank-switching compiler optimization pbqp ram allocation