ENERGY ESTIMATION FOR n-INPUT ADIABATIC LOGIC GATE: A PROPOSED ANALYTICAL MODEL
In this paper, an analytical model is proposed to estimate the energy consumption of n-input adiabatic logic gate. The model is based on RC linearization of the adiabatic circuit network. To validate the model expressions, simulations are carried out at 90 nm technology node using the Cadence Spectre simulator. Model validates with simulation results at a maximum error equals to 9.94%. Model expressions are also applied in comparison of energy performance of adiabatic logic and conventional CMOS logic. Proposed research work suggests the operating conditions which makes the adiabatic logic more energy efficient than conventional CMOS logic.
adiabatic switching energy estimation model energy recovery logic low-power cmos circuit