A parametric VLSI architecture for video motion estimation
This paper presents a VLSI macro-cell for the implementation of full-search (FS) motion estimation that is a key issue of various video processing and compression standards such as MPEG and H.263. Beyond the usual algorithm, advanced-prediction and static-priority options are supported to improve the SNR/bit-rate efficiency. The architecture is fully parametric in terms of block size and maximum search area size and the latter is also dynamically programmable. Based on a hardware multiplexing strategy and a saturation mechanism, the architecture features high throughput/area efficiency and reduced hardware complexity with respect to conventional FS systolic arrays. Two ASICs were implemented on a 0.25?m CMOS technology. The high-speed one features a 5.4mm2 core size and processes up to 4CIF format at 105MHz. The smaller one features a 2mm2 core size and processes QCIF and CIF formats at 18 and 72MHz, respectively. Exploiting the search area size programmability, these two formats can be processed with an average power consumption of 16 and 65mW, respectively, which is of paramount interest for wireless applications.
motion estimation image coding very large scale integration (vlsi) high-speed integrated circuits low-power circuits