Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-seriesparallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80 speed-up when comparing to electrical simulation.
cmos complex gates static power dissipation subthreshold leakage gate oxide tunneling