Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose
The data throughput of SDRAMs is significantly reduced by the control overhead required for access or transposition of large two-dimensional data matrices stored in SDRAM memories. In this paper, a new address mapping scheme is introduced, taking advantage of multiple banks and burst capabilities of modern SDRAMs. In this way, the data throughput is maximized when reading or writing rows or columns of a two-dimensional data matrix. Other address mapping strategies minimize the total number of SDRAM page-opens while traversing the two-dimensional index-space in row or column direction. In order to achieve a higher data throughput, the new approach uses an alternative bank interleaving method to hide additional wait cycles. In this way, the number of data bus wait cycles do not depend on the overall number of page-opens directly any more. It is shown, that the data bus utilization can be increased significantly. In particular, the new mapping strategy is optimized for access of parallel samples, distributed among a number of SDRAM chips. Therefore, double buffering can be omitted. As a special operation, 2D-FFT processing for radar applications is considered. Depending on SDRAM parameters and dimensions, a continuous bandwidth utilization of 96-98 % is achieved for accesses in both matrix dimensions, including all page-opens and refresh operations.
sdram two-dimensional transpose 2d large matrices