analysis and optimization of thermal issues in high-performance vlsi
This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.
analysis optimality high-performance performance paper attention reliability effect interconnect design conflict large-scale circuits minimal scheme influence physical design rules clock skew