Performance and energy impact of parallelization and vectorization techniques in modern microprocessors
While Moores law states that the number of transistors is approximately doubled every 2years, powering these transistors simultaneously is only possible as long as Dennard scaling continues. Unfortunately, voltage scaling has slowed down in recent years, and microprocessor designers have hit what is known as the utilization wall or the dark silicon effect. Vectorization, parallelization, specialization and heterogeneity are the key approaches to deal with this utilization wall. However, how software developers can maximize energy efficiency of these architectures remains an open question. This paper presents an energy evaluation of parallelization using both physical and logical cores (i.e., SMT/Hyper-Threading), vectorization (SSE, Advanced Vector Extensions and NEON) and dynamic core reconfiguration [\(\hbox {Intel}^{\circledR }\)s Turbo Boost Technology (TBT)]. The evaluation spans microprocessors for embedded, laptop, desktop and server markets, since there is a convergence among them towards energy efficiency. The analyzed processors include Intels Core\(^\mathrm{TM}\) i5 and i7 family and ARM\(^{\circledR }\)s Cortex\(^\mathrm{TM}\) A9 and A15. Results show that software developers should prioritize vectorization over thread parallelism when possible, as it yields better energy efficiency, especially on the Intel platforms. Application scalability can be reduced drastically when using vectorization and threading simultaneously since vectorization increases pressure on the memory subsystem. Intels TBT further improves energy efficiency by an additional 1020% depending on the number of active threads.
vectorization energy efficiency performance evaluation 68-04