Optimized Hardware Implementation for Forward Quantization of H.264/AVC
An efficient implementation for the computation of the forward quantization of H.264/AVC is presented. It uses a modified reformulation of quantization expressions, in full compliance with the standard, combined with an adaptive truncated Booth multiplier to reduce hardware complexity. The JM reference softwares C code has been rewritten to analyze the effect of the proposed approach. Simulations carried out on several typical video sequences with different texture characteristics demonstrate the validity of this approach with an improvement in the PSNR at low QP, between a maximum of +0.8dB and a minimum of 0.3dB, with a slight increment in the bit-rate of about 0.8%. However, this improvement is smoothed for typical values of QP and only an insignificant difference is found with respect to the JM results. The proposed architecture synthesized in the AMS 0.35?m technology, which is suitable for VLSI implementation, reduces the area by 26%, the power by 32% and the critical path delay by 21% in comparison with a classic implementation.
quantization h.264/avc truncated booth multiplier