Automatic simulation and verification of pipelined microcontrollers
This paper presents a methodology for automatic simulation and verification of pipelined microcontrollers. Using this methodology, we can generate the simulation for the instruction set architecture (ISA), abstract finite slate machine (FSM) and pipelined register transfer level design and compare the simulation results across different levels quickly. We have implemented our method in the simulation and verification of a synthesized microcontroller HT_4 using our behavioral synthesis tool.
simulation microcontrollers functional verification high level synthesis microprocessors