RLC coupling-aware simulation and on-chip bus encoding for delay reduction
This paper shows. that the worst case switching pattern that incurs the longest bus delay While considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses.
coupling worst case switching pattern inductance bus-invert method interconnect delay