Robust design of LV/LP low-distortion CMOS rail-to-rail input stages
Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage (less than or equal to 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K-p, K-n mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.
robust rail-to-rail low voltage constant-g(m) input stage maximum current selecting circuit transconductance equalizer bias circuit