Data reordering converter: an interface block in a linear chain of processing arrays
This paper addresses the problem of hardware synthesis of data reordering converter intended to reorganize the layout of transferred data between various processing stages (components) with different I/O format requirements. The proposed design is based on two objectives: (a) fixed bandwidth to main memory, and (b) scalability to higher performance without increasing main-memory bandwidth. The data reordering converter involves two address transformators and an array of dual-port RAMs. The use of distributed dual-port RAM architecture provides several benefits. First, to exploits parallelism, second, to achieve very high-speed data transfer, and third, to allow random access to data elements within the stream. We outline a new architecture for interfacing processing stages in a linear chain, which operate in a pipeline-parallel fashion that trades speed advantages of systolic/processor arrays with area advantages of high wire organizations. An implementation, in VLSI, of address transformators is described, and shown why data reordering converter is useful in designing special purpose high-performance computing for embedded digital signal processing applications.
data reordering converter address transformator digital signal processing accelerator memory bandwidth scalable coprocessor system