A framework for the functional verification of SystemC models
The problems of error simulation, error model evaluation, and test generation are faced considering the peculiar features of SystemC. In particular, error simulation are considered in the perspective of the transaction level modelling (TLM) capabilities of this emerging system level design language to obtain a coherent, environment for functional verification. The error simulation is accomplished without any modification of the native simulation engine, thus avoiding the problem of upgrading the error simulator together with the language simulation engine. Moreover, error modelling and error simulation tasks are orthogonalized in this approach. With the support of this environment, a test pattern generation algorithm for SystemC descriptions of systems made of interacting Finite State Machines (FSMs) is developed. The approach is based on the definition of the transitions, that represent ordered sets of statements executed within one clock cycle. Through different state sequence paths enumeration strategies, interesting behaviors of the system are obtained.
functional verification systemc test pattern generator