accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits
We propose an accuracy driven synthesis methodology for analog circuits. The proposed approach relies on macro-models for performance estimation and is thus orders of magnitude faster than simulation based synthesis techniques. Unlike existing macro-model based approaches, which use static models, our approach dynamically improves the accuracy of the model during synthesis to ensure true convergence. Our method is based on identifying and accurately modeling those regions in the design space where feasible designs lie. The identified feasible regions and their corresponding models are used in conjunction with an initially generated global model for performance estimation. Experimental results demonstrate that the proposed approach is able to synthesize designs using the enhanced performance models quickly, yet accurately.
performance modeling circuit sizing analog synthesis