P(2)EDAS: Asynchronous, distributed event driven simulation algorithm with inconsistent event preemption for accurate execution of VHDL descriptions on parallel processors
The DoD's Very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype. Since its conception in the early 1980s, an important goal of VHDL has been to execute complex models concurrently and efficiently on parallel processors. To achieve this objective while exploiting the maximum theoretical parallelism, one requires a deadlock-free, asynchronous, distributed, discrete event simulation algorithm. The YADDES approach, proposed in the literature, achieves deadlock-free, distributed, discrete event simulation, but suffers from an important limitation. YADDES assumes that every entity is characterized by a single propagation delay. In contrast, for hardware entities such as gates, flip-flops, ALUs, and microprocessors, two or more propagation delay values are used corresponding to every path between the input and output. While the use of multiple delays aims at accurate representation of reality, often inconsistent events may be generated that must be detected and preempted. This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P-2 EDAS. P-2 EDAS represents a significant advancement in that it permits the use of any number of propagation delays for every path between the input and output of every hardware entity. P-2 EDAS permits, for the first time, accurate, concurrent, asynchronous, and efficient, i.e., deadlock-free and null-message-free, execution of VHDL models of sequential and combinatorial digital designs on parallel processors. A model refers to a VHDL entity. It is a conservative algorithm in that only those output transitions, ii any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, it accurately detects and preempts inconsistent events. To achieve efficiency in the simulation of actual system designs, especially large-scale designs, P-2 EDAS is designed to exploit coarse-grain parallelism, focusing on entities with significant computational complexities. P-2 EDAS is not limited to VHDL models only, it extends to hardware descriptions described in any high-level hardware description language. This paper presents a detailed description of the algorithm, illustrative examples, and mathematical proofs of correctness, freedom from deadlock, and termination of simulation in finite time. P-2 EDAS is implemented for VHDL on both a multithreaded shared memory multiprocessor and a network of Pentium-based Linux workstations, configured as a loosely coupled parallel processor. Performance analysis reveals that P-2 EDAS achieves superior speedup for a number of representative digital designs, including a large computer system-the DLX architecture.
event driven simulation vhdl discrete event simulation digital simulation timing semantics simulation of hardware descriptions logic simulation vlsi inertial delays descheduling anticipatory scheduling preemption of inconsistent events parallel processing distributed algorithms