Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator
In this paper, the bandwidth of the delta sigma modulator (DSM)-transmitter is improved using low complexity time-interleaved DSM. The high clock speed requirement of DSM is the main limitation to increase the signal bandwidth in DSM-transmitter. In this research, the bandwidth of DSM-transmitter is increased four times by using low complexity four-branch time-interleaved parallel DSM without the need for increasing clock speed. This low complexity parallel DSM is designed based on polyphase implementation technique. Then, the transmitter architecture is simulated using MATLAB simulink and Advanced Design System (ADS). For this simulation, the uplink long-term evolution (LTE) signal with different bandwidths of up to 7.68MHz is used. The simulation shows that by using four-branch time-interleaved parallel DSM in transmitter architecture for 7.68MHz LTE signal with oversampling ratio (OSR) of 16, the signal to noise and distortion ratio (SNDR) is about 41dB with the clock speed of only 30.72MHz. This is four times lower than the required clock speed of the conventional transmitter to achieve the same SNDR.
long-term evolution (lte) signal to noise and distortion ratio (sndr) delta sigma modulator (dsm) switching mode power amplifier (smpa) parallel processing