A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit
A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply.
end-around carry adder multiply-add fused floating-point