a simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays
Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple , is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic processes and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.
technology mapping map placement global routing algorithm fpgas network blocking layout informal account paper version recursion partition region process experimentation benchmark circuits demonstrate efficiency effect field-programmable-gate-array logic