the minimization of hardware size in reconfigurable embedded platforms
To minimize the hardware fabrications in reconfigurable devices, this paper explores hardware synthesis to derive reconfiguration plans during the design time based on schedules derived by CAD tools, where a schedule includes the starting time, the execution time, and the intertask data transmissions for each task. We propose scheduling algorithms to derive optimal solutions for hardware descriptions with the same reconfiguration latency based on backward configuration and backward ordering strategies. For general cases, where a hardware description might be shared by tasks, we develop an algorithm based on a duplication merging strategy with performance evaluations. Our proposed algorithms could be applied after the hardware/software co-design procedures of task partitioning and scheduling to optimize the hardware requirements during the design time.
scheduling fpga dynamically reconfiguration