A hardware architecture for real-time image compression using a searchless fractal image coding method
In this paper we present a novel hardware architecture for real-time image compression implementing a fast, searchless iterated function system (SIFS) fractal coding method. In the proposed method and corresponding hardware architecture, domain blocks are fixed to a spatially neighboring area of range blocks in a manner similar to that given by Furao and Hasegawa. A quadtree structure, covering from 3232 blocks down to 22 blocks, and even to single pixels, is used for partitioning. Coding of 22 blocks and single pixels is unique among current fractal coders. The hardware architecture contains units for domain construction, zig-zag transforms, range and domain mean computation, and a parallel domain-range match capable of concurrently generating a fractal code for all quadtree levels. With this efficient, parallel hardware architecture, the fractal encoding speed is improved dramatically. Additionally, attained compression performance remains comparable to traditional search-based and other searchless methods. Experimental results, with the proposed hardware architecture implemented on an Altera APEX20K FPGA, show that the fractal encoder can encode a 5125128 image in approximately 8.36ms operating at 32.05MHz. Therefore, this architecture is seen as a feasible solution to real-time fractal image compression.
real-time image compression searchless quadtree fractal image encoding