Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths
This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided. (C) 2009 Elsevier B.V. All rights reserved.
coarse-grain reconfigurable architectures canonical interconnection flexibility inlining carry-save arithmetic chain addition array multiplier