A VHDL--Forth Core for FPGAs
The Forth programming language is typically implemented to run on some particular microprocessor. Several Forth engines have been designed that execute Forth instructions directly, typically in a single clock cycle. With the advent of high density FPGAs it has become feasible to implement a high-performance Forth core in an FPGA. This paper describes the design of a Forth core using VHDL that has been implemented on a Xilinx Spartan II FPGA. Examples are presented of high-level Forth programs that are compiled to VHDL code that implements a ROM embedded in the FPGA. The use of a Forth core in an FPGA allows for rapid prototyping of digital systems. Experiments show that an identical Forth program for the Sieve of Eratosthenes executes nearly 30 times faster on the FPGA Forth core than on a 68HC12 microcontroller at the same clock speed. This same program executes over six times faster on the FPGA Forth core than an equivalent compiled C program run on the same 68HC12. The Forth core is available as an EDIF file at www.tigs.com/fc16, which can be included in a VHDL project and uses approximately 30% of a Spartan II FPGA.
vhdl forth core fpga rapid prototyping stack-based microprocessor