An improved algorithm for the net assignment problem
In this paper, we consider the net assignment problem in the logic emulation system. This problem is also known as the board-level-routing problem. There are held programmable logic arrays (FPGAs) and crossbars on an emulator board. Each FPGA is connected to each crossbar. Connection requests between FPGAs are called nets, and FPGAs are interconnected through crossbars. We are required to assign each net to the suitable crossbar. This problem is known to be NP-complete in general. A polynomial time algorithm is known for a certain restricted case, in which we treat only 2-terminal nets. In this paper we propose a new polynomial time algorithm for this case.
net assignment problem logic emulator edge coloring nearly equitable edge coloring