On the use of random limited-scan to improve at-speed random pattern testing of scan circuits
A method is proposed for improving the fault coverage that can be achieved by random patterns for circuits with scan. Under the test application scheme considered, primary input sequences are applied at-speed between scan operations. The proposed method uses limited scan operations to improve the fault coverage. Under a limited scan operation, the circuit state is shifted by a number of positions which may be smaller than the number of state variables. Limited scan operations are inserted randomly to ensure that the complete test set can be generated by a random pattern generator. Experimental results show that complete fault coverage is achieved by the proposed method, i.e., the proposed method detects all the detectable circuit faults, for all the benchmark circuits considered.
scan circuits at-speed test application built-in test generation random test generation