A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit
A fully bidirectional mixed-voltage input/output (I/O) buffer using a novel floating N-well circuit is presented. To provide appropriate gate voltages for output stage transistors, a dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon using 0.18 mu m CMOS process that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.
floating n-well mixed-voltage dynamic gate bias wide-range input/output (i/o) buffer