statistical timing analysis for intra-die process variations with spatial correlations
Process variations have become a critical issue in performanceverification of high-performance designs. We present a new, statisticaltiming analysis method that accounts for inter- and intra-dieprocess variations and their spatial correlations. Since statisticaltiming analysis has an exponential run time complexity, we proposea method whereby a statistical bound on the probability distributionfunction of the exact circuit delay is computed with linear run time.First, we develop a model for representing inter- and intra-die variationsand their spatial correlations. Using this model, we thenshow how gate delays and arrival times can be represented as a sumof components, such that the correlation information betweenarrival times and gate delays is preserved. We then show howarrival times are propagated and merged in the circuit to obtain anarrival time distribution that is an upper bound on the distributionof the exact circuit delay. We prove the correctness of the bound andalso show how the bound can be improved by propagating multiplearrival times. The proposed algorithms were implemented andtested on a set of benchmark circuits under several process variationscenarios. The results were compared with Monte Carlo simulationand show an accuracy of 3.32\% on average over all test cases.
statistics time analysis timing analysis process variation spatial correlation critic high-performance design analysis method method account time complexity probability distributed circuits delay model component informal correctness algorithm test benchmark monte carlo accuracy process -variation