an efficient method of fault simulation for digital circuits modeled from boolean gates and memories
The ability to predict the behavior of digital circuits containing faults is required for the verification and automatic generation of fault detection tests, and for the creation of fault dictionaries. The most common method of prediction is with a fault simulation program. Fault simulators simulate the fault-free (good) circuit and each of the possible faulty circuits. In most cases, the faulty circuit is assumed to contain only a single fault modeled as either a component input or output stuck-at-0 (SA0) or stuck-at-1 (SA1). Even so, a typical circuit may imply hundreds to thousands of possible faulty circuits. Reducing the cost of simulating large numbers of faulty circuits is the first major consideration in fault simulation.
efficiency method fault simulation digitize circuits memorialized predict behavior verification generation component input cost fault-detection