architecture and implementation of a vliw supercomputer
Very-Long-Instruction-Word (VLIW) computers achieve high performance by exploiting the fine-grain parallelism present in sequential or vectorizable code. Multiflow's /200 and /300 VLIW systems yielded near-supercomputer performance by this means despite the relatively slow (65 nS) clocks. With its much faster clock period (15 nS) and architectural improvements, the new /500 system attains approximately 4-9X the performance of its predecessors. This paper describes the /500 architecture and implementation, with special attention paid to the tradeoffs involved in designing very high speed VLIWs.
architecture implementation supercomputer computation performance parallel code systems clock paper attention instruction high-performance