High-level parameterizable area estimation modeling for ASIC designs
A simple yet accurate high-level area estimation method for ASIC designs is proposed. The method allows parameterizable area models to be created. The method can be applied very early in the design process and requires minimal information about the implementation technology. Application to several real world design examples is presented. The gate count estimate accuracies are mostly within 5% for real world cases.
gate-count estimation architecture exploration vlsi circuits integrated circuit modeling system-on-chip