On the relation between the throughput gain with slot reuse and the number of address bits in the dual bus configuration Part 2: Linear and equal throughputs
in slotted, dual bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, i > i, then the slot can be reused by a station k, k greater than or equal to j. In order to enable full slot reuse with one bit delay at the stations, addresses must contain M - 2 bits. We consider two schemes for throughput assignments which determine the number of station transmissions. In the linear scheme the throughput of a station i equals h - (M - 1) where h is a throughput factor. In the equal throughput scheme the throughput of every station is equal to some value C We compute the maximum possible values for h and C respectively, when addresses are M - 2 - y bits long, 0 5 y:5 M - 2 - [(M - 1)]. We find that for both schemes the address overhead can be reduced by more than 60% while keeping the size of h and C as in full slot reuse. Also, when there is a loss in h and C, it reaches about 25%. However, in these cases the overhead is reduced significantly, and sometimes more information bits, between 10-40%, are transmitted although the number of transmissions is smaller. Our algorithms for the computation of h and C as a function of y are pseudo-polynomial with complexity O(M-2).
slot reuse dual bus equal throughput destination release linear throughput