Delay Test with Embedded Test Pattern Generator
A new on-chip embedding mechanism to improve fault coverage in scan-based delay test is proposed. A major problem of scan-based delay test techniques is that they may not provide good fault coverage as many valid test pattern pairs cannot be launched. In the proposed method, the initialization vector is shifted into the scan chain, and then the activation vector is generated by selectively inverting some bits to be loaded into the scan chain. Therefore, this method provides a mechanism to modify activation vectors so that desired test pattern pairs can be launched. A formal design procedure for the embedded mechanism is presented. Experimental results show that, compared with previous work, the proposed method improves delay fault coverage with small area overhead.
delay test test pattern generator two pattern test bist on-line testing