hw/sw partitioning and code generation of embedded control applications on a reconfigurable architecture platform
This paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. The hw/sw codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an intermediate model of computation (Extended Finite State Machines) and derives both hardware and software, based on performance constraints. We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance. A new mapping flow and algorithms to partition hardware and software are proposed to generate implementations that best utilize this architecture. Encouraging preliminary results are shown for automotive electronic control examples.
partition code generation general embedding control applications reconfigurable architecture reconfigurability architecture platform paper use timing performance codesign methodology model of computation state machine hardware software constraint processor core functional map flow algorithm implementation automotive examples hw/sw co-design csoc real-time data