interpolation-based incremental eco synthesis for multi-error logic rectification
To cope with last-minute design bugs and specification changes, engineering change order (ECO) is usually performed toward the end of the design process. This paper proposes an automatic ECO synthesis algorithm by interpolation. In particular, we tackle the problem by a series of partial rectifications. At each step, partial rectification can reduce the functional difference between an old implementation and a new specification. Our algorithm is especially effective for multiple error circuits. Experimental results show the proposed method is far superior to the most recent work and scales well on a set of large circuits.
interpolation logic rectification engineering change order satisfiability