stochastic interconnect layout sensitivity model
Semiconductor manufacturing yield is determined by the defect density and critical area i.e. that portion of the layout in which the occurrence of a defect results in yield loss. In this paper, we define layout sensitivity as the ratio of critical area to the layout area. Utilizing the basic probability theory, a rigorous derivation of layout sensitivity for random logic network is performed. This model is compared to actual critical area distributions for a modern microprocessor design. A methodology to calculate the layout sensitivity pattern for a complex layout is proposed.
layout sensitivity yield defect density critical area analysis stochastic model design for manufacturability reliability