vectorizing for a simdd dsp architecture
The Single Instruction Multiple Data (SIMD) model for finegrained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demonstrate how SIMdD (SIMD on disjoint data) supports e#ective vectorization of digital signal processing (DSP) benchmarks, by facilitating data reorganization and reuse. In particular we show that this model can be adopted by a compiler to achieve nearoptimal performance for important classes of kernels.
vectorization simd architecture instruction data model parallel support operability paper demonstrate digital signal processing benchmark reuse compilation performance class kernel viterbi data reuse compiler controlled cache rotating register file subword parallelism