A fault-tolerant message passing algorithm and its hardware implementation
A message passing algorithm for processor arrays that can tolerate any number of faulty blocks, which form any shape, is presented. Each message is delivered to its destination, provided that the destination processor is not surrounded by faults. In this case the message is returned to its source processor. Only local knowledge of faults is demanded. The hardware implementation of this algorithm leads to a message passing coprocessor which is allocated at each processor of the array. No need for high silicon overhead is required for the implementation of the message passing coprocessor. This coprocessor executes only the fault tolerant message passing algorithm presented here. The usage of the proposed coprocessor improves the general processing efficiency, as well as, the performance reliability under faulty conditions.
fault-tolerant message passing hardware implementation processor arrays