A framework for run-time reconfigurable systems
We present a framework for run-time reconfigurable systems. The framework provides a methodology and a design representation which allow to plug in different design and implementation tools. Front-end tools cover design capture, temporal partitioning and scheduling; back-end tools provide reconfiguration control, communication channel generation, estimation, and the final code composition. This paper elaborates on two of the framework's main issues: First, we discuss the design representation comprising aspects of the problem, the target architecture, and the communication channels. Second, we present a hierarchical approach to reconfiguration control in multi-FPGA systems.
run-time reconfiguration design representation multi-fpga systems