A 485ps 64-bit parallel adder in 0.18 mu m CMOS
This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18 mu m CMOS process. It achieves the goal of higher speed and lower power.
sparse-tree semi-dynamic parallel prefix adder