An area and power optimization technique for CMOS bandgap voltage references
This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in the technology and also the area of bipolar transistors. The proposed technique does not depend on a special process and can be applied for designing bandgap reference circuits with different topologies.
optimization bandgap voltage reference cmos analog integrated circuit