Design and analysis of heterogeneous nanoscale on-chip communication networks
With a continuing downscaling of the physical feature sizes, an increase in complexity and the number of on-chip devices, and an increase in their heterogeneity, the traditional on-chip communication infrastructure needs to be revisited. It has previously been shown that multi-hop communication suffers from high latency and power consumption and that networks with long-range, high-bandwidth, and low power communication links significantly improve the system performance. Yet, it is an open problem what level of heterogeneity and what link type characteristics represent an optimum for on-chip communication networks. In this paper we design and analyze optimal heterogeneous networks by considering different cost and performance trade-offs in a technology-agnostic framework. We show that there is an optimal number of different link types for each set of constraints and that the heterogeneous network performance allows for a higher throughput at a lower cost compared to 2D regular mesh and homogeneous networks. From our results it follows that the link types available with current technology are non-optimal in a heterogeneous setup. We show that the main results are robust against certain model assumptions. In addition, the proposed heterogeneous networks scale up significantly better in terms of both cost and performance. The results are relevant for the design of emerging nanoscale communication fabrics and will help to drive the development of new technology.
heterogeneous networks-on-chip noc