Majority Logic Mapping for Soft Error Dependability
This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. A new type of voter circuit, that uses some knowledge from the analog design arena is proposed, together with a new mapping approach to implement circuits given their input/output table. This new mapping approach is shown to compare favorably against a classic mapping. The implementation and validation of an adder circuit, using conventional triple modular redundancy (TMR), the classic mapping, and the proposed solution are analyzed, in order to confirm that the shown technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR. Finally, implementations of a subset of the ISCAS 85 benchmark circuits using TMR with the analog voter and the proposed approach are compared and the results analyzed.
majority logic majority gates fault tolerance set