Modeling and evaluation of ring-based interconnects for Network-on-Chip
A popular network topology for Network-on-Chip (NoC) implementations is the two-dimensional mesh, which has its drawbacks in the communication latency scalability, and the concentration of the traffic in the center of the mesh. In this paper, we consider the addition of simple and hierarchical rings to the mesh network. We propose several composite topologies that use the ring networks to reduce hop counts and latencies of global (long distance) traffic. Furthermore, we study two alternative ring architectures. The first is a slotted ring architecture that is suitable for NoC implementation due to its simplicity and low cost. The second uses wormhole routing and virtual channels, providing increased flexibility and better performance. Simulation results show that the composite architectures decrease the latencies and hop counts incurred by global traffic, thereby validating our claim that the use of hierarchical rings for global routing can in fact increase the scalability of the normal mesh network used for NoC implementations.
modeling network-on-chip mesh hierarchical ring interconnect topologies systemc