Power-speed trade-off in parallel prefix circuits
Optimizing area and speed in parallel prefix circuits has been considered important for a long time. The issue of power consumption in these circuits, however, has not been addressed. This paper presents a comparative study of different parallel prefix circuits from the point of view of power-speed trade-off. An effective circuit capacitance model that is verified through PSpice simulations is used to investigate the power consumption in parallel prefix circuits. The model results in an analytical function for power consumption for each prefix circuit considered. The degrees of freedom studied include different parallel prefix circuits and voltage scaling. The results of the study were applied to evaluate power-speed trade-offs when different prefix circuits axe used in Brent's parallel adder(5).
power-speed trade-off prefix circuits parallel adder