Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes
We propose a polynomial-time optimal algorithm for allocating a minimum number of Adjustable Delay Buffers (ADBs) in clock tree to resolve the clock skew violation in multiple power mode designs. We solve the ADB allocation problem in both of the use of ADBs with continuous delay increments and ADBs with discrete delay increments. We provide complete proofs of the optimality of the proposed algorithm. We propose a systematic exploration of the combined utilization of ADBs and buffer sizing to further optimize the multiple power mode designs with clock skew constraint.
timing power modes adjustable delay buffers clock skew resource allocation design optimization