an integrated debugging environment for fpga computing platforms
Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. This poster describes our solution to this problem, in which the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment are translated into logic inserted automatically into the hardware implementation. Variables provide full read/write access to hardware signals during runtime, complete with dynamic assertion checking capable of automatically halting the system clock. System data is consistently cached via attached DRAM, providing a very deep history of variable sample values and the ability to "rewind" system state. Process execution can also be controlled by the user on a cycle-by-cycle basis, either manually or through the declaration of breakpoints. Assertion failures and breakpoints are accurate within the same cycle of detection, and are implemented using on-chip gated clock buffers. All debugging controls are provided by a remote graphical user interface, which also supports back-annotation in the input design for improved data visibility and comprehension. The complete hardware and software infrastructure of the debugger has already been fully implemented, with user trials and overhead measurements ongoing at the time of writing
fpga design simulation verification