FPGA and ASIC implementations of the eta(T) pairing in characteristic three
Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient implementations of pairing primitives, the study of hardware accelerators has become an active research area. In this paper, we propose two coprocessors for the reduced eta(T) pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We eventually present the first ASIC implementation of the reduced eta(T) pairing. (C) 2009 Elsevier Ltd. All rights reserved.
eta(t) pairing hardware accelerator tate pairing elliptic curve cryptography finite held arithmetic