Diminished-one modulo 2(n)+1 adder design
This paper presents two new design methodologies for modulo 2(n) + 1 addition in the diminished-one number system. The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. VLSI realizations of the proposed circuits in a standard-cell technology are utilized for quantitative comparisons against the existing solutions. Our results indicate that the proposed carry look-ahead adders are area and time efficient for small values of n, while for the rest values of n the proposed parallel-prefix adders are considerably faster than any other already known in the open literature.
parallel-prefix adders modulo 2(n)+1 addition carry look-ahead addition diminished-one number representation vlsi adders