Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design
High level synthesis has now almost become an industry de facto standard for designing Application Specific Processors (ASPs) and Application Specific Integrated Circuits (ASICs). High level synthesis (HLS) designing requires an efficient exploration approach with the ability to determine optimal/near-optimal scheduling solutions and module selection with significant speed and precision. A novel exploration approach using the S-value method that reduces the final power dissipation of the solution using minimal control step is presented in this paper. This approach is based on the proposed Primacy Selector (S-value) metric and Intersect Matrix topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Two novel aspects discussed in this paper are: (a) introduction of Intersect Matrix topology with its associated algorithm, which is used to check for precedence violation during scheduling, (b) introduction of S-value method metric, which assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach is done with an existing design space exploration method for qualitative assessment using proposed Quality Cost Factor (Q-metric). An average improvement of approximately 5.07% in quality of final scheduling solution and average reduction of 59% in exploration runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.
application specific processor s-value intersect matrix integrated exploration q-metric