Hardware implementation of DIRLS mismatched compressor applied to a pulse-Doppler radar system
In this work, the hardware implementation of a digital mismatched pulse compressor and its application to a pulse-Doppler radar system are presented. The emphasis is to use one generalized compressor with reloading coefficient capability for several different types of signals. This implementation starts with a generic VHDL specification and then it is developed on FPGA architecture. The compression filter implementation on FPGA lets us eliminate special chips previously needed. The achieved design can be adapted to different computational requirements, easily modifying its data path and the length of the used signal sequence. From the experimental results it is known that this approach appears to work well for chirp and discrete phase matched/mismatched pulse compression and it outstands when TB is of order 1000. Also, it fits for arbitrary spread spectrum waveforms. The design performances have been analyzed modifying the used precision and the length of the used signal sequences.
fpga sidelobes suppression pulse compression system