An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs
During the power mode transition, simultaneously turning ON sleep transistors provides a sufficiently large surge current, which may cause a large IR drop in the power networks. The IR drop in turn causes errors in the retention sequential elements of the sleep modules or errors of the nonsleep modules. One efficient way to control the surge current is to schedule the turn-ON sequences of sleep transistors. In this paper, we introduce several important properties of the surge current during the power mode transition for the distributed sleep transistor network (DSTN) design, which is a popular power gating design style. Based on these properties, we propose an accurate estimation of the surge current and provide efficient schedules on the DSTN structure. Our methods achieved significantly better results than previous works-on average, 261 times wake-up time reduction and 30% less energy loss during the power mode transition.
power gating power mode transition schedule leakage low power multithreshold cmos (mtcmos)