An Analog VLSI Architecture for High Speed, Low Power Object Tracking
Using a two-dimension array of MOSFET switches, a robust, high speed object tracking CMOS sensor is presented. The edges of the image scene are extracted by the in-pixel differential comparators and a region (object) of interest, which is selected by the user, is segmented using the switch network. Tracking is performed by automatic reselection of the desired region. The proposed design presents less sensitivity to threshold adjustments compared to the binarization technique. The processing is mainly performed in analog domain, thus reducing dynamic power dissipation and making the chip ideal for low power applications. The sensor has been designed as a 50 x 50 pixel VLSI CMOS chip in the 0.6 mm technology. Features such as power dissipation, output latency, and operating frequency are reported.
low power object tracking segmentation switch network cmos image sensor