A VLSI array architecture for Hough transform
In this article, an asynchronous array architecture for straight line Hough transform (HT) is proposed using a scaling-free modified Co-Ordinate Rotation Digital Computer (CORDIC) unit as a basic processing element (PE). It exhibits four-fold angle parallelism by dividing the Hough space into four subspaces to reduce the computation burden to 25% of the conventional requirements. A distributed accumulator arrangement scheme is adopted to ensure conflict free voting operation. The architecture is then extended to compute circular and elliptic HT given their centers and orientations. Compared to some other existing architectures, this one exhibits higher computation speed. Society. Published by
hough transform cordic low power image processing multiplierless array architecture