Area-optimal technology mapping for field-programmable gate arrays based on lookup tables
We present an exact solution to the technology mapping problem for field-programmable gate arrays (FPGAs), where the objective is to minimize the number of lookup tables (LUTs) required to map a logic circuit. The key idea is to compactly formulate the mapping problem as a mixed-integer linear-programming (MILP) problem, which can then be solved by any off-the-shelf MILP solver. MILP problem formulations are systematically developed for various classes of circuits with increasing complexities-trees, monotone circuits, and general nonmonotone circuits, where the monotonicity of a circuit implies that the number of signals increases monotonically as the circuit is traversed from primary outputs to primary inputs. Several circuit properties related to reconvergent paths and monotone signal sets are determined, which provide insight into the mapping problem for LUTs. Our experiments show that optimal mappings for circuits with several hundred gates can be obtained very quickly by solving their MILP formulations exactly. For larger circuits, we present two powerful heuristic approximation methods based on partitioning the circuit or simplifying its structure. We show that these approximations yield near-optimal solutions for several benchmark circuits.
field-programmable gate arrays (fpgas) circuit synthesis design automation integer programming logic partitioning table lookup