a geometric programming aided knowledge based approach for analog circuit synthesis and sizing
A knowledge based approach empowered by geometric programming (GP) for analog circuit synthesis and sizing is presented. Analog circuit performance specification is mapped to various building blocks of a circuit topology. Thereafter the topology is modified according to the design rules in the library. Each modification is validated over two steps. In the first step, dc performances constraints are introduced. If qualified, ac performance constraints are introduced. Validation over two steps helps to gradually close in on input specifications removing any undesired correction made initially, resulting in faster convergence.
geometric programming knowledge synthesis topology