a path selection algorithm for timing analysis
Due to the rapid progress in semiconductor technology, the number of gates that can be placed in a chip increases dramatically. Existing algorithms for timing analysis have difficulties when dealing with large designs. A new algorithm for timing analysis is proposed in this paper. This algorithm enumerates all the paths with delay greater than a given threshold. The execution time of the proposed algorithm is proportional to the number of paths generated. Therefore, it is suitable for large designs. Classification : timing verification.
select algorithm time analysis timing technologies design paper delay threshold verification