Improving the Delay of Residue-to-Binary Converter for a Four-Moduli Set
The residue number system (RNS) is an unconventional number system which can be used to achieve high-performance hardware implementations of specialpurpose computation systems such as digital signal processors. The moduli set {2(n)-1, 2(n), 2(n)+1, 2(2n+1)-1} has been recently suggested for RNS to provide large dynamic range with low-complexity, and enhancing the speed of internal RNS arithmetic circuits. But, the residue-to-binary converter of this moduli set relies on high conversion delay. In this paper, a new residue-to-binary converter for the moduli set {2(n)-1, 2(n), 2(n)+1, 2(2n+1)-1} using an adder-based implementation of new Chinese remainder theorem-1 (CRT-I) is presented. The proposed converter is considerably faster than the original residue-to-binary converter of the moduli set {2(n)-1, 2(n), 2(n)+1, 2(2n+1)-1}; resulting in decreasing the total delay of the RNS system.
residue-to-binary converter residue number system (rns) digital circuits computer architecture high-speed computer arithmetic