Design and analysis of enhanced Abacus switch
Combined input-output buffering with a moderate speedup for internal switch fabric has been considered as the most feasible solution to build large-capacity packet switches. This paper describes several schemes to further scale up our previously proposed Abacus switch [IEEE J. Select. Areas Commun. 15 (1997) 830] to multiple terabit per second. The Abacus switch implements the arbiter in a distributed manner, allowing the switch to be scaled in both the port speed and the switch capacity. The switch can be easily implemented using crosspoint switch chips with self-routing capability. The enhanced version can also route variable-length packets without doing packet reassembly at the output. (C) 2002 Elsevier Science B.V. All rights reserved.
terabit switching switch architecture arbitration input buffered switch