Critical evaluation of hard-breakdown based reliability methodologies for ultrathin gate oxides
Reliability methodologies based on the tolerance of CMOS devices and circuits to breakdown events are examined. It is shown that the prevalence ratio model (devices tolerate soft breakdown and fail with hard breakdown) and the successive breakdown description of the statistics are consistent with one another. The definition of breakdown of ultra-thin oxides and possible problems for the experimental measure of the hard breakdown prevalence ratio are discussed. Finally, it is shown that hard breakdown occurs in ultra-thin oxides under stress voltages much lower than previously anticipated.
mos devices dielectric breakdown gate oxide reliability