Efficient Modulo 2(n)+1 Multipliers
Area-time efficient modulo (2(n) + 1) multipliers are proposed. The result and one operand for the new modulo multipliers use weighted representation, while the other uses the diminished-1. By using the radix-4 Booth recoding, the new multipliers reduce the number of the partial products to n/2 for even and (n + 1)/2 for n odd except for one correction term. Although one correction term is used, the circuit is very simple. The architecture for the new multipliers consists of an inverted end-around-carry carry save adder tree and one diminished-1 adder. The new multipliers receive full inputs and avoid (n + 1)-bit circuits. The analytical and experimental results indicate that the new multipliers offer enhanced operation speed and more compact area among all the efficient existing solutions.
diminished-1 representation modular arithmetic modular multiplier