1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation
This paper presents a 1080p 60 Hz intra-frame CODEC system for zero delay AV streaming. For high quality streaming, the proposed CODEC employs an RGB-domain inter-color compensation algorithm using strong correlation between RGB color components which was previously presented by the authors of this paper. The proposed CODEC architecture is based on macroblock-level pipelining and parallel processing to handle a significant pixel rate of 1080p 60 Hz videos with RGB 4:4:4 format, i.e., 3 Gbps. Since syntax processing is a bottleneck to supporting speeds of up to 100 Mbps in real-time, a high performance context-adaptive variable length coding architecture exploiting the look-ahead technique is included in the proposed design. Also, the number of syntax symbols is adaptively restricted to accomplish zero end-to-end delay. Finally, by using MPEG-2 TS as the AV stream format, compatibility with general channel chips is guaranteed. Using TSMC 90 nm CMOS technology, the prototype chip is implemented with 1,208 K logic gates and 359 Kb internal SRAM. The chip can achieve real-time encoding and decoding of 1080p 60 Hz videos at 200 MHz execution speed in typical work conditions.
1080p zero delay rgb ts intra-frame coding full high definition