Evolution of a CMOS Based Lateral High Voltage Technology Concept
This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35?m LV CMOS technology (C35) which is optimized for digital and analog applications. The technology covers two different gate oxide thicknesses which allow to control two LV logic levels with different gate voltages and drain voltages (max.VGS=max.VDS=3.3V, max.VGS=max.VDS=5.5V). The key requirement for the HV integration is to preserve the LV design rules (DR) and the LV transistor parameters. Only in this case it is possible to reuse the digital and analog intellectual property (IP) blocks. The major challenge of this integration is to overcome the relatively high surface concentration of the 0.35?m CMOS process which defines the threshold voltages and the short channel effects. Because the HV devices use the same channel formation like the LV devices, a process concept for the drift region connection to the channel is the key point in this integration approach. A benchmark for the process complexity is given by the mask count (low volume production) and the number of alignments (high volume production). Starting from a very simple approach n-channel HV transistors are described which can be integrated in the substrate related LV CMOS concept without adding additional masks. During the next steps the LV CMOS process is modified continuously using additional masks and alignment steps. From each step to step the new HV properties are explained and the trade-off between process complexity and device performance is discussed.
high voltage ics process integration ldmos 0.35 cmos adaptive resurf