Identification of Critical Executable Paths at the Architectural Level
A framework to identify critical executable paths in an acyclic syntbesizable very-high-speed integrated circuits hardware description language or software code is presented. It can be used effectively in a variety of problems that include compiler-level architectural optimization for improved performance and static software timing analysis. The approach is path implicit and scalable. The set of executable paths is stored implicitly using zero-suppressed binary decision diagrams. Functions that represent condition statements at the basic blocks are manipulated using binary decision diagrams. Postprocessing algorithms on the canonical data structures identify critical paths and other useful metrics such as a most frequently used critical path. Experimental results demonstrate the scalability of the proposed method.
timing analysis binary decision diagram (bdd) timing optimization worst-case execution time (wcet)