Designing fast on-chip interconnects for deep submicrometer technologies
This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a10-mm long interconnect in a 0.12-mum CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.
on-chip interconnect deep submicrometer technology wire delay simultaneous redundant switching shielding spacing capacitive coupling critical wire redundant wire