A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter
High-performance pipeline architecture for the H.264/AVC deblocking filter. High-throughput ASIC and FPGA implementations. High-speed and low-area circuit implementation of the deblocking filter. Support of the H.264/AVC high profiles. Overlapped computations and efficient distribution of them at the pipeline stages.
pipeline deblocking filter asic fpga h.264avc video compression