Systolic productsum circuit for GF((22)m) GF ( ( 2 2 ) m ) using neuron MOSFETs
A quaternary systolic product-sum computation circuit for GF((22)m) GF ( ( 2 2 ) m ) using voltage-mode v MOSFETs is presented. The design is composed of four basic cells connected in a pipelined fashion. Each basic cell is composed of 2 Galois field adders, 2 Galois field multipliers, and 7 flip-flops. The circuit was simulated using Affirma Analog Circuit Design Environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((22)2) GF ( ( 2 2 ) 2 ) shows a significant amount of savings in both transistor count and number of connections compared to the one that uses the binary field GF(24) GF ( 2 4 ) .
neuron mosfet composite and binary galois fields mvl quaternary logic