SAFETY CORE APPROACH FOR THE SYSTEM WITH HIGH DEMANDS FOR A SAFETY AND RELIABILITY DESIGN IN A PARTIALLY DYNAMICALLY RECON-FIGURABLE FIELD-PROGRAMMABLE GATE ARRAY (FPGA)
This paper deals with a new approach to designing the micro-electronic system suitable for mass-parallel and neuronal structures realizations in which the high demand on safety and reliability is given. The presented concept is based on the FPGA platform. Authors point out various kinds of faults which can possibly occur during system cycle. Furthermore, authors introduce the Safety Core principle and define systems for which it is applicable. There are possibilities of using partial dynamic reconfiguration shown in this paper in the context of FPGA fabric testing, faults catching and correcting.
safety core safety reliability fpga partial dynamic reconfiguration mass-parallel computing neural networks virtex-4