software power estimation using ipi(inter-prefetch interval) power model for advanced off-the-shelf processor
This paper addresses a problem of modeling the power consumption of advanced off-the-shelf processors. Unlike existing methods for processor power estimation, where the internal information of processor architecture such as activation of specfic modules such as pipeline stages, etc.) is available via simulation or runtime counters, power modeling method presented in this paper is to estimate the power consumption of complex off-the-shelf RISC processor without such a detailed information, only based on the information of the processor I/O signals (i.e memory access). To tackle this problem, we propose a new power model, called IPI(Instruction-Prefetch Interval) power model. The IPI represents the time interval between two consecutive instruction prefetchs. Our model has two major advantages. First, this model can consider prefetch mechanism. Most of advanced RISC processors have prefetch mechanism which makes processor power estimation difficult. IPI model is the first approach to model prefetch mechanism in processor power estimation. Second, this model can provide power variation in time and therefore it overcomes the limitation of previous work, such as instruction-level energy model. Experiments show that the proposed model yields 96\% accuracy on theaverage in case of ARM1136JF-S test chip.
software power estimation black-box power model prefetch power model processor power modeling ipi power model