Impact of dummies on interconnects network HF propagation performances for the 65nm node
Based on electromagnetic approach, electrical models of coupled interconnects surrounded by dummies are extracted, and a simulation procedure in time domain is performed to obtain signal propagation along interconnects representative of the 65nm CMOS node. This technique is used to quantify effects of size and placement of dummies on parasitic effects such as delay and crosstalk and an optimization of their sizes is proposed.
dummies interconnect performance integrated circuits cmos 65nm node