viability of analog inner product operations in cmos imagers
A new model for the sensitivity analysis of inner products to CMOS analog hardware implementation is proposed. It is derived from Spice simulations of the circuits to be implemented, and is required for the design of analog image compression systems based on vector quantization at the focal plane of CMOS imaging sensors. The model is shown to be equivalent to a simpler, previously introduced model, if the errors caused by the fabrication process are around 6\%. For 1.5\% errors, the results differ from the theoretical predictions made by the previous model. Image compression results and the layout of the fabricated circuit, currently under test, are presented.
cmos analog hardware vector quantization analog image processing