thinking outside of the chip
Before a chip ships in volume, PCB design is often a bottleneck. The PCB is a significant cost element of the final product, which drives major time and effort spent on cost reduction. To achieve these savings, the PCB designer must minimize the number of layers while achieving optimal signal and power performance; no easy task given the density of IC pins and the literal "rats nest" of connections. The problem is that the IC designer may not consider the PCB placement and breakout patterns and channels resulting in longer design cycles and too many layers. Awareness of the PCB would enable the IC designer to optimize chip I/O & block level planning, and the package designer to optimize the PCB interface represented by the package's pin-out. At the same time, they can leverage industry standard interfaces such as DDRx and PCIe and their corresponding design constraints. The result would be a "PCB aware" IC that results in fewer PCB layers designed in less time. This paper will outline the requirements for a design environment that promotes IC, package and PCB cross team collaboration allowing bi-directional data exchange between the different design teams. Given the IC focus of ISPD, we hope to get the IC community thinking "outside of the chip", to provide insights into package and PCB design challenges and to identify areas where collaboration and further research is needed.
chip pcb ic package collaboration co-design