Optimizing RapidIO Architectures for Onboard Processing
In this article, we study optimization of a RapidIO network and FPGA-based computation engines to address the taxing requirements of a set of real-time Ground-Moving Target Indicators (GMTI) and Synthetic Aperture Radar (SAR) kernels for Space-Based Radar (SBR). By employing a RapidIO hardware testbed and validated simulation, we determine key trade-offs in design of reconfigurable systems for GMTI and SAR in terms of processing, memory, and network throughput. In addition, we study considerations for timely delivery of latency-sensitive control traffic present in many satellite applications. Based on our results, we propose architectural modifications to further improve performance of SBR systems.
rapidio gmti radar sar design performance algorithms fpga space