Power supply design parameters for switching-noise control in deep-submicron circuits design flows
In high performance integrated circuits phenomena like crosstalk, IR drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their effects are assuming increasing impact compromising circuits functionality and not only their performances. This paper suggests a methodology to evaluate and to prevent power supply noise generation in more and more increasing dimensions circuit blocks. The power supply busses modeling is addressed to find out actual parameters to face early in the design phase noise phenomena related to power distribution. In particular using the equations reported in this paper the designer has the possibility to control the global power bus noise generation depending on the design strategy used, on the library characteristics and on the given performance constraints. The appropriateness of the developed methodology seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a target noise reduction besides delay and power optimization.
noise integrated circuits cmos interconnections signal integrity