A methodology to analyze the performance of a parallel frame synchronization scheme in SDH high speed networks
In this article, we first summarize our novel parallel frame synchronization system scheme designed for 155.520 Mbps high speed networks or higher. By using the parallel approach, we are able to process in synchronous digital hierarchy (SDH) systems at a rate of 19.44 MHz. This means that all functions contained in STM-N frame, such as descramble, section overhead monitoring, pointer processing, payloads demultiplexing, etc. are operated on at byte rate after the framer. All of these functions must he done on a byte wide basis. Thus, all operations are performed in parallel in an SDH processor. We analyze the performance of the scheme using false synchronous probability P-FS, the average synchronous incoming time T-ASI, the average synchronous catching time T-ASC and the average synchronization holding time T-ASH. Analysis indicates that the performance of our scheme is similar to that of the traditional approaches, or better under some condition. Further, our scheme permits designers to use off-the-shelf integrated circuits to build SDH synchronization system. (C) 1999 Elsevier Science B.V. All rights reserved.
parallel frame synchronization average synchronous incoming time average synchronous catching time average synchronization holding time sdh networks