Design and performance of 155 Mbps clock/data recovery circuits on heavy loaded PLDs
This paper discusses the design and performance of all-digital clock and data recovery mechanisms integrated in low-cost PLDs. Two designs have been explored and analyzed, using data sampling systems with phase detection and decision logic to select either the most appropriate sample as the recovered data or the most appropriate phase as the recovered clock. These mechanisms have been implemented in low cost PLDs from two major manufacturers. These PLDs have been further heavily loaded with typical communications functions, and the performance of the clock/data recovery circuits has been analyzed. The results show that different architectures behave differently, and that internal noise can significantly impair the performance of the circuit for high operating frequencies. This poses large difficulties to the re-usage of these blocks as generic virtual components. Nevertheless their overall performance typically exceeds regular telecommunications requirements.
plds clock and data recovery synchronization oversampling clock recovery