improved heuristics for finite word-length polynomial datapath optimization
Conventional high-level synthesis techniques are not able to manipulate polynomial expressions efficiently due to the lack of suitable optimization techniques for redundancy elimination over Z 2 n . This paper, in comparison with [1], presents 1) an improved partitioning heuristic based on single-variable monomials instead of checking all sub-polynomials, 2) an improved compensation heuristic which is able to compensate monomials as well as coefficients, and 3) a combined area-delay-optimized factorization approach to extract the most frequently used sub-expressions from multi-output polynomials over Z 2 n . Experimental results have shown an average saving of 32\% and 27.2\% in the number of logic gates and critical path delay respectively compared to the state-of-the-art techniques. Regarding the comparison with [1], the number of gates and delay are improved by 14.3\% and 13.9\% respectively. Furthermore, the results show that the combined area-delay optimization can reduce the average delay by 26.4\%.
high-level synthesis modular optimization