Scalable and efficient implementations of the LDPC decoder using reconfigurable models
In this paper we propose constant-time parallel algorithms for implementing the message-passing decoder of LDPC codes on a two dimensional R-Mesh and an LARPBS. The R-Mesh and LARPBS are dynamically reconfigurable models that provide hardware reuse and flexibility to problem changes. The same hardware can implement the decoder in both probability and logarithm domains over different channels. Moreover, to decode an alternate code, we may simply set up the required connections between the bit-nodes and check-nodes by modifying the initialization phase of the proposed algorithms. No extra wiring or hardware changes are required, as compared to other existing approaches. We illustrate that the R-Mesh and the LARPBS are efficient models for parallel implementation of the decoder in terms of time complexity, flexibility to problem changes and simplicity of routing messages. We also demonstrate that it is possible to optimally scale large block code sizes down to a smaller, available machine size if using an LR-Mesh or HVR-Mesh, two variants of the R-Mesh model.
ldpc decoder reconfigurable models r-mesh larpbs