on testability of checkable digital circuits under pseudorandom signals
Summary form only given. Checkable digital circuits synthesis method and algorithm are proposed. The essence of the method is in the insertion of probability converters into predetermined nodes of the original circuit. The converters are based on XOR-elements, whose one input is connected to the equal probability sequences' source.
testability checkable digital circuits digital circuits pseudorandom signals synthesis method algorithm probability converters probability design for testability logic testing xor-elements logic design circuit testing