Versatile motion estimation processor with scalability and high throughput
A high-performance versatile motion estimation processor with regular hardware and control structure capable of MP@HL is presented. It can compute 1920 X 1080 pels in 4096 cycles within search point range 64 with eight identical processors. The presented processor has 100% hardware utilization by eliminating the computation delay between stages, and the capability to compute half pel precision motion estimation. Also, by enhancing image data reuse, the I/O bottleneck problem is alleviated. With efficient scalability, the amount of hardware and computation speed can be easily adjusted for a variety of application areas. The proposed edge effect hardware can be used for object-based coding for MPEG-4. The processor was verified with C++ and VHDL based on actual image data and implemented with 0.6 mu m gate array. Also, a motion estimator system with image memories and PC host interface was designed.
motion estimation half pel data reuse mpeg hierarchical search block matching