Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process
130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.
yield improvement back-end-of-line process integration copper interconnects low-k dielectrics failure analysis