A SET/MOS Hybrid Multiplier Using Frequency Synthesis
This paper proposes a frequency synthesizer using single-electron transistor (SET)/MOS hybrid architectures for binary multiplier design. The main idea is to first convert the operands from their digital representation to frequency representation, and then perform multiplication in the frequency domain before converting the result back to the digital representation. The major merits of the proposed method include: 1) simplified implementation of binary multiplication and 2) high immunity against the background charges inherent in SET islands. Both circuit design and simulation are provided to show the effectiveness of the approach.
multiplier frequency synthesis set/mos hybrid architecture single-electron transistor (set)