estimation of the likelihood of capacitive coupling noise
The corruption of signals due to capacitive and inductive coupling of interconnects has become a significant problem in the design of deep submicron circuits (DSM). Noise simulators, based on worst-case assumptions, are overly pessimistic. As a result, when they are used on industrial ICs with hundreds of thousands of nets, thousands of nets are reported as having potential noise violations. There is a need to prioritize the problem nets based on the likelihood of the noise and possibly even eliminate them from further consideration if the likelihood is negligable . In this paper, a probabilistic approach is described which allows for a quantitative means to prioritize nets based on the likelihood of the reported noise violation. We derive upper bounds on the probability that the total noise injected on a given victim net by a specific set of aggressors exceeds a threshold. This bound is then used to determine a lower bound on the expected number of clock cycles (ENC) before the first violation occurs on a given net. Nets can be prioritized based on the ENC. We demonstrate the utility of this approach through experiments carried out on a large industrial processor design using a state-of-the-art industrial noise analysis tool. A significant and interesting result of this work is that a substantial portion (25\%) of the nets were found to have an ENC of more than five years. If five years is deemed to be sufficiently long time, then these could be eliminated from further consideration.
noise deep submicron signal integrity