fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework ( e.g. , simulation of the complete system), or are not accurate enough to drive the design of the communication architecture ( e.g. , techniques that perform a static analysis of the system performance). The proposed system-level performance analysis technique consists of (i) initial co-simulation performed after IIW/SW partitioning and mapping, with the communication between components modeled in an abstract manner ( e.g. , as events or data transfers), (ii) extraction of abstracted symbolic traces, represented as a Bus and Synchronization Event (BSE) Graph, that captures the activity of the various system components and their communication over time, and (iii) manipulation of the BSE Graph using the bus parameters, to derive the behavior of the system accounting for effects of the bus architecture. We present experimental results on several example systems, including a TCP/IP network interface card sub-system. The results indicate that our performance estimation technique is over two orders of magnitude faster than performing a complete system simulation, while being very accurate (within 2.2\% of performance estimates derived from accurate HW/SW co-simulation).
performance performance analysis analysis systems communication architecture paper efficiency drive exploration design use iter architectural design simulation completeness partition map component abstraction event data extraction traces synchronization graph activation timing manipulation behavior account effect experimentation examples network interfaces performance estimates  framework  system on-chip