a model to exploit power-performance efficiency in superscalar processors via structure resizing
Power consumption has become a major cause of concern spanning from data centers to handheld devices. Traditionally, improvement in power-performance efficiency of a modern superscalar processor came from technology scaling. However, that is no longer the case. Many of the current systems deploy coarse grain voltage and/or frequency scaling for power management. These techniques are attractive, but limited due to their granularity of control and effectiveness in nano-CMOS technologies. This paper proposes a novel architecture-level mechanism to exploit intra thread variations for power-performance efficiency in modern superscalar processors. This class of processors implements several buffering/queuing structures to support speculative out-of-order execution for performance enhancement. Applications may not need full capabilities of such structures at all times. A mechanism that collaboratively adapts a finite set of key hardware structures to the changing program behavior can allow the processor to operate with heterogeneous power-performance capabilities. We present a novel offline regression based empirical model to estimate structure resizing for a selected set of structures. It is shown that using a few processor runtime events, the system can dynamically estimate structure resizing to exploit power-performance efficiency. Results show that using the proposed empirical model, a selective set of key structures can be resized at runtime to deliver 35\% power-performance efficiency over a baseline design, with only 5\% loss of performance.
modeling power