Area-time efficient modulo 2(n)-1 adder design using hybrid carry selection
A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2(n)-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2(n)-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.
modulo 2(n)-1 adder hybrid carry selection architecture residue number system