cancellation of loads that return zero using zero-value caches
The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads -- loads accessing memory locations that contain the value "zero" -- to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18\% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-of-order cores. We propose a non-speculative microarchitectural technique -- Zero-Value Cache (ZVC) -- to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment (typically a 512-byte structure), we can obtain speedups up to 32\%. Most importantly, zero-value caches never cause performance loss.
cache zero load frequent value locality load criticality