bit parallel test pattern generation for path delay faults
A method to apply bit-parallel processing at all stages of robust and nonrobust test pattern generation for path delay faults is presented. Two different modes of bit-parallel processing are combined: fault parallel test pattern generation (FPTPG) and alternative parallel test pattern generation (APTPG). We discuss the problems that appear while exploiting bit-parallelity and we describe how to overcome them. Experimental results demonstrate a reduction of aborted faults and an acceleration up to a factor of nine.
bit parallel test pattern generation parallel test pattern generation path delay faults delays fault method bit-parallel processing robust experimentation demonstrate reduction acceleration factor logic testing parallel processing