Applying analog techniques in digital CMOS buffers to improve speed and noise immunity
A digital CMOS buffer circuit with a voltage transfer characteristic (VTC) with low threshold voltage detection, hysteresis, and high noise immunity is presented. The circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty, offering at the same time high noise immunity to glitches induced either through capacitive coupling or from the power supply lines. The high noise immunity of the proposed buffer circuit is achieved using differential mode rejection and a differential redundant circuit architecture.
cmos buffers noise immunity digital circuits