Image compression sensor based on column parallel architecture
We propose a novel image sensor which has compression function on its sensor plane. The image compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging. The compression algorithm is based on conditional replenishment. It detects motion and encodes only the pixels in moving areas. We have been investigating pixel parallel and column parallel architectures of the image compression sensor. In this paper, we present the column parallel architecture of the proposed sensor. In this architecture, fill factor and power dissipation are comparable to conventional MOS sensors in spite of integration of the processing circuits. We have fabricated a prototype chip based on the column parallel architecture. We describe the circuit and layout design and the results of some experiments using the prototype.
compression column parallel architecture conditional replenishment smart sensor computational sensor intelligent sensor cmos sensor