dynamic task set partitioning based on balancing memory requirements to reduce power consumption
Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on reducing power consumption has become a hot research topic. Different ways to reduce power consumption consist on using processors that do not implement the most power-hungry microarchitectural mechanisms, attacking hot spots, or reducing consumption in the larger microprocessor components like the cache. Unlike these works which focus on specific parts of the microprocessor, Dynamic Voltage Scaling (DVS) is a technique which applies on the whole microprocessor die. This technique allows the system to work at different frequency/voltage levels. DVS costs in a multicore system can be reduced by sharing the same DVS regulator among the cores (global DVS). In this context, to handle energy efficiently, the workload must be properly balanced among the cores. In this paper we propose a new partitioning heuristic aimed at increasing the execution overlapping to reduce energy consumption in coarse-grain multithreaded multicore processors working on a global DVS regulator. The proposed algorithm works by distributing hard real-time tasks attending to two criteria while guaranteeing real-time constraints. Tasks are firstly distributed among cores by balancing memory requirements. This criterion is followed until the utilization of any core reaches a given threshold. Then, as all cores must work at the same speed (global DVS), the less loaded core must be selected each time a task is launched. Energy savings depend on the range of frequency/voltage levels that DVS implements. Experimental results show that the proposed heuristic reduces the energy consumption in almost 3 times with respect to a system with no DVS regulator and applying no heuristic.
multicore coarse-grain multithreaded real-time scheduling power-aware