Critical evaluation of SOI design guidelines
Design guidelines for static and domino silicon-on-insulator (Sol) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for Sol as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of Sol domino circuits is thus proposed. The topic of multiple output domino logic in Sol technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk.
cmos digital integrated circuits integrated circuit design leakage currents silicon-on-insulator (soi) technology