A tool for power and phase noise optimization in frequency synthesizers
In this paper, we present a CAD technique to design low-power and low phase noise integrated frequency synthesizers. This technique introduces a key parameter, Phase Noise per Unit Power, which correlates phase noise and power among all the sub-circuits in the frequency synthesizer. By correlating the performance of all the independent circuits together, sophisticated synthesizer design and optimization can be significantly simplified. We demonstrate a 1.8 GHz frequency synthesizer design in a 0.18 mu m CMOS process achieving -132 dBc/Hz phase noise at 100 kHz offset with less than 4.3 mW power consumption.
phase noise frequency synthesizer low-power pll vco