An automated, FPGA-based reconfigurable, low-power RFID tag ? ??
The use of radio frequency identification (RFID) technology is expanding rapidly in numerous applications such as logistics, supply chain management, transportation, healthcare and aviation. Due to the variety of the current applications, typical RFID systems use application specific hardware and proprietary protocols. These systems generally have long design times, no tolerance to changes in application or standard, and hence very high system costs. This paper describes an RFID tag specification and automated design flow for the creation of customized, low-power, active RFID tags. RFID primitives supported by the tag are enumerated with assembly like RFID macros. From these macros, the RFID pre-processor generates templates automatically. The behavior of each RFID primitive is specified using ANSI C where indicated within the template. The resulting file is compiled by the RFID compiler for the extensible tag. In order to save power, a smart buffer has been developed to sit between the transceiver and the tag controller. Because RFID packets are broadcast to everyone in range, the smart buffer contains minimal logic to detect whether incoming packets are intended for the tag. By doing so, the main controller may remain powered down to reduce system power consumption. Two System-on-a-Chip implementation strategies are presented. First, a microprocessor based system for which a C program is automatically generated and compiled for the system. The second replaces the microprocessor with a block of low-power FPGA logic. The user supplied RFID logic is specified in RFID macros and ANSI-C and automatically converted into combinational VHDL by the RFID compiler. Based on a test program, the processors required 183, 43, and 19?J per transaction for StrongARM, XScale, and EISC processors, respectively. By replacing the processor with a Coolrunner II, the controller can be reduced to 1.11nJ per transaction.
fpga low-power rfid behavioral synthesis