leakage power estimation for deep submicron circuits in an asic design environment
Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consideration of static power in early phases of design development. Design houses that use RTL synthesis based flow for designing ASICs require a quick and reasonably accurate estimate of static power dissipation. This is important for making early packaging decisions and planning the power grid. Keeping this in view, we propose a simple model which enables estimation of static power early in the design phase. Our model is based on the experimental data obtained from simulations at the design level: ln Pleak lib =S lib ln Cells + C lib , where S lib and C lib are the technology-dependent slope and intercept parameters of the model and "Cells" is the number of cells in the design. The model is validated for a large benchmark circuit and the leakage power predicted by our model is within 2\% of the actual leakage power predicted by a popular tool used in the industry.
leakage power leakage power estimation power estimates deep submicron circuits design design environment power dissipation leakage current technologies developer power efficiency product use synthesis flow packaging plan power grid model experimentation data simulation benchmark tool industrial dependencies linear regression