Support for partial run-time reconfiguration of platform FPGAs
Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support. The paper is concerned with several aspects related to the effective exploitation of run-time partial reconfiguration, with particular emphasis on the generation of partial configurations and the run-time utilisation of the reconfigurable resources. The paper presents an approach inspired by the traditional software development: partial configurations are produced by assembling components from a previously created library, thus enabling the embedded application developer to produce the configuration data required for run-time modifications with less effort than is needed with the conventional design flow. A tool that supports this approach is also described. A second set of issues is addressed by a run-time support library that provides facilities for managing the hardware reconfiguration process and the communication with the reconfigured circuits. The use of run-time partial reconfiguration requires a high level of system support. The paper describes one possible approach, presenting a demonstration system developed to support the present work and characterising its performance. In order to clarify the advantages of the approach to run-time reconfigiaration discussed in the paper, two small case studies are described, the first on the use of dedicated datapaths for subword operations and the second on two-dimensional pattern-matching for bilevel images. Timing measurements for both cases are included. (c) 2006 Elsevier B.V. All rights reserved.
run-time reconfiguration platform fpga partial reconfiguration bitstream manipulation run-time support system