hybrid techniques for fast functional simulation
W e implement and experiment with techniques for the functional simulation of very large digital systems. We consider techniques that are a hybrid of classical compiled code simulation and recent branching program based simulation in order to resolve memory performance problems inherent to BDD based cycle simulation. Specifically, predefined functional units (macros) are extracted from the circuit and evaluated directly instead of building BDDs for them. The functionality of those macros, such as multipliers, filters, etc., can in turn be verified by simulation of their gate-level implementations respectively or by formal verification techniques. Our results demonstrate that this approach leads to considerably faster simulation.
simulation asic verification emulation