power savings in embedded processors through decode filer cache
In embedded processors, instruction fetch and decodecan consume more than 40\% of processor power. An instructionfilter cache can be placed between the CPU coreand the instruction cache to service the instruction stream.Power savings in instruction fetch result from accesses to asmall cache. In this paper, we introduce decode filter cacheto provide decoded instruction stream. On a hit in the decodefilter cache, fetching from the instruction cache and thesubsequent decoding is eliminated, which results in powersavings in both instruction fetch and instruction decode.We propose to classify instructions into cacheable oruncacheable depending on the decoded width. Then sectoredcache design is used in the decode filter cache so thatcacheable and uncacheable instructions can coexist in a decodefilter cache sector. Finally, a prediction mechanismis presented to reduce the decode filter cache miss penalty.Experimental results show average 34\% processor powerreduction and less than 1\% performance degradation.
power embedding processor decode cache instruction instruction caches streams paper filtering design predict experimentation performance power-save