low power error resilient encoding for on-chip data buses
As technology scales toward deep submicron, on-chip interconnectsare becoming more and more sensitive to noisesources such as power supply noise, crosstalk, radiationinduced effects, etc. Transient delay and logic faults arelikely to reduce the reliability of data transfers across data-pathbus lines. This paper investigates how to deal withthese errors in an energy efficient way. We could opt forerror correction, which exhibits larger decoding overhead,or for the retransmission of the incorrectly received dataword. Provided the timing penalty associated with this lattertechnique can be tolerated, we show that retransmissionstrategies are more effective than correction ones from anenergy viewpoint, both for the larger detection capabilityand for the minor decoding complexity. The analysis wasperformed by implementing several variants of a Hammingcode in the VHDL model of a processor based on the SparcV8 architecture, and exploiting the characteristics of AMBAbus slave response cycles to carry out retransmissions in away fully compliant with this standard on-chip bus specification.
low power power errors resilience encode data technologies sensitive noise crosstalk effect delay logic fault reliability paper energy efficiency correctness decode timing association detection complexity analysis model processor architecture response standardization