8t single-ended sub-threshold sram with cross-point data-aware write operation
This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.
sram data-aware wirte operation static random access memory