An efficient list scheduling algorithm for time placement problem
The partially reconfigurable FPGAs allows an overlap between the execution and the reconfiguration of tasks. The partial approach can be used to fit a large application into the FPGA device by partitioning the application over time. The executions being partitioned over time and the configurations of tasks are done so that the imposed constraints are satisfied. The main aim of this work consists in answering the question when will a task be mapped in the FPGA? A time placement algorithm based on the list scheduling technique is developed to solve efficiently the above question. We have just used the list scheduling algorithm because of its fast run time. Compared to the run time of other algorithms used in this filed like the spectral and ILP algorithms, the list scheduling algorithm remains a good temporal placement candidate, especially, for a several nodes graph. Also, a part of this paper is devoted for the study and the implementation of DCT task graph. This graph is the most computationally intensive part of the Color Layout Descriptor algorithm of a low-level visual descriptor of MPEG 7. The studied case shows that the use of the partial approach is very efficient in terms of latency of the whole application than the full one.
list scheduling time placement partial reconfiguration run time reconfiguration