Speedups and energy reductions from mapping DSP applications on an embedded reconfigurable system
This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes coarse-grained reconfigurable logic with a micro-processor. The reconfigurable hardware is a 2-D array of processing elements connected with a mesh-like network. Analytical results derived from mapping seven real-life digital signal processing applications, with the aid of an automated design flow, on six different instances of the system architecture are presented. Significant overall application speedups relative to an all-software solution, ranging from 1.81 to 3.99 are reported being close to theoretical speedup bounds. Additionally, the energy savings range from 43 % to 71 %. Finally, a comparison with a system coupling a microprocessor with a very long instruction word core shows that the micro-processor/coarse-grained reconfigurable array platform is more efficient in terms of performance and energy consumption.
energy reduction performance improvement design flow coarse-grained reconfigurable array (cgra) embedded systems reconfigurable computing