a re-engineering approach to low power fpga design using spfd
In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) for low power design after technology mapping, placement and routing are performed. We use Set of Pairs of Functions to be Distinguished (SPFD) to express functional permissibility of each signal. Using different propagations of SPFD to fan-in signals, we change the functionality of a PLB (Programmable Logic Block) which drives large loading into one with low transition density. Experimental results show that our method can reduce on average 12\% power consumption compared to the original circuits without affecting placement and routing.
low power fpgas design use paper method technology mapping placement routing functional signaling change programmable logic blocking transit experimentation power consumption circuits field-programmable-gate-array engine low-power design