Automatic creation of domain-specific reconfigurable CPLDs for SoC
This paper presents tools that automate the creation of domain-specific complex programmable logic devices (CPLDs), targeted for systems-on-a-chip. By tailoring full-crossbar-based CPLDs to the domains that they support, we provide results that beat fixed reconfigurable architectures by 5.5x-11.8x on average in terms of area-delay product. We also create sparse-crossbar-based CPLD architectures, using a novel switch-smoothing algorithm that makes the crossbars amenable to layout. This algorithm reduced the wire jog pitch of our largest layout from 48 to just 3, allowing for a compact very-large-scale-integration layout. These sparse-crossbar-based CPLDs require just 0.37 x the area and 0.30 X the delay of our full-crossbar-based CPLDs. We also address the question of how best to add resources to a CPLD in order to support future, unknown circuits, concluding that the best strategy is to add 5% to the crossbar switch density and to provide additional programmable logic arrays of the same size found in the base architecture.
automation domain-specific complex programmable logic device (cpld) system-on-a-chip (soc)