GATE LOCATION CHANGING: AN OPTIMIZATION TECHNIQUE FOR QUANTUM CIRCUITS
During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to find critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.
gate location changing physical design quantum computing quantum circuit optimization