fpga synthesis for minimum area, delay and power
In this paper, we address the problems of minimizing the area, delay and power during synthesis of field programmable gate arrays (FPGAs). We use Boolean decomposition techniques to minimize the number of configurable logic blocks (CLBs), the depth of the network and the power dissipations. We use OBDDs to represent functions so that our methods can be implemented more effectively. Our mapping algorithm is based on function decomposition which was pioneered by Ashenhurst [1959].
fpgas fpga synthesis synthesis area delay power paper addressing field programmable gate arrays use boolean decomposition techniques decomposition configurable logic blocks configurability logic network power dissipations obdds functional method map mapping algorithm algorithm function decomposition boolean functions logic cad