rtl c-based methodology for designing and verifying a multi-threaded processor
A RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.
rtl methodology design verification multi-threads processor simulation network processor scheduling code translation equivalence checking checking flow performance developer c/c++ formal equivalence