a new low power and area efficient semi-digital pll architecture for low bandwidth applications
Traditional PLL architecture uses one control voltage for both integrated and proportional part of the oscillator. Digital PLL architecture uses 2 control words for integrated and proportional part of the oscillator. In this paper, we describe a new architecture of a Phase lock loop which combines the two approaches and takes the advantages of both.
low power pll quantization noise dpll semi digital pll real time clock