An 8??8 20Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking
In this paper, we propose a reconfigurable load balanced symmetric TDM switch fabric. We fold this two-stage switch to reduce 50% hardware complexity, and then implement a 3.65mm??3.57mm prototype switch fabric IC, including a digital 8??8 switch core, eight 16B20B CODECs, eight SERDES ports, eight CML I/O interfaces and a PLL, in 0.18?m CMOS technology. The digital 8??8 switch core has reconfigurable connection patterns for the ease of scaling up to an NN switch (N is power of 4). We propose the 16B20B CODEC scheme to reduce the switch core clock rate by half. In the SERDES, we employ the half-rate scheme and then use static CMOS gates for the low power consumption. We develop a low power, area-efficient and wide-band CML I/O interface with our patented PMOS active load inductive-peaking scheme for high-speed data transmission. With the 16B20B CODEC, the half-rate, and the PMOS active load schemes, almost 50% of the power is saved as compared with the design of the 8B10B CODEC, the full-rate and on-chip inductors CML schemes. Our measurement shows that an 8??8 switch fabric IC can achieve 20Gbps switching rate and consumes only about 690mW power. A terabit switch fabric can then be constructed by cascading the designed switch ICs.
load balancing symmetric tdm switch 16b20b codec serdes cml pll