A 0.7V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35?m CMOS technology
This paper presents a discussion on an ultralow supply voltage low-dropout regulator (LDO) using a digitally controlled technique. Based on a 0.35?m standard CMOS process with VTN?0.5V and |VTP|?0.7V, measurement results showed that the proposed digitally controlled LDO can operate from 0.7V to 0.9V with a dropout voltage of 200mV. At a supply voltage of 0.9V, the proposed LDO is capable of providing a regulated output of 0.7V and delivering a maximal load current of 50mA at 99.9% current efficiency. With the proposed LDO operated at 1MHz clock, the measured quiescent current is only 4.7?A. No external output capacitor is required to stabilize the control loop. For a supply voltage of 0.9V, the proposed digital LDO features a tunable transient time with a maximal operating frequency up to approximately 14MHz. The proposed LDO can also operate at supply voltages of 0.7V in a 0.35?m standard CMOS process. For an input voltage of 0.7V and an output voltage of 0.5V, the proposed LDO can deliver a maximal load current of 5mA, which meets the specification of recently published 0.5V applications. With these advantages, the proposed digitally controlled LDO is suitable for low-voltage and low-power applications.
output-capacitor-free digital control low-dropout regulator ultralow voltage