analysis of power consumption on switch fabrics in network routers
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs.
analysis power consumption switch network router paper estimates model methodology intern buffers interconnect architecture simulation platform traces dynamic accuracy traffic throughput exploration low power design  framework  high-performance interconnect networks networks on chip systems on chip