through-silicon-via-aware delay and power prediction model for buffered interconnects in 3d ics
In this paper, we present a delay and power prediction model for buffered interconnects used in 3D ICs. The key idea is to model the impact of RC parasitics of Through-Silicon Vias (TSVs) used in 3D interconnects on delay and power consumption. Due to its large size compared with other layout objects such as metal wires, TSVs contain significant RC parasitics, which directly affect the overall delay and power of the wires that contain them. On the other hand, buffer insertion on TSV-based 3D interconnects is also non-trivial mainly because buffers as well as TSVs have non-trivial area overhead. In addition, both TSVs and buffers occupy device and M1 layers, thereby becoming layout obstacles to each other. Our interconnect model accurately captures the impact of both TSVs and buffers on 3D interconnects.
delay power buffer interconnect 3d ic through-silicon via tsv