Low-power flip-flops with reliable clock gating
The paper presents two gated flip-flops aimed at low-power applications. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter and an audio sampler register are presented as examples of low-power applications.
flip-flops cmos digital integrated circuits low-power circuits transition probability