Testing and built-in self-test  A survey
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This built-in self-test (BIST) approach not only offers economic benefits but also interesting technical opportunities with respect to hierarchical testing and the reuse of test logic during the application of the circuit. Starting with an overview of test problems, test applications and terminology this survey reviews common test methods and analyzes the basic test procedure. The concept of BIST is introduced and discussed, BIST strategies for random logic as well as for structured logic are shown.
built-in self-test boundary-scan test pattern generation response analysis scan path