Proposal and implementation of a new interpolation technique for a double folding A/D converter
This proposal of a new interpolation technique is presented for application in a double folding A/D converter with interpolation. This interpolation technique is applied in the master latches of the A/D converter without consumption increase. Compared to resistive interpolation, this new interpolation technique has the advantage of avoiding the resistive interpolation ladder adding only three transistors in some master latches and the current is the same as in the simple master latch. A 6-bit A/D converter was designed and implemented in a 1.2?m BiCMOS process, an FT of 8GHz, to explain the implementation of interpolation circuitry and evaluate the experimental results.
interpolation folding a/d converter