Numerical simulation of creation-passivation kinetics of interface traps in irradiated n-channel power VDMOSFETs during thermal annealing with various gate biases
Influence of gate bias on creation-passivation processes of interface traps in irradiated n-channel MOS transistors during thermal annealing has been investigated. The experimental results, which show the dependence of these processes on gate bias, are explained by combined hydrogen-water (H-W) model. The modelling of kinetics of creation and passivation of interface traps, based on bimolecular theory and numerical analysis, is also performed. Numerical simulation shows that H-W model predicts the maximum of interface trap density and latent interface trap buildup during thermal annealing.
interface traps irradiation annealing mos transistor oxide trapped charge