interconnect layout optimization under higher-order rlc model
Studies the interconnect layout optimization problem under a higher-order RLC model to optimize not just the delay but also the waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner (RATS) trees, providing a smooth trade-off among signal delay, waveform and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot and routing cost.
interconnect layout optimization interconnect layout optimality higher-order rlc model model delay circuits signaling response topology optimization topologies wire-sizing optimization waveform optimization algorithm class routing topologies routing shortest-path steiner trees trees bounded-radius steiner trees steiner routings smooth signal delay routing area incremental computation evaluation quality experimentation signal settling time timing voltage overshoot routing cost cost circuit optimisation order rats trees required-arrival-time steiner trees nonmonotone signal response waveform quality evaluation shortest path size delay optimization