Dynamic-width reconfigurable parallel prefix circuits
Parallel prefix circuits have drawn high interest because of their importance in many applications such as fast adders. Most proposed parallel prefix circuits assume fixed width. The input size could be of the same width as the circuit or different than the width of the circuit. In this paper, we propose a class of reconfigurable parallel prefix circuits, \(\check{R}\)-circuits, that support different operational modes. The \(\check{R}\)-circuit can be reconfigured as one parallel prefix circuit of high width as well as several smaller width parallel prefix circuits that can operate on different prefix problems in parallel. In particular, an \(\check{R}\)-circuit, \(\check{R}(k(m))\), of width km with \(k\) building blocks (slices) each of width \(m\), can be configured as a number of \(z\) prefix circuits, \(z\le k\), each of width \(b_{j}\), such that \(\sum \nolimits _{j=1}^z {b_j } =km\). For a circuit \(CR_b \in \check{R}(k(m))\) of \(b\) slices and width bm, we show how such circuit can be constructed. We derive a bound for the depth of \(CR_b \) and show how \(CR_b \) can handle input size \(n\ge bm\). Then, we show the performance of \(\check{R}(k(m))\) and compare it with other fixed same-width prefix circuits.
dynamic-width circuits prefix operations parallel algorithms reconfigurable circuits