a delay measurement method using a shrinking clock signal
This paper describes a delay measurement method using a shrinking clock signal. The shrinking clock is generated from an AND operation on two clock signals having slightly different periods, which are provided by an external tester. Instead of measuring the number of clocks before it vanishes, another AND operation is utilized to reduce the size of the counter. A differential approach is used to minimize the effect from any non-ideal behavior of circuits used for the measurement as well as to substitute for calibration. In the proposed method, the dynamic range, the measurement resolution and accuracy do not depend on the measurement circuit itself, but on the external clocks from the tester. Circuit-level simulations show good linearity and measurement accuracy regardless of process, voltage, and temperature (PVT) variations when the edge placement accuracy of the external tester amounts to 100ps.
delay measurement tester edge placement accuracy