Comments on Dual-rail asynchronous logic multi-level implementation
Comments on Dual-rail asynchronous logic multi-level implementation are provided. Incorrect interpretation of disjoint sum-of-products (DSOP) form is clarified. Possibility for the occurrence of deadlock condition is elucidated. Problems with completion detection are described. Nave and incorrect decomposition of NAND gates in the function block is explained.
asynchronous logic multi-level implementation decomposition boolean network node