an architecture for graphics processing in an fpga (abstract only)
Graphics processing is most often accomplished in standalone ASICs that were originally designed for gaming applications. The graphics processors produce visually appealing functionality based upon 3D rendering algorithms, but they can also require large amounts of power and typically have only short-term device availability. This paper proposes a novel architecture for graphics processing in an FPGA that is motivated by industrial applications that require low power, high reliability, low cost, and long-term device availability. Due to resource constraints and architectural constructs, many traditional graphics processing concepts do not translate well to FPGAs; hence, a graphics processing architecture crafted specifically for FPGAs is needed. The proposed architecture provides a high degree of scalability and flexibility to allow customization for unique applications, and it also features the migration of technology that previously has been used only for packet processing. The unique multi-threaded packet processing engine accelerates the line rasterization with a careful partitioning of the processing across software and hardware. The baseline architecture, which can be scaled for higher performance through parallelisms, will be capable of rasterizing over 50 million pixels per second -- more than enough for any application with XGA resolution. Future work will focus on the complete implementation and optimization of the architecture as well as an extension to support general-purpose computations (GPGPU) on the FPGA-based graphics processor.
architecture fpga scalability flexibility gpu