Design of instruction address queue for high degree x86 superscalar architectures
A major hurdle of recent x86 superscalar processor designs is limited instruction issue rate due to the overly complex x86 instruction formats. To alleviate this problem, the machine states must be preserved and the instruction address routing paths must be simplified. We propose an instruction address queue, whose queue size has been estimated to handle saving of instruction addresses with three operations: allocation, access, and retirement. The instruction address queue will supply the stored instruction addresses as data for three mechanisms: changing instruction flow, updating BTB, and handling exceptions. It can also be used for internal snooping to solve self-modified code problems. Two CISC hazards in the x86 architectures, the variable instruction length and the complex addressing mode, have been considered in this design. Instead of the simple full associative storing method in lower degree (< 4) superscalar systems, the line-offset method is used in this address queue. This will reduce by 1/3 the storage space for a degree-5 superscalar x86 processor with even smaller access latency. We use synthesis tools to analyze the design, and show that it produces optimized results. Because the address queue design can keep two different line addresses in an instruction access per cycle, this method can be extended for designing a multiple instruction block issue system, such as the trace processor.
address queue superscalar processor x86 architecture ilp multiple instruction issue