A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System
This paper presents the design of a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. Based on a single phase-locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. The image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18-mu m CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm(2) providing 14 bands I/Q phases.
frequency synthesizer i/q calibration multi-band orthogonal frequency division multiplexing (mb-ofdm) ultra-wide band (uwb) phase-locked loop (pll) single-side band (ssb) mixer