Application of design reuse to artificial neural networks: case study of the back propagation algorithm
The aim of this paper is to propose a new high-level hardware design reuse methodology for automatic generation of artificial neural networks (ANNs) descriptions. A case study of the back propagation (BP) algorithm is proposed. To achieve our goal, the proposed design methodology is based on a modular design of the ANN. The originality of the work is the application of design for reuse (DFR) and the design with reuse (DWR) concepts to ANNs. The DFR is used for the generation of the general ANN architecture, while the DWR is applied for the exploration and exploitation of predefined ANN submodules components that are stocked in a library. The result is a synthesis and parameterisable soft IP-ANN VHDL code ready for placement and routing. With this approach, the user/designer can fix the ANN parameters and choose between different architectural possibilities and performances. The approach has been applied to the three case figures of the BP algorithm. These are the off-chip implementation, the on-chip static implementation and the on-chip-based run time reconfiguration (RTR). To validate our approach, performance evaluation of the three case architectures of the BP algorithm, using the Virtex-II and Virtex-4 FPGA is done through three examples: the XOR problem, a cardiac arrhythmia classifier and a high-dimension ANN circuit. To evaluate the design reuse concept, two tests are done: the first one concerns estimation of the cost of the design. Results show that the application of the DFR is time consuming compared to the design from scratch: 168% for the off-chip implementation, 256% for the on-chip static implementation and 260% for the on-chip RTR. However, after reuse, the design time is reduced to 0.5% for off-chip implementation, 2.08% for on-chip static implementation and 2.5% for on-chip RTR implementation. The second test concerns evaluation of the generated IP-ANN code, using the OpenMore tool. Results show a mean score of 62% which lead us to conclude that the IP-ANN code is good to be reused.
reuse artificial neural networks design for reuse (dfr) design with reuse (dwr) off-chip implementation run time reconfiguration fpga openmore on-chip implementation design cost