Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up
Counter-based power models have attracted the interest of researchers because they became a quick approach to know the insights of power consumption. Moreover, they allow one to overpass the limitations of measurement devices. In this paper, we compare different Top-down and Bottom-up Counter-based modeling methods. We present a qualitative and quantitative evaluation of their properties. In addition, we study how to extend them to support the currently ubiquitous dynamic voltage and frequency scaling (DVFS) mechanism. We propose a simple method to generate DVFS agnostic power models from the DVFS-specific models. The proposed method is applicable to models generated using any methodology and allows the reduction of the modeling time without affecting the fundamental properties of the models. The study is performed on an 18 DVFS states Intel((R)) Core (TM) 2 platform using the SPECcpu2006, NAS and LMBENCH benchmark suites. In our testbed, a 6x reduction on the modeling time only increments 1% point on average the error in the predictions.
power modeling dvfs power estimation performance counters