Low voltage and mismatch analysis of quadruple source coupled Multi-input Floating-gate Mosfet multiplier with offset trimming
Considerations for optimisation of the MFMOS (Multi-input Floating-gate Mosfet) multiplier for gain, minimal total harmonic distortion, low supply voltage operation and offset trimming are considered in this paper. Analysis shows that good matching between pairs of devices are essential for low harmonic distortion. Results from simulation studies show that offset trimming can be facilitated by connecting the de bias inputs in pairs and biasing them separately. A +/-1.5 volt supply MFMOS multiplier has been designed and fabricated. Measured THD and nonlinearity at fullscale input are 0.8% and 0.5%, respectively. Bandwidth is more than 20 MHz and input dynamic range over a 0-1 MHz bandwidth is 92.6 db. The lowest measured operable supply voltage is +/-0.9 volt.
floating-gate mosfet analog multiplier square-law