an efficient heuristic for instruction scheduling on clustered vliw processors
Clustering is a well-known technique for improving the scalability of classical VLIW processors. A clustered VLIW processor consists of multiple clusters, each of which has its own register file and functional units. This paper presents a novel phase coupled priority-based heuristic for scheduling a set of instructions in a basic block on a clustered VLIW processor. Our heuristic converts the instruction scheduling problem into the problem of scheduling a set of instructions with a common deadline. The priority of each instruction v i is the l max ( v i )-successor-tree-consistent deadline which is the upper bound on the latest completion time of v i in any feasible schedule for a relaxed problem where the precedence-latency constraints between v i and all its successors, as well as the resource constraints are considered. We have simulated our heuristic, UAS heuristic and Integrated heuristic on the 808 basic blocks taken from the MediaBench II benchmark suite using six processor models. On average, for the six processor models, our heuristic improves 25\%, 25\%, 33\%, 23\%, 26\%, 27\% over UAS heuristic, respectively, and 15\%, 16\%, 15\%, 9\%, 20\%, 8\% over Integrated heuristic, respectively.
instruction scheduling clustered vliw processor inter-cluster communication latency inter-instructional latency