set-based nano-circuit simulation and design method using hspice
This paper presents a simulation and design method for complementary SET-based nano-circuits. A HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows a reduced CPU time and more compatibility with other SPICE softwares on both Windows and Unix. The design methodology illustrates how to build CMOS-like SET circuits, and based on it, conventional static CMOS circuit design methodologies are all applicable to SET circuit designs. Simulation results show that, for 1M$\Omega$ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3pW, and the propagation delay for a SET XOR2 gate is only 29.8ns while driving a 10aF load.
set modeling set circuit design set simulation with hspice