A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing
This paper presents a link layer design of DisplayPort interface with a state machine based packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 ALUTs(Loop Up Tables), 6,020 register, and 451,425 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.
displayport main link auxiliary channel (aux channel) displayport configuration data(dpcd) extended display identification data(edid) digital visual interface(dvi)