a novel dynamic power cutoff technique (dpct) for active leakage reduction in deep submicron cmos circuits
Due to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the dynamic power cutoff technique (DPCT). First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. Each group is turned on only long enough for a wavefront of changing signals to propagate through that group. Since each gate is only turned on during a small timing window within each clock cycle, this significantly reduces active leakage power. This technique can also save standby leakage and dynamic power. Results on ISCAS '85 benchmark circuits modeled using 70 nm Berkeley Predictive Models [1] show up to 90\% active leakage, 99\% standby leakage, 54\% dynamic power, and 72\% total power savings.
dynamic power power cutoff standby current leakage current stacking