conflict-free access of vectors with power-of-two strides
An address mapping and an access order is presented for conflict-free access to vectors with any initial address and power-of-two strides. We show that for this conflict-free access it is necessary that the memory be unmatched and present an implementation for M=2T, where M is the number of modules and T the module latency. Moreover, the implementation allows the masking of the latency of the address calculation, of the mapper, and of the bus arbiter.
conflict-free access access vectorization power-of-two strides addressing map order memorialized implementation module latency vector processors conflict power storage schemes multi-module memories out-of-order access