Dual-threshold CAD framework for subthreshold leakage power aware FPGAs
Managing leakage power in field programmable gate arrays (FPGAs) has become critical for the FPGA industry to remain competitive in the semiconductor market and enter the mobile applications domain. This paper proposes and evaluates several dual-Vt-based designs of FPGA architecture for reducing the leakage power. A dual-Vt FPGA computer-aided design (CAD) framework has been proposed, which is used to develop and evaluate different dual-Vt FPGA architectures. The logic elements and the routing resources are considered as candidates for dual-Vt assignment. The authors estimate the number of the logic elements that can be assigned as high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework. Based upon this estimate, the authors develop and evaluate two kinds of architectures, homogenous and heterogenous. The results indicate that an average leakage-power savings of up to 50% can be obtained from these architectures. This CAD framework can also be used for developing and evaluating different dual-Vt FPGA architectures other than the ones proposed in this paper.
field programmable gate arrays (fpgas) cmos digital integrated circuits delay estimation design automation leakage currents