Fast physical design of CMOS ROs for optimal performance using constrained NSGA-II
The performance of nanoscale radio frequency integrated circuits (RFIC) is influenced by the circuit parasitics and device dimensions. The present work predicts the design parameters of CMOS ring oscillator (CMOS RO) for its optimal performance and designs the CMOS RO using these parameters in Cadence Virtuoso Analog Design Environment with GPDK 90nm process. An efficient optimization technique, non-dominated sorting based genetic algorithm (NSGA-II) is used to minimize the power consumption and phase noise of the circuit at its schematic and physical levels. This optimization is also carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and by considering the variations in the process parameters. The optimization algorithm, effectively converts several time consuming design iterations to a single step design, ensuring the near best performance of the CMOS RO with all possible real time constraints. In this proposed design methodology the optimization objectives such as frequency, power and phase noise are formulated in such a manner that those are implicitly parasitic aware. The design of CMOS RO with different number of stages is verified by performing simulations for transient and noise analysis using Cadence tools.
cmos ring oscillator (cmos ro) parasitic aware design analog and mixed signal (ams) circuit non-dominated sorting genetic algorithm ii (nsga-ii)