Low-voltage BiCMOS four-quadrant multiplier and squarer
A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 mu m BiCMOS process. Experimental results show that for a power supply of +/- 1.5 V, the linear range is over +/- 0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to +/- 0.8 V. The measured -3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 mu W. The squarer modified from the proposed multiplier has the input range up to +/- 1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.
bicmos multiplier squarer