the horizon supercomputing system: architecture and software
Horizon is the name currently being used to refer to a shared-memory Multiple Instruction stream - Multiple Data stream (MIMD) computer architecture under study by independent groups at the Supercomputing Research Center and at Tera Computer Company. Its performance target is a sustained rate of 100 giga (10 11 ) Floating Point Operations Per Second (FLOPS) . Horizon achieves this speed with a few hundred identical scalar processors. Each processor has a horizontal instruction set that allows the production of one or more floating point results per cycle without resorting to vector operations. Memory latency is hidden, assuming enough parallelism is available, by allowing processors to switch context on each machine cycle. In this overview, the Horizon architecture is introduced and its performance is estimated. The processor instruction set and a simple programming example are given. Additional details on the processor architecture, interconnection network design, performance analyses, machine simulator, compiler development, and application studies can be found in companion papers.
supercomputer computation architecture software memorialized instruction streams data streaming group research performance floating point point operability processor product vectorization latency parallel switch context program examples interconnection network design simulation compilation developer applications paper shared memory system architecture