A 1 mW power-efficient high frequency CML 2:1 divider
In this study, a low power high operating frequency current mode logic (CML) 2:1 divider is presented. Because the latching transistor pair is biased in low current mode, the proposed divider is power-saving. In this divider, each latch has only one clock transistor, which means that the capacitive load to the former stages is reduced. This makes the buffer of the voltage controlled oscillator (VCO) or VCO be easily designed in phase locked loops. Besides, an active inductor is used in this circuit to resonate with parasitic capacitances and thus endows this topology a high-speed capability. The measurement results indicate that the proposed divider achieves an operation band from 10 to 15 GHz with only 1mW power dissipation.
high frequency low power cml divider cmos