Simulation of an integrated architecture for IP-over-ATM frame processing
The performance of an integrated architecture for full-duplex IP-over-ATM processing is evaluated through detailed simulation. The architecture combines processing, memory, and multiple direct-memory-access engines for single-chip implementation. The simulation models the segmentation and reassembly operations needed to translate IP frames to and from a fixed ATM cell size. A key operation is the insertion of a virtual path and virtual channel identifier (VPI/VCI) into the outgoing ATM cells. Software-based VPI/VCI insertion provides flexibility but requires the on-chip processor to perform this function. Hardware-based VPI/VCI insertion is an optimization that requires one of the direct-memory-access engines to perform this task. The two approaches are evaluated through simulated execution of representative control software with detailed modeling of all on-chip components. Results indicate that software-based VPI/VCI insertion supports full-duplex traffic at 475 Mbps on a 500-MHz processor and that hardware-based VPI/VCI insertion supports full-duplex traffic at 560 Mbps on a 500-MHz processor.
ip-over-atm computer networks processor-memory integration computer systems discrete-event simulation