A scalable interconnection network architecture for petaflops computing
Extrapolating technology advances in the near future, a computer architecture capable of petaflops performance will likely be based on a collection of processing nodes interconnected by a high-performance network. One possible organization would consist of thousands of inexpensive, low-power symmetric multiprocessor (SMP) nodes. Each node will inject data into the interconnection network at a very large rate and consequently, the interconnect scheme is one of the most crucial design issues affecting system performance. This paper describes the 2D simultaneous optical multiprocessor exchange bus ( 2D SOME-Bus) which has the potential to become the basis of a high-end computer architecture capable of petaflops performance. It consists of N horizontal, N vertical 1D SOME-Bus networks, and N 2 nodes. Each node is connected to one horizontal and one vertical 1D SOME- Bus. Each of N nodes connected to one 1D SOME- Bus has a dedicated broadcast channel and an input channel interface based on an array of N receivers monitoring all N channels and allowing multiple simultaneous broadcasts. In the 2D SOME-Bus, messages being broadcast on one Bus can be broadcast in a cut-through manner on one or more Buses in the other dimension. This paper describes the optoelectronic devices and technology which make the 2D SOME- Bus possible, and the network interface organization. It also presents simulation results which compare the performance of the 2D SOME- Bus, the 1D SOME- Bus, the crossbar and the torus under the message-passing paradigm.
interconnection networks petaflops computing computer architecture performance analysis