secure processing using dynamic partial reconfiguration
A popular research topic as of late has been dynamic partial FPGA (Field Programmable Gate Array) reconfiguration. This concept allows on-the-fly reconfiguration of digital systems where only parts of the circuit change, providing application acceleration and allowing static modules to continue processing unaffected by the dynamic elements. Design characteristics which benefit from this progressive approach include increased system flexibility, increased performance, and a reduction in circuit complexity. One characteristic receiving limited focus thus far has been the increased security that could result from these changing circuits. This benefit is innate to the design and makes reverse engineering of the system a much more ambitious task. In an effort to further enhance this passive security feature, a new partial reconfiguration technique has been proposed that changes connectivity between generic modules. This extended abstract introduces the method, model, and design flow for this dynamic partial FPGA reconfiguration technique and addresses the security implications of such a design.
partial reconfiguration field programmable gate arrays sandboxes system security