A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays
This paper presents a method based on stochastic logic to analyse fault trees. This method supports both static and dynamic gates, and can be applied to any type of fault trees. In this paper, static and dynamic gates would be translated into stochastic logic templates, and a hardware implementation for each gate would be achieved. Based on these hardware templates, it is possible to implement the whole logic on a Field-Programmable Gate Array (FPGA). Utilizing the stochastic logic for implementing a given fault tree on FPGA, the analysis would outperform the following parameters compared to traditional methods: 1) Speed-up, 2) Simplicity, 3) Reliability, and 4) Accuracy. Experimental results illustrate that using stochastic logic for modeling fault trees results in fast convergence of Monte Carlo simulation. Moreover, on average, our FPGA approach takes 50% of the time required by previous emulation approaches. Simplicity is an additional advantage of the proposed approach, achieved because of simplicity behind stochastic logic. Also, the stochastic logic is more reliable compared to traditional logic because any faults like SEUs in stochastic logic have less impact on the whole results compared to traditional arithmetic logic. To evaluate the proposed technique, the analysis is performed on several standard benchmarks composed of static and dynamic gates. The results obtained using this approach agree with those obtained from an analytical approach, which proves that the method is an accurate tool for system reliability modeling.
fault tree analysis stochastic logic field-programmable gate array static and dynamic gates single event upset