lp based cell selection with constraints of timing, area, and power consumption
This paper presents a new LP based optimal cell selection method. Optimal cell selection is a useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it reduces the clock cycle of a manual designed 13k-transistor chip by 17\% without any increase of area.
select constraint timing power consumption power paper optimality method tool tuning design time constraint efficiency experimentation clock