New low-power 13.56-MHz CMOS ring oscillator with low sensitivity of f(OSC) to V(DD)
A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, f(OSC), to decay of the power supply V(DD). By employing a g.-boosting subcircuit, power dissipation is decreased to 49 mu W at fosc = 13.56 MHz. The sensitivity of f(OSC) to VDD is reduced to -0.02 at f(OSC) = 13.56 MHz thanks to the use of composite high-impedance current sources.
cmos ring oscillator low power g(m)-booster v(dd)-dependency composite transistor figure of merit