Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous
3D Stacked IC (3D-SIC) technology is becoming increasingly popular due to its improved design density and performance. However, single global clock distribution to a 3D-SIC can be very challenging and is far more prone to process and environmental non-idealities, which somewhat limits the scope of 3D-SICs. A possible solution to this problem is to perform inter-logic-layer communication in 3D-SICs using clock domain crossing (CDC) techniques. In this paper, we investigate the two classes of CDC techniques; the semi Quasi Delay Insensitive QDI-based asynchronous and loosely synchronous CDC. In particular, the paper explores the main challenges faced by these CDC techniques in utilizing through-silicon vias (TSVs). Representative designs from each technique are used for performing proof of concept electrical simulations. Our experimental results are expected to facilitate the 3D-SIC logic designers to choose the most appropriate CDC technique for a given design context. For example, one of the key findings of this paper is that although semi QDI-based asynchronous design provides an attractive solution because of its relaxed constraint on clock distribution network, but it has more timing overhead for TSV failures than the counterpart loosely synchronous design.
clock domain crossing 3d-sics tsv gals