logic design automation of diagnosable mos combinational logic networks
The MOS (Metal Oxide Semiconductor) offers a lot of advantages over the bipolar logic elements, such as smaller size, complexity and power consumption, as well as more flexibility and versatility. Since MOS is playing a major role in LSI (large scale integration), synthesis of MOS networks with a large number of variables is very important. In this paper, an efficient algorithm for computer-aided synthesis of MOS combinational logic networks is presented. The algorithm can synthesize both completely and incompletely specified switching functions of a large number of variables. It rapidly generates an easily-testable MOS network with near-minimum number of MOS complex cells and FET's (field effect transistors). A 10-variable example is given to illustrate the algorithm step-by-step. The algorithm has been programmed in FORTRAN IV for UNIVAC 1108 and the results of computer execution is reported. Statistical data has been taken to evaluate the performance and efficiency of the algorithm.
logic design logic automation network size complexity power consumption flexibility play role integrability synthesis variability paper efficiency algorithm computation switch effect examples statistics data evaluation performance large-scale