Asynchronous microprocessors: From high level model to FPGA implementation
Asynchronous logic principles can be potentially advantageous for novel micro-processor designs as they offer greater design modularity and complete avoidance of clock distribution, mitigate various negative operational effects such as metastability, high power dissipation and electromagnetic emission, to name but a few. The designs of the Amulet microprocessors, originally built as an asynchronous challenge to the clocked ARM architecture, have already demonstrated that some of these benefits can be realised in practice. As more asynchronous processor designs are expected within the next decade, the problem of an efficient design methodology is of prime importance. We present an FPGA implementation of an asynchronous microprocessor, called ADLX. This microprocessor employs 2-phase event driven transition signalling logic that functions within the conceptual framework of a Sutherland micropipeline. The implementation was constructed from a series of VHDL descriptions using a range of commercially available products. Parts of the design were developed using Petri Net models which were validated and then synthesized using Petrify, a software tool designed for the manipulation of concurrent specifications of asynchronous control circuits.
asynchronous logic petri nets field programmable gate arrays