an empirical analysis of the performance of a multiprocessor-based circuit simulator
Our original MSPLICE multiprocessor-based circuit simulator showed excellent efficiency with up to 10 processors. As shown in this paper, however, the efficiency of the program drops significantly when over 40 processors are used. A new generation of the MSPLICE program is described which shows high efficiency with up to 99 processors for three different benchmark circuits. Data is compared against predictions made from simulations of an ideal Gauss-Seidel machine model with unit delay, and the data as well as the model are evaluated in light of this comparison. The results from the new implementation are used to study actual limitations that arise as more processors are employed to solve the circuit simulation problem. A major problem identified is that of scheduling overhead and queue contention. Elimination of this bottleneck has led to significant performance improvement. Another bottleneck discovered in the original implementation was that of global data structure contention. Solutions for these and other problems have been implemented in MSPLICE and are currently being used to direct the continued development of the program.
empirical analysis performance processor circuit simulation circuits simulation efficiency paper generation benchmark data predict model delay lighting comparisons implementation scheduling contention global data structures direct developer multiprocessor