A micropower low-voltage multiplier with reduced spurious switching
We describe a micropower 16 x 16-bit multiplier (18.8 muW/MHz @ 1.1 V) for low-voltage power-critical low speed (less than or equal to 5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by similar to 62 % and similar to 79 % compared to conventional 16 x 16-bit and 32 x 32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the Latch Adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from similar to 5.6 and similar to 10 per adder in the Adder Block in conventional 16 x 16-bit and 32 x 32-bit designs respectively to similar to 2 in our designs. Based on simulations and measurements on prototype ICs (0.35 mum three metal dual poly CMOS process), we show that our 16 x 16-bit design dissipates similar to 32 % less power, is similar to 20 % slower but has similar to 20 % better energy-delay-product (EDP) than conventional 16 x 16-bit multipliers. Our 32x32-bit design is estimated to dissipate similar to 53 % less power, similar to 29 % slower but is similar to 39 % better EDP than the conventional general multiplier.
low-voltage multiplier arithmetic low power switching activity