A reduced delay method for improving the performance of sigma-delta analog-to-digital converters (ADC)
Excess loop delay in a continuous-time switched-current SigmaDelta modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the "predicted next state" to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6-10 dB improvement in dynamic range for a second-order SigmaDelta modulator.
analog-to-digital converters continuous-time switched-current lossless digital integrator