a framework for layout-level logic restructuring
It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only visible after layout. As a result, several attempts at physically aware logic synthesis have been made (e.g.,[2], [9], [14], [4], [7], [12], [16], [15]). In this paper a corrective methodology is proposed for timing-driven logic restructuring at the placement level; the approach currently focuses on LUT-based FPGAs. Driven by placement level static timing analysis, the method induces relatively large, timing-critical fan-in trees via (temporary) replication as in [9]. Such trees are then reimplemented where the degrees of freedom include functional decomposition of LUTs, subject graph covering/mapping, and physical embedding. A dynamic programming algorithm optimizes over all of these freedoms simultaneously. All simple disjoint decompositions (i.e., Ashenhurst style) are encoded in the subject tree/graph using choice nodes similar to those in [11]. At the same time, because embedding is done simultaneously, interconnect delay is directly taken into account We have implemented the framework and in many cases we were able to approach a fixed flip-flop lower-bound on achievable clock period. Promising experimental results are reported with average 14.8\% (up to 37.4\%) clock period reduction compared with the timing-driven placement from VPR [13] and average 6.6\% (upto 17\%) reduction compared with the basic fan-in tree embedder from [9].
logic resynthesis timing optimization