Rail-to-rail adaptive biased low-power Op-Amp
This paper presents a novel power-efficient operational amplifier (Op-Amp) topology, suitable for both standard CMOS and bipolar technologies. The circuit is based on the adaptive biasing (AB) topology, presented by the authors earlier (Microelectron. J. 30(3) (1999) 223), aimed to find an optimum trade-off between slew-rate and power consumption. The proposed amplifier has been designed by applying the above-cited AB principle to both the input stage (for increasing dynamically the input source current, see Microelectron. J. 31(3) (1999) 153) and the class-AB output stage (to control and limit the output current). A constant-Gm topology has been used in the input stage in order to obtain high linearity and good frequency compensation. The circuit shows rail-to-rail input and output characteristics and good performance as well as a high efficiency factor when compared with the other adaptive biasing solutions presented in the literature.
adaptive biasing low-power spice simulation