Design of High Speed BCH Codec for Solid State Recorder in Statellite
Because of the existing of single-event effects for mass solid state recorder in satellite due to space radiation a BCH codec is designed and implemented in FPGA (Field Programmable Gate Array) with high speed and high efficiency. On, the aspect of encoder, an 8-parallel BCH encoder architecture based on unfolding algorithm is proposed, which achieves the throughput of 800Mbps, while the scale of hardware can be reduced to 1/8 of that with the traditional serial encoder architecture; on the aspect of decoder, an 8-parallel decoder architecture inheriting the basic idea of systolic array is proposed to achieve the throughput of 260Mbps, while the decoding latency can be reduced to 1/8 comparing with the traditional serial decoder architecture.
bch unfolding algorithm systolic array state solid recorder (ssr) modified euclid algorithm