Dynamically configurable bus topologies for high-performance on-chip communication
The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose FLEXBUS, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. FLEXBUS achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of FLEXBUS-based architectures. The techniques underlying FLEXBUS are general, and are applicable to a variety of bus standards. We have implemented FLEXBUS as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied FLEXBUS to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UNITS turbo decoder. Our results show that FLEXBUS provides gains of up to 34.55% in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.
communication architectures system-on-chip (soc) on-chip buses high-performance communication