A pixel pipeline architecture with selective z-test scheme for 3D graphics processors
We propose pixel pipeline architecture with a selective z-test scheme that focuses on reducing the data processed in the pixel pipeline by employing preprocessing. Reduction of data can reduce the data transmission between the 3D graphics processor and the memory and also reduce the power consumption of memory access, which is a critical point in the case of mobile devices. In 3D graphics processor, most of the memory transmissions are occurred in rasterization stage, especially in pixel pipelines. To reduce memory transmission, the proposed architecture exploits the coherency among pixel fragments to predict the visibility of each pixel fragment. Through this, the proposed architecture eliminates invisible fragments before texture mapping using a single z-test, which would require two z-tests in the mid-texturing architecture. According to the simulations, the proposed architecture reduces data transmission by 19.922.6% as compared to the mid-texturing architecture at the expense of a 5% reduction in performance. Further, the proposed architecture also reduces the cell area of the depth cache by 26.4% and the area of overall architecture by 6% as compared to that in the mid-texturing architecture.
3d graphics graphics hardware rendering hardware pixel cache