a chip for low-cost raster-scan graphic display
Lowering the cost of graphic display units for use in personnal computers and as time-sharing consoles suggests the use of TV sets. Display electronics for such a raster-scan unit will include a screen memory containing the state of all displayable points, that is up to 256 Kbits for 512  512 B&W display and more for colour applications. Technological advances in NMOS memories make such memory sizes cheaper and cheaper. The control part ensuring screen refresh, memory management, vector and character generation, and computer coupling remains very complex. A microprocessor-oriented Large-Scale-Integrated circuit including all these functions has been designed at the Ecole Normale Suprieure. Versatility has guided the design, as well for screen memory organization as for microprocessor interface. Display resolution from 64  64 to 512  512 are possible, with any number of colours or grey levels, depending only upon the memory size. Microprocessor interface is standard: an eight bits bidirectionnal data bus, a four bits address bus, a read-write signal and an interrupt request. These signals control the vector and character generators which execute microprocessor's commands during the idle phasis of the display controller. This permits an always clean diplay and yet a decent average speed of one point every 1.3 &mgr;s. In addition, a light-pen or crosshair circuitry allows interactive graphic use.
cost graphic display graphics use computation memorialized point applications size control management vectorization character generator character generation couples complexity microprocessor circuits design organization interfaces standardization data addressing signaling interactive graphics large-scale screen buffer management raster-scan display vector generator graphic and microprocessor timing low cost graphic integrated circuit read writing scan colour graphic lighting sharing pen integrability