A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs
Recent studies have shown that On-Chip Interconnects (OCI) architecture represents one of the most important component that determines the overall performance of future System-on-Chip (SoC). In order to improve the performance of a specific SoC application domain, the OCI architecture must be optimized at design/run time. Different OCI-based architectures have been recently proposed, the most recent ones are fractal-based or self-similar topologies. In this paper, we present a customization approach by adding strategic links targeted to match large application workload. Simulations results show the effectiveness of this method to achieve better performance compared to the basic OCI architectures. Furthermore, fractal based OCIs perform well almost in all traffic patterns because of their attractive properties.
design space exploration system-on-chip simulation on-chip interconnect customization performance evaluation