Optimization of gate stack parameters towards 3D-SONOS application
A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation.
sonos fusi charge trapping memory thin film substrate