Design of SDH STM-1 transmission test set
In this paper, we describe the design of a SDH STM-1 test set, including the hardware and firmware designs. The major function of the test set is to generate the desired test patterns and analyze results. This is achieved by using two Bit Error Rate Tester chips and the custom designed FPGA. The firmware is designed based on a real time operating system and integrated with the hardware. The test set can be used for bit error rate analysis, error and alarm tests, which can be performed on STM-1 or TU-12 (E1) level. An external E1 test set can also be cascaded with this STM-1 test set for more detailed analysis. This test set provides quick continuity checking, fault localization, and performance evaluation, thus provides significant aids to the installation of SDH equipment.
test set bit error rate tester fpga synchronous digital hierarchy