An on-chip frequency programmable test clock generation and application method for small delay defect detection ?
A launch and capture clock generator (LCCG) is proposed for generating faster-than-at-speed test clock with programmable frequencies, which can be used to detect SDDs effectively by reducing the slacks of paths under test. The frequencies of faster-than-at-speed test clocks can be easily programmed by embedding the control information into the test patterns. Moreover, the frequencies of the generated test clocks have a high resolution and can achieve a large dynamic range. Both LOC and LOS test frameworks can be supported by the proposed method. The control information for selecting various test frameworks can also be embedded in the test patterns. The reason of not considering the ES test framework in this paper is that the enhanced scan delay testing approach is rarely used in industry for the unacceptable hardware overhead. With a programmable clock selection signal from the LCCG, a clock signal selector is designed to effectively support the application mode such as scan mode, functional operation mode, and test mode by selecting the required clock signal. Frequency variation of the generated test clock in the presence of process variations is analyzed. A method for preventing yield loss caused by frequency variation is presented, so that the test clock period can be programmed to leave a sufficient margin to avoid yield loss. The hardware overhead of the proposed LCCG and clock signal selector is very low, which isapproximately equal to that of 40 standard muxed-D scan cells and can be ignored by modern designs.
small delay defect faster-than-at-speed delay testing launch on capture launch on shift