A graph based approach for reliability analysis of nano-scale VLSI logic circuits
This work proposes a fast method to analyze the reliability of logic circuits. It is based on a modified form of Masons rule and probabilistic SFG (PSFG). A system of nonlinear equations is solved using fixed-point iterations. Employing the sparsity of matrices, the proposed approach is scalable. Compared to previous works it is 7X faster and runtime complexity is O(N0.86).
reliability masons rule signal flow graph combinational logic probabilistic graph