Predicting potential performance for digital circuits
This paper presents a new concept of potential slack to measure so-called potential performance of digital circuits. Potential means how much improvement could be made in the future in terms of timing, area, and power dissipation. Predicting potential performance helps the circuit designers make good design decisions at a specific level of abstraction. We describe two algorithms for potential slack: an optimal algorithm and a fast greedy algorithm. The former is based on a maximal-independent set on transitive graphs, while the latter focuses on potential slack estimation in a greedy manner. Applications to gate- and physical-level design problems are provided to show the effectiveness of potential slack in predicting the potential performance of digital circuits.
area algorithms maximal-independent set physical-level design delay and power optimization gate-level optimization potential performance prediction slack assignment synthesis of digital integrated circuits