parallelizing systemc kernel for fast hardware simulation on smp machines
SystemC is a system-level modeling language and simulation framework which facilitates design and verification of processor designs at different levels. Recently, SystemC is becoming a popular choice for designers of both System-On-Chip (SoC) and embedded processors, due to its adaptability at cycle as well as transaction levels, and ability to model concurrent processes. However, the single threaded simulation kernel inherent to SystemC, prevents it from utilizing the potential computing power of symmetric multiprocessing (SMP) machines to speed up hardware simulation. We present a parallel SystemC simulation kernel, which is implemented using parallel programming techniques and leverages the parallel execution capabilities of multi-core machines to speed up hardware simulation. We discuss the mechanism we use for mapping parallel SystemC modules into different cores. Finally we report the performance of the parallelized SystemC kernel using a linear pipelined performance model and a pipelined performance model tailored to exhibit the behavior of real world simulation. Our results demonstrate that the performanceimprovement obtained by using parallelized SystemC for simulation of the above models is significant and improves with increasing design complexity of the simulated design and the number of cores in the machine running the simulators.
systemc smp soc tlm core affinity osci