High-speed continuous-time subsampling bandpass Delta Sigma AD modulator architecture employing radio frequency DAC
This paper proposes a continuous-time bandpass Delta Sigma AD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.
continuous-time subsampling bandpass rf dac jitter delta sigma modulator