ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing
We propose Iterative Sequential GP (ISGP) optimization methodology for analog sizing. The methodology is quite fast yet accurate even at very high frequency. An efficient as well accurate modeling approach of phase margin is considered. ISGP considers layout aware and yields aware design centering for robust final design. ISGP algorithm is a potential solution for robust analog circuit sizing at sub-micron.
analog circuit sizing geometric programming (gp) device parameter performance parameter