A wide range, low power clock and data recovery scheme for RFID tags
An extremely low power clock and data recovery (CDR) circuit that covers a large input speed range is reported in this paper. The CDR recovers accurately-synchronized clock and data directly from the pulse position modulated (PPM) input, and the bit information embedded in time domain is converted into a voltage through charging integration on linear capacitors. The threshold voltage required for data recovery is accurately generated from the input bit period to produce the best noise margin for both bit 1 and bit 0. Furthermore, the current that is used for charge integration is dynamically set by a feedback loop to expand the input speed range. The prototype CDR circuit was implemented using a standard CMOS 0.25 mu m technology. Results show that the designed prototype can cover a large input speed range from 0.5 to 500 kbit/s, while only consumes 11-75 mu W of power, respectively.
clock and data recovery rfid low power design charge pump