Employed VeriLite simulation to improve SOC design and verification
This study employed the VeriLite PC-based FPGA platform to improve co-design and co-verification simulation for System-on-chip (SOC) design process in FPGA transactional level modeling. This VeriLite platform is a real-time simulations system. It provided SMIMS powerful SoftwareVeriComm, VeriInstrument and software developer's kit (SDK), offers an incredible performance and improvement in time-to-market. In this investigation, the main advantages of the system allow designers to use tools such as FPGA, Matlab, and Real-View SOC designers to perform. Users can import the input signals easily from PC into the user-designed circuit on the FPGA of VeriLite and export the output signals to PC for observation. A powerful method is proposed that speeds up the ESL design time with a precise result. VeriLite can be an intuitive and easy to use environment provides to access the functionality of HDL simulation acceleration, IP verification, and HW/SW co-verification. In this study, the propose method allows users to quickly develop a hardwaresoftware co-design/co-verification environment finally.  2010 Wiley Periodicals, Inc. Comput Appl Eng Educ 20: 374382, 2012
co-design co-verification system-on-chip transactional level modeling electronic system level