on testable multipliers for fixed-width data path architectures
The usage of multipliers in the increasingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output responses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to improve the overall testability of data paths. The methodology takes into account the truncated least significant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal performance degradation and area overhead.
design for testability high-level synthesis built-in self -test fixed-width architectures