yield modeling and beol fundamentals
The advent of deep submicron technologies with larger die sizes lends itself to an increase in fabrication cost. An appropriate yield forecast renders significant benefits in both time-to-market and manufacturing cost prediction. Yield forecasting is essential for the development of new products as it effectively shows if a design is feasible of meeting its cost objectives or not. In mature manufacturing processes, spot defects are the main detractors in the successful outcome of an IC. Their manifestation is as local disturbances of silicon layer structures. Spot defects are in essence random phenomena occurring on the wafer with certain stochastic size, spatial distribution, and frequency of occurrence per unit area. To verify the robustness of an IC it is necessary to extract its critical areas. The so-called critical areas are the places in the layout where defects can induce and IC faulty behavior such as a short or a break circuit. A figure of merit that measures the layouts robustness is obtained as the ratio of the total critical area to the layout area. This figure of merit is known as defect sensitivity. Knowledge of the designs defect sensitivity and the stochastic behavior of defects in the manufacturing line is used to ultimately predict yield. This tutorial reviews the basics on spot defect modeling, critical area modeling and its application in interconnect yield analysis.
yield model technologies size cost forecasting manufacturability predict developer product design meeting object process locality layer randomization spatial distributed robust extraction critic place layout behavior circuits measurement sensitive knowledge tutorial review applications interconnect analysis market timing