A High Performance ST-Box Based Unified AES Encryption/Decryption Architecture on FPGA
A single integrated and symmetric ST-Box structure followed by a single XOR Network is proposed for a unified AES encryptor & decryptor architecture. Switching capabilities of BRAM are explored to maximize the performance of system by proposing a duty-cycle based accessing technique. The Effectiveness of unified AES encryptor and decryptor core is then evaluated in both iterative and pipelined architectures. Our single-unit AES encryptor & decryptor cores on Virtex-7 FPGA result in highest design efficiencies.
aes fpga bram look-up-table unified encryptor & decryptor