Compact modeling of a PD SOI MESFET for wide temperature designs
A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the sourcesubstrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of ?180 to 150C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.
mesfets silicon-on-insulator spice model tom3 capacitance model verilog-a