Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares
In this paper, a synthesis method for combinational multiple-valued reversible logic (MVRL) circuits is proposed. This algorithm can use the don't care values in the synthesis process to obtain the optimal circuit with respect to quantum cost. The binary Fredkin gate is extended to the MVRL Fredkin gate, and its synthesis using 22 gates is proposed. Additionally, we have used the algorithm to design sequential MVRL circuits based on the state transition table. We propose three generalized designs for T, D, and JK flip flops (FF). The generalized r-valued T-FF is designed using 2r?3 controlled Cycle gates (r stands for radix). The r-valued D-FF is designed using the new version of the MVRL Fredkin gate. The ternary JK-FF, which performs nine distinct functions, is designed using only seven controlled Cycle gates. These FFs are the essential circuits to design MVRL state machines, and we synthesize the circuits with the minimal number of constant inputs and garbage outputs.
synthesis optimization multiple-valued reversible logic reversible logic sequential reversible logic