A traveling-wave-based waveform approximation technique for the timing verification of single transmission lines
Today's high-speed,very large scale integration interconnects are becoming inductively dominated (moderate Q) resistance-inductance-capacitance (RLC) transmission lines. The time-domain system responses of RLC interconnect lines driving load capacitances cannot be accurately represented by using a finite number of poles with exception for a particular case of RC-time-constant-dominant (low Q) RLC systems. In this paper, a new traveling-wave-based waveform approximation technique is presented. The method suggests that a steady-state traveling wave is approximately determined by a three-pole approximation technique. Then the time-domain response of the system can be accurately determined by using the traveling waves that are modeled by multiple reflections. The signal delay models of the RLC interconnect lines are derived as a closed form. The technique is verified by varying the source resistance, load impedance, and transmission line circuit model parameters of several RLC lines. The results show excellent agreement with HSPICE simulation results. That is, approximately 5% error in a 50% delay calculation can be achieved.
transmission line traveling wave signal delay signal integrity system pole vlsi interconnect