8 GHz 1V, CMOS quadrature downconverter for wireless applications
The design and implementation of an 8 GHz CMOS quadrature downconverter, achieving simultaneously low voltage supply operation and good linearity is presented in this paper. This is achieved by relaxing the inherent tradeoff between power conversion gain and linearity governing all active mixers and implementing a mixer using a new version of the bias-offset technique. The quadrature generator uses active inductors embodied in the LO buffer, and provides easy tuning by relaxing the coupling between amplitude and phase tuning of the outputs. It also provides reduced power consumption by eliminating the buffers located between the quadrature generator and the mixers. A prototype implemented in a 0.18 mu m CMOS technology occupies an area of 0.44 x 0.3 mm(2), operates from a 1V power supply and features an IIP3 of +3.5 dBm, an IIP2 of better than +48 dBm, an input compression point of -5.5 dBm, a power conversion gain of +6.5 dB for the mixers and a quadrature phase and amplitude matching of better than 1.5 degrees and 1 dB respectively over a bandwidth of 100 MHz after tuning. The overall power consumption of the quadrature downconverter is 25.8 mW.
cmos quadrature downconverter low voltage linearity bias-offset technique active inductor