multiple-process behavioral synthesis for mixed hardware-software systems
Abstract: Systems composed of microprocessors interacting with ASICs are necessarily multiple-process systems, since the controller in the microprocessor is separate from any controllers on the ASIC. For this reason, the design of such systems offers an opportunity to exploit not only hardware-software tradeoffs, but concurrency tradeoffs as well. The paper describes an automated iterative improvement technique for performing concurrency optimization and hardware-software tradeoffs simultaneously. Experimental results illustrate that addressing these two issues simultaneously enables us to identify a number of interesting cost/performance points that would not have been found otherwise.
multiple-process behavioral synthesis behavioral synthesis mixed hardware-software systems systems abstraction microprocessors asics controllers design exploit hardware-software tradeoffs concurrency tradeoffs concurrency paper automation iter performance concurrency optimization optimality experimentation cost point optimisation concurrency control high level synthesis software engineering multiprocessing systems software cost/performance ratio resource allocation microprocessor chips process cost-benefit analysis hardware logic design