A scalable thread scheduling co-processor based on data-flow principles
We present a data-flow based co-processor supporting the execution of fine-grain threads. We propose a minimalistic core ISA extension for data-flow threads. We propose a two-level hierarchical scheduling co-processor that implements the ISA extension. We show the scalability of the proposed system through a set of experimental results.
data-flow co-processor architecture many-core high-performance systems