High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
The markets today observe users having increasing demands on processing speed and energy consumption of their mobile devices. However, processing speed as well as functionality always comes at the expense of energy and thus limits, among other things, mobility and integration density. Recent technological developments allow for the simultaneous realization of slow, low-energy consuming as well as fast, high-energy consuming gates on the very same chip. In this respect, a particular design is an abstract optimization task for which this paper applies evolutionary algorithms. These algorithms are heuristic population-based search procedures that utilize certain mechanisms known from natural evolution. In comparison to currently available deterministic optimization procedures, the evolutionary algorithms achieved some energy savings of about 1040% on standard ISCAS test problems, while still yielding the highest processing speed possible.
evolutionary algorithms low-power leakage minimization dual-threshold cmos