high performance code compression architecture for the embedded arm/thumb processor
The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. Our proposed memory compression architecture has showed a further size reduction of 15\% to 20\% on the THUMB code. In this paper we propose to use a high-speed data lossless hardware decompressor to improve the timing performance of the architecture. We simulated the architecture on the SimpleScalar platform and show that for some applications, the time overheads are limited within 5\% of the original application.
performance code code compression compression architecture embedding processor use embedded systems systems standardization instruction cost memorialized size reduction paper data hardware timing simulation platform applications high-speed hardware decompressor high-performance