realizable rlck circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of extracted RLCK netlists by node elimination. The method is much faster than model order reduction techniques and hence is appropriate as a pre-processing step. The proposed method eliminates nodes with time constants below a user specified time constant. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a tradeoff between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER [13] in the absence of any inductances.
realizable crunching model order reduction simulation passive interconnect