High-linear, energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs
Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50MS/s SAR ADC is designed in 0.18um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16dB SNDR while consuming about 589?W from a 1.2-V supply.
successive approximation analog to digital converter (sar adc) high linear high speed