Multistage A2LVQ architecture and implementation for image compression
We implement two hardware architectures, i.e., A2 Lattice Vector Quantization (LVQ) and Multistage A2LVQ (MA2LVQ). Implementations are based on Field-Programmable Gate Array (FPGA). A multistage A2LVQ (MA2LVQ) architecture is implemented based on single A2LVQ.
a2 lattice vector quantization fpga vlsi architecture