a hierarchical approach for energy efficient application design using heterogeneous embedded systems
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application design using heterogeneous embedded systems. However, more choices during application design results in a large design space that must be traversed efficiently. In this paper, we propose a hierarchical methodology that integrates optimization heuristics, high-level performance estimators, and low-level simulators to enable efficient exploration of large design spaces. Our methodology is fast, robust against approximation errors due to high-level modeling, and can evaluate a much larger design space than an optimization heuristic only design space exploration technique. We have augmented MILAN, a model-based integrated simulation framework for embedded systems, to develop an environment to perform hierarchical design space exploration. Using our methodology for a beamforming application, we identify an energy-efficient mapping onto a heterogeneous embedded system while meeting a given latency constraint. We also demonstrate the use of our methodology in identifying an energy and latency efficient heterogeneous embedded system based on user-specified performance requirements for a personnel detection algorithm from a set of devices that includes FPGAs, DSPs, and traditional processors.
energy efficiency heterogeneous embedded systems performance estimation design space exploration