Architecture of an application-specific processor for real-time implementation of H.264/AVC sub-pixel interpolation
This paper presents an efficient VLSI architecture for fast implementation of sub-pixel interpolation of H.264/AVC. Several optimization techniques at different design levels, such as parallel processing, vector register, pipeline architecture, and in-place computation, are utilized to reduce the number of memory access and accelerate the interpolation computations. The proposed application-specific processor can meet the real-time constraint of the sub-pixel interpolation algorithm for the 16:9 video format (4,6902,304) at 30 frames per second (fps) at 100MHz clock rate.
application-specific processor h.264 vlsi motion estimation video compression