Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
Selecting a clock period is an essential step in implementing hardware from behavioral descriptions. Current methods either estimate the clock prior to scheduling or involve exhaustive runs of the high-level synthesis tools to obtain a globally optimum clock period. Further, the potential benefits of allowing the use of multiple clocks for performance optimization has not been investigated. This paper presents a clock selection method that works simultaneously with synthesis by selecting a clock from an optimal clock set. The synthesis is iterative and is optimized by evolutionary techniques. The method is very flexible and can accommodate a large set of potentially optimal clocks. We also present multirate clock synthesis with path-dependent clock selection where different paths in a control data flow graph (CDFG) are optimized with different clock periods. The results shown prove the method's effectiveness.
clocks genetic algorithms scheduling design automation high-level synthesis (hls) integrated circuit design very large scale integration (vlsi)