Performance optimization by interacting netlist transformations and placement
Performance optimization has become one of the most important problems at all design stages of today's highly integrated circuits. During logic synthesis performance optimization is guided by only rough net delay models. Therefore, net delays cannot be optimized effectively during Logic synthesis. As device dimensions are shrinking in deep submicron designs, net delays tend to dominate performance. Consequently, the netlist generated during logic synthesis is suboptimal as only rough approximations for the most dominant part of the path delays are available. In this paper, we present a placement approach that exploits the optimization potential of netlist transformations during placement. As netlist transformations are integrated into the placement process, they can be guided by more accurate net delay models. In contrast to previous approaches that apply netlist transformations during placement, our approach is not restricted to local transformations like buffer insertion and gate resizing, but exploits global dependencies between the signals in a circuit. On the average, the maximum path delay is reduced by 11% compared to the initial performance-driven placement of the original netlist, Furthermore, the experiments show that applying the same netlist transformation procedure before placement yields no improvement as net delays cannot be considered due to missing layout information.
performance optimization placement interconnect post-layout resynthesis