Architecture and instruction set design of an ATM network processor
Microprocessor architectures are diversifying to support niche market requirements, with growing emphasis for performance delivery on the architectural design rather than the silicon implementation. This paper outlines the architectural design, programmer's model and instruction set of a microprocessor, which adopts a novel approach to network data. In particular, Asynchronous Transfer Mode (ATM) cells are delivered to a special FIFO cache memory, located at the heart of the processor. Cell input and output is conducted at wire speed using dedicated streaming input and output hardware. Special read and write instructions then allow the cell payloads to be accessed directly, and transferred from/to the register file. Multimedia applications have previously been identified as an important market for such a network centric architecture. Therefore the paper ends with a demonstration of the power of some key instructions. A motion estimation kernel from the MPEG standard is used to exercise the architecture and instruction set. Execution speed is shown to be comparable to today's processors, using only a 400 MHz clock for a full search. The minimally resourced design is therefore suited to embedded network applications from both economic and performance standpoints.
asynchronous transfer mode network processor architecture