CASCADE: A standard supercell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large-scale integrated circuits
In this paper, CASCADE, a standard supercell-based design methodology, its supporting automated design flow, and associated design tools, are presented for 3-D implementations of a class of interconnect-heavy application-specific very large-scale integrated circuits. In CASCADE, a system is first partitioned and synthesized using standard 2-D design tools to a set of supercells with the same height and varying widths. With this, the 3-D design is reduced to 3-D supercell placement and 3-D-via assignment. A congestion-driven simulated-annealing method is used to find a 3-D placement of supercells to minimize the total wire length, the longest wire length, and the number of 3-D vias and routing density. To efficiently estimate the routing density of a 3-D grid space within the optimization loop, a simple probabilistic congestion model with an incremental congestion computation has been developed. Once the supercell placement is fixed, the problem of assigning 3-D vias to accomplish minimal 2-D routing densities and uniform 3-D-via distribution is solved by an efficient min-cost-max-flow method. The proposed methods have been implemented and tested on a set of ISPD98 circuit benchmarks. Experimental results have shown that the proposed congestion-driven 3-D supercell placement and flow-based 3-D-via-assignment tools have yielded satisfactory placement with small-area, low-congestion, short-wire-length, few, and uniformly distributed 3-D vias. Furthermore, an excellent correlation between routing-density estimation by our model and the actual routing performed by a commercial router has been observed. We have applied the proposed 3-D design methodology, tools, and flows to tape out an over 4-million-gate low-density parity-check decoder in a three-tier 0.18-mu m fully depleted silicon-on-insulator 3-D CMOS process manufactured by MIT Lincoln Laboratory. The postlayout simulation of this DRC-clean layout design showed an about ten times improvement on the power-delay-area product compared to a 2-D implementation in the same process.
congestion-driven placement 3-d-via assignment interconnect-heavy integrated circuits low-density parity-check (ldpc) decoder three-dimensional integrated circuits (3-d-ics)