on tests to detect via opens in digital cmos circuits
We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.
open defects constrained stuck-at tests dft test generation