High performance level restoration circuits
Three high performance level restoration circuits are proposed, which outperform the existing level restoration circuits with cross-coupled PMOS, in terms of power dissipation and delay. The first configuration employs a back-bias scheme in order to eliminate the stand-by leakage caused by the low-swing input. The second one adopts a bootstrapping technique, in order to restore the low-swing signal, without dc power consumption. Finally, a level restoration circuit is proposed, based on the generation of a narrow zero-pulse, for properly controlling the output PMOS device. The presented level restoration circuits can be implemented in standard CMOS technologies. By simulating the proposed circuits on a low-swing interconnect scheme, a 60% power savings have been observed over the conventional full-swing case.
level restoration circuits back-bias low-swing bootstrapping low power