A folding technique for reducing circuit complexity of flash ADC decoders
The performance of a decoder is one of the factors that dominate the performance of a flash ADC. In this paper a folding technique is proposed to reduce the decoder circuit complexity. After folding, a k-bit decoder is replaced with two sub-decoders. The decoding of the upper k/2 bits and the lower k/2 bits can be accomplished respectively. Consequently, the number of inputs to the decoder is reduced to the square root of the original. Analytic results show that for different decoder structures, more than 17% of hardware and 13% of time delay can be saved. Moreover, the tolerance of bubble induced errors is enhanced. A 6-bit flash ADC has been implemented in 0.18-mu m CMOS that occupies 0.37 mm x 0.35 mm active area. Simulations show that the figure-of-merit number is as low as 1.03 pJ/convsetp at 1G Sample/s and the maximum bubble induced error is limited to the number of bubbles.
decoding analog system fault tolerance high-speed integrated circuit analog-digital conversion