Acceleration of the Discrete Element Method (DEM) on a reconfigurable co-processor
The Discrete Element Method (DEM) is a numerical method devised to model the behaviour of particle assemblies. However in order to simulate entire engineering structures, which may involve millions of particles, the computing power has to increase as the DEM is computationally extremely expensive. A dedicated hardware architecture, implemented on a reconfigurable computing platform based on a Field Programmable Gate Array (FPGA) is presented in this paper. The main computational tasks are fully overlapped using domain decomposition techniques, and the lower level parallelism is also exploited by using concurrent arithmetic operations. A speedup of a factor of 30 could be observed compared to an optimised software simulator running on a 1 GHz Pentium III PC with 1.3 Gbytes of RAM for 2-D particles assemblies ranging from 25,000 to 200,000 particles. The scalability of this design was tested on a multi-FPGA system, allowing the complete overlap of communication and computation for two FPGA boards working in parallel, achieving a speedup factor of almost 60.
discrete element method (dem) reconfigurable computing field programmable gate arrays (fpgas) hardware acceleration