reducing the complexity of the issue logic
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs that are much simpler than the traditional scheme while they retain most of its ability to exploit ILP. These alternative schemes are based on the observation that most values produced by a program are used by very few instructions, and the latencies of most operation are deterministic.
complexity logic scheduling superscalar processor paper design scheme exploit ilp observability values instruction complexity-effective design power out-of-order issue instruction issue logic wide-issue superscalar