logic simulation on massively parallel architectures
This work examines the mapping of logic simulation onto massively parallel computer architectures. We discuss alternative communication primitives for a massively parallel instruction set architecture and the impact of the choice of communication primitives on logic simulation. We have developed compilation tools to automatically map the simulation of an MOS transistor circuit onto a massively parallel computer. We analyze the efficiency of this mapping as a function of the available communication primitives. The compilation process is illustrated by describing our pilot implementation on a 32k processor Connection Machine.
logic simulation parallel parallel architecture architecture map parallel computation communication instruction compilation tools circuits efficiency functional process implementation processor connection