nanometer mosfet effects on the minimum-energy point of 45nm subthreshold logic
In this paper, we observe that minimum energy E min of subthreshold logic dramatically increases when reaching 45nm node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage and DIBL. We then investigate the new impact of MOSFET parameters on E min in nanometer technologies. We finally propose an optimum MOSFET selection intended for subthreshold circuit designers, which favors low- V t mid- L g devices in standard 45nm GP technology. The use of such optimum MOSFETs yields 35\% E min reduction for a benchmark multiplier with good speed performances and negligible area overhead.
subthreshold logic variability gate leakage cmos digital integrated circuits short-channel effects ultra-low power