code transformations to improve memory parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in removing memory stall time than CPU time, making the memory system a greater bottleneck in ILP-based systems than previous-generation systems. These deficiencies arise largely because applications present limited opportunities for an out-of-order issue processor to overlap multiple read misses, the dominant source of memory stalls. This work proposes code transformations to increase parallelism in the memory system by overlapping multiple read misses within the same instruction window, while preserving cache locality. We present an analysis and transformation framework suitable for compiler implementation. Our simulation experiments show substantial increases in memory parallelism, leading to execution time reductions averaging 23\% in a multiprocessor and 30\% in a uniprocessor. We see similar benefits on a Convex Exemplar.
code memorialized parallel processor exploit instruction-level parallelism instruction ilp effect timing memory system systems applications read windows cache locality analysis compilation implementation simulation experience reduction multiprocessor  framework  order generation