enhancing application efficiency by packing instructions into registers
Instruction packing is a combination architectural/compiler technique that allows for reduced energy consumption, code size, and execution time. Frequently occurring instructions are placed into a small instruction register file (IRF), which requires significantly less energy to access than an L1 instruction cache. Multiple instruction register references can be placed in a single packed instruction, leading to reduced instruction cache accesses and decreased static code size. Execution time can be slightly improved due to the reduced working set size, resulting in fewer L1 IC misses. We will present the design and evaluation of the instruction register file and its associated compiler tools and show its effect on energy consumption, code size, and execution time. Instruction packing with an IRF is also shown to be complementary to several other popular fetch energy reduction techniques including a loop buffer and a small L0/filter cache. Finally, an IRF can be used to supply additional instructions to an aggressive pipeline backend.
compilers instruction register file computer architectures