Scalability implications of software-implemented coherence
It has been argued many times that the cost-effectiveness of hardwired cache coherence protocols is questionable. Several proposals have been developed to migrate the protocol execution from hardwired controllers to software handlers executing on each processor. An important issue is the scalability of such an approach with respect to the number of processors, the communication speed, and the speed of processors. As the speed gap between processor and DRAM technology widens, the relative overhead of software protocols execution oil the processor tends to decrease over time. In this paper, we compare a system with software-implemented coherence to an idealized all-hardware system in Which the execution of the protocol actions by hardware controllers takes zero time. Based on our Simulation results we derive some simple analytical models which can explain Most issues related to scalability. These models also enable us to explore whether software-implemented coherence protocols can really take advantage of shorter development cycle and time-to-market.
distributed shared-memory multiprocessor systems coma software cache coherence execution-driven simulation