A memory efficient parallel layered QC-LDPC decoder for CMMB systems
This paper presents a memory efficient architecture of layered decoder for the dual-rate LDPC codes in the China Multimedia Mobile Broadcasting (CMMB) system. An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced. At the same time, the memory structure keeps the one cycle one layer access timing schedule to achieve high decoding throughput. Furthermore, the early termination strategy is employed to further increase the throughput; a non-uniform quantization scheme and an area efficient calculation module are developed to further improve the memory efficiency and hardware resource efficiency, respectively. By using SMIC 130nm 1P7M CMOS process, the decoder is implemented and the core area is 5.29mm2. The total memory bits consumption is only 130.5K which consumes 2.53mm2 memory area.
memory efficient china multimedia mobile broadcasting (cmmb) system parallel layered ldpc decoding