soft error rate computation in early design stages using boolean satisfiability
Soft errors, due to cosmic radiations, are the major reliability barriers for VLSI designs. To meet reliability constraints in a costeffective way, it is critical to assess soft error reliability parameters in early design stages. In this paper, we present a framework to accurately obtain soft error rate (SER) for high-level (behavioral) descriptions (Verilog or VHDL). We transform the SER problem into an equivalent Boolean satisfiability (SAT) problem and use state-of-the-art SAT-solvers to obtain SER. We have developed an automated flow to convert high-level hardware descriptions into SAT formulations for exact SER computation. We compare our technique to traditional fault simulation techniques. The experimental results show that fault simulations with orders of magnitude run time overhead still result in significantly inaccurate underestimation of SER values. We applied the technique on the largest ISCAS benchmark circuits and found out that it scales well.
soft error reliability modeling hardware description language