Design strategies for class A CMOS CCIIS
In this paper, solutions for class A CCIIs are discussed and design arrangements are suggested to achieve improved performance in terms of gain accuracy, impedance level, offset and linearity. The noise performance is also evaluated and compared for the various solutions. Finally, a novel CCII is proposed which is based on an innovative arrangement of the biasing. The circuit provides a THD 15 dB lower than previous solutions and has a linearity feature which has low sensitive to the mismatch of the parameters beta and V-T.
ccii analog circuits current-mode