Implementation of low power adder design and analysis based on power reduction technique
This paper presents improved design of low power adder and analysis based on power reduction technique. Using example of adder and multiplier, low leakage power CMOS digital circuit is verified by respective benchmark suite for each example and compared with conventional design of adder and multiplier. Using various supply voltages and fault coverage as parameters, reduction in power was measured. Simulation result and validation by example foresee implementation of proposed design as an essential part of high performance circuit design. The proposed technique offer power reduction up to 20.2% and fault coverage of 99.65%.
low power adder power reduction circuit design