Optimal Design of Low Power CMOS Power Amplifier Using Particle Swarm Optimization Technique
A low voltage 2.4GHz CMOS power amplifier for wireless personal area network (WPAN) applications is presented in TSMC 0.13 \(\upmu \)m CMOS process. It consists of driver and power amplifier stages which are connected in current reuse structure. The driver amplifier has push pull inverter configuration. The power amplifier is the common source amplifier. These two stages are biased in class AB mode. For optimizing out-of-band emissions, the proposed power amplifier is linearized by RF predistortion technique. For efficient power amplifier, the design parameters are needed to be optimized using particle swarm optimization technique. The optimized power amplifier achieves 0 dBm output power, 34.06% PAE, 18dB power gain at 2.4GHz frequency. It consumes 2.95mW power at a supply voltage of 1.2V.
cmos power amplifier predistortion pae