A current-mode folding/interpolating CMOS A/D converter with multiplied folding amplifiers
A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 mum n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of +/-0.5LSB, an integral nonlinearity (INL) of +/-1.0LSB, 20 Ms/s of the data conversion rate, and the power dissipation of 180 mW with a power supply of 5 V.
current-mode folding/interpolating cmos multiplied folding amplifier adc