A 95 mW MPEG2 MP@HL motion estimation processor core for portable high-resolution video application
This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 1920 x 1080 @ 30 fps resolution video. The search range is +/- 128 x +/- 64 pixels. The ME core integrates 2.25 M transistors in 3.1 mm x 3.1 mm using 0.18-micron technology.
mpeg2 motion estimation low power hdtv ip