Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2
We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO2 dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (?VFB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The currentvoltage (IV) curves exhibited two transient peaks at voltages corresponding to the two steps in ?VFB vs. Vgate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.
si-nanocrystals si-nanocrystal memories non-volatile memories electrical characterization