Energy-efficient skewed static logic with dual Vt: Design and synthesis
In this paper, we describe skewed static logic (S-2 L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S-2 L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S-2 L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-mum CMOS technology and verified hat S-2 L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S-2 L with dual Vt reduces delay by 43% and energy-delay product by 31% for IN power supply over conventional CMOS circuit. Synthesis algorithm for S-2 L is developed and the experimental results show S-2 L consumes 23% less power than MS CMOS with minor increase in delay.
dual vt accelerator adder synthesis algorithm low power skewed logic