A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-mum CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot be applied. To reduce the propagation delays of the S-Box, the slowest function block, we developed a special circuit architecture that we call twisted-binary decision diagram (BDD), where the fanout of signals is distributed in the S-Box circuit. Our S-Box. is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.
s-box advanced encryption standard (aes) asic implementation binary decision diagram (bdd) cryptography high-speed hardware