Steiner tree optimization for buffers, blockages, and bays
Timing optimization is a critical component of deep submicrometer design and buffer insertion is an essential technique for achieving timing closure, This work studies buffer insertion under the constraint that the buffers either: 1) avoid blockages or 2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this application and present a maze-routing-based heuristic that either avoids blockages or finds buffer bays. We show that the combination of our Steiner-tree optimization with leading-edge buffer-insertion techniques leads to effective solutions on industry designs.
deep submicrometer buffer insertion interconnect performance optimization physical design routing vlsi