A selective CMP process for stacked low-k CVD oxide films
A chemical mechanical polishing process for a stacked low-k dielectric material, which is suitable for inter-metal dielectric applications, has been developed. The dielectric is deposited by CVD and composed of a methyl-doped silicon oxide (i.e., low-k Flowfill) embedded between thin SiO2 layers. A new CMP parameter is introduced, which is the removal rate selectivity between two different kinds of materials. We were able to adjust the selectivity between cap and low-k Flowfill layer in a range between 3:1 and 1:5 by tuning the slurry mixture. Different test structures were used to investigate the effect of the removal rate selectivity on the planarisation efficiency of the CMP process. A higher removal rate of the low-k Flowfill layer in comparison to that of the cap layer results in a significant increase of the planarisation length and a reduction of the overpolish needed to achieve planarity.
cmp low-k dielectrics flowfill removal rate selectivity planarisation