Analysis of op-amp phase margin impact on SC ?? modulator performance
The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (???) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35?m CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in ??? behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase.
operational amplifier (op-amp) sigma-delta modulator switched-capacitor (sc) integrator behavioural modelling transient response settling time