Reduction of Area per Good Die for SoC Memory Built-In Self-Test
To reduce the manufacturing cost of SoCs with many em bedded SRAMs we propose a scheme to reduce the area per good die for the SoC memory built in self test (MBIST) We first propose BIST hard ware overhead reduction by application of an encoder based comparator For the repair of a faulty SRAM module with 2 D redundancy we propose spare assignement algorithm Based on an existing range cheking first algorithm (RCFA) we propose assign all row RCFA (A RCFA) which as sign unused spare rows to faulty ones in order to suppress the degradation of repair rate due to compressed fail location information output from the encoder based comparator Then considering that an SoC has many SRAM modules we propose a heuristic algorithm based on iterative improvement algorithm (IIA) which determines whether each SRAM should have a spare row or not in order to minimize area per a good die Experimental results on practical scale benchmark SoCs with more than 1 000 SRAM modules indicate that encoder based comparators reduce hardware overhead by about 50% compared to traditional ones and that combining the IIA based algorithm for determining redundancy architecture with the encoder based comparator effectively reduces the area per good die
memory bist bisr embedded sram area per good die iterative improvement algorithm