Gate oxide leakage and delay tradeoffs for dual-T-ox circuits
Gate oxide tunneling current (I-gate) is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness (T-ox) is below 15 angstrom. Increasing the value of T-ox reduces the leakage at the expense of increased delay, and hence a practical tradeoff between delay and leakage can be achieved by assigning one of two permissible T-ox values to each transistor. In this paper, we propose an algorithm for dual-T-ox assignment to optimize the total leakage power under delay constraints and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T-ox, our approach achieves an average leakage reduction of 86% under 100 nm models and 81% under 70 mn models. We also propose a transistor and pin reordering technique that has minimal layout impact to further reduce the total leakage current up to 12% and I-gate up to 27% without incurring any delay penalty.
subthreshold leakage leakage power pin reordering dual oxide thicknesses gate leakage power delay tradeoffs technology scaling transistor reordering