An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction
To achieve aggressive standby power reduction for static random access memory (SRAM), we have previously proposed a closed-loop V(DD) scaling system with canary replicas that can track global variations. In this paper, we propose several techniques to enhance the efficiency of this system for more advanced technologies. Adding dummy cells around the canary cell improves the tracking of systematic variations. A new canary circuit avoids the possibility that a canary cell may never fail because it resets into its more stable data pattern. A built-in self-test (BIST) block incorporates self-calibration of SRAM minimum standby V(DD) and the initial failure threshold due to intrinsic mismatch. Measurements from a new 45 nm test chip further demonstrate the function of the canary cells in smaller technology and show that adding dummy cells reduces the variation of the canary cell.
standby power static random access memory (sram) variation built-in self test (bist) data retention voltage (drv)