Clock jitter impact on the performance of general charge sampling amplifiers
In this paper we present the detailed performance analysis of general charge sampling amplifiers (CSAs) due to clock jitter impact. A simple analytical model for quick estimation of the signal-to-noise ratio by considering clock jitter alone as a noise source is proposed for a general CSA. The proposed analytical model is compared with a previously published more complex model and also with the well known voltage sampling. Simulation results showing the performance due to clock jitter impact of CSAs are also presented here to confirm the proposed analytical model. The potential advantages of clock jitter tolerances in charge sampling are discussed in detail.
clock jitter charge sampling charge sampling amplifiers sampling jitter analysis snr