A 960?W 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme
This paper presents a low-power 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a novel energy-efficient capacitor-switching scheme. Compared to the conventional scheme, the proposed split-capacitor Vcm-based capacitor-switching scheme can reduce the capacitor-switching energy by about 92% with better monotonicity. Meanwhile, full-custom SAR logic and registers, variable-delay self-timing cell and dynamic comparator with proposed two-segment DC offset correction scheme are also implemented to improve the conversion speed and accuracy requirements. The prototype was fabricated in 65-nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2dB, while consuming 960?W from 1.2V supply voltage. The figure of merit (FoM) is 36.8fJ/conversion-step and the total active area is only 220220?m2.
successive approximation register (sar) analog-to-digital converter (adc) split-capacitor vcm-based cap-switching scheme comparator dc offset correction asynchronous self-timing