A reconfigurable processor based on FPGAs for pattern recognition, processing, analysis and synthesis of images1
FPGA chips, with their large capacity memory and potential for reconfigurability, have opened new possibilities in the analysis, recognition and processing of images. This article describes research results in these areas and the architecture of a dynamic programmable processor (PSWO). This processor was designed around FPGAs, which provided an experimental basis for implementing procedures and executing algorithms used in the analysis and synthesis of images. The results of tests and simulations conducted on a large Power Challenge Calculation Server were further verified through implementation in an actual PSWO. An increase in speed of several tens to several hundred times was achieved in the test cases. Finally, the article outlines the effects of applying FPGAs in analysis, synthesis, recognition and processing of images. It describes the genesis and architecture of a systolic processor designed to use the reprogramming and reconfigurability features of FPGAs as well as the design of a so-called PSWO intended for the execution of algorithms which permit intensive parallel processing of calculations. Also discussed are the application of PSWOs to the field segmentation split-and-merge method of image analysis and the effectiveness and prospects for further development of the PSWO.
pattern recognition image analysis image processing fpga-processor systolic array