two-level partitioning of image processing algorithms for the parallel map-oriented machine
The partitioning of image processing algorithms with a novel hardware/software co-design framework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Map-oriented Machine) is used as universal accelerator based on a reconfigurable datapath hardware for speeding-up image processing applications. CoDe-X accepts C-programs and carries out both, the profiling-driven host/accelerator partitioning for performance optimization, and the resource-driven sequential/structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable datapath resources.
partition image processing algorithm parallel hardware software code paper acceleration reconfigurability applications performance optimization optimality resource structure program  framework  architecture design source-code profiles