A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms
The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used toots in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.
inverse discrete cosine transform discrete cosine transform systolic array application specific processor architecture image compression serial-parallel processor