finite state machine decomposition for low power
Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clock-gating technique based on finite state machine (FSM) decomposition. We compute two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. This way we will have a small amount of logic that is active most of the time, during which is disabling a much larger circuit, the other sub-FSM. We provide a set of experimental results that show that power consumption can be substantially reduced, in some cases up to 80\%.
finite state machine decomposition low power clock effect reduction switch activation logic circuits paper computation functional transit disabilities search cluster probability use timing experimentation power consumption system-on-chip test intellectual property test testing embedded core clock gating