Ultra low power phase detector and phase-locked loop designs and their application as a receiver
In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48?W power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13?m CMOS technology. Dissipating 0.26mW from a 1.2V supply, the fabricated PLL can track signals between 1.62 and 2.49GHz. For receiver applications, the energy per bit of the receiver is only 0.26nJ making it attractive for low power applications including wireless sensor networks.
phase detector phase-locked loops (pll) low power mixer ring oscillator vco frequency-modulation (fm) receiver frequency-shift keying (fsk)