Resource allocation for coarse-grain FPGA development
The development of domain-specialized reconfigurable devices, and even the nature of domains themselves, has been largely unexplored. In part this is because the same architectural improvements that allow domain-specialized field programmable gate arrays (FPGAs) to outperform conventional reconfigurable devices,also significantly change the design problem. The migration from completely generic lookup tables (LUTs) and highly connected routing fabrics to specialized coarse-grain functional units and very structured communication resources presents designers with the problem of how to best customize the system based upon anticipated usage. In this paper, the authors establish the nature of many of these problems and illustrate the difficulties of determining the appropriate number and ratio of functional units considering the demands of a diverse domain. The authors present three algorithms that Attempt to balance the hardware needs of the domain while considering design constraints such as the performance and area of the system.
field programmable gate arrays design automation reconfigurable architectures system on a chip