AN ENERGY EFFICIENT HALF-STATIC CLOCK-GATING D-TYPE FLIP-FLOP
This paper presents a new design of half-static clock-gating D-type flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock-gating circuitry. The new circuit has a very compact size, and can achieve low-power dissipation, especially in the case of low data activity. SPICE simulation results of the proposed DFF implemented with 0.18 mu m CMOS technology are presented, which shows that the overall performance of the present design is better than most of the DFFs reported in literatures.
flip-flop d flip-flop half-static flip-flop