cache coherence support for non-shared bus architecture on heterogeneous mpsocs
We propose two novel integration techniques ? bypass and bookkeeping ?in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.
cache coherence heterogeneous mpsoc real-time and embedded systems inter-processor communication