On the characterization of the trapped charge in FG-CMOS inverters
In this work, an experimental comparison between measured FG CMOS inverters using the quasi-floating gate (QFG) and layout-based (L-b) techniques for charge removal in the Floating-gate (FG) and simulations through PSpice is presented. The experiment was developed through the measurements of 40 different IC's with a total of 200 FG and QFG CMOS inverters characterized on AMI C5FN 0.5 mu m technology. The data obtained shows that the layout-based technique reduces the initial charge present at the FG, but presents a very small residual charge. Nevertheless, the offset associated to the charge follows a normal distribution and is predictable. Comparison between measured QFG inverters and simulations shows that the high resistance parasitic diode must be modeled accurately for a proper simulation.
neuron-mos vmos floating-gate transistors