On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
A new framework for generating test sets with high test efficiency for path delay faults (PDFs) is presented. The proposed method is based on a data structure that can implicitly represent all sensitizable PDFs in a circuit, along with all their corresponding tests. A path and test implicit method to construct such a data structure, for various path sensitization types, is presented. It uses zero-suppressed binary decision diagram (ZBDD) representations of irredundant sum-of-products (ISOPs), and requires only a polynomial number of standard ZBDD operations. Consequently, an ATPG algorithm that can exploit the properties of the proposed structure to derive tests with maximal test efficiency is presented. The obtained experimental results on the ISCAS85 and enhanced full-scanned version of the ISCAS89 benchmarks demonstrate that the proposed framework is scalable in terms of test efficiency and can generate compact test sets for critical PDFs.
critical path delay faults path delay faults zero-suppressed binary decision diagram irredundant sum-of-products delay testing compact test generation