SAD computation based on online arithmetic for motion estimation
Block-based motion estimation is one of the critical tasks in today's video compression standards such as H.26x, MPEG-1, -2 and -4. Most of the block-based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference blocks. In this paper, an field-programmable gate-array (FPGA) design is proposed for rapidly computing the minimum SAD. Two goals are achieved due to the use of online arithmetic (OLA): it is possible to implement a full 1616 macroblock SAD in a single FPGA device; and it allows us to speed up computation by early termination of the SAD calculation when the candidate involved is bigger than the current reference SAD. Reconfigurable devices enable us to change 88 or 1616pixels per block quickly and easily. For a 1616 SAD unit 1945 look-up tables (LUTs) are required at 425MHz. A comparison with other related works is provided.
online arithmetic motion estimation sum of absolute differences fpga