COLLAPSING THE HIERARCHY OF PARALLEL COMPUTATIONAL MODELS
We investigate the computational power of parallel models with directed reconfigurable buses and with shared memory. Based on feasibility considerations present in the literature, we split these models into "heavyweight" (directed reconfigurable buses, the Combining PRAM, and the BSR) and "lightweight" (all the other PRAMs) and then find that the heavyweight class is strictly more powerful than the lightweight class, as expected. On the other hand, we contradict the long held belief that the heavyweight models form a hierarchy, showing that all of them are identical in computational power with each other. We start the process by showing that the Collision write conflict resolution rule is universal on models with reconfigurable buses ( in the sense that complex conflict resolution rules such as Priority and Combining can be simulated with constant overhead by Collision).
parallel computation real-time computation reconfigurable multiple bus machine reconfigurable network parallel random access machine broadcast with selective reduction concurrent-read concurrent-write conflict resolution rules graph accessibility problem