Interconnection optimization in data path allocation using minimal cost maximal flow algorithm
In most designs of digital systems, as the area taken up by multiplexers and wires outweighs that of functional modules and registers, the interconnection optimization in high-level synthesis becomes very significant. In this paper, a layout area estimation model based on bit-sliced standard cell design style is presented. With the model, a data path allocation system was developed to optimize the interconnection. Both the module allocation problem and the register allocation problem are modeled as the minimal cost maximal flow problem in a network. Experimental results show that the layout area estimation model is suitable to guide the design decisions during the allocation and good designs with optimal interconnections can be produced by the system.
interconnection optimization data path allocation high-level synthesis layout area estimation flow network