An RTL design-space exploration method for high-level applications
In this paper. we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performanced riven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration flow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.
rtl at-curve design exploration high-level synthesis design space