Optimum wire sizing of RLC interconnect with repeaters
Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in determining the optimum number and size of the repeaters driving a line. The optimum repeater system uses uniform repeater insertion in order to achieve the minimum propagation delay. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by the optimum repeater system. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low-power design objectives. A reduction in power of 65% and delay of 97% is achieved for an example repeater system. The Power-Delay-Area-Product (PDAP) criterion is introduced as an efficient technique to size the interconnect within a repeater system. A reduction in buffer area of 67% and interconnect area of 46% is achieved based on the PDAP.
wire sizing repeater insertion propagation delay transient power dissipation power delay product on-chip inductance