energy-efficient code generation for dsp56000 family (poster session)
This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces the dependencies between instructions, a register allocation algorithm that spills variables based on their packability , and an address code generation algorithm that minimizes the number of additional instructions. The size of the code generated by this procedure is on the average 45\% (25\%) smaller than that generated by Motorola's g56K (SPAM).
code generation low power