A programmable spike-timing based circuit block for reconfigurable neuromorphic computing
A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 10 event blocks is fabricated using Austria Microsystems 0.35 ? m CMOS technology to demonstrate the functionality of the circuits in silicon.
reconfigurable neuromorphic arrays spiking neurons spike-timing-dependent plasticity on-chip learning