A processor-sharing model for input-buffered ATM-switches in a correlated traffic environment
We present a model to analyze the performance of a class of input-buffered ATM-switches when the offered traffic is correlated. The correlation not only pertains to the arrival instants of consecutive cells, but to their destinations too, and is modeled by a message train-arrival process. The switches under consideration use a pure random resolution scheme for the output-port contention. This contention is modeled through the well-known virtual-queue concept. For correlated traffic, the random scheme results in a discrete-time processor-sharing discipline inside these virtual queues. The analysis of this discipline presented here is based on generating functions and yields straightforward algorithms to calculate various measures of interest, as illustrated by numerical examples. The main conclusion drawn is that under realistic circumstancesno exact prior knowledge of the extent of the correlationthe random resolution scheme can provide a fair compromise between design complexity, robustness and performance.
processor-sharing atm-switches round-robin