interconnect and communication synthesis for distributed register-file microarchitecture
Distributed register-file microarchitecture (DRFM) which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data-routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on-chip memory or register-file IP blocks. In comparison with the discrete-register based architecture, DRFM offers a higher degree of opportunity of reducing the cost of global (inter-island) connections by confining as many the computations to the inside of the islands as possible. Consequently, for DRFM architecture, two important problems to be solved effectively in high-level synthesis are: (problem 1) scheduling and resource binding for minimizing inter-island connections, and (problem 2) data transfer (i.e., communication) scheduling through the inter-island connections for minimizing the access conflicts among the data transfers. This work proposes novel solutions to the two problems. Specifically, for problem 1 previous work solves it in two separate steps: (i) scheduling and (ii) then determining the inter-island connections by resource binding to islands. However, in our algorithm called DFRM-int, we place primary importance on the cost of interconnections. Consequently, we minimize the cost of interconnections first to fully exploit the effects of scheduling on interconnect and then to schedule the operations later . For problem 2, previous work tries to solve the access conflicts by forwarding data directly to the destination island. However, in our algorithm called DFRM-com, we devise an efficient technique of exploring an extensive design space of data forwarding indirectly as well as directly to find a near-optimal solution . By applying our proposed synthesis approach DFRM-int+DFRM-com we are able to reduce the inter-island connections by 18.1\% more, compared to that by the DRFM approach in [4], even completely eliminating register-file access conflicts, which could never been resolved by [4], without any latency increase.
communication synthesis distributed register file