timed petri nets and preliminary performance evaluation
It is shown that the behavior of a certain class of timed Petri nets can be represented by a finite labeled directed graph in which the labels describe times and probabilities of transitions between vertices of the graph. Further analysis of such a graph can be done by techniques known for Markov chains. The method is applied to evaluation of some performance indices for two simple processor architectures. The timed Petri nets modeling the processors are shown and the resulting performance indices are compared. Some other architectures are discussed shortly.
performance performance evaluation evaluation behavior class label directed graph graph probability transit analysis method processor architecture model