An 8.38 fJ/conversion-step 0.6 V 8-b 4.35 MS/s asynchronous SAR ADC in 65 nm CMOS
An asynchronous reference-free successive-approximation register analog-to-digital converter (ADC) in 65 nm CMOS is presented. In order to fit for low supply voltage design in advanced digital sub-nanometer process, a differential time-domain comparator is implemented. It tracks process variation with unit transistor of input device as well as charging capacitor, and enables differential configuration by using RS trigger instead of D-flip-flop. The proposed architecture is digital circuits heavily involved; therefore it will benefit from technology scaling. The power dissipation is further improved by means of asynchronous architecture, which is adjusted for low supply voltage operation, as well as reference-free configuration. The prototype ADC is fabricated in SMIC 65 nm digital CMOS process. It has signal to noise and distortion ratio of 46.7 dB at the sampling rate of 4.35 MS/s while consuming 6.6 mu W from 0.6-V power supply. It maintains linearity over 7-bit when the input frequency is lower than 5 MHz. The figure of merit of 8.38 fJ/conversion-step and die area of 0.011 mm(2) is achieved.
asynchronous analog-to-digital converter (adc) time-domain comparator successive approximation register (sar) pulse width modulation (pwm)