clock skew bounds estimation under power supply and process variations
In this paper, we address the problem of estimating clock-skew bounds in presence of power supply and process variations. We present a novel technique based on sequence of linear programs to compute the upper and lower bounds of clock skew. We apply our method to pairs of sinks between which logic paths in the circuit exist. When spatial correlations of process variations are known, our method provides more accurate results which reflect the real design. We use accurate models and time-domain analysis ts calculate the clock network delay and delay sensitivity. The experimental results demonstrate that our technique is capable of providing very accurate skew bounds estimation (within 10\% error as compared to Monte-Carlo method) in acceptable run-times.
clock skew process variation slp