combining multicore and reconfigurable instruction set extensions
The shift to multi-core processors presents a number of opportunities and challenges to different research fields, including the field of FPGA applications. This paper investigates the advantages of combining multi-core processors and reconfigurable instruction set extensions. Both our analysis and the experimental results show that these two approaches exploit different levels of parallelism. Using a case study on the Floyd-Warshall algorithm, we demonstrate that the multi-core architecture and the reconfigurable instruction set extensions complement each other. By combining these two methods together we find a win-win solution, which gives us a more efficient implementation with higher performance.
multi-core embedded extensible microprocessors