power optimization using divide-and-conquer techniques for minimization of the number of operations
We develop an approach to minimizing power consumption of portable wireless DSP applications using a set of compilation and architectural techniques. The key technical innovation is a novel divide-and-conquer compilation technique to minimize the number of operations for general DSP computations. Our technique optimizes not only a significantly wider set of computations than the previously published techniques, but also outperforms (or performs at least as well as other techniques) on all examples. Along the architectural dimension, we investigate coordinated impact of compilation techniques on the number of processors which provide optimal trade-off between cost and power. We demonstrate that proper compilation techniques can significantly reduce power with bounded hardware cost. The effectiveness of all techniques and algorithms is documented on numerous real-life designs.
power power optimization optimality divide-and-conquer minimal operability power consumption portability portable wireless dsp applications wireless applications compilation architectural techniques architecture innovating divide-and-conquer compilation general dsp computations examples processor cost demonstrate hardware effect algorithm design data flow graphs