Helper Thread Prefetching Control Framework on Chip Multi-processor
Helper thread prefetching can improve performance of irregular data-intensive applications. However, helper thread prefetching quality depends on the values of control parameters. Adopting traditional manual methods to find the better values of control parameters is a time-consuming and complicated enumeration process. For selecting dynamically the better parameter values, this paper proposes a helper thread prefetching control framework (HPCF) based on the dynamic behavior of irregular application. The proposed HPCF is evaluated on commodity multi-core platforms by using selected benchmarks from SPEC2006, Olden, and Scalable Synthetic Compact Application #2 (SSCA2). Results show that the proposed approach is effective, the performance gain is similar to skip helper thread prefetching with the manual best parameter values. The performance improvements for Mst, Mcf, and SSCA2 benchmarks are 34.5, 18.9, and 21.4%, respectively. More importantly, compared with traditional manual methods, a helper thread does not input the parameter values manually and may be quickly solved by using the HPCF tool.
helper thread prefetching chip multi-processor parameter-value optimization data-intensive computing