An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer
In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-mu m CMOS technology are also presented and discussed.
fixed-width squarer lookup table (lut)-based computation truncated squarer digital signal processing (dsp)