Testing of core-based systems-on-a-chip
Available techniques for testing of core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesizing low-overhead test architectures and compact test solutions, In this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for SOCs, First, me develop a common ground for addressing issues such as fore test requirements, core access, and testing hardware additions. For this purpose, we introduce finite-state automata (FSA) for modeling tests, transparency modes, and testing hardware behavior. In many cases, the tests repeat a basic set of test actions for different test data that can again be modeled using FSA, While earlier work can derive a single symbolic test for a module in a register-transfer level (RTL) circuit as a finite-state automaton, this work extends the methodology to the system level and additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time. This problem is known to be a bottleneck in testability analysis not only at the system level, but also at the RTL, Experimental results show that the system-level average area overhead for making SOCs testable with our method is only 4.5%, while achieving an average test application time reduction of 80 % over recent approaches, At the same time, it provides 100% test coverage of the precomputed test sets/sequences of the embedded cores.
cores symbolic testability analysis system-on-a-chip test access