Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45nm
With the downscaling of feature dimensions, each layer of the metallization stack has to become thinner and thinner to comply with the geometrical constraints. In particular, seed layer thickness will have to be drastically reduced for the 45nm node and beyond. As PVD is a non-conformal technique, discontinuous seeding of the sidewalls of narrow features can be expected. In this study, a seed layer enhancement (SLE) process is evaluated for 300mm processing, as a possible solution for copper seeding for the 45nm node and below. We demonstrate the extendibility of this process to the fabrication of 300mm wafers. We confirm the excellent morphological properties of the deposit, which is extremely conformal, thus continuous inside the features. This process is successfully integrated in the existing metallization sequence, without any modification of the subsequent steps, including electroplating. This demonstration is supported by electrical results, showing that a 10nm thick PVD liner, which leads to severe degradation of line and via resistance, is efficiently repaired with only 20nm SLE. All electrical performances (line and via resistance, dispersion and yield) are fully recovered with implementation of the SLE step.
copper seed repair interconnects