hierarchical cross-layer control esl verification for wireless communications
We propose a cost-effective and efficient Electronic System Level (ESL) verification framework for exploration of cross-layer algorithms and architectures of wireless multimedia networking embedded systems. In the proposed ESL platform, a network simulator alleviates both benchmarking and deployment of wireless network environment when fitting a Silicon Intellectual Property (SIP) prototype to the Field-Programmable Gate Array (FPGA). We further integrate the Hierarchical Cross-Layer Control (HCLC) model with the ESL platform to form an efficient and cost-effective verification framework. With the proposed framework, cross-layer algorithms and system prototypes are easily co-verified. An IEEE 802.11p VANET case study show that we efficiently approach optimal collaborations between MAC layer QoS SIP and upper layer protocols based on the fast exploration of cross-layer control algorithms and architectures.
wireless multimedia network algorithm and architecture co-design electronic system level verification cross-layer design