A new dual bridge multilevel dc-link inverter topology
This paper attempts to construct a new hybrid multilevel dc-link inverter (MLDCLI) topology with a focus to synthesize a higher quality sinusoidal output voltage. The idea emphasizes the need to reduce the switch count considerably and thereby claim its superiority over the existing multilevel inverter (MLI) configurations. The structure incorporates a new module along with a differently used H-bridge that facilitates the increase in levels with much lower switch counts. The proposed dual bridge MLDCLI (DBMLDCLI) is evaluated using phase disposition (PD) multi-carrier pulse width modulation (MC-PWM) strategy in a filed programmable gate array (FPGA) platform. The MATLAB/System generator based simulation results validated through FPGA based prototype for a typical output level exhibit the drastic enhancement in the quality of output voltage. The total harmonic distortion (THD) obtained using a harmonic spectrum reveals the mitigation of the frequency components of output voltage other than the fundamental and paves the way to open a new avenue for nurturing innovative applications in this domain.
multilevel dc-link inverter (mldcli) switch count total harmonic distortion (thd) field programmable gate array (fpga)