low-voltage adc for sample to serial interface applications
This paper presents a CMOS implementation for a cyclic Analog-to-Digital Converter (ADC).The sampled-hold (S/H) circuit is based on the Switched-Mosfet (SM) technique described in [1-4], which is appropriate for low-voltage operation. The proposed Analog-to-Digital converterarchitecture works as sample (analog) to serial (digital) interface. The proposed ADC circuit isdesigned and simulated by using double-polysilicon double-metal 0.8m CMOS technology with 500K bite/sec. The estimated power consumption is 20W from  0.75 V supply.
analog-to-digital converter cmos analog ic design and low-voltage