Reconfigurable gate array architecture for logic functions in tunneling transistor technology
This work describes the design of a reconfigurable logic gate array composed of single-electron tunneling (SET) transistors currently under investigation as potential post-CMOS candidates for future nano-scale integrated circuits for use in low-power embedded systems. A layer in the proposed array consists of a SET summing-inverter block replicated in subsequent blocks and extended to implement flexible logic functions in terms of the sum-of-products (SoP) and products-of-sum (PoS) forms. The reconfiguring of the array can be accomplished through the alteration of a block's logic function by way of a control voltage. The reconfigurable array can work normally at room temperature and can flexibly realize functions with better performance at lower power compared with pure MOSFET circuits.
single-electron transistor (set) reconfigurable set logic circuit simulation