Low power TLB structure by using dynamic searching algorithm
We present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, with small bank buffers, called as a filter-bank buffer, located above its associated bank. Either the filter-bank buffer or the main bank TLB is selectively accessed on the basis of two bits in the filter-bank buffer. First, one block filtering TLB is proposed to support low cost and simple mechanism. Second, two-blocks filtering TLB is proposed to obtain lower power consumption and higher performance than the one block filtering TLB. Dynamic power savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The performance overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. That is, the two cycle overhead of the proposed TLB is only about 4%similar to 2%, as compared with the 15% overhead of a filter (micro)-TLB and the 22% overhead of a banked-filter TLB. We show that the average hit ratios of the filter buffers and the main banks of the proposed TLB are about 90% and 10% respectively. Therefore, significant power savings can be achieved with just a small performance degradation. The power consumption can be reduced by about 89% compared with a fully associative TLB, 69% with respect to a filter-TLB, and 37% relative to a banked-filter TLB.
translation lookaside buffer low power consumption bank structure filtering mechanism performance evaluation