A reliable quick parasitic capacitance extraction tool for the physical layer in communication systems
High speed communication and application requirements are rapidly increasing, and the quality of physical layer is more and more important to realize real reliable communications. It requires accurate and reliable hardware devices, or else communications may be unstable and unsure. In this paper, we focus on the high speed network hardware integrated circuit systems to obtain good electrical, mechanical and procedural characters. Very large scale integrations (VLSI) form the basis for the implementation of high-performance, low-power, and low-cost wireless computing and mobile application systems. In integrated circuit (IC) design flow, distributed electromagnetic effects at high frequencies become prominent and decisively impact overall IC performance. To solve this problem, this paper presents an electronic design automation tool capable of automatic capacitance extraction for IC interconnections. This tool integrates electromagnetic field based two-dimensional (2-D) and three-dimensional (3-D) interconnect capacitance extraction solvers. It can be used for VLSI parasitic capacitance parameters extraction. The system architecture, capacitance extraction process flow and some important data structures will be discussed. Some extraction experimental results will demonstrate the accuracy and high efficiency of our 2-D and 3-D solvers.
parasitic capacitance very large scale integrations electronic design automation giga bit wireless communications