interconnect-power dissipation in a microprocessor
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50\% of the dynamic power. Over 90\% of the interconnect power is consumed by only 10\% of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router's algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14\% in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.
interconnect microprocessor interconnect power power dynamic power dissipation switch paper characterization high-performance power efficiency analysis distributed hierarchies lighting router routing algorithm use wire spacing minimal power-aware demonstrate power consumption timing tuning physical design art low-power design