Low power flip-flop design based on PAL-2N structure
Adiabatic or energy-recovery logic has gained much attention recently in the development of low-power digital logic. The previously proposed adiabatic logic families have focused mainly on combination logic. In this paper, we extend this principle to the design of flip-flops. SR and JK flip-flop designs based on the pass-transistor adiabatic logic with NMOS pull-down configuration (PAL-2N) are presented. Based on the simulation results, these adiabatic flip-flops outperform their CMOS counterparts in terms of power consumption. The operation of a 4-bit binary counter developed using the proposed JK flip-flop has also been simulated and verified.
flip-flop pass-transistor adiabatic logic energy recovery