multi-level logic optimization of fsm networks
Abstract: Current approaches to compute and exploit the flexibility of a component in an FSM network are all at the symbolic level. Conventionally, exploitation of this flexibility relies on state minimizers for incompletely specified FSMs (ISFSMs) or pseudo non-deterministic FSMs (PNDFSM's). However, state-of-the art state minimizers cannot handle large ISFSMs or PNDFSMs. In addition, these exploitation techniques are at the symbolic level, not directly at the net-list logic level. We present a general approach to exploit exact or approximate flexibility directly at the net-list logic level, and we demonstrate that many sequential logic optimization techniques can be applied in exploitation. Moreover, we propose a new procedure for input don't care sequences. As a result, both computation and exploitation of input don't care sequences in larger FSM networks can be made efficient and effective. Finally, we give preliminary results on some artificially constructed FSM networks. Preliminary results indicate that our approach can be effective in reducing the size of a component of an FSM network.
multi-level logic logic optimization fsm networks net-list logic level sequential logic optimization input don't care sequences optimisation sequential circuits finite state machines logic cad multivalued logic circuits logic design multivalued logic