maintaining consistency between systemc and rtl system designs
We describe how system design consistency can be maintained across multiple levels of design abstraction using a modular verification IP strategy. This strategy involves delivery of verification IP in an environment independent manner, utilizing a standard system verification architecture that leverages re-usable component verification drivers, transaction-based interfaces, and synchronization through a system-verification master. This enables a single test-bench to be applied for systems modeled both in SystemC, as well as at the RT level. The configuration of the verification testbench is kept consistent with the design by using system-design meta-data described using the specifications of The SPIRIT Consortium.
systemc rtl verification testbench spirit transactor vip tlm