A continuous-time cascaded delta-sigma modulator with PMW-based automatic RC time constant tuning and correlated double sampling
In continuous-time (CT) delta-sigma modulators (DSMs), cascading low-order stages provides an effective way to achieve stable high-order modulation. Compared to their single-loop counterparts, CT cascaded modulators are significantly more sensitive to variation of RC time constants and finite dc gain of the opamp as these nonidealities affect the cancellation of quantization noises between the analog and digital paths. In this paper, a pulse-width-modulation (PWM) technique is proposed for CT cascaded DSMs for on-chip automatic RC time constant tuning, which in turn enables the use of a correlated double sampling (CDS) technique to boost the effective dc gain of the opamp. A finite-opamp-bandwidth compensation technique is also proposed. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented. A prototype CT cascaded 2-2 DSM operating from a low supply voltage of 0.8V is designed and fabricated in a 0.18-?m CMOS. Measurement results show that with the proposed CDS technique the signal-to-noise-plus-distortion ratio of the modulator is 28dB higher than that of the same modulator when the CDS is turned off.
continuous-time cascaded delta-sigma modulator correlated double sampling rc time constant variation pulse width modulation