High-speed CMOS Track/Hold circuit design
This paper describes the design of a high-speed CMOS Track/Hold circuit in front of an ADC. The Track/Hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 mum CMOS BSIM3v3 parameters showed that it achieves a signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption.
cmos track/hold circuit sampling sample/hold circuit ad converter