automatic generation of fast timed simulation models for operating systems in soc design
To enable fast and accurate evaluation of HW/SW implementationchoices of on-chip communication, we presenta method to automatically generate timed OS simulationmodels. The method generates the OS simulation modelswith the simulation environment as a virtual processor.Since the generated OS simulation models use finalOS code, the presented method can mitigate the OS codeequivalence problem. The generated model also simulatesdifferent types of processor exceptions. This approach providestwo orders of magnitude higher simulation speedupcompared to the simulation using instruction set simulatorsfor SW simulation.
generation simulation model operating system design evaluation communication method environments virtualization processor use code types exception instruction