A novel IEEE rounding algorithm for high-speed floating-point multipliers
Modern floating-point multipliers perform rounding in compliance with the IEEE 754 standard. Since rounding is on the critical path, high-speed rounding algorithms are used to increase the performance for floating-point multiplication. To achieve high performance with minimum increase in hardware, existing rounding algorithms generate two consecutive values in parallel, and compute the rounded product using these values. This paper presents a novel IEEE rounding algorithm which generates two nonconsecutive values in parallel to compute the rounded product. Synthesis results for double precision operands show that the proposed algorithm has approximately 2441% less delay than previous high-speed rounding algorithms presented elsewhere. The verification of the new algorithm is also presented in a simple and straightforward manner.
rounding floating-point multiplication computer arithmetic combinational circuits