Passive mixer with OPA filter for DVB-H front-end in 65nm digital CMOS technology
This paper presents a passive mixer combined with a 1st-order active low-pass filter implemented in a purely digital low-power 65nm CMOS technology. The filter consists of a four-stage operational amplifier with two feed-forward paths for a 3dB corner frequency of 4MHz. The mixer offers a very low flicker noise corner frequency of 80Hz for DVB-H application. A fabricated test chip with integrated clock regeneration circuit offers even for a very small clock input signal amplitude a maximum gain of 26dB. The combination offers an IIP3 of ?5dBm while the mixer consumes 12.27mA and the filter 4.42mA from a 1.25V supply.
mixer dvb-h clock regeneration analog circuit design nanometer cmos