Transparent DFT: A design for testability and test generation approach for synchronous sequential circuits
This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode.
test generation synchronous sequential circuits design for testability (dft) scan circuits test compaction