a methodology for hardware architecture trade-off at different levels of abstraction
In this paper a method of architecture exploration and selection is presented. Compared with other approaches, no special tools or modeling languages are needed - instead the models and tools of the ASIC design flow are used. The architecture trade-off process is performed iteratively, and considers information from different levels of abstraction in parallel. At system level, software and behavioral models, which are part of executable specifications are examined to get the necessary top-down information (performance). Bottom-up information (hardware costs) for irregular hardware structures is obtained by generating, analyzing and synthesizing VHDL code at RT-Level. For regular structures, formulas or tables can be used to estimate area and timing. The proposed approach was successfully performed for parts of a multimedia design, where an executable specification (in 'C') was available together with the standard.
architecture trade-off architecture exploration abstraction levels architecture selection