performance-aware scheduler synthesis for control systems
We consider the problem of designing a cyber-physical system where several control loops share the same architectural resources. Typically, the design of such systems proceeds in two steps. In the platform independent step, for each control loop in the system, the control designer calculates a control law and a sampling time that together ensure that the control loop has certain desired performance. Then, in the platform dependent step, these control tasks are scheduled on the platform, and a schedulability analysis determines if (and how) the control laws can be implemented and scheduled without missing the sampling deadlines. In this paper, we explore an alternative controller-scheduler co-design approach that aims to achieve optimal performance for all the individual control loops maintaining fairness. We first analyze the control systems to find out the rates at which control signals should be dropped to maintain schedulability and the optimal performance. We then use the rates to compute a schedule statically. We show a control theoretic approach to compute the effect of the rate of drops on the performance of the control systems and provide an SMT-based scheduling algorithm that takes as input control tasks, their periods, worst-case execution times, and their rate of drops, and outputs a static schedule that optimizes the performance of the control systems. We demonstrate our results through a case study on a family of inverted pendulums sharing the same processor for their control computations.
performance scheduling synthesis control systems