Estimation of FMAX and ISB in microprocessors
Inherent process device variations and fluctuations during manufacturing have a large impact on the microprocessor maximum clock frequency and total leakage power. These fluctuations have a statistical distribution that calls for usage of statistical methods for frequency and leakage analysis. This paper presents a simple technique for accurate estimation of product high-level (Full Chip) parameters such as the maximum frequency (FMAX) distribution and the total leakage (ISB). Moreover, this technique can grade critical paths by their failure probability and perform what-if analysis to estimate FMAX after fixing specific speed paths. Using our FMAX/ISB prediction, we show good correlation with silicon measurements from a production microprocessor.
critical path delay die-to-die process variation fmax distribution path-to-path correlation spatial timing model (stm) static timing analysis (sta) statistical static timing analysis (ssta) sub-threshold leakage (isb) systematic process variation timing model (tm) within-die process fluctuation