Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring
The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity "near response" and a lower fidelity "far response" in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.
thermal analysis 3-d integrated circuits (3dics) simulation measurement power blurring method silicon-on-insulator (soi) through-silicon vias (tsvs)