A General Reverse Converter Architecture with Low Complexity and High Performance
This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2(alpha), 2(2 beta+1)-1, 2(beta)-1}, where beta < alpha <= 2 beta, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2(alpha), 2(2 beta+1)-1, 2(beta)-1} is free from modulo (2(k)+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of alpha and beta can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {2(2n), 2(2n+1)-1, 2(n)-1) which is a special case of the general set {2(alpha), 2(2 beta+1)-1, 2(beta)-1}, where alpha=2n and beta=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {2(2n), 2(2n+1)-1, 2(n)-1} Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {2(2n), 2(2n+1)-1, 2(n)-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.
reverse converter residue number system (rns) residue arithmetic vlsi architecture