optimal body bias selection for leakage improvement and process compensation over different technology generations
We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage current and compensate process variations in scaled CMOS technologies. A circuit trades off sub-threshold leakage with band-to-band tunneling leakage at the source/drain junctions to determine the optimal substrate bias for different technology generations and under process variations. Using optimal body bias results in 43\% and 42\% savings in leakage for predictive 70nm and 50nm NMOS devices, respectively. This technique also reduces the effects of die-to-die and intra-die process variations in transistor length and supply voltage by 43\% and 60\%, respectively, in 50nm NMOS devices, resulting in improved yield.
optimality body bias bias select leakage process compensation process technologies forward leakage current process variation circuits band-to-band tunneling substrate bias predict device effect yield threshold cmos scaling leakage components