A flexible architecture for H.263 video coding
In this paper a flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors that perform the discrete cosine transform (DCT), the inverse discrete cosine transform (IDCT), the direct and inverse quantization (DQ and IQ), the motion estimation (ME) and the motion compensation (MC). The architecture also includes pre-processing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 stream generation. The processors have been written in synthesizeable Verilog and the firmware for the RISC (a commercial processor) has been developed in C language. The design has been tested with hardwaresoftware co-simulations in a Verilog testbench using standard video sequences and has also been prototyped onto a development system based on an FPGA and a RISC. It performs 30 QCIF frames/s with a system clock of 12 MHz or 30 CIF frames/s with a system clock of 48 MHz, which is better than other reported designs with similar degree of flexibility. Also, the low frequency system clock makes it suitable for low-power applications such as mobile videotelephony.
h.263 risc discrete cosine transform motion estimation fpga intellectual property low bit-rate video coding pipelined architecture