Modulo 2(n) +/- 1 adder design using select-prefix blocks
In this paper, we present new design methods for modulo 21, I adders. We use the same select-prefix addition block for both modulo 2(n) - 1 and diminished-one modulo 2(n) + 1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.
modulo 2n +/- 1 adders select-prefix adders computer arithmetic vlsi architectures