Sequential circuit ATPG using combinational algorithms
In this paper, we introduce two design-for-testability (DFT) techniques based on clock partitioning and clock freezing to ease the test generation process for sequential circuits. In the first DFT technique, a circuit is mapped into overlapping pipelines by selectively freezing different sets of registers so that all feedback loops are temporarily cut. An opportunistic algorithm takes advantage of the pipeline structures and detects most faults using combinational techniques. This technique is feasible to circuits with no or only a few self-loops. In the second DFT technique, we use selective clock freezing to temporarily cut only the global feedback loops. The resulting circuit, called a loopy pipe, may have any number of self-loops. We present a new clocking technique that generates clock waves to test the loopy pipe. Another opportunistic algorithm is proposed for test generation for the loopy pipe. Experimental results show that the fault coverage obtained is significantly higher and test generation time is one order of magnitude shorter for many circuits compared to conventional sequential circuit test generators. The DFT techniques do not introduce any delay penalty into the data path, have small area overhead, allow for at-speed application of tests, and have low power consumption.
clock partitioning clock freezing clock waves sequential circuit test generation power consumption automatic test pattern generation design for testability