An 8-bit 40 MS/s pipeline A/D converter for WCDMA testbed
This paper describes an 8-bit 40 MS/s pipeline A/D converter suitable for WCDMA receiver applications. Small power consumption is achieved by using 1.5 bit/stage pipeline architecture and by scaling the capacitor values along the converter. Digital correction allows also to use very low power dynamic comparators. The multiplying D/A converters (MDACs) utilize a modified folded cascode amplifier. The circuit is designed and fabricated in a 0.5 mu m CMOS technology. The measured DNL is 0.85 LSB and INL 1.91 LSB. The converter achieves over 48 dBc SFDR and more than 41 dBc SNDR dissipating 61 mW from a 2.7 V supply.
pipeline a/d converter wcdma cmos high-speed