Process optimization of plasma nitridation SiON for 65 nm node gate dielectrics
The gate leakage current and reliability concern become more serious due to the aggressive scalingdown of the gate oxide thickness. Developing advanced gate dielectrics process for mass production is essential in China. In this paper, the gate leakage current reduction and reliability optimization for plasma nitridation SiON aimed at 65 nm node CMOS application was explored. A three-step fabrication process based on single wafer tools for plasma nitridation SiON has been demonstrated. The effects of each process condition on the electrical and reliability characteristics of plasma nitridation SiON have been investigated in terms of nitrogen concentration, equivalent oxide thickness(EOT), gate leakage current, mobility, time-dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). The optimized plasma nitrided oxide demonstrated good gate leakage reduction and high carrier mobility without sacrificing the reliability performance. This optimized plasma nitridation process has been implemented into the mass production to meet the throughput and reliability requirement.
plasma nitridation gate leakage current tddb nbti post-nitridation annealing