Designing CMOS folded-cascode operational amplifier with flicker noise minimisation
The strategy for minimising the flicker noise in the folded-cascode amplifier topology is presented and the inter-relationship of design parameters for optimum design is described. The HSPICE simulation results correlate very well with the theory and validate the design methodology. The proposed solution offers good tradeoff on the conflicting performance parameters such as noise, silicon area, bandwidth and power consumption. It will be useful for the analytic model in CAD design optimisation and allows fast computation or first-order hand analysis on noise evaluation.
noise optimisation cmos operational amplifier