Large matrix-vector products on distributed bus networks with communication delays using the divisible load paradigm: performance analysis and simulation
We present a performance analysis and experimental simulation results on the problem of scheduling a divisible load on a bus network. In general, the computing requirement of a divisible load is CPU intensive and demands multiple processing nodes for efficient processing. We consider the problem of scheduling a very large matrix-vector product computation on a bus network consisting of a homogeneous set of processors. The experiment was conducted on a PC-based networking environment consisting of Pentium II machines arranged in a bus topology. We present a theoretical analysis and verify these findings on the experimental test-bed. We also developed a software support system with flexibility in terms of scalability of the network and the load size. We present a detailed discussion on the experimental results providing directions for possible future extensions of this work. (C) 2001 IMACS. Published by Elsevier Science B.V. All rights reserved.
matrix-vector product bus networks communication delay divisible load computation delay processing time minimisation