a mask double patterning technique using litho simulation by wavelet transform
Optical Lithography is a key to semiconductor device scaling. As technology continues to scale, the fundamental limits of lithography are pushed to an extreme. Today 193nm light is used to print features in 45nm technology node. As the minimum feature size on the mask is less than half the wavelength of light used for the lithography process, diffraction at the mask edges dominates the errors in mask printing. Mask transfer fidelity issues are countered using a number of Resolution Enhancement Techniques (RET) which include Optical Proximity Correction (OPC), Phase Shift Masking (PSM), Sub Resolution Assist Features (SRAF) and Dual Patterning Lithography (DPL). DPL reduces wafer throughput but has become a necessity in current and upcoming technology nodes. It involves splitting patterns in a mask into two masks that are exposed separately. DPL CAD problem is a pattern coloring problem to minimize mask edge placement error (EPE). EPE results from interaction of near field waves and any geometric solution that does not consider interaction of fields, suffers from inaccuracies. Previous publications were mostly focused on a rule based geometric solution. In this paper we investigate a method to implement DPL using fast lithography simulation taking into account not only the bad, but also the beneficial effects of having polygons in the mask close to one another in the final partitioned layout. We present results on metal layer 2 of the ISCAS-85 benchmarks. Results show that even though our model based solution is slower, unlike many previous approaches, the final output meets the objectives of reducing EPE.
wavelet transform edge placement error polygon stitch double patterning lithography