A performance optimization method by gate resizing based on statistical static timing analysis
This paper discusses a Rate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses oil timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize highperformance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method ran reduce the delay time further from the circuits optimized for minimizing the delay without the consideration of delay fluctuation.
performance optimization gate resizing statistical static timing analysis static timing analysis transistor sizing