flexible modeling environment for embedded systems design
The integration of hardware and software is perhaps the most important issue of embedded systems design. The software content of these systems is increasing in complexity which makes the code verification an important issue. Moreover, If the software development is to proceed in parallel with the hardware design, a simulation model representing the hardware behavior is needed. In this paper we describe a strategy for modeling the behavior of instruction set processors. The proposed strategy allows for retargetability and cycle true simulation with practically acceptable speed. The approach allows for very flexible timing annotations so that complex instruction sets with data dependant or addressing mode dependant timing can be modeled. The cycle true behavior allows the model to be embedded into its environment so that the system operation can be verified. The approach is seen as an improvement over a stand alone, hard-coded models since being retargetable, it requires a fraction of the development time.
flexibility model environments embedding embedded systems systems design integrability hardware software contention complexity code verification software development developer parallel simulation behavior paper strategies instruction processor timing annotation data