A Highly Adaptive and Efficient Router Architecture for Network-on-Chip
Network-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. Efficient buffer management is not only instrumental in the overall performance of the on-chip networks but also greatly affects the network energy consumption. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed, which can be used by all input channels in the router. Implementation results show up to 50% in reducing power consumption and up to five times reduction in memory utilization in router architectures when compared with a traditional router. Moreover, our extensive simulation study shows that the proposed router architecture enhances the network performance by increasing the acceptance traffic rate and decreasing the average message latency.
router architecture network-on-chip low power design performance evaluation