Linear systolic multiplier/squarer for fast exponentiation
This paper presents a new linear systolic multiplier/squarer that can compute modular multiplication and squaring simultaneously by extracting the common computable parts using a right-to-left exponentiation. The proposed method is able to reduce the latency by 49 and 32% in the worst and average case, respectively, when compared to the method that computes modular multiplication and squaring in sequence. The new systolic multiplier/squarer is highly regular, nearest-neighbor connected, and thus well suited for VLSI implementation. (C) 2000 Elsevier Science B.V. All rights reserved.
fast exponentiation cryptography public key cryptosystem common-multiplicand multiplication montgomery algorithm