a new look at exploiting data parallelism in embedded systems
This paper describes and evaluates three architectural methods for accomplishing data parallel computation in a programmable embedded system. Comparisons are made between the well-studied Very Long Instruction Word (VLIW) and Single Instruction Multiple Packed Data (SIM p D) paradigms; the less-common Single Instruction Multiple Disjoint Data (SIM d D) architecture is described and evaluated. A taxonomy is defined for data-level parallel architectures, and patterns of data access for parallel computation are studied, with measurements presented for over 40 essential telecommunication and media kernels. While some algorithms exhibit data-level parallelism suited to packed vector computation, it is shown that other kernels are most efficiently scheduled with more flexible vector models. This motivates exploration of non-traditional processor architectures for the embedded domain.
data data parallelism parallel embedded embedded systems paper architecture method parallel computation computation programmer instruction vliw taxonomies data-level parallelism parallel architecture pattern access measurement telecommunications media kernel algorithm vectorization scheduling flexibility model exploration processor simd dsp sub-word parallelism dlp ilp