Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver
This paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate to within 10% of measurements. The calibrated parasitic extractor results in good agreement between simulations and measurements for substrate noise coupling in fabricated test circuits.
boundary element solver substrate noise coupling green's function integrated circuit noise substrate parasiticm extraction