exploiting soft redundancy for error-resilient on-chip memory design
Memory design is facing the upcoming challenges due to a combination of technology scaling and higher levels of integration and system complexity. In particular, memory circuits become vulnerable to transient (soft) errors caused by particle strikes and process spread. In this paper, we propose a new error-tolerance technique referred to as the soft redundancy for on-chip memory design. Program runtime variations in memory spatial locality cause wasted memory spaces occupied by the irrelevant data. The proposed soft-redundancy allocated memory exploits these wasted memory spaces to achieve efficient memory access and effective error protection in a coherent manner. Simulation results on the SPEC CPU2000 benchmarks demonstrate 73.7\% average error protection coverage ratio on the 23 benchmarks, with average of 52\% and 48.3\% reduction in memory miss rate and bandwidth requirement, respectively, as compared to the existing techniques.
memory system error tolerance cache space utilization