a system of computer aids for designing logic circuit tests
A system of computer programs which aid in generating and validating logic circuit tests is described. Easy to use and available on a time-share computer, the system includes: 1) a preprocessor that translates a logic topology from a simple input language to binary (machine readable) form and determines indistinguishable fault sets, 2) an automatic test sequence generator for combinational circuits, and 3) a fault simulator for asynchronous sequential circuits. The faults considered are those causing any single wire branch to be fixed at logic 0 or fixed at logic 1. Wires which fan-out are simulated with independent faults on each fan-out branch as well as with faults common to all the fan-outs. Gates are simulated with unit delay and are allowed three possible logic values0, 1 and don't know. Don't know is the starting value on every gate, representing the uncertainty of internal states when power is applied to a circuit. Don't know is also used to settle critical races and oscillations.
systems computation logic circuits program generation use topologies input language fault automatic test sequence combinational circuit simulation asynchronicity sequential circuits delay value value uncertainty intern power critic sharing values timing