Low voltage high-speed CMOS square-law composite transistor cell
A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\+2 V-ds,V-sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3V supply are given.
low voltage cmos composite transistor multiplier analog signal processing