Two-phase synchronization with sub-cycle latency
Synchronizers typically incur long latency of multiple-clock cycles, resulting in low throughput. This paper presents two novel fast synchronizers, both based on two-phase protocols: a two-flip-flop synchronizer which reduces the data cycle from 612 down to 24 clock cycles, and a LDL synchronizer which strives for maximum throughput and sub-cycle latency, namely data transfers that incur no extra penalty due to synchronization. These synchronizers are useful for data transfers over long interconnects. Simulations of best- and worst-case scenarios are presented which demonstrate the improved performance of the novel synchronizers. The results are compared to two-clock FIFO and to conventional two-flip-flop synchronizers.
two-phase protocol data synchronization asynchronous circuits clock domains