seu tolerant device, circuit and processor design
Development of highly reliable and available systems requires consideration of the occurrence of single event upsets, the effects they have on system performance, and strategies for their prevention and mitigation. Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets.
single event upset fault masking error detection and correction coding soft error rate modular redundancy fault tolerant systems radiation effects temporal redundancy fault avoidance