A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
This paper presents an ASIC processor chip for real-time implementation of the computing of the complete process of forward transform, quantization, inverse transform, dequantization, and reconstruction of a 16??16 macroblock in full compliance with the H.264/AVC video coding standard. This processor is capable of processing 4??4 blocks without interruption, with a parallelism in the data-path of 16 data/cycle, in a pipeline architecture with the twofold aim of achieving high operation frequency and high throughput. To implement the four 4??4 transforms and two 2??2 transforms required in the H.264/AVC coding system, two configurable multitransform direct 2-D architectures are used, one for forward and another for inverse. Moreover, a reduction in hardware is achieved by reformulating of quantization and dequantization equations and appropriately adjusting the datapath bus widths. A prototype of this processor chip was fabricated in the HCMOS9 STMicroelectronics 130nm standard cell technology. The latency for 16??16 macroblocks is 26 clock cycles in normal mode and 42 in Intra 16??16 mode with a maximum operating frequency of 280MHz and a throughput of 4,480 Mpixels/s. As a result, our processor chip is able to support the UHDTV 7680??4320@60Hz (3G sample/s) format requirement.
quantization h.264 asic processor integer transform transform coding