voltage dependent gate capacitance and its impact in estimating power and delay of cmos digital circuits with low supply voltage (poster session)
Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, C G, eff it is shown that the power and delay of CMOS digital circuit can be estimated accurately. C G, eff is a strong function of V TH /V DD and V TH /V DD tends to increase in low-voltage region. Hence, the effective capacitance (relative to oxide capacitance, C G, eff , is decreasing in low-voltage low-power designs. Therefore, considering C G, eff in accurate power and delay) estimation becomes more important in the future.
gate capacitance low supply voltage low-power design