deeply-scaled cmos-integrated nanophotonic devices for next generation supercomputers
High-performance computing (HPC) systems capable of delivering Exaflops performance are envisioned to become a reality by the end of this decade. In order to provide the enormous communication bandwidth that is necessary, hundreds of millions of optical interconnects will have to be deployed to connect together racks, modules and chips. To achieve such massive level of parallelism for HPC systems, monolithic integration of deeply scaled silicon optical circuits into the front-end of standard CMOS process have been demonstrated as a promising technology. The monolithic integration of electronic and nanophotonic components was performed at the IBM using 200 mm SOI wafers (SOITEC) having a 220 nm silicon device layer on top of a 2 m BOX. Several processing modules have been added to a standard CMOS processing flow at the front-end of the line. These modules require a minimal number of additional unique masks and processing steps, while sharing most mask levels and processing steps with the rest of CMOS. For example passive waveguides and electro-optical and thermo-optical modulators share the same silicon device layer with CMOS PFETS and NFETS.
integrated nanophotonic devices