simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum coupling noise under power, delay, and area constraints. Design expressions exhibiting parabolic noise behavior are compared with SPICE simulations. Due to the parabolic coupled noise behavior, the minimum noise is established. Good agreement between the analytic results and SPICE simulations is shown.
noise power delay area interconnects