A fast scheduling algorithm for low power design
In this paper, a fast low power scheduling algorithm is presented for high-level synthesis with multiple voltages. The resources are assumed to operate at different voltages and their power consumption and delay for each voltage level is known in advance. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal available parallelism of power hungry operators in an initial schedule. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in quadratic complexity in the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resource-and-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3%-5% of the linear programming method.
scheduling algorithm low power high-level synthesis multiple voltages