Efficient BEM-based substrate network extraction in silicon SoCs
This paper is focused on the efficient extraction of the substrate network in complex system-on-chip designs. A boundary element method (BEM)-based approach, which employs spatial-frequency domain Green's function analysis, is considered and very high efficiency is achieved by a novel formulation of the boundary conditions which describe both resistive and capacitive couplings. The efficiency of the proposed technique is further increased taking advantage of the inherent information compression provided by the discrete cosine transform (DCT). The effectiveness of the proposed method is assessed by comparison with a commercial substrate extraction tool and its computational advantage is illustrated on the basis of computer simulation results.
substrate network extraction system-on-chip substrate analysis substrate coupling smart power integrated circuits