System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown
We analyze system-level lifetimes of a state-of-art microprocessor due to BTI, HCI, and GOBD while accounting for PVT variations. A unified model including both GOBD and PVT variations on timing impact is introduced for the first time. We present a simulator which can evaluate microprocessor lifetime under simultaneous degradation due to BTI, HCI, and GOBD. The work employs statistical timing analysis to estimate the degradation of the microprocessor performances and its lifetime distributions.
variation-aware bti hci gobd