Resource requirements and layouts for field programmable interconnection chips
Field-programmable interconnection chips (FPIC's) provide the capability of realizing user programmable interconnection for any desired permutation. Such an interconnection is very much desired for supporting rapid prototyping of hardware systems and for providing programmable communication networks for parallel and distributed computing. An FPIC should realize any possible permutation of input to output pins via a set of programmable switches, In this paper, we show that any such architecture requires a minimum of Omega(n log n) switches, where n is the number of I/O pins. The result stems from an analysis of the underlying permutation network. In addition, for networks of bounded degree d, we prove an Omega(log(d-1) n) bound on the routing delay (maximum length of routing paths for specific I/O permutations) and an Omega(nlog(d-1) n) bound on the average utilitation of programmable switches used by the FPIC to implement a specific permutation. For the same type of networks, we prove an Omega(n log(d-1) n) bound on the number of nodes of the network. Furthermore, we design efficient architectures for FPIC's offering a wide variety of routing delays, high average programmable resource utilization, and O(n(2))-area two-layer layouts. The proposed structures are called hybrid Benes-Crossbar (HBC) architectures and clearly exhibit a tradeoff between performance (routing delay, utilization) and area of the layout.
field programmable interconnection chips permutation networks routing delay area-performance tradeoff programmable devices vlsi layout