FinFET based SRAM bitcell design for 32nm node and below
The methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves consideration of both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower Vccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1?m2 below 32nm node.
finfet sram bitcell 32nm vccmin mugfet 22nm snm icell