analysis and reduction of glitches in synchronous networks
The influence of transition activity on dynamic power dissipation is analysed by examining three components: dissipation in combinational logic, flipflops and clock line. Transition activity is analysed by making a distinction between useful transitions and glitches (useless transitions). A transition counting and parity evaluation method is used for this. Most glitches can be eliminated by introducing flipflops using retiming and pipelining and/or by choosing different architectures. In this way an optimal level for pipelining can be found.
glitches synchronous networks transition activity dynamic power dissipation combinational logic clock line retiming pipelining flip-flops timing cmos logic circuits combinational circuits pipeline processing logic design