On-line integrity monitoring of microprocessor control logic
This paper presents a low-cost reliability enhancement strategy for the microprocessor's control logic, which usually remains unprotected against soft errors due to great overhead. We classify control signals into static and dynamic control depending on their changeability. For static control, signals used in pipeline stages are integrated into a signature and verified with a cached check code at commit time. The concept of caching signatures is introduced. Dynamic control is examined on the spot in which the signals are created using component-level duplication. Fault injection simulations on a SimR2K processor demonstrate that our schemes can achieve more than 99% coverage on average with a very small hardware addition.
soft error fault injection simulation fault tolerant microprocessor concurrent integrity checking fault sensitivity