a system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms
Current and future SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility,performance and cost constraints. Designing such a heterogenous MP-SoC architecture bears enormous potential for optimization, but requires a system-level design environment andmethodology to evaluate architectural alternatives. This paper proposes a methodology to jointly design and optimize the processor architecture together with the on-chip communicationbased on the LISA Processor Design Platform in combination with SystemC Transaction Level Models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modeling ef.ciency, accuracy and simulation performance possible on the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.
systems processor communication methodology platform future design heterogeneity programmer combinational complexity architecture flexibility performance cost constraint optimality system-level design environments evaluation paper systemc model refine flow accuracy simulation abstraction effect decode transaction-level model exploration system on-chip