A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture which is designed with the minimum hardware cost compared to other kinds of architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.
h.264/avc deblocking filter computer architecture