VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform
Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.
vlsi discrete wavelet transform lifting scheme