Analytical synthesis of bandwidth-efficient SDRAM address generators
SDRAM memories are a commodity technology which deliver fast, cheap and high capacity external memory in many cost-sensitive embedded applications. When designing with SDRAM memory, the memory bandwidth available is strongly dependent on the sequence of addresses requested. For applications with hard real-time performance requirements, it is prudent to perform at compile time, some form of analysis to guarantee those hard real-time deadlines are met. In general with SDRAM memories, this analysis is difficult, and this leads to conservative implementations. On-chip memory buffers can make possible data reuse and request reordering which together ensure bandwidth on an SDRAM interface is used efficiently. This paper outlines an automated procedure for synthesizing application-specific address generators which exploit data-reuse in on-chip memory and transaction reordering on an external memory interface. We quantify the impact this has on memory bandwidth over a range of representative benchmarks. Across a range of parameterized designs, we observe up to 50 reduction in the quantity of data fetched from external memory. This, combined with reordering of the transactions, allows up to 128 reduction in the memory access time of certain memory-intensive benchmarks implemented in an FPGA. Since the synthesis procedure results in monotonic memory addressing functions, we can extract tight worst-case execution (WCET) bounds that are useful in system analysis. We show that we can extract performance guarantees which are significantly tighter than the absolute worst-case SDRAM performance.
sdram memory fpga analytical design technique worst case execution time