Current-mode signaling in deep submicrometer global interconnects
This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines,simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a vide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is Accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs With arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage And current mode repeater insertion for long global deep submicrometer interconnects is presented.
current-mode interconnect delay repeater on-chip signaling