Voltage dependences of parameter drifts in hot carrier degradation for n-channel LDMOS transistors
We evaluate the hot carrier degradation mechanisms for n-channel LDMOS transistor with STI based structures. The slope of ID,lin degradation indicates the different degradation mechanism under various bias stress. The location of peak impact ionization differs at various VGS stress but consistent at various VDS stress. The degradation mechanism is highly dependent on the stress voltage at the gate (VGS). The VDS is found as an accelerating factor for the hot carrier stress test.
hot carrier ldmos sti based structures tcad