wirelength-driven force-directed 3d fpga placement
In this paper, a wirelength-driven force-directed three-dimension (3-D) Field Programmable Gate Arrays (FPGA) placement algorithm (3D-WFP) is presented. The algorithm is composed of three stages: Overlap permitted force-directed 2-D placement, legalization and 3-D layer partition. Different from traditional partition-based 3-D placers, we adjust the layer partition process after the 2-D global placement, which effectively provides the global interconnection and timing information for the next two sub-steps. To legalize the position of the logic block, a 3-D space filling curve is adopted. A low temperature simulated annealing (SA) is used to determine the blocks final layer. Only blocks with the same horizontal coordinate are permitted to interchange, the speed of the SA is very fast. Compared to recently publish 3-D FPGA placement work, this algorithm improves the half perimeter wire-length (HPWL) by 8.57\%, almost at the same time cost and keeps the same timing performance.
force-directed placement 3-d legalization partition sa