interface timing verification with delay correlation using constraint logic programming
Using constraint logic programming and relational interval arithmetic, as implemented in CLP (BNR) Prolog, we develop a simple yet complete method for interface timing verification. We show how the problems raised by timing verification (consistency, causality and compatibility) can be formulated as constraint satisfaction problems and solved using relational interval arithmetic when the timing constraints are of the linear, earliest or latest type; we examine the effect of correlation between timing delays (within their specified intervals) and show how an interval delay narrowing method can be applied in this context. The original contribution of this paper is to provide a unifying framework for interface timing verification and to present a method that allows delay correlation to be considered.
interfaces timing timing verification verification delay delay correlation correlation constraint logic programming relational interval arithmetic relation interval interval arithmetic clp prolog completeness method consistency causality compatibility constraint satisfaction problem time constraint effect context paper  framework  time separation of events timing diagrams