TurboLock: increasing associativity of lock table in transactional memory
Transactional memory (TM) is emerging as a promising paradigm to simplify parallel programming for chip multiprocessors. Most of software transactional memory (STM) systems exploit a lock table to synchronize transactional accesses to the shared memory locations. Memory addresses map to entries of the lock table through a hash function to detect conflicts in the event of simultaneous accesses to the shared memory locations. In the current implementation of the lock table, if two distinct addresses map to the same entry of the table, they are treated as a conflict even though there is no true conflict between the two addresses. This is called false conflict. In the event of a false conflict, transactions are aborted conservatively which reduces concurrency level in programs. In this paper, we study false conflicts in STMs and propose TurboLock to reduce frequency of false conflicts. Inspired by set associative caches, TurboLock increases associativity of the lock table to reduce likelihood of aliasing-induced conflicts. While TurboLock is effective in reducing the false conflicts, it may degrade performance due to overhead of the associative lock table in software. To improve performance of TurboLock, we propose HW-TurboLock which exploits hardware to reduce overhead of the associative lock table. We have evaluated our optimization techniques using Gem5 full-system simulator and compared the performance of the new implementation with the baseline scheme. Our simulation results reveal that HW-TurboLock is highly effective and significantly improves performance of TM systems.
lock table transactional memory false conflict performance aliasing 68 computer science