Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22nm node on a 6T-SRAM cell
This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90nm on a 6T-SRAM cell. The target fins consist of straight structures (40nm height and 17nm of critical dimension) patterned on a 22nm node with 90nm fin pitch. The patterning stack consists of 70nm of amorphous carbon as a hard mask with 25nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32nm node with 124nm fin pitch was no longer functional for patterning fins on a 22nm node with 90nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17nm of critical dimension on 90nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability.
dry etching 22nm node 6t-sram cell softlanding fins on soi