Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec
Application studies indicate that between 50% and 80% of the power cost in image and video processing systems is due to data storage and transfers. This is especially true for multi-processor realizations, because conventional parallelization strategies ignore this cost and focus only on the performance, whereas the power consumption also depends heavily on the way a system is parallelized. We will demonstrate the impact of processor partitioning on the memory requirements by exploring a QSDPCM video codec realization. Furthermore, we show that a strategy for combined task and data parallelism exploration leads to a significant power reduction.
processor partitioning memory optimization low-power design multi-media hybrid task-data parallelism