A two-level reconfigurable architecture for digital signal processing
This paper describes a novel reconfigurable architecture for digital signal processing (DSP). This architecture consists of a two-level array of cells and interconnections. On the upper level, fundamental DSP operations such as multiplication and addition are mapped onto blocks of 4-bit cells. On the lower level, each cell uses a 44 matrix of smaller elements to perform the necessary computations. Cells also contain pipeline latches for increased throughput. The architecture features a simple VLSI implementation that combines the flexibility of memory elements with the speed of DOMINO logic. Initial prototypes have been fabricated using a modest 0.5-?m CMOS technology. Circuit simulations of the cell in 0.25-?m technology indicate that the design achieves a clock frequency of 200MHz.
digital signal processing reconfigurable systems design two-level architecture vlsi systems