An efficient VLSI architecture for real-time additive synthesis of musical signals
This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infinite-impulse-response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. a chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to II chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-mu m CMOS technology and has a core area of approximately 19 mm(2).
additive synthesis bit-level systolic arrays iir marginally stable filters musical synthesis algorithms real-time musical synthesis sinusoid generation systolic architectures