scheduling and resource binding for low power
Abstract: Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget.
scheduling resource binding resource binding low power power abstraction design process implementation paper power consumption resource-binding high-level synthesis algorithm low-power data-paths trading off activation functional units functional adders multipliers transit input account data-path power budget budget high level synthesis network synthesis logic circuits data flow graphs data