Implementation of cache coherence protocol for COMA multiprocessor systems based on the scalable coherent interface
The Scalable Coherent Interface (SCI) provides high bandwidth, low latency communication in systems with point-to-point links. SCI can also support cache coherence in shared memory multiprocessors. Existing Cache-Only Memory Architecture (COMA) systems are all based on communication and cache coherence protocols other than SCI. Hierarchical COMA systems generally suffer from high message latencies. In this paper, we examine the implementation of COMA multiprocessors using SCI protocol. Implementing the SCI communication protocol in hierarchical COMA systems reduces latencies and its cache coherence protocol will reduce directory sizes. In this work, a hierarchical COMA system was modified so that it fits the SCI. In addition, a new replacement policy is proposed in which replaced lines swap storage locations with new ones fetched into the attraction memory. Similar to other COMA systems, this new system still gives high performance when part of the attraction memory is left unallocated. However, the performance of this system is slightly influenced by the initial distribution of data across the system.
cache coherency protocol coma multiprocessors interface sci data traffic