power estimation of dividers implemented in fpgas
We present a methodology for power estimation of non-fractional divider cores implemented in FPGAs. The methodology takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10\%, with a maximum error of 22\% when estimates are compared to on-board measurements and less than 11\% when estimates are compared to low-level estimates provided by the commercial tool.
power estimation dividers fpgas