Deterministic BIST for RNS adders
Modulo 2(n) - 1 adders as fast as n-bit 2's complement adders have been recently proposed in the open literature. This makes a Residue Number System (FINS) adder with channels based on the moduli 2(n), 2" - 1, and any other of the form 2(k) - 1, with k < n, faster than RNS adders based on other moduli. In this paper, we formally derive a parametric, with respect to the adder size, test set, for parallel testing of the channels of an RNS adder based on moduli of the form 2(n), 2(n) - 1,2(k) - 1, 2(l) - 1,..., With L < k < re. The derived test set is reusable; it can be used for any value of n, k,1,..., regardless of the implementation library used and is composed of n(2) + 2 test vectors. A test-per-clock BIST scheme is also proposed that applies the derived test vectors within n(2) + 2n cycles. Static CMOS implementations reveal that the proposed GIST offers 100 percent postcompaction fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST.
residue number system built-in self-test deterministic and pseudorandom tests formal test sets