Delay fault testing of IP-based designs via symbolic path modeling
Predesigned blocks called intellectual property (IP) cores are increasingly used for complex system-on-a-chip (SOC) designs. The implementation details of IP cores are often unknown or unavailable, so delay testing of such designs is difficult. We propose a method that can test paths traversing both IP cores and user-defined blocks, an increasingly important but little-studied problem. It models representative paths in IP circuits using an efficient form of binary decision diagram (BDD) and generates test vectors from the BDD model. We also present a partitioning technique, which reduces the BDD size by orders of magnitude and makes the proposed method practical for large designs. Experimental results are presented that show that it robustly tests selected paths without using extra logic and, at the same time, protects the intellectual contents of IP cores.
delay fault testing system-on-a-chip (soc) automatic test pattern generation (atpg) binary decision diagram (bdd) decomposition intellectual property (ip) (core) testing