A High-Speed Word Level Finite Field Multiplier in F-2m Using Redundant Representation
In this paper, a high-speed word level finite field multiplier in using redundant representation is proposed. For the class of fields that there exists a type I optimal normal basis, the new architecture has significantly higher speed compared to previously proposed architectures using either normal basis or redundant representation at the expense of moderately higher area complexity. One of the unique features of the proposed multiplier is that the critical path delay is not a function of the field size nor the word size. It is shown that the new multiplier outperforms all the other multipliers in comparison when considering the product of area and delay as a measure of performance. VLSI implementation of the proposed multiplier in a 0.18-mu m complimentary metal-oxide-semiconductor (CMOS) process is also presented.
redundant representation type i optimal normal basis finite field arithmetic word level architecture