Delay testing viability of gate oxide short defects
Gate Oxide Short (GOS) defects are becoming predominant as technology is scaling down. Boolean and I(DDQ) testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the COS defect taking into account the random parameter of the defect such as the COS resistance and the COS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the COS as a function of the COS resistance and location. It is demonstrated that i) COS has a significant impact on gate delay, ii) COS located close to the source of the transistor and with small resistance has very high impact.
delay testing defect gate oxide short (gos) vlsi