A carrier peak synchronous direct digital demodulation technique and its FPGA implementation
This paper presents a carrier peak synchronous direct digital demodulation scheme for linear modulated signals and its innovative FPGA implementation. The demodulation scheme generates a carrier equivalent signal that is in quadrature with the modulated signal and strobes the modulated signal at the carrier peaks. A digitizer in the form of an analog to digital converter now converts the sampled data to a digital count, thereby producing a direct digital read-out of the modulated signal. This obviously eliminates the necessity of the standard sequence of multiplication, low pass filtering and subsequent processing common in existing analog and digital synchronous quadrature demodulators. Removal of the low pass filtering stage eliminates the inherent filter time lag that proves beneficial in those measurement applications where exact phase sensitive detection of the measurand at specific time instant is important. The feasibility of the proposed scheme is established through its FPGA implementation for reconstructing the modulating signal by sampling the modulated signal at every carrier peak and holding the sampled value till the next sampling instant. The implementation is found to automatically capture and remain tuned to any carrier frequency in the range 763 Hz to 100 kHz.
fpga implementation digital synchronous demodulation quadrature carrier generation