Baseband digital predistorter with quadrature error correction
In this article simulation and measurement results of a FPGA implementation of a baseband digital complex gain predistorter with a quadrature modulator and demodulation error correction circuits are presented. Four different methods for finding the quadrature error correction values are compared and the effect of quadrature errors to predistortion is discussed. A 50 dB three stage power amplifier chain with an analog quadrature modulator and demodulator was used in the measurements as the device to be predistorted. The signal used in the measurements and simulations was a 30 dBm 18 kHz 16-QAM signal at 400 MHz carrier frequency. In the measurements 15 dB reduction in 3rd order nonlinearity was achieved. The usage of quadrature error correction reduced the adjacent channel power by 9 dB.
quadrature error correction digital complex gain predistortion power amplifier linearization