Analysis of the Soft Error Susceptibility and Failure Rate in Logic Circuits
The failure rate of logic circuits due to high-energy particles originating from outer space has been increasing dramatically over the past 10 years. Whereas soft errors have traditionally been of much greater concern in memories, smaller feature sizes, lower voltage levels, higher operating frequencies, and reduced logic depth are projected to cause a dramatic increase in soft error failure rate in core combinational logic in near-future technologies. Traditional fault tolerance strategies may be utilized to protect against these failures; however, the excessive area overhead and stringent power dissipation requirements have made these techniques obsolete, especially in mainstream applications. Therefore, there is an urgent necessity to identify the weak steps during the synthesis of these components that result in the generation of highly-susceptible designs. In this paper, we analyze the susceptibility of logic circuits to transient pulses through an extensive set of logic synthesis experiments while varying the synthesis process. Our aim is to identify the correlation between the key design options and their consequent effect on the susceptibility of the produced implementation. The results in this work reveal that the SER is strongly correlated with logical masking of transient pulses and, thus, fast logic-level soft error failure rate assessment methods can be used in place of computationally-intensive circuit-level assessment techniques. Furthermore, we project that logical masking will become the dominant source for protecting logic circuits from transient pulses, which encourages the development of logic synthesis techniques that maximize the logical masking of potential transient
soft errors soft error susceptibility soft error failure rate single-event transient soft error sensitization probability