Fine grain faults diagnosis of FPGA interconnect
This paper proposes a new fine grain fault diagnosis method for the interconnect of an arbitrary design implemented in a Field Programmable Gate Array (FPGA). In the proposed method, interconnect faults detected at the primary output are back-tracked until the faulty nets are precisely located. This is carried out by programming the LUTs on the faulty path to be transparent and thus propagating the value of a specific net under test to the primary output for verification against the expected value of the net. After every back-tracking iteration, the fault location is narrowed down and thus the number of nets to be tested decreases significantly. Therefore, the upper bound of the number of configurations (NMAX) required to locate a faulty net, depends on the maximum combinational depth (DCOMB) of the circuit, and it is approximately equivalent to three times of DCOMB. The proposed method has the ability to locate multiple faults without any fault masking with fault coverage that includes all possible stuck-at, open and pair-wise bridging faults. The proposed method is validated on the ISCAS89 benchmark circuits mapped on Xilinx Spartan 3E, Virtex-4 and Virtex-5 FPGAs and the results are presented. The simulation results show that applying the proposed method on circuits with less combinational depth reduces the required number of test configurations on average by 35% when compared with the latest method available in the literature.
fpga interconnect diagnosis interconnect fault location