An improved compact model for CMOS cross-shaped Hall-effect sensor including offset and temperature effects
A compact model of a cross-shaped horizontal integrated Hall-effect sensor is presented in this paper. Compared to existing models, reliability is improved, especially to simulate systems in which biasing and measurement circuits are not independent. The Hall device model core, already published, is based on a network of six non-linear resistances and four Hall voltage sources, and includes only 11 physical parameters. In this paper, in order to improve model predictivity, four additional parameters have been added to take the offset issue into account. In addition, variations of parameters with temperature are also addressed. The model is implemented in Verilog-A and has been validated through experiments carried out on Hall devices designed in a CMOS 0.35 mu m technology. The parameters extraction procedure is detailed and the maximum error between simulations and experimental data is less than 1 % for a wide range of biasing currents and temperatures.
compact modeling offset temperature verilog-a cmos hall-effect sensor cross-shaped hhd