Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution
A VLSI efficient multiplier-less architecture for real-time computation of multi-dimensional convolution is presented in this paper. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less log2 and inverse-log2 modules which are capable of converting the fraction numbers currently not available in the literature. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The proposed approach reduces hardware resources significantly compared to other approaches maintaining a high degree of accuracy. The architecture is developed as a combined systolic-pipelined design that produces an output in every clock cycle after an initial latency of 93.19 uSec. The architecture is capable of operating with a clock frequency of 99MHz based on Xilinxs Virtex II 2v2000ff896-4 FPGA and the throughput of the system is observed as 99 MOPS (million outputs per second). Error analysis performed with the FPGA-based system in the image processing examples of edge detection and noise filtering shows that the proposed architecture produces outputs similar to that obtained by software simulation using Matlab.
multi-dimensional convolution multiplier-less architecture logarithmic domain computation systolic-pipelines architecture fpga-based implementation