general ac constraint transformation for analog ics
The problem of designing complex analog circuits is attacke dusing a hier archic altop-down, constr aint-driven design methodolo gy. In this methodolo gy, constraints are prop agate dautomatically from high-level specific ationsto physic aldesign through a sequence of gradual transformations. Constraint tr ansformation is a critic al step in the methodolo gy, sinc e it determines in lar ge p art the degree to which specific ations are met. In this pap er we describ e how constr ainttransformations can be efficiently carrie d out using hier ar chic al parameter modeling and constr aine d optimization techniques. The process supp orts c omplexhigh-level sp ecific ation handling and accounts for second-order effects, such as inter connect parasitics and mismatches. The suitability of the appr oachis demonstrate d through an 4 th order active filter test case.
gate-sizing logic synthesis fanout optimization