Logic synthesis for cellular architecture FPGAs using EXOR Ternary Decision Diagrams
In this paper, an efficient approach to the synthesis of CA (Cellular Architecture)-type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms which can be mapped directly to the cell arrays are generated by using ETDDs (EXOR Ternary Decision Diagrams). Since a traversal of the ETDD is sufficient to generate a Maitra term which takes O(n) steps where n is the number of nodes in the ETDD, Maitra terms are generated very efficiently. The experiments show that the proposed method generates better results than existing methods.
logic synthesis cellular architecture fpga maitra terms etdd