A reduced data bandwidth integrated electrode driver for visual intracortical neural stimulation in 0.35 ? m high voltage CMOS
This paper presents an integrated electrode driver for intracortical neural stimulation requiring a reduced data bandwidth. The device has been fabricated in the OnSemi I3T50 0.35 ? m high voltage CMOS process, measures 44mm2 and drives 45 electrodes: electrical measurements corroborate the functional simulations, and confirm that the data bandwidth can be significantly reduced using preloaded wavetables as is introduced in this architecture. The maximum power usage is 13.3mW under maximum load for all 45 electrodes.
visual intracortical neural stimulation integrated neural stimulator biomedical integrated circuits mixed-signal integrated circuit design