Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes
This paper presents a block-layered decoder architecture and efficient design techniques for quasi-cyclic nonbinary low-density parity-check (QC-NB-LDPC) codes. Based on a Min-Max decoding algorithm, an efficient block-layered decoder architecture for QC-NB-LDPC codes is proposed for fast decoder convergence. Further, a novel two-way merging Min-Max algorithm, which significantly reduces decoding latency, is proposed for check node processing. The NB-LDPC decoder using the proposed algorithm can provide a considerably higher throughput rate than that using a conventional Min-Max algorithm. The proposed (225, 165) NB-LDPC decoder over GF(24) is synthesized using a 90-nm CMOS process. It can operate at a clock rate of 400MHz and achieve a data processing rate of 24.6 Mbps under 10 decoding iterations.
block-layered nonbinary min-max decoding two-way merging low-density parity-check (ldpc) codes vlsi