lut-based fpga technology mapping for reliability (abstract only)
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 32nm and beyond. It is common for defect points to occur in the lookup table (LUT) configuration bits, which are crucial to the correct operation of FPGAs. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using an overlapping window-based method which allows for accurate and efficient error calculations. This new windowing technique can approximate the complete don't cares (CDC) within 2.5\%. This is 5X faster than a 100k Monte Carlo simulation and 26\% more accurate. Compared to the windowing method used in the ABC synthesis system, our new method is 2.77X more accurate for computing the CDC. We then use our new windowing in an FPGA mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher success of functioning correctly when implemented on a faulty FPGA. By using our algorithm, we are able to reduce the number of possible faults by over 12\% with no area increase. Our work shows that it is possible to effectively increase the reliability of a design in the presence of LUT faults in FPGAs.
technology mapping error analysis windowing don't cares logic synthesis fpga lookup table