Evaluation and performance analysis of the process cache: a partitioned multi-process secondary cache
This paper describes an advance in multiprocess cache system design called the process cache in which the secondary cache has segments dedicated to each process. This approach is in contrast to a monolithic secondary cache in which every process' data can be distributed throughout the secondary cache. The process cache system is equally applicable to instruction and data caches, however, its performance is evaluated only for an instruction cache in this paper. The goal of the process cache architecture is to improve program performance in environments which have high context switch rates and long tertiary memory access times. This paper presents an instruction only trace-driven simulation that demonstrates that for long tertiary memory latencies (10 ?s) and short context switch intervals (1 ms) the process cache architecture significantly (1114%) outperforms monolithic secondary cache architectures independent of cache memory size, associativity, or cache line size. This improvement does not require significantly more hardware than current cache memory designs. Additionally, we present an architecture which allows the system to allocate different amounts of secondary cache memory per process. Furthermore, process caches provide a high degree of locality for process information in a multiple processor configuration allowing efficient task migration between processors.
performance analysis cache momories multiprogramming