A high-performance fully reconfigurable FPGA-based 2D convolution processor
This paper presents a new fully reconfigurable 2D convolver designed for FPGA-based image and video processors. The proposed architecture operates on image pixels coded with different bit resolutions and varying kernel weights avoiding power and time-consuming reconfiguration. This is made possible by using new SIMD arithmetic modules purposely designed for the new circuit. When optimized for the XILINX VIRTEX device family, the convolver presented in this work requires just 18.4ms to perform a 55 convolution on a 10241024 8-bit pixels image and dissipates only 102.1mW/MHz. The new circuit can be exploited in all the real-time applications in which adaptive convolutions are required and it can be realized also in many other FPGA device families.
convolution image processing single instruction multiple data circuits