depth optimal incremental mapping for field programmable gate arrays
In this paper, we study the incremental technology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-level networks, a mapping solution associated with it, and a sequence of changes to the original network, we compute a new mapping solution by modifying the existing one. Moreover, we assume that the given mapping solution is depth-optimal and we are required to come up with a modified mapping solution that maintains the depth optimality. The objective of our incremental mapper is to maintain depth-optimality with very high efficiency while minimizes the modifications to the existing mapping solution. We revealed a set of sufficient conditions for maintaining depth optimal mapping solution after a sequence of incremental changes. Based on these results, we developed a very fast incremental technology mapping algorithm, called IncFlow, that runs up to 300 x faster than the well-known depth-optimal FlowMap algorithm [1](with an average of 14x speedup) while achieves the same depth-optimal mapping quality.
optimality incremental map paper technology mapping fpgas change network association sequence computation maintainability object efficiency algorithm speedup quality field-programmable-gate-array