specification of timing constraints for controller synthesis
For controller synthesis to be successful, detailed knowledge of the timing constraints of the system under synthesis is essential. This paper presents a method for extracting timing constraints from a behavioral description, architectural restrictions, component timing requirements and protocol specifications. The timing constraints are combined in a timing constraint graph that can be solved in polynomial time using algorithms known from symbolic layout compaction.
time constraint timing control synthesis knowledge systems paper method behavior architecture component requirements graph polynomial algorithm layout compact