Low power clock recovery circuit for passive HF RFID tag
A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable system clock when communication occurs from interrogator to tag with 100% ASK modulation. An envelope detector is designed to detect the incident power from interrogator and control the operating state of the proposed clock recovery circuit. Loop bandwidth of PLL circuits is minimized to reduce the frequency deviation when operating in frequency maintaining state. Furthermore, an initialization circuit for loop filter is also used to speed up locking during initial system power-on-reset. Prototype chips have been fabricated in 0.35 mu m 2P4M CMOS technology. A total current consumption of 3 mu A has been achieved in the frequency maintaining state. Measurement results show that, when communication occurs from interrogator to tag with 100% ASK modulation, clock recovery circuit generates a stable and consecutive system clock and has an inevitable frequency derivation of 7.5% when operating in frequency maintaining state.
low power clock recovery hf rfid tag pll 100% ask modulation