A read-decoupled gated-ground SRAM architecture for low-power embedded memories
In this work, a gated ground SRAM architecture based on a seven transistor (7T) bit-cell is proposed. The proposed cell shows higher data stability and yield under varying process, voltage, and temperature (PVT) conditions than the conventional 6T cell. A single-ended sense amplifier is also presented to read from the proposed cell while a unique write mechanism is used to reduce the write power to less than half of the write power of the 6T cell. The proposed cell consumes similar silicon area and leakage power as the 6T cell when laid out and simulated using a commercial 65-nm CMOS technology. The ground gating is done by selectively controlling the column virtual ground (CVG) of accessed word in a row. This significantly reduces the leakage power consumption and enables implementing multiple words per row, which lowers multiple-bit data upset in the event of radiation induced single event upset or soft error. In addition, the proposed cell inherently has a 30% larger soft error critical charge, making its soft error rate (SER) less than the half of that of the 6T cell.
leakage power soft error sram bit-cell read noise margin