A low-power block-matching cell for video compression
This paper describes the implementation of a block-matching module with digital I/O. Algorithmic analysis demonstrates that the precision requirements can be met by a compact circuit that processes the signal in the charge domain. The required conversion between voltages and charges is achieved by MOS capacitors. As a result, it can be fabricated by any inexpensive digital CMOS technology. A test chip has been implemented in a standard CMOS 1.6 mum technology and the measured energy consumption is 1.2 nJ per block match using an 8 x 8 pixel matrix. Simulations of the same cell in 0.35 mum and 0.25 mum CMOS technology are presented, showing the scalability of the approach.
video compression block matching low-power ics