Data bus swizzling in TSV-based three-dimensional integrated circuits
The purpose of this paper is to efficiently exploit swizzling in reducing coupling noise between the bit lines of a TSV-based data bus in three-dimensional integrated circuits. The core concept of swizzling is to distribute the noise of an aggressor to all victims, rather than concentrating on the nearest victim. Based on this principle, an optimal swizzling pattern, which achieves an equal distribution of the coupling impedance, is proposed. The efficiency of this optimal pattern is demonstrated through comparison to no swizzling and two other swizzling patterns while considering different TSV diameters, aspect ratios, pitches, and transition times of the aggressor signal. A circuit model of a TSV-based 3-D data bus is evaluated in HSPICE with each TSV modeled as an RLC impedance. A maximum reduction of 51% in peak coupling noise is achieved.
data bus swizzling three-dimensional integrated circuits through silicon via