Fast Waveform Estimation (FWE) for Timing Analysis
This paper proposes a new technique, fast waveform estimation (FWE), to quickly and accurately estimate the output waveform for general resistance-capacitance (RC) interconnect networks in the presence of coupling noise. It is a common view that the traditional transient analysis is not feasible for full-chip timing analysis. The static methods suffer from inaccuracy and inability to capture the non-monotonic nature of signal waveform in the presence of coupling noise. The dynamic methods, such as, general model order reduction techniques provide a good compromise between the accuracy and efficiency. But they make no use of the typical topological structures of the general RC interconnect networks. The proposed FWE technique achieves a better overall performance through topological reduction of the general RC interconnect networks. It is demonstrated that the accuracy of the proposed method is comparable to the general model order reduction-based methods while maintaining an efficiency that is comparable to Elmore delay based analysis.
timing analysis circuit simulation