hierarchical timing analysis using conditional delays
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identification of false paths. We exploit hierarchy information to perform efficient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit c6288, which is difficult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAT. The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.
hierarchical timing analysis hierarchic time analysis analysis conditional delays delay method circuits representation module event propagation model complexity identification exploit hierarchies informal efficiency computation effect high-level modeling applications order path sensitization timing modeling symbolic analysis