SAccO: An implementation platform for scalable FPGA accelerators
This paper presents SAccO (Scalable Accelerator platform Osnabrck), a novel framework for implementing data-intensive applications using scalable and portable reconfigurable hardware accelerators. Instead of using expensive reconfigurable supercomputers, SAccO is based on standard PCs and PCI-Express extension cards featuring Field-Programmable Gate Arrays (FPGAs) and memory. In our framework, we exploit task-level parallelism by manually partitioning applications into several parallel processes using the SAccO communication API for data streams. This also allows pure software implementations on PCs without FPGA cards. If an FPGA accelerator is present, the same API calls transfer data between the PCs CPU and the FPGA. Then, the processes implemented in hardware can exploit instruction-level and pipelining parallelism as well. Furthermore, SAccO components follow a set of hardware implementation rules which enable portable and scalable designs. Device specific hardware wrappers hide the FPGAs and boards idiosyncrasies from the application developer. SAccO also comprises a new method to automatically select a tasks optimal degree of parallelism on an FPGA for a given hardware platform, i.e. to generate a hardware design which uses the available communication bandwidth between the PC and the FPGA optimally. Experimental results show the feasibility of our approach.
implementation platform fpga hardware acceleration reconfigurable computing coprocessor hardware/software codesign