Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation
This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for superthreshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows similar to 2.5 x improvement in throughput at iso-power compared to a conventional design.
parallelization and pipelining pseudo-nmos logic subthreshold logic