circuit clustering for delay minimization under area and pin constraints
We consider the problem of circuit partitioning for multiple-chip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow duplication of logic gates as if would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the non-optimality occurs and show that the condition occurs rarely in practice. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays.
circuit clustering circuits cluster delays minimal pin constraints constraint circuit partitioning partition multiple-chip implementation implementation motivation tools fpga chips logic gates logic circuit delay paper algorithm general model repeated network cut technique network optimality area constraints practical benchmark benchmark circuits circuit layout cad delay minimization constraints vlsi layout design nonoptimality field programmable gate arrays network topology logic partitioning logic cad vlsi