Design of an FPGA logic, element for implementing asynchronous NULL convention logic circuits
Two versions of a reconfigurable logic element are developed for use in constructing a NULL convention logic (NCL) field-programmable gate array (FPGA): one with extra embedded registration capability, which requires additional area, and one without. Both versions can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and both can utilize embedded registration for gates with three or fewer inputs; however, only the version with the additional embedded registration capability can utilize embedded registration with four-input gates. These two approaches are compared with each other and with an existing approach, showing that both,versions developed herein yield a more area efficient NCL circuit implementation, compared to the previous work. The two FPGA logic elements are simulated at the transistor level using the 1.8-V, 180-nm TSMC CMOS process.
reconfigurable logic null convention logic (ncl) asynchronous logic design delay-insensitive circuits field-programmable gate array (fpga)