adapative error protection for energy efficiency
With dramatic scaling in feature sizes, noise resilience is becomingone of the most important design parameters, similar to performanceand energy efficiency. Noise resilience is particularly problematicin long on-chip buses of complex single chip systems suchas on-chip multiprocessors. While one might opt to employ a verypowerful error protection scheme, this may not be very energy efficientas noise behavior typically varies over time. In this paper, wepropose an adaptive error protection scheme for energy efficiency,where the type of the coding scheme is modulated dynamically.The idea behind this strategy is to monitor the dynamic variationsin noise behavior and use the least powerful (and hence the mostenergy efficient) error protection scheme required to maintain theerror rates below a pre-set threshold. Our detailed experimental resultsobtained through simulation show that this adaptive strategyachieves the same level of error protection as the most powerfulstrategy experimented, without experiencing the latter's energy inefficiency.Based on our results, we recommend system designersto adopt adaptive protection schemes in environments where bothenergy and reliability are important.
errors protection energy energy efficiency efficiency scale feature noise resilience design use complexity systems scheme behavior timing paper adapt code dynamic strategies monitor maintainability threshold experimentation simulation environments reliability chip multiprocessors