Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2(m)) Using Multiple Parity Prediction Schemes
New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over G F (2(m)) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.
normal basis parity prediction concurrent error detection (ced) cryptography