A 220-MSample/s CMOS sample-and-hold circuit using double-sampling
A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in a 0.5 mu m CMOS technology. The measurements show 10-bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW @ 3 V power dissipation.
cmos sample-and-hold double-sampling high-speed