Test energy minimization for C-testable ILAs
We consider energy consumption during testing for C-testable iterative logic arrays (ILAs). We show that the cell test sequences in the ILA have a property of repetition and ensure that the test energy depends on the order of the test patterns, which is obvious for random logic, but is not for ILAs due to its iteration property. The time complexity for obtaining the transition energy of all possible pattern sequences is reduced from O((XNC2)-N-2-C-2) to O((XC2)-C-2), where X, N, and C represent the test length, array size, and cell complexity, respectively. We formulate the problem of finding the optimal test sequence, as a shortest-path problem. Using the obtained test sequence the total energy consumption is minimized, and the transition power is within the design specification. The time complexity is independent of the array size.
test energy minimization c-testability iterative logic array built-in self-test design for testability logic testing