Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths
This article presents experimental results for a clock-timing methodology that allows timing characterization and testing of high-speed pipelined datapaths using slow-speed testers. The technique uses a clock-timing circuit to control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9ps in 0.18?m CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit used to generate and control test mode clocks.
timing characterization high-speed pipelined datapaths circuit testing delay circuits design-for-testability