directory-based cache coherency protocol for a ring-connected multiprocessor-array
The main goal of this paper is to demonstrate that a multiporcessor with very fast point-to-point interconnection can be 10 times faster than a bus-based one. In this work, we presented a two-dimensional ring-connected system where the processing-nodes are arranged in rows and columns and interconnected through horizontal and vertical unidirectional 64-bit links (similar to the Illiac 4). After presenting the architecture for the processing-nodes, the pipelined feature of the network and the cache-coherency protocol, we discussed some implementation issues for the system. Using trace-driven simulation, some performance results for the new system and for a bus-based two-dimensional system (similar to the Wisconsin multicube) were presented to show the superiority of using point-to point interconnections instead of buses.
cache coherence paper demonstrate point interconnect present systems links architecture pipeline feature network implementation performance arrays trace driven simulation process multiprocessor