ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces
RDMA needs independent memory management by the NIC in host/GPU virtual address space. This requires fast lookup of buffers and Virtual-to-Physical address translation. We developed an ASIP for the FPGA to accelerate these operations with good results. ASIP design has been effective thanks to architecture exploration toolsuite.
programmable interconnect point-to-point networks network protocols virtual memory hardware accelerators electronic design automation