post-route lut output polarity selection for timing optimization
Modern FPGA architectures support flexible polarity propagation in the fabric of logic blocks and interconnects. For example, the output of a lookup-table (LUT) logic block can be inverted by inverting all the bits in the LUT table. The rise and fall delays in either a LUT or a routing multiplexer usually differ substantially. The flexibility of polarity propagation and the difference between the rise and fall delays provide an opportunity to further optimize timing. This paper describes an algorithm to minimize the longest path delay by adjusting LUT output polarity after routing. The algorithm can be extended to reduce active leakage power in routing multiplexers while meeting timing constraints. The algorithm is efficient,easy to implement, and does not require change in placement and routing. Preliminary experiments show that the algorithm can reduce the longest path delay by up to 5.8\% and on average 2.5\% on a set of customer designs.
polarity timing optimization fpga lookup table