Verification and fault synthesis algorithm at switch-level
Switch-level simulation has become a common means for accurate modelling of CMOS circuit behaviour and testing. This paper presents an algorithm for modelling CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Another advantage of this algorithm is its application in the mapping of single and multiple faults from switch-level to gate level as well as its function as a multi level model. Multiple faults can be of the same or different types. Experimental results show that the algorithm is successful and reliable for CMOS technology.
synthesis physical fault vlsi testing graph algorithm switch-level model