A 1.8-V 3.1 mW successive approximation ADC in system-on-chip
This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital converter (ADC) for SoC system. Based on conventional successive approximation ADC architecture a new and faster solution is used. The new solution consists of bootstrap switch, capacitors for sample-hold (S/H) circuit and DAC, using an offset cancellation method and there is no need for any active element. Together with an added bit and an offset compensation comparator the speed and accuracy is increased. The ADC exhibits higher 9 effective number of bits (ENOB) for sample rate to 2.5 Ms/s. The ADC consumes 3.1 mW from a 1.8 V supply and occupies about 0.25 mm(2). The measured SNR is 56.05 dB.
offset compensation successive approximation analog-to-digital converter (sar adc) low power sc technique