High-level side-channel attack modeling and simulation for security-critical systems on chips
The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side-channel observation. The adoption of high-level countermeasures and the verification of the feasibility of new attacks presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered at high-level simulation in order to evaluate the actual implementation of a cryptographic algorithm, this being software or hardware based. The simulation is performed within a unified tool based on SystemC, which can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation and mixed software-hardware implementations with cycle-accurate resolution. Here, we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and identification of the weaknesses in cryptographic algorithm implementations ("Side Channel Analysis Resistant Design Flow").
aes power-analysis attacks smart cards code breaking system-level simulation