Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays
This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In addition, the partial rerouting approach is generalized so that as many as possible previous routing results can be reused in the current rerouting step. The reconfiguration time is reduced from O ((1 - rho).beta.m.n) to its lower bound O((1 - rho).m.n) for m x n host arrays with small fault density, rho, where beta is the expected routing length required per logical column.
routing reconfiguration degradable very large scale integration arrays algorithm fault tolerance