high-performance raster graphics for microcomputer systems
A frame buffer architecture is presented that reduces the overhead of frame buffer updating by three means. First, the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel. Second, the pixel-change operation is performed by hardware in a single read-modify-write cycle. Third, multiple objects in the frame buffer are addressable simultaneously by a set of address registers. The remaining task of generating (x,y) addresses and providing new data can be managed rapidly by current microprocessors or DMA-devices. With a modest expenditure of hardware, this architecture eliminates all the bit-shifting, bit-masking, and bit-manipulation conventionally associated with frame buffer graphics, while retaining the full generality of user-programmable control. The particular implementation described allows raster manipulation at full bit-map memory bandwidth. It can paint a 1616 pixel character into the frame buffer in 16 microseconds and can modify a 10241024 pixel raster in 64 milliseconds.
high-performance graphics microcomputer systems frame buffer buffers architecture update bit-map memorialized addressing strings parallel hardware object task general data management manipulation association control implementation bandwidth paint character read writing user change device functional memory raster operation raster-scan graphics programmer