a low power 3d integrated fft engine using hypercube memory division
In this paper we demonstrate a floating point FFT processor that leverages both 3D integration and a hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227 ?J. The hypercube memory division scheme lowers the energy per memory access by 59.2\% while only increasing the total area required by 16.8\%, while using 3D integration reduces the logic power by 5.2\%. For comparison, we analyze the amount of power and wire length reduction that can be expected from 3D integration for normal digital logic circuits.
fft 3dic scaling