AUTONOMOUS GROUP TESTING BASED FAULT TOLERANCE IN RECONFIGURABLE LOGIC DEVICES (RETRACTED ARTICLE) (Retracted article. See vol. 22, 1393001, 2013)
A fault tolerance technique for reconfigurable logic devices in self-organized systems is developed by using the Combinatorial Group Testing (CGT) principles. It employs adaptive combinatorial group testing techniques to autonomously maintain resource viability information as an organic means of transient and permanent fault resolution. By minimizing the repair time due to using CGT algorithm addressed in this paper, the online availability of the device progressively increases. The approach of CGT proposes a novel method for isolating faults at progressively increasing granularity using only functional testing. Dedicated test vectors are unnecessary as the algorithm operates on the output response produced for real-time operational FPGA's throughput. The information about the resource performance obtained using CGT techniques is utilized to identify the faulty resource on the FPGA by using alternate configurations which lead to exclude the faulty resource. However, after the algorithm locates the fault, a cell swapping operator is used to isolate the defective resource and realizes the fault tolerance. Simulation is done on two different combinatorial circuits from LGSynth93 Benchmarks. Results show that the algorithm would be able to successively isolate a stuck-at fault at the input of a logic resource for proposed benchmark circuits at most in 27 stages.
group testing fault tolerance autonomous systems reconfigurable hardware reliable systems