ESDInspector: A new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism
On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESDInspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-mum BiCMOS technology.
esdinspector esd protection electrostatic discharge (esd) layout verification parasitic esd protection device