A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization
A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 mu m 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25 degrees C), a clock frequency of 266 MHz can be achieved.
h.264/avc memory organization variable block size motion estimation (vbsme)