Timing driven genetic placement
In this paper, a timing-driven genetic placer for standard-cell IC design is presented. The objective of the placer comprises minimizing both area and path delays. The objective function is such that when the algorithm starts converging toward generations with acceptable delay properties, the objective is dynamically adjusted toward optimizing area and wire length. Experiments with benchmark tests demonstrate delay performance improvement by up to 20%. It is also shown that sizable reduction in runtime is obtained when population size is allowed to decrease in a controlled manner whenever the search hits a plateau. This reduction in runtime is achieved without any noticeable loss in solution quality.
placement combinatorial optimization critical paths genetic algorithm interconnect delay estimation physical design standard-cell layout timing-driven placement timing verification timing prediction vlsi