A novel on-chip electrostatic discharge protection design for RF ICs
A novel, compact electrostatic discharge (ESD) protection structure is designed, which protects integrated circuits (ICs) against ESD damages in all modes. This ultra-fast-response ESD structure, with response time of t1?0.16nS, operates symmetrically. Measurements showed desired low holding voltage (?2V), low discharging impedance (<2?), high current handling capacity and adjustable triggering voltages. ESD testing passed HBM 14 and 15kV air-gap IEC zapping. Design prediction was achieved by comprehensive mixed-mode ESD simulation. The area-efficient ESD design features small Si consumption, low parasitic effects and is particularly suitable for high-speed VLSI and RF ICs. The design was implemented in commercial sub micron BiCMOS technologies for multi-power-supplies mixed-signal ICs.
electrostatic discharge integrated circuits bipolar transistors