circuit architecture for low-power race-free programmable logic arrays
The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50\% power savings at less than 10\% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.
programmable logic arrays circuit timing low power