Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications
This paper presents results of a simulated performance evaluation of RISC-based SoC platforms for networking applications and compares them to measurement results on an FPGA prototype. We use our SystemC simulation environment, which is calibrated with a reference implementation. Starting with an analysis of the reference scenario, two approaches for improvements are investigated: at first, hardware assists are added, which offload the CPU from compute-intensive bit-level manipulations. Secondly, the concept of flexible processing paths as proposed in FlexPath NP with AutoRoute is evaluated, in which certain parts of the traffic can bypass the central CPU cluster. For each of the three scenarios we determine the maximum throughput and discuss the improvements and limitations of each solution. It can be shown that a FlexPath NP may achieve up to 2.5 times the throughput of the reference scenario. Simulation results are compared to additional measurements on the FPGA platform, which led to a further refinement of our system model. The investigations provide a deeper insight on the practical benefits and limitations of system-level performance simulations. (C) 2007 Elsevier B.V. All rights reserved.
performance simulation system-on-chip network processors architecture evaluation and exploration