Clock-delayed domino for dynamic circuit design
Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design toots developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino's characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS's 0.8 mu m CMOS process with scalable CMOS design rules that allow a 1.0-mu m drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6X faster than a dual-rail domino adder designed with the same cell library and technology.
adder dynamic logic circuit dynamic logic clocking inverting single-rail dynamic gates self-timed circuits