adapting instruction level parallelism for optimizing leakage in vliw architectures
Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions ---issued--- per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38\% of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.
instruction level parallelism vliw architecture leakage energy functional units instruction scheduling power supply gating