multiplier architectures for fpga double precision functions (abstract only)
FPGA devices are now more capable at supporting floating point applications, but double precision IEEE754 systems are still very challenging to implement, with large amounts of logic, routing, and DSP resources needed. Double precision multiplier operators, requiring 54x54 multiplier cores, are now directly supported in the fabric, however, multiplier based algorithms for algebraic and elementary functions typically require larger multiplier functions, typically in excess of 60x60 bits precision. This paper will use the example of a double precision exp (ex) to explore tradeoffs with multiplier architectures mapped to current FPGAs devices. Different types of the larger multiplier architectures, including direct implementations and Karatsuba-Ofman algorithms will be compared, including their effect on the resource requirements and system performance of the exp function. Smaller multiplier architectures, which introduce a small maximum functional error, will also be examined. Alternate large multiplier architectures can provide the same accuracy with increased system performance, with up to 33\% less multiplier resources. Smaller multiplier will reduce the multiplier resources by up to 50\%, albeit with a small maximum error, in the range of 5 ulp.
fpga floating point