Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Through Silicon Via (TSV) is the state-of-the-art vertical interconnect technology in three dimensional Integrated Circuits (3D-ICs). TSVs offer short wire length with low capacitive load and, hence, fast connections between two or more chip layers. On the other hand, TSVs consume a relative large amount of chip area and are error prone during manufacturing resulting in a dramatic yield drop for large TSV counts. Because of their short wire length, TSVs can be clocked much higher than conventional intra-layer links. To efficiently utilize the vertical bandwidth of TSVs, this paper proposes multiplexing several virtual links with dynamically allocated bit rates for guaranteed service connections via a shared TSV-Hub-Array. Virtual links can be state-of-the-art interconnects like busses, crossbars or 2D-NoC links. The TSV-Hub allows migration of traditional 2D interconnects towards the 3D stack while benefiting from a reduced TSV count and reuse of existing IP blocks and interconnection schemes. Furthermore, the TSV-Hub approach is also advantageous under interconnect resilience considerations. An incorporated switchbox enables dynamic protection switching for several faulty TSVs. Moreover, it can even cope with situations when more than the number of spare TSVs becomes defective. By means of a case study with two independent AXI interconnects, we could show an area reduction in the range of at least 10% for a TSV size of 10?m and conservatively estimated the reliability improvement by one order of magnitude in comparison to a direct link interconnection.
virtualization 3d-ics tsvs fault tolerant systems on-chip-interconnect noc