A built-in self-test method for diagnosis of synchronous sequential circuits
We propose an approach for built-in fault diagnosis of synchronous sequential circuits. The proposed approach distinguishes faults based on their detection by modified versions of a fault detection test sequence generated on-chip. The modified versions are defined by one-bit-wide auxiliary sequences, also generated on-chip. The auxiliary sequences indicate which test vectors of the fault detection test sequence need to be applied to the circuit. Experimental results presented indicate that the proposed on-chip test generation method is effective in achieving high levels of diagnostic resolution.
synchronous sequential circuits fault diagnosis built-in self-test (bist)