Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams
We address the problem of computing critical area for open faults (opens) in a circuit layout in the presence of multilayer loops and redundant interconnects. The extraction of critical area is the main computational bottleneck in predicting the yield loss of a very large scale integrated design due to random manufacturing defects. We first model the problem as a geometric graph problem and we solve it efficiently by exploiting its geometric nature. To model open faults, we formulate a new geometric version of the classic min-cut problem in graphs, termed the geometric min-cut problem. Then the critical area extraction problem gets reduced to the construction of a generalized Voronoi diagram for open faults, based on concepts of higher order Voronoi diagrams. The approach expands the Voronoi critical area computation paradigm with the ability to accurately compute critical area for missing material defects even in the presence of loops and redundant interconnects spanning over multiple layers. The generalized Voronoi diagrams used in the solution are combinatorial structures of independent interest.
voronoi diagrams open faults layout geometric min-cuts computational geometry critical area analysis design for manufacturability yield prediction