an energy-efficient fdct/idct configurable ip core for mobile multimedia platforms
The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents an energy-efficient FDCT/IDCT configurable IP core. Synthesis for 90 nm resulted in 50 MHz as maximum frequency and 1.66 mW as total power, achieving a throughput of 188.2 Mpixels/s, which is enough to process two HDTV@1080p videos in real time. The IP core architecture is based on Massimino's algorithm, which was chosen for its accuracy and parallelism. The exploration of its parallelism resulted in a fully-combinational 1-D FDCT/IDCT configurable datapath. In addition, the IP core is IEEE-1180 compliant. Comparisons with related work, in terms of energy efficiency (mJ/Mpixel), revealed that our architecture is at least 64\% more efficient than other DCT architectures.
energy efficiency. discrete cosine transform (dct) vlsi architecture