on-chip transactional memory system for fpgas using tcc model
The amount of processing elements in chip-multiprocessors is increasing continuous. Parallel programs use locks or mutexes to access shared resources. However, coarse-grained-locks are easy to write but limit the parallelization of the code, while fine-grained locks allow more parallel execution but often lead to deadlocks or other bugs, due to a more difficult program development. Hardware Transactional Memory allows an easement in parallel program development by providing a simplified concurrency management. The basic idea of transactional memory are atomic transactions, which offer a method for synchronization of processes without having the problems of synchronization methods like locks. In this paper a concept for adopting the TCC transactional memory model to Xilinx FPGAs using MicroBlaze soft-core processor is presented and first implementation details are given.
fpga tcc microblaze multicore