power analysis and low-power scheduling techniques for embedded dsp software
Abstract: This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Significant points of difference have been observed between this model and the ones developed earlier for some general-purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instructions to be packed into pairs. The energy reduction possible through the use of this feature is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A micro-architectural power model for the multiplier is developed and analyzed for further energy minimization. A scheduling algorithm incorporating these new techniques is proposed to reduce the energy consumed by DSP software. Energy reductions varying from 11\% to 56\% have been observed for several example programs. These energy savings are real and have been verified through physical measurement.
power analysis power analysis low-power scheduling scheduling embedded dsp software embedding software abstraction paper applications measurement measurement based power analysis dsp processor processor instruction-level power model instruction power model model use point effect circuit state circuits cost streams case architecture feature energy reduction energy reduction on-chip booth multiplier energy consumption program micro-architectural power model energy minimization scheduling algorithm examples energy saving physical real-time systems general digital signal processing chips low power instruction sets circuit cad