low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power efficiency of superscalar processors through instruction reuse at the execution stage. This paper proposes a new method for reusing instructions when they compose small loops: the loop's instructions are first buffered in the Reorder Buffer and reused afterwards without the need for dynamically unrolling the loop, as commonly implemented by the traditional instruction reusing techniques. The proposed method is implemented with the introduction of two new auxiliary hardware structures in a typical superscalar microarchitecture: a Finite State Machine (FSM), used to detect the reusable loops; and a Log used to store the renaming data for each instruction when the loop is "unrolled". In order to evaluate the proposed method we modified the sim-outorder tool from Simplescalar v3.0 for the PISA, and Wattch v1.02 Power Performance simulators. Several different configurations and benchmarks have been used during the simulations. The obtained results show that by implementing this new method in a superscalar microarchitecture, the power efficiency can be improved without significantly affecting neither the performance nor the cost.
superscalar processor power reduction loop reusing technique reorder buffer optimization