bidwidth analysis with application to silicon compilation
This paper introduces Bitwise , a compiler that minimizes the bitwidth the number of bits used to represent each operand for both integers and pointers in a program. By propagating 70 static information both forward and backward in the program dataflow graph, Bitwise frees the programmer from declaring bitwidth invariants in cases where the compiler can determine bitwidths automatically. Because loop instructions comprise the bulk of dynamically executed instructions, Bitwise incorporates sophisticated loop analysis techniques for identifying bitwidths. We find a rich opportunity for bitwidth reduction in modern multimedia and streaming application workloads. For new architectures that support sub-word data-types, we expect that our bitwidth reductions will save power and increase processor performance. This paper also applies our analysis to silicon compilation, the translation of programs into custom hardware, to realize the full benefits of bitwidth reduction. We describe our integration of Bitwise with the DeepC Silicon Compiler. By taking advantage of bitwidth information during architectural synthesis, we reduce silicon real estate by 15 - 86\%, improve clock speed by 3 - 249\%, and reduce power by 46 - 73\%. The next era of general purpose and reconfigurable architectures should strive to capture a portion of these gains.
analysis applications compilation paper pointers program informal forward dataflow graph programmer invariance instruction reduction multimedia streams architecture support power processor performance custom hardware integrability synthesis clock general reconfigurable architecture types data