Scaling trends of power noise in 3-D ICs
Paper shows how power noise changes in 3-D ICs with CMOS and TSV technology scaling. Uniform distribution of P/G TSVs array exhibit lower on-chip power noise. An accurate and fast closed-form expression to calculate TSV equivalent inductance. Tradeoffs among TSV parameters, technologies, and power noise are discussed.
technology scaling through silicon vias (tsvs) 3-d integrated circuits (3-d ics) inductive coupling power supply noise