Hardware architectures for the Tate pairing over GF(2(m))
In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying, Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design. parameters are presented. (C) 2007 Elsevier Ltd. All rights reserved.
hardware architecture tate pairing cryptography bkls/ghs algorithm