HW/SW co-design for low power arithmetic and logic units
As many embedded microprocessors are battery driven, low power design is becoming increasingly necessary. In this paper, we proposed hardware-software co-design architecture for low power arithmetic and logic units. By including multiple functional units with the same functions and different speeds, we provide instruction implementations at various power prices. Then, with an assembler level scheduler, we identify and create situations whereby the low-power slow functional units can be utilized. The overall performance is not compromised as no additional stalls are introduced. Simulations show 10%similar to 35% power saving in typical addition operations.
arithmetic logic unit design instruction scheduling instruction interdependence