power-aware design synthesis techniques for distributed real-time systems
This paper presents an end-to-end synthesis technique for low-power distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-level power consumption while satisfying end-to-end hard real-time latency bounds. A system is modeled as a set of distributed task chains (or pipelines). Each task chain is given its own end-to-end constraints. Task chains may share resources. Our approach searches the space of the trade-off between end-to-end latency and supply voltages of resources to minimize system-level power consumption. A power optimization algorithm is proposed for simple distributed real-time systems that do not have any resource sharing between task chains, and its optimality is shown. For more general systems, a heuristic based on the same techniques is proposed.
synthesis real-time distributed system voltage scaling