A new methodology for single event transient suppression in flash FPGAs ?
This paper describes a Single Event Transient (SET) suppression design technique for hardening combinational circuits against SETs in non-volatile Field Programmable Gate Arrays (FPGAs). The proposed method adds a SET suppressor circuit that is insensitive to SETs, to each primary output of a combinational circuit. The SET suppressor circuit consists of three components; an AND gate to suppress an SET reaching the primary output, when the primary output is logic 0, and an OR gate when the primary output is logic 1. The third component is a simple two input multiplexer with its output connected to its own select line such that it will select the AND gate output when the combinational circuit primary output is logic 0 and the OR gate output when the primary output is logic 1. A delay element is used to split each primary output of the combinational circuit into two signals. The two signals, one being the original primary output and the other a delayed copy of it, is sent to input one and input two of the SET suppressor. An alternative embodiment of the SET suppressor circuit is to use Double Modular Redundancy (DMR) instead of the delay element implementation. The SET Suppressor method is thoroughly tested on MCNC91 benchmarks using the ModelSim simulator. The SET Suppressor circuit provides total immunity against SETs, however it does so with an area savings of 11.662.2% with respect to TMR when the delay element technique is use. When the DMR SET Suppressor technique is used, the area savings with respect TMR is between 16.1% and 31.9%.
single event transient field programmable gate array single event upset tripple modular redundancy application specific integrated circuits