An analog on-line-learning K-means processor employing fully parallel self-converging circuitry
A hardware-efficient on-line-learnable processor was developed for the K-means clustering of highly dimensional vectors. Based on our proposed sample updating strategy, an incremental number of sample vectors can be clustered by a constant set of VLSI circuits. In order to speed up the learning process, we developed an analog fully parallel self-converging circuitry to implement the K-means algorithm. Upon receiving a sample vector on-line, the K-means learning autonomously proceeds and converges within a single system clock cycle (0.1 mu s at 10 MHz). Furthermore, the chip-area and inner connection explosion problem was solved by using the proposed architecture. A proof-of-concept processor was designed and verified by the HSPICE and Nanosim simulations. The images from an actual database were used as learning samples in the form of 64 dimensional feature vectors. From the simulation results, all the samples were clustered into correct categories with a randomly ill initialization. In addition, the number of sample vectors can be freely increased.
on-line-learning k-means fully parallel self-converge highly dimensional