A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter
A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 mu m CMOS process, According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
settling boost pipelined adc cmos low power