Influence of high-level synthesis on average and peak temperatures of CMOS circuits
The aim of this paper is introducing a new modified high-level synthesis (HLS) technique resulting in reduction of the power dissipation in CMOS circuits leading to lowering the peak and the average temperature of the designed chip. The presented approach enables us designing contemporary electronic systems with reduction of the peak and average power consumption, so the reliability of the system can be improved. In the present method, the initial HLS is performed by the ASAP algorithm [The Synthesis Approach to Digital System Design, 1992]. In the next stage, acceptable increase of the toggling time of chosen functional units (without exceeding the system throughput  the latency is constant) leads to the possibility of decreasing their supply voltages. These chosen functional units are determined by the inserting idle operations with interchanging (IIOI) algorithm. This approach leads to decreasing the power dissipated in the chosen functional units and finally their peak and average temperature is lowered.
reduction of power dissipation in cmos circuits low power design reduction of average and peak temperatures of vlsi cmos circuits