Low Power Motion Estimation Design Based on Non-Uniform Pixel Truncation
Motion estimation (ME) consumes large hardware cost and power (50%90%) in most video encoders. Thus reducing the power consumption of ME is a major concern of low power video encoder design. A lot of fast ME approaches have been proposed but many of them focus on algorithm speed up rather than power consumption. Pixel truncation can effectively reduce the hardware cost and the power consumption. Classical pixel truncation is usually performed uniformly within the search window. However, it suffers great compression efficiency degradation when high power reduction ratio is required. This paper proposes a low power motion estimation scheme based on non-uniform pixel truncation. By observing the unequal distribution of motion vectors, we divide the search window into different sub-regions and employ different numbers of truncated bits (NTB) in these sub-regions. NTB pairs are appropriately examined to achieve a better tradeoff between the compression efficiency and the hardware cost. Then hardware architecture is designed to evaluate the hardware cost of the algorithm and a carefully designed threshold parameter is introduced to make the algorithm more hardware-friendly. Test results demonstrate that the proposed hardware-friendly algorithm achieves 21% and 49% power saving in the 2D and 1D ME architecture, respectively, both with negligible compression efficiency degradation.
motion estimation pixel truncation low power electronics power efficient video coding vlsi architecture