An adaptive write error detection technique in on-chip caches of multi-level caching systems
Cache memories are becoming an integral part of modern computer systems and are instrumented in various ways. As a result of the nature of reference locality, the CPU mostly communicates instructions and data with the first level on-chip caches that are originally fetched from the secondary cache or memory with very low frequency. Thus, the guarantee of this initial fetch-and-write into the first level cache, which is rare but fundamental for correct future operation, is indispensable for a dependable caching system. This paper presents a new cache write error detection scheme, called cache write sure (CWS), which exploits the preexisting information redundancy of the multi-level caching systems. The effectiveness of this detection technique is evaluated by using on-the-fly trace driven simulations of thirteen benchmarks combined with software error injection. The results show that for most workloads, the CWS provides almost complete write error detection for non-protected I-cache in a two-level on-chip caching system with a cache cycle time ratio between L1 and L2 of 1.5. At the same time, it can also cover 57.9% of write error for D-cache. (C) 1999 Elsevier Science B.V. All rights reserved.
transient error detection fault tolerant cache cache write sure technique