A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts XOR gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the XOR gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific reduction of the peak current can be achieved. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% by assigning polarity to XOR gates at the sink level of the clock tree. An additional 12.8% reduction in the worst case peak current can be achieved by reconfiguring the polarity assignment based on the clock gating information. The proposed flow increases the area by 7.1% but reduces both the total power consumption by 23.8% and the global skew increase (due to polarity assignment) from 19.3 to 8.8 ps. The insertion of XOR gates at the non-sink nodes is also studied to further reduce the global skew increase and the area overhead.
polarity assignment clock gating clock network synthesis physical design optimization