A complete model for glitch analysis in logic circuits
One of the major factors, which contribute to the power consumption in CMOS combinational logic circuits, is the switching activities in the circuits. Many of such switching activities axe due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones, which model only the propagation of glitches to count the number of glitches in the circuits, it allows to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we complete the concept of G-vector by providing a set of efficient solutions to the three important practical issues: (1) extending to signals over multiple clock cycles, which exactly accounts for a sequence of input signals over multiple clock cycles. (2) extending to a nonzero delay model, which accounts for both nonzero and nonuniform delay of each gate in the circuit and (3) extending to a logic decomposition utilizing the model, which reveals a possibility of utilizing the model in synthesizing logic circuit with less glitches. Integrating the solutions all together enables G-vector to be practically very efficient. A set of experimental results is provided to show the effectiveness of the proposed solutions.
glitch logic synthesis low-power design power optimization