sizing cmos circuits by means of the gm/id methodology and a compact model
The gm/ID sizing methodology. Sizing the Intrinsic Gain Stage by means of experimental data or a model like the E.K.V./A.C.M. model. Sizing short channel devices with parameters that are functions of bias conditions. Parameter acquisition, accuracy, examples. Application to the sizing of low-power low-voltage CMOS circuits like the Miller Op. Amp, Barranco's current sources, etc.
circuit sizing