Voltage-controlled nano-addressing for nanosystem communication ?
An outstanding challenge for realizing a nanosystem is nano-addressing, i.e., how to precisely access a nanoscale wire in an array for communication between a nanosystem and the outside world. Existing nano-addressing methods are based on implementation of binary decoders, which requires unrealistic precise layout control in nanotechnology. Presented in this paper is a voltage-controlled nano-addressing scheme, which differentiates each nanoscale data line by its electrical parameters (e.g., voltages), instead of requiring unique physical structures. As a result, the proposed voltage-controlled nano-addressing scheme enables bottom-up self-assembly and aggressive scaling of nano-addressing circuits with the rest of a nanosystem. A novel nano-addressing circuit includes two address lines which form resistive voltage dividers, and provide gate voltages for two rows of transistors which gate the nanoscale data lines. For two proposed nano-addressing metrics, resolution and accuracy, the proposed circuit achieves single data line resolution by applying high voltage drops to the address lines or by deploying high subthreshold slope transistors, while an adaptive addressing method achieves addressing accuracy only depending on the uniformity of the address lines, and external time domain variations. SPICE simulations based on compact CNFET models demonstrate the effectiveness of voltage-controlled nano-addressing.
nano-addressing nanotechnology nanoelectronics