eliminating the z-buffer bottleneck
We present a solution to one of the fundamental problems in computer graphics, the hidden surface removal. In most 3D-graphics systems the hidden surface removal is done using the Z-Buffer algorithm. This method, however, requires one to perform a read-modify-write memory access for each visible pixel, which represents a severe performance limit. We introduce a novel SRAM cell, which incorporates the needed logical units to perform the Z-Buffer algorithm on its own. Placed into the page register of conventional DRAMs, almost any pixel rate can be achieved.
z-buffer bottleneck computer graphics hidden surface removal sram cell logical units page register pixel rate memory architecture sram chips buffer storage hidden feature removal