Decoupling of data and tag arrays for on-chip caches
In traditional cache structures, entries in the data array and the tag array are tightly coupled, that is, entries in both arrays are one-to-one mapped. In this paper, we decouple the traditional one-to-one mapping between data and tag arrays for cache structures. The key idea is that the block tag is stored in different tag arrays such that these tag and data arrays are accessed by different indices. The freedom due to decoupling the tag association may bring several advantages. We use a formal inference to verify if a cache structure can give correct decoupled addressing. We summarize three generalized decoupled models that can also be applied to other previously proposed approaches in the literature. We evaluate our schemes and compare with other approaches by trace-driven simulation. The simulation results show that the decoupled mechanisms can reduce significant tag area with a slight increase of the average access time per instruction.
decoupled caches interleaved cache architectures partial tag array caching tag sectored caches