load and store reuse using register file contents
The detection of opportunities for value reuse optimizations in memory operations require both the addresses and values associated with these operations to be available. Although the values are typically available in the physical register file, their presence cannot be exploited because no correspondence between the values and addressess is maintained. In this paper we propose the explicit management of the physical register file contents as a level in the memory hierarchy by supporting the Value Address Association Structure (VAAS). The entries in VAAS have a one-to-one correspondence with entries in the physical register file. For each value in the register file that is involved in a load or store operation, the associated information, including the memory address, are stored in the corresponding VAAS entry. Several optimization tasks can be performed using the combination of physical registers and VAAS. Specifically VAAS enables unified implementation of the following optimization tasks: (i) Store-to-load forwarding is performed without explicitly saving the stored values; (ii) Load-to-load forwarding is performed without saving loaded values in a reuse buffer; (iii) Silent stores are eliminated without saving or loading the prior value stored to the same addresses; (iv) Switching of bits in L1 cache is minimized without saving additional history; and (v) False memory access order violations are avoided without holding speculatively loaded values in the speculated loads table. Our experiments demonstrate that our implementation of non-speculative optimizations is highly effective as it eliminates memory references due to 60\% (58\%) of loads in SPECint95 (SPECfp95) and 25\% (22.6\%) of stores in SPECint95 (SPECfp95). On an average over 45\% of cache references are eliminated due to non-speculative reuse. On an average the L1 switching activity was reduced by 7.75\%.
reuse register file contention detection value value optimality memorialized operability addressing association physical presence paper management memory hierarchies informal combinational implementation forward switch cache access order speculating experience demonstrate effect activation values