fpga synthesis with retiming and pipelining for clock period minimization of sequential circuits
In this paper, we present a new algorithm, named TurboSYN,for FPGA synthesis with retiming and pipelining to minimizethe clock period for sequential circuits.For a target clockperiod, since pipelining can eliminate all critical I/O paths,but not critical loops, we concentrate on FPGA synthesis toeliminate the critical loops.We combine the combinationalfunctional decomposition technique with retiming to performthe sequential functional decomposition, and incorporate itin the label computation of TurboMap to eliminate allcritical loops.The results show a significant improvementover the state-of-the-art FPGA mapping and resynthesis algorithms(1.7 ~ 2 times reduction on the clock period).Moreover,we develop a novel approach for positive loop detectionwhich leads to over 10 ~ 50 times speedup of the algorithm.As a result, TurboSYN can optimize sequential circuits ofover 10 gates and 10{3} flipflops in reasonable time.
synthesis retiming pipeline clock minimal sequential circuits paper algorithm critic decomposition posit functional label computation map timing reduction speedup optimality art