Functionality and stability analysis of a 400mV quasi-static RAM (QSRAM) bitcell
The development of low-voltage SRAM bitcells with ultra-low static power consumption has become a primary focus of memory design in recent years. The analysis of these bitcells requires the evaluation of dynamic noise margin metrics in addition to the traditional static noise margins. In this paper, we extend the presentation of our recently proposed quasi-static RAM (QSRAM) cell that employs an aggressive internal feedback technique for leakage suppression. In addition to the presentation of the QSRAM circuit topology and operation, a broad stability analysis of the cell is introduced, proving the functionality and bi-stability of the bitcell. Many of the recently proposed dynamic stability metrics used in this analysis have been demonstrated on standard SRAM bitcells; however, this is one of the first times these metrics have been used to analyze the functionality of an alternative implementation. Functionality of the proposed bitcell is shown for a sub-threshold 400mV supply voltage, providing a typical leakage reduction of 21X45X as compared to a standard two-port bitcell operating at its nominal voltage. An 8kb QSRAM array was implemented and fabricated in a commercial low-power 40nm process demonstrating full functionality and ultra-low power consumption under a sub-threshold 400mV supply.
sram leakage suppression cmos memory integrated circuits ultra low power sub-threshold sram