low power state assignment targeting two-and multi-level logic implementations
The problem of minimizing power consumption during the state encoding of a finite state machine is considered. A new power cost model for state encoding is proposed and encoding techniques that minimize this power cost for two- and multi-level logic implementations are described. These techniques are compared with those which minimize area or the switching activity at the present state bits. Experimental results show significant improvements.
low power power assignment logic implementation power consumption encode finite state machine cost model cost switch activation experimentation