Transformer: Run-time reprogrammable heterogeneous architecture for transparent acceleration of dynamic workloads
We design run-time programmable on-chip accelerators on a heterogeneous architecture. We design middleware and scheduling algorithms for transparent acceleration. We characterize power consumption of the system with accurate modeling tools. Our study gives insights on the scalability and power-performance trade-offs. We study how system parameters affect the performance and power-efficiency.
heterogeneous architecture transparent acceleration accelerator coarse-grain fpga