high rate soft output viterbi decoder
This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s for worst case process conditions, 8 states, coding rate R=1/2, using a 0.6ym CMOS technology), using the "radix" trellis method (collapsed trellis) to speed up the rate of a soft output decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes", which are a new class of convolutional codes whose performances, in terms of bit error rate, are close to the Shannon limit.
soft output viterbi decoding viterbi decoding collapsed trellis digital communication systems vlsi design high data rates