A fault-tolerant approach to test control utilizing dual-redundant processors
A simple dual-redundant fault-tolerant test control system architecture has been designed, developed, and demonstrated in a real-time environment using inexpensive personal computers. A survey of existing fault-tolerant control systems was performed to assess the relative cost and capabilities of currently available technology. A costbenefit analysis was performed comparing the relative benefit of this system to triplex systems and non-fault-tolerant systems for various applications. Functionally identical implementations of a prototype proof-of-concept software design were constructed in two different languages and tested using a unit-under-test model. Bugs (faults) were injected into this model to verify the ability of the system to reliably detect anomalous test hardware operation. Also, simulated bugs (faults) were introduced to verify smooth control transfer between primary and standby, both nominally and in the presence of hardware-under-tests anomalies. Results indicate significant improvement in system reliability, sufficient to justify the additional cost of the proposed duplex system for many potential users.
fault-tolerant control dual-redundant computing costbenefit triplex primary duplex hot standby