A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates
A new technique called MCSD is presented for reducing the power consumption of wide fan-in dynamic OR circuits. It has shown that in modern technology nodes using the MCSD technique, the power consumption of the OR gates can be effectively reduced without sacrificing other circuit parameters. An important benefit of the proposed approach is 98.7X reduction in power consumption of the gate load by limiting its switching activity. Using the proposed technique, a 40-bit Tag Compotator is designed that its power-delay product is reduced approximately by 49.4%.
wide fan-in power-delay product dynamic logic reduced power