C-based SoC design flow and EDA tools: An ASIC and system vendor perspective
This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design now from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoCs complexity and the timing closure caused by deep-sub-micrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design feature into the C-based SoC design environment. Finally we describe our global vision for an SoC architecture and SoC design methodology.
soc timing closure high-level synthesis high-level verification c-based design dynamic reconfigurable computation floor plan hardware description language hardware/software co-simulation