wiring requirement and three-dimensional integration of field-programmable gate arrays
In this paper analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for 3-D implementation of FPGAs are examined. The analytical models for 2-D FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with 20K 4-input look-up tables, the reduction in channel width, interconnect delay, and power dissipation can be over 50\% by 3-D implementation.
requirements integrability paper model predict interconnect fpga fpga implementation routing placement experience benchmark circuits system-level modeling tables reduction delay power dissipation fpgas field-programmable-gate-array systems input 3-d integrated circuits wire-length