fault modelling and fault equivalence in cmos technology
The need of greater confidence for fault coverage of test sequences for VLSI circuits has led to the proposal of more accurate fault models and test pattern generation tools. Such improvement induces a large increase in fault list to be considered and CPU time to generate test. In this paper, we propose a complete methodology to obtain a minimal set of faults. This methodology is based upon theoretical basis allowing the determination of the equivalence and dominance of non-classical CMOS faults.
fault modelling test pattern generation fault collapsing