On chip interconnects for multiprocessor turbo decoding architectures
Turbo codes are among the most powerful and widely adopted error correcting codes in several communication applications. The high throughput requirements of current and future standards impose that parallel decoders composed by multiple interconnected processing elements are used at the receiver side to efficiently decode turbo codes. In this work, on chip interconnects for multiprocessor turbo decoding are investigated. Due to the dominant trend towards the design of flexible, multi-standard decoders, capable to support the decoding of several turbo codes, the Network-on-Chip approach is seen as a viable and promising solution, although the specific characteristics of the addressed application impose a drastic simplification in the network organization. Both indirect and direct network topologies are studied and experimental results show that a Network-on-Chip based decoder made of 16 processing elements can achieve a throughput of several hundreds of Mbps. Moreover, the area required by the network compares favorably with previously published works on flexible interconnect architectures for turbo decoding and the cost overhead of NOC based solutions with respect to a fully dedicated implementation is limited to 13%.
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