An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
A pipelined architecture is developed for a Sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The promising feature of the proposed SMC receiver is achieving the near-bound performance in fading channels without using any decision feedback, training or pilot symbols. The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks, i.e., the SMC core, weight calculator, and resampler. Hardware efficient/parallel architectures for each functional block including the resampling block is developed. The novel feature of the proposed architecture is that makes the execution time of the resampling independent of the distributions of the weights. Despite the alternatives in the literature, the proposed scheme achieves a very small execution time by pipelining the resampling and sampling steps. Moreover, it is scalable for high levels of parallelism, has lower memory usage, fixed routing time, and has close to the ideal performance. Finally, an ASIC implementation of the resampling core is presented in a 0.13 ?m CMOS technology, which operates at 200 MHz with 0.8 mm2 of silicon area.
sequential monte carlo vlsi architecture wireless channels