low jitter audio range pll with ultra low power dissipation
This paper presents the design of an ultra low power Phase-Locked Loop (PLL) intended for applications in the extended audio range. The PLL is well suited for battery operated systems, where small size and low power operation are crucially important. The presented implementation is based on a current controlled relaxation oscillator, which creates a sawtooth output with a frequency range of approximately 300 kHz. The frequency is controlled by a current that can vary from 2 to 74 nA. Using a reference frequency of  of the typical watch crystal frequency, the user can select any integer multiple of 8.192 kHz up to the maximum of 122.88 kHz. The PLL circuit operates from a single 3 V supply and, depending on the actual output frequency, dissipates between 0.9 -1.4 W of power.
plls phase jitter low power cmos design