Degradation of n-channel low temperature poly-Si TFTs dynamically stressed in OFF region with positive drain bias
The degradation characteristics of n-channel low temperature poly-Si thin film transistors (LTPS TFTs), which are alternately stressed in OFF region with drain positively biased and source grounded, are investigated. In this research, rectangular pulse signals, dynamically changing from ?18 to 0V with varied parameters such as rising time, falling time, and frequency, are applied to the gate terminal, and the drain is simultaneously biased at +5V to stress the LTPS TFTs and examined the deterioration. It is observed that the degradation strongly depends on the frequency and rising time rather than the falling time of AC signals. As the gate voltage transitionally changes in the rising period, the accumulated holes should be swept out and flow into the source terminal, resulting from the drain with positively biased and the floating body structure of TFTs. A degradation model of the parasitic BJT, based on the flowing direction of a sampling current Id, is proposed to explain the degradation mechanism of LTPS TFTs, and demonstrated by two electrical measurements, CV curves and saturated forward and reverse IdVg transfer curves.
low temperature poly-si sampling current thin-film transistors ac stress reliability