Locally clocked pipelines and dynamic logic
Micropipelines and most of its variants use a delay-insensitive controller to moderate a pipeline. In search of improved performance, we depart from the delay-insensitive model in favor of a bounded-delay model for the controller. In particular, we demonstrate how a general delay-insensitive controller for level-sensitive pipelines can be improved by assuming a bounded-delay model and taking advantage of delay information to make the controller faster and more efficient. The new control scheme is referred to as locally clocked (LC) control. A highly pipelined logic technique called LC dynamic logic is presented that combines the bounded-delay controller with a latching dynamic logic gate design. Simulations comparing LC control with its delay-insensitive counterpart are presented. Also, an 8 x 8 bit multiplier with a maximum frequency of 715 MHz for a 1 mum CMOS process that uses LC dynamic logic is presented.
locally clocked (lc) control asynchronous pipelines digital complementary metal-oxide-semiconductor (cmos) dynamic-logic circuit high performance multiplier design