testing scheme for ic's clocks
This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.
testing skew clock signal digital synchronous ic cmos sensing circuit failure on-line testing cmos digital integrated circuits off-line testing