ON EMBEDDING TEST PATTERNS INTO LOW-POWER BIST SEQUENCES
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise unnaturally the power consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray code generators is proposed as a low-power BIST solution; starting from the concept of embedding test patterns into such sequences, we investigate various alterative generators. Experimental results indicate that such generators can result into realistically short lower-power BIST sequences, as compared to other solutions proposed in the open literature.
built-in self test test set embedding gray sequences low power sequences