A Defect Localization Scheme for Cellular Nanocomputers
Computers with device feature sizes of a few nanometers-so-called nanocomputers-are expected within a few decades, but this expectation is accompanied by the realization that the boundary conditions of such systems differ substantially from those of current VLSI-based computers. Prominent among the concerns is the increased degree of permanent defects that will affect nanocomputers, such as defects caused by imperfections at the manufacturing stage, but also defects occurring later, possibly even during the use of these systems. New techniques to deal with defects are called for, but given the huge number of devices involved, such techniques may need to be self-contained: they need be applicable at local levels without outside control, even while computations continue to take place. This paper proposes an important element in such techniques, i.e. the localization of defects among a huge number of devices. It employs a cellular automaton-based architecture, and uses statistical techniques combined with randomly moving configurations in the cellular space to estimate defect locations.
cellular automata defect tolerance asynchronous nanotechnology biased random walk