hpex: a hierarchical parasitic circuit extractor
A hierarchical parasitic circuit extractor HPEX for Manhattan layouts is described. HPEX can model interconnection lines as distributed lumped circuits directly from a circuit layout by using analytical formulas instead of numerical methods. The difference in feature sizes between mask layouts and actual fabricated conductors is also taken into account by a geometrical preprocessing algorithm based on a novel Y-X scanline method and a simple rectangle data structure. In addition, a simple and accurate node reduction technique based on the concept of Elmore's delay is employed in HPEX to make layout verification simpler. All features mentioned above clearly indicate that HPEX will be a promising tool in verifying VLSI system performance especially when interconnect parasitics associated with VLSI circuits are taken into consideration.
hierarchic circuits layout model interconnect distributed method feature account algorithm data structures reduction concept delay verification tool systems performance association