minimizing peak power in synchronous logic circuits
Minimizing peak power decreases the probability of failure due to hot carrier effects and electromigration. It also reduces the maximum IR voltage drop, the magnitude of substrate noise, and packaging costs. In mobile applications, minimizing peak power can help reduce the battery size. In synchronous circuits the peak power draw is correlated with clock transitions when the entire clock distribution network, all of the flip-flops and their immediate fanout switch simultaneously. In this paper, we propose an efficient, deterministic method for finding the optimal distribution of clock latencies for minimizing peak power consumption. Our algorithm spreads the clock transitions using timing slacks on non-critical paths and preserves the circuit performance. We validate our method by transistor level simulations on benchmark circuits. These experiments show that our method can reduce the peak power consumption up to 55 percent in circuits whose peak power is due to simultaneous clock transitions.
peak power clock scheduling power optimization