An improved constant coefficient multiplication algorithm based on cascaded adder graph
In many digital signal processing algorithms, e.g., digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work a new algorithm of constant coefficient multiplication with few adders and registers is proposed. This approach is based on cascaded adder graph. In this paper all cascaded adder graph structures for any integer can be derived, and the analytical method for the number of register and adder occupation is given. Through comparison of occupied resources, the optimal adder graph can be obtained. Finally, comparing with previous optimal algorithms, a design example for finite impulse response (FIR) filter confirms the validity and good engineering practicability of this algorithm.
constant coefficient multiplication cascaded adder graph finite impulse response (fir) resource occupation adder-step