A difference reference voltage buffer for Delta Sigma-converters
An open loop architecture for a reference voltage buffer in DeltaSigma-converters is presented to achieve fast-settling, since the settling time of the references plays an important role in the global performance of sampled data converters. This design has been tested on a 2-1 DeltaSigma-converter with an on-chip bandgap reference increasing the input related dynamic range up to 93.4 dB for a bandwidth of 99 kHz.
converters analog design reference buffers