Linearization technique using bipolar transistor at 5GHz low noise amplifier
A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18m CMOS process. At 5GHz, the proposed LNA achieves a measurement results as 16dBm of IIP3, 10.5dB of gain, 2.1dB of noise figure, and 8mW of power consumption.
low noise amplifier (lna) high linearity third-order input intercept point (iip3) rf integrated circuits nonlinearity