HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures
Dual supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOS circuits. In this paper, we propose a comprehensive design framework that includes dual-scheduling, dual-allocation, controller synthesis as well as layout generation. In particular, we address a problem of high-level synthesis with objective of minimizing power consumption of storage units and multiplexers using dual-V-dd; this is made possible by utilizing timing slack that is left in the data-path after operation scheduling. We use integer linear programming (ILP) and also provide heuristic algorithms to solve the dual-register and connection allocation. The physical layout of dual-circuits has to separate power rails of V-ddh and V-ddl cells from each other. We propose a voltage island based placement algorithm to relieve this restriction and allow more flexibility of placement. In experiments on benchmark designs implemented in 1.08 V (with V-ddl of 0.8 V) 65-nm CMOS technology, both switching and leakage power are reduced by 20% on average, respectively, compared to data-path with dual-V-dd applied to functional units alone. Detailed analysis of area and wirelength is performed to assess feasibility of the proposed method.
dual supply voltages high-level synthesis (hls) low power register allocation