VLSI design of 1-D DWT architecture with parallel filters
Wavelet transform coding has been drawing much attention because of its ability to decompose images into a hierarchical structure that is suitable for adaptive processing in the transform domain. This paper presents an Efficient VLSI design of one-dimensional direct discrete wavelet transform processor. The proposed architecture computes three DWT stages and uses four parallel filters. The architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one storage unit, four filters, and a control unit. No memory or registers are used for storing intermediate results. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7106 samples/s corresponding to a typical clock speed of 7MHz. The architecture is simulated and verified at the gate level in VLSI. Process parameters used were those of 0.6?m technology. The chip area is about 15.7mm2.
vlsi design parallel filters discrete wavelet transform new optimized architecture dwt processor