Partial error tolerance for bit-plane FIR filter architecture
Whereas some applications require correct computation many others do not. A large domain where perfect functional performance is not always required is multimedia and DSP systems. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. The goal of this paper is to develop a method for trading computational correctness for an additional chip area involved by fault-tolerance implementation. The method is demonstrated for the BP array in the following way: only the most significant bits of the output word are made fault-tolerant. By introducing the concept of partially error-tolerant BP array, designers achieve one more degree of tradeoff freedom. Formal definitions of the proposed terms are given. A mathematical path based on transitive closure that generates an error significance map for the BP array is proposed. The design tradeoff is demonstrated through FPGA implementation. The achieved area savings are presented as a function of a number of most significant fault-tolerant bits.
error tolerance fir filtering fault tolerance systolic arrays