energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
In this paper, we present an approach for low--power driven synthesis based on local frequency/voltage scaling. During the scheduling phase of the High--Level Synthesis (HLS) the design is partitioned into different frequency/voltage islands. Operators within these islands, are encapsulated by wrappers to ensure correct dataflow between the islands. A wrapper consists of a clock generator and input- and output ports. The local clocks are calculated by dividing the global clock signal. With the developed wrappers we are able to automatically integrate local frequency/voltage scaling for our target architecture by our HLS tool. As an example we implement the inverse discrete cosine transformation (IDCT).
voltage scaling low power design bit-serial architecture high-level synthesis