solving the i/o bandwidth problem in system on a chip testing
The first part of this paper describes the control of CAS-BUS, a P1500 compatible Test Access Mechanism (TAM). Boundary scan features are used to allow controlling of the TAM and the P1500 wrappers. The final architecture characteristics are its flexibility, scalability and reconfigurability. It also allows trade-off to optimize test time and area overhead. The second part deals with a test pin expansion method in order to solve the bandwidth problem. The solution we propose is based on a new compression/decompression mechanism which avoid TAM performances degradation.
i/o bandwidth problem system on a chip testing p1500 compatible test access mechanism boundary scan features p1500 wrappers architecture characteristics flexibility scalability reconfigurability test pin expansion method compression/decompression mechanism data compression logic testing microprocessor chips test time optimisation cas-bus tam performances degradation avoidance soc testing area overhead optimisation vlsi boundary scan testing automatic testing integrated circuit testing