Error correcting encoders for parallel-type ADCs
Full-parallel and folding and interpolation (F&I) ADCs have a bank of latched comparators, the output of which is a "thermometer code" in full-parallel ADCs and a "circular code" in F&I ADCs. These special codes have to be transformed into a binary code. Nonideal effects can originate more than one "0" to "1" transition in the thermometer or circular code, causing large errors in the output binary code. A comparison of existing error correction techniques is presented in this paper, which shows that 1st order error correction provides considerable performance improvement, without a significant increase of circuit complexity. Higher order correction in full-parallel ADCs using Wallace tree encoding is very effective, but has a high cost in terms of circuit area and power consumption. In this paper it is shown that Wallace tree encoding can be extended to F&I ADCs, and that this leads to a very compact circuit for higher order error correction in low and medium resolution ADCs. This is demonstrated by designing and simulating a 6-bit, 200 Msample/s F&I ADC which has low power consumption and a small area.
analogue-to-digital converters parallel adcs folding & interpolation adcs adc error correction