design challenges for mobile communication devices
System on Chips (SoC) for mobile devices, such as GSM/EDGE/UMTS, have strongly conflicting requirements. On one hand the demand for processing performance is steadily increasing with every new standard and on the other hand extremely low power dissipation is demanded. The performance demands vary strongly, depending on the phone modes and activities e.g. stand-by mode vs. talk mode vs. high performance application modes such as video processing and gaming.Next to the development of new telecommunication standards the silicon technologies develop according to the shrink path. Scaling of physical structures, especially the gate thickness, induces larger leakage in DSM technologies. The shrink is accompanied with a further reduction of supply voltage that helps to reduce the dynamic power dissipation but also reduces the leverage of performance improvement. To reduce the leakage and to reach the targets of design projects new low power measures have to be defined and implemented by integration into technology, libraries, design tools, and the design flow.In recent years several low power features have been developed to address both the static leakage power consumption and the dynamic active power consumption. These features, or a combination of them, can be tailored to dynamically varying performance needs of the SoC in different modes meaning different use cases.
soc leakage design for low power