a high level synthesis tool for mos chip design
This paper describes a design tool called Functional Design System (FDS) that supports high level MOS LSI design. Designers can build circuits at the register transfer level by using a set of high level FDS primitives. FDS then automatically produces in seconds an accurate and efficient polycell implementation for these primitives. Therefore, the design cycle time can be reduced significantly. FDS is an integral part of a larger CAD system [1] which supports other aspects of the design cycle, namely, graphical design capture, simulation, test generation, and layout. The system has proved to be highly successful in helping designers to develop extremely reliable chips in a short time frame.
high level synthesis tool design paper design tool functional systems circuits efficiency implementation timing integrability aspect graphic design simulation test generation layout reliability