analyzing testability from behavioral to rt level
e Abstract: In this paper, we present a method for analyzing the testability of a circuit during high level synthesis. The testability analysis returns values that represent the relative difficulty for computing test data, whatever the level of description of a circuit is (from the behavioral level-initial specification-down to the Register Transfer Level-high level synthesis output-). Experiments show the good correlation of the so-obtained testability measures with gate-level testability measures (e.g. Scoap). The proposed measures are used to guide high level synthesis towards the generation of easily SATPG testable datapaths.
high level synthesis scoap satpg datapath circuit testability circuit testing register transfer level behavioral level