A 6.9mA 5 bits 90nm 1GS/s ADC without calibration for UWB application
Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1Gs/s ADC without calibration, realized in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9mA from a 1.2V supply.
adc calibration