Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network
A power and latency efficient scheme for on-chip network communication is presented and its performance is analyzed. This new scheme is designed for a general architecture with a buffered/bufferless router (BR/BLR), which eliminates buffers in the majority of routers to achieve power efficiency while keeping buffers in a few routers to facilitate various desirable services and to reduce latency. Extensive simulation shows that the proposed scheme performs better than purely bufferless as well as buffered approach under different synthetic traffic patterns.
bufferless power efficient network-on-chip multicore