An improved branch and bound algorithm for exact BDD minimization
Ordered binary decision diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of the BDDs depends on a chosen variable ordering, i.e., the size may vary from linear to exponential, and the problem of improving the variable ordering is known to be NP-complete. In this paper, we present a new exact branch and bound technique for determining an optimal variable order. In contrast to all previous approaches that only considered one lower bound, our method makes use of a combination of three bounds and, by this, avoids unnecessary computations. The lower bounds are derived by generalization of a lower bound known from very large scale integration design. They allow one to build the BDD either top down or bottom up. Experimental results are given to show the efficiency of our approach.
binary decision diagram (bdd) logic synthesis exact minimization pass transistor logic