a new approach to logic synthesis of multi-output boolean functions on pal-based cplds
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CPLDs. The presented approach is an alternative to the classical method based on two-level minimization of separate single-output functions. The essence of the presented method is to search for multi-output implicants that can be shared by several functions. This approach presents a original form for illustrating a minimized form of a multi-output Boolean function. Graph node represents groups of multiple-output implicants with the common output part. The graph analyses allow to effective implementation of multi-output function in PAL-based devices. Results of experiments, which are also presented, prove that the proposed algorithm leads to significant reduction of chip area in relation to the classical method, especially for CPLD structures consisting of PAL-based logic blocks containing low number of product terms.
logic synthesis cplds technology mapping