Simulations and measurements of capacitance in dielectric stacks and consequences for integration
In this paper simulations and measurements of capacitance in dielectric stacks of dual damascene architecture are presented, and consequences for integration are discussed. Hard mask (HM) properties as thickness and relative permittivity (k) are taken into account together with the geometry of the dual damascene architecture to study their influence on the effective permittivity (keff), RC delay and cross-talk resulting from the dielectric stack. It is shown that a careful choice of the thickness and k-value of the hard masks is necessary to obtain an important decrease in keff. Decreasing the via height results in a small RC-delay increase but also in an important cross-talk decrease. Finally, comparison between measured and simulated single damascene structures is reported.
damascene hard mask effective permittivity cross-talk rc-delay