A novel eigenvector technique for large scale combinatorial problems in VLSI layout
Modern integrated circuit design involves laying out circuits which consist of millions of switching elements or transistors. Due to the sheer complexity, optimizing the connectivity between transistors is a very difficult problem. How a circuit is interconnected is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size and cost. These factors dictate that interconnections-wires, be made as short as possible. The wire-minimization problem is formulated as a sequence of discrete optimization subproblems. These problems are known to be NP-hard, hence they can only be solved approximately using meta-heuristics or linear programming techniques. Nevertheless, these methods are computationally expensive and the quality of solution depends to a great extent on an appropriate choice of starting configuration. A matrix reordering technique for solving very hard discrete optimization problems in Very Large Scale Integrated (VLSI) design which overcomes some of these shortcomings is proposed. In particular, the computational cost is reasonable-of the order of n(1.4) running time.
eigenvectors vlsi layout combinatorial optimization linear relaxation partitioning global routing