design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power should not decrease design performance. Therefore, an enhanced Dual Vth/Dual Tox CMOS ap-proach is presented which applies mixed gates consisting of different transistor types. The paper introduces the new and fundamental idea of different gate types before the various possible configurations are analyzed. This is followed by extraction and exploration of design rules and recommendations. Simulations of modified ISCAS'85 designs show an average leakage reduction of 60\% at constant performance compared to raw designs. This corresponds to an additional reduction of 20\% compared to previous Dual Vth/Dual Tox CMOS approaches.
mixed gates gate leakage leakage current threshold voltage