Floorplan-aware analog IC sizing and optimization based on topological constraints ?
Fast floorplan generation using topological constraints for circuit synthesis. Usage of multiple templates to increase the floorplan quality. Wide range of solutions obtained from the multi-objective circuit optimization. Complete design flow demonstrated for the UMC 130nm design process. Circuit evaluation using the industrial simulators tool (ELDO, HSPICE, Spectre).
electronic design automation analog integrated circuits floorplan-aware circuit sizing automatic module generator multi-objective optimization