Simulation and verification of void transfer patterning (VTP) technique for nm-scale features
This paper investigates simulation of a patterning technique for defining sub-lithographic features. The technique studied involves intentional creation of voids using a conformal chemical vapor deposition (CVD) followed by controlled etch-back to form nanoscale pores. This method provides features that are independent of lithographically defined parent holes and exhibit lower critical dimension (CD) variations. It offers efficient low thermal budget and backend process compatible integration scheme that requires just one additional mask level. The void diameter obtained in this work is 74nm i.e. ?10 reduction from lithographically defined hole of 714nm using i-line lithography. Critical parameters affecting the void formation and the final pore size have been identified and modeled. Simulation of the void transfer process has been investigated using plasma etch module of Elite by Silvaco that employs 2-D Monte Carlo ion transport modeling. The results of this investigation show that the geometrical design parameters can be coupled with the plasma process simulations to develop an efficient module for the void transfer process.
plasma etch simulation topography simulation void patterning technique