on-chip em-sensitive interconnect structures
Due to ever greater current densities in modern IC designs, electromigration (EM) in copper interconnects has become an important reliability factor. In this paper, we analyze current densities on bus and clock networks. We observe that under certain conditions, these networks may become sensitive to EM effects and prone to failure. We perform SPICE simulations on open source Wishbone bus and non-tree clocks for IBM and ISCAS89 benchmarks. Experiments on these networks show that on some wire segments current may flow predominantly in one direction and its density may exceed the maximum allowed values suggested by the International Technology Roadmap for Semiconductors (ITRS). When power network experiences noise, the links of a non-tree clock may carry currents whose densities could be 100 times greater than those of the tree branches. In our study, we compare various methods of reducing the EM effect on interconnects. We demonstrate that in comparison to such design methods as increasing wire widths, reducing circuit frequency or decreasing driver sizes, the technology-based solution of capping copper (Cu) wires with cobalt tungsten phosphide (CoWP) coating works best and eliminates EM violations without area overhead, performance loss or additional design effort.
electromigration non-tree clock cowp unidirectional current tri-state bus power noise