hardware acceleration of gate array layout
In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large private memory. One or more such slaves can be attached. We have implemented placement improvement on the system, achieving a 20 x speedup vs. a high-level host implementation. We give performance results, which are comparable to those reported elsewhere for mainframe implementations.
hardware acceleration hardware arrays layout paper software systems implementation physical design processor memorialized placement speedup performance general user