Design of efficient architectures for 1-D and 2-D DLMS adaptive filters
This paper presents a design of systolic array architectures for 1-D and 2-D finite impulse response adaptive filters. The design is based on the delayed least mean squares algorithm (DLMS). Two designs have been proposed and their performance is analyzed in terms of speed up, adaptation delay and throughput. The second realization results in a lowest critical period equal to one multiply operation time and a higher throughput. Unlike the existing architectures the adaptation delay of this design is independent of the filter length and has a higher speedup. It is shown that the convergence performance of this design is in par with the conventional LMS algorithm.
adaptive filters equalization 2-d dlms algorithm systolic architectures