an analysis of the robustness of cmos delay elements
In this paper, we review three different families of delay elements used in CMOS VLSI design: (1) transmission gate based, (2) cascaded inverter based, and (3) voltage-controlled ones. We compare their effectiveness in terms of yield , which is defined as the number of delay elements that have delays within a specified delay range. The delay variations are obtained through HSpice Monte Carlo simulations and are analyzed using analytical delay expressions. The sensitivity of the delay elements to different process and environmental variations can be studied using the simulation results. This will enable designers to select the best delay element for their design and also do a robust design by taking into account the sensitivities of delay elements to different parameters.
delay element yield monte carlo simulation process variation