combining module selection and resource sharing for efficient fpga pipeline synthesis
In FPGA designs significant area savings can be achieved by using slower, more area-efficient circuit modules or by time-multiplexing faster circuit modules. Unfortunately, the ability of designers to manually make such trade-offs is limited by the large number of different architectural possibilities. In order to automatically perform these trade-offs, we have developed a synthesis methodology that generates pipelined data-path circuits from a high-level data-flow specification. This methodology is capable of selecting among a variety of circuit implementations for each operation, a synthesis technique often called module selection , and generating control logic to time multiplexing each circuit module, a synthesis technique often called resource sharing . These techniques are applied together to minimize the area cost of the resulting circuit while meeting a user-specified minimum throughput constraint. We show that even for small benchmark circuits, combining these techniques can offer significant area savings relative to applying them alone.
module selection resource sharing data-path synthesis pipeline scheduling