A temperature-insensitive self-recharging circuitry used in DRAMs
This paper presents a practical self-recharging circuitry for DRAMs. The proposed self-recharging circuitry not only reduces the standby power by monitoring the voltage drop caused by the data loss of a memory cell but also adjusts the recharging period of the memory cell that results from leakage currents. The proposed design is insensitive to temperature variations. A 1-Kb DRAM using our design is fabritcated by a TSMC 0.35-mu m 1P4M CMOS process. The physical measurement of the proposed design on silicon verifies the correctness of the proposed circuitry.
self-recharge dram adaptive self-recharging circuitry