Legalizing a placement with minimum total movement
Most tools for the placement of very large scale integrated chips work in two steps. First, the cells that have to be placed are roughly spread out over the chip area, ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization). In this paper, we describe new ideas for legalization. We divide the task into appropriate subproblems that can be solved to optimality in polynomial time. For the most important parts, even a linear running time can be shown. Together, the solutions of the subproblems can be combined to an algorithm that legalizes a placement minimizing the total (linear or squared) movement of cells. The algorithm is tested on a set of recent application specific integrated circuits and the results are compared to lower bounds showing that it computes provably good solutions (within a few percent of the optimum) even on very large industrial chips. By introducing significantly fewer violations, our legalization helps in overall design closure.
design automation integrated circuit design physical design placement legalization very large scale integration (vlsi) vlsi placement