A high-speed rail-to-rail output buffer with push-pull dual-path and dynamic-bias for LCD driver ICs
The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push-pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 mu m CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 mu W, with settling times of 0.7 and 0.68 mu s for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 x 48 mu m(2).
push-pull dual-path dynamic-bias tft-lcd rail-to-rail current mirror amplifier class-ab output stage auxiliary output stage