A coarse-grain phased logic CPU
This paper describes an asynchronous design tool flow known as Phased Logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18&mu; and 0.13&mu;) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13&mu; library. The design style includes a feature known as early evaluation, which is a generalized form of bypass, that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.
asynchronous micropipelines self-timed automatic synthesis pipelined processor