energy-efficient register access
We present and evaluate seven techniques to reduce energy dissipation for accesses to a processor register file: modified storage cell avoids bitline discharge for zero bits, precise read control avoids fetching unused operands, latch clock gating disables latch clocks when operands are not needed, bypass skip turns off regfile reads when bypass circuitry will supply the value, bypass RO treats accesses to RO separately, split bitline reduces access energy for frequently-used registers, and read caching avoids regfile reads when the same register is read twice in succession. For a 0.25 /spl mu/m CMOS three-port regfile, we find individual energy savings of 27\%, 21\%, 8\%, 16\%, 14\%, 12\%, and 1\% respectively and a combined saving of 59\% when all seven techniques are used in combination. The total area overhead is around 17\% and the total delay overhead is around 3\%.
energy-efficient register access access evaluation value energy dissipation energy processor register file processor register file modified storage cell storage precise precise read control read control latch clock gating clock gating clock bypass skip regfile reads bypass circuitry bypass ro split bitline read caching caches cmos three-port regfile energy savings combinational total area overhead total delay overhead delay pipelined risc processor 0.25 micron embedded systems reduced instruction set computing cmos digital integrated circuits microprocessor chips pipeline processing low-power electronics energy efficiency