Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase
Vt instability at steady phase is attributed to lateral charges transport model. Higher P/E cycle counts increase Vt instability at steady phase. Higher bake temperatures enhance Vt instability at steady phase. Cycling alters trapped charge profile that dictates Vt instability at steady phase.
threshold voltage instability charge trapping non-volatile memory activation energy data retention nanoscale semiconductors