a framework for interactive analysis of timing constraints in embedded systems
An important goal of embedded system co-synthesis is to realize system designs under constraints on timing performance. We present applicable constraints and the notion of satisfiability of a given set of constraints. We describe a two-level system model that is useful for carrying out constraint analysis in presence of the timing and execution uncertainty inherent in embedded systems. We conclude by presenting a framework to determine constraint satisfiability and to interactively debug constraint violations. Examples are presented to show the utility of our approach.
interactive analysis analysis timing timing constraints constraint embedded systems systems design timing performance performance present satisfiability system modeling presence uncertainty constraint satisfiability debugging examples utility  framework  real-time systems computability performance evaluation synthesis logic design