Safe integration of parameterized IP
In order to be reused in different applications Intellectual Properties (IP) are usually parameterized. On the one hand the extensive use of parameters enables users to customize IP to their needs in different applications. On the other hand a large number of parameters imposes new problems during IP qualification, verification and integration. This article gives an overview of the present work in the IP Qualification Project (IPQ) addressing problems due to IP parameterization. We are working on solutions to handle large parameter sets, to automatically implement parameter checking, and to improve functional coverage of the parameter space. Within this scope, a novel graph-based methodology to split the parameter space into orthogonal subspaces has been devised. On the basis of a formal description of parameters and their interdependences so-called Parameter Domain Graphs (PDG) are constructed. Relying on PDG, testbench components for assertion-based parameter checking are automatically generated. Furthermore, generation constraints for verification environments are derived and collection and analysis of functional coverage data is implemented.
parameter intellectual property verification functional coverage interdependences parameter domain graph system-on-chip design