A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The compression algorithm must be simple for hardware implementation; a common method is to store only the difference between the previous value and the current one. Such differential compression has trouble with the circular buffer that is needed for recording continuous traces. Previous solutions are complex and waste memory. By a transformation that expresses differential compression in reverse form, we derive a new solution that is simpler than previous methods and does not waste memory. Our algorithm is based on an innovative reverse-encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a real-time on-chip advanced high-performance bus tracer and has been embedded in a 3-D graphics system-on-a-chip as an application example. The bus tracer costs only 44 K gates and runs at 500 MHz in TSMC 0.13-mu m technology. Experiments have shown that our bus tracer achieves 100% circular-buffer utilization and captures 4.86 times trace depths as compared with a conventional industrial approach.
compression circular-buffer management forward encoding posttrigerring (post-t) trace pretriggering (pre-t) trace real-time trace reverse encoding system-on-a-chip (soc) debugging