Temperature and annealing effects on InAs nanowire MOSFETs
We report on temperature dependence on the drive current as well as long-term effects of annealing in vertical InAs nanowire Field-Effect Transistors. Negatively charged traps in the HfO2 gate dielectric are suggested as one major factor in explaining the effects observed in the transistor characteristics. An energy barrier may be correlated with an un-gated InAs nanowire region covered with HfO2 and the effects of annealing may be explained by changed charging on defects in the oxide. Initial simulations confirm the general effects on the IV characteristics by including fixed charge.
annealing inas nanowire mosfet hfo2 fet high-k iiiv semiconductor