title: A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip
abstract: A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18- mu m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW
keyphrases: reconfigurable bus embedded DRAM macros 8-pixel-parallel rendering logic low power consumption polygon-dependent access line-block mapping read-modify-write data transaction CMOS embedded memory logic technology 120 mW low-power 3D rendering engine three-dimensional rendering engine mobile PDA chip mobile personal digital assistant chip 3D graphics rendering 6 Mbit 3.2 GB/s 0.18 micron