The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design
Abstract
Placement and routing are two critical yet time-consuming steps of chip design in modern VLSI systems.
Distinct from traditional heuristic solvers, this paper on one hand proposes an RL-based model for mixed-size macro placement, which differs from existing learning-based placers that often consider the macro by coarse grid-based mask.
While the standard cells are placed via gradient-based GPU acceleration.
On the other hand, a one-shot conditional generative routing model, which is composed of a special-designed input-size-adapting generator and a bi-discriminator, is devised to perform one-shot routing to the pins within each net, and the order of nets to route is adaptively learned.
Combining these techniques, we develop a flexible neural pipeline, which to our best knowledge, is the first joint placement and routing network without involving any traditional heuristic solver.
Experimental results on chip design benchmarks showcase the effectiveness of our approach. Source code will be made publicly available at: https://github.com/Thinklab-SJTU/EDA-AI
Introduction
The scale of integrated circuits (ICs) has been enlarged dramatically, posing a challenge to the existing Electronic Design Automation (EDA) technologies.
The increasing circuit density raises additional issues for VLSI placers and routers as the component size of modern VLSI design continues to drop and on-chip connectivity becomes increasingly sophisticated.
Due to growing on-chip connectivity, concentrated needs and restricted resources, modern designs are prone to congestion issues and wirelength minimization, which has become a critical task at every stage of the chip design process.
Accordingly, placement and routing that physically arranges the locations and the routes of nets become more crucial in modern VLSI systems, which are also very time-consuming.
The components of a netlist, including macros and standard cells, are mapped to positions on the chip layout by placement, with standard cells being basic logic cells (e.g. logic gates) and macros as functional blocks (e.g. SRAMs).
Moreover, the increasingly extensive use of intellectual property (IP) modules and pre-designed macro blocks make mixed-size placement an indispensable part of physical design.
The goal of placement is to optimize power, performance, and area (PPA) metrics meanwhile obeying the constraints e.g. placement density and routing congestion.
It is worth noting that, in this paper we address the global routing problem, while the detailed routing involves more physical constraints, and is beyond the scope of this paper.
Global routing, on the other hand, creates routing channels inside a layout based on the placement assignment by connecting pins of positioned IC components to a net while adhering to technological limits.
It is tightly coupled with the placement task, as an excellent placement solution can result in better chip area utilization, timing performance, and routability etc.
The objective of routing is to minimize total wirelength without violating the limits of congestion and critical timing.
Differing from the traditional learning-free solvers for placement and routing, learning-based models are recently explored and applied to (macro) placement [1, 2] and routing [3], which are mostly based on reinforcement learning (RL).
Like in vision, language and other domains, an end-to-end network is often welcomed for the possibility for global optimization of the whole system, while such pure neural networks for joint placement and routing remains unresolved in literature.
In particular, there are two standing issues worth further study in this paper: i) the macros are of mixed-size with varying width/height [4], bringing difficulty to the discrete grid-based placement by (current reinforcement) learning; ii) the scale of grid size in routing dataset e.g. ISPD-07 [5] can be intractable for RL as currently its action has to be designed at the local grid point level [6] rather than generate the whole routing across grids in one shot.
In this paper, we aim to develop a flexible (mixed-size friendly) approach.
More ambitiously, we further aim to enable a pure neural pipeline with both learnable placement net and routing net.
Specifically, the placement part is fulfilled by a policy gradient based
RL method for macros by considering their sizes, followed with gradient-based optimization for placing stand cells.
The routing part involves a conditional generative model to finish the routing across pins at net level.
The highlights of this work are:
1) We propose an RL-based model for learning mixed-size macro placement, which differs from existing learning-based placers [2, 1, 7] that often consider the macro by coarse grid-based mask.
As such, the placement results are more realistic and require less post-processing to resolve collision.
We propose a conditional generative routing network to perform routing, in one-shot for each net.
In contrast, existing RL-based solvers [6] need to perform routing step by step at grid point level within each net, in a sequential and inefficient manner.
Moreover, the order for nets to route is adaptively optimized by learning instead of a pre-fixed one as performed in existing routers.
3) Combining these techniques, we develop a neural network-based pipeline for placement and routing, which to our best knowledge, is the first pure neural networks for placement and routing 2 .
4) Experimental results on benchmarks show the relatively cost-efficiency (compared with RL-based routing solver [6]) and competitive performance.
Source code will be made publicly available.
Related Work
For the inter-discipline nature of this paper, we briefly introduce the necessary background and related work to properly position our work with different communities from EDA to machine learning.
Due to page limit, classical methods for placement and routing are presented in Appendix A.1.
Learning-based Solvers for Placement.
Machine learning has recently been introduced in placement which may help reduce the heuristics.
[7] devises a cyclic framework between reinforcement learning (RL) and SA modules, in which the RL module alters the relative spatial sequence between circuit components, while SA searches the solution space based on RL initialization.
Following the seminal work [1] of learning sequential decision-making for macro placement, the method called DeepPlace in [2] proposes a joint learning technique for the placement and subsequent routing via RL.
Learning-based Solvers for Routing.
The recent work [8] presents an attention-based RL method for obtaining pin order within each net (rather than net order in this paper which is of much larger size), followed by a classical pattern router.
A DQN agent [6] is developed to decide on the routing direction on a grid graph at each step.
It makes up a simple 12-element vector to represent the state of the environment.
However, the model is trained on synthesized 8 × 8 and 16 × 16 grids, with no more than 50 nets that consist of 2 or 3 pins.
To make the learning more scalable, a two-page preliminary work [9] formulates the routing of a net as an image-to-image translation and uses a variational auto-encoder (VAE) [10] model to generate the result.
However, the model is merely capable of handling a net with no more than three pins on a 64 × 64 grid.
Compared with classic routing solvers, existing RL-based methods can be much more time-consuming, making the end-to-end learning of both placement and routing nets very difficult.
Moreover, compared with [8] learning the pin order inside a net, we try to learn the order for routing at the net level which is new in literature.
Generative Models for Placement and Routing.
There are emerging works on introducing generative models for chip design.
[11] proposes a generative adversarial network (GAN) [12] guided well generation framework to mimic experts’ behavior from high-quality manually-crafted layouts. [13] adopts a GAN for generating wells and guides the placement in analog circuit layout synthesis. [14] proposes a generative model for the placement optimization of analog integrated circuit basic blocks.
ThermGAN [15] treats the thermal map estimation problem as an image-generation problem using the generative model.
[16] uses GAN to predict the congestion heatmap to assist classical routers.
The work [17] proposes a conditional GAN to solve the multi-terminal path-finding task.
In [18] the generative models are adopted to synthesize diverse layout patterns.
More broadly speaking, generative models have also been recently applied in combinatorial optimization, specifically via a latent space learning and search scheme as done in CVAE-Opt [19].
In this paper, we adopt cGAN to generate routes in one shot for each net by regarding the layout to be routed as an image.
To our best knowledge, no generative model has been successfully devised and applied to the pin routing problem for each net, which in fact involves complicated and constrained routing.
Methodology
Approach Overview.
Given a netlist as input, the goal of placement is to place the macros and standard cells on the chip canvas, ideally with a minimized overlapping areas.
Based on the placement results, routing is performed in general to minimize the total wirelength while not violating the constraints.
For placement, we aim to flexibly and efficiently handle the mixed-size macros via an RL scheme, and meanwhile optimize the net order for routing.
For routing, we propose a conditional generative model to obtain the routes in one-shot instead of performing sequential pin connection as done in previous learning-based [6] as well as classic routers [20, 21].
The stacking RL placement network and generative routing network can be learned via gradient back propagation in an end-to-end manner, which meanwhile completes the whole task in line with the state-of-the-art learning-based placement and routing solvers [2, 1].
Note our work is pure learning based in contrast to [2] that still involves unlearnable classic routers in the whole pipeline.
The pure neural architecture implies that our model has the potential to enjoy higher capacity by using larger model for further improvement.
3.1 Reinforcement Learning for Mixed-size Placement
A natural idea for classical placers to address the mixed-size issue for placement is to adopt a hierarchical approach based on partitioning.
However, it sacrifices the solution quality since each sub-problem is solved independently.
Meanwhile, DeepPlace as a learning-based placer assumes that each macro only occupies one cell in the grid graph and ignores pre-placed macros, which leads to a severe overlap issue in the final placement result.
This motivates us to extend the formulation of DeepPlace by considering the real size of macros as well as initial placement information.
We still adopt [22] as the CNN backbone and GCN [23] as the GNN backbone which consists of three layers that contain 16, 32 and 16 feature channels. The policy network is updated by Proximal Policy
Optimization (PPO) [24], in line with the effective setting adopted in [2].
The revised elements of the
Markov Decision Processes (MDPs) for mixed-size placement are defined as:
• State s t : the state representation still consists of global image I portrayed the layout and netlist graph H contains detailed position of placed macros
except
that the initial state of I is no longer a zero matrix I n × n = O .
Instead, our model preprocesses the positions of fixed macros in the dataset and sets I xy as 1 if ( x, y ) has already been occupied before placement.
• Action a t : the action of RL agent is to find the central of current macro, and position ( x o , y o ) is available if all points p in the region R satisfy I p = 0 , where R = { ( x, y ) | | x − x o | ≤ h 2 , | y − y
o | ≤ w 2 } and h , w denote the height and width of the current macro respectively.
• Reward r t : to further control the overlap in the final placement, the reward at the end of episode is a negative weighted sum of wirelength, routing congestion and overlapping area from the final solution: R E
= − L wl − λ 1 · L cg − λ 2 · L ol as weighted by λ 1 and λ 2 .
3.2 Conditional Generative Learning for Pin Routing in Net
The Global Routing Grid Protocol.
In global routing, the physical chip is usually divided into rectangular areas, as shown in the left part of Fig.
Each area is called a global routing cell (Gcell), which corresponds to a node v i ∈ V in the grid graph G ( V, E ) on the right side.
While each edge e ij ∈ E represents the joint boundary between abutting Gcells v i and v j .
For edge e , its capacity c e is the allowed maximum number of wires that can cross e , and the usage u e is the actual number of wires that e has been assigned.
The overflow o e = max (0 , u e − c e ) denotes the amount of wires beyond c e .
Each route conforms to the rectilinear Steiner tree structure [25].
The overall routing task is composed of numerous nets whose routing can be independent to each other.
A single net consists of a series of pins placed in the nodes of the grid graph.
Thus in this paper, we mainly consider the routing over multiple pins in one net.
Given a single net, we formulate the one-net routing problem as the mapping from a one-net routing image x to the corresponding route layout image y , where x contains three channels: 1) the locations of pins, 2) the availability of horizontal grid edges, and 3) the availability of vertical grid edges, and one channel for y .
As to the output, the value of each pixel of y denotes the likelihood of whether this grid point belongs to the route or not.
Hence, the synthesis of routes can also be viewed as a binary classification of the pixels in y .
The pixels whose likelihood is higher than the threshold are subsequently collected to form the route.
In case of disconnected routes, we apply maze routing to refine the outcomes.
In the initial design of our model, we do not adopt the random noise z , which mainly leads to producing fairly stochastic outputs, since the routing task barely requires stochasticity.
Our routing model adopts the conditional generative adversarial framework, which has shown effectiveness in image generation.
The generator is composed of a basic generator for the input size of 64 × 64 or below (the smaller ones are padded to 64 × 64) and an extension for the input size of larger than 64 × 64.
The discriminator consists of two sub-discriminators to estimate routes from validity and realness perspectives.
We, furthermore, design an enhanced loss to improve the performance of our model.
The structure of the generative model is visualized in Fig.
3.2.1 Layout Input-size-Adapting Generator
During routing, the physical chips are decomposed into Gcells in terms of various widths and heights as shown in Fig.
1, causing the diversity of the scale of the corresponding grid graphs.
To make it more tractable, we develop an input-size-adapting generator to handle various grid graphs.
First, we construct a basic generator, G base , to solve grids not larger than 64 × 64 as the chip is divided into 64 × 64 tiles in the macro placement stage.
The architecture proposed by [26] is partly adopted as the backbone of G base , which has been proven successful in generative tasks.
Our basic generator contains four components : 1) a convolutional front-end, 2) a series of residual blocks, 3) a transposed convolutional component, and 4) a convolutional layer to generate the output.
Second, to handle larger grids, we establish another generator G large , which is composed by two sub-networks: G inner and G outer ( G i and G o , for simplicity).
G i and G o are termed as the guiding network and the filling network, respectively.
The guiding network consists of the first three parts that
G base owns.
In contrast, the components of filling network are similar to G base , and correspondingly we use G ko ( k = 1 , 2 , 3 , 4) to denote them.
We feed the input grid to G 1 o to obtain a feature map, and downsample the input grid to feed G i to acquire another feature map.
G 2 o takes in the element-wise sum of these two feature maps and integrates the guiding information into G o , and the hybrid feature map then is converted into the output.
The architecture of our generator is illustrated in Fig. 2(left).
We can further incrementally stack additional sub-networks on G large , and model compression techniques can be used to help keep the inner network neat.
While training the networks, we first pre-train the sub-networks separately, and then we jointly train them to fine-tune the whole network.
Remarks.
The CNN-based generator coincides with routing: 2-D neighborhood structure, translation equivariance and locality.
Amid routing, chips are formulated as grids, which are further transformed into images.
Routing also exhibits translation equivariance since translating a whole net with the context will not change the routing result.
Moreover, for each grid node, the convolution kernel gathers the information from locally adjacent vertices, especially those directly connected to it, to form local routing features.
The holistic route is then produced.
Rather than simply stacking layers to handle long-range dependencies, the well-trained guiding network provides global information equivalent to long-range dependencies.
3.2.2 Bi-Discriminator to Consider both Realness and Connectivity
Routing problems have an inherent constraint that all pins should be connected.
Therefore we devise a discriminator to evaluate the connectivity of the output.
To effectively train the connectivity discriminator, we develop an algorithm to accurately figure out the connectivity of each fake and real route, and then we employ the results as labels.
Connectivity alone is not sufficient to evaluate the authenticity of the output, so we adopt another discriminator to estimate the realness of the output, as the original discriminator in GAN.
Overall, the adversarial loss of our model can be expressed as
[Equation]
[Equation]
where D 1 and D 2 denote the connectivity discriminator and the realness discriminator, respectively, and λ 1 and λ 2 represent the corresponding weights s.t.
λ
1 + λ 2 = [Equation]
The discriminators share the convolutional front-end and a stack of L = 3 convolutional and residual blocks, and then they make evaluations from different angles as depicted in the right part of Fig.
3.2.3 Enhanced Model Loss
With the cGAN objective mixed with a traditional loss, such as L1 and L2 loss, training is inefficient as most grid points are easy negatives that cannot yield effective learning signals.
In addition, tons of trivial negatives impair the training and give rise to a degraded model, and the output, thus, inclines to converge to an empty route.
To bridge the gap between easy negatives and scarce positives, we apply the focal loss [27] and modify it to fit our task:
[Equation]
where i = 1 , . .
. , N represents grid points, and y i and g i respectively denotes the real and generated value of corresponding grid point.
We also incorporate the L2 loss into our objective to approach the real routes, and because it has been found beneficial to the synthesis [28, 29].
minimize wirelength
The introduction of the connectivity discriminator improves the correctness of the results, but at the same time, it may slightly increase the wirelength.
Since the wirelength has an accurate theoretical lower bound, i.e. half-perimeter wirelength (HPWL) of the bounding box of a net, we take the difference between the length of the generated route and the HPWL as a regularization term to limit the wire length.
We use L r ( G ) =
E x [ ∥ l ( G ( x )) − h ( x ) ∥ 1 ] to represent the regularization term, where l ( G ( x )) denotes the length of the generated route, and h ( x ) denotes the HPWL of the net.
The overall enhanced objective of our model gathers the above losses:
[Equation]
(3) where µ FL , µ L 2 and µ r are defined as the factors of L FL , L L 2 and L r , respectively.
3.3 Neural Macro Placement and Routing Pipeline
Combining the RL-based model for learning mixed-size macro placement with one-shot generative routing network to perform routing as we introduce above, we propose a pure neural pipeline for macro placement and routing.
Fig.
3 shows the flow of our mixed-size macro placer with adaptive reward function between coarse HPWL estimation to wirelength from the neural router.
Given the circuit information, our mixed-size agent sequentially places the macros on the chip layout, after which the generative model for routing is adopted to connect the net chosen by net order agent and finally calculate wirelength as feedback.
Inspired by EM algorithm, we first update the generative router using placement result from mixed-size agent (similar to E step ), then placement and net order agents are learned jointly in a whole reinforcement learning framework to minimize wirelength calculated by trained generative model (corresponding to M step ) following a recursive pattern.
3.3.1 Reward Adaptation between Coarse HPWL and Router’s WL
HPWL is a common metric for estimating the true wirelength decided by routing.
In our neural pipeline, however, we apply a one-shot generative routing network to route all the nets directly, which reduces bias in the reward signal.
Nevertheless, it is worth noting that the untrained policy network for placement would start with random weights so that placement results are of low quality.
As a result, the distribution of pins in a single net will spread out, which is difficult for a generative model-based router to produce accurate route layout images.
To tackle this problem, we propose an adaptive scheme to calculate wirelength for our placement agent, integrating HPWL and neural router’s output simultaneously.
We introduce λ to scale two values and define the smoothed wirelength WL s :
[Equation]
(4) where WL n is the feedback of neural router.
In each iteration, variable λ is updated by function 1 − e − 0 .
01 · n iter .
Initially, λ begins with 0 so that the wirelength is determined by HPWL that serves as a coarse reward signal.
As the training proceeds, the feedback of neural router gradually becomes a prominent factor to provide a more accurate objective for the placement agent.
3.3.2 Learning Net Order to Route
The order in which nets are routed is one of the most critical factors that affects the routing quality [30].
Most classical routers determine the net order by heuristics, e.g., routing smaller nets earlier [31] due to the flexibility of finding free path.
However, there are diverse definitions for “smaller net”, none of which is proved to be optimal.
What makes the situation worse, the complexity of real routing procedure requires us to change the net order dynamically, which is hard to implement in such a complicated system.
Fortunately, our neural router divides the routing task into a series of one-net routing problems and then solves them independently, making it convenient to learn the net order.
We build net order learning module upon the neural router by developing a RL agent to determine which net to route next.
Inspired by the structure of placement agent, the state of net order problem consists of routing image R as a representation of current routing layout, and graph G indicating the connectivity between nets.
There are three channels of R : the locations of routed net, the capability of horizontal and vertical grid edges.
Graph G is an edge-to-vertex dual of netlist graph H , whose vertices denote nets (i.e., hyperedges of H ) and edges denote common cells between nets (i.e., nodes of H ).
Note that the state of placement and net ordering tasks are quite similar while both seek to minimize the total wirelength, we combine them into a whole RL framework by adopting same policy network to generate feature embeddings for two tasks respectively.
The united structure without heuristic solver reflects the strongly coupled relationship between placement and routing, which differs from [2] that merely applies router as a black box to calculate the reward.
Experiments 4.1 Protocols and Setup
Experiments are conducted on a server with RTX 3090 GPUs and AMD 3970X 32-Core CPU, and implemented by PyTorch.
We term our whole approach for placement and routing as PRNet .
Benchmarks & Datasets.
For placement, we validate our RL agent for mixed-size macro placement using ISPD-2005 benchmark [32] after pre-processing, such that most fixed macros are exchanged for movable ones in line with [2].
For routing 3 , we choose the ISPD-07 [5] benchmarks to produce routing instances and use the routes generated by the strong classic router [33] as training labels.
In the ISPD-07 benchmarks, some nets can contain up to hundreds of pins, but the average amount of pins in a single net is still about 4.
In other words, massive nets contain no more than 4 pins.
Therefore, the routing model should have sufficient ability to route the easy nets.
From around 750K routing instances, we collect 30K 64 × 64 nets as the Route-small-4 dataset whose instance contains up to 4 pins, 80K 64 × 64 samples as Route-small, and 100K 128 × 128 samples as Route-large to evaluate the model’s ability.
Each of the three datasets is randomly divided into a training set (80%) and a test set (20%).
These three training sets are used to train generative routing models and pick up the best one according to their performance on the test sets.
Then we continue to train the best 64 ×model with additional 200K 64 × 64 instances and train the 128 × 128 model with additional 400K 128 × 128 instances, which is used to perform experiments on the ISPD-98 routing benchmarks [34].
Training.
To train the placement and net ordering RL agent, we use PPO [24] to update the policy network and Adam optimizer [35] is utilized with a learning rate of 2.5 × 10 − 4 .
For training the routing models, we use Adam with learning rate of 2 × 10 − 4 , β 1 = 0 .
5 , β 2 = 0 .
999 and a weight decay of 0.01.
We employ a batch size of 64.
A linear learning rate decay is also applied.
Evaluation.
In mixed-size placement, we adopt HPWL as the proxy of wirelength and overlapping area to evaluate both methods while we introduce wirelength (WL) and routing congestion (RC) [36] in overall placement and routing.
For routing, since there is little metric for generative routing model, we introduce the metrics correctness rate (CrrtR) and wirelength ratio (WLR) to evaluate the generated results of generative models on the datasets.
CrrtR signifies the ratio of the amount of connected overflow-free routes to the number of all routes, or in short the accuracy of generated result.
WLR represents the ratio of the total wirelength of connected overflow-free routes to the total wirelength of the corresponding real routes.
Lower WLR indicates that the route requires fewer wires.
In the experiments on the ISPD-98 routing benchmarks, wirelength, overflow and runtime are used.
4.2 Results on Mixed-size Placement
We compare the total wirelength together with overlapping area of our mixed-size approach with the state-of-the-art and open-sourced method called DeepPlace [2] as shown in Table 1.
Both methods generate intermediate macro placement via RL, and then adopt gradient-based optimization placer [Figure] [Table] as used in [37] to obtain complete placement solution.
With only a slight increase of the total wirelength (within 1.3% difference on average)
[Table]
our mixed-size macro placer achieves approximately 4 × reduction over DeepPlace on the overlapping area, stressing the importance of modeling macro’s shape in state space.
Moreover, the reduced overlapping area requires less post-processing to resolve collision, which facilitates improvement of wirelength in the long term.
Examples of our mixed-size placer and DeepPlace on circuit bigblue 1 are visualized in Fig.
4.3 Results on Routing
Comparison of Generative Backbones.
We compare our model with a CVAE based router using
CNN as the backbone [9] and use CVAE*(CNN) to denote it.
We then combine the CVAE*(CNN) with a vanilla discriminator and our bi-discriminator to build CVAE*-GAN and CVAE*-bcGAN, following the idea of [38].
In addition, we implement a U-Net based cGAN following pix2pix [29] and use cGAN(U-Net*) to denote it.
Then we remove the discriminator to obtain a U-Net [39] generator and define it as U-Net*.
We further replace the discriminator of cGAN(U-Net*) with our bi-discriminator.
We also try to train the RL agent following the work of [6], but it fails to converge after 2-week training.
Table 2 shows the comparison results.
The ResNet-based [40] models outperform the counterparts based on CVAE*(CNN) and U-Net*.
Our model achieves approximately 2 × correctness rate, 14.7% improvement of the wirelength on Route-small-4 and 2.4% on Routesmall over CVAE*(CNN).
The vanilla cGAN discriminator slightly improves CVAE*(CNN) and U-Net* on one side while sacrificing the other side, and it debases the ResNet generator.
However, the bi-discriminator strengthens the generators except for the CVAE*(CNN).
Ablation Studies.
We conduct ablation experiments to investigate the contributions of the design choices in our model.
In Table 2, we compare the full version with ResNet-based cGAN, as well as the pure ResNet generator.
The ResNet generator outdoes the cGAN, but the bi-discriminator significantly improves the generator.
Moreover, the enhanced loss improves the wirelength at the marginal expense of correctness.
Appendix A.3.1 contains further details of comparison among loss functions, and Appendix A.3.2 shows the effectiveness of the input-size-adapting network.
[Table]
[Table] [Table]
Test Results.
We test our conditional generative router on the ISPD-98 benchmarks and compare the wirelength, overflow and runtime with three classical routers that perform best on ISPD-98 benchmarks.
Table 4 shows the results.
Our generative routing model presents competitive consequences on wirelength, while it takes a longer time to accomplish the routing task, compared with strong heuristic baselines [30, 41, 42].
Our model takes an image encoded from the whole grid with a net as the input and sequentially solve each net in a one-shot manner, while classical routers only consider the local area, which may obtain fewer wirelength yet consume more time.
However, it is still much more efficient and easier to train than the RL-based router [6] in our empirical experience.
4.4 Comparison with a Concurrent Version of Our Router and Other Classic Routers
By default, our generative router routes the nets sequentially (i.e. one net by one net) such that it produces routes with lower wirelength and overflow.
In another word, the batch size in the inference stage for the deep routing network is 1 which is not common and does not release the computing advantage of GPU.
To speed up our generative router, we set the batch size to 16 in the inference stage to enable our router to run in a concurrent manner. However, the concurrent version may degenerate the performance of the outputs on wirelength and overflow. As illustrated in Fig. 5 in Appendix, the bounding box of net 1 overlaps with that of net 2 , and the bounding box of net 3 is far away from them.
When routing these three nets concurrently, the routes of net 1 and net 2 may intersect with each other and cause conflict in the usage of routing capacity, which leads to overflow and makes routing harder for the rest of nets.
We first test our conditional generative routing model with each net routed sequentially (i.e. a batch size of 1) on the ISPD-98 benchmarks.
In addition, we run our generative router with nets routed concurrently (a batch size of 16), which may trade wirelength and overflow for runtime, and we reimplement the post-processing module by C++.
The sequential and concurrent variants of our
[Table]
generative routing model are defined as Sequential and Concurrent, respectively.
We further compare the wirelength, overflow and runtime with three more classical routers, Labyrinth 1.1 [43], Fengshui 5.1 [44] and BoxRouter [45] in Table 5.
The results of three classical routers are directly quoted from the paper BoxRouter [45].
The experiments of classical routers are performed on a 1.4GHz
PentiumIII workstation with Linux operating system, and our generative routers are performed on a server with RTX 3090 GPUs and AMD 3970X 32-Core CPU.
We also secure the source code of
Labyrinth 1.1 and run on our machine where results are shown in Table 9 in Appendix, while the other two routers are not open-source and are difficult to reproduce.
Table 5 shows the results.
On the one hand, our sequential generative routing model outperforms the classical routers on wirelength and overflow, while it takes a longer time, compared with strong heuristic baselines.
On the other hand, our concurrent version dramatically speeds up the running ( 3 .
36 ∼ 7 . 98 × speedup) of generative routing model at the expense of total wirelength and overflow, and it still performs better than the three classical routers on wirelength and overflow, except the overflow on ibm 05 and the overflow of BoxRouter on ibm 03 and ibm 06 .
Modifying our algorithms and finding other techniques to cut down the runtime are still being explored.
4.5 Results of Overall Placement and Routing with Ablation Study on Net Order Learning
We compare our PRNetwith DeepPlace, along with an ablation study to verify the impact of net order learning.
The circuits used for evaluation are the same as in mixed-size placement, and we concentrate on macros only for simplicity.
Note that the real shape of macros is ignored and the grid-based mask is coarser in [2], hence the results shown in Table 3 are not identical to those in the original paper [2].
For all test cases, our neural placement and routing pipeline outperforms the other two methods in terms of both wirelength (WL) and routing congestion (RC).
The significant difference in routing congestion without net order learning indicates that net order agent is able to arrange the sequence of routing efficiently, especially on circuits adaptec 3 and adaptec 4 .
As a result, it is easy for every net to find free routing path while keeping away from congested area.
In addition, training placement model with generative neural router in an end-to-end manner further improves the final wirelength, despite a little degradation of routing congestion if we discard the net order agent.
Conclusion and Outlook
We have presented a neural mixed-size placement and routing pipeline.
The routing is achieved by one-shot generation of the whole path, with our devised net order learning module to dynamically adjust the routing order.
Experimental results show the effectiveness of our approach.
Limitation & potential negative impact. The conditional generative routing model is currently trained on the routes generated by the state-of-the-art classical router. Therefore, its performance may be limited by the trainer. Unsupervised/semi-supervised learning is possible alternatives.
For its negative side, AI-based placement and routing may cause the lose of jobs in EDA industry.
This work was partly supported by National Key Research and Development Program of China (2020AAA0107600), National Natural Science Foundation of China (61972250, 72061127003), and Shanghai Municipal Science and Technology (Major) Project (2021SHZDZX0102, 22511105100). Checklist
For all authors... (a) Do the main claims made in the abstract and introduction accurately reflect the paper’s contributions and scope?
[Yes] (b) Did you describe the limitations of your work?
[Yes] (c) Did you discuss any potential negative societal impacts of your work?
[Yes] See Appendix ??
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A Appendix
We provide more discussion on the classic solvers for placement and routing in Sec.
A.1.
We further design and implement an RL-based router (regarded as our implementation of the router [6]) for additional comparison with our generative router in Sec.
A.2, which shows its efficacy.
A.1 Related Work on Classic Solvers for Placement and Routing
Classic Solvers for Placement.
Global placement solvers have been studied for a long history [46, 47], as basically in three categories: partitioning-based methods, stochastic/hill-climbing methods, and analytic solvers.
Partition-based approaches utilize the divide-and-conquer strategy in the early years, after which multi-level partitioning algorithms [48] are devised, with many stochastic methods using annealing [49].
When regarding to analytic solvers, force-directed algorithms [50] and nonlinear optimizers [51, 52] are extensively adopted.
Modern analytical placers, e.g. ePlace [53] and RePlAce [36], have recently introduced an electrostatics-based system that contains globalsmooth density cost function and nonlinear optimizers, which are accelerated by DREAMPlace [37] later based on deep neural network.
Mixed-size placement attracts attention for its practical value.
Hierarchical [54] and constraint graph-based [55] are proposed to place large scale mixed size designs.
Classic Solvers for Routing.
According to the way for solving global routing, there are two types of classic methods: concurrent and sequential solvers.
Concurrent approaches attempt to handle numerous nets simultaneously.
BoxRouter [45] develops progressive integer linear programming (ILP) and adaptive maze routing to diffuse the congestion.
BoxRouter 2.0 [41] further provides a more systematic way of eliminating congestion and assigning layers to wires.
GRIP [56, 57], built on a partitioning strategy in a 3D manner, obtains the ideal wirelength but leads to prohibitive runtime.
While sequential approaches typically employ net decomposition [58], maze routing [59], pattern routing [43], or negotiation-based rip-up and rerouting (NR&R), and solely route a 2-pin net every time (e.g. [20, 21, 60, 33]).
The sequential methods have been often shown faster than the concurrent approaches, but they may rely on the ordering of the nets and thus leading to sub-optimal solutions.
A.2 Implementation of an RL-based Router
We further devise an additional RL-based router following [6] which only gives limited result on small-scale dataset that is generated randomly additional routing methods for comparison.
The RL-based router in our experiment is based on recent work [6] that decides actions of the routing direction, i.e. going north, south, etc in each step.
In our implementation, we enlarge the grid size from 8 × 8 to 16 × 16 while ignoring different layers in routing, as we concentrate on calculating the final wirelength in more realistic cases.
The structure of our Q-network consists of three fully-connected layers with 128 hidden units in each layer.
Reward is set as − 1 for all valid actions, except that the reward of finding terminal pin is 50 and a penalty of − 50 is supposed to pay for invalid action which makes the capacity of routing path smaller than zero.
[Table]
A.3 Additional Experimental Results A.3.1 Ablation Study for Loss Function of the Routing Model
In this experiment, we utilize our conditional generative routing network as the base model and verify the effectiveness of the enhanced loss function.
Our adversarial loss is
[Equation]
where we set λ
= λ 2 = 0 .
5 by default.
While our focal loss is
[Equation]
where we set α = 0 .
5 and γ = 2 by default.
For the enhanced loss, it can be expressed as
[Equation]
where we set µ FL = µ L 2 = 5 × 10 3 and µ r = 0 .
1 in all our experiments.
In Table 6, focal loss delivers the best correctness rate while introducing higher wirelength.
In contrast, the L2 loss is opposite of the focal loss.
The enhanced loss combines the advantages of these two loss functions and obtains a competitive correctness rate and the best wirelength ratio.
A.3.2 Input-size-Adapting vs. Non-Input-size-Adapting
[Table]
We explore the performance difference between our input-size-adapting network (represented by
ISA) and a non-input-size-adapting variant (represented by Non-ISA).
The Non-ISA follows the structure of our basic generator.
Its convolutional front-end contains one more layer, and it has three additional residual blocks.
The ISA utilizes the well-trained basic generator in part as the guiding network to obtain a feature map, and it further uses another convolutional front-end as the filling network to acquire another feature map.
Then the element-wise sum of the feature maps are fed into a series of residual blocks and a decoder to generate the output.
We compare the Non-ISA withvariants of our ISA (without pre-training the filling network, pre-training the filling network forepochs and pre-training the filling network for 100 epochs).
The ISA outperforms the Non-ISA as illustrated in Table 7, while the variants pre-trained for different number of epochs behave similarly. [Table]
Fig.
6 shows the training plot for the Non-ISA, the ISA and the basic generator.
The variants of the
ISA pre-trained for diverse amounts of epochs share similar training curves.
The training of all the networks is stable [Table] and the ISA converges faster than the Non-ISA and achieves a better result since it partly inherits the well-trained basic generator and the filling network has also been pre-trained [Table]
A.3.3 Additional Experiments of Generative Backbones
We extend the dataset Route-small to a larger dataset named Route-small-extension that contains 650k instances from 3 circuits as the training set and 200k samples from another circuit as the test set.
We conduct additional experiments of generative routing models on Route-small-extension with results shown in Table 8, which is an extension to Table 2. A.3.4 Additional Experiments of Classical Router
We secure source code of Labyrinth 1.1 [43] and run it on our machine, then we obtain the results in Table 9. We set Num _ Reroute as 500 and two-terminal as True . All experiments are run on a AMD Ryzen 5 4600H CPU with 2G RAM.
Circuit ibm 05 is a trivial case due to the sufficient routing resources, so that it requires fewer iterations in the rip-up and reroute phase and runtime is relatively shorter.
[Table]
[Table]
A.3.5 Comparison with RL-based Router
Table 10 compares the results between our conditional generative routing model and RL-based router on circuit adaptec 1 from ISPD-2005 benchmark.
Our conditional generative router is much more efficient than the RL-based router, achieving approximately 10 × speedup.
In addition, the overflow of RL-based router is greater than zero, which degrades the performance of wirelength in the long run.
Note the maximal grid size that RL router can deal with is 16 × 16 while our generative routing model is still applicable for grids larger than 64 × 64 .
Such limitation on size and extremely low efficiency make RL-based router not an option in neural macro placement and routing pipeline.
A.3.6 Additional Visualization of Mixed-size Placement
Despite circuit bigblue 1 , two additional visualization of our mixed-size placer and DeepPlace on circuits adaptec 2 and adaptec 4 are elaborated in Fig.
[Figure]