W RAP N ET : N EURAL N ET I NFERENCE WITH U LTRA -L OW -P RECISION A RITHMETIC
A BSTRACT
Low-precision neural networks represent both weights and activations with few bits, drastically reducing the cost of multiplications.
Meanwhile, these products are accumulated using high-precision (typically 32-bit) additions. Additions dominate the arithmetic complexity of inference in quantized (e.g., binary) nets, and high precision is needed to avoid overﬂow.
To further optimize inference, we propose WrapNet, an architecture that adapts neural networks to use low-precision (8-bit) additions while achieving classiﬁcation accuracy comparable to their 32bit counterparts.
We achieve resilience to low-precision accumulation by inserting a cyclic activation layer that makes results invariant to overﬂow.
We demonstrate the efﬁcacy of our approach using both software and hardware platforms.
I NTRODUCTION
Signiﬁcant progress has been made in quantizing (or even binarizing) neural networks, and numerous methods have been proposed that reduce the precision of weights, activations, and even gradients while retaining high accuracy (Courbariaux et al., 2016;
Hubara et al., 2016; Li et al., 2016; Lin et al., 2017; Rastegari et al., 2016; Zhu et al., 2016; Dong et al., 2017; Zhu et al., 2018; Choi et al., 2018a;
Zhou et al., 2016; Li et al., 2017; Wang et al., 2019; Jung et al., 2019; Choi et al., 2018b;
Gong et al., 2019).
Such quantization strategies make neural networks more hardware-friendly by leveraging fast, integer-only arithmetic, replacing multiplications with simple bit-wise operations, and reducing memory requirements and bandwidth.
Unfortunately, the gains from quantization are limited because quantized networks still require high-precision arithmetic.
Even if weights and activations are represented with just one bit, deep feature computation requires the summation of hundreds or even thousands of products.
Performing these summations with low-precision registers results in integer overﬂow, contaminating downstream computations and destroying accuracy.
Moreover, as multiplication costs are slashed by quantization, high-precision accumulation starts to dominate the arithmetic cost.
Indeed, our own hardware implementations show that an 8-bit × 8-bit multiplier consumes comparable power and silicon area to a 32-bit accumulator.
When reducing the precision to a 3-bit × 1-bit multiplier, a 32-bit accumulator consumes more than 10 × higher power and area; see Section 4.5.
Evidently, low-precision accumulators are the key to further accelerating quantized nets.
In custom hardware, low-precision accumulators reduce area and power requirements while boosting throughput.
On general-purpose processors, where registers have ﬁxed size, low-precision accumulators are exploited through bit-packing , i.e., by representing multiple low-precision integers side-by-side within a single high-precision register (Pedersoli et al., 2018; Rastegari et al., 2016;
Bulat & Tzimiropoulos, 2019).
Then, a single vector instruction is used to perform the same operation across all of the packed numbers.
For example, a 64-bit register can be used to execute eight parallel 8-bit additions, thus increasing the throughput of software implementations.
Hence, the use of low-precision accumulators is advantageous for both hardware and software implementations, provided that integer overﬂow does not contaminate results.
We propose WrapNet, a network architecture with extremely low-precision accumulators.
WrapNet exploits the fact that integer computer arithmetic is cyclic, i.e, numbers are accumulated until they reach the maximum representable integer and then “wrap around” to the smallest representable integer.
To deal with such integer overﬂows, we place a differentiable cyclic (periodic) activation function immediately after the convolution (or linear) operation, with period equal to the difference between the maximum and minimum representable integer.
This strategy makes neural networks resilient to overﬂow as the activations of neurons are unaffected by overﬂows during convolution.
We explore several directions with WrapNet.
On the software side, we consider the use of bitpacking for processors with or without dedicated vector instructions.
In the absence of vector instructions, overﬂows in one packed integer may produce a carry bit that contaminates its neighboring value.
We propose training regularizers that minimize the effects of such contamination artifacts, resulting in networks that leverage bit-packed computation with very little impact on ﬁnal accuracy.
For processors with vector instructions, we modify the Gemmlowp library (Jacob et al., 2016) to operate with 8-bit accumulators.
Our implementation achieves up to 2 .
4 × speed-up compared to a 32-bit accumulator implementation, even when lacking specialized instructions for 8-bit multiplyaccumulate.
We also demonstrate the efﬁcacy of WrapNet in terms of cycle time, area, and energy efﬁciency when considering custom hardware designs in a commercial 28 nm CMOS technology.
R ELATED W ORK AND B ACKGROUND 2. N ETWORK Q UANTIZATION
Network quantization aims at accelerating inference by using low-precision arithmetic.
In its most extreme form, weights and activations are both quantized using binary or ternary quantizers.
The binary quantizer Q b corresponds to the sign function, whereas the ternary quantizer Q t maps some values to zero.
Multiplications in binarized or ternarized networks (Hubara et al., 2016; Courbariaux et al., 2015; Lin et al., 2017; Rastegari et al., 2016; Zhu et al., 2016) can be implemented using bitwise logic, leading to impressive acceleration.
However, training such networks is challenging since fewer than 2 bits are used to represent activations and weights, resulting in a dramatic impact on accuracy compared to full-precision models.
Binary and ternary networks are generalized to higher precision via uniform quantization, which has been shown to result in efﬁcient hardware (Jacob et al., 2018).
The multi-bit uniform quantizer Q u is given by: Q u ( x ) = round ( x/ ∆ x )∆ x , where ∆ x denotes the quantization step-size.
The output of the quantizer is a ﬂoating-point number x that can be expressed as x = ∆ x x q , where x q is the ﬁxed-point representation of x .
The ﬁxed-point number x q has a “precision” or “bitwidth,” which is the number of bits used to represent it.
Note that the range of ﬂoating-point numbers representable by the uniform quantizer Q u depends on both the quantization step-size ∆ x and the quantization precision.
Nonetheless, the number of different values that can be represented by the same quantizer depends only on the precision.
Applying uniform quantization to both weights w = ∆ w w q and activations x = ∆ x x q simpliﬁes computations, as an inner-product simply becomes
[Equation]
The key advantage of uniform quantization is that the core computation (cid:80) i ( w q ) i ( x q ) i can be carried out using ﬁxed-point (i.e., integer) arithmetic only.
Results in (Gong et al., 2019; Choi et al., 2018b;
Jung et al., 2019; Wang et al., 2019; Mishra et al., 2017; Mishra & Marr, 2017) have shown that high classiﬁcation accuracy is attainable with low-bitwidth uniform quantization, such as 2 or 3 bits.
Although ( w q ) i , ( x q ) i , and their product may have extremely low-precision, the accumulated result z q of many of these products has very high dynamic range.
As a result, high-precision accumulators are typically required to avoid overﬂows, which is the bottleneck for further arithmetic speedups.
2. L OW - PRECISION A CCUMULATION
Several approaches have been proposed that use accumulators with fewer bits to obtain speed-ups.
For example, reference (Khudia et al., 2021) splits the weights into two separate matrices, one with
[Table]
small- and another with large-magnitude entries.
If the latter matrix is sparse, acceleration is attained as most computations rely on fast, low-precision operations.
However, to signiﬁcantly reduce the accumulator’s precision, one would need to severely decrease the magnitude of the entries of the ﬁrst matrix, which would, in turn, prevent the second matrix from being sufﬁciently sparse to achieve acceleration.
Recently, (de Bruin et al., 2020) proposed using layer-dependent quantization parameters to avoid overﬂowing accumulators with ﬁxed precision.
Fine-tuning is then used to improve performance.
However, if the accumulator precision is too low (e.g., 8 bits or less), the optimized precision of activations and weights is too coarse to attain satisfactory performance.
Another line of work (Sakr et al., 2019; Micikevicius et al., 2017; Wang et al., 2018) uses 16-bit ﬂoating-point accumulators for training and inference—such approaches typically require higher complexity than methods based on ﬁxed-point arithmetic.
2. T HE I MPACT OF I NTEGER O VERFLOW
Overﬂow is a major problem, especially in highly quantized networks.
Table 1 demonstrates that overﬂows occur in around 11% of the neurons in a network with 3-bit activations (A) and binary weights (W) that is using 8-bit accumulators for inference after being trained on CIFAR-10 with standard precision.
Clearly, overﬂow has a signiﬁcant negative impact on accuracy.
Table 1 shows that if we use an 8-bit (instead of a 32-bit) accumulator, then the accuracy of a binary-weight network with 2-bit activations drops by more than 40%, even when only 1.72% neurons overﬂow.
If we repeat the experiment with 3-bit activations and binary weights, the accuracy is only marginally better than a random guess.
Therefore, existing methods try to avoid integer overﬂow by using accumulators with relatively high precision, and pay a correspondingly high price when doing arithmetic.
W RAP N ET : D EALING WITH I NTEGER O VERFLOWS
We now introduce WrapNet, which includes a cyclic activation function and an overﬂow penalty, enabling neural networks to use low-precision accumulators.
We also present a modiﬁed quantization step-size selection strategy for activations, which retains high classiﬁcation accuracy.
Finally, we show how further speed-ups can be achieved on processors with or without specialized vector instructions.
We propose training a network with layers that emulate integer overﬂows on the ﬁxed-point preactivations z q to maintain high accuracy.
However, directly training a quantized network with an overﬂowing accumulator diverges (see Table 2) due to the discontinuity of the modulo operation.
To facilitate training, we insert a cyclic “smooth modulo” activation immediately after every linear/convolutional layer, which not only captures the wrap-around behavior of overﬂows, but also ensures that the activation is continuous everywhere.
The proposed smooth modulo activation c is a composite function of a modulo function m and a basis function f that ensures continuity.
Speciﬁcally, given a b -bit accumulator, our smooth-modulo c for ﬁxed-point inputs is as follows:
[Equation]
where k is a hyper-parameter that controls the slope of the transition.
Note that we apply constant shifts to keep the input of f in [ − 2 b − 1 , 2 b − 1 ) .
Figure 1a illustrates the smooth modulo function with
[Figure]
two different slopes k = 1 , 4 .
As k increases, the cyclic activation becomes more similar to the modulo operator and has a greater range, but the transition becomes more abrupt.
Since our cyclic activation is continuous and differentiable almost everywhere, standard gradient-based learning can be applied easily.
A convolutional block with cyclic activation layer is shown in Figure 1b.
After the convolution result goes into the cyclic activation, the result is multiplied by ∆ z to compute a ﬂoating-point number, which is then processed through BatchNorm and ReLU.
A ﬁxed per-layer quantization step-size is then used to convert the ﬂoating-point output of the ReLU into a ﬁxed-point input for the next layer.
We detail the procedure to ﬁnd this step-size in Section 3.2.
3. O VERFLOW P ENALTY
An alternative way to adapt quantized networks to low-precision accumulators is to directly reduce the amount of overﬂows.
To achieve this, we propose a regularizer which penalizes outputs that exceed the bitwidth of the accumulation register.
Concretely, for a b -bit accumulator, we deﬁne an overﬂow penalty for the l -th layer of the network as follows:
R ol =
(1 /N )
(cid:80) i max {| z iq | − 2 b − 1 , 0 } .
Here, z iq is the ﬁxed-point result in (1) for the i -th neuron of the l -th layer, and N is the total number of neurons in the l -th layer.
The overﬂow penalty is imposed after every quantized linear layer and before the cyclic activation.
All these penalties are combined into one regularizer R o = (cid:80) l R ol .
3. S ELECTION OF A CTIVATION Q UANTIZATION S TEP -S IZE
To keep multiplication simple, the ﬂoating-point output of ReLU must be quantized before it is fed into the following layer.
However, as shown in Table 1, a signiﬁcant number of overﬂows occur even with 3-bit activations.
From our experiments (see Table 3), we have observed that if overﬂow occurs too frequently (i.e., on more than 10% of the neurons), then WrapNet starts to suffer signiﬁcant accuracy degradation.
However, if we reduce the activation precision so that no overﬂows happen at all, several layers will have 1-bit activations (see Table 3), thereby increasing quantization errors and degrading accuracy.
To balance accumulation and quantization errors, we adjust the quantization step-size ∆ x of each layer based on the overﬂow rate, i.e., the percentage p % of neurons that overﬂow in the network.
If the overﬂow rate p % is too large, then we increase ∆ x to reduce the overﬂow rate p %.
The selected quantization step-size is then ﬁxed for further ﬁne-tuning.
3. A DAPTING TO B IT -P ACKING
Most modern processors provide vector instructions that enable parallel operation on multiple 8bit numbers.
For instance, the AVX2 (NEON) instruction set on x86 (ARM) processors provides parallel processing with 32 (16) 8-bit numbers.
Vector instructions provide a clean implementation of bit-packing, which WrapNet can leverage to attain signiﬁcant speed-ups.
While some embedded processors and legacy chips do not provide vector instructions, bit-packing can still be applied.
Without vector instructions for multiplication, binary/ternary weights must be used to replace multiplication with bit-wise logic (Bulat & Tzimiropoulos, 2019; Pedersoli et al., 2018).
Furthermore, bit-packing of additions is more delicate: Each integer overﬂow not only results in wrap-around behavior, but also generates a carry bit that contaminates the adjacent number—specialized vector instructions avoid such contamination.
We propose the following strategies to minimize the impact of carry propagation.
Reducing variance in the number of carries.
The number of carries generated during a convolution operation can be large.
Nevertheless, if we can keep the number of carries approximately the same for all the neurons among a batch of images, the estimated number of carries can be subtracted from the result to correct the outputs of a bit-packed convolution operation.
To achieve this, during training, we calculate the number of carries for each neuron and impose a regularizer, R c , to keep the variance of the number of carries small.
The detailed formulation of R c can be found in Appendix A.1.
Using a buffer bit.
Alternatively, since each addition can generate at most one carry bit, we can place a buffer bit between every low-bit number in the bit-packing.
For example, instead of packing eight 8-bit representations into a 64-bit number, we pack eight 7-bit numbers with one buffer bit between each of them.
These buffer bits absorb the carry bits, and are cleared using bit-wise logic after each addition.
Buffering makes representations 1-bit smaller, which potentially degrades accuracy.
A hybrid approach.
To get the beneﬁts from both strategies, we use a variance penalty on layers that have small standard deviation to begin with, and equip the remaining layers with a buffer bit.
E XPERIMENTS
We compare the accuracy and efﬁciency of WrapNet to networks with full-precision accumulators using the CIFAR-10 and ImageNet datasets.
Most experiments use binary or ternary weights for
WrapNet as AVX2 lacks 8-bit multiplication instructions, but supports 8-bit additions and logic operations needed for binary/ternary convolutions.
4. T RAINING P IPELINE
We ﬁrst pre-train a network with quantized weights and no cyclic layers, while keeping full-precision activations.
Then, we select the quantization step-sizes of the activations (see Section 3.2) such that each layer has an overﬂow rate of around p % (a hyper-parameter) with respect to the desired accumulator bitwidth.
Given the selected quantization step-size for each layer and the pre-trained network, we insert our proposed cyclic activation layer.
We then warm-up our WrapNet by ﬁnetuning with full-precision activation for several epochs.
Finally we further ﬁne-tune the network with both activations and weights quantized.
Both overﬂow and carry variance regularizers are only applied in the ﬁnal ﬁne-tuning step, except when training ResNet for ImageNet, where the regularizers are also included during warm-up.
4. A DAPTING TO L OW - PRECISION A CCUMULATORS
We conduct ablation studies on the following factors: the type of cyclic function, the initial overﬂow rate for quantization step-size and precision selection, and the coefﬁcient of the overﬂow penalty regularizer.
These experiments are conducted on VGG-7 (Li et al., 2016), which is commonly used in the quantization literature for CIFAR-10.
We binarize the weights as in (Rastegari et al., 2016), and we train WrapNet to adapt to an 8-bit accumulator.
As our default setting, we use k = 2 as the transition slope, p = 5% as the initial overﬂow rate, and 0 as the coefﬁcient of the regularizer.
Cyclic activation function.
We compare the performance of various transition slopes k of our cyclic function c in Table 2, and we achieve the best performance when k = 2 .
If k is too small, then the accuracy decreases due to a narrower effective bitwidth (only half of the bitwidth is used when k = 1 ).
Meanwhile, the abrupt transition for large k hurts the performance as well.
In the extreme case where the cyclic function degenerates to modulo ( k → ∞ ) , WrapNet diverges to random guessing, which highlights the importance of training with a “smooth” cyclic non-linearity to assimilate integer overﬂow.
We also ﬁnd that placing a ReLU after batch norm yields the best performance, even though the cyclic function is already non linear.
More experimental results can be found in Appendix B.1.
Quantization step-size.
As described in Section 3.2, the quantization step-sizes are selected to balance the rounding error of the activations and accumulation errors due to overﬂow.
We compare the classiﬁcation performance when we choose different step-sizes to control the overﬂow rate as in
[Table]
[Table] [Table]
Table 3.
If the initial overﬂow rate is large, then the quantization step-size will be ﬁner, but training is less stable.
We obtain the best performance when the initial overﬂow rate is around 5%.
The median bitwidths of the activations across layers are also reported in Table 3.
Note that if we want to suppress all overﬂows, we can only use 1-bit activations.
We also observe that WrapNet can attain reasonable accuracy (85%) even with a large overﬂow rate (around 30%), which demonstrates that our proposed cyclic activations provides resilience against integer overﬂows.
Overﬂow penalty.
The overﬂow penalty regularizer improves stability to step-size selection.
More speciﬁcally, in Table 4, the difference in accuracy between two step-size selections decreases from 2.27% to 0.76% after adding the regularizer.
The overﬂow penalty also complements our cyclic activation, as we achieve the best performance when using both of them together during the ﬁnetuning stage.
Moreover, in Appendix B.2, we compare our results to ﬁne-tuning the pre-trained network using the overﬂow regularizer only.
In the absence of a cyclic layer, neural networks still suffer from low accuracy (as in Section 2.3) unless a very strong penalty is imposed.
4. A DAPTING TO B IT -P ACKING
We now show the efﬁcacy of WrapNet for bit-packing without vector operations.
We use the same architecture, binary weights, 8-bit accumulators, and hyper-parameters as in Section 4.2.
The training details can be found in Appendix A.2.
We consider CIFAR-10, and we compare with the best result of WrapNet from the previous section as a baseline.
Without speciﬁc vector instructions, accuracy degenerates to a random guess because of undesired carry contamination during inference.
Surprisingly, with the carry variance regularizer, WrapNet works well even with abundant carry contamination during inference (for each neuron, 384 on average over all the dataset).
The regularizer drops the standard deviation of the per-neuron carry contamination by 90%.
When we use the hybrid approach, the accuracy is further improved (89.43%) and close to the best result (90.81%) we can achieve with vector instructions that do not propagate carries across different numbers (see Table 5).
[Table]
4. B ENCHMARK R ESULTS
In this section, we compare our WrapNet when there is no carry contamination, with the following 32-bit accumulator baselines: a full-precision network (FP), a network trained with binary/ternary weights but with full-precision activations (BWN/TWN), and a network where both weights and activations are quantized to the same precision as our WrapNet (BWN/TWN-QA).
We benchmark our results on both CIFAR-10 and ImageNet.
We use VGG7 and ResNet20 for our CIFARexperiments, and we use AlexNet (Krizhevsky et al., 2012;
Simon et al., 2016), ResNet18 and
ResNet50 (He et al., 2016) for our ImageNet experiments.
Details of training can be found in
Appendix B.3.
For CIFAR-10, even with an 8-bit accumulator, our results are comparable to both BWN and TWN.
When adapting to a 12-bit accumulator, we further achieve performance on-par with TWN and better than BWN (see Table 6).
For ImageNet, our WrapNet can achieve accuracy as good as BWN when adapting to a 12-bit accumulator where we can use binary weights and roughly 7-bit quantized activations.
However, in the extreme low-precision case (8-bit), the accuracy of our binary WrapNet drops around 8% due to the limited bitwidth we can use for activations.
As reported in Table 6, the median activation bitwidth is roughly 3-bit, and for some layers in AlexNet, we can only use 1-bit activations.
Despite the gap from BWN, we observe that our model can achieve almost the same as performance as BWN-QA where the same precision is used for activations.
When using ternary weights, our WrapNet only drops by 3% and 2% from TWN for ResNet18 and ResNet respectively, even when using an 8-bit accumulator.
In addition, in the case of 12-bit accumulator, our ternary WrapNet with roughly 7-bit activations is slightly better than TWN for ResNet50.
Note that, without cyclic activation function, all the results for 8-bit accumulator are as poor as random guessing which is consistent with Table 1.
[Table]
4. E FFICIENCY A NALYSIS
We conduct an efﬁciency analysis of parallelization by bit-packing, both with and without vector operations, on an Intel i7-7700HQ CPU operating at 2.80 GHz.
We also conduct a detailed study of improvements that can be obtained using custom hardware.
[Table]
instruction efﬁciency analysis.
We study the empirical efﬁciency of WrapNet when vector operations are available.
We extended Gemmlowp (Jacob et al., 2016) to implement matrix multiplications using 8-bit accumulators with AVX2 instructions.
To demonstrate the efﬁciency of low-precision accumulators, we compare our implementation with the AVX2 version of Gemmlowp, which uses 32-bit accumulators.
We report the execution speed of both on various convolution kernels of ResNet18 in Table 7.
From Table 7 we observe signiﬁcant speed-ups ranging from 2 × to 2 .
4 × among different blocks.
Besides, we compare the entire inference time (ms) of ResNet18 for
WrapNet (234.74) with a 32b-accumulator quantized network (312.42), which gains 33% speed-up.
The result provides solid evidence for the efﬁciency advantage of using low-precision accumulators.
We remark that in average, the time cost for cyclic activation is only around 10% of the time cost
[Table] [Table]
for the GEMM kernel.
We also remark that AVX2 lacks a single instruction that performs both multiplication and accumulation for 8-bit data, but it does have such instruction for 32-bit data.
Thus, further acceleration can be achieved on systems like ARM where such combined instructions for 8-bit data are available.
Bit-packing results without vector operations.
We implement a na¨ıve for-loop based matrix multiplication, which uses buffer bit and logical operations introduced in Section 3.3 to form the baseline.
We then pack four 8-bit integers into 32 bits, and report the execution speed of both implementations on various convolution kernels of ResNet18 in Table 8.
The results show signiﬁcant speed-ups ranging from 2 .
8 × to 4 .
3 × .
Such observations demonstrate our proposed approach to handle extra carry bits makes bit-packing viable and efﬁcient, even when vector instructions are not available.
Hardware analysis.
To illustrate the potential beneﬁts of WrapNet for custom hardware accelerators, we have implemented a multiply-accumulate (MAC) unit in a commercial 28nm CMOS technology.
The MAC unit consists of (i) a multiplier with an output register, (ii) an accumulator with its corresponding register, and (iii) auxiliary circuitry.
Please refer to Appendix C for the details.
We have considered 8-bit × 8-bit and 3-bit × 1-bit multipliers, as well as 32-bit and 8-bit accumulators, where the latter option is enabled by our WrapNet approach and its cyclic activation function.
We consider a slope k
= 2 for the cyclic activation.
Figure 2 shows our post-layout results.
Figure 2a shows that reducing the multiplier bitwidth decreases the cycle time by 7 %; reducing the accumulator precision from 32-bit to 8-bit further the cycle time by 16 %.
Figures 2b and 2c highlight the importance of reducing the accumulator’s precision.
When using an 8-bit × 8-bit multiplier, the 32-bit accumulator already constitutes more than 40% of the area and energy of a MAC unit.
Once the multiplier’s precision reduces, the accumulator dominates area- and energy-efﬁciency.
Thanks to WrapNet, we can reduce the accumulator precision from 32-bit to 8-bit, thus reducing the accumulator’s area- and energy-efﬁciency by more than 5 × and 4 × , respectively.
WrapNet requires the implementation of the cyclic activation, which has an area- and energy-efﬁciency comparable (although lower) to that of the accumulator.
In spite of this overhead, WrapNet is still able to reduce the total MAC unit’s area- and energy-efﬁciency by up to 3 × and 2 × , respectively.
While our hardware implementation only uses one adder per inner-product, we note that WrapNet can also be applied to spatial architectures, such as systolic arrays, which use several adders per inner-product.
For such spatial architectures, WrapNet avoids an increase in the adders’ bitwidth, normalizing all
[Figure]
bit adders to the same low bitwidth.
Moreover, the use of several adders per inner-product amortizes the overhead from the cyclic activation, of which only one is needed per inner-product.
Finally, we note that this analysis only considers the computation part of a hardware accelerator as this is where WrapNet has a signiﬁcant impact—the memory sub-system will remain virtually the same, as existing methods already quantize the output activations to low-bit before storing them in memory.
C ONCLUSION
We have proposed WrapNet, a novel method to render neural networks resilient to integer overﬂow, which enables the use of low-precision accumulators.
We have demonstrated the effectiveness of our adaptation on both CIFAR-10 and ImageNet.
In addition, our custom GEMM kernel achieves 2 .
4 × acceleration over its standard library version, and our hardware exploration shows signiﬁcant improvements in area- and energy-efﬁciency.
Our hope is that hardware-aware architectures will enable deep learning applications on a wide range of platforms and mobile devices.
Furthermore, with future innovations in GPU and data center technologies, we hope that WrapNet can provide further speed-ups by enabling inference using quarter-precision—a step forward in terms of performance from the currently available half-precision standard available on emerging GPUs.
A CKNOWLEDGEMENT
The university of Maryland team was supported by the ONR MURI program, AFOSR MURI program, and the National Science Foundation DMS division.
Addition support was provided by
DARPA GARD, DARPA QED4RML, and DARPA YFA.
A D ETAILS OF C ARRY V ARIANCE R EDUCTION R EGULARIZER A. C ARRY V ARIANCE C ALCULATION
With two’s complement representations for signed integers, a carry bit is generated in the following three cases: (i) addition of two negative numbers, (ii) addition of two positive numbers whose result exceeds the representation range, thus provoking integer overﬂow, and (iii) addition of a positive and a negative number whose result is a positive number.
Dealing with these cases individually is complicated, but the calculation can be simpliﬁed by ﬁrst reinterpreting the two’s complement representation as an unsigned integer.
Carry bits resulting from accumulation of unsigned integers is easier to calculate as they can only happen in case (ii) as described above.
Since we only consider binary/ternary weights for bit-packing, carry bits can only be generated during accumulation, and not by multiplication.
To produce a single output from a convolution, we must perform the accumulation (cid:80) Li
=1 v i of all entries of the vector v ∈ R L . .
This is done by batching computations inside a b -bit register as follows.
First, we bit-pack groups of numbers v i into several high-resolution registers.
For example, let us consider the use of 32 -bit registers to pack four b = 8 -bit numbers; then, we need to use (cid:100) L/ 4 (cid:101) 32 -bit registers to represent all L entries of v .
In the absence of vector instructions, the addition of these high-resolution registers will generate carry bits that will contaminate the adjacent bit-packed numbers.
After all (cid:100) L/ 4 (cid:101) additions take place, we add the 4 bit-packed numbers together to get a ﬁnal result.
When one output feature is calculated by bit-backing as described above, the effect of carry bits is easy to simulate; accumulations can be done without accounting for carry bits during convolution, and then the carry bits can be added into the the ﬁnal result after convolution takes place.
If the total number of carries is large, this ﬁnal correction can in turn produce new carry bits.
Hence, we use
Algorithm 1 to compute the total number of carry bits that are generated in an accumulation.
The ﬁrst equation simply reinterprets the signed representation to its unsigned counterpart u .
Then, we compute the amount of carry bits
c i , as well as the result r i remaining within the b -bit accumulator.
Due to carry contamination, the carry bits c i will be added to the result r i , which may generate new carry bits
c
i +1 .
We keep on adding the new carry bits to the accumulator until no new carry bits are generated.
Note that, in real hardware at inference time, the most signiﬁant carry bit produced inside a register will be thrown away.
For simplicity, our simulations during training accumulate all carry bits, including the most signiﬁcant.
We ﬁnd that dropping the most signiﬁcant carry during inference does not signiﬁcantly impact testing.
initialization v , b ; u = (cid:80) i ((sign( v i ) + 1) / 2) v
[Equation]
+ (( − sign( v i ) + 1) / 2) (cid:0) v i + 2 b (cid:1) ; c i = u, r i = 0 , c = 0 ; while c i (cid:54) = 0 do c
i +1 =
(cid:4) ( c i + r i ) / 2 b (cid:5) ; r i +1 =
( c i + r i ) mod 2 b ; c
= c + c i +1 ; c i
=
c i +1 , r i =
r i + endreturn c
Given the number of carry bits calculated during the inner product, the variance of the carry among a batch ( b s ) of images is calculated as follows:
[Equation] [Equation]
k
[Equation]
(cid:0)
[Equation]
(cid:33)
[Equation]
where n i,l is the carry bit for the i -th neuron in l -th layer (assuming all the feature maps are vectorized).
The estimated mean among all the images are learned by a moving average based on the mean of batches equation 2.
However, the sign and rounding function may have zero gradient almost everywhere.
To make all the operations differentiable, we replace the sign function with a tanh function and we use a straight through estimator for rounding during the backward pass (gradient is identity).
Then ﬁnally, our regularizer R c will be the mean variance among all the neurons.
A. T RAINING WITH C ARRY V ARIANCE R EDUCTION R EGULARIZER
Due to the large amount and high variance of carry-bit occurrences, it is hard to ﬁne-tune our WrapNet even when using the carry variance reduction regularizer.
The generated carry bits will be accumulated, which increases the overﬂow rate dramatically.
In addition, the accumulation error will contaminate downstream computations and destroy accuracy.
As a result, we ﬁne-tune WrapNet with simulated carry bits layer by layer, starting from the layer which has the least carry variance.
For the hybrid approach, we stop simulating the carry bit when we notice a signiﬁcant accuracy drop; the remaining layers are trained using a buffer bit instead.
B E XPERIMENTAL D ETAILS B. M ORE C YCLIC F UNCTIONS
We compare two more “smooth” cyclic functions with our proposed cyclic activation function in
Section 3.
Speciﬁcally, we consider a cyclic absolute value function, and a ReLU-like function with transition slope k as alternative cyclic activations.
Figure 3 illustrates the compared functions.
We compare the results with and without a ReLU activation after batch normalization as well.
Tableshows that retaining the ReLU activation after the batch normalization layer always achieves a better result, and that our proposed cyclic activation outperforms the other two choices.
[Table]
ULL O VERFLOW P ENALTY R ESULTS
Table 10 shows the results for ﬁne-tuning our WrapNet with different coefﬁcients for the overﬂow penalty.
When applying the overﬂow penalty, the overﬂow rate decreases and we can achieve a higher accuracy.
In addition, when we apply the regularizer to a network with low-resolution accumulators that does not use our cyclic activation, the network still suffers from performance degradation unless a large coefﬁcient is used.
However, a strong penalty kills almost all of the overﬂow, which may limit the performance of a deep neural network.
[Table]
T RAINING D ETAILS FOR B ENCHMARK R ESULTS
For fair comparison, all our baselines (BWN/TWN, BWN-/TWN-QA) are ﬁne-tuned from a pretrained full-precision network.
We leave the ﬁrst and last layer at full-precision as in (Rastegari et al., 2016; Zhou et al., 2016).
To obtain the benchmark results of our WrapNet, we follow a training pipeline, where we ﬁrst warm-up our WrapNet with full-precision activations, and then we ﬁne-tune the network for quantized activations.
We set the transition slope k = 2 , and the initial overﬂow rate p = 5% .
The overﬂow penalty coefﬁcients for CIFAR-10 and ImageNet are 0.01 and 0.001, respectively.
For the CIFAR-10 results, we use ADAM as our optimizer with an initial learning rate of 0.001.
For both warm-up and ﬁne-tuning stages, we run 200 epochs, and the learning rate is divided by 10 every 60 epochs.
For all the ImageNet results, we use SGD with momentum 0.9, weight decay 1 × 10 − 4 as our optimizer.
We run 60 epochs for both warm-up and ﬁne-tuning stages, where the initial learning rate is 0.01, which is divided by 10 at (20, 40, 50) epochs.
We note that, due to depth of ResNet, we select a ﬁxed quantization step-size for all the layers, where the average initial overﬂow rate is around 5%.
As a result, the overﬂow penalty is also imposed during the warm-up stage for ResNet experiments.
C H ARDWARE A NALYSIS
Figure 4 shows the multiply-accumulate (MAC) unit implemented in TSMC 28nm CMOS.
The
MAC unit multiplies two scalars and accumulates these products using an adder.
To perform this functionality, the MAC unit is composed of multiplication, accumulation, and auxiliary circuitry, colored in Figure 4 with blue, orange, and gray, respectively.
Clock distribution circuitry is not shown, but is included in our results as part of the auxiliary circuitry.
Furthermore, we have implemented the cyclic activation function in hardware, colored in Figure 4 with yellow, which is only used together low-bitwidth accumulators.
To achieve lower cycle times (i.e., a faster operation frequencies), as well as to separate the multiplier’s and accumulator’s critical paths, we introduced a pipeline register between the multiplier and accumulator.
For our implementation results, we consider this pipeline register as part of the multiplication circuitry.
We implemented the circuit in Figure 4 using different bitwidths for the multiplier (8-bit × 8-bit or 3bit × 1-bit) and the accumulator (32-bit or 8-bit).
When using the 8-bit × 8-bit multiplier with the 32bit accumulator, we use 16 bits for the multiplier’s output register to represent all possible products.
When using the 8-bit × 8-bit multiplier with the 8-bit accumulator, we use 8 bits for the multiplier’s output register, since the accumulator does not support larger bitwidths.
When using the 3-bit × 1-bit multiplier, we use 4 bits for the multiplier’s output register, regardless of the accumulator’s bitwidth.
The cyclic activation is only implemented when using the 8-bit accumulator, for both multiplier’s bitwidth.
We implemented the cyclic activation for slopes of k = 2 and k = 4 .
The four different MAC units were synthesized using Synopsys Design Compiler (DC), and automatically placed-and-routed using Cadence Innovus.
Power analysis was done using Cadence
Innovus with stimuli-based post-layout simulations at 0.9V and 25 ◦ C in the typical-typical corner.
For the stimuli, we used weights and activations extracted from a layer of the ResNet-18 network.
Tables 11, 12, and 13 show the implementation results from Figure 2 in tabular form.
Note that throughput is computed as 2 / cycle time, as the MAC unit completes two operations (multiplication and accumulation) in a single clock cycle.
However, in Figure 2, we decided to report cycle time so that, for all metrics presented (cycle time, area- and energy-efﬁciency), a lower value corresponds to a better performance.
Note that circuits with a higher throughput (which corresponds, in this case, to a lower cycle time) often result in higher area and power consumption.
As a matter of fact, dynamic power consumption is directly proportional to operation frequency (i.e., 1 /cycle time).
Thus, to perform a fair comparison, we have normalized the area and power reported in Table 11 by the throughput achieved, resulting in the area- and energy-efﬁciencies reported in Tables 12 and 13, respectively.
[Table] [Table]
[Table]
D U SING MORE WEIGHT BITS
Since ARM provides arithmetic operations that handle multiplication between various 8-bit numbers in parallel, we further conduct experiments in which more bits are used for weight quantization.
[Table]
Table 14 displays the classiﬁcation accuracy, as well as the overﬂow rate of the ﬁnal models.
Surprisingly, in some cases, we may have a lower overﬂow rate even when using more bits for the weight quantization.
We also collect the accuracy degradation from the full precision network.
Our results show that the best performance is achieved when we use 4-bit weights, which is close to the full-precision result (around 0.7% degradation).
[Table]