The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design
Anonymous Author(s)
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Abstract
Placement and routing are two critical yet time-consuming steps of chip design inmodern VLSI systems.
Distinct from traditional heuristic solvers, this paper onone hand proposes an RL-based model for mixed-size macro placement, whichdiffers from existing learning-based placers that often consider the macro by coarsegrid-based mask.
While the standard cells are placed via gradient-based GPUacceleration.
On the other hand, a one-shot conditional generative routing model,which is composed of a special-designed input-size-adapting generator and a bidiscriminator, is devised to perform one-shot routing to the pins within each net,and the order of nets to route is adaptively learned.
Combining these techniques,we develop a flexible neural pipeline, which to our best knowledge, is the first jointplacement and routing network without involving any traditional heuristic solver.
Experimental results on chip design benchmarks showcase the effectiveness of ourapproach, with code that will be made publicly available.
Introduction
The scale of integrated circuits (ICs) has been enlarged dramatically, posing a challenge to thescalability of existing Electronic Design Automation (EDA) technologies.
The increasing circuitdensity raises additional issues for VLSI placers and routers as the component size of modern VLSIdesign continues to drop and on-chip connectivity becomes increasingly sophisticated.
Due togrowing on-chip connectivity, concentrated needs and restricted resources, modern designs are proneto congestion issues and wirelength minimization, which has become a critical task at every stage ofthe chip design process.
Accordingly, placement and routing that physically arranges the locationsand the routes of nets become more crucial in modern VLSI systems.
Placement and global routing 1 are two critical and time-consuming steps in chip design.
On the onehand, the components of a netlist, including macros and standard cells, are mapped to positions onthe chip layout by placement, with standard cells being basic logic cells (e.g. logic gates) and macrosas functional blocks (e.g. SRAMs).
Moreover, the increasingly extensive use of intellectual property(IP) modules and pre-designed macro blocks makes mixed-size placement an indispensable part ofphysical design.
The goal of placement is to optimize power, performance, and area (PPA) metricsmeanwhile obeying the constraints e.g. placement density and routing congestion.
Global routing, on the other hand, creates routing channels inside a layout based on the placementassignment by connecting pins of positioned IC components to a net while adhering to technologicallimits.
It is tightly coupled with the placement task, as an excellent placement solution can result inbetter chip area utilization, timing performance, and routability etc.
The objective of routing is tominimize total wirelength without violating the limits of congestion and critical timing
Differing from the traditional learning-free solvers for placement and routing, learning-based modelsare recently explored and applied to (macro) placement [2, 1] and routing [3], which are mostly basedon reinforcement learning (RL).
Like in vision, language and other domains, an end-to-end networkis often welcomed for the possibility for global optimization of the whole system, while such pureneural networks for joint placement and routing remains unresolved in literature.
In particular, thereare two standing issues worth further study in this paper: i) the macros are of mixed-size with varyingwidth/height [4], bringing difficulty to the discrete grid-based placement by (current reinforcement)learning; ii) the scale of grid size in routing dataset e.g. ISPD-07 [5] can be intractable for RL ascurrently its action has to be designed at the local grid point level [6] rather than generate the wholerouting across grids in one shot.
In this paper, we aim to develop a flexible (mixed-size friendly)approach.
More ambitiously, we further aim to enable a pure neural pipeline with both learnableplacement net and routing net.
Specifically, the placement part is fulfilled by a policy gradient based
RL method for macros by considering their sizes, followed with gradient-based optimization forplacing stand cells.
The routing part involves a conditional generative model to finish the routingacross pins at net level.
The highlights of this work are:
1) We propose an RL-based model for learning mixed-size macro placement, which differs from
existing learning-based placers [1, 2, 7] that often consider the macro by coarse grid-based mask.
As
such, the placement results are more realistic and require less post-processing to resolve collision.
We propose a conditional generative routing network to perform routing, in one-shot for eachnet.
In contrast, existing RL-based solvers [6] need to perform routing step by step at grid point level within each net, in a sequential and inefficient manner.
Moreover, the order for nets to route is
adaptively optimized by learning instead of a pre-fixed one as performed in existing routers.
Combining these techniques, we develop a neural network-based pipeline for placement androuting, which to our best knowledge, is the first pure neural networks for placement and routing 2 .4)
Experimental results on benchmarks show the relatively cost-efficiency (compared with RL-basedrouting solver [6]) and competitive performance.
Source code will be made publicly available.
Related Work
For the inter-discipline nature of this paper, we briefly introduce the necessary background and relatedwork to properly position our work with different communities from EDA to machine learning.
Dueto page limit, classical methods for placement and routing are presented in Appendix A.1.
Learning-based Solvers for Placement.
Machine learning has recently been introduced whichmay help reduce the heuristics.
[7] devises a cyclic framework between the reinforcement learning(RL) and SA modules, in which the RL module alters the relative spatial sequence between circuitcomponents, while SA searches the solution space based on RL initialization.
Following the seminalwork [2] of learning sequential decision-making for macro placement, the method called DeepPlacein [1] proposes a joint learning technique for the placement and subsequent routing via RL.
Learning-based Solvers for Routing.
The recent work [8] presents an attention-based RL methodfor obtaining pin order within each net (rather than net order in this paper which is of much largersize), followed by a classical pattern router.
A DQN agent [6] is developed to decide on the routingdirection on a grid graph at each step.
It makes up a simple 12-element vector to represent the state ofthe environment.
However, the model is trained on synthesized 8 × 8 and 16 × 16 grids, with no morethan 50 nets that consist of 2 or 3 pins.
To make the learning more scalable, a two-page preliminarywork [9] formulates the routing of a net as an image-to-image translation and uses a variationalauto-encoder (VAE) [10] model to generate the solution.
However, the model is merely capable ofhandling a net with no more than three pins on a 64 × 64 grid.
Compared with classic routing solvers,existing RL-based methods can be much more time-consuming, making the end-to-end learning ofboth placement and routing nets very hard.
Moreover, compared with [8] learning the pin order insidea net, we try to learn the order for routing at the net level which is new in literature.
Generative Models for Placement and Routing.
There are emerging works on introducing generative models for chip design.
[11] proposes a generative adversarial network (GAN) [12] guided well generation framework to mimic experts’ behavior from high-quality manually-crafted layouts.[13] adopts a GAN for generating wells and guides the placement in analog circuit layout synthesis.[14] proposes a generative model for the placement optimization of analog integrated circuit basicblocks.
ThermGAN [15] treats the thermal map estimation problem as an image-generation problemusing the generative model.
[16] uses GAN to predict the congestion heatmap to assist classicalrouters.
The work [17] proposes a conditional GAN to solve the multi-terminal path-finding task.
In[18] the generative models are adopted to synthesize diverse layout patterns.
More broadly speaking,generative models have also been recently applied in combinatorial optimization, specifically via alatent space learning and search scheme as done in CVAE-Opt [19].
In this paper, we adopt cGANto generate routes in one shot for each net by regarding the layout to be routed as an image.
To ourbest knowledge, no generative model has been successfully devised and applied to the pin routingproblem for each net, which in fact involves complicated and constrained routing.
Methodology
Approach Overview.
Given a netlist as input, the goal is to place the macros and standard cellson the chip canvas, ideally with a minimized overlapping areas.
Based on the placement results,routing is performed in general to minimize the total wirelength while not violating the constraints.
For placement, we aim to flexibly and efficiently handle the mixed-size macros via an RL scheme,and meanwhile optimize the net order for routing.
For routing, we propose a conditional generativemodel to obtain the routes in one-shot instead of performing sequential pin connection as done inprevious learning-based [6] as well as classic routers [20, 21].
The stacking RL placement networkand generative routing network can be learned via gradient back propagation in an end-to-end manner,which meanwhile completes the whole task in line with the state-of-the-art learning-based placementand routing solvers [1, 2].
Note our work is pure learning based in contrast to [1] that still involvesunlearnable classic routers in the whole pipeline.
The pure neural architecture of our model impliesour model has the potential to enjoy higher capacity by using larger model for further improvement.
3.1 Reinforcement Learning for Mixed-size Placement
A natural idea for classical placers to address the mixed-size issue for placement is to adopt ahierarchical approach based on partitioning.
However, it sacrifices the solution quality since eachsub-problem is solved independently.
Meanwhile, DeepPlace as a learning-based placer assumes thateach macro only occupies one cell in the grid graph and ignores pre-placed macros, which leads toa severe overlap issue in the final placement result.
This motivates us to extend the formulation of
DeepPlace by considering the real size of macros as well as initial placement information.
We stilladopt [22] as the CNN backbone and GCN [23] as the GNN backbone which consists of three layersthat contain 16, 32 and 16 feature channels in policy network which is updated by Proximal Policy
Optimization (PPO) [24], in line with the effective setting adopted in [1].
The revised elements of the
Markov Decision Processes (MDPs) for mixed-size placement are defined as:
• State s t : the state representation still consists of global image I portrayed the layout and
netlist
graph H contains detailed position of placed macros, except that the initial state of I is no longer a
zero matrix I n × n = O .
Instead, our model preprocesses the positions of fixed macros in the dataset
and sets I xy as 1 if ( x, y ) has already been occupied before placement.
• Action a t : the action of RL agent is to find the central of current macro, and position ( x o , y o ) isavailable if all points p in the region R satisfy I p = 0 , where R = { ( x, y ) | | x − x o | ≤ h 2 , | y − y
o | ≤w 2 } and h , w denote the height and width of the current macro respectively.
• Reward r t : to further control the overlap in the final placement, the reward at the end of episode
is a negative weighted sum of wirelength, routing congestion and overlapping area from the final
solution: R E
= − L wl − λ 1 · L cg − λ 2 · L ol as weighted by λ 1 and λ 2 .
3.2 Conditional Generative Learning for Pin Routing in Net
The Global Routing Grid Protocol.
In global routing, the physical chip is usually divided intorectangular areas, as shown in the left part of Fig.
Each area is called a global routing cell (Gcell),which corresponds to a node v i ∈ V in the grid graph G ( V, E ) on the right side.
While each edgee ij ∈ E represents the joint boundary between abutting Gcells v i and v j .
For edge e , its capacity c eis the allowed maximum number of wires that can cross e , and the usage u e is the actual number of wires that e has been assigned.
The overflow o e denotes the amount of wires beyond c e defined asmax (0 , u e − c e ) .
Each route conforms to the rectilinear Steiner tree structure [25].
[Figure]
The overall routing task is composed of numerous nets whose routing can be independent toeach other.
A single net consists of a series ofpins placed in the nodes of the grid graph.
Thusin this paper, we mainly consider the routingover multiple pins in a net.
Given a single net,we formulate the one-net routing problem as themapping from a one-net routing image x to thecorresponding route layout image y , where xcontains three channels: 1) the locations of pins,2) the availability of horizontal grid edges, and 3) the availability of vertical grid edges, and one for y .
As to the output, the value of each pixel of y denotes the likelihood of whether this grid point belongsto the route or not.
Hence, the synthesis of routes can also be viewed as a binary classification of thepixels in y .
The pixels whose likelihood is higher than the threshold are subsequently collected toform the route.
In case of disconnected routes, we apply maze routing to refine the outcomes.
In theinitial design of our model, we do not adopt the random noise z , which mainly leads to producingfairly stochastic outputs, since the routing task barely requires stochasticity.
Our routing model adopts the conditional generative adversarial framework, which has showneffectiveness in image generation.
The generator is composed of a basic generator for the input size of64 × 64 or below (the smaller ones are padded to resize into 64 × 64) and an extension for the inputsize of larger than 64 × 64.
The discriminator consists of two sub-discriminators to estimate routesfrom validity and realness.
We, furthermore, design an enhanced loss to improve the performance ofour model.
The structure of the generative model is visualized in Fig.
3.2.1 Layout Input
-size-Adapting Generator
During routing, the physical chips are decomposed into Gcells in terms of various widths and heightsas shown in Fig.
1, causing the diversity of the scale of the corresponding grid graphs.
To make itmore tractable, we develop an input-size-adapting generator to handle various grid graphs.
First, we construct a basic generator, G base , to solve grids not larger than 64 × 64 as the chip is dividedinto 64 × 64 tiles in the macro placement stage.
The architecture proposed by [26] is partly adoptedas the backbone of G base , which has been proven successful in generative tasks.
Our basic generatorcontains four components : 1) a convolutional front-end, 2) a series of residual blocks, 3) a transposedconvolutional component, and 4) a convolutional layer to generate the output.
Second, to handle larger grids, we establish another generator G large , which is composed by twosub-networks: G inner and G outer ( G i and G o , for simplicity).
G i and G o are termed as the guidingnetwork and the filling network, respectively.
The guiding network consists of the first three parts that
G base owns.
In contrast, the components of filling network is similar to G base , and correspondinglywe use G ko ( k = 1 , 2 , 3 , 4) to denote them.
We feed the input grid to G 1 o to obtain a feature map, anddownsample the input grid to feed G i to acquire another feature map.
G 2 o takes in the element-wisesum of these two feature maps and integrates the guiding information into G o , and the hybrid featuremap then is converted into the output.
The architecture of our generator is illustrated in Fig. 2(left).
We can further incrementally stack additional sub-networks on G large , and model compressiontechniques can be used to help keep the inner network neat.
While training the networks, we firstpre-train the sub-networks separately, and then we jointly train them to fine-tune the whole network.
Remarks.
The CNN-based generator coincides with routing: 2-D neighborhood structure, translationequivariance and locality.
Amid routing, chips are formulated as grids, which are further transformedinto images.
Routing also exhibits translation equivariance since translating a whole net with thecontext will not change the routing result.
Moreover, for each grid node, the convolution kernelgathers the information from locally adjacent vertices, especially those directly connected to it, toform local routing features.
The holistic route is then produced.
Rather than simply stacking layersto handle long-range dependencies, the well-trained guiding network provides global informationequivalent to long-range dependencies.
2 Bi-Discriminator to Consider both Realness and Connectivity
Routing problems have an inherent constraint that all pins should be connected.
Therefore wedevise a discriminator to evaluate the connectivity of the output.
To effectively train the connectivitydiscriminator, we develop an algorithm to accurately figure out the connectivity of each fake and realroute, and then we employ the results as labels.
Connectivity alone is not sufficient to evaluate theauthenticity of the output, so we adopt another discriminator to estimate the realness of the output, asthe original discriminator in GAN.
Overall, the adversarial loss of our model can be expressed as
[Equation]
1) where D 1 and D 2 denote the connectivity discriminator and the realness discriminator, respectively,and λ 1 and λ 2 represent the corresponding weights s.t.
λ
1 + λ 2 = 1 .
The discriminators share theconvolutional front-end and a stack of L = 3 convolutional and residual blocks, and then they makeevaluations from different angles as depicted in the right part of Fig.
3.2.3 Enhanced Model Loss
With the cGAN objective mixed with a traditional loss, such as L1 and L2 loss, training is inefficientas most grid points are easy negatives that cannot yield effective learning signals.
In addition, tons oftrivial negatives impair the training and give rise to a degraded model, and the output, thus, inclinesto converge to an empty route.
To bridge the gap between easy negatives and scarce positives, weapply the focal loss [27] and modify it to fit our task:
[Equation]
where i = 1 , . .
. , N represents grid points, and y i and g i respectively denotes the real and generatedvalue of corresponding grid point.
We also incorporate the L2 loss into our objective to approach thereal routes, and because it has been found beneficial to the synthesis [28, 29].
The introduction of the connectivity discriminator improves the correctness of the results, but at thesame time, it may slightly increase the wirelength.
Since the wirelength has an accurate theoreticallower bound, i.e. half-perimeter wirelength (HPWL) of the bounding box of a net, we take thedifference between the length of the generated route and the HPWL as a regularization term to limit the wire length.
We use L r ( G ) =
E x [ ∥ l ( G ( x )) − h ( x ) ∥ 1 ] to represent the regularization term,where l ( G ( x )) denotes the length of the generated route, and h ( x ) denotes the HPWL of the net.
The overall enhanced objective of our model gathers the above losses:
[Equation]
where µ FL , µ L 2 and µ r are defined as the factors of L FL , L L 2 and L r , respectively.
3.3 Neural Macro Placement and Routing Pipeline
Combining the RL-based model for learning mixed-size macro placement with one-shot generativerouting network to perform routing as we introduce above, we propose a pure neural pipeline formacro placement and routing.
Fig.
3 shows the flow of our mixed-size macro placer with adaptivereward function between coarse HPWL estimation to wirelength from the neural router.
Given thecircuit information, our mixed-size agent sequentially places the macros on the chip layout, afterwhich the generative model for routing is adopted to connect the net chosen by net order agent andcalculate wirelength as feedback.
Inspired by EM algorithm, we first update the generative routerusing placement result from mixed-size agent (similar to E step ), then placement and net order agentsare learned jointly in a whole reinforcement learning framework to minimize wirelength calculatedby trained generative model (corresponding to M step ) following a recursive pattern.
3.3.1 Reward Adaptation between Coarse HPWL and Router’s WL
For classical placers, HPWL is a common metric for estimating the true wirelength decided byrouting.
In our neural pipeline, however, we apply a one-shot generative routing network to route allthe nets directly, which reduces bias in the reward signal.
Nevertheless, it is worth noting that theuntrained policy network for placement would start with random weights so that placement resultsare of low quality.
As a result, the distribution of pins in a single net will spread out, which is difficultfor a generative model-based router to produce accurate route layout images.
To tackle this problem,we propose an adaptive scheme to calculate wirelength for our placement agent, integrating HPWLand neural router’s output simultaneously.
We introduce variable λ to scale two values and define thesmoothed wirelength WL s as follows:
[Equation]
where WL n is the feedback of neural router.
In each iteration, variable λ is updated by function1 − e − 0 .
01 · n iter .
Initially, λ begins with 0 so that the wirelength is determined by HPWL that servesas a coarse reward signal.
As the training proceeds, the feedback of neural router gradually becomesa prominent factor to provide a more accurate objective for the placement agent.
3.3.2 Learning Net Order to Route
The order in which nets are routed is one of the most critical factors that affects the routing quality [30].
Most classical routers determine the net order by heuristics, e.g., routing smaller nets earlier [31] dueto the flexibility of finding free path.
However, there are diverse definitions for “smaller net”, none of which is proved to be optimal.
What makes the situation worse, the complexity of real routingprocedure requires us to change the net order dynamically, which is hard to implement in such acomplicated system.
Fortunately, our neural router divides the routing task into a series of one-netrouting problems and then solves them independently, making it convenient to learn the net order.
We build net order learning module upon the neural router by developing a RL agent to determinewhich net to route next.
Inspired by the structure of placement agent, the state of net order problemconsists of routing image R as a representation of current routing layout, and graph G indicating theconnectivity between nets.
There are three channels of R : the locations of routed net, the capabilityof horizontal and vertical grid edges.
Graph G is an edge-to-vertex dual of netlist graph H , whosevertices denote nets (i.e., hyperedges of H ) and edges denote common cells between nets (i.e., nodesof H ).
Note that the state of placement and net ordering tasks are quite similar while both seek tominimize the total wirelength, we combine them into a whole RL framework by adopting same policynetwork to generate feature embeddings for two tasks respectively.
The united structure withoutheuristic solver reflects the strongly coupled relationship between placement and routing, whichdiffers from [1] that merely applies router as a black box to calculate the reward.
Experiments
4.1 Protocols and Setup
Experiments are conducted on a server with RTX 3090 GPUs and AMD 3970X 32-Core CPU, andimplemented by PyTorch.
We term our whole approach for placement and routing as PRNet .
Benchmarks & Datasets.
For placement, we validate our RL agent for mixed-size macro placementusing ISPD-2005 benchmark [32] after pre-processing, such that most fixed macros are exchangedfor movable ones in line with [1].
For routing 3 , we choose the ISPD-07 [5] benchmarks to producerouting instances and use the routes generated by the strong classic router [33] as training labels.
In the ISPD-07 benchmarks, some nets can contain up to hundreds of pins, but the average amountof pins in a single net is still about 4.
In other words, massive nets contain no more than 4 pins.
Therefore, the routing model should have sufficient ability to route the easy nets.
From around 750Krouting instances, we collect 30K 64 × 64 nets as the Route-small-4 dataset whose instance containsup to 4 pins, 80K 64 × 64 samples as Route-small, and 100K 128 × 128 samples as Route-large toevaluate the model’s ability.
Each of the three datasets is randomly divided into a training set (80%)and a test set (20%).
These three training sets are used to train generative routing models and pick upthe best one according to their performance on the test sets.
Then we continue to train the best 64 × 64model with additional 200K 64 × 64 instances and train the 128 × 128 model with additional 400K128 × 128 instances, which is used to perform experiments on the ISPD-98 routing benchmarks [34].
Training.
To train the placement and net ordering RL agent, we use PPO [24] to update the policynetwork and Adam optimizer [35] is utilized with a learning rate of 2.5 × 10 − 4 .
For training therouting models, we use Adam with learning rate of 2 × 10 − 4 , β 1 = 0 .
5 , β 2 = 0 .
999 and a weightdecay of 0.01.
We employ a batch size of 64.
A linear learning rate decay is also applied.
Evaluation.
In mixed-size placement, we adopt HPWL as the proxy of wirelength and overlappingarea to evaluate both methods while we introduce wirelength (WL) and routing congestion (RC)
[36]in overall placement and routing.
For routing, since there is little metric for generative routingmodel, we introduce the metrics correctness rate (CrrtR) and wirelength ratio (WLR) to evaluatethe generated results of generative models on the datasets.
CrrtR signifies the ratio of the amountof connected overflow-free routes to the number of all routes, or in short the accuracy of generatedresult.
WLR represents the ratio of the total wirelength of connected overflow-free routes to the totalwirelength of the corresponding real routes.
Lower WLR indicates that the route requires fewer wires.
In the experiments on the ISPD-98 routing benchmarks, wirelength, overflow and runtime are used.
4.2 Results on Mixed-size Placement
We compare the total wirelength together with overlapping area of our mixed-size approach with thestate-of-the-art and open-sourced method called DeepPlace [1] as shown in Table 1.
Both methodsgenerate intermediate macro placement via RL, and then adopt gradient-based optimization placeras used in [37] to obtain complete placement solution.
With only a slight increase of the total
[Figure]
[Table]
wirelength (within 1.3% difference on average), our mixed-size macro placer achieves approximately4 × reduction over DeepPlace on the overlapping area, stressing the importance of modeling macro’sshape in state space.
Moreover, the reduced overlapping area requires less post-processing to resolvecollision, which facilitates improvement of wirelength in the long term.
Examples of our mixed-sizeplacer and DeepPlace on circuit bigblue 1 are visualized in Fig.
4.3 Results on Routing
Comparison of Generative Backbones.
We compare our model with a CVAE based router using
CNN as the backbone [9] and use CVAE*(CNN) to denote it.
We then combine the CVAE*(CNN)with a vanilla discriminator and our bi-discriminator to build CVAE*-GAN and CVAE*-bcGAN,following the idea of [38].
In addition, we implement a U-Net based cGAN following pix2pix
[29]and use cGAN(U-Net*) to denote it.
Then we remove the discriminator to obtain a U-Net [39]generator and define it as U-Net*.
We further replace the discriminator of cGAN(U-Net*) withour bi-discriminator.
We also try to train the RL agent following the work of [6], but it fails toconverge after 2-week training.
Table 2 shows the results.
The ResNet-based [40] models outperformthe counterparts based on CVAE*(CNN) and U-Net*.
Our model achieves approximately 2 ×correctness rate, 14.7% improvement of the wirelength on Route-small-4 and 2.4% on Route-smallover CVAE*(CNN).
The vanilla cGAN discriminator slightly improves CVAE*(CNN) and U-Net*on one side while sacrificing the other side, and it debases the ResNet generator.
However, thebi-discriminator strengthens the generators except for the CVAE*(CNN).
Ablation Studies.
We conduct ablation experiments to investigate the contributions of the designchoices in our model.
In Table 2, we compare the full version with ResNet-based cGAN, as wellas the pure ResNet generator.
The ResNet generator outdoes the cGAN, but the bi-discriminatorsignificantly improves the generator.
Moreover, the enhanced loss improves the wirelength at themarginal expense of correctness.
Appendix A.5.1 contains further details of comparison among lossfunctions, and Appendix A.5.2 shows the effectiveness of the input-size-adapting network.
[Table]
[Table] [Table]
Test Results.
We test our conditional generative routing model on the ISPD-98 benchmarks andcompare the wirelength, overflow and runtime with three classical routers that perform best on
ISPD-98 benchmarks.
Table 9 shows the results.
Our generative routing model presents competitiveconsequences on wirelength, while it takes a longer time to accomplish the routing task, comparedwith strong heuristic baselines [30, 41, 42].
Our model takes an image encoded from the whole gridwith a net as the input and sequentially solve each net in a one-shot manner, while classical routersonly consider the local area, which may obtain fewer wirelength yet consume more time.
However,it is still much more efficient and easier to train than the RL-based router [6] from our empiricalexperience.
We leave the speedup of our generative model for future work.
4.4 Results of Overall Placement and Routing with Ablation Study on Net Order Learning
We compare our PRNet with DeepPlace, along with an ablation study to verify the impact of netorder learning.
The circuits used for evaluation are the same as in mixed-size placement, and weconcentrate on macros only for simplicity.
Note that the real shape of macros is ignored and thegrid-based mask is coarser in [1], hence the results shown in Table 3 are not identical to those inthe original paper [1].
For all test cases, our neural placement and routing pipeline outperforms theother two methods in terms of both wirelength (WL) and routing congestion (RC).
The significantdifference in routing congestion without net order learning indicates that net order agent is able toarrange the sequence of routing efficiently, especially on circuit adaptec 3 .
As a result, it is easy forevery net to find free routing path while keeping away from congested area.
In addition, trainingplacement model with generative neural router in an end-to-end manner further improves the finalwirelength, despite a little degradation of routing congestion if we discard the net order agent.
Conclusion and Discussion
We have presented a neural mixed-size placement and routing pipeline.
The routing is achieved byone-shot generation of the whole path, with our devised net order learning module to dynamically adjust the routing order.
Experimental results show the effectiveness of our approach
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A Appendix
In this appendix, we give more description on the classic learning-free solvers.
We also give morediscussion on the possible limitation of the method.
More importantly, we devise two additional methods for further empirical comparison, particularlywith other (older) classic routing solvers.
The results show that our generative router is indeed muchmore efficient than RL-based peer method which in fact is our implementation of the recent work [6].
Though our presented generative router in the main text is less efficient than state-of-the-art routers:
NTHU-Route 2.0 [30], BoxRouter 2.0 [41], FastRoute 3.0 [42], while we show that our speedupversion (by approximate parallelization of net routing) is comparable to extra classic routing solvers:
Labyrinth 1.1 [43], Fengshui 5.1 [44] and BoxRouter [45] in runtime, on our limited computingresource (a server with RTX 3090 GPUs and AMD 3970X 32-Core CPU).
We believe there is muchroom to improve the cost-efficiency of our generative router by more careful parallelization design andmore efficient code-level implementation as current compared routers are all written and optimized in
C/C++ while we use PyTorch.
We hope our appendix can help the reviewers make more informative review and decision.
Thesource code and trained models used in the appendix will also be made publicly available.
A.1 Related Work on Classic Solvers for Placement and Routing
Classic Solvers for Placement.
Global placement solvers have been studied for a long history [46,47 ], as basically in three categories: partitioning-based methods, stochastic/hill-climbing methods,and analytic solvers.
Partition-based approaches utilize the divide-and-conquer strategy in the earlyyears, after which multi-level partitioning algorithms [48] are devised, with many stochastic methodsusing annealing [49].
When regarding to analytic solvers, force-directed algorithms [50] and nonlinear optimizers [51, 52] are extensively adopted.
Modern analytical placers, e.g. ePlace [53]and RePlAce [36], have recently introduced an electrostatics-based system that contains globalsmooth density cost function and nonlinear optimizers, which are accelerated by DREAMPlace [37]later based on deep neural network.
Mixed-size placement attracts attention for its practical value.
Hierarchical [54] and constraint graph-based [55] are proposed to place large scale mixed size designs.
Classic Solvers for Routing.
According to the way for solving global routing, there are two typesof classic methods: concurrent and sequential solvers.
Concurrent approaches attempt to handlenumerous nets simultaneously.
BoxRouter [45] develops progressive integer linear programming(ILP) and adaptive maze routing to diffuse the congestion.
BoxRouter 2.0 [41] further provides amore systematic way of eliminating congestion and assigning layers to wires.
GRIP [56, 57], built ona partitioning strategy in a 3D manner, obtains the ideal wirelength but leads to prohibitive runtime.
While sequential approaches typically employ net decomposition [58], maze routing [59], patternrouting [43], or negotiation-based rip-up and rerouting (NR&R), and solely route a 2-pin net everytime (e.g. [20, 21, 60, 33]).
The sequential methods have been often shown faster than the concurrentapproaches, but they may rely on the ordering of the nets and thus leading to sub-optimal solutions.
A.2 Limitation
The limitation refers to our end-to-end pipeline which can be a little blackbox compared with heuristicalgorithms.
Moreover, the conditional generative routing model is currently trained on the routesgenerated by the state-of-the-art classical router.
Therefore, the performance of the routing modelmay be limited by the router.
Unsupervised learning and semi-supervised learning are possibleapproaches to break the performance limitation.
A.3 Negative Social Impact
We have not identified potential negative social impact of our work.
A.4 Additional Methods: an RL Router and Speedup
Generative
To make a more comprehensive study, we further devise two additional routing methods for comparison.
One is an RL-based router following [6] which only gives limited result on small-scale dataset that is generated randomly.
The other is a concurrent version of our proposed generative router, tospeed up the routing process.
A.4.1 Our Implemented RL Router
The RL-based router in our experiment is based on recent work [6] that decides actions of therouting direction, i.e. going north, south, etc in each step.
In our implementation, we enlarge thegrid size from 8 × 8 to 16 × 16 while ignoring different layers in routing, as we concentrate oncalculating the final wirelength in more realistic cases.
The structure of our Q-network consists ofthree fully-connected layers with 128 hidden units in each layer.
Reward is set as − 1 for all validactions, except that the reward of finding terminal pin is 50 and a penalty of − 50 is supposed to payfor invalid action which makes the capacity of routing path smaller than zero.
A.4.2 Speedup Version of Our Generative Router
In the main text, our generative router routes the nets sequentially (i.e. one net by one net) such that itproduces routes with lower wirelength and overflow.
In another word, the batch size in the inferencestage for the deep routing network is 1 which is not common and does not release the computingadvantage of GPU.
To speed up our generative router, we set the batch size to 128 in the inferencestage to enable our router to run in a concurrent manner.
However, the concurrent version may degenerate the performance of the outputs on wirelength andoverflow.
As illustrated in Fig.
5, the bounding box of net 1 overlaps with that of net 2 , and thebounding box of net 3 is far away from them.
When routing these three nets concurrently, the routesof net 1 and net 2 may intersect with each other and cause conflict in the usage of routing capacity,which leads to overflow and makes routing harder for the rest of nets.
A.5 Additional Results
A.5.1 Ablation Study for Loss Function of the Routing Model
In this experiment, we utilize our conditional generative routing network as the base model and verifythe effectiveness of the enhanced loss function.
Our adversarial loss is
[Equation] [Equation]
where we set λ
= λ 2 = 0 .
5 by default.
While our focal loss is
[Equation] [Equation]
[Table] [Table]
where we set α = 0 .
5 and γ = 2 by default.
For the enhanced loss, it can be expressed as
[Equation]
(7) where we set µ FL = µ L 2 = 5 × 10 3 and µ r = 0 .
1 in all our experiments.
In Table 5, focal loss delivers the best correctness rate while introducing higher wirelength.
Incontrast, the L2 loss is opposite of the focal loss.
The enhanced loss combines the advantages ofthese two loss functions and obtains a competitive correctness rate and the best wirelength ratio.
A.5.2 Input-size-Adapting vs. Non-Input-size-Adapting
We explore the performance difference between our input-size-adapting network (represented by
ISA) and a non-input-size-adapting variant (represented by Non-ISA).
The Non-ISA follows thestructure of our basic generator.
Its convolutional front-end contains one more layer, and it has threeadditional residual blocks.
The ISA utilizes the well-trained basic generator in part as the guidingnetwork to obtain a feature map, and it further uses another convolutional front-end as the fillingnetwork to acquire another feature map.
Then the element-wise sum of the feature maps are fed intoa series of residual blocks and a decoder to generate the output.
We compare the Non-ISA with 3variants of our ISA (without pre-training the filling network, pre-training the filling network for 50epochs and pre-training the filling network for 100 epochs).
The ISA outperforms the Non-ISA asillustrated in Table 6, while the variants pre-trained for different number of epochs behave similarly.
Fig.
6 shows the training plot for the Non-ISA, the ISA and the basic generator.
The variants of the
ISA pre-trained for diverse amounts of epochs share similar training curves.
The training of all thenetworks is stable, and the ISA converges faster than the Non-ISA and achieves a better result since itpartly inherits the well-trained basic generator and the filling network has also been pre-trained.
A.5.3 Additional Experiments of Generative Backbones
We extend the dataset Route-small to a larger dataset named Route-small-extension that contains650k instances from 3 circuits as the training set and 200k samples from another circuit as the test set.
We conduct additional experiments of generative routing models on Route-small-extension to make
[Table]
[Table]
further comparison among the generative backbones.
The results are shown in Table 7, which is anextension to Table 2.
A.5.4 Comparison with RL-based Router
Table 8 compares the results between our conditional generative routing model and RL-based routeron circuit adaptec 1 from ISPD-2005 benchmark.
Our conditional generative router is much moreefficient than the RL-based router, achieving approximately 10 × speedup.
In addition, the overflowof RL-based router is greater than zero, which degrades the performance of wirelength in the longrun.
Note the maximal grid size that RL router can deal with is 16 × 16 while our generative routingmodel is still applicable for grids larger than 64 × 64 .
Such limitation on size and extremely lowefficiency make RL-based router not an option in neural macro placement and routing pipeline
[Table] [Table]
A.5.5 Comparison with a Concurrent Version of Our Router and Other Classic Routers
We first test our conditional generative routing model with each net routed sequentially (i.e. a batchsize of 1) on the ISPD-98 benchmarks.
In addition, we run our generative router with nets routedconcurrently (a batch size of 16), which may trade wirelength and overflow for runtime, and wereimplement the post-processing module by C++.
The sequential and concurrent variants of ourgenerative routing model are defined as Sequential and Concurrent, respectively.
We further comparethe wirelength, overflow and runtime with three more classical routers, Labyrinth 1.1 [43], Fengshui5.1 [44] and BoxRouter [45].
Since these three routers are not open-source and are difficult toreproduce, we directly use the experimental results in their papers.
The experiments of the classicalrouters are performed on a 1.4GHz PentiumIII workstation with Linux operating system.
Ourexperiments are performed on a server with RTX 3090 GPUs and AMD 3970X 32-Core CPU.
Table 9 shows the results.
On the one hand, our sequential generative routing model outperformsthe classical routers on wirelength and overflow, while it takes a longer time to accomplish therouting task, compared with strong heuristic baselines.
On the other hand, our concurrent versiondramatically speeds up the running ( 3 .
36 ∼ 7 . 98 × speedup) of generative routing model at theexpense of total wirelength and overflow, and it still performs better than the three classical routerson wirelength and overflow, except the overflow on ibm 05 and the overflow of BoxRouter on ibm 03and ibm 06 .
Modifying our algorithms and finding other techniques to cut down the runtime are stillbeing explored.
A.5.6 Additional Visualization of Mixed-size Placement
Despite circuit bigblue 1 , two additional visualization of our mixed-size placer and DeepPlace oncircuits adaptec 2 and adaptec 4 are elaborated in Fig.
[Figure]