Original: Quantum Circuit Compilation: An Emerging Application for Automated Reasoning
Revised: Quantum Circuit Compilation: An Emerging Application for Automated Reasoning

Original: Abstract
Revised: Abstract

Original: Quantum computing is an information processing paradigm with the potential to solve certain problems faster than any algorithm running on classical computer architectures.
Revised: Quantum computing is an information processing paradigm with the potential to solve certain problems faster than any algorithm running on classical computer architectures.

Original: In the next few years, new processors will be developed that support quantum computations exceeding the simulation abil- ity of even the largest classical computer systems.
Revised: In the next few years, new processors will be developed that support quantum computations exceeding the simulation abil- ity of even the largest classical computer systems.

Original: A number of academic and industrial groups are developing pro- totypes of such devices, also known as NISQ (Noisy Intermediate Scale Quantum) processors.
Revised: A number of academic and industrial groups are developing pro- totypes of such devices, also known as NISQ (Noisy Intermediate Scale Quantum) processors.

Original: Much as software must be compiled to run on classical computers, quantum algorithms must be compiled to take into account the constraints of particular NISQ devices.
Revised: Much as software must be compiled to run on classical computers, quantum algorithms must be compiled to take into account the constraints of particular NISQ devices.

Original: Especially in these early prototypes, algorithm performance degrades with runtime due to noise; for this reason, minimizing the runtime of the compiled algorithm (which is represented by a ”quantum circuit”) is critical.
Revised: Especially in these early prototypes, algorithm performance degrades with runtime due to noise; for this reason, minimizing the runtime of the compiled algorithm (which is represented by a ”quantum circuit”) is critical.

Original: We describe a software framework to enable an automated reasoning approach to Quantum Circuit Compi- lation for NISQ architectures (QCC-NISQ), and our current implementation of it as part of software suite for automated, architecture-aware, compilation for emerging quantum computers.
Revised: We describe a software framework to enable an automated reasoning approach to Quantum Circuit Compi- lation for NISQ architectures (QCC-NISQ), and our current implementation of it as part of software suite for automated, architecture-aware, compilation for emerging quantum computers.

Original: The key components of this suite are a circuit synthe- sizer, a QCC solver, and a visualizer.
Revised: The key components of this suite are a circuit synthe- sizer, a QCC solver, and a visualizer.

Original: These tools provide critical support for the continued development of practical quan- tum computers and research into quantum algorithms.
Revised: These tools provide critical support for the continued development of practical quan- tum computers and research into quantum algorithms.

Original:  Introduction
Revised:  Introduction

Original: Quantum computing is an emerging computational paradigm with the potential to solve certain problems faster than any algorithm running on classical computer architectures.
Revised: Quantum computing is an emerging computational paradigm with the potential to solve certain problems faster than any algorithm running on classical computer architectures.

Original: The breadth of quantum computing applications will become clearer in the next few years as new processors are developed that support quantum computations exceeding the simulation ability of even the largest classical supercomputers.
Revised: The breadth of quantum computing applications will become clearer in the next few years as new processors are developed that support quantum computations exceeding the simulation ability of even the largest classical supercomputers.

Original: The emerging gate-model noisy, intermediate scale quantum (NISQ) processor units, currently in the prototype phase, are universal in that, once scaled up, they can run any quantum algorithm.
Revised: The emerging gate-model noisy, intermediate scale quantum (NISQ) processor units, currently in the prototype phase, are universal in that, once scaled up, they can run any quantum algorithm.

Original: Much as software must be compiled to run on classical computers, quantum algorithms, also referred to as logical quantum circuits , must be compiled to take into account the constraints of particular NISQ devices.
Revised: Much as software must be compiled to run on classical computers, quantum algorithms, also referred to as logical quantum circuits , must be compiled to take into account the constraints of particular NISQ devices.

Original: Especially in these early prototypes, algorithm performance degrades with runtime due to noise; for this reason, minimizing the runtime of the compiled circuit is critical.
Revised: Especially in these early prototypes, algorithm performance degrades with runtime due to noise; for this reason, minimizing the runtime of the compiled circuit is critical.

Original: Current NISQ architectures have geometric limitations (e.g., connectivity), the speciﬁcs of which vary from processor to processor.
Revised: Current NISQ architectures have geometric limitations (e.g., connectivity), the speciﬁcs of which vary from processor to processor.

Original: In this paper, we concentrate on the problem of producing optimally-compiled circuits given the geometric limitations of the processor.
Revised: In this paper, we concentrate on the problem of producing optimally-compiled circuits given the geometric limitations of the processor.

Original: Variants of this problem are known as the qubit mapping, qubit routing, qubit allocation, and qubit movement problem.
Revised: Variants of this problem are known as the qubit mapping, qubit routing, qubit allocation, and qubit movement problem.

Original: We refer to this problem as Quantum
Revised: We refer to this problem as Quantum

Original: Circuit Compilation for NISQ architectures (QCC-NISQ).
Revised: Circuit Compilation for NISQ architectures (QCC-NISQ).

Original: We focus on solid-state architectures based on superconducting quantum bits (qubits), which are among the most advanced NISQ processors.
Revised: We focus on solid-state architectures based on superconducting quantum bits (qubits), which are among the most advanced NISQ processors.

Original: As one example of a geometric limitation, the planar architecture of these processors means that quantum operations can be carried out only between nearest-neighbor locations (qubits).
Revised: As one example of a geometric limitation, the planar architecture of these processors means that quantum operations can be carried out only between nearest-neighbor locations (qubits).

Original: A variety of small superconducting processors, with varying architectures, already exist.
Revised: A variety of small superconducting processors, with varying architectures, already exist.

Original: Such processors include the 20-qubit IBMQ by IBM made available through the Q-Network (IBM Corp.
Revised: Such processors include the 20-qubit IBMQ by IBM made available through the Q-Network (IBM Corp.

Original: 2018); the 8-, 16-, and 19-qubit chips by Rigetti Computing (Rigetti Computing 2018), and the 72-qubit Bristlecone processor unveiled recently by Google (Google AI Blog 2018).
Revised: 2018); the 8-, 16-, and 19-qubit chips by Rigetti Computing (Rigetti Computing 2018), and the 72-qubit Bristlecone processor unveiled recently by Google (Google AI Blog 2018).

Original: The 50-qubit Intel Tangle Lake chip (Intel Corp.
Revised: The 50-qubit Intel Tangle Lake chip (Intel Corp.

Original: 2018) and
Revised: 2018) and

Original: a new IBM 50-qubit device are under test and evaluation.
Revised: a new IBM 50-qubit device are under test and evaluation.

Original: Other commercial players in the superconducting NISQ race include Alibaba (Alibaba Cloud 2018) and
Revised: Other commercial players in the superconducting NISQ race include Alibaba (Alibaba Cloud 2018) and

Original: Quantum Circuits Inc.
Revised: Quantum Circuits Inc.

Original: (Ofek et al. 2016).
Revised: (Ofek et al. 2016).

Original: In this paper, we detail our software suite based around applying AI Planning, aided by Constraint Programming (CP), to solve the QCC-NISQ problem.
Revised: In this paper, we detail our software suite based around applying AI Planning, aided by Constraint Programming (CP), to solve the QCC-NISQ problem.

Original: Our suite targets: (1) multiple gate-model quantum computing hardware platforms built by different companies (speciﬁcally, at the time of writing, Google, Rigetti, and IBM), and (2) different combinatorial optimization problems that can be solved with speciﬁc quantum algorithms such as the quantum alternating operator ansatz algorithm (QAOA) (Hadﬁeld et al. 2019)
Revised: Our suite targets: (1) multiple gate-model quantum computing hardware platforms built by different companies (speciﬁcally, at the time of writing, Google, Rigetti, and IBM), and (2) different combinatorial optimization problems that can be solved with speciﬁc quantum algorithms such as the quantum alternating operator ansatz algorithm (QAOA) (Hadﬁeld et al. 2019)

Original: (e.g., Max-Cut, graph coloring, and job shop scheduling).
Revised: (e.g., Max-Cut, graph coloring, and job shop scheduling).

Original: While we have previously published technical details on how we model and solve the QCC-NISQ problem, in this paper we report not only on the actual QCC-NISQ solver, but also on our software suite in its entirety: its components, engineering, and deployment in this promising application area for AI technologies.
Revised: While we have previously published technical details on how we model and solve the QCC-NISQ problem, in this paper we report not only on the actual QCC-NISQ solver, but also on our software suite in its entirety: its components, engineering, and deployment in this promising application area for AI technologies.

Original: In the circuit model of quantum computation, a quantum algorithm is expressed conceptually as a logical quantum circuit , consisting of a series of quantum operations called quantum logic gates .
Revised: In the circuit model of quantum computation, a quantum algorithm is expressed conceptually as a logical quantum circuit , consisting of a series of quantum operations called quantum logic gates .

Original: Quantum processors are physical devices that implement these quantum logic gates so that the desired quantum operations can be carried out on the quantum states stored in the qubits.
Revised: Quantum processors are physical devices that implement these quantum logic gates so that the desired quantum operations can be carried out on the quantum states stored in the qubits.

Original: In simple cases, the quantum logic gates directly correspond to physical quantum gates on the quantum processor, but more typically the processor has physical constraints that prevent a quantum logic circuit, describing the desired algorithm, from being directly implemented.
Revised: In simple cases, the quantum logic gates directly correspond to physical quantum gates on the quantum processor, but more typically the processor has physical constraints that prevent a quantum logic circuit, describing the desired algorithm, from being directly implemented.

Original: Atahigh level, these constraints can be classiﬁed into two types: (1) gate set constraints (i.e., those that specify the set of logic gates the processor is capable of applying), and (2) geometric constraints (i.e., those that specify upon which sets of qubits the available logic gates can be applied, limited by, for example, processor connectivity).
Revised: Atahigh level, these constraints can be classiﬁed into two types: (1) gate set constraints (i.e., those that specify the set of logic gates the processor is capable of applying), and (2) geometric constraints (i.e., those that specify upon which sets of qubits the available logic gates can be applied, limited by, for example, processor connectivity).

Original: Although these constraints differ among quantum processors, quantum algorithms can be re-expressed respecting the processor constraints with polynomial overhead in the number of gates (Brierley 2017).
Revised: Although these constraints differ among quantum processors, quantum algorithms can be re-expressed respecting the processor constraints with polynomial overhead in the number of gates (Brierley 2017).

Original: As such, for theoretical algorithmic work, the design of logical quantum circuits without concern for the implementation constraints of physical devices is sufﬁcient.
Revised: As such, for theoretical algorithmic work, the design of logical quantum circuits without concern for the implementation constraints of physical devices is sufﬁcient.

Original: However, to implement a quantum algorithm on an actual device, these constraints must be efﬁciently addressed to take full advantage of NISQ processors.
Revised: However, to implement a quantum algorithm on an actual device, these constraints must be efﬁciently addressed to take full advantage of NISQ processors.

Original: In this work, we focus on a particular approach to addressing geometric constraints associated with processor connectivity.
Revised: In this work, we focus on a particular approach to addressing geometric constraints associated with processor connectivity.

Original: The approach maps logical qubits to physical qubits on the processor and iteratively updates the mapping through the insertion of additional gates in the course of the computation so as to enable the logical operations to be implemented respecting the physical contraints.
Revised: The approach maps logical qubits to physical qubits on the processor and iteratively updates the mapping through the insertion of additional gates in the course of the computation so as to enable the logical operations to be implemented respecting the physical contraints.

Original: This problem is often referred to as “quantum compilation,” though quantum compilation usually involves addressing gate set constraints as well as geometric (e.g., connectivity) constraints.
Revised: This problem is often referred to as “quantum compilation,” though quantum compilation usually involves addressing gate set constraints as well as geometric (e.g., connectivity) constraints.

Original: Another simple constraint is that gates involving the same qubit cannot be executed in parallel.
Revised: Another simple constraint is that gates involving the same qubit cannot be executed in parallel.

Original: A generalization of this constraint is a “cross-talk” constraint that may prevent gates in physical proximity from being executed at the same time (Booth et al. 2018).
Revised: A generalization of this constraint is a “cross-talk” constraint that may prevent gates in physical proximity from being executed at the same time (Booth et al. 2018).

Original: QCC-NISQ frequently requires adding supplementary operations supported by the hardware to those speciﬁed in the idealized circuit.
Revised: QCC-NISQ frequently requires adding supplementary operations supported by the hardware to those speciﬁed in the idealized circuit.

Original: Current superconducting quantum processors have planar architectures with connections only between nearest-neighbor locations (qubits), resulting in restrictions as to where gates can be applied.
Revised: Current superconducting quantum processors have planar architectures with connections only between nearest-neighbor locations (qubits), resulting in restrictions as to where gates can be applied.

Original: Speciﬁcally, a gate can operate only on qubit states located on adjacent qubits on the chip.
Revised: Speciﬁcally, a gate can operate only on qubit states located on adjacent qubits on the chip.

Original: To compensate for the nearest-neighbor limitation, swap gates can move qubit states between connected qubits to reach a conﬁguration where the desired gate, speciﬁed in the idealized circuit, can be applied.
Revised: To compensate for the nearest-neighbor limitation, swap gates can move qubit states between connected qubits to reach a conﬁguration where the desired gate, speciﬁed in the idealized circuit, can be applied.

Original: Current quantum computational hardware suffers greatly from decoherence (akin to noise), which degrades the ﬁdelity of the computation (Bishop 2017).
Revised: Current quantum computational hardware suffers greatly from decoherence (akin to noise), which degrades the ﬁdelity of the computation (Bishop 2017).

Original: In NISQ processors, decoherence is intimately linked to the duration of the executed circuit that carries out the quantum computation, so it is
Revised: In NISQ processors, decoherence is intimately linked to the duration of the executed circuit that carries out the quantum computation, so it is

Original: [Figure]
Revised: [Figure]

Original: q1q2q3q
Revised: q1q2q3q

Original: [Figure]
Revised: [Figure]

Original: connected architecture can be executed if they do not in- can only be swap route connected gates critical to minimize the duration of compiled circuits.
Revised: connected architecture can be executed if they do not in- can only be swap route connected gates critical to minimize the duration of compiled circuits.

Original: Thus, compilation is challenging due to: the parallel execution of gates with different durations, the planar or quasi-planar topology of the qubit locations on the chip, the ordering constraints from the original idealized circuit, as well as additional constraints such as cross-talk.
Revised: Thus, compilation is challenging due to: the parallel execution of gates with different durations, the planar or quasi-planar topology of the qubit locations on the chip, the ordering constraints from the original idealized circuit, as well as additional constraints such as cross-talk.

Original: Example: Figure 1 shows a concrete QCC example requiring gate operations g A
Revised: Example: Figure 1 shows a concrete QCC example requiring gate operations g A

Original: =
Revised: =

Original: G ( q 1 , q 2 ) and g B = G ( q 3 , q 8 ) .
Revised: G ( q 1 , q 2 ) and g B = G ( q 3 , q 8 ) .

Original: At the top, the algorithm is speciﬁed, as is typically done in the gate-model quantum computing literature, as an idealized quantum circuit, with sequential speciﬁcations of 2-qubit gates over qubit states.
Revised: At the top, the algorithm is speciﬁed, as is typically done in the gate-model quantum computing literature, as an idealized quantum circuit, with sequential speciﬁcations of 2-qubit gates over qubit states.

Original: There are no hardware constraints; further, some ordered pairs of gates in the idealized circuit may commute (i.e., could execute in arbitrary order, even simultaneously, and still produce correct results).
Revised: There are no hardware constraints; further, some ordered pairs of gates in the idealized circuit may commute (i.e., could execute in arbitrary order, even simultaneously, and still produce correct results).

Original: A fullyconnected quantum hardware, with no hardware constraints except that two gates involving the same qubit cannot be carried out at the same time, is represented in the middle as a connecting all possible
Revised: A fullyconnected quantum hardware, with no hardware constraints except that two gates involving the same qubit cannot be carried out at the same time, is represented in the middle as a connecting all possible

Original: A
Revised: A

Original: For instance, the gates acting respectively on qubit states qand q 2 and on q 3 and q 8 can be executed, even concurrently, when these states are located at pairs qubits connected in the chip.
Revised: For instance, the gates acting respectively on qubit states qand q 2 and on q 3 and q 8 can be executed, even concurrently, when these states are located at pairs qubits connected in the chip.

Original: Furthermore, on the actual chip, gate execution durations may differ depending on the actual location they are executed, indicated by red or blue edges in the chip (bottom).
Revised: Furthermore, on the actual chip, gate execution durations may differ depending on the actual location they are executed, indicated by red or blue edges in the chip (bottom).

Original: Cross-talk constraints preclude operations on qubits that are physically located nearby an activated gate.
Revised: Cross-talk constraints preclude operations on qubits that are physically located nearby an activated gate.

Original: A 2-qubit gate operating on the quantum state residing on qubit n 1 and nwill prevent any other gate operating concurrently on n 3 or n 8 ; this is shown by the yellow Xs (bottom).
Revised: A 2-qubit gate operating on the quantum state residing on qubit n 1 and nwill prevent any other gate operating concurrently on n 3 or n 8 ; this is shown by the yellow Xs (bottom).

Original: In this example, we assume the initial assignment of quantum states to qubits allocates q i to qubit n i , shown as a dashed line.
Revised: In this example, we assume the initial assignment of quantum states to qubits allocates q i to qubit n i , shown as a dashed line.

Original: We see that g A can be applied immediately, but g B involves two qubit states that are not mapped to nearest neighbors.
Revised: We see that g A can be applied immediately, but g B involves two qubit states that are not mapped to nearest neighbors.

Original: One solution is for the QCC software to add additional “swap” gates.
Revised: One solution is for the QCC software to add additional “swap” gates.

Original: For instance, swap ( n 1 , n 8 ) and concurrently swap ( n 2 , n 3 ) , shown in bold (bottom), will bring the states q 3 and q 8 to qubits where g B can be applied.
Revised: For instance, swap ( n 1 , n 8 ) and concurrently swap ( n 2 , n 3 ) , shown in bold (bottom), will bring the states q 3 and q 8 to qubits where g B can be applied.

Original: This highlights that
Revised: This highlights that

Original: the
Revised: the

Original: QCC procedure can also determine the initial assignment task (i.e., decide the initial qubit location for each qubit state on the idealized hardware) to optimize the gate schedule.
Revised: QCC procedure can also determine the initial assignment task (i.e., decide the initial qubit location for each qubit state on the idealized hardware) to optimize the gate schedule.

Original: For example, the QCC solver could decide to initialize q 3 and qon two adjacent qubits on the actual hardware chip, avoiding all swaps for executing the idealized circuit in question.
Revised: For example, the QCC solver could decide to initialize q 3 and qon two adjacent qubits on the actual hardware chip, avoiding all swaps for executing the idealized circuit in question.

Original: To summarize, to compile from the idealized quantum circuit illustrated at the top of Figure 1 consisting of two gates {G ( q 1 , q 2 ) , G ( q 3 , q 8 ) } and no hardware constraints, into the sequence of (parallel) gates that can be executed in the actual NISQ hardware chip at the bottom of Figure 1, the QCC solver will: (1) ﬁrst ﬁnd the initial locations for the four qubit states q 1 , q 2 , q 3 , and q 8 on the NISQ chip; then (2) add auxiliary swap gates to bring the two pairs ( q 1 , q 2 ) and ( q 3 , q 8 ) to adjacent physical qubits that are connected and execute the required operations; and (3) schedule all the gates, each with possibly different duration, to execute in parallel in the shortest amount of time, while obeying all hardware constraints such as cross-talks constraints.
Revised: To summarize, to compile from the idealized quantum circuit illustrated at the top of Figure 1 consisting of two gates {G ( q 1 , q 2 ) , G ( q 3 , q 8 ) } and no hardware constraints, into the sequence of (parallel) gates that can be executed in the actual NISQ hardware chip at the bottom of Figure 1, the QCC solver will: (1) ﬁrst ﬁnd the initial locations for the four qubit states q 1 , q 2 , q 3 , and q 8 on the NISQ chip; then (2) add auxiliary swap gates to bring the two pairs ( q 1 , q 2 ) and ( q 3 , q 8 ) to adjacent physical qubits that are connected and execute the required operations; and (3) schedule all the gates, each with possibly different duration, to execute in parallel in the shortest amount of time, while obeying all hardware constraints such as cross-talk constraints.

Original: Existing Work on QCC: Since the development of NISQ superconducting processors, there has been development of software libraries to synthesize and compile quantum circuits from algorithm speciﬁcations (Wecker and Svore 2014;
Revised: Existing Work on QCC: Since the development of NISQ superconducting processors, there has been development of software libraries to synthesize and compile quantum circuits from algorithm speciﬁcations (Wecker and Svore 2014;

Original: Smith, Curtis, and Zeng 2016; Steiger, H¨aner, and Troyer 2018; Barends and others 2016), including work explicitly addressing theoretical bounds on the overhead introduced by swap gates (Beals and others 2013; Brierley 2017; Bremner,
Revised: Smith, Curtis, and Zeng 2016; Steiger, H¨aner, and Troyer 2018; Barends and others 2016), including work explicitly addressing theoretical bounds on the overhead introduced by swap gates (Beals and others 2013; Brierley 2017; Bremner,

Original: Montanaro, and Shepherd 2017).
Revised: Montanaro, and Shepherd 2017).

Original: Recently, it was proven that the QCC problem and its common variants are NPComplete (Botea, Kishimoto, and Marinescu 2018).
Revised: Recently, it was proven that the QCC problem and its common variants are NPComplete (Botea, Kishimoto, and Marinescu 2018).

Original: (Bhattacharjee and Chattopadhyay 2017) investigated approaches with off-the-shelf MILP solvers, such as Gurobi, for solving QCC.
Revised: (Bhattacharjee and Chattopadhyay 2017) investigated approaches with off-the-shelf MILP solvers, such as Gurobi, for solving QCC.

Original: (Guerreschi and Park 2018; Zulehner and Wille 2018) developed heuristics that address NISQ constraints while minimizing the number of required swap gates.
Revised: (Guerreschi and Park 2018; Zulehner and Wille 2018) developed heuristics that address NISQ constraints while minimizing the number of required swap gates.

Original: The initial assignment task has been recently addressed in (Paler 2019).
Revised: The initial assignment task has been recently addressed in (Paler 2019).

Original: Policies for compilation in chips with variable performance parameters among different qubits and gates have been studied in (Tannu and Qureshi 2018), as well as in (Murali et al. 2019).
Revised: Policies for compilation in chips with variable performance parameters among different qubits and gates have been studied in (Tannu and Qureshi 2018), as well as in (Murali et al. 2019).

Original: In (Oddi and Rasconi 2018;
Revised: In (Oddi and Rasconi 2018;

Original: Rasconi and
Revised: Rasconi and

Original: Oddi 2019), the authors present heuristics (greedy randomized search, and genetic algorithms) speciﬁcally designed to solve the QCC Max-Cut benchmark set that was introduced in (Venturelli et al. 2018).
Revised: Oddi 2019), the authors present heuristics (greedy randomized search, and genetic algorithms) speciﬁcally designed to solve the QCC Max-Cut benchmark set that was introduced in (Venturelli et al. 2018).

Original: In (Booth et al. 2018), CP is explored as an alternative and complementary approach to the temporal planning methods introduced in (Venturelli et al.
Revised: In (Booth et al. 2018), CP is explored as an alternative and complementary approach to the temporal planning methods introduced in (Venturelli et al.

Original: Other methods are proposed in (Li, Ding, and Xie 2018) and in (Childs, Schoute, and Unsal 2019), where the crosstalk-free compilation of circuits is handled heuristically on benchmarks for the IBM chip.
Revised: Other methods are proposed in (Li, Ding, and Xie 2018) and in (Childs, Schoute, and Unsal 2019), where the crosstalk-free compilation of circuits is handled heuristically on benchmarks for the IBM chip.

Original: In (Khatri et al. 2018), an approach based on iteratively learning a sequence of native gate implementing a target unitary is introduced, solving the problem of compilation with that of gate-synthesis at the same time, for small shallow circuits.
Revised: In (Khatri et al. 2018), an approach based on iteratively learning a sequence of native gate implementing a target unitary is introduced, solving the problem of compilation with that of gate-synthesis at the same time, for small shallow circuits.

Original: Another recent learning approach in (Jones and Benjamin 2018) converts the approximate compilation problem into an auxiliary quantum variational algorithm native on the hardware.
Revised: Another recent learning approach in (Jones and Benjamin 2018) converts the approximate compilation problem into an auxiliary quantum variational algorithm native on the hardware.

Original: In (Nash, Gheorghiu, and Michele 2019) and (Kissinger and Meijer-van de
Revised: In (Nash, Gheorghiu, and Michele 2019) and (Kissinger and Meijer-van de

Original: Griend 2019)
Revised: Griend 2019)

Original: the QCC problem is solved heuristically for circuits consisting of CNOT gates only.
Revised: the QCC problem is solved heuristically for circuits consisting of CNOT gates only.

Original:  Automated Reasoning for QCC-NISQ
Revised:  Automated Reasoning for QCC-NISQ

Original: Our approach to solve the QCC-NISQ problem is to deploy a general-purpose software suite that leverages model-based approaches, including temporal planning and constraint programming (CP) for the solution of the actual combinatorial problem.
Revised: Our approach to solve the QCC-NISQ problem is to deploy a general-purpose software suite that leverages model-based approaches, including temporal planning and constraint programming (CP) for the solution of the actual combinatorial problem.

Original: Since quantum computing is still a relatively new paradigm, different quantum hardware architectures and algorithms running on them are introduced and revised frequently, with no current clear winner.
Revised: Since quantum computing is still a relatively new paradigm, different quantum hardware architectures and algorithms running on them are introduced and revised frequently, with no current clear winner.

Original: Therefore, instead of a machine-speciﬁc QCC tool, there is a tremendous beneﬁt in developing a general-purpose QCC software suite that is capable of addressing different hardware architectures, different quantum algorithms running on them, and different optimization problems that can be solved by those algorithms.
Revised: Therefore, instead of a machine-speciﬁc QCC tool, there is a tremendous beneﬁt in developing a general-purpose QCC software suite that is capable of addressing different hardware architectures, different quantum algorithms running on them, and different optimization problems that can be solved by those algorithms.

Original: Furthermore, our approach is a very attractive option because: (1) declarative model adjustment (e.g., through a declarative planning model) can adapt quickly to revised hardware designs and constraints, and can also cover a wide range of hardware architectures; (2) existing hardware from various companies are still limited in size, thus even general-purpose algorithms can quickly ﬁnd good, sometimes proven optimal, solutions.
Revised: Furthermore, our approach is a very attractive option because: (1) declarative model adjustment (e.g., through a declarative planning model) can adapt quickly to revised hardware designs and constraints, and can also cover a wide range of hardware architectures; (2) existing hardware from various companies are still limited in size, thus even general-purpose algorithms can quickly ﬁnd good, sometimes proven optimal, solutions.

Original: Why AI Planning?
Revised: Why AI Planning?

Original: In planning, a planner searches for a set of actions that can be executed in sequence to achieve the pre-deﬁned set of goals, while satisfying all domain constraints.
Revised: In planning, a planner searches for a set of actions that can be executed in sequence to achieve the pre-deﬁned set of goals, while satisfying all domain constraints.

Original: In model-based temporal planning, speciﬁcally
Revised: In model-based temporal planning, speciﬁcally

Original: PDDL-based planning
Revised: PDDL-based planning

Original: , actions can have different durations and can be executed in parallel.
Revised: , actions can have different durations and can be executed in parallel.

Original: We choose planning to be the center piece of the QCC solver suite because:
Revised: We choose planning to be the center piece of the QCC solver suite because:

Original: • The action model and plan constraints in PDDL planning can be used to describe gate operation naturally, capturing chip layout, gate duration, and domain constraints such as “cross-talk”.
Revised: • The action model and plan constraints in PDDL planning can be used to describe gate operation naturally, capturing chip layout, gate duration, and domain constraints such as “cross-talk”.

Original: This ﬂexibility lets us model various chips from all of the groups mentioned above developing NISQ chips.
Revised: This ﬂexibility lets us model various chips from all of the groups mentioned above developing NISQ chips.

Original: • Any new adjustment or hardware updates from the manufacturer can also be reﬂected easily in planning model updates, without extensive writing of new software.
Revised: • Any new adjustment or hardware updates from the manufacturer can also be reﬂected easily in planning model updates, without extensive writing of new software.

Original: • The default objective function of optimizing makespan for most temporal planners ﬁts well with quantum decoherence (discussed in the previous section).
Revised: • The default objective function of optimizing makespan for most temporal planners ﬁts well with quantum decoherence (discussed in the previous section).

Original: • There are multiple off-the-shelf open-sourced PDDL temporal planners that have been tested through multiple International Planning Competitions (IPC), providing a rich set of algorithms, ranging from exact to anytime, to test on the NISQ-QCC problem.
Revised: • There are multiple off-the-shelf open-sourced PDDL temporal planners that have been tested through multiple International Planning Competitions (IPC), providing a rich set of algorithms, ranging from exact to anytime, to test on the NISQ-QCC problem.

Original: For more details on the AI planning approach to NISQQCC, see (Venturelli et al. 2018).
Revised: For more details on the AI planning approach to NISQQCC, see (Venturelli et al. 2018).

Original: Why
Revised: Why

Original: Constraint Programming?
Revised: Constraint Programming?

Original: Constraint Programming (CP) is a paradigm for modeling and solving combinatorial optimization problems, leveraging a diverse set of techniques from ﬁelds including operations research and artiﬁcial intelligence (Rossi, Van Beek, and Walsh 2006).
Revised: Constraint Programming (CP) is a paradigm for modeling and solving combinatorial optimization problems, leveraging a diverse set of techniques from ﬁelds including operations research and artiﬁcial intelligence (Rossi, Van Beek, and Walsh 2006).

Original: CP is more general than other discrete optimization paradigms, such as integer programming, as it allows variable types beyond integer and continuous (e.g., interval and set variables), and drops the linearity on the constraints and objective function.
Revised: CP is more general than other discrete optimization paradigms, such as integer programming, as it allows variable types beyond integer and continuous (e.g., interval and set variables), and drops the linearity on the constraints and objective function.

Original: CP complements PDDL-based planning for the QCC software suite for a number of reasons, including:
Revised: CP complements PDDL-based planning for the QCC software suite for a number of reasons, including:

Original: • The scheduling characteristics of QCC (i.e., gate durations, precedence constraints, makespan minimization, and unary qubit capacity) are readily modeled within modern CP solver software.
Revised: • The scheduling characteristics of QCC (i.e., gate durations, precedence constraints, makespan minimization, and unary qubit capacity) are readily modeled within modern CP solver software.

Original: • Solutions found by PDDL-based planning or a heuristic method can be used as a starting point for the CP search, leading to subsequently better solutions.
Revised: • Solutions found by PDDL-based planning or a heuristic method can be used as a starting point for the CP search, leading to subsequently better solutions.

Original: • The CP search is an exact algorithm, ensuring that, given enough runtime, the optimal quantum circuit compilation will be found.
Revised: • The CP search is an exact algorithm, ensuring that, given enough runtime, the optimal quantum circuit compilation will be found.

Original: Additionally, modern CP solvers provide anytime bounds on solution quality
Revised: Additionally, modern CP solvers provide anytime bounds on solution quality

Original: in the form of an optimality gap.
Revised: in the form of an optimality gap.

Original: For more details on the CP approach to optimize circuits together with planners, see (Booth et al. 2018).
Revised: For more details on the CP approach to optimize circuits together with planners, see (Booth et al. 2018).

Original:  System Architecture
Revised:  System Architecture

Original: The objective of the whole framework is to provide to quantum computing researchers the ability to efﬁciently deploy executables of speciﬁc quantum algorithms by keeping control over the tradeoffs imposed by the different choices related to what strategy to adopt to solve the QCC-NISQ problem.
Revised: The objective of the whole framework is to provide to quantum computing researchers the ability to efﬁciently deploy executables of speciﬁc quantum algorithms by keeping control over the tradeoffs imposed by the different choices related to what strategy to adopt to solve the QCC-NISQ problem.

Original: While the key component of our suite is the QCC solver that does the compilation, multiple additional tools complement the software suite.
Revised: While the key component of our suite is the QCC solver that does the compilation, multiple additional tools complement the software suite.

Original: [Figure]
Revised: [Figure]

Original: Figure 2 shows the architecture of our software suite, with the initial inputs provided by the users consisting of two main components: the problem instance containing details on the problem for which we attempt to solve using a quantum algorithm, and the machine conﬁguration specifying the details of the gate-model quantum chip (e.g., physical layout, gate durations, constraints).
Revised: Figure 2 shows the architecture of our software suite, with the initial inputs provided by the users consisting of two main components: the problem instance containing details on the problem for which we attempt to solve using a quantum algorithm, and the machine conﬁguration specifying the details of the gate-model quantum chip (e.g., physical layout, gate durations, constraints).

Original: (A third input, the algorithm parameters , concerns the setting of the classical parameters of the gates once they are already compiled, and will be discussed in connection with the generation of the executable.)
Revised: (A third input, the algorithm parameters , concerns the setting of the classical parameters of the gates once they are already compiled, and will be discussed in connection with the generation of the executable.)

Original: These inputs are provided to the Synthesizer that generates three different outputs (described in later sections), that can be fed into two other components: the QCC Solver and the Machine Code Generator (MCG) .
Revised: These inputs are provided to the Synthesizer that generates three different outputs (described in later sections), that can be fed into two other components: the QCC Solver and the Machine Code Generator (MCG) .

Original: The QCC Solver generates planning problems in the standard Planning Domain Deﬁnition Language (PDDL) and generates plans in the standard IPC format, which can then be parsed in a circuit plan representation or fed into the CP solver (the ” optimizer ”) to generate a better quality solution.
Revised: The QCC Solver generates planning problems in the standard Planning Domain Deﬁnition Language (PDDL) and generates plans in the standard IPC format, which can then be parsed in a circuit plan representation or fed into the CP solver (the ” optimizer ”) to generate a better quality solution.

Original: The last two components are: the Visualizer , which can show graphically the machine logical layout, the high-level problem speciﬁcations, and the QCC solutions; and the
Revised: The last two components are: the Visualizer , which can show graphically the machine logical layout, the high-level problem speciﬁcations, and the QCC solutions; and the

Original: Machine Code Generator , which maps the QCC solution and information on how to synthesize gates onto a particular hardware architecture to produce the machine-speciﬁc executable ﬁle (e.g. a python script) that can submit a job on the cloud to a quantum NISQ device through its public API.
Revised: Machine Code Generator , which maps the QCC solution and information on how to synthesize gates onto a particular hardware architecture to produce the machine-speciﬁc executable ﬁle (e.g. a python script) that can submit a job on the cloud to a quantum NISQ device through its public API.

Original: In the rest of this section, we will describe in more detail the different components and their inputs and outputs.
Revised: In the rest of this section, we will describe in more detail the different components and their inputs and outputs.

Original: (Circuit) Synthesizer (CS): the CS is in charge of two main tasks: (1) generate the low-level gate synthesis ( gate decom- positions ) to act as one input to the MCG; and (2) generate the inputs for the QCC Solver ( circuit DAG and abstract device ).
Revised: (Circuit) Synthesizer (CS): the CS is in charge of two main tasks: (1) generate the low-level gate synthesis ( gate decom- positions ) to act as one input to the MCG; and (2) generate the inputs for the QCC Solver ( circuit DAG and abstract device ).

Original: The ﬁrst task is meant to decompose the abstract gates, which appear in the idealized circuit of the quantum algorithm, into elementary gates supported by the hardware, whose duration in nanoseconds is known at all possible locations in the chip.
Revised: The ﬁrst task is meant to decompose the abstract gates, which appear in the idealized circuit of the quantum algorithm, into elementary gates supported by the hardware, whose duration in nanoseconds is known at all possible locations in the chip.

Original: This decomposition is known as the gatesynthesis problem.
Revised: This decomposition is known as the gatesynthesis problem.

Original: It is non-trivial in the general case, but for many quantum algorithms and for standard universal elementary gate sets, optimal decompositions are known.
Revised: It is non-trivial in the general case, but for many quantum algorithms and for standard universal elementary gate sets, optimal decompositions are known.

Original: Currently, the CS implementation just consists of a lookup library of known decompositions into elementary gates 1 .
Revised: Currently, the CS implementation just consists of a lookup library of known decompositions into elementary gates 1 .

Original: This decomposition library has been found by various methods, including proven optimal results (Vatan and Williams 2004).
Revised: This decomposition library has been found by various methods, including proven optimal results (Vatan and Williams 2004).

Original: The CS assigns a total duration (in standardized clock units) to each possible logical gate, to inform the second component of the module that will have to generate the input ﬁles to the QCC solver.
Revised: The CS assigns a total duration (in standardized clock units) to each possible logical gate, to inform the second component of the module that will have to generate the input ﬁles to the QCC solver.

Original: The second task is to instantiate an abstract device software object, which is representing the topology of the hardware but is aware only of the different types of gates that need to be scheduled (including swaps), which are represented as edges, and their duration obtained through synthesis (the edge weight).
Revised: The second task is to instantiate an abstract device software object, which is representing the topology of the hardware but is aware only of the different types of gates that need to be scheduled (including swaps), which are represented as edges, and their duration obtained through synthesis (the edge weight).

Original: The abstract device includes information about crosstalks/simultaneity constraints in the form of an extra graph whose vertices are the edges of the hardware graph and whose edges indicate impossibility of concurrent gate operations using the corresponding edges of the hardware graph.
Revised: The abstract device includes information about crosstalks/simultaneity constraints in the form of an extra graph whose vertices are the edges of the hardware graph and whose edges indicate impossibility of concurrent gate operations using the corresponding edges of the hardware graph.

Original: Fig.
Revised: Fig.

Original: 1 (bottom) is a pictorial representation of some informations contained in the abstract device .
Revised: 1 (bottom) is a pictorial representation of some informations contained in the abstract device .

Revised: While the properties described in the Abstract Device instance are tailored to the QCC solver capabilities, the device class should be used by different solvers.

Revised: For instance, if a non-temporal method is used as a solver instead of temporal planning, the gate durations could be discarded.

Original: Finally, the CS composes a Directed Acyclic Graph (Circuit DAG ) representation of the problem instance, which takes care of deﬁning the partial ordering rules of the gates composing the circuit.
Revised: Finally, the CS composes a Directed Acyclic Graph (Circuit DAG ) representation of the problem instance, which takes care of deﬁning the partial ordering rules of the gates composing the circuit.

Original: The vertices of the DAG correspond to gates on speciﬁed qubits and the arcs correspond to precedence constraints; operations that are incomparable by this relation can be scheduled in any order relative to each other.
Revised: The vertices of the DAG correspond to gates on speciﬁed qubits and the arcs correspond to precedence constraints; operations that are incomparable by this relation can be scheduled in any order relative to each other.

Original: This freedom arises naturally in quantum computation for quantum gates that “commute” with each other, i.e., produce the same effect regardless of the order in which they are applied.
Revised: This freedom arises naturally in quantum computation for quantum gates that “commute” with each other, i.e., produce the same effect regardless of the order in which they are applied.

Original: But can also be used in the context of heuristic algorithms that try to balance the effectiveness of the logical circuit and cost of implementing it as a physical circuit.
Revised: But can also be used in the context of heuristic algorithms that try to balance the effectiveness of the logical circuit and cost of implementing it as a physical circuit.

Original: The DAG includes only the synthesized two-qubit gates that are necessary for the logical description of the algorithm.
Revised: The DAG includes only the synthesized two-qubit gates that are necessary for the logical description of the algorithm.

Original: QCC Solver: The QCC solver takes the SC input and produces internally the PDDL ﬁles that represent the planning instances .
Revised: QCC Solver: The QCC solver takes the SC input and produces internally the PDDL ﬁles that represent the planning instances .

Original: The ultimate objective of this module is to output the circuit plan , which is the compiled representation of the target algorithm.
Revised: The ultimate objective of this module is to output the circuit plan , which is the compiled representation of the target algorithm.

Original: The following options are currently implemented:
Revised: The following options are currently implemented:

Original: • With/without cross-talk constraints: specifying whether or not the underlying hardware has cross-talk constraints
Revised: • With/without cross-talk constraints: specifying whether or not the underlying hardware has cross-talk constraints

Original: between adjacent qubits; see Figure 1 (bottom).
Revised: between adjacent qubits; see Figure 1 (bottom)

Original: • With/without qubit initialization: specifying whether or not the QCC Solver should decide (as part of the planning objective) the mapping of speciﬁc qubits to quantum states at the beginning of the algorithm; see Figure(dashed line, middle-bottom).
Revised: • With/without qubit initialization: specifying whether or not the QCC Solver should decide (as part of the planning objective) the mapping of speciﬁc qubits to quantum states at the beginning of the algorithm; see Figure(dashed line, middle-bottom).

Original: • Single or multiple phases: specifying if the idealized circuit should be executed multiple times in sequence (see Section 2).
Revised: • Single or multiple phases: specifying if the idealized circuit should be executed multiple times in sequence (see Section 2).

Original: This is particularly important for QAOA circuits, which require insertion of alternating “phaseseparation” and “mixing” sets of gates to increase the accuracy of the solution returned by the algorithm.
Revised: This is particularly important for QAOA circuits, which require insertion of alternating “phaseseparation” and “mixing” sets of gates to increase the accuracy of the solution returned by the algorithm.

Original: Requirements on running multiple phases will lead to CS generating PDDL ﬁles with different sets of actions and goals.The planning instance is
Revised: Requirements on running multiple phases will lead to CS generating PDDL ﬁles with different sets of actions and goals.

Original:  processed by a Planner to obtain a temporal plan, which is a sequence of gates to be executed on the designated hardware architecture.
Revised: The planning instance is processed by a Planner to obtain a temporal plan, which is a sequence of gates to be executed on the designated hardware architecture.

Original: Speciﬁcally, at the moment we use two different macro-approaches to generate the ﬁnal plan 2 : • Use off-the-shelf temporal planners that can take the standard PDDL input.
Revised: Speciﬁcally, at the moment we use two different macro-approaches to generate the ﬁnal plan 2 : • Use off-the-shelf temporal planners that can take the standard PDDL input.

Original: The following planners have been used: LPG, TFD, POPF, CPT, and SGPlan; all previous winners at different IPC.
Revised: The following planners have been used: LPG, TFD, POPF, CPT, and SGPlan; all previous winners at different IPC.

Original: The performance of different individual planners is reported on in (Venturelli et al. 2018).
Revised: The performance of different individual planners is reported on in (Venturelli et al. 2018).

Original: • Use a combination of planning and CP in a hybrid setting where plans found by any temporal planner can then be used to warm-start (i.e., seed) the CP model that in turn is solved by the commercial software CP Optimizer to ﬁnd a new, better quality plan.
Revised: • Use a combination of planning and CP in a hybrid setting where plans found by any temporal planner can then be used to warm-start (i e., seed) the CP model that in turn is solved by the commercial software CP Optimizer to ﬁnd a new, better quality plan.

Original: The evaluation of this approach is described in (Booth et al.2018) 3 . Results on the use
Revised: The evaluation of this approach is described in (Booth et al.

Original:  of the QCC solver with the various variants for MaxCut QAOA are presented in (Venturelli et al. 2018) and (Booth et al. 2018).
Revised: Results on the use of the QCC solver with the various variants for MaxCut QAOA are presented in (Venturelli et al. 2018) and (Booth et al. 2018).

Original: The QCC solvers have been also conﬁgured for tests on Graph Coloring, which are currently being performed.
Revised: The QCC solvers have been also conﬁgured for tests on Graph Coloring, which are currently being performed.

Revised: The versatility of our approach utilizing off-the-shelf domain-independent PDDL temporal planners is reﬂected in the ability to quickly test machine models from different companies (Rigetti, Google, IBM) at different scales and diffferent chip layouts, for different set of gate operations, gate durations, and gate constraints.

Original: Figure 3 shows the visualizer displaying a single phase of QAOA to solve a Maxcut problem (referred to below as
Revised: Figure 3 shows the visualizer displaying a single phase of QAOA to solve a Maxcut problem (referred to below as

Original: Maxcut-QAOA) on the Google Bristlecone chip.
Revised: Maxcut-QAOA) on the Google Bristlecone chip.

Original: The ﬁgure shows the following components:
Revised: The ﬁgure shows the following components:

Original: • Goal Graph: at the top-left corner, the goal graph shows the gates to be scheduled (colored edges) according to the idealized quantum circuit.
Revised: • Goal Graph: at the top-left corner, the goal graph shows the gates to be scheduled (colored edges) according to the idealized quantum circuit.

Original: For Maxcut-QAOA, the goal graph is identical to the actual graph that we want to cut.
Revised: For Maxcut-QAOA, the goal graph is identical to the actual graph that we want to cut.

Original: The goal graph contains essentially information related to the circuit DAG (Fig. 2).
Revised: The goal graph contains essentially information related to the circuit DAG (Fig. 2).

Original: • Machine Graph: at the top-right corner, the machine graph represents the underlying logical layout of the NISQ processor target (in this case, a portion of Google’s Bristlecone chip).
Revised: • Machine Graph: at the top-right corner, the machine graph represents the underlying logical layout of the NISQ processor target (in this case, a portion of Google’s Bristlecone chip).

Original: Multiple connections between a given pair of qubits represent different types of gates that can be applied to the nearest-neighbor connected qubits.
Revised: Multiple connections between a given pair of qubits represent different types of gates that can be applied to the nearest-neighbor connected qubits.

Original: Each type of gate has a different duration.
Revised: Each type of gate has a different duration.

Original: The machine graph contains essentially information related to the abstract device (Fig. 2).
Revised: The machine graph contains essentially information related to the abstract device (Fig. 2).

Original: • QCC plan: this shows the temporal schedule of gate operations as a Gantt chart, each with its starting time, duration, and the qubits involved in that particular gate operation.
Revised: • QCC plan: this shows the temporal schedule of gate operations as a Gantt chart, each with its starting time, duration, and the qubits involved in that particular gate operation.

Original: The gates are color coded to match the high-level goals (see the matching edge color on the Goal Graph described above).
Revised: The gates are color coded to match the high-level goals (see the matching edge color on the Goal Graph described above).

Original: Sliding over the timeline of this Ganttchart representation will also highlight on the machine graph the qubit set and the active gates operating on that set, at the timepoint selected on the timeline of the plan. 
Revised: Sliding over the timeline of this Ganttchart representation will also highlight on the machine graph the qubit set and the active gates operating on that set, at the timepoint selected on the timeline of the plan. For

Original: For reference, in Figure 3, the slider has been set on time slot number 5.
Revised: reference, in Figure 3, the slider has been set on time slot number 5.

Original: The QCC plan contains essentially the same information related to the circuit plan (Fig. 2).
Revised: The QCC plan contains essentially the same information related to the circuit plan (Fig. 2).

Original: For the case of graph coloring, the QAOA algorithm logical gates require multiple kind of two qubit gates, as explained in (Hadﬁeld et al. 2019).
Revised: For the case of graph coloring, the QAOA algorithm logical gates require multiple kind of two qubit gates, as explained in (Hadﬁeld et al. 2019).

Original: A more advanced visualizer that is able to show the various steps by using different colors, graphic notations and animations is under development.
Revised: A more advanced visualizer that is able to show the various steps by using different colors, graphic notations and animations is under development.

Original: Machine Code Generator (MCG): this component outputs the machine instructions that perform the compiled algorithm on the target quantum processor or in a simulator (the Executable circuit ).
Revised: Machine Code Generator (MCG): this component outputs the machine instructions that perform the compiled algorithm on the target quantum processor or in a simulator (the Executable circuit ).

Original: The MCG integrates the abstract
Revised: The MCG integrates the abstract

Original: QCC solution (the circuit plan ) with the gate synthesis instructions generated by the CS, and sets the parameters that are required for the execution of the algorithm, which are given as inputs ( Algorithm parameters ).
Revised: QCC solution (the circuit plan ) with the gate synthesis instructions generated by the CS, and sets the parameters that are required for the execution of the algorithm, which are given as inputs ( Algorithm parameters ).

Original: More speciﬁcally, it unwinds the duration abstraction of the gates that has been scheduled and replaces the composite gate with the code that activates the exact sequence of native gates on the chip with the correct parameters.
Revised: More speciﬁcally, it unwinds the duration abstraction of the gates that has been scheduled and replaces the composite gate with the code that activates the exact sequence of native gates on the chip with the correct parameters.

Original: For instance, for the case of QAOA, these includes the angles for the alternating unitary transformations that compose the algorithm.
Revised: For instance, for the case of QAOA, these includes the angles for the alternating unitary transformations that compose the algorithm.

Original: The algorithm speciﬁcations not only set the individual gate parameters, but also many control-loop policies for hybrid classical-quantum computation.
Revised: The algorithm speciﬁcations not only set the individual gate parameters, but also many control-loop policies for hybrid classical-quantum computation.

Original: Examples include the measurement and accuracy evaluation functions that determine whether the algorithm needs to be iterated one more time with different parameters after execution.
Revised: Examples include the measurement and accuracy evaluation functions that determine whether the algorithm needs to be iterated one more time with different parameters after execution.

Original: Current deployment and implementation details: The software suite we describe ultimately will be integrated with the general software framework for programming quantum processors QuaSar (NASA’s Quantum user-assisting Software for applied research .
Revised: Current deployment and implementation details: The software suite we describe ultimately will be integrated with the general software framework for programming quantum processors QuaSar (NASA’s Quantum user-assisting Software for applied research .

Original: QuaSar is a high-level backend and frontend system, soon to be released, which support transparent inter-operability between code written for most quantum computers that released APIs, including Cirq,
Revised: QuaSar is a high-level backend and frontend system, soon to be released, which support transparent inter-operability between code written for most quantum computers that released APIs, including Cirq,

Original: Rigetti Computing PyQuil as well as QASM 2.0.
Revised: Rigetti Computing PyQuil as well as QASM 2.0.

Original: The current implementation of the CS, and of the
Revised: The current implementation of the CS, and of the

Original: QCC Solver is in Cirq (Google AI 2018) 4 , an opensource framework that conveniently abstracts several aspects of temporal manipulation of operations in quantum circuits.
Revised: QCC Solver is in Cirq (Google AI 2018) 4 , an opensource framework that conveniently abstracts several aspects of temporal manipulation of operations in quantum circuits.

Original: This excludes the actual implementation of the planner and the CP optimizer, that varies case by case (they are considered external black boxes to be interfaced).
Revised: This excludes the actual implementation of the planner and the CP optimizer, that varies case by case (they are considered external black boxes to be interfaced).

Original: The output of the MCG is a Cirq schedule object; such an object can be run directly on Google’s hardware or converted by QuaSar to the common quantum circuit format QASM for compatibility with other hardware providers.
Revised: The output of the MCG is a Cirq schedule object; such an object can be run directly on Google’s hardware or converted by QuaSar to the common quantum circuit format QASM for compatibility with other hardware providers.

Original: Relation to existing work on software frameworks: as reviewed in (LaRose 2019), most quantum computing companies have released software frameworks that allow endto-end deployment of quantum algorithms.
Revised: Relation to existing work on software frameworks: as reviewed in (LaRose 2019), most quantum computing companies have released software frameworks that allow endto-end deployment of quantum algorithms.

Original: These packages could be as simple as generic wrappers around machine instruction languages, or include suites for handling speciﬁc aspects.
Revised: These packages could be as simple as generic wrappers around machine instruction languages, or include suites for handling speciﬁc aspects.

Original: For instance, Xanadu’s PennyLane focuses on facilitating aspects of development of (quantum) machine learning algorithms (Bergholm et al.
Revised: For instance, Xanadu’s PennyLane focuses on facilitating aspects of development of (quantum) machine learning algorithms (Bergholm et al.

Original: 2018), Microsoft’s Quantum
Revised: 2018), Microsoft’s Quantum

Original: Development Kit (Svore et al.
Revised: Development Kit (Svore et al.

Original: ) focuses on resource estimation for fault-tolerant quantum computers, and Zapata’s algo2qpu (Sim et al. 2018) focuses attention on the hybridization of variational algorithms with classical optimization techniques.
Revised: ) focuses on resource estimation for fault-tolerant quantum computers, and Zapata’s algo2qpu (Sim et al. 2018) focuses attention on the hybridization of variational algorithms with classical optimization techniques.

Original: Our framework focuses on facilitating the optimization of the compilation by allowing the user to use alternative compilation strategies, possibly hybridizing them, and allowing the inspection of the results of the compilation.
Revised: Our framework focuses on facilitating the optimization of the compilation by allowing the user to use alternative compilation strategies, possibly hybridizing them, and allowing the inspection of the results of the compilation.

Original:  Conclusions and Future Work
Revised:  Conclusions and Future Work

Original: We have introduced a framework for applying AI Planning to the QCC-NISQ problem, and developed a software suite that implements components of that framework.
Revised: We have introduced a framework for applying AI Planning to the QCC-NISQ problem, and developed a software suite that implements components of that framework.

Original: The framework and suite are completely general and can be used to target quantum computing hardware devices of different types and by different companies.
Revised: The framework and suite are completely general and can be used to target quantum computing hardware devices of different types and by different companies.

Original: Different planning algorithms, complemented by hybrid algorithms using Constraint Programming, can be used to compile a qunatum circuit to a speciﬁed hardware device.
Revised: Different planning algorithms, complemented by hybrid algorithms using Constraint Programming, can be used to compile a qunatum circuit to a speciﬁed hardware device.

Original: The compiled circuit can be visualized, enabling users to understand how the compilation of the circuit interacts with the constraints of the device.
Revised: The compiled circuit can be visualized, enabling users to understand how the compilation of the circuit interacts with the constraints of the device.

Original: The resulting compiled circuit can then be run on actual hardware, or simulators therof, by different companies.
Revised: The resulting compiled circuit can then be run on actual hardware, or simulators therof, by different companies.

Original: The ﬂexibility of declarative AI planning models allows us to solve the QCC-NISQ problem for these diverse hardware architectures, and to evolve our solutions as the details of the hardware evolve.
Revised: The ﬂexibility of declarative AI planning models allows us to solve the QCC-NISQ problem for these diverse hardware architectures, and to evolve our solutions as the details of the hardware evolve.

Original: The suite integrates several planners (LPG, POPF, TFD,
Revised: The suite integrates several planners (LPG, POPF, TFD,

Original: CPT, and SGPlan), together with IBM’s CP Optimizer suite, the best performing commercial software of its kind.
Revised: CPT, and SGPlan), together with IBM’s CP Optimizer suite, the best performing commercial software of its kind.

Original: We have generated tens of thousands of instances of the QCCNISQ problem based on pairing QAOA for MaxCut on random graphs with quantum computer architectures of varying size and constraints.
Revised: We have generated tens of thousands of instances of the QCCNISQ problem based on pairing QAOA for MaxCut on random graphs with quantum computer architectures of varying size and constraints.

Original: Performance comparisons of different planners and hybrid approaches are reported in (Booth et al.
Revised: Performance comparisons of different planners and hybrid approaches are reported in (Booth et al.

Original: 2018; Venturelli et al.
Revised: 2018; Venturelli et al.

Original: and benchmark instances are available online 5 and have already been used to test other QCC-NISQ solver approaches (e.g. in (Oddi and Rasconi 2018)).
Revised: and benchmark instances are available online 5 and have already been used to test other QCC-NISQ solver approaches (e.g. in (Oddi and Rasconi 2018)).

Original: Future hybrid efforts are under development, including the use of different planners hybridized with LPG, which can take as input a “seed” plan.
Revised: Future hybrid efforts are under development, including the use of different planners hybridized with LPG, which can take as input a “seed” plan.

Original: While CP improves on seed plans, it requires a separate modeling effort; hybridizing multiple planners uses multiple algorithms but requires no additional modeling effort.
Revised: While CP improves on seed plans, it requires a separate modeling effort; hybridizing multiple planners uses multiple algorithms but requires no additional modeling effort.

Original: We claim that a general-purpose software suite built on declarative planning algorithms and constraint programming is a promising approach to addressing the constraints of
Revised: We claim that a general-purpose software suite built on declarative planning algorithms and constraint programming is a promising approach to addressing the constraints of

Original: NISQ devices.
Revised: NISQ devices.

Original: A highly optimized problem-speciﬁc tool may perform better in some cases, but at the cost of significant engineering effort that cannot be reused for new problems.
Revised: A highly optimized problem-speciﬁc tool may perform better in some cases, but at the cost of significant engineering effort that cannot be reused for new problems.

Original: Our model-based, automated reasoning approach is very ﬂexible with respect to features of the hardware graph, including irregular structures, as often arise from manufacturing imperfections.
Revised: Our model-based, automated reasoning approach is very ﬂexible with respect to features of the hardware graph, including irregular structures, as often arise from manufacturing imperfections.

Original: The ease and expressiveness of PDDL modeling facilitates the inclusion of additional features that are characteristic of quantum computer architectures, such as the ability to quantum teleport quantum states across the chip (Copsey et al. 2003), providing more ﬂexibility than mere nearest-neighbor swap.
Revised: The ease and expressiveness of PDDL modeling facilitates the inclusion of additional features that are characteristic of quantum computer architectures, such as the ability to quantum teleport quantum states across the chip (Copsey et al. 2003), providing more ﬂexibility than mere nearest-neighbor swap.

Original: The modularity of the software suite we introduced allows it to be improved iteratively, giving a foundation for future work on the application artiﬁcial intelligence methods to quantum computing.
Revised: The modularity of the software suite we introduced allows it to be improved iteratively, giving a foundation for future work on the application artiﬁcial intelligence methods to quantum computing.

Original: Here, we focused on the makespan of the compiled circuit as the objective function to minimize, but data from ongoing experimental work will likely yield more sophisticated quantities to optimize.
Revised: Here, we focused on the makespan of the compiled circuit as the objective function to minimize, but data from ongoing experimental work will likely yield more sophisticated quantities to optimize.

Original: We are also actively looking at compiling circuits corresponding to QAOA for different combinatioral optimization problems (e.g. job shop scheduling), many of which involve new types of multi-qubit gates with different characteristics from the simple ones used in illustrative examples in this paper and in other introductory publications.
Revised: We are also actively looking at compiling circuits corresponding to QAOA for different combinatioral optimization problems (e.g. job shop scheduling), many of which involve new types of multi-qubit gates with different characteristics from the simple ones used in illustrative examples in this paper and in other introductory publications.

Original: Another avenue of extension of our work is to generalize the NISQ-QCC problem and our software suite to the speciﬁcities of quantum processors that are dramatically different than superconducting
Revised: Another avenue of extension of our work is to generalize the NISQ-QCC problem and our software suite to the speciﬁcities of quantum processors that are dramatically different than superconducting

Original: NISQ devices.
Revised: NISQ devices.

Original: For instance, soon to made available Iontrap processors such as the one of IonQ (Nam et al. 2019) or of Honeywell International Inc. feature a number fullyconnected cells of qubits (where qubits interact through a different set of native gates than the ones of superconducting processors) which are in communinication to each other through the ability to swap quantum information via photonic interfaces.
Revised: For instance, soon to made available Iontrap processors such as the one of IonQ (Nam et al. 2019) or of Honeywell International Inc. feature a number fullyconnected cells of qubits (where qubits interact through a different set of native gates than the ones of superconducting processors) which are in communinication to each other through the ability to swap quantum information via photonic interfaces.

Revised: In a future work, we intend to provide examples for different architectures including sample code.

Revised: We plan to make the architecture available (to be interfaced with a planner and optionally a CP optimizer) as an opensource package.

Original: Finally we believe that our approach should be of great interest to the community developing lowlevel quantum compilers for generic architectures (Steiger, H¨aner, and Troyer 2018; H¨aner et al. 2018), to designers of machine-instructions languages for quantum computing (Smith, Curtis, and Zeng 2016;
Revised: Finally we believe that our approach should be of great interest to the community developing lowlevel quantum compilers for generic architectures (Steiger, H¨aner, and Troyer 2018; H¨aner et al. 2018), to designers of machine-instructions languages for quantum computing (Smith, Curtis, and Zeng 2016;

Original: Bishop 2017), and to developers of unifying frameworks for quantum computing software toolchains and interface to solvers (McCaskey et al. 2018).
Revised: Bishop 2017), and to developers of unifying frameworks for quantum computing software toolchains and interface to solvers (McCaskey et al. 2018).

Original: Acknowledgement: The authors would like to acknowledge support from the NASA Advanced Exploration Systems program, NASA Academic Mission Services (NNA16BD14C) and the NASA Ames Research Center.
Revised: Acknowledgement: The authors would like to acknowledge support from the NASA Advanced Exploration Systems program, NASA Academic Mission Services (NNA16BD14C) and the NASA Ames Research Center.

Original: B.O. was supported by a NASA Space Technology Research Fellowship.
Revised: B.O. was supported by a NASA Space Technology Research Fellowship.