Original: Versatile Multi-stage Graph Neural Network for Circuit Representation
Revised: Versatile Multi-stage Graph Neural Network for Circuit Representation

Original: Anonymous Author(s)

Original: AffiliationAddress email

Original: Abstract
Revised: Abstract

Original: Due to the rapid growth in the scale of circuits and the desire for knowledgetransfer from old designs to new ones, deep learning technologies have been widelyexploited in Electronic Design Automation (EDA) to assist circuit design.
Revised: Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old designs to new ones, deep learning technologies have been widely exploited in Electronic Design Automation (EDA) to assist circuit design.

Original: In chipdesign cycles, we might encounter heterogeneous and diverse information sources,including the two most informative ones: the netlist and the design layout.
Revised: In chip design cycles, we might encounter heterogeneous and diverse information sources, including the two most informative ones: the netlist and the design layout.

Original: However,handling each information source independently is sub-optimal.
Revised: However, handling each information source independently is sub-optimal.

Original: In this paper, wepropose a novel way to integrate the multiple information sources under a unifiedheterogeneous graph named Circuit Graph , where topological and geometricalinformation is well integrated.
Revised: In this paper, we propose a novel way to integrate the multiple information sources under a unified heterogeneous graph named Circuit Graph , where topological and geometrical information is well integrated.

Original: Then, we propose Circuit GNN to fully utilize thefeatures of vertices, edges as well as heterogeneous information during the messagepassing process.
Revised: Then, we propose Circuit GNN to fully utilize the features of vertices, edges as well as heterogeneous information during the message passing process.

Original: It is the first attempt to design a versatile circuit representationthat is compatible across multiple EDA tasks and stages.
Revised: It is the first attempt to design a versatile circuit representation that is compatible across multiple EDA tasks and stages.

Original: Experiments on the twomost representative prediction tasks in EDA show that our solution reaches stateof-the-art performance in both logic synthesis and global placement chip designstages.
Revised: Experiments on the two most representative prediction tasks in EDA show that our solution reaches stateof-the-art performance in both logic synthesis and global placement chip design stages.

Original: Besides, it achieves a 10x speed-up on congestion prediction compared tothe state-of-the-art model.
Revised: Besides, it achieves a 10x speed-up on congestion prediction compared to the state-of-the-art model.

Original:  Introduction
Revised:  Introduction

Original: Integrated circuits (ICs) are extensively used in modern electronic products like computers, smartphones, and cars.
Revised: Integrated circuits (ICs) are extensively used in modern electronic products like computers, smartphones, and cars.

Original: Electronic Design Automation (EDA) includes a set of tools for circuit designin different development stages especially logic synthesis stage and placement stage (Fig.1).
Revised: Electronic Design Automation (EDA) includes a set of tools for circuit design in different development stages especially logic synthesis stage and placement stage (Fig.1).

Original: Asthe scale and complexity of circuits continuously grow, the design efficiency and precision of EDAtools have become an essential problem which attracts researchers to adopt deep learning techniquesto assist the circuit design process [1].
Revised: As the scale and complexity of circuits continuously grow, the design efficiency and precision of EDA tools have become an essential problem, which attracts researchers to adopt deep learning techniques to assist the circuit design process [1].

Original: Remarkable progress has been made in predicting circuits’quality and practicability in the earlier stage of the chip design to speed up optimization and reducedesign cost [2, 3].
Revised: Remarkable progress has been made in predicting circuits’ quality and practicability in the earlier stage of the chip design to speed up optimization and reduce design cost [2, 3].

Original: For example, predicting congestion for circuits in physical design stage can helpdetect their flaws and avoid producing defective chips and chip design production cycle time can befurther saved if such prediction could be done in logic synthesis stage.
Revised: For example, predicting congestion for circuits in physical design stage can help detect their flaws and avoid producing defective chips, and chip design production cycle time can be further saved if such prediction could be done in logic synthesis stage.

Original: Because of the sophisticated process of circuit design, we will encounter diverse information sourcesfrom various design stages, among which logic synthesis and placement & routing determine thequality, e.g. time delay, of circuit and consume the majority of design pipeline time, as shown in Fig.2.

Original: In the logic synthesis stage, a circuit design is represented as a Netlist composed of cells and nets ,where cells refer to the electronic units and nets refer to the connectivity (i.e. hyper-edges) amongthe cells .

Original: After the placement & routing stage, we will obtain the circuit layout with the position

Original: System Specification Architectural Design
Revised: [Figure]

Original: ROM Arbiter

Original: CPU

Original: [Figure]
Revised: [Figure]

Original: Bus Arbiter

Original: Functional &

Original: Logic Design Logic Synthesis Placement & Routing
Revised: Because of the sophisticated process of circuit design, we will encounter diverse information sources from various design stages, among which logic synthesis and placement & routing determine the quality, e.g. time delay, of circuit and consume the majority of design pipeline time, as shown in Fig.2.

Original: Fabrication & Packaging

Original: [Figure]

Original: net  link [Figure] Graph ( cell -oriented) ( [Figure]
Revised: In the logic synthesis stage, a circuit design is represented as a Netlist composed of cells and nets , where cells refer to the electronic units and nets refer to the connectivity (i.e. hyper-edges) among the cells .

Original: Homo

Original: [Figure] Graph ( net -oriented) a 1, 2,b 2,3, c 4,5, net a a        b 3,c 3, 5,      grid cell b c [Figure] c of each electronic unit provided after they have been fully placed on the circuit board.
Revised: After the placement & routing stage, we will obtain the circuit layout with the position of each electronic unit provided after they have been fully placed on the circuit board.

Original: Besides, thedownstream tasks might require learning representations on both cells and nets , tailoring for specificdownstream tasks.
Revised: Besides, the downstream tasks might require learning representations on both cells and nets , tailoring for specific downstream tasks.

Original: Thus, how to better organize and fuse the diverse and heterogeneous informationprovided in the context of circuit representation is an important research question.
Revised: Thus, how to better organize and fuse the diverse and heterogeneous information provided in the context of circuit representation is an important research question.

Original: Although the information underlying the circuit design varies according to the input stages, we candivide it into geometrical information and topological information .
Revised: Although the information underlying the circuit design varies according to the input stages, we can divide it into geometrical information and topological information .

Original: The netlists only containthe topological information (e.g. cell type and logical relationship between cells and nets ), whilesome geometrical information (e.g. positions of standard cells ) is available after placement stage.
Revised: The netlists only contain the topological information (e.g. cell type and logical relationship between cells and nets ), while some geometrical information (e.g. positions of standard cells ) is available after placement stage.

Original: According to which information they focus on, we categorize the existing prediction methods incircuit designs into topological methods and geometrical methods .
Revised: According to which information they focus on, we categorize the existing prediction methods in circuit designs into topological methods and geometrical methods .

Original: The topological methods convertcircuit designs into homogeneous graphs (Fig.2(c)(d)) and solve the problems with Graph Neural
Revised: The topological methods convert circuit designs into homogeneous graphs (Fig.2(c)(d)) and solve the problems with Graph Neural

Original: Network (GNN) [4, 5, 6], while most recent geometrical models convert the circuit designs into gridfeature matrices (see Def.1 and Fig.2(b)) and adopt Computer Vision (CV) technologies to predicttheir properties [7, 8, 9].
Revised: Network (GNN) [4, 5, 6], while most recent geometrical models convert the circuit designs into grid feature matrices (see Def.1 and Fig.2(b)) and adopt Computer Vision (CV) technologies to predict their properties [7, 8, 9].

Original: However, the topological methods only consider the topological information in netlists and cannoteffectively perceive geometrical structure introduced after the placement stage, so their performanceon circuits after placement is greatly stifled.
Revised: However, the topological methods only consider the topological information in netlists and cannot effectively perceive geometrical structure introduced after the placement stage, so their performance on circuits after placement is greatly stifled.

Original: Besides, the geometrical models heavily rely ongeometrical information and neglect the topology underlying the netlists, so they cannot handlecircuits in stages earlier than global placement where geometry is not available.
Revised: Besides, the geometrical models heavily rely on geometrical information and neglect the topology underlying the netlists, so they cannot handle circuits in stages earlier than global placement where geometry is not available.

Original: In a word, they canonly work well on circuits either in logic synthesis stage or placement stage but are not compatiblewith both.
Revised: In a word, they can only work well on circuits either in logic synthesis stage or placement stage but are not compatible with both.

Original: Moreover, most of the existing prediction methods design modules with prior knowledgeto serve certain applications, so they are not flexible enough to handle diverse EDA tasks.
Revised: Moreover, most of the existing prediction methods design modules with prior knowledge to serve certain applications, so they are not flexible enough to handle diverse EDA tasks.

Original: Therefore,it is necessary to: (1) design a data structure to represent the circuit, which is adaptive to circuits inboth logic synthesis and placement stages; (2) propose an efficient and effective circuit representationmodel which is compatible with two stages and various downstream tasks.
Revised: Therefore, it is necessary to: (1) design a data structure to represent the circuit, which is adaptive to circuits in both logic synthesis and placement stages; (2) propose an efficient and effective circuit representation model which is compatible with two stages and various downstream tasks.

Original: In this paper, we first convert the circuit design to Circuit Graph (see (Fig.3)), a heterogeneous graphwhich preserves most of the topological and geometrical information, with a linear time consumptionto the scale of the design (see Appendix.
Revised: In this paper, we first convert the circuit design to Circuit Graph (see (Fig.3)), a heterogeneous graph which preserves most of the topological and geometrical information, with a linear time consumption to the scale of the design (see Appendix.

Original: B.2 for proof).
Revised: B.2 for proof).

Original: A circuit graph contains two types of verticesi.e. cells and nets .
Revised: A circuit graph contains two types of vertices i.e. cells and nets .

Original: We use pins which connect cells and nets to represent the topology, which are also noted as topo-edges .
Revised: We use pins which connect cells and nets to represent the topology, which are also noted as topo-edges .

Original: When handling circuits in placement stage, we additionally link the cells whichare geometrically close (named geom-edges ) to represent the geometry.
Revised: When handling circuits in placement stage, we additionally link the cells which are geometrically close (named geom-edges ) to represent the geometry.

Original: Then, we design Circuit GNN to process Circuit Graphs with optimal efficiency and producerepresentations for cells and nets to handle diverse tasks on circuits in both logic synthesis stageand placement stage.
Revised: Then, we design Circuit GNN to process Circuit Graphs with optimal efficiency and produce representations for cells and nets to handle diverse tasks on circuits in both logic synthesis stage and placement stage.

Original: To collect and enrich the topological and geometrical information, we conductmessage-passing [10] on topo-edges and geom-edges individually and later fuse the messages toupdate cells and nets representations.
Revised: To collect and enrich the topological and geometrical information, we conduct message-passing [10] on topo-edges and geom-edges individually and later fuse the messages to update cells and nets representations.

Original: Multiple layers of such “message-passing & fusion” inferencefurther exploit the deep relationships between topology and geometry and facilitate Circuit GNN tooutput nutritious representations.
Revised: Multiple layers of such “message-passing & fusion” inference further exploit the deep relationships between topology and geometry and facilitate Circuit GNN to output nutritious representations.

Original: Circuit GNN is also compatible with Circuit Graphs converted fromcircuits in logic synthesis stage because geom-edges ’s absence will not disable the message-passingover topo-edges and the topological information can still be collected.
Revised: Circuit GNN is also compatible with Circuit Graphs converted from circuits in logic synthesis stage because geom-edges ’s absence will not disable the message-passing over topo-edges and the topological information can still be collected.

Original: In summary, our contributions are:
Revised: In summary, our contributions are:

Original: • To address the challenge posed by the diverse and heterogeneous information source in the context of circuit representation, we propose a novel way to integrate the information namedCircuit Graph , a heterogeneous graph where topological and geometrical informationare integrated jointly, which is able to handle diverse circuit tasks on cell, nets level andon different stages.
Revised: • To address the challenge posed by the diverse and heterogeneous information source in the context of circuit representation, we propose a novel way to integrate the information named Circuit Graph , a heterogeneous graph where topological and geometrical information are integrated jointly, which is able to handle diverse circuit tasks on cell, nets level and on different stages.

Original: To our best knowledge, this is the first unified circuit representationapproach that can be easily compatible across EDA tasks and stages.
Revised: To our best knowledge, this is the first unified circuit representation approach that can be easily compatible across EDA tasks and stages.

Original: • We propose a novel message-passing paradigm Circuit GNN that tailors the aforementionedgraph dataset structure.
Revised: • We propose a novel message-passing paradigm Circuit GNN that tailors the aforementioned graph dataset structure.

Original: We design message-passing on both topological and geometricaledges distinctively and then fuse the messages to update cells and nets representations.
Revised: We design message-passing on both topological and geometrical edges distinctively and then fuse the messages to update cells and nets representations.

Original: The efficiency and effectiveness of our design are demonstrated both methodologically andexperimentally.
Revised: The efficiency and effectiveness of our design are demonstrated both methodologically and experimentally.

Original: • Experiment results validate the superior performance and efficiency of Circuit Graph acrossmulti-stages/tasks.
Revised: • Experiment results validate the superior performance and efficiency of Circuit Graph across multi-stages/tasks.

Original: For circuit congestion prediction task at logic synthesis stage, it improvesthe average grid-level accuracy by 16.7% against SOTA.
Revised: For circuit congestion prediction task at logic synthesis stage, it improves the average grid-level accuracy by 16.7% against SOTA.

Original: At placement stage, it achieves5.6% accuracy gain with 10x speed-up in congestion prediction task and 16.9% error gainin net wirelength prediction task.
Revised: At placement stage, it achieves 5.6% accuracy gain with 10x speed-up in congestion prediction task and 16.9% error gain in net wirelength prediction task.

Original:  Related Work 
Revised:  Related Work 2.1 Topological Methods

Original: .1 Topological Methods

Original: The topological methods in EDA focus on the logic relationships between the cells and nets and usuallyreconstruct the circuit designs into graphs with vertices and edges.
Revised: The topological methods in EDA focus on the logic relationships between the cells and nets and usually reconstruct the circuit designs into graphs with vertices and edges.

Original: CongestionNet[5] and solutionsin [6] link the cell -pairs connected via nets (Fig.2(c)) and adopt popular GNNs (e.g. GAT[11]) togenerate cell representations for congestion prediction.
Revised: CongestionNet[5] and solutions in [6] link the cell -pairs connected via nets (Fig.2(c)) and adopt popular GNNs (e.g. GAT[11]) to generate cell representations for congestion prediction.

Original: To handle net length identification and netdelay prediction, Net 2 [12] links the nets connecting to one cell (Fig.2(d)) and designs a customized
Revised: To handle net length identification and net delay prediction, Net 2 [12] links the nets connecting to one cell (Fig.2(d)) and designs a customized

Original: GNN to obtain net representations.
Revised: GNN to obtain net representations.

Original: All these methods perceive the circuit designs as homogeneousgraphs and neglect the underlying heterogeneity, e.g. the interaction between cells and nets likesignal input/output, so their solutions suffer from information loss and will affect the performance ofdownstream GNN.
Revised: All these methods perceive the circuit designs as homogeneous graphs and neglect the underlying heterogeneity, e.g. the interaction between cells and nets like signal input/output, so their solutions suffer from information loss and will affect the performance of downstream GNN.

Original: 2.2 Geometrical Methods
Revised: 2.2 Geometrical Methods

Original: The geometrical methods in EDA focus on the spatial information of the circuit designs.
Revised: The geometrical methods in EDA focus on the spatial information of the circuit designs.

Original: A universalapproach is to cut a circuit into small rectangles i.e. grids and convert it into RGB channels, wherethe grids are treated as pixels [8, 13].
Revised: A universal approach is to cut a circuit into small rectangles i.e. grids and convert it into RGB channels, where the grids are treated as pixels [8, 13].

Original: Then, they encode the netlist structure and circuit features intogreen and blue channels while red channels are left for prediction targets (e.g. congestion).
Revised: Then, they encode the netlist structure and circuit features into green and blue channels while red channels are left for prediction targets (e [Figure] g. congestion).

Original: Finally,they use image translation methods (e.g. pix2pix [9]) to output new images with red channels filledand indirectly solve the EDA tasks.
Revised: Finally, they use image translation methods (e.g. pix2pix [9]) to output new images with red channels filled and indirectly solve the EDA tasks.

Original: The cutting-edge LHNN [14], however, converts the circuits into lattice networks [15] instead ofimages, where each grid serves as an internal node in the network and each net, as an external node, isconnected to the grids it covers geometrically.
Revised: The cutting-edge LHNN [14], however, converts the circuits into lattice networks [15] instead of images, where each grid serves as an internal node in the network and each net, as an external node, is connected to the grids it covers geometrically.

Original: LHNN successfully enhances topological informationin geometrical method and achieves SOTA performance, but it can only handle congestion predictiontask and can only work on circuits with placement information.
Revised: LHNN successfully enhances topological information in geometrical method and achieves SOTA performance, but it can only handle congestion prediction task and can only work on circuits with placement information [Figure]

Original:  Circuit Graph
Revised:  Circuit Graph

Original: [Figure]
Revised: [Figure]

Revised: (i.e. pin

Original: [Figure]
Revised: [Figure]

Original: 3.1 Circuit Featurization
Revised: 3.1 Circuit Featurization

Original: A circuit design is initially represented as a netlist composed of cells V and nets U (Fig.2(a)), and wedefine X V , X U to be their feature matrices.
Revised: A circuit design is initially represented as a netlist composed of cells V and nets U (Fig.2(a)), and we define X V , X U to be their feature matrices.

Original: X V mainly contains the size and degree (to net ) of thecells, and X U stores the net span [14] and the degree (to cell ).
Revised: X V mainly contains the size and degree (to net ) of the cells, and X U stores the net span [14] and the degree (to cell ).

Original: Besides the basic attributes of cells and nets , the topology and geometry also play important roles infeaturizing the circuit designs.
Revised: Besides the basic attributes of cells and nets , the topology and geometry also play important roles in featurizing the circuit designs.

Original: The pins P ⊆
Revised: The pins P ⊆

Original: V × U stand for the bipartite topology between cells
Revised: V × U stand for the bipartite topology between cells

Original: V and nets U , and X P , the feature matrix of P , preserves their interaction details e.g. the signaldirection (input/output).
Revised: V and nets U , and X P , the feature matrix of P , preserves their interaction details e.g. the signal direction (input/output).

Original: After placement, the positions of cells p x , p y are obtained, which serveas a major geometrical information.
Revised: After placement, the positions of cells p x , p y are obtained, which serve as a major geometrical information.

Original: When carrying out deep learning on EDA, how to arrange thefeatures of circuit design varies according the downstream model.
Revised: When carrying out deep learning on EDA, how to arrange the features of circuit design varies according the downstream model.

Original: The geometrical methods cut the circuit into smaller rectangles i.e. grids 1 and generate raw featureson them by synthesizing the positions of cells p x , p y along with cells ’ and nets ’ features X V , X Uand their connections P (Fig.2(b))
Revised: The geometrical methods cut the circuit into smaller rectangles i.e. grids 2 and generate raw features on them by synthesizing the positions of cells p x , p y along with cells ’ and nets ’ features X V , X U and their connections P (Fig.2(b))

Original: Definition 1 (Geometry-driven Circuit Featurization) .
Revised: Definition 1 (Geometry-driven Circuit Featurization) .

Original: F G = { X gr } , where X gr = R C x × C y × D gr isthe feature matrix of grids.
Revised: F G = { X gr } , where X gr = R C x × C y × D gr is the feature matrix of grids.

Original: Note that C x , C y are the column and row numbers of grids and D gr isthe dimension of grids’ raw features.
Revised: Note that C x , C y are the column and row numbers of grids and D gr is the dimension of grids’ raw features.

Original: The grid feature X gr mainly includes pin density and net density [7].
Revised: The grid feature X gr mainly includes pin density and net density [7].

Original: As the structure of X gr issimilar to RGB channels of image data, CV models (e.g. CNN[9]) can be easily adopted to handle
Revised: As the structure of X gr is similar to RGB channels of image data, CV models (e.g. CNN[9]) can be easily adopted to handle

Original: EDA tasks where geometrical information are provided as input.
Revised: EDA tasks where geometrical information are provided as input.

Original: The topological methods prefer to construct the circuit design as a bipartite graph (Def.2) [12]:
Revised: The topological methods prefer to construct the circuit design as a bipartite graph (Def.2) [12]:

Original: Definition 2 (Topology-driven Circuit Featurization) .
Revised: Definition 2 (Topology-driven Circuit Featurization) .

Original: F T = {V , U , P , X V , X U , X P } , where cells
Revised: F T = {V , U , P , X V , X U , X P } , where cells

Original: V and nets U are two types of vertices, and pins P are the edges connecting them.
Revised: V and nets U are two types of vertices, and pins P are the edges connecting them.

Original: However, F T is usually simplified as a homogeneous graph, and is fed to some popular GNNs, suchas GAT (see Fig.2(c)(d) and Sec.2.1) [5, 6, 12], which leads to loss of heterogeneous information.
Revised: However, F T is usually simplified as a homogeneous graph, and is fed to some popular GNNs, such as GAT (see Fig.2(c)(d) and Sec.2.1) [5, 6, 12], which leads to loss of heterogeneous information.

Original: Note that the explicit raw features of grid , cell , net and pin are listed in Appendix A.
Revised: Note that the explicit raw features of grid , cell , net and pin are listed in Appendix A.

Original: 3.2 Definition of Circuit Graph
Revised: 3.2 Definition of Circuit Graph

Original: To better benefit from both the above two commonly used featurization system for circuit, we proposea novel way to encode both the topological and geometrical information (when available) underlyingthe circuits into a unified heterogeneous graph.
Revised: To better benefit from both the above two commonly used featurization system for circuit, we propose a novel way to encode both the topological and geometrical information (when available) underlying the circuits into a unified heterogeneous graph.

Original: As shown in Fig.3, we first take pins as topo-edges( E T = P and X E T = X P ).
Revised: As shown in Fig.3, we first take pins as topo-edges ( E T = P and X E T = X P ).

Original: Then we link the geometrically-close cells with geom-edges E G andstore the cell -pair distances in feature matrix X E G .
Revised: Then we link the geometrically-close cells with geom-edges E G and store the cell -pair distances in feature matrix X E G .

Original: Finally, we define Circuit Graph as follows:
Revised: Finally, we define Circuit Graph as follows:

Original: Definition 3 (Circuit Graph) .
Revised: Definition 3 (Circuit Graph) .

Original: A Circuit Graph G =
Revised: A Circuit Graph G =

Original: {V , U , E T , E G , X V , X U , X E T , X E G } , where
Revised: {V , U , E T , E G , X V , X U , X E T , X E G } , where

Original: V , U , E T ⊆
Revised: V , U , E T ⊆

Original: V ×U , E G ⊆
Revised: V ×U , E G ⊆

Original: V ×V refer to the set of cells, nets, topo-edges and geom-edges, respectively,and X V , X U , X E T , X E G are their feature matrices.
Revised: V ×V refer to the set of cells, nets, topo-edges and geom-edges, respectively, and X V , X U , X E T , X E G are their feature matrices.

Original: To preserve the topological information, we completely inherit V , U , P and their features from F T in
Revised: To preserve the topological information, we completely inherit V , U , P and their features from F T in

Original: Def.2 rather than simplify them as homogeneous graphs with loss of heterogeneity.
Revised: Def.2 rather than simplify them as homogeneous graphs with loss of heterogeneity.

Original: For geometricalinformation, to avoid calculating all O ( |V| 2 ) cell -pairs’ distances and reduce time cost to O ( |V| ) , wesplit the cells by shifted windows[16] with size ( w x , w y ) and link the cells with up to c (named “linkcapacity”) neighbouring cells located in the same window (see explicit steps in Appendix B.1).
Revised: For geometrical information, to avoid calculating all O ( |V| 2 ) cell -pairs’ distances and reduce time cost to O ( |V| ) , we split the cells by shifted windows[16] with size ( w x , w y ) and link the cells with up to c (named “link capacity”) neighbouring cells located in the same window (see explicit steps in Appendix B.1).

Original: Ifwe need to handle the problem at the pre-placement phase such as the logic synthesis stage, we willnot have the geom-edges among the cells and will set E G = ∅ for the representation learning phase,which shows that Circuit Graph is compatible with circuits in logic synthesis stage.
Revised: If we need to handle the problem at the pre-placement phase such as the logic synthesis stage, we will not have the geom-edges among the cells and will set E G = ∅ for the representation learning phase, which shows that Circuit Graph is compatible with circuits in logic synthesis stage.

Original: Note that the time consumption of converting a circuit design into a Circuit Graph is O ( |V| + |U| + |P| ) ,which is linear to the scale of the circuit (see proof in Appendix B.2).[Figure]
Revised: Note that the time consumption of converting a circuit design into a Circuit Graph is O ( |V| + |U| + |P| ) , which is linear to the scale of the circuit (see proof in Appendix B.2).

Original:  Circuit GNN 
Revised:  Circuit GNN 4.1 Overview

Original: [Figure] 4.1 Overview

Original: [Figure]
Revised: [Figure]

Revised: b   56 c

Original: The framework of Circuit GNN is shown in Fig.4.
Revised: The framework of Circuit GNN is shown in Fig.4.

Original: We first input the Circuit Graph G and initialize the feature of cells V , nets U , topo-edges E T and geom-edges E G to hidden representations
Revised: We first input the Circuit Graph G and initialize the feature of cells V , nets U , topo-edges E T and geom-edges E G to hidden representations

Original: H (0) V , H (0) U , H E T , H E G with Multi-Layer Perceptrons (MLPs).
Revised: H (0) V , H (0) U , H E T , H E G with Multi-Layer Perceptrons (MLPs).

Original: Then deeper representations of cellsand nets are generated via L layers of circuit message-passing.
Revised: Then deeper representations of cells and nets are generated via L layers of circuit message-passing.

Original: Finally, the output cell and netrepresentations are used for downstream tasks after passing through task-adaptive readout layers.
Revised: Finally, the output cell and net representations are used for downstream tasks after passing through task-adaptive readout layers.

Original: Note that Circuit GNN’s model sensitivity is justified in Appendix D.[Figure]
Revised: Note that Circuit GNN’s model sensitivity is justified in Appendix D.

Original: 4.2 Topo-Geom Message-passing
Revised: 4.2 Topo-Geom Message-passing

Original: Inside each layer out of L Topo-Geom Message-passing layers, topological and geometrical information are collected by passing messages through two types of heterogeneous edges ( E T and E G ).
Revised: Inside each layer out of L Topo-Geom Message-passing layers, topological and geometrical information are collected by passing messages through two types of heterogeneous edges ( E T and E G ).

Original: Then,the messages are used to update cell representations H V and net representations H U .
Revised: Then, the messages are used to update cell representations H V and net representations H U .

Original: In Topological
Revised: In Topological

Original: Message-passing, the messages between cells V and nets U are transmitted through topo-edges E T :
Revised: Message-passing, the messages between cells V and nets U are transmitted through topo-edges E T :

Original: [Equation]
Revised: [Equation]

Original: l [Equation] where l is the number of current layer and Φ U E T −−→ V msg is the message function which collects topological messages from nets U and sends them to cells V via topo-edges E T ( Φ V E T −−→
Revised: where l is the number of current layer and Φ U E T −−→ V msg is the message function which collects topological messages from nets U and sends them to cells V via topo-edges E T ( Φ V E T −−→

Original: U msg similarly).
Revised: U msg similarly).

Original: In
Revised: In

Original: Geometrical Message-passing, we consider the geom-edges E G and collect geometrical messages forcells V :
Revised: Geometrical Message-passing, we consider the geom-edges E G and collect geometrical messages for cells V :

Original: [Equation]
Revised: [Equation]

Original: Then, we fuse the topological and geometrical messages and update the representations:
Revised: Then, we fuse the topological and geometrical messages and update the representations:

Original: [Equation]

Original: [Equation]
Revised: [Equation]

Original: where the update function Φ update ( H , M )
Revised: where the update function Φ update ( H , M )

Original: =
Revised: =

Original: H + Tanh( M ) .
Revised: H + Tanh( M ) .

Original: The efficiency and the capability of perceiving heterogeneous information (e.g. the edge embeddingsin E T and E G which encode topological and geometrical information) should be considered whendesigning the exact message functions Φ msg .
Revised: The efficiency and the capability of perceiving heterogeneous information (e.g. the edge embeddings in E T and E G which encode topological and geometrical information) should be considered when designing the exact message functions Φ msg .

Original: In Topological Message-passing, inspired by [17], fora net u , we fuse the representations of surrounding cells { v | ( v,
Revised: In Topological Message-passing, inspired by [17], for a net u , we fuse the representations of surrounding cells { v | ( v,

Original: u ) ∈ E T } and topo-edges connectingthem:
Revised: u ) ∈ E T } and topo-edges connecting them:

Original: [Equation]
Revised: [Equation]

Original: where h V v is the representation vector of cell v , h E T ( v,u ) is the representation vector of topo-edgeconnecting v, u , W V→U , W E T →U are learnable weight matrices and ⊙ is the element-wise multiplication.
Revised: where h V v is the representation vector of cell v , h E T ( v,u ) is the representation vector of topo-edge connecting v, u , W V→U , W E T →U are learnable weight matrices and ⊙ is the element-wise multiplication.

Original: As topo-edge ’s representations have already been collected in Φ V E T −−→ U msg , we only considernet ’s representations h U u in the messages passed back to the cells , which speeds up message-passing(because of less computation) with minor topological information loss:
Revised: As topo-edge ’s representations have already been collected in Φ V E T −−→ U msg , we only consider net ’s representations h U u in the messages passed back to the cells , which speeds up message-passing (because of less computation) with minor topological information loss:

Original: [Equation]
Revised: [Equation]

Original: In Geometrical Message-passing, to enhance the geometrical information, the geom-edge ’s representations are used to compute the edge weights when convolving the cells :
Revised: In Geometrical Message-passing, to enhance the geometrical information, the geom-edge ’s representations are used to compute the edge weights when convolving the cells :

Original: [Equation]
Revised: [Equation]

Original: where a is a learnable weight vector and W V→V is a learnable weight matrix.
Revised: where a is a learnable weight vector and W V→V is a learnable weight matrix.

Original: Discussion of Inference Time.
Revised: Discussion of Inference Time.

Original: Assume that the hidden layer dimensions of cell , net , topoedge , geom-edge are F V , F U , F E T , F E G .
Revised: Assume that the hidden layer dimensions of cell , net , topoedge , geom-edge are F V , F U , F E T , F E G .

Original: The inference times of Φ V E T −−→ U msg , Φ U E T −−→ V msg , Φ V E G −−→ V msg are
Revised: The inference times of Φ V E T −−→ U msg , Φ U E T −−→ V msg , Φ V E G −−→ V msg are

Original: O ( |E T | ( F E T F U + F V F U + F U )) , O ( |E T | F U F V ) , O ( |E G | ( F E G + F 2 V )) , respectively.
Revised: O ( |E T | ( F E T F U + F V F U + F U )) , O ( |E T | F U F V ) , O ( |E G | ( F E G + F 2 V )) , respectively.

Original: The time complexities of fusing ( MaxPooling ) and updating are O ( |V| F V ) , O ( |V| F V + |U| F U ) , respectively.
Revised: The time complexities of fusing ( MaxPooling ) and updating are O ( |V| F V ) , O ( |V| F V + |U| F U ) , respectively.

Original: Asthe dimensions are constant numbers and |E T | =
Revised: As the dimensions are constant numbers and |E T | =

Original: O ( |P| ) , |E G
Revised: O ( |P| ) , |E G

Original: | =
Revised: | =

Original: O ( |V| ) (see Appendix B.2), thetotal inference time in one Topo-Geom Message-passing layer is O ( |V| + |U| + |P| ) , which is linearto the scale of input Circuit Graph.
Revised: O ( |V| ) (see Appendix B.2), the total inference time in one Topo-Geom Message-passing layer is O ( |V| + |U| + |P| ) , which is linear to the scale of input Circuit Graph.

Original: Therefore, our message-passing method can handle Circuit Graphwith optimal efficiency , and it is further demonstrated to be as fast as CongestionNet [5], a deep
Revised: Therefore, our message-passing method can handle Circuit Graph with optimal efficiency , and it is further demonstrated to be as fast as CongestionNet [5], a deep

Original: GAT architecture, in Tab.1.
Revised: GAT architecture, in Tab.1.

Original: 4.3 Task-adaptive Readout
Revised: 4.3 Task-adaptive Readout

Original: After L iterations of message-passing, we read out the cell and net representations H ( L ) V , H ( L ) U tohandle diverse downstream tasks on circuits.
Revised: After L iterations of message-passing, we read out the cell and net representations H ( L ) V , H ( L ) U to handle diverse downstream tasks on circuits.

Original: For tasks on Cell-level (e.g. congestion prediction foreach cell [5]), to enhance the raw features, we concatenate the cell representation and its raw featuresand pass them through an MLP (similarly for Net-level tasks e.g. net length prediction [12]):
Revised: For tasks on Cell-level (e.g. congestion prediction for each cell [5]), to enhance the raw features, we concatenate the cell representation and its raw features and pass them through an MLP (similarly for Net-level tasks e.g. net length prediction [12]):

Original: [Equation]
Revised: [Equation]

Original: However, Grid-level tasks (e.g. congestion prediction for each grid in chip map [9]) assign targets oneach grid , which our model is not aware of.
Revised: However, Grid-level tasks (e.g. congestion prediction for each grid in chip map [9]) assign targets on each grid , which our model is not aware of.

Original: To enable model’s training and evaluation on these tasks,we generate an output representation on each grid by mean-pooling the representation of cells insidethe grid :
Revised: To enable model’s training and evaluation on these tasks, we generate an output representation on each grid by mean-pooling the representation of cells inside the grid :

Original: [Equation]
Revised: [Equation]

Original: where ˆ M ∈ R C x × C y ×|V| is the transformation matrix with (cid:80) 
Revised: where ˆ M ∈ R C x × C y ×|V| is the transformation matrix with (cid:80) k ˆ M i,

Original: k ˆ M i,j,k = 1 , ∀ i, j .
Revised: [Equation] ,k = 1 , ∀ i, j .

Original:  Experiments 
Revised:  Experiments 5.1 Tasks and Datasets

Original: 5.1 Tasks and Datasets

Original: Congestion Prediction is the task of predicting the routing congestion before the wires are routedin the detailed routing stage.
Revised: Congestion Prediction is the task of predicting the routing congestion before the wires are routed in the detailed routing stage.

Original: It is widely used in placement tools to provide quick feedback aboutthe quality of placement and avoid placement solutions with poor routability [18][19][20].
Revised: It is widely used in placement tools to provide quick feedback about the quality of placement and avoid placement solutions with poor routability [18][19][20].

Original: Inorder to identify and solve potential congested structures earlier, multiple works have attemptedto predict cell-level congestion in logic synthesis stage, before cells are placed [6][21][22].
Revised: In order to identify and solve potential congested structures earlier, multiple works have attempted to predict cell-level congestion in logic synthesis stage, before cells are placed [6][21][22].

Original: Weconduct the experiment on ISPD2011 2 , which contains 12 VLSI designs in total.
Revised: We conduct the experiment on ISPD2011 3 , which contains 12 VLSI designs in total.

Original: We use 10 designs (1/2/3/5/6/7/9/11/14/16) for training, design #18 for validation, and #19 for testing.
Revised: We use 10 designs (1/2/3/5/6/7/9/11/14/16) for training, design #18 for validation, and #19 for testing.

Original: We use
Revised: We use

Original: DREAMPlace[18] to place cells and initialize the raw features of cells , nets and grids .
Revised: DREAMPlace[18] to place cells and initialize the raw features of cells , nets and grids .

Original: NCTU-GR2.0[23], a popular global router, is used to generate the congestion targets on the grids.
Revised: NCTU-GR 2.0[23], a popular global router, is used to generate the congestion targets on the grids.

Original: The congestiontarget of each cell is set as the value of the grid it is located in.
Revised: The congestion target of each cell is set as the value of the grid it is located in.

Original: For congestion prediction in logicsynthesis stage, we only use the topology of the circuits and the geometry-insensitive features.
Revised: For congestion prediction in logic synthesis stage, we only use the topology of the circuits and the geometry-insensitive features.

Original: Forprediction in placement, we additionally use the cells ’ positions generated by DREAMPlace.
Revised: For prediction in placement, we additionally use the cells ’ positions generated by DREAMPlace.

Original: Similar to [6], we compare the prediction and ground-truth in Pearson/Spearman/Kendall correlationon both Cell-level and Grid-level.
Revised: Similar to [6], we compare the prediction and ground-truth in Pearson/Spearman/Kendall correlation on both Cell-level and Grid-level.

Original: We also divide the congestion values to [0 , 0 . 9] and (0 . 9 , ∞ ) anduse precision/recall/F1-score to further evaluate their ability of identifying congestion [14].
Revised: We also divide the congestion values to [0 , 0 . 9] and (0 . 9 , ∞ ) and use precision/recall/F1-score to further evaluate their ability of identifying congestion [14].

Original: Net Wirelength Prediction aims to deduce the wire length of each net , which is an importantindicator of the eventual chip performance [24].
Revised: Net Wirelength Prediction aims to deduce the wire length of each net , which is an important indicator of the eventual chip performance [24].

Original: We use half-perimeter wirelength (HPWL) as thewirelength estimator, which is the most commonly used method for wirelength calculation [2].
Revised: We use half-perimeter wirelength (HPWL) as the wirelength estimator, which is the most commonly used method for wirelength calculation [2].

Original: Weconduct the experiment on DAC2012 3 , where we use 7 designs (3/6/7/9/11/12/14) for training, design#16 for validation and #19 for testing.
Revised: We conduct the experiment on DAC2012 4 , where we use 7 designs (3/6/7/9/11/12/14) for training, design #16 for validation and #19 for testing.

Original: DREAMPlace[18] is used to generate the targets for every net .
Revised: DREAMPlace[18] is used to generate the targets for every net .

Original: The featurization of circuits in both stages is the same with Congestion Prediction mentioned above.
Revised: The featurization of circuits in both stages is the same with Congestion Prediction mentioned above.

Original: As the regression targets of wirelength range from 0 to about 25k, we take the log 10 of them to makethe distribution of targets more smoothing.
Revised: As the regression targets of wirelength range from 0 to about 25k, we take the log 10 of them to make the distribution of targets more smoothing.

Original: We evaluate the results in Pearson/Spearman/Kendallcorrelation as well as Mean Average Error (MAE) and Root Mean Square Error (RMSE).
Revised: We evaluate the results in Pearson/Spearman/Kendall correlation as well as Mean Average Error (MAE) and Root Mean Square Error (RMSE).

Original: Transfer Task To evaluate baselines’ transferability, we conduct an experiment in Appendix G.
Revised: Transfer Task is designed to further evaluate the representativeness of extracted GNN features.

Revised: Here, we first train Circuit GNN/LHNN with Congestion Prediction task and then evaluate/fine-tune them with Wirelength Prediction.

Original: 5.2 Baselines and Settings
Revised: 5.2 Baselines and Settings

Original: When conducting the two tasks above, we compare our model with the following baselines.
Revised: When conducting the two tasks above, we compare our model with the following baselines.

Original: Traditional machine learning methods include MLP , typical graph representation models
Revised: Traditional machine learning methods include MLP , typical graph representation models

Original: GCN [25]/ GAT [11]/ GraphSAGE [26] and pix2pix [9]/ MPNN [10], a typical image translation modelin CV.
Revised: GCN [25]/ GAT [11]/ GraphSAGE [26]/ MPNN [10] and pix2pix [9]/, a typical image translation model in CV.

Original: We also carry out results on EDA-customized machine learning models: (1) CongestionNet [5],a multi-layer graph attentive architecture designed to predict circuit congestion; (2) Net 2f / Net 2a [12],pre-placement net representation models with customized GNN; (3) LHNN [14]: a geometricalcongestion prediction method supplied with topological information i.e. net span.
Revised: We also carry out results on EDA-customized machine learning models: (1) CongestionNet [5], a multi-layer graph attentive architecture designed to predict circuit congestion; (2) Net 2f / Net 2a [12], pre-placement net representation models with customized GNN; (3) LHNN [14]: a geometrical congestion prediction method supplied with topological information i.e. net span.

Original: To further validateour model’s ability to fuse the topological and geometrical information, we test two variants of ourmodel: Ours (w/o. geom.) which throws all geom-edges and Ours (w/o. topo.) which throws alltopo-edges in Circuit Graph (Def.3).
Revised: To further validate our model’s ability to fuse the topological and geometrical information, we test two variants of our model: Ours (w/o. geom.) which throws all geom-edges and Ours (w/o. topo.) which throws all topo-edges in Circuit Graph (Def.3).

Original: For cited methods, we use their default model settings.
Revised: For cited methods, we use their default model settings.

Original: For Circuit GNN, we set hidden layerdimensions of cell , net , topo-edge , geom-edge ( F V , F U , F E T , F E G ) =
Revised: For Circuit GNN, we set hidden layer dimensions of cell , net , topo-edge , geom-edge ( F V , F U , F E T , F E G ) =

Original: (64 , 128 , 8 , 4) and
Revised: (64 , 128 , 8 , 4) and

Original: messagepassing layers L = 2 .
Revised: message passing layers L = 2 .

Original: We have default settings of window size ( w x , w y )
Revised: We have default settings of window size ( w x , w y )

Original: =
Revised: =

Original:  and link capacityc = 5 , and their parameter sensitivity is tested in Appendix C to show the robustness of our model.
Revised: (32 , 40) and link capacity c = 5 , and their parameter sensitivity is tested in Appendix C to show the robustness of our model.

Original: When training our model with Adam Optimizer , we use learning rate γ = 0 . 0002 , learning ratedecay ∆ γ = 0 .
Revised: When training our model with Adam Optimizer , we use learning rate γ = 0 . 0002 , learning rate decay ∆ γ = 0 .

Original: 02 , weight decay η = 0 .
Revised: 02 , weight decay η = 0 .

Original: and training epoch e = 100 .
Revised: and training epoch e = 100 .

Original: 5.3 Result of Congestion Prediction
Revised: 5.3 Result of Congestion Prediction

Original: [Table]
Revised: [Table]

Original: [Table] [Table] [Table] [Table]
Revised: GAT 13.

Original: CongestionNet 22.
Revised: CongestionNet 22.

Original: [Table] [Table] [Table] MPNN 
Revised: MPNN 116.

Original: [Table] [Table] [Table]
Revised: Ours (w/o. geom.) 21.

Original: [Table] [Table]
Revised: Baseline

Original: [Table] Ours (w/o. geom.)
Revised: Time (s/epoch) Cell-level

Original: [Table] [Table] [Table] [Table]
Revised: Grid-level pearson spearman kendall pearson spearman kendall

Original: GAT [Table] [Table]
Revised: GAT (w. geom.) 16.

Original: LHNN [Table] [Table] Ours
Revised: pix2pix 4.

Original: [Table]
Revised: LHNN 305.

Original: w/ [Table] . topo.)[Table]
Revised: Ours (w/o. topo.)

Original: [Table] Ours [Table] [Table]
Revised: Ours 27.

Original: [Figure]
Revised: [Figure]

Original: We first evaluate the congestion prediction result on circuits in logic synthesis stage when geometricinformation is not available (Tab.1).
Revised: We first evaluate the congestion prediction result on circuits in logic synthesis stage when geometric information is not available (Tab.1).

Original: Then we perform the same task in placement stage as shown in
Revised: Then we perform the same task in placement stage as shown in

Original: Tab.2 and Tab.15 (in Appendix).
Revised: Tab.2 and Tab.16 (in Appendix).

Original: Note that geometrical methods pix2pix and LHNN are not aware ofcells in circuit design, so they are not evaluated on Cell-level.
Revised: Note that geometrical methods pix2pix and LHNN are not aware of cells in circuit design, so they are not evaluated on Cell-level.

Original: GAT (w. geom.) is regular GAT withcell positions as additional features.
Revised: GAT (w. geom.) is regular GAT with cell positions as additional features.

Original: The results show that: (1) In logic synthesis stage, our method with only topo-edges achieves thebest performance (16.7% over cutting-edge CongestionNet ) with a similar time cost compared totraditional GNN models (5x faster than MPNN which has a time-expensive and underused edgefunction for netlist input).
Revised: The results show that: (1) In logic synthesis stage, our method with only topo-edges achieves the best performance (16.7% over cutting-edge CongestionNet ) with a similar time cost compared to traditional GNN models (5x faster than MPNN which has a time-expensive and underused edge function for netlist input).

Original: In placement stage, our method beats the cutting-edge LHNN in mostmetrics (5.6% on average) while taking only one-tenth of the run-time.
Revised: In placement stage, our method beats the cutting-edge LHNN in most metrics (5.6% on average) while taking only one-tenth of the run-time.

Original: The superior performance ofour model is primarily attributed to the fusion of both topological and geometrical information.
Revised: The superior performance of our model is primarily attributed to the fusion of both topological and geometrical information.

Original: Fig.5 visualizes the predicted congestion values using different methods.
Revised: Fig.5 visualizes the predicted congestion values using different methods.

Original: Compared to vision-basedmethod [9] and lattice network-based method [15], our proposed method can generate finer congestionprediction with better discriminability.
Revised: Compared to vision-based method [9] and lattice network-based method [15], our proposed method can generate finer congestion prediction with better discriminability.

Original: 5.4 Result of Net Wirelength Prediction
Revised: 5.4 Result of Net Wirelength Prediction

Original: [Figure] [Table]
Revised: [Table] [Table]

Revised: [Table]

Original: [Figure]
Revised: [Figure]

Original: The result of net wirelength prediction is shown in Tab.14 (logic synthesis stage, in Appendix),
Revised: The result of net wirelength prediction is shown in Tab.15 (logic synthesis stage, in Appendix),

Original: Tab.3 and Fig.6 (placement stage).
Revised: Tab.3 and Fig.6 (placement stage).

Original: We obtain LHNN’s result on this task by reading out its netrepresentations generated in the intermediate stage.
Revised: We obtain LHNN’s result on this task by reading out its net representations generated in the intermediate stage.

Original: The result shows that our model achieves SOTAperformance (16.9% error gain) with similar time cost to Net 2f and Net 2a .
Revised: The result shows that our model achieves SOTA performance (16.9% error gain) with similar time cost to Net 2f and Net 2a .

Revised: 5.5 Result of Transfer Task

Revised: Here are the experimental settings:

Revised: • For the evaluation setting, a different readout module is trained from scratch, but GNN’s parameters are fixed.

Revised: • For the fine-tuning setting, a different readout module is trained from scratch, and GNN’s parameters are fine-tuned at the same time.

Original:   Conclusion and Future Work
Revised: • For evaluation & fine-tuning , LHNN and Ours are only trained for 1/5 epochs of default setting, to show the transferability of learned features. [Table] The results show that the knowledge Circuit GNN learns from Congestion Prediction can be easily transferred to another task (no matter for direct use or fine-tuning), while LHNN is weak in transferability.  Conclusion and Future Work

Original: We present a versatile graph neural network to facilitate EDA circuit design process.
Revised: We present a versatile graph neural network to facilitate EDA circuit design process.

Original: To this end, wedesign a heterogeneous graph, Circuit Graph, to integrate topological and geometrical informationinto a unified data structure, based on which we further propose a message-passing and fusionapproach named Circuit GNN.
Revised: To this end, we design a heterogeneous graph, Circuit Graph, to integrate topological and geometrical information into a unified data structure, based on which we further propose a message-passing and fusion approach named Circuit GNN.

Original: It is the first circuit representation method applied to multiple EDAtasks and stages.
Revised: It is the first circuit representation method applied to multiple EDA tasks and stages.

Original: By integrating multi-source information, Circuit Graph outperforms previousmethods in prediction performance and computation time.
Revised: By integrating multi-source information, Circuit Graph outperforms previous methods in prediction performance and computation time.

Original: Our work further supports the EDAprocess “shift-left”, a new future direction that aims to speed-up circuit design by deeply combiningartificial intelligence in all EDA tool chains.
Revised: Our work further supports the EDA process “shift-left”, a new future direction that aims to speed-up circuit design by deeply combining artificial intelligence in all EDA tool chains.

Original: Limitations Although AI for EDA becomes a hot research topic recently and some deep learningdriven techniques have been adopted in the main-stream EDA tools (Cadence, Synopsys, etc.), thereis still a gap between the novel machine learning algorithms and their application in commercial tools.
Revised: Limitations Although AI for EDA becomes a hot research topic recently and some deep learningdriven techniques have been adopted in the main-stream EDA tools (Cadence, Synopsys, etc.), there is still a gap between the novel machine learning algorithms and their application in commercial tools.

Original: Moreover, in early EDA stages, other circuit representations like data-flow graph or And-Inverter
Revised: Moreover, in early EDA stages, other circuit representations like data-flow graph or And-Inverter

Original: Graph (AIG) graph might be used.
Revised: Graph (AIG) graph might be used.

Original: As the meaning of nodes and edges in these graphs are differentfrom netlist graph used in the paper, our method might not apply to these graphs in early EDA stages.
Revised: As the meaning of nodes and edges in these graphs are different from netlist graph used in the paper, our method might not apply to these graphs in early EDA stages.

Original: Societal Impact.
Revised: Societal Impact.

Original: Our solution explores dual-stage circuit representation to serve various EDAdownstream tasks, which have limited societal impact.
Revised: Our solution explores dual-stage circuit representation to serve various EDA downstream tasks, which have limited societal impact.

Original: Whatever, there is a minimal possibility ofmisuse that violate some ethics of life science.
Revised: Whatever, there is a minimal possibility of misuse that violate some ethics of life science.

Original: Checklist
Revised: Checklist

Original: For all authors... (a) Do the main claims made in the abstract and introduction accurately reflect the paper’s contributions and scope?
Revised: For all authors... (a) Do the main claims made in the abstract and introduction accurately reflect the paper’s contributions and scope?

Original: [Yes] (b) Did you describe the limitations of your work?
Revised: [Yes] (b) Did you describe the limitations of your work?

Original: [Yes]
Revised: [Yes]

Original: In section 6 Limitations .(c)
Revised: In section 6 Limitations .

Original:  Did you discuss any potential negative societal impacts of your work?
Revised: (c) Did you discuss any potential negative societal impacts of your work?

Original: [Yes] In section6 Societal Impact .(d)
Revised: [Yes] In section 6 Societal Impact .

Original:  Have you read the ethics review guidelines and ensured that your paper conforms tothem?
Revised: (d) Have you read the ethics review guidelines and ensured that your paper conforms to them?

Original: [Yes]2.
Revised: [Yes] 2.

Original: If you are including theoretical results... (a) Did you state the full set of assumptions of all theoretical results?
Revised: If you are including theoretical results... (a) Did you state the full set of assumptions of all theoretical results?

Original: [N/A] (b) Did you include complete proofs of all theoretical results?
Revised: [N/A] (b) Did you include complete proofs of all theoretical results?

Original: [Yes] In appendix B.23.
Revised: [Yes] In appendix B. 3.

Original: If you ran experiments... (a) Did you include the code, data, and instructions needed to reproduce the main experi- mental results (either in the supplemental material or as a URL)?
Revised: If you ran experiments... (a) Did you include the code, data, and instructions needed to reproduce the main experimental results (either in the supplemental material or as a URL)?

Original: [Yes] see the hyper links in experiment and supplemental material (b) Did you specify all the training details (e
Revised: [Yes] see the hyper links in experiment and supplemental material (b) Did you specify all the training details (e

Original: g., data splits, hyperparameters, how theywere chosen)?
Revised: g., data splits, hyperparameters, how they were chosen)?

Original: [Yes](c) Did you report error bars (e
Revised: [Yes] (c) Did you report error bars (e

Original: g., with respect to the random seed after running experiments multiple times)?
Revised: g., with respect to the random seed after running experiments multiple times)?

Original: [No] The datasets are so big (contain million of samples) that running on multiple data splits with different random seeds is not necessary.
Revised: [No] The datasets are so big (contain million of samples) that running on multiple data splits with different random seeds is not necessary.

Original: (d) Did you include the total amount of compute and the type of resources used (e g., typeof GPUs, internal cluster, or cloud provider)?
Revised: (d) Did you include the total amount of compute and the type of resources used (e.g., type of GPUs, internal cluster, or cloud provider)?

Original: [Yes] on NVIDIA RTX
Revised: [Yes] on NVIDIA RTX4.

Original: If you are using existing assets (e g., code, data, models) or curating/releasing new assets...
Revised: If you are using existing assets (e.g., code, data, models) or curating/releasing new assets...

Original: (a) If your work uses existing assets, did you cite the creators?
Revised: (a) If your work uses existing assets, did you cite the creators?

Original: [Yes] see Section 5.
Revised: [Yes] see Section 5.

Original: (b) Did you mention the license of the assets?
Revised: (b) Did you mention the license of the assets?

Original: [N/A] (c) Did you include any new assets either in the supplemental material or as a URL?
Revised: [N/A] (c) Did you include any new assets either in the supplemental material or as a URL?

Original: [N/A] d) Did you discuss whether and how consent was obtained from people whose data you’re using/curating?
Revised: [N/A] (d) Did you discuss whether and how consent was obtained from people whose data you’re using/curating?

Original: [Yes] from GitHub limbo018/DREAMPlace (e) Did you discuss whether the data you are using/curating contains personally identifiable information or offensive content?
Revised: [Yes] from GitHub limbo018/DREAMPlace (e) Did you discuss whether the data you are using/curating contains personally identifiable information or offensive content?

Original: [Yes] no such content inside our data 
Revised: [Yes] no such content inside our data 5.

Original: If you used crowdsourcing or conducted research with human subjects... (a) Did you include the full text of instructions given to participants and screenshots, if applicable?
Revised: If you used crowdsourcing or conducted research with human subjects... (a) Did you include the full text of instructions given to participants and screenshots, if applicable?

Original: [N/A] (b) Did you describe any potential participant risks, with links to Institutional Review Board (IRB) approvals, if applicable?
Revised: [N/A] (b) Did you describe any potential participant risks, with links to Institutional Review Board (IRB) approvals, if applicable?

Original: [N/A] (c) Did you include the estimated hourly wage paid to participants and the total amount spent on participant compensation?
Revised: [N/A] (c) Did you include the estimated hourly wage paid to participants and the total amount spent on participant compensation?

Original: [N/A]
Revised: [N/A]

Original: A Featurization
Revised: A Featurization

Original: The featurization of grid , cell , net and pin is shown in Tab.4/5/6/7.
Revised: The featurization of grid , cell , net and pin is shown in Tab.5/6/7/8.

Original: [Table]
Revised: [Table]

Original: [Table]
Revised: [Table]

Original: When conducting experiments on circuits in placement stage, grid features in Tab.4 are borrowed tosupply node features by assigning each node with the features of the grid it’s located in.
Revised: When conducting experiments on circuits in placement stage [Table] grid features in Tab.5 are borrowed to supply node features by assigning each node with the features of the grid it’s located in

Original: [Table]
Revised: [Table]

Original: Note that the feature span

Original: [Table]
Revised: [Table]

Original: only available
Revised: and vertically

Original: [Table]
Revised: [Table]

Original: placement stage.

Original: [Table]
Revised: [Table]

Revised: Note that the feature span is only available in placement stage.

Original: [Table]
Revised: [Table]

Revised: and vertically) signal direction 0/ this pin input/output signal to the cell

Original: B Graphization of Circuit Design 
Revised: B Graphization of Circuit Design B.1 Graphize Geometrical Information

Original: B.1 Graphize Geometrical Information

Original: For circuit designs in placement stage, a universal solution of graphizing geometry is to link thecell -pairs whose distances are lower than a threshold δ [27]:
Revised: For circuit designs in placement stage, a universal solution of graphizing geometry is to link the cell -pairs whose distances are lower than a threshold δ [27]:

Original: [Equation]
Revised: [Equation]

Original: (10) where ( (cid:101) px
Revised: where ( (cid:101) p

Original:  [ i ] , (cid:101) p y
Revised: x [ i ] , (cid:101) p y

Original: [ i ]) is the position of i -th cell ’s center, and s x , s y are the width/height of cells .
Revised: [ i ]) is the position of i -th cell ’s center, and s x , s y are the width/height of cells .

Original: However, the time cost of this solution is O ( |V| 2 ) and makes it unpractical for very large circuitswith millions of cells and nets .
Revised: However, the time cost of this solution is O ( |V| 2 ) and makes it unpractical for very large circuits with millions of cells and nets .

Original: To accelerate the geometry graphization, we cut the circuit into windows with size ( w x , w y ) , scatterthe cells into the windows and link the cells appearing in the same window, as it shows in Fig.7.
Revised: To accelerate the geometry graphization, we cut the circuit into windows with size ( w x , w y ) , scatter the cells into the windows and link the cells appearing in the same window, as it shows in Fig.7.

Original: Notethat every cell has its 2D structure and may appear in multiple windows e.g. cell 4 in Fig.7(b). 
Revised: Note that every cell has its 2D structure and may appear in multiple windows e.g. cell 4 in Fig.7(b). [Figure]

Original:  However, it is still possible that two adjacent cells are incidentally split into different windows andcan’t get linked e.g. cell 2 and 3 in Fig.7(b).
Revised: [Figure] However, it is still possible that two adjacent cells are incidentally split into different windows and can’t get linked e.g. cell 2 and 3 in Fig.7(b).

Original: To avoid this, we shift the windows by w x / 2 horizontallyor w y / 2 vertically and add new links (see Fig.7(c)(d)(e)).
Revised: To avoid this, we shift the windows by w x / 2 horizontally or w y / 2 vertically and add new links (see Fig.7(c)(d)(e)).

Original: Finally, as it shows in Fig.7(f), we getgeom-edges E G :[Figure]
Revised: Finally, as it shows in Fig.7(f), we get geom-edges E G :

Original: Link the cells appearing in the same

Original: [Figure]

Original: [Figure]

Original: E

Original: [Equation]
Revised: [Equation]

Original: E G is actually a sampling of the cell -pairs with distance lower than δ = (cid:113) w 2 x + w 2 y , and the possibilityof being sampled is inversely proportional to their distance.
Revised: E G is actually a sampling of the cell -pairs with distance lower than δ = (cid:113) w 2 x + w 2 y , and the possibility of being sampled is inversely proportional to their distance.

Original: However, the time consumption ofconstructing E G is still O ( |V| 2 / |W| ) 4 .
Revised: However, the time consumption of constructing E G is still O ( |V| 2 / |W| ) 5 .

Original: To further lower the consumption, for every cell i , we onlylink it to at most c others appearing in the same window and produce an E ∗ G ⊆
Revised: To further lower the consumption, for every cell i , we only link it to at most c others appearing in the same window and produce an E ∗ G ⊆

Original: E G to substitute E G .
Revised: E G to substitute E G .

Original: As c is a constant, the time cost of constructing E ∗ G is O ( |V| ) (see proof in Appendix.
Revised: As c is a constant, the time cost of constructing E ∗ G is O ( |V| ) (see proof in Appendix.

Original: B.2).
Revised: B.2).

Original: To furtherenhance the information in geom-edges , we store the cell -pair distances as raw features in E G .
Revised: To further enhance the information in geom-edges , we store the cell -pair distances as raw features in E G .

Original: To show the robustness of our geometry graphization method, we test the sensitivity of window size( w x , w y ) and link capacity c in Sec.
Revised: To show the robustness of our geometry graphization method, we test the sensitivity of window size ( w x , w y ) and link capacity c in Sec.

Original: C
Revised: C

Original: B.2 Time Consumption
Revised: B.2 Time Consumption

Original: Inside a circuit design, despite of several “macros” occupying the margins (see Fig.5a for example),most cells are not big enough to appear in multiple windows in Fig.7, and they are normallydistributed to the windows to avoid placement conflicts [2].
Revised: Inside a circuit design, despite of several “macros” occupying the margins (see Fig.5a for example), most cells are not big enough to appear in multiple windows in Fig.7, and they are normally distributed to the windows to avoid placement conflicts [2].

Original: Therefore, we assume that the averagenumber of cells appear in a window is |V| / |W| .
Revised: Therefore, we assume that the average number of cells appear in a window is |V| / |W| .

Original: The time consumption of constructing E ∗ G is4 |W| · ( |V||W| 
Revised: The time consumption of constructing E ∗ G is 4 |W| · ( |V||W| · c )

Original: [Equation]{+= 
+}
Revised: {+= 
+}

Original:  Moreover, the time costs of constructing V , U , E T are O ( |V| ) , O ( |U| ) , O ( |P| ) respectively, so wecan produce circuit graph G in O ( |V| + |U| + |P| ) .
Revised: c |V| = O ( |V| ) . Moreover, the time costs of constructing V , U , E T are O ( |V| ) , O ( |U| ) , O ( |P| ) respectively, so we can produce circuit graph G in O ( |V| + |U| + |P| ) .

Original: C Parameter Sensitivity Experiment
Revised: C Parameter Sensitivity Experiment

Original: [Table] [Table]
Revised: [Table] [Table]

Original: We test the sensitivity of window size ( w x , w y ) and link capacity c , as it shows in Tab.8 and Tab.9.
Revised: We test the sensitivity of window size ( w x , w y ) and link capacity c , as it shows in Tab.9 and Tab.10.

Original: The results indicate that the choice of these hyper-parameters has little influence on the model’s function, so the robustness of Circuit GNN is claimed.
Revised: The results indicate that the choice of these hyper-parameters has little influence on the model’s function, so the robustness of Circuit GNN is claimed.

Original: D Model Sensitivity Experiment 
Revised: D Model Sensitivity Experiment D.1 Message Function

Original: [Table] D.1 Message Function

Revised: The choice of Φ V E T

Original: [Table]
Revised: [Equation]

Original: The choice
Revised: U

Original: [Table]
Revised: [Equation]

Original: andΦ
Revised: and

Original: [Table]
Revised: [Equation]

Original: On the one hand, there are usually more geom-edges thantopo-edges in Circuit Graph (3.4M geom-edges and 1.9M topo-edges in superblue19 ), so we useedge-weight summation rather than inner product, which is F U (hidden dimension of net) timesmore expansive in computation.
Revised: On the one hand, there are usually more geom-edges than topo-edges in Circuit Graph (3.4M geom-edges and 1.9M topo-edges in superblue19 ), so we use edge-weight summation rather than inner product, which is F U (hidden dimension of net) times more expansive in computation.

Original: On the other hand, it is also reasonable for geom-edges to useedge-weight summation because geometrically closer cells have a stronger relationship.
Revised: On the other hand, it is also reasonable for geom-edges to use edge-weight summation because geometrically closer cells have a stronger relationship.

Original: Still, we testthe performance when topo-edges use edge-weight summation ( topo.
Revised: Still, we test the performance when topo-edges use edge-weight summation ( topo.

Original: e. ) or geom-edges use innerproduct ( geom.
Revised: e. ) or geom-edges use inner product ( geom.

Original: i. ):
Revised: i. ):

Original: [Table]
Revised: [Table]

Original: D.2 Information Fusing Strategy
Revised: D.2 Information Fusing Strategy

Original: We hope to keep most of the informative values when fusing the topological and geometricalinformation, while sum-pooling and mean-pooling may revise them.
Revised: We hope to keep most of the informative values when fusing the topological and geometrical information, while sum-pooling and mean-pooling may revise them.

Original: Concatenation is not consideredbecause we hope to keep the same hidden dimension in each layer.
Revised: Concatenation is not considered because we hope to keep the same hidden dimension in each layer.

Original: The results below show that using sum-pooling and mean-pooling has worse spearman & kendall (Grid-level) and only marginalimprovement in other metrics:
Revised: The results below show that using sum-pooling and mean-pooling has worse spearman & kendall (Grid-level) and only marginal improvement in other metrics:

Original: [Table]
Revised: [Table]

Revised: D.3 Readout Representation

Original: We concatenate the raw features to enrich the representations.
Revised: We concatenate the raw features to enrich the representations.

Original: The results below show that excludingraw features only causes a marginal performance drop:
Revised: The results below show that excluding raw features only causes a marginal performance drop:

Original: [Table]
Revised: [Table]

Revised: D.4 Position Encoding

Original: Directly encoding the cell positions as features leads to very bad generalization because raw 3Dpositions do not satisfy translation and rotation invariances[28].
Revised: Directly encoding the cell positions as features leads to very bad generalization because raw 3D positions do not satisfy translation and rotation invariances[28].

Original: Here are the results: ( Ours (pos.encode) is the modification we made which encodes the cell positions into node features instead ofusing geom-edges .)
Revised: Here are the results: ( Ours (pos. encode) is the modification we made which encodes the cell positions into node features instead of using geom-edges .)

Original: [Table]
Revised: [Table]

Original: E Additional Experiment Tables
Revised: E Additional Experiment Tables

Original: [Table] [Table]
Revised: [Table] [Table]

Original: F Number of Parameters and Inference Time
Revised: F Number of Parameters and Inference Time

Original: The # of parameters and inference time on superblue19 are listed below:[Table] [Table] [Table]
Revised: The # of parameters and inference time on superblue19 are listed below:

Original: prediction in placement stage.

Original: [Table]

Original: When working on superblue19 , DREAMPlace spends around 285s to output congestion and wirelength from netlist input, where it takes 226.2s to produce placement result of superblue19 , 55.2s tooutput congestion and 3.63 to calculate wirelength, respectively.

Original: G Transfer Experiment

Original: To further evaluate the representativeness of extracted GNN features, we first train Circuit

Original: GNN/LHNN with Congestion Prediction task and then evaluate/fine-tune them with Wirelength

Original: Prediction.

Original: Here are the experimental settings:

Original: • For the evaluation setting, a different readout module is trained from scratch, but GNN’s

Original: [Table]
Revised: [Table]

Original: parameters are fixed.

Original: [Table]
Revised: [Table]

Original: • For the fine-tuning setting, a different readout module is trained from scratch, and GNN’s

Original: [Table]
Revised: [Table]

Original: parameters are fine-tuned at the same time.

Original: [Table]
Revised: [Table]

Original: • For evaluation & fine-tuning , LHNN and Ours are only trained for 1/5 epochs of default [Table] setting, to show the transferability of learned features. [Table]
Revised: When working on superblue19 , DREAMPlace spends around 285s to output congestion and wirelength from netlist input, where it takes 226.2s to produce placement result of superblue19 , 55.2s to output congestion and 3.63 to calculate wirelength, respectively.

Original: The results show that the knowledge Circuit GNN learns from Congestion Prediction can be easily transferred to another task (no matter for direct use or fine-tuning), while LHNN is weak intransferability.