PATENT DOCUMENT

Publication Number: US-9379092-B2
Application Number: US-201514931680-A
Country: US
Kind Code: B2

Title: Micro device with stabilization post

Abstract:
A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of stabilization posts. Each stabilization cavity includes sidewalls surrounding a stabilization post. The array of micro devices is on the array of stabilization posts. Each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Claims:
What is claimed is: 
     
       1. A structure comprising:
 a stabilization layer comprising an array of stabilization cavities and an array of stabilization posts, wherein each stabilization cavity includes a stabilization post and sidewalls that surround and are taller than a corresponding stabilization post; and 
 an array of light emitting diodes (LEDs) on the array of stabilization posts; 
 wherein each LED in the array of LEDs includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. 
 
     
     
       2. The structure of  claim 1 , further comprising a sacrificial layer between the stabilization layer and the array of LEDs, wherein the array of stabilization posts extend through a thickness of the sacrificial layer, and wherein the sacrificial layer spans along a side surface of each of the LEDs in the array of LEDs, the side surface running between a top surface and the bottom surface of each LED in the array. 
     
     
       3. The structure of  claim 2 , wherein the sacrificial layer comprises an oxide or nitride. 
     
     
       4. The structure of  claim 1 , further comprising an array of bottom conductive contacts on the bottom surfaces of the array of LEDs. 
     
     
       5. The structure of  claim 4 , wherein each stabilization post includes a top surface contact area that is less than a bottom surface contact area of a corresponding bottom conductive contact. 
     
     
       6. The structure of  claim 4 , wherein each stabilization post top surface is characterized by a length and a width. 
     
     
       7. The structure of  claim 4 , wherein each stabilization post top surface is characterized by an equal length and width. 
     
     
       8. The structure of  claim 4 , wherein each bottom conductive contact comprises a layer stack. 
     
     
       9. The structure of  claim 8 , wherein the layer stack comprises:
 an electrode layer; 
 a mirror layer on the electrode layer; 
 a barrier layer on the mirror layer; 
 a diffusion barrier layer on the barrier layer; and 
 a bonding layer on the diffusion barrier layer. 
 
     
     
       10. The structure of  claim 8 , wherein the layer stack comprises:
 an electrode layer comprising nickel; 
 a mirror layer comprising silver on the electrode layer; 
 a barrier layer comprising titanium on the mirror layer; 
 a diffusion barrier layer comprising platinum on the barrier layer; and 
 a bonding layer comprising a noble metal on the diffusion barrier layer. 
 
     
     
       11. The structure of  claim 8 , wherein the layer stack comprises a bonding layer, and the bonding layer comprises a noble metal. 
     
     
       12. The structure of  claim 11 , wherein the stabilization layer is formed of a thermoset material. 
     
     
       13. The structure of  claim 12 , wherein the thermoset material comprises benzocyclobutene (BCB), and the noble metal is gold. 
     
     
       14. The structure of  claim 8 , wherein the layer stack further comprises:
 an electrode layer on the bottom surface of the LED; and 
 a diffusion barrier layer on and around sidewalls the electrode layer; 
 wherein the bonding layer is on the diffusion barrier layer. 
 
     
     
       15. The structure of  claim 14 , wherein the stabilization layer is formed of a thermoset material, and the bonding layer comprises a noble metal. 
     
     
       16. The structure of  claim 1 , wherein the stabilization posts in the array of stabilization posts are separated by a pitch of 1 μm to 100 μm. 
     
     
       17. The structure of  claim 1 , wherein the stabilization posts in the array of stabilization posts are separated by a pitch of 1 μm to 10 μm. 
     
     
       18. The structure of  claim 1 , wherein each LED includes a top surface that is above a corresponding staging cavity sidewalls top surface.

Description:
RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 14/681,715, filed Apr. 8, 2015, which is a divisional of U.S. patent application Ser. No. 13/937,000, filed Jul. 8, 2013, now U.S. Pat. No. 9,035,279, the full disclosure of which is incorporated herein by reference. 
    
    
     BACKGROUND 
     1. Field 
     The present invention relates to micro devices. More particularly embodiments of the present invention relate to the stabilization of micro devices on a carrier substrate. 
     2. Background Information 
     Commercial manufacturing and packaging of micro devices often becomes more challenging as the scale of the micro devices decreases. Some examples of micro devices include radio frequency (RF) microelectromechanical systems (MEMS) microswitches, light-emitting diode (LED) display systems, and MEMS or quartz-based oscillators. 
     One implementation for transferring devices includes peeling devices from an adhesive sheet using a vacuum nozzle that is included in a mounting head. Once the device is picked up by the vacuum pressure, it can be moved by the mounting head to a receiving substrate. A camera may image the receiving substrate to assist the system in placing the device on the receiving substrate. When the mounting head is positioned in the desired location above the receiving substrate, the vacuum pressure can be adjusted to allow the device to stay positioned on the receiving substrate while the mounting head moves away from the receiving substrate. 
     In another implementation, devices are formed on an adhesive layer that is partially removed using a solvent. This results in only a bridging portion of the adhesive layer connecting the device to a host substrate. To prepare the devices for removal from the substrate, a patterned elastomeric transfer stamp can be selectively applied in order to fracture the bridging portions of the adhesive layer and transfer the devices from the host substrate. 
     SUMMARY OF THE INVENTION 
     A structure and method of forming an array of micro devices which are poised for pick up are disclosed. In an embodiment, a structure includes a stabilization layer including an array of stabilization posts, and the stabilization layer is formed of a thermoset material such as epoxy or benzocyclobutene (BCB) which is associated with 10% or less volume shrinkage during curing, or more particularly about 6% or less volume shrinkage during curing. An array of micro devices are on the array of stabilization posts. Each micro device may include a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. An array of bottom conductive contacts may be formed on the bottom surfaces of the array micro devices. An array of top conductive contacts may be formed on top of the array of micro devices. In an embodiment the array of stabilization posts are separated by a pitch of 1 μm to 100 μm, or more specifically 1 μm to 10 μm. 
     The stabilization layer may be bonded to a carrier substrate. The stabilization layer may have an array of stabilization cavities having stabilization cavity sidewalls surrounding the stabilization posts. An adhesion promoter layer may be formed between the carrier substrate and the stabilization layer to increase adhesion. A sacrificial layer may also be located between the stabilization layer and the array of micro devices, where the array of stabilization posts also extend through a thickness of the sacrificial layer. In an embodiment, the sacrificial layer is formed of a material such as an oxide or nitride. An adhesion promoter layer may also be formed between the stabilization layer and the sacrificial layer to increase adhesion, where the array of stabilization posts also extend through a thickness of the adhesion promoter layer. Each stabilization post may be x-y centered below a corresponding micro device or may be off-centered with respect to the corresponding micro devices. 
     The array of micro devices may be micro LED devices, and may be designed to emit a specific wavelength such as a red, green, or blue light. In an embodiment, each micro LED device includes a device layer formed of a p-doped semiconductor layer, one or more quantum well layers over the p-doped semiconductor layer, and an n-doped semiconductor layer. For example, where the micro LED device is designed to emit a green or blue light, the p-doped layer may comprise GaN and the n-doped layer may also comprise GaN. 
     One embodiment includes patterning a device layer to form an array of micro device mesa structures over a handle substrate, forming a patterned sacrificial layer including an array of openings over the corresponding array of micro device mesa structures, forming a stabilization layer over the patterned sacrificial layer and within the array of openings, and removing the handle substrate. The stabilization layer may be bonded to a carrier substrate prior to removing the handle substrate. Bonding the stabilization layer to the carrier substrate may include curing. The stabilization layer may be formed of a thermoset material, which may be BCB in one embodiment. 
     In an embodiment, the array of openings are formed directly over an array of conductive contacts of the corresponding array of micro device mesa structures. In an embodiment, patterning the device layer to form the array of micro device mesa structures leaves unremoved portions of the device layer between the array of micro device mesa structures, and the unremoved portions of the device layer are subsequently removed to form laterally separate micro LED devices. Removing the unremoved portions of the device layer may include thinning the array of micro device mesa structures so that an exposed top surface of the array of micro LED devices is below an exposed top surface of the patterned sacrificial layer between the micro LED devices. The patterned sacrificial layer is removed to form an open space below and around each micro device, in an embodiment. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a cross-sectional side view illustration of a bulk LED substrate in accordance with an embodiment of the invention. 
         FIG. 1B  is a cross-sectional side view illustration of a device wafer including circuitry in accordance with an embodiment of the invention. 
         FIG. 2A  is a cross-sectional side view illustration of a patterned conductive contact layer on a bulk LED substrate in accordance with an embodiment of the invention. 
         FIG. 2B  is a cross-sectional side view illustration of a patterned conductive contact layer on a bulk LED substrate in accordance with an embodiment of the invention. 
         FIG. 3  is a cross-sectional side view illustration of a device layer patterned to form an array of micro device mesa structures over a handle substrate in accordance with an embodiment of the invention. 
         FIG. 4  is a cross-sectional side view illustration of an adhesion promoter layer and a sacrificial layer including an array of openings formed over an array of micro device mesa structures in accordance with an embodiment of the invention. 
         FIG. 5  is a cross-sectional side view illustration of a stabilization layer formed over an adhesion promoter layer and a sacrificial layer and within an array of openings included in the sacrificial layer in accordance with an embodiment of the invention. 
         FIG. 6  is a cross-sectional side view illustration of bringing together a carrier substrate and micro device mesa structures formed on a handle substrate in accordance with an embodiment of the invention. 
         FIG. 7  is a cross-sectional side view illustration of the removal of a growth substrate in accordance with an embodiment of the invention. 
         FIG. 8  is a cross-sectional side view illustration of the removal of an epitaxial growth layer and a portion of a device layer in accordance with an embodiment of the invention. 
         FIGS. 9A-9B  are cross-sectional side view illustrations of patterned conductive contacts formed over an array of laterally separate micro devices in accordance with an embodiment of the invention. 
         FIG. 10A  is a cross-sectional side view illustration of an array of micro devices formed on array of stabilization posts after removal of a sacrificial layer in accordance with an embodiment of the invention. 
         FIGS. 10B-10C  are schematic top view illustrations of example stabilization post locations relative to a group of micro devices in accordance with an embodiment of the invention. 
         FIGS. 11A-11E  are cross-sectional side view illustrations of an array of electrostatic transfer heads transferring micro devices from a carrier substrate to a receiving substrate in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the present invention describe a method and structure for stabilizing an array of micro devices such as micro light emitting diode (LED) devices and micro chips on a carrier substrate so that they are poised for pick up and transfer to a receiving substrate. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with metal redistribution lines. While embodiments of some of the present invention are described with specific regard to micro LED devices comprising p-n diodes, it is to be appreciated that embodiments of the invention are not so limited and that certain embodiments may also be applicable to other micro semiconductor devices which are designed in such a way so as to perform in a controlled fashion a predetermined electronic function (e.g. diode, transistor, integrated circuit) or photonic function (LED, laser). Other embodiments of the present invention are described with specific regard to micro devices including circuitry. For example, the micro devices may be based on silicon or SOI wafers for logic or memory applications, or based on GaAs wafers for RF communications applications. 
     In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to “one embodiment,” “an embodiment” or the like means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in one embodiment,” “an embodiment” or the like in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. 
     The terms “over”, “spanning”, “to”, “between”, and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over”, “spanning”, or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers. 
     The terms “micro” device, “micro” LED device, or “micro” chip as used herein may refer to the descriptive size of certain devices, devices, or structures in accordance with embodiments of the invention. As used herein the term “micro device” specifically includes “micro LED device” and “micro chip”. As used herein, the terms “micro” devices or structures are meant to refer to the scale of 1 to 100 μm. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller size scales. In an embodiment, a single micro device in an array of micro devices, and a single electrostatic transfer head in an array of electrostatic transfer heads both have a maximum dimension, for example length or width, of 1 to 100 μm. In an embodiment, the top contact surface of each micro device or electrostatic transfer head has a maximum dimension of 1 to 100 μm, or more specifically 3 to 20 μm. In an embodiment, a pitch of an array of micro devices, and a corresponding array of electrostatic transfer heads is (1 to 100 μm) by (1 to 100 μm), for example a 20 μm by 20 μm pitch or 5 μm by 5 μm pitch. 
     In the following embodiments, the mass transfer of an array of pre-fabricated micro devices with an array of transfer heads is described. For example, the pre-fabricated micro devices may have a specific functionality such as, but not limited to, an LED for light-emission, silicon IC for logic and memory, and gallium arsenide (GaAs) circuits for radio frequency (RF) communications. In some embodiments, arrays of micro LED devices which are poised for pick up are described as having a 20 μm by 20 μm pitch, or 5 μm by 5 μm pitch. At these densities, a 6 inch substrate, for example, can accommodate approximately 165 million micro LED devices with a 10 μm by 10 μm pitch, or approximately 660 million micro LED devices with a 5 μm by 5 μm pitch. A transfer tool including an array of transfer heads matching an integer multiple of the pitch of the corresponding array of micro LED devices can be used to pick up and transfer the array of micro LED devices to a receiving substrate. In this manner, it is possible to integrate and assemble micro LED devices into heterogeneously integrated systems, including substrates of any size ranging from micro displays to large area displays, and at high transfer rates. For example, a 1 cm by 1 cm array of micro device transfer heads can pick up and transfer more than 100,000 micro devices, with larger arrays of micro device transfer heads being capable of transferring more micro devices. 
     In one aspect, embodiments of the invention describe a structure for stabilizing an array of micro devices such as micro light emitting diode (LED) devices on a carrier substrate so that they are poised for pick up and transfer to a receiving substrate. In an embodiment, an array of micro devices are held in place on an array of stabilization posts on a carrier substrate. In an embodiment, the stabilization posts are formed of an adhesive bonding material. In this manner, the array of stabilization posts may retain the array of micro devices in place on a carrier substrate while also providing a structure from which the array of micro devices are readily picked up. In an embodiment, the adhesive bonding material includes a thermoset material such as, but not limited to, benzocyclobutene (BCB) or epoxy. In an embodiment, the thermoset material may be associated with 10% or less volume shrinkage during curing, or more particularly about 6% or less volume shrinkage during curing. In this manner low volume shrinkage during curing of the adhesive bonding material may not cause delamination between the array of stabilization posts and the array of micro devices, and may allow for uniform adhesion between the array stabilization posts and the array of micro devices supported by the array of stabilization posts. In one aspect, the adhesive bonding material (e.g. BCB) forms stabilization cavity sidewalls that are advantageously positioned to contain micro device within a stabilization cavity formed by the sidewall. In this respect, even if a micro device loses adherence to a stabilization post, it may still be poised for pick up because it is still positioned within an acceptable tolerance (defined by the stabilization cavity) to be transferred to a receiving substrate. 
     In one aspect of embodiments of the invention, the array of micro devices are formed in a one sided process sequence in which a device layer is etched to form an array of micro device mesa structures prior to applying a stabilization layer (the stabilization layer having the adhesive bonding material that forms the stabilization posts). A one sided process sequence is distinguishable from a two sided process sequence, which is characterized by etching mesa structures in the device layer after bonding to a stabilization layer. Suitability of a one sided process or two sided process may depend upon the system requirement, and materials being used. For example, where the micro devices are micro LED devices, the devices layers may be formed from different materials selected for different emission spectra. By way of example, a red-emitting micro LED device may be formed of a GaP (5.45 Å lattice constant) based material grown on a GaAs substrate (5.65 Å lattice constant). By way of comparison, a blue-emitting or green-emitting micro LED device may be formed of a GaN (5.18 Å lattice constant) based material grown on a sapphire substrate (4.76 Å lattice constant). It has been observed that when fabricating devices at the “micro” scale in accordance with the embodiments of the invention, that the stored energy in the form of stress in the device layer, typically grown by heterogenous growth techniques on a lattice-mismatched growth substrate, that stressed device layer may shift upon removal of the growth substrate, potentially causing misalignment between the array of micro devices that are formed over the array of stabilization posts. In accordance with embodiments of the invention, and in particular when lattice mismatch between the device layer and growth substrate is greater than 0.2 Å, a one sided process sequence is performed in order to reduce the amount of shifting between the micro devices and stabilization posts by forming micro device mesa structures on stabilization posts prior to removing the growth substrate. 
     Without being limited to a particular theory, embodiments of the invention utilize transfer heads and head arrays which operate in accordance with principles of electrostatic grippers, using the attraction of opposite charges to pick up micro devices. In accordance with embodiments of the present invention, a pull-in voltage is applied to a transfer head in order to generate a grip pressure on a micro device and pick up the micro device. In accordance with embodiments of the invention, the minimum amount pick up pressure required to pick up a micro device from a stabilization post can be determined by the adhesion strength between the adhesive bonding material from which the stabilization posts are formed and the micro device (or any intermediate layer), as well as the contact area between the top surface of the stabilization post and the micro device. For example, adhesion strength which must be overcome to pick up a micro device is related to the minimum pick up pressure generated by a transfer head as provided in equation (1):
 
 P   1   A   1   =P   2   A   2   (1)
 
where P 1  is the minimum grip pressure required to be generated by a transfer head, A 1  is the contact area between a transfer head contact surface and micro device contact surface, A 2  is the contact area on a top surface of a stabilization post, and P 2  is the adhesion strength on the top surface of a stabilization post. In an embodiment, a grip pressure of greater than 1 atmosphere is generated by a transfer head. For example, each transfer head may generate a grip pressure of 2 atmospheres or greater, or even 20 atmospheres or greater without shorting due to dielectric breakdown of the transfer heads. Due to the smaller area, a higher pressure is realized at the top surface of the corresponding stabilization post than the grip pressure generate by a transfer head. In an embodiment, a bonding layer is placed between each micro device and stabilization post in order to aid in bonding each micro device to a receiving substrate. A variety of different bonding layers with different melting temperatures are compatible with embodiments of the invention. For example, heat may or may not be applied to the transfer head assembly, carrier substrate, and/or receiving substrate during the pick up, transfer, and bonding operations. In some embodiments, the bonding layer may be a comparatively higher melting temperature material such as gold. In some embodiments the bonding layer is a comparatively lower melting temperature material such as indium. In some embodiments, the transfer head assembly may be maintained at an elevated temperature during the pick up and transfer operations in order to assist bonding to the receiving substrate without thermal cycling of the transfer head assembly. In one embodiment, the bonding layer is gold, and the bonding layer is not liquefied during the pick up or transfer operations. In one embodiment the bonding layer is indium, and the bonding layer is liquefied during the pick up and transfer operations. In such an embodiment, the bonding layer may be partially picked up and transferred to the receiving substrate.
 
     In another embodiment, the bonding layer is formed of a material characterized by a low tensile strength. For example, indium is characterized by a tensile strength of approximately 4 MPa which can be less than or near the adhesion strength between a gold/BCB bonding interface of 10 MPa or less, and which is significantly lower than an exemplary 30 MPa adhesion strength between a gold/BCB bonding interface (determined with stud pull test) when treated with adhesion promoter AP3000, an organosilane compound in 1-methoxy-2-propoanol available from The Dow Chemical Company. In an embodiment, the bonding layer is cleaved during the pick up operation due to the lower tensile strength, and a phase change is not created curing the pick up operation. Though, a phase change may still be created in the portion of the bonding layer which is picked up with the micro device during placement of the micro device onto a receiving substrate to aid in bonding of the micro device to the receiving substrate. 
     In another aspect, embodiments of the invention describe a manner of forming an array of micro devices which are poised for pick up in which conductive contact layers can be formed on top and bottom surfaces of the micro devices, and annealed to provide ohmic contacts. Where a conductive contact is formed on a top surface of a micro device, the stabilization layer is formed of a material which is capable of withstanding the associated deposition and annealing temperatures. For example, a conductive contact may require annealing at temperatures between 200° C. to 350° C. to form an ohmic contact with the micro device. In this manner, embodiments of the invention may be utilized to form arrays of micro LED devices based upon a variety of different semiconductor compositions for emitting various different visible wavelengths. For example, micro LED growth substrates including active devices layers formed of different materials for emitting different wavelengths (e.g. red, green, and blue wavelengths) can all be processed within the general sequence of operations of the embodiments. 
     In the following description exemplary processing sequences are described for forming an array of micro devices on an array of stabilization posts. Specifically, exemplary processing sequences are described for forming an array of micro LED devices and an array of micro chips. Where possible, similar features are illustrated with similar annotations in the figures and following description. 
       FIG. 1A  is an example cross-sectional side view illustration of a bulk LED substrate  100  in accordance with an embodiment of the invention. In the illustrated embodiment, bulk LED substrate  100  includes a growth substrate  102 , an epitaxial growth layer  103 , and a device layer  105 . In an embodiment, growth substrate  102  is sapphire and may be approximately 500 μm thick. Using a sapphire growth substrate may correspond with manufacturing blue emitting LED devices (e.g. 450-495 nm wavelength) or green emitting LED devices (e.g. 495-570 nm wavelength). It is to be appreciated, that while the specific embodiments illustrated and described in the following description may be directed to formation of green or blue emitting LED devices, the following sequences and descriptions are also applicable to the formation of LED devices that emit wavelengths other than blue and green. Epitaxial growth layer  103  may be grown on growth substrate  102  using known epitaxial growth techniques. Epitaxial growth layer  103  may be grown on growth substrate  102  at a relatively high temperature to facilitate gliding out dislocations in the layer. In an embodiment, epitaxial growth layer  103  is a gallium nitride (GaN) based material. 
     Device layer  105  may be formed on epitaxial growth layer  103 , as shown in  FIG. 1A . In an embodiment the growth substrate  102  is a sapphire substrate and is approximately 200 μm thick. The epitaxial growth layer  103  may be any suitable thickness such as between 300 Å-5 μm. In the illustrated embodiment, device layer  105  includes layers for forming LED devices. In  FIG. 1A , a zoomed-in view of an example device layer  105  illustrates one or more quantum well layers  110  between doped semiconductor layer  108  (e.g. n-doped) and doped semiconductor layer  112  (e.g. p-doped), although the doping of layers  108 ,  112  may be reversed. In an embodiment, doped semiconductor layer  108  is formed of GaN and is approximately 0.1 μm to 3 μm thick. The one or more quantum well layers  110  may have a thickness of approximately 0.5 μm. In an embodiment, doped semiconductor layer  112  is formed of GaN, and is approximately 0.1 μm to 2 μm thick. 
       FIG. 1B  is a cross-sectional side view illustration of a device wafer including circuitry in accordance with an embodiment of the invention. In accordance with embodiments of the invention, the device wafer  180  may be formed of a variety of materials depending upon the desired function. For example, in an embodiment, the device wafer  180  is a silicon wafer, or silicon-on-insulator (SOI) wafer for logic or memory. In an embodiment, the device wafer  180  is a gallium arsenide (GaAs) wafer for radio frequency (RF) communications. These are merely examples, and embodiments of the invention envision are not limited to silicon or GaAs wafers, nor are embodiments limited to logic, memory, or RF communications. 
     In an embodiment, the device wafer  180  includes an active device layer  185 , optional buried oxide layer  184 , and base substrate  182 . In the interest of clarity, the following description is made with regard to an SOI device wafer  180 , including an active device layer  185 , buried oxide layer  184 , and base silicon substrate  182 , though other types of devices wafers may be used, including bulk semiconductor wafers. In an embodiment, the active device layer  185  may include working circuitry to control one or more LED devices. In some embodiments, back-end processing may be performed within the active device layer  185 . Accordingly, in an embodiment, the active device layer  185  includes an active silicon layer  187  including a device such as a transistor, metal build-up layers  188  including interconnects  189 , bonding pads  190 , and passivation  192 . 
     In interests of clarity the remainder of the description is made with regard to the bulk LED substrate of  FIG. 1A . However, it is appreciated that the process sequences in the following description may be used to fabricate other micro devices. For example, micro chips may be similarly manufactured by substituting bulk LED substrate  100  with device wafer  180  and using the same or similar processes as described with reference to bulk LED substrate  100 . Accordingly, in the following description, both the growth substrate  102  and base substrate  182  can alternatively be referred to more generically as a “handle” substrate so as to not preclude the processing sequence on a growth substrate  102  from being applied to the a processing sequence on a base substrate  182 . 
       FIG. 2A  is a cross-sectional side view illustration of a patterned conductive contact layer on bulk LED substrate  100  in accordance with an embodiment of the invention. A conductive contact layer may be formed over device layer  105  using a suitable technique such as sputtering or electron beam physical deposition followed by etching or liftoff to form the array of conductive contacts  120 . In an embodiment, the array of conductive contacts  120  have a thickness of approximately 0.1 μm-2 μm, and may include a plurality of different layers. For example, a conductive contact  120  may include an electrode layer  121  for ohmic contact, a mirror layer  122 , an adhesion/barrier layer  123 , a diffusion barrier layer  124 , and a bonding layer  125 . In an embodiment, electrode layer  121  may make ohmic contact to a p-doped semiconductor layer  112 , and may be formed of a high work-function metal such as nickel. In an embodiment, a mirror layer  122  such as silver is formed over the electrode layer  121  to reflect the transmission of the visible wavelength. In an embodiment, titanium is used as an adhesion/barrier layer  123 , and platinum is used as a diffusion barrier  124  to bonding layer  125 . Bonding layer  125  may be formed of a variety of materials which can be chosen for bonding to the receiving substrate and/or to achieve the requisite tensile strength or adhesion or surface tension with the stabilization posts. Following the formation of layers  121 - 125 , the substrate stack can be annealed to form an ohmic contact. For example, a p-side ohmic contact may be formed by annealing the substrate stack at 510° C. for 10 minutes. 
     In an embodiment, bonding layer  125  is formed of a conductive material (both pure metals and alloys) which can diffuse with a metal forming a contact pad on a receiving substrate (e.g. gold, indium, or tin contact pad) and has a liquidus temperature above 200° C. such as tin (231.9° C.) or bismuth (271.4° C.), or a liquidus temperature above 300° C. such as gold (1064° C.) or silver (962° C.). In some embodiments, bonding layer  125  such as gold may be selected for its poor adhesion with the adhesive bonding material used to form the stabilization posts. For example, noble metals such as gold are known to achieve poor adhesion with BCB. In this manner, sufficient adhesion is created to maintain the array of micro LED devices on the stabilization posts during processing and handling, as well as to maintain adjacent micro LED devices in place when another micro LED device is being picked up, yet also not create too much adhesion so that pick up can be achieved with an applied pick up pressure on the transfer head of 20 atmospheres or less, or more particularly 5-10 atmospheres. 
     In the embodiment illustrated in  FIG. 2A , where bonding layer  125  has a liquidus temperature above the annealing temperature for forming the p-side ohmic contact, the anneal (e.g. 510° C. for 10 minutes) can be performed after the formation of the patterned conductive contact layer  120 , including bonding layer  125 . Where bonding layer  125  has a liquidus temperature below the annealing temperature for forming the p-side ohmic contact, the bonding layer  125  may be formed after annealing. 
       FIG. 2B  is a cross-sectional side view illustration of a patterned conductive contact layer on a bulk LED substrate  100  in accordance with an embodiment of the invention. The embodiment illustrated in  FIG. 2B  may be particularly useful where bonding layer  125  is formed of a material with a liquidus temperature below the annealing temperature of the p-side ohmic contact, though the embodiment illustrated in  FIG. 2B  is not limited to such and may be used where the bonding layer  125  is formed of a material with a liquidus temperature above the annealing temperature of the p-side ohmic contact. In such embodiments, electrode layer  121  and mirror layer  122  may be formed similarly as described with regard to  FIG. 2A . Likewise, adhesion/barrier layer  123  and diffusion barrier  124  may be formed similarly as described with regard to  FIG. 2A  with one difference being that the layers  123 ,  124  may optionally wrap around the sidewalls of the layers  121 ,  122 . Following the formation of layers  121 - 124 , the substrate stack can be annealed to form an ohmic contact. For example, a p-side ohmic contact may be formed by annealing the substrate stack at 510° C. for 10 minutes. After annealing layer  121 - 124  to form the p-side ohmic contact, the bonding layer  125  may be formed. In an embodiment, the bonding layer  125  has a smaller width than for layers  121 - 124 . 
     In an embodiment, bonding layer  125  has a liquidus temperature or melting temperature of approximately 350° C. or lower, or more specifically of approximately 200° C. or lower. At such temperatures the bonding layer may undergo a phase change without substantially affecting the other components of the micro LED device. In an embodiment, the resultant bonding layer may be electrically conductive. In accordance with some embodiments, the bonding layer  125  may be a solder material, such as an indium, bismuth, or tin based solder, including pure metals and metal alloys. In a particular embodiment, the bonding layer  125  is indium. 
       FIG. 3  is a cross-sectional side view illustration of device layer  105  patterned to form an array of micro device mesa structures  127  over a handle substrate that includes growth substrate  102  and epitaxial growth layer  103  in accordance with an embodiment of the invention. Etching of layers  108 ,  110 , and  112  of device layer  105  may be accomplished using suitable etch chemistries for the particular materials. For example, n-doped semiconductor layer  108 , quantum well layer(s)  110 , and p-doped layer  112  may be dry etched in one operation with a BCl 3  and Cl 2  chemistry. As  FIG. 3  illustrates, device layer  105  may not be etched completely through which leaves unremoved portions  129  of device layer  105  that connect the micro device mesa structures  127 . In one example, the etching of device layer  105  is stopped in n-doped semiconductor layer  108  (which may be n-doped GaN). Height of the micro device mesa structures  127  (not including the thickness of the unremoved portions  129  may correspond substantially to the height of the laterally separate micro devices to be formed. In accordance with embodiments of the invention, the device layer  105  may alternatively be completely etched through. For example, where the bulk LED substrate  100  is replaced with a device wafer  180  in the processing sequence, etching may stop on the buried oxide layer  184 . 
       FIG. 4  is a cross-sectional side view illustration of an adhesion promoter layer  144  and a sacrificial layer  135  including an array of openings  133  formed over the array of micro device mesa structures  127  in accordance with an embodiment of the invention. In an embodiment, sacrificial layer  135  is between approximately 0.5 and 2 microns thick. In an embodiment, sacrificial layer  135  is formed of an oxide (e.g. SiO 2 ) or nitride (e.g. SiN x ), though other materials may be used which can be selectively removed with respect to the other layers. In an embodiment, sacrificial layer  135  is deposited by sputtering, low temperature plasma enhanced chemical vapor deposition (PECVD), or electron beam evaporation to create a low quality layer, which may be more easily removed than a higher quality layer deposited by other methods such as atomic layer deposition (ALD) or high temperature PECVD. 
     Still referring to  FIG. 4 , after the formation of sacrificial layer  135 , an adhesion promoter layer  144  may optionally be formed in order to increase adhesion of the stabilization layer  145  (not yet formed) to the sacrificial layer  135 . A thickness of 100-300 angstroms may be sufficient to increase adhesion. 
     Specific metals that have good adhesion to both the sacrificial layer  135  and a BCB stabilization layer (not yet formed) include, but are not limited to, titanium and chromium. For example, sputtered or evaporated titanium or chromium can achieve an adhesion strength (stud pull) of greater than 40 MPa with BCB. 
     After forming sacrificial layer  135 , the sacrificial layer  135  is patterned to form an array of openings  133  over the array of conductive contacts  120 . If adhesion layer  144  is present, it can also be patterned to form the array of openings  133 , exposing the array of conductive contacts  120  as illustrated in  FIG. 4 . In an example embodiment, a fluorinated chemistry (e.g. HF vapor, or CF 4  or SF 6  plasma) is used to etch the SiO 2  or SiN x  sacrificial layer  135 . 
     As will become more apparent in the following description the height, and length and width of the openings  133  in the sacrificial layer  135  correspond to the height, and length and width (area) of the stabilization posts to be formed, and resultantly the adhesion strength that must be overcome to pick up the array of micro devices (e.g. micro LED devices) poised for pick up on the array of stabilization posts. In an embodiment, openings  133  are formed using lithographic techniques and have a length and width of approximately 1 μm by 1 μm, though the openings may be larger or smaller so long as the openings have a width (or area) that is less than the width (or area) of the conductive contacts  120  and/or micro LED devices. Furthermore, the height, length and width of the openings  131  between the sacrificial layer  135  formed along sidewalls between the micro device mesa structures  127  will correspond to the height, length and width of the stabilization cavity sidewalls to be formed. Accordingly, increasing the thickness of the sacrificial layer  135  and space separating adjacent micro device mesa structures  127  will have the effect of decreasing the size of the stabilization cavity sidewalls. 
       FIG. 5  is a cross-sectional side view illustration of a stabilization layer  145  formed over adhesion promoter layer  144  and sacrificial layer  135  and within an array of openings  133  included in sacrificial layer  135  in accordance with an embodiment of the invention. Stabilization layer  145  may be formed of an adhesive bonding material. The adhesive bonding material may be a thermosetting material such as benzocyclobutene (BCB) or epoxy. In an embodiment, the thermosetting material may be associated with 10% or less volume shrinkage during curing, or more particularly about 6% or less volume shrinkage during curing so as to not delaminate from the conductive contacts  120  on the micro device mesa structures  127 . In order to increase adhesion to the underlying structure, in addition to, or in alternative to adhesion promoter layer  144 , the underlying structure can be treated with an adhesion promoter such as AP3000, available from The Dow Chemical Company, in the case of a BCB stabilization layer in order to condition the underlying structure. AP3000, for example, can be spin coated onto the underlying structure, and soft-baked (e.g. 100° C.) or spun dry to remove the solvents prior to applying the stabilization layer  145  over the patterned sacrificial layer  135 . 
     In an embodiment, stabilization layer  145  is spin coated or spray coated over the patterned sacrificial layer  135 , though other application techniques may be used. Following application of the stabilization layer  145 , the stabilization may be pre-baked to remove solvents, resulting in a b-staged layer. In an embodiment, the stabilization layer  145  is thicker than the height of openings  131 , when present, between micro device mesa structures  127 , and openings  133  in the patterned sacrificial layer  135 . In this manner, the thickness of the stabilization layer filling openings  133  will become stabilization posts  152 , the thickness of the stabilization layer filling openings  131  will become stabilization cavity sidewalls  147 , and the remainder of the thickness of the stabilization layer  145  over the filled openings  131 ,  133  can function to adhesively bond the bulk LED substrate  100  to a carrier substrate. 
       FIG. 6  is a cross-sectional side view illustration of bringing together (bonding) a carrier substrate  160  and micro device mesa structures  127  formed on the handle substrate in accordance with an embodiment of the invention. In order to increase adhesion with the stabilization layer  145 , an adhesion promoter layer  162  can be applied to the carrier substrate  160  prior to bonding the bulk LED substrate  100  to the carrier substrate  160  similarly as described above with regard to adhesion promoter layer  144 . Likewise, in addition to, or in alternative to adhesion promoter layer  162 , an adhesion promoter such as AP3000 may be applied to the surface of the carrier substrate  160  or adhesion promoter layer  162 . Carrier substrate  160  may be silicon, for example. 
     Alternatively stabilization layer  145  can be formed on carrier substrate  160  prior to bonding the carrier substrate  160  to the handle substrate. For example, the structure including the patterned sacrificial layer  135  and micro device mesa structures  127  can be embossed into an a-staged or b-staged stabilization layer  145  formed on the carrier substrate  160 . 
     Depending upon the particular material of stabilization layer  145 , stabilization layer  145  may be thermally cured, or cured with application of UV energy. In an embodiment, stabilization layer  145  is a-staged or b-staged prior to bonding the carrier substrate to the handle substrate, and is cured at a temperature or temperature profile ranging between 150° C. and 300° C. Where stabilization layer  145  is formed of BCB, curing temperatures should not exceed approximately 350° C., which represents the temperature at which BCB begins to degrade. In accordance with embodiments including a bonding layer  125  material characterized by a liquidus temperature (e.g. gold, silver, bismuth) greater than 250° C., full-curing of a BCB stabilization layer  145  can be achieved in approximately 1 hour or less at a curing temperature between 250° C. and 300° C. Other bonding layer  125  materials such as Sn (231.9° C.) may require between 10-100 hours to fully cure at temperatures between 200° C. and the 231.9° C. liquidus temperature. In accordance with embodiments including a bonding layer  125  material characterized by a liquidus temperature below 200° C. (e.g. indium), a BCB stabilization layer  145  may only be partially cured (e.g. 70% or greater). In such an embodiment the BCB stabilization layer  145  may be cured at a temperature between 150° C. and the liquidus temperature of the bonding layer (e.g. 156.7° C. for indium) for approximately 100 hours to achieve at least a 70% cure. 
     Achieving a 100% full cure of the stabilization layer is not required in accordance with embodiments of the invention. More specifically, the stabilization layer  145  may be cured to a sufficient curing percentage (e.g. 70% or greater for BCB) at which point the stabilization layer  145  will no longer reflow. Moreover, it has been observed that such partially cured (e.g. 70% or greater) BCB stabilization layer  145  may possess sufficient adhesion strengths with the carrier substrate  160  and patterned sacrificial layer  135  (or any intermediate layer(s)). 
       FIG. 7  is a cross-sectional side view illustration of the removal of growth substrate  102  in accordance with an embodiment of the invention. When growth substrate  102  is sapphire, laser lift off (LLO) may be used to remove the sapphire. Removal may be accomplished by other techniques such as grinding and etching, depending upon the material selection of the growth substrate  102 . 
       FIG. 8  is a cross-sectional side view illustration of the removal of epitaxial growth layer  103  and a portion of device layer  105  in accordance with an embodiment of the invention. The removal of epitaxial growth layer  103  and a portion of device layer  105  may be accomplished using one or more of Chemical-Mechanical-Polishing (CMP), dry polishing, or dry etch.  FIG. 8  illustrates that that unremoved portions  129  of device layer  105  that connected the micro device mesa structures  127  ( FIG. 7 ) are removed in  FIG. 8 , which leaves laterally separated micro devices  128 . In an embodiment, removing unremoved portions  129  of device layer  105  includes thinning the array of micro device mesa structures  127  so that an exposed top surface  109  of each of the laterally separate micro devices  128  are below an exposed top surface  139  of patterned sacrificial layer  135 . 
     In embodiments where the bulk LED substrate  100  includes epitaxial growth layer  103 , a portion of the doped semiconductor layer  108  adjacent the epitaxial growth layer may also function as a “buffer”. For example, epitaxial growth layer  103  may or may not be doped, while semiconductor layer  108  is n-doped. It may be preferred to remove the epitaxial growth layer  103  using any suitable technique such as wet or dry etching, or chemical mechanical polishing (CMP), followed by a timed etch of the remainder of the doped semiconductor layer  108  resulting in the structure illustrated in  FIG. 8 . In this manner, the thickness of the laterally separate micro devices  128  is largely determined by the etching operation illustrated in  FIG. 3  for the formation of the micro device mesa structures  127 , combined with the timed etch or etch stop detection of the etching operation illustrated in  FIG. 8 . 
       FIGS. 9A-9B  are cross-sectional side view illustrations of a patterned conductive contacts  175  formed over an array of laterally separated micro device  128  in accordance with an embodiment of the invention.  FIGS. 9A and 9B  are substantially similar, with a difference being the arrangement of layers within conductive contacts  120 .  FIG. 9A  corresponds with the conductive contacts  120  illustrated in  FIG. 2A  while  FIG. 9B  corresponds with the conductive contacts  120  illustrated in  FIG. 2B . 
     To form conductive contacts  175 , a conductive contact layer is formed over micro devices  128  and sacrificial layer  135 . The conductive contact layer may be formed of a variety of conductive materials including metals, conductive oxides, and conductive polymers. In an embodiment, conductive contacts are formed of a metal or metal alloy. In an embodiment, the conductive contact layer is formed using a suitable technique such as sputtering or electron beam physical deposition. For example, the conductive contact layer may include BeAu metal alloy, or a metal stack of Au/GeAuNi/Au layers. The conductive contact layer can also be a combination of one or more metal layers and a conductive oxide. In an embodiment, after forming the conductive contact layer, the substrate stack is annealed to generate an ohmic contact between the conductive contact layer and the device layer of micro devices  128 . Where the stabilization layer is formed of BCB, the annealing temperature may be below approximately 350° C., at which point BCB degrades. In an embodiment, annealing is performed between 200° C. and 350° C., or more particularly at approximately 320° C. for approximately 10 minutes. After the conductive contact layer is deposited, it can be patterned and etched to form conductive contacts  175 , which may be n-metal conductive contacts. 
     The resultant structures illustrated in  FIGS. 9A and 9B  are robust enough for handling and cleaning operations to prepare the substrate structure for subsequent sacrificial layer removal and electrostatic pick up. In an exemplary embodiment where the array of micro devices have a pitch of 5 microns, each micro device may have a minimum width (e.g. along the top surface  109 ) of 4.5 μm, and a separation between adjacent micro devices of 0.5 μm. It is to be appreciated that a pitch of 5 microns is exemplary, and that embodiments of the invention encompass any pitch of 1 to 100 μm as well as larger, and possibly smaller pitches. 
       FIGS. 9A and 9B  illustrate a structure having a stabilization layer  145  that includes an array of stabilization cavities and an array of stabilization posts  152 . Each stabilization cavity in the array includes sidewalls  147  (which may be coated with adhesion promoter layer  144 ) of stabilization layer  145  that surround stabilization posts  152 . In  FIGS. 9A and 9B , the bottom surface  107  (having dimension D1) of each micro device  128  is wider that the corresponding stabilization post  152  that is directly under the micro device  128 . In  FIGS. 9A and 9B , sacrificial layer  135  spans along side surfaces  106  of micro devices  128 . In the illustrated embodiments, stabilization posts  152  extend through a thickness of sacrificial layer  135  and the stabilization cavity sidewalls  147  of the stabilization layer  145  are taller than the stabilization posts  152 . However, in some embodiments, stabilization posts  152  are taller than the stabilization cavity sidewalls  147 . For example, the thickness of the sacrificial layer  135  and space between laterally adjacent micro devices  128  may affect the size of the stabilization cavity sidewalls  147 . 
       FIG. 10A  is a cross-sectional side view illustration of an array of micro devices  128  formed on array of stabilization posts  152  after removal of sacrificial layer  135  in accordance with an embodiment of the invention. In the embodiments illustrated, sacrificial layer  135  is removed resulting in an open space  177  between each micro device  128  and stabilization layer  145 . As illustrated, open space  177  includes the open space below each micro device  128  and stabilization layer  145  as well as the open space between each micro device  128  and stabilization cavity sidewalls  147  of stabilization layer  145 . A suitable etching chemistry such as HF vapor, CF 4 , or SF 6  plasma may be used to etch the SiO 2  or SiN x  of sacrificial layer  135 . 
     After sacrificial layer  135  is removed, the array of micro devices  128  are on the array of stabilization posts  152  are supported only by the array of stabilization posts  152 . At this point, the array of micro devices  128  are poised for pick up transferring to a target or receiving substrate. After sacrificial layer  135  is removed leaving only stabilization posts  152  to support micro devices  128 , it is possible that a micro device  128  may shift off of its corresponding stabilization post  152 . However, in the illustrated embodiment, the stabilization cavity sidewalls  147  may be advantageously positioned to contain the shifted micro device  128  within the stabilization cavity. Therefore, even when a micro device  128  loses adherence to a stabilization post  152 , it may still be poised for pick up because it is still positioned within an acceptable tolerance (defined by the stabilization cavity) to be transferred to a receiving substrate. 
     To further illustrate,  FIGS. 10B-10C  are schematic top view illustrations of example stabilization post  152  locations relative to a group of micro devices  128  in accordance with an embodiment of the invention. The cross-sectional side view of  FIG. 10A  is illustrated along line A-A in  FIGS. 10B and 10C .  FIG. 10B  shows an embodiment where stabilization posts  152  are centered in the x-y directions relative to a top view illustration of micro devices  128 .  FIG. 10B  also shows how stabilization cavity sidewalls  147  can function to contain micro devices  128 , if a micro device  128  loses adhesion to a stabilization post  152 .  FIG. 10C  is substantially similar to  FIG. 10B  except that stabilization posts  153  have replaced stabilization posts  152 . Stabilization posts  153  differ from stabilization posts  152  in that they are not centered in the x-y direction relative to a top view illustration of the micro devices  128 . Of course, positions of stabilization posts other than the illustrated positions of stabilization posts  152  and  153  are possible. In an embodiment, during the pick up operation described below the off-centered stabilization posts  153  may provide for the creation of a moment when the array of transfer heads contact the array of micro devices in which the micro devices tilt slightly as a result of the applied downward pressure from the array of transfer heads. This slight tilting may aid in overcoming the adhesion strength between the stabilization posts  153  and the array of micro devices  128 . Furthermore, such assistance in overcoming the adhesion strength may potentially allow for picking up the array of micro devices with a lower grip pressure. Consequently, this may allow for operation of the array of transfer heads at a lower voltage, and impose less stringent dielectric strength requirements in the dielectric layer covering each transfer head required to achieve the electrostatic grip pressure. 
       FIGS. 11A-11E  are cross-sectional side view illustrations of an array of electrostatic transfer heads  204  transferring micro devices  128  from a carrier substrate  160  to a receiving substrate  300  in accordance with an embodiment of the invention.  FIG. 11A  is a cross-sectional side view illustration of an array of micro device transfer heads  204  supported by substrate  200  and positioned over an array of micro devices  128  stabilized on stabilization posts  152  of stabilization layer  145  on carrier substrate  160 . The array of micro devices  128  are then contacted with the array of transfer heads  204  as illustrated in  FIG. 11B . As illustrated, the pitch of the array of transfer heads  204  is an integer multiple of the pitch of the array of micro devices  128 . A voltage is applied to the array of transfer heads  204 . The voltage may be applied from the working circuitry within a transfer head assembly  206  in electrical connection with the array of transfer heads through vias  207 . The array of micro devices  128  is then picked up with the array of transfer heads  204  as illustrated in  FIG. 11C . The array of micro devices  128  is then placed in contact with contact pads  302  (e.g. gold, indium, or tin) on a receiving substrate  300 , as illustrated in  FIG. 11D . The array of micro devices  128  is then released onto contact pads  302  on receiving substrate  300  as illustrated in  FIG. 11E . For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or ICs, or a substrate with metal redistribution lines. 
     In accordance with embodiments of the invention heat may be applied to the carrier substrate, transfer head assembly, or receiving substrate during the pickup, transfer, and bonding operations. For example, heat can be applied through the transfer head assembly during the pick up and transfer operations, in which the heat may or may not liquefy the micro device bonding layers  125 . The transfer head assembly may additionally apply head during the bonding operation on the receiving substrate that may or may not liquefy one of the bonding layers on the micro device or receiving substrate to cause diffusion between the bonding layers. 
     The operation of applying the voltage to create a grip pressure on the array of micro devices can be performed in various orders. For example, the voltage can be applied prior to contacting the array of micro devices with the array of transfer heads, while contacting the micro devices with the array of transfer heads, or after contacting the micro devices with the array of transfer heads. The voltage may also be applied prior to, while, or after applying heat to the bonding layers. 
     Where the transfer heads  204  include bipolar electrodes, an alternating voltage may be applied across a the pair of electrodes in each transfer head  204  so that at a particular point in time when a negative voltage is applied to one electrode, a positive voltage is applied to the other electrode in the pair, and vice versa to create the pickup pressure. Releasing the array of micro devices from the transfer heads  204  may be accomplished with a varied of methods including turning off the voltage sources, lower the voltage across the pair of silicon electrodes, changing a waveform of the AC voltage, and grounding the voltage sources. 
     Furthermore, the method of pickup up and transferring the array of micro devices from a carrier substrate to a receiving substrate described with regard to  FIGS. 11A-11E  is applicable contexts where the micro devices are micro LEDs or other examples of micro devices described herein. 
     In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for stabilizing an array of micro devices on a carrier substrate, and for transferring the array of micro devices. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.

Metadata:
Filing Date: 20151103
Publication Date: 20160628
Grant Date: 20160628
Priority Date: 20130708
Inventors: HU HSIN-HUA
CHANG KEVIN K. C.
BIBL ANDREAS
Assignee: APPLE INC
CPC Classifications: [{"code": "H01L2224/83005", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L2924/12042", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L24/95", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2924/12041", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L24/75", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L24/83", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2224/83005", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L24/75", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2924/12041", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2924/12042", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L24/95", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L24/83", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10H29/142", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10H20/0364", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10H29/10", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/856", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/825", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/813", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/812", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/811", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/018", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/01", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/812", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/018", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/01", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H29/142", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10H29/10", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/857", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L33/62", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L33/60", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 51134377