PATENT DOCUMENT

Publication Number: US-10862428-B2
Application Number: US-201816140991-A
Country: US
Kind Code: B2

Title: Feed-forward envelope tracking

Abstract:
An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.

Claims:
The invention claimed is: 
     
       1. An envelope tracking system for controlling a power amplifier supply voltage or bias, comprising:
 a voltage source circuitry configured to generate a plurality of voltages; 
 a selector circuitry configured to select one of the plurality of voltages based on a target envelope signal that is associated with an envelope of a radio frequency (RF) transmit signal, 
 wherein the selector circuitry is configured to output the selected voltage for coupling to a supply voltage input or a bias input of a power amplifier that amplifies the RF transmit signal, 
 wherein the target envelope signal includes voltage information that identifies which of the plurality of voltages to select, and 
 wherein the target envelope signal includes time information comprising a start time to output the selected voltage from the selector circuitry. 
 
     
     
       2. The envelope tracking system of  claim 1 , wherein the time information comprises a predetermined time period within which the selected voltage is output from the selector circuitry. 
     
     
       3. The envelope tracking system of  claim 1 , wherein the time information further comprises a duration from the start time in which the selected voltage is output from the selector circuitry. 
     
     
       4. The envelope tracking system of  claim 1 , wherein the time information further comprises an end time to discontinue the output of the selected voltage from the selector circuitry. 
     
     
       5. A method configured to provide a supply voltage to a power amplifier, the method comprising:
 generating a plurality of voltages; 
 receiving a target envelope signal based on an envelope of a radio frequency (RF) transmit signal; 
 selecting one of the plurality of voltages based at least on the target envelope signal that communicates voltage information and time information; and 
 providing the selected voltage to an output terminal that is configured to couple to a supply voltage input of a power amplifier that amplifies the RF transmit signal, 
 wherein the voltage information identifies which of the plurality of voltages to select, and 
 wherein the time information comprises a start time to output the selected voltage from a selector circuitry. 
 
     
     
       6. The method of  claim 5 , wherein the time information comprises a predetermined time period within which the selected voltage is output from the selector circuitry. 
     
     
       7. The method of  claim 5 , wherein the time information further comprises a duration from the start time in which the selected voltage is output from the selector circuitry. 
     
     
       8. The method of  claim 5 , wherein the time information further comprises an end time to discontinue the output of the selected voltage from the selector circuitry. 
     
     
       9. A feed forward envelope tracking circuitry, comprising:
 a voltage source circuitry configured to generate a plurality of voltages; and 
 a selector circuitry configured to select one of the plurality of voltages based at least on a target envelope signal that is associated with an envelope of a radio frequency (RF) transmit signal, wherein the target envelope signal includes voltage information that identifies which of the plurality of voltages to select and time information comprising a start time to provide the selected voltage to an output thereof; 
 wherein the selector circuitry output is configured to couple to a supply voltage input of a power amplifier that amplifies the RF transmit signal. 
 
     
     
       10. The feed forward envelope tracking circuitry of  claim 9 , wherein the time information comprises a predetermined time period within which to provide the selected voltage. 
     
     
       11. The feed forward envelope tracking circuitry of  claim 9 , wherein the time information further comprises a duration from the start time in which to provide the selected voltage. 
     
     
       12. The feed forward envelope tracking circuitry of  claim 9 , wherein the time information further comprises an end time to discontinue the providing of the selected voltage.

Description:
REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 15/474,186 filed on Mar. 30, 2017, the contents of which are incorporated by reference in their entirety. 
    
    
     FIELD 
     The present disclosure relates to the field of wireless transmitters and in particular to methods and apparatus for performing envelope tracking to improve the efficiency of a power amplifier in a transmit chain of a transmitter. 
     BACKGROUND 
     Envelope tracking is a technique by which the bias or supply voltage (e.g., V CC ) and current of a power amplifier (PA) in a transmit chain of a transmitter is controlled based on the RF signal envelope of the transmit signal being amplified by the power amplifier. The idea is to operate the power amplifier close to or slightly in compression and to lower the PA supply voltage when the instantaneous signal amplitude is low, thereby boosting the efficiency of the power amplifier and its supply generation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Some examples of circuits, apparatuses and/or methods will be described in the following by way of example only. In this context, reference will be made to the accompanying figures. 
         FIG. 1  illustrates an exemplary transmitter architecture that includes a feed forward digital to analog convertor (DAC) circuitry that supplies voltage to a power amplifier. 
         FIG. 1A  illustrates an exemplary radio frequency (RF) transmit signal, an envelope of the RF transmit signal, and a PA supply voltage provided to the PA from the feed forward DAC circuitry of  FIG. 1 . 
         FIG. 2  illustrates an exemplary feed forward DAC circuitry. 
         FIG. 3  illustrates an exemplary voltage source circuitry for use in a feed forward DAC circuitry. 
         FIG. 4  illustrates an exemplary feed forward DAC circuitry configured to supply voltage to two different power amplifiers. 
         FIG. 5  illustrates an exemplary method for providing supply voltage to a power amplifier. 
         FIG. 6  illustrates an exemplary feed forward DAC circuitry that includes low on-resistance switches in the selector circuitry. 
         FIG. 7  illustrates an exemplary feed forward DAC circuitry that includes a dual impedance circuity in the selector circuitry. 
         FIG. 8  illustrates voltage traces of supply voltage when the supply voltage is switched. 
         FIG. 9  illustrates an exemplary feed forward DAC that includes a charge pump. 
         FIG. 9A  illustrates an exemplary charge pump. 
         FIG. 9B  illustrates, schematically, a selection of supply voltages having an equal spacing. 
         FIG. 9C  illustrates, schematically, a selection of supply voltages having an unequal spacing. 
         FIG. 9D  illustrates an exemplary charge pump. 
         FIG. 10  illustrates an example user equipment device that includes a transmitter front end that includes frequency dependent envelope tracking circuitry in accordance with various aspects described. 
     
    
    
     DETAILED DESCRIPTION 
     Some transmitters that employ envelope tracking techniques generate the supply voltage for the power amplifier using an analog control loop. Within the loop, the power amplifier supply voltage is sensed, compared to a target supply voltage that tracks the envelope of the signal being amplified, and the difference is used to steer a continuous actuator such as an amplifier to correct the power amplifier supply voltage. This solution suffers from several problems. For example, the realization of the analog control loop becomes difficult for increasing envelope signal bandwidth while maintaining reasonable system efficiency. Further, the alternating current (AC) signal path used to generate and control the supply voltage to be equal to the target supply voltage and the direct current (DC) signal path used to determine the target supply voltage are normally separated into two supply chains, which yields an unattractively large solution area on the printed circuit board (PCB). The analog control loop for supply voltage control is feasible for 2× or possibly 3× carrier aggregation in the cellular context. For higher levels of carrier aggregation in cellular applications and for WLAN/WiFi applications, the analog control loop solution does not scale. 
     The systems, devices, and methods described herein perform “feed forward” envelope tracking that generates the power amplifier supply voltage in a feed forward manner. A feed forward digital to analog converter (DAC) circuitry outputs a set of supply voltages, from which one is selected for powering the power amplifier. In this manner, the described feed forward envelope tracking techniques and systems do not rely on an analog control loop and the supply voltage. In addition the described feed forward DAC circuitry is more accurate and less load dependent than an analog control loop, especially at high frequencies. 
     The present disclosure will now be described with reference to the attached figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms “module”, “component,” “system,” “circuit,” “element,” “slice,” “circuitry,” and the like are intended to refer to a set of one or more electronic components, a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, circuitry or a similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and/or a computer with a processing device. By way of illustration, an application running on a server and the server can also be circuitry. One or more circuits can reside within the same circuitry, and circuitry can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other circuits can be described herein, in which the term “set” can be interpreted as “one or more.” 
     As another example, circuitry or similar term can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, circuitry can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components. 
     It will be understood that when an element is referred to as being “electrically connected” or “electrically coupled” to another element, it can be physically connected or coupled to the other element such that current and/or electromagnetic radiation (e.g., a signal) can flow along a conductive path formed by the elements. Intervening conductive, inductive, or capacitive elements may be present between the element and the other element when the elements are described as being electrically coupled or connected to one another. Further, when electrically coupled or connected to one another, one element may be capable of inducing a voltage or current flow or propagation of an electro-magnetic wave in the other element without physical contact or intervening components. Further, when a voltage, current, or signal is referred to as being “applied” to an element, the voltage, current, or signal may be conducted to the element by way of a physical connection or by way of capacitive, electro-magnetic, or inductive coupling that does not involve a physical connection. 
     Use of the word exemplary is intended to present concepts in a concrete fashion. The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of examples. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. 
     In the following description, a plurality of details is set forth to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring embodiments of the present disclosure. In addition, features of the different embodiments described hereinafter may be combined with each other, unless specifically noted otherwise. 
       FIG. 1  illustrates a transmitter architecture  100  that includes a transmitter chain  110  and an exemplary envelope tracking system  140 . The transmitter chain processes a digital baseband transmit signal to generate a radio frequency (RF) transmit signal. The RF transmit signal is amplified by a PA to generate an uplink signal that is transmitted by an antenna or cable (not shown). The exemplary transmit chain  110  includes transmit digital processing circuitry  120  that operates on a digital baseband transmit signal to convert the signal into amplitude and phase components. The amplitude and phase components are converted into the analog RF transmit signal by transmit analog processing circuitry  130 . 
     The envelope tracking system  140  includes envelope circuitry  150  that generates a target envelope signal that is used to control a feed forward DAC circuitry  160  to supply a selected supply voltage to the PA. The envelope circuitry  150  samples the baseband transmit signal to project an envelope of the RF transmit signal that will be amplified by the PA to generate the uplink signal.  FIG. 1A  illustrates an exemplary RF transmit signal  190  and an envelope that bounds the RF transmit signal. The envelope circuitry  150  determines the envelope of the RF transmit signal and generates the target envelope signal to control the feed forward DAC circuitry  160  to provide a PA supply voltage that closely matches the envelope. 
     The target envelope signal includes voltage domain information that may be a control word or voltage that communicates the desired supply voltage or a selection setting from the plurality of voltage levels to the feed forward DAC circuitry  160 . In addition, the target envelope signal may include time domain information that communicates a time during which the desired supply voltage should be provided to the PA. For example, the target envelope signal may specify voltage domain information V S2  and time domain information st n  to cause the feed forward DAC circuitry  160  to change the PA supply voltage from V S1  to V S2  at the switching time st n  as shown in  FIG. 1A . The time domain information may also include a duration of time until a next voltage level and switching time will be communicated. In order to reduce noise, the envelope circuitry  150  may determine a switching time that will coincide with a relative low RF transmit signal (e.g., when the RF transmit signal is crossing the frequency axis as shown in  FIG. 1A ). In one example, “relative low” means that the RF transmit signal is lower or equal to a predetermined threshold. In an alternate implementation the envelope circuitry  150  may choose a switching time when the instantaneous envelope signal is low, i.e., when the instantaneous signal power is low. In this case the next selected voltage is an upper bound of all instantaneous envelop signal voltages which occur until another low phase is reached. At the next low phase another voltage is selected and so on. Thus the switching time may be selected based on either a zero crossing of the RF signal or a close to zero condition of the envelope signal. 
     The feed forward DAC circuitry  160  includes voltage source circuitry  170  and selector circuitry  180 . The principle of the feed forward DAC circuitry  160  is to remove the analog control loop of prior envelope tracking systems and instead to generate the PA supply voltage in a feed-forward manner from the feed forward DAC circuitry  160 . The voltage source circuitry  170  is an analog circuit that is configured to generate a plurality of supply voltages having differing levels. The selector circuitry  180  is a switching circuit that connects one of these supply voltages to the output of the feed forward DAC circuitry  160 . The output of the feed forward DAC circuitry  160  is connected to a supply input (not shown) of the PA. 
     It can be seen in  FIG. 1A  that the PA supply voltage provided by the feed forward DAC circuitry  160  varies in a stepwise fashion to approximate the envelope. While analog envelope tracking PA power supply solutions may be able to more closely follow the envelope, recall that analog solutions have limited applicability in high frequency applications as well as presenting the other drawbacks discussed above. The feed forward envelope tracking described herein provides effective envelope tracking in a manner that scales for higher frequencies and presents a small package size. 
     The voltage source circuitry  170  is capable of producing any number of voltage levels (see  FIG. 3 ). To leverage this feature of the voltage source circuitry  170 , the feed forward DAC circuitry  160  inputs transmitter operation parameters that include, for example, a transmit power level and mode of operation. The feed forward DAC circuitry  160  may use this information to control which voltage levels are produced by the voltage source circuitry  170 . For example, if the transmit power level is relatively small, the set of voltages may span smaller range so that the PA supply voltage can more closely follow the envelope or the number of voltages may be reduced to a smaller set. In contrast, if the transmit power level is large, the set of voltages may span a larger range to cover the variation in the envelope. 
       FIG. 2  illustrates an exemplary feed forward DAC circuitry  260 . Note that in the figures, components having an analogous component in another figure are assigned a reference character that has the same number in the tens and ones digit as the component in the other figure. In order to achieve high efficiency (&gt;90%) a voltage source circuitry  270  generates the set of voltages with an inductor  272  and a single-inductor-multiple-output (SIMO) DCDC converter  274 . One exemplary implementation of the voltage source circuitry is illustrated in  FIG. 3 . The SIMO DCDC converter  274  outputs, in a time multiplexed fashion, a plurality of PA supply voltages V S1 , V S2 , V S3 , and V S4 . 
     A selector circuitry  280  is embodied as a multiplexer that is controlled by the target envelope signal to select one of the supply voltages generated by the SIMO DCDC converter  274  to be output by the feed forward DAC circuitry  260 . The selector circuitry  280  may be any suitable switch that is capable of connecting one of the SIMO DCDC converter  274  outputs to the PA. While in the illustrated feed forward DAC circuitry the target envelope signal is a digital signal, the target envelope signal may be an analog signal in which case the selector circuitry  280  is capable of being controlled by an analog signal. 
     When the envelope circuitry switches the target envelope signal voltage from a first voltage level to a second voltage level, in one example the selector circuitry switches directly from the first to the second voltage level. In another example, the selector circuitry may follow a sequence of switching events such as switching back and forth between the first voltage level and the second voltage level several times or switching temporarily to a third voltage level. This may interpolate voltage levels or shape the step response by pre-distorting the voltage wave traveling from the selector circuitry to the input terminal of the PA 
     It can be seen in  FIG. 2  that the there is no control loop in the generation of the PA supply voltage. The output PA supply voltage is delivered from pure voltage sources instead of a regulated stage. Thus the PA supply voltage may be more accurate and less load dependent especially at high frequencies and during fast switching. Fast switching multiplexers or other switches are available to be used for the selector circuitry  280 . This is advantageous because the higher signal bandwidths of modern devices translate into a need for faster switching between the different voltage levels. The fast switching provided by the selector circuitry  280  thus fits well to modern, digital dominated technologies. The illustrated feed forward DAC circuitry separates the analog task of voltage level generation from the control of voltage selection, which is digital. 
       FIG. 3  illustrates an exemplary implementation of a voltage source circuitry  170 . A SIMO DCDC converter  374  generates several voltage levels with a single coil  372  in a time-multiplexed manner. The SIMO DCDC converter  374  generates the voltages using the inductor  372 , a set of capacitors C 1 -C 4 , and switches S 1 , S 2 , S 3 , and S 4 . Switches S 1  and S 2  are connected to battery voltage and ground, respectively. The SIMO DCDC converter  374  includes control circuitry (not shown) that controls S 1  and S 2  to either connect the inductor  372  to the battery voltage or ground to maintain a predetermined amount of current stored in the inductor  372 . S 3  and S 4  are controlled by the control circuitry to selectively connect one of the capacitors C 1 -C 4  to either the current source inductor  372  or ground to maintain the amount of voltage stored in the capacitor at its designated supply voltage level. It can be seen that by controlling the switches S 1 -S 4 , any number of supply voltages may be generated by the voltage source  370 . Recall that the feed forward DAC  160  selects the supply voltages to be generated by the voltage source  370  based at least on operating parameters of the transmitter, such as transmit power. While four supply voltages are illustrated, the number of supply voltages generated by the feed forward DAC may be more or less than four. The controller which controls the switches S 1 , S 2  and S 3  may consider the near future switch selection of S 4 , i.e. the intended voltage selection in near future in order to ramp the coil current to a most appropriate current level. This pre-emptive control of the SIMO switches is possible because the Envelope Circuitry  150  and the Transmit Digital Processing Circuitry know the transmitted signal in advance. 
     As illustrated in  FIGS. 2 and 3 , the feed forward DAC architecture may be very small. The largest component, which does not scale well, is the coil  272 . Thus it is advantageous to have only one coil in the system. Some other power amplifier supply voltage systems have two coils and these coils cannot be shared among different channels. While the feed forward DAC includes several capacitors C 1 -C 4  in order to stabilize the voltage levels, capacitors scale much better and are already available in much smaller package size than inductors. 
       FIG. 4  illustrates a feed forward DAC  460  that is configured to generate supply voltages for two different power amplifiers. Once a set of voltages are generated by voltage source circuitry  470 , the voltages can be accessed by multiple independent selector circuitries  480  and  485  to feed two (or more) power amplifiers. This makes the feed forward DAC even more attractive because the incremental increase in area utilized for powering an additional power amplifier is only the selector circuitry  485  (e.g., switches) which can have a very small package size. Thus even more voltage levels than active parallel channels can be realized. This is attractive because the capacitive load of the power amplifiers can be distributed to several parallel channels which improves efficiency at high bandwidth. 
     When the RF DAC and the power amplifier are merged into a single device, the feed forward DAC can be used as well. Then the feed forward DAC is part of this combined DAC and may contribute the MSBs of the output power supply voltage in either an additive or multiplicative way. 
     While the methods are illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Also, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
       FIG. 5  depicts a flowchart outlining one embodiment of a method  500  for providing a supply voltage to a power amplifier. The method  500  may be performed by the feed forward DAC circuitry of  FIGS. 1 and/or 2 . The method includes, at  510 , generating a plurality of voltages. At  520 , a target envelope signal based on or based on a selected power amplifier supply voltage is received. The method includes, at  530 , selecting one of the plurality of voltages based at least on the target envelope signal. At  540  the selected voltage is provided or connected to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal. 
     It can be seen from the foregoing description that the disclosed systems, devices, and methods provide effective envelope tracking over a wide range of frequencies using a feed forward approach to generating power amplifier supply voltages. 
       FIG. 6  illustrates an exemplary feed forward DAC  660  that includes voltage source circuitry  670  and selector circuitry  680  as described with reference to  FIGS. 1-5 . The voltage source circuitry  670  generates a plurality of supply voltages and the selector circuitry  680  includes switches that connect a selected one of the supply voltages to the output of the feed forward DAC  660 . The load for the feed forward DAC  660  can be any electrical load (e.g. a power amplifier, a current sink, a capacitance or any combination of these elements). The load is connected to the feed forward DAC  660  by a wire that contributes a wire inductance Lwire and a wire capacitance Cwire. Effectively this arrangement yields the equivalent circuit depicted in  FIGS. 6  (and  FIG. 7 ), i.e. an LC low pass circuit with output resistance. 
     Because the feed forward DAC  660  provides high power (high current) to the PA (shown as Rload), any switches in the selector circuitry  680  should have a low on-resistance. Low on-resistance switches yield low power consumption and so high efficiency but also cause poor settling when switching from one voltage to another. If the switch resistance of the selector circuitry  680  which connects the load to a selected supply voltage has a low on-resistance a high-Q resonator arises which will ring as soon as the voltage is switched from one level to another. This is because the load circuit (e.g., power amplifier) which can be described as an LC network, resonates when a step signal is applied via a low resistance path. 
       FIG. 8  illustrates voltage traces captured at the moment that the PA supply voltage output by the feed forward DAC circuitry  660  is switched to V S1 . In particular, trace  810  illustrates a control signal A that controls a first switch in the selector circuitry  680  to connect the voltage V S1  to the power amplifier. It can be seen in trace  830  that V S1  exhibits ringing and poor settling. The ringing frequency and the damping depends on the load itself as well as on the wiring parasitics. Thus the settling behavior is not well defined. A reasonably known settling behavior, however, is an important consideration for DAC based envelope tracking as the settling behavior needs to be known for the RF signal pre-distortion. 
     In order to achieve acceptable RF performance the resonant settling should be suppressed. Suppression of resonant settling (or ringing) can be done either by a high ohmic driver (which degrades the system efficiency) or by a dissipative output filter (which increases the PCB area and bill of material as well as degrading the system efficiency).  FIG. 7  illustrates an exemplary feed forward DAC  760  in which selector circuitry  780  includes dual impedance circuitry  790  that does not exhibit either of these drawbacks. For simplicity sake, only a first portion of the selector circuitry  780   a  associated with the first supply voltage as well as a corresponding portion of the dual impedance circuitry  790   a  associated with the first portion of the selector circuitry  780   a  is illustrated. Additional portions of the selector circuitry  780  and the dual impedance circuitry  790  associated with the other three (or more or less) supply voltages are not illustrated. 
     Recall that from an efficiency perspective the on-resistance of the selector circuitry switches should be small. From a settling and RF quality perspective the switch on-resistance should terminate the line between the feed forward DAC  760  and the PA such that the step response is aperiodically damped. The dual impedance circuitry  790   a  first closes a first switch  793  that connects the supply voltage to a high impedance path  792  including a relatively large resistance  794 . This first stage of operation of the dual impedance circuitry  790   a  may be performed in response to receiving control signal A (which may be generated based on the time domain information in the target envelope signal). 
     Once the voltage has aperiodically settled to its new value the dual impedance circuitry  790   a  closes a second switch  798  that connects the supply voltage to a low impedance path  797  that includes a small resistance and thus provides a low ohmic connection for the high current that is supplied to the power amplifier. This second phase of operation of the dual impedance circuitry  790   a  is triggered by control signal B. 
     To generate control signal B, the dual impedance circuitry  790   a  includes a delay element or circuitry  795  that delays control signal A. An AND gate circuitry  796  performs a logical AND operation on control signal A and the output of the delay element  795  to generate the control signal B. Thus, the control signal B will go “high” after a predetermined delay period (which is controlled by the delay element  795 ). Control signal B is illustrated in trace  820  of  FIG. 8 . 
     For optimum power efficiency the delay introduced by the delay element  795  shall be chosen to be as small as possible. If the delay is too small, however, the ringing is not fully suppressed. Thus, adaptive delay selection may be employed so the delay can be calibrated when the actual load and wire conditions are known. To calibrate the delay, a peak detector can be connected to the output node of the feed forward DAC  760 . Based on the measurement results of this peak detector the delay can be increased until no peaking occurs or the peaking is below an acceptable level. The amount of delay that is suitable for each possible supply voltage may be stored for use when changes in transmitter operation will cause different supply voltages to be used. 
     The dual impedance circuitry  790   a  causes each switching event performed by the selector circuitry  780   a  to include two steps: first a “small” switch  793  is used with source side termination resistance  794  and then after the predetermined delay period a “large” and low ohmic switch  798  is connected in parallel with the source side termination resistance. The same principle can be applied when the interconnect is not lumped but e.g. a micro-strip line. In this case the resistor  794  in series to the first switch is the characteristic impedance of the wire or a function of this characteristic impedance. 
       FIG. 8  trace  830  shows the supply voltage V S1 ′ that is output by the feed forward DAC  760 . It can be seen that when switch control signal A goes high the first switch  793  closes. In series with this switch  793  a damping resistor  794  is placed which avoids ringing during the step response. After a delay the second switch  798  is closed. The second switch does not have a series resistance element and thus provides a low-ohmic connection between the supply voltage output by the feed forward DAC and the load. The effect can be seen in the in trace  830 . If the delay is properly selected a step response without ringing is realized: When the control signal A goes low, both switches  793  and  798  are opened immediately. 
     It can be seen from the foregoing description that the disclosed systems, devices, and methods can achieve aperiodic settling of the supply voltage to a power amplifier together with low switch resistance. Conventional switches can optimize only one of these aspects. Thus they are not well suited for high speed power applications. 
       FIG. 9  illustrates an exemplary feed forward DAC circuitry  960  that includes a voltage source circuitry  970  with a SIMO DCDC converter  974  that utilizes a single coil  972  to generate a set of supply voltages across a bank of capacitors  975  (C 1 -C 4 ) as described above with reference to  FIGS. 1-5 . A typical SIMO DCDC converter can regulate voltages with a (small) finite bandwidth, e.g. 10 MHz. However, the power amplifier load on the feed forward DAC circuitry  960  is quickly varying with the transmit RF signal envelope bandwidth. Thus the supply voltages V S1 -V S4  generated by the SIMO DCDC converter  974  across the capacitor bank  975  may be perturbed by the load current. One way to generate stable supply voltages which would not be much perturbed by the load current variation is to use very large capacitors in the capacitor bank  975 . This, however, would mean using large components which lead to unattractively large PCB area. The capacitors in the bank  975  are intentionally chosen with a relatively small capacitance to present a smaller footprint. 
     To compensate for the use of small capacitors, the voltage source circuitry  970  includes a charge pump  976  arranged in parallel with the SIMO DCDC converter  974  to make fine adjustments to the voltages across the capacitors  975  to compensate for voltage errors due to perturbations. The use of the charge pump  976  in combination with the SIMO DCDC converter  974  means that very stable voltage levels can be achieved even with small capacitors. Voltage errors resulting from the fact that small capacitors are used are compensated by the charge pump  976  quickly and with high power efficiency 
     The charge pump  976  can be characterized as an adiabatic charge pump that is capable of altering the charge (and so the voltage) of the capacitors  975 . The charge pump  976  operates quasi adiabatically, meaning that the charge pump transfers charge to and from the capacitors  975  with low losses, i.e. high efficiency. The major portion of the charge provisioning on the capacitors  975  is done by the relatively slow SIMO DCDC converter  974  and the adiabatic charge pump  976  is responsible for smaller but very fast correction work. The charge pump  976  includes several features that improve its operating efficiency, as will now be described. 
     If a capacitor C is charged to a voltage V it contains the energy ½×CxV{circumflex over ( )}2 and another ½×CxV{circumflex over ( )}2 is dissipated during the charging process. In other words half of the energy is always lost. For charging and discharging with low losses it is thus important to have a small voltage delta. The capacitors  975  are charged to different nominal voltages and the actual voltages may occasionally deviate from these nominal voltages by a perturbation. 
     Referring to  FIG. 9A , a charge pump  976 ′ is illustrated that includes a pump capacitor  977  (a plurality of capacitors may be used in some examples) that is connected to the bank  975  and, by way of a switch  978 , selectively transfers charge from one capacitor in the bank  975  to another capacitor in the bank in order to correct for the perturbations. The losses incurred by such a transfer of power are proportional to the square of the voltage delta across the pump capacitor  977 . Because in the charge pump  976 ′ the pump capacitor  977  is connected between ground and the bank capacitors  975 , depending on the supply voltages on the capacitors, unacceptably large energy dissipation for an envelope tracking application may result. For example, if the nominal supply voltages across the capacitors are about 1.1, 2.2, 3.3 and 4.4V, when the pump capacitor  977  switches between two adjacent bank capacitors  975  in order to transfer charge from one bank capacitor to the other the voltage delta which causes the losses is always about 1.1V. 
       FIG. 9D  illustrates an exemplary charge pump  976 ″ in which the pump capacitor  977  is selectively connected, by way of switches  978   a ,  978   b , in between two of the bank capacitors instead of between a bank capacitor and ground as in  FIG. 9A . This arrangement should result in a lower voltage delta across the pump capacitor. As shown schematically in  FIG. 9B , if the different supply voltages V S1  to V S4  are equally spaced in terms of voltage, the voltage delta between capacitors, which leads to the losses, would be small. This would result in relatively small losses. However, the downside to having equally spaced supply voltages is that the amount of charge that can be transferred is also very small, meaning that the pump effect is very small unless a huge pump capacitor or a very high switching frequency is used. 
     To facilitate an efficient charge pump, the supply voltages VS 1 -VS 2  are selected such that the voltage levels are not equally spaced but rather the voltage spacing changes slightly from level to level. With this arrangement, the voltage deltas are so small that no significant power dissipation happens when they are alternately connected in between two voltage steps. On the other hand the nominal voltage delta is not zero (as for equally spaced voltages) and so a significant charge transfer is possible even with a reasonably small pump capacitor  977  and switching frequency.  FIG. 9C  illustrates the concept of using unequal spacing between the supply voltages. For example, if the supply voltage levels V S1  toV S4  are 1.0V, 2.1V, 3.3V and 4.6V, respectively, the difference between two adjacent voltage deltas (e.g., delta across the pump capacitor when it is connected between C 1  and C 2  as compared to the delta across the pump capacitor when it is connected between C 2  and C 3 ) is always 0.1V. This is the voltage which defines the losses, which will be relatively low. This principle is independent on the actual connection of the capacitors, as long as the voltage delta across the pump capacitor  977  is kept small but not zero. 
     As can be seen from the foregoing description, an adiabatic charge pump that selectively connects a pump capacitor between two bank capacitors to regulate the charge on the bank capacitors can provide an efficient way to maintain the supply voltages generated by the feed forward DAC circuitry, especially when the supply voltages are not equally spaced. 
     To provide further context for various aspects of the disclosed subject matter,  FIG. 10  illustrates a block diagram of an embodiment of user equipment  1000  (e.g., a mobile device, communication device, personal digital assistant, etc.) related to access of a network (e.g., base station, wireless access point, femtocell access point, and so forth) that can enable and/or exploit features or aspects of the disclosed aspects. 
     The user equipment or mobile communication device  1000  can be utilized with one or more aspects of the feed forward DAC circuitry described herein according to various aspects. The user equipment device  1000 , for example, comprises a digital baseband processor  1002  that can be coupled to a data store or memory  1003 , a front end  1004  (e.g., an RF front end, an acoustic front end, or the other like front end) and a plurality of antenna ports  1007  for connecting to a plurality of antennas  10061  to  1006   k  (k being a positive integer). The antennas  10061  to  1006   k  can receive and transmit signals to and from one or more wireless devices such as access points, access terminals, wireless ports, routers and so forth, which can operate within a radio access network or other communication network generated via a network device (not shown). 
     The user equipment  1000  can be a radio frequency (RF) device for communicating RF signals, an acoustic device for communicating acoustic signals, or any other signal communication device, such as a computer, a personal digital assistant, a mobile phone or smart phone, a tablet PC, a modem, a notebook, a router, a switch, a repeater, a PC, network device, base station or a like device that can operate to communicate with a network or other device according to one or more different communication protocols or standards. 
     The front end  1004  can include a communication platform, which comprises electronic components and associated circuitry that provide for processing, manipulation or shaping of the received or transmitted signals via one or more receivers or transmitters (e.g. transceivers)  1008 , a mux/demux component  1012 , and a mod/demod component  1014 . The front end  1004  is coupled to the digital baseband processor  1002  and the set of antenna ports  1007 , in which the set of antennas  10061  to  1006   k  can be part of the front end. In one aspect, the user equipment device  1000  can comprise a phase locked loop system  1010 . 
     The processor  1002  can confer functionality, at least in part, to substantially any electronic component within the mobile communication device  1000 , in accordance with aspects of the disclosure. As an example, the processor  1000  can be configured to execute, at least in part, executable instructions that determine transmitter operation parameters and select the different supply voltages to be generated as described in  FIGS. 1-5 . The processor  1000  may embody various aspects of the feed forward DAC circuitry, and so on, of  FIGS. 1-9  as a multi-mode operation chipset that affords a feed forward approach to generating PA supply voltages. 
     The processor  1002  is functionally and/or communicatively coupled (e.g., through a memory bus) to memory  1003  in order to store or retrieve information necessary to operate and confer functionality, at least in part, to communication platform or front end  1004 , the phase locked loop system  1010  and substantially any other operational aspects of the phase locked loop system  1010 . The phase locked loop system  1010  includes at least one oscillator (e.g., a VCO, DCO or the like) that can be calibrated via core voltage, a coarse tuning value, signal, word or selection process according the various aspects described herein. 
     The processor  1002  can operate to enable the mobile communication device  1000  to process data (e.g., symbols, bits, or chips) for multiplexing/demultiplexing with the mux/demux component  1012 , or modulation/demodulation via the mod/demod component  1014 , such as implementing direct and inverse fast Fourier transforms, selection of modulation rates, selection of data packet formats, inter-packet times, etc. Memory  1003  can store data structures (e.g., metadata), code structure(s) (e.g., modules, objects, classes, procedures, or the like) or instructions, network or device information such as policies and specifications, attachment protocols, code sequences for scrambling, spreading and pilot (e.g., reference signal(s)) transmission, frequency offsets, cell IDs, and other data for detecting and identifying various characteristics related to RF input signals, a power output or other signal components during power generation. 
     While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. 
     Examples can include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described herein. 
     Example 1 is an envelope tracking system for controlling a power amplifier supply voltage, including an envelope circuitry and a feed forward digital to analog (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal. 
     Example 2 includes the subject matter of example 1, including or omitting optional elements, wherein the envelope circuitry is configured to generate the target envelope signal including: voltage domain information that identifies which of the plurality of voltages to select; and time domain information that identifies a time during which to provide the selected voltage to the power amplifier. 
     Example 3 includes the subject matter of example 1, including or omitting optional elements, wherein the envelope circuitry is further configured to: determine a time during which the RF transmit signal will be at a relative low; and generate a target envelope signal that includes time domain information that specifies the determined time. 
     Example 4 includes the subject matter of example 1, including or omitting optional elements, wherein the voltage source circuitry includes: an inductor having an input configured to be connected to either a supply voltage or ground; and a plurality of capacitors each coupled to an output of the inductor. The voltage source circuitry is configured to control one or more switches to charge, with current from the inductor, each capacitor to one of the plurality of voltages. 
     Example 5 includes the subject matter of example 1, including or omitting optional elements, wherein the selector circuitry includes a multiplexer that receives the target envelope signal and selects one of the plurality of voltages based at least on the target envelope signal. 
     Example 6 includes the subject matter of any of examples 1-5, including or omitting optional elements, wherein the feed forward DAC circuitry includes a second selector circuitry configured to select a second one of the plurality of voltages based at least on a second target envelope signal, and further wherein the feed forward DAC circuitry provides the second selected voltage to a supply voltage input of a second power amplifier, different from the first power amplifier. 
     Example 7 includes the subject matter of any of examples 1-5, including or omitting optional elements, wherein the feed forward DAC circuitry is configured to: analyze one or more transmitter operation parameters; and determine the plurality of voltages to be generated by the voltage source circuitry based at least on the one or more transmitter operation parameters. 
     Example 8 includes the subject matter of any of examples 1-5, including or omitting optional elements, wherein the feed forward DAC circuitry includes a dual impedance circuitry connected in series to an output of the selector circuitry and the supply input, wherein the dual impedance circuitry is configured to provide a relatively high impedance path between the selector circuitry and the supply input when the selector circuitry is initially connected to the supply input and to provide a relatively low impedance path between the selector circuitry and the supply input after a predetermined delay period. 
     Example 9 includes the subject matter of any of examples 1-5, including or omitting optional elements, wherein the feed forward DAC circuitry includes a dual impedance circuitry connected in series to an output of the selector circuitry and the supply input. The dual impedance circuitry includes a relatively high impedance first signal path that includes a first switch and a resistance element; a relatively low impedance second signal path that includes a second switch, wherein the second signal path is in parallel to the first signal path such that when second switch is closed the second signal path is connected in parallel between the output of the selector circuitry and the supply input; and control circuitry. The control circuitry is configured to, in response to determining that the output of the selector circuitry is to be connected to the supply input: close the first switch; and after a predetermined delay period close the second switch. 
     Example 10 includes the subject matter of any of examples 1-5, including or omitting optional elements, wherein the feed forward DAC circuitry includes a first plurality of bank capacitors coupled to an output of an inductor; wherein the feed forward DAC circuitry is configure to charge, by current from the inductor, each bank capacitor to a designated one of the plurality of voltages; and a charge pump circuitry. The charge pump circuitry includes a pump capacitor and switches configured to selectively connect the pump capacitor between a selected two bank capacitors to charge or discharge one of the two bank capacitors to maintain the voltage of each of the bank capacitors at the designated voltage for the capacitor. 
     Example 11 includes the subject matter of example 10, including or omitting optional elements, wherein the feed forward DAC is configured to select values for the plurality of voltages such that a difference between all pairs of voltages in the plurality of voltages is different. 
     Example 12 is a method configured to provide a supply voltage to a power amplifier. The method includes generating a plurality of voltages; receiving a target envelope signal based on a selected power amplifier supply voltage; selecting one of the plurality of voltages based at least on the target envelope signal; and providing the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal. 
     Example 13 includes the subject matter of example 12, including or omitting optional elements, including generating the target envelope signal that communicates: voltage domain information that identifies which of the plurality of voltages to select; and time domain information that identifies a time during which to provide the selected voltage to the power amplifier. 
     Example 14 includes the subject matter of example 13, including or omitting optional elements, including determining a time during which the RF transmit signal will be at a relative low; and generating a target envelope signal that includes time domain information that specifies the determined time. 
     Example 15 includes the subject matter of any of examples 12-14, including or omitting optional elements, including selecting a second one of the plurality of voltages based at least on a second target envelope signal, and providing the second selected voltage to a supply voltage input of a second power amplifier, different from the first power amplifier, that amplifies a second RF transmit signal. 
     Example 16 includes the subject matter of any of examples 12-14, including or omitting optional elements, including receiving one or more transmitter operation parameters; and determining a new plurality of voltages to be generated based at least on the one or more transmitter operation parameters. 
     Example 17 includes the subject matter of any of examples 12-14, including or omitting optional elements, including providing a relatively high impedance path for the supply voltage when a supply voltage is first connected to the supply voltage input of the power amplifier; and providing a relatively low impedance path for the supply voltage at an expiration of a predetermined delay period after the supply voltage is first connected to the supply voltage input. 
     Example 18 includes the subject matter of any of examples 12-14, including or omitting optional elements, including generating the plurality of voltages by: charging each of a first plurality of bank capacitors to a designated one of the plurality of voltages by coupling the bank capacitors, in turn, to an inductor; and selectively coupling a pump capacitor between a pair of bank capacitors to maintain the voltage of each of the bank capacitors at the designated voltage for the bank capacitor. 
     Example 19 includes the subject matter of example 18, including or omitting optional elements, wherein a difference between any pair of voltages in the plurality of voltages is different from all other differences between pairs of voltages in the plurality of voltages. 
     Example 20 is a feed forward digital to analog converter (DAC) circuitry including a voltage source circuitry configured to generate a plurality of voltages and a selector circuitry configured to select one of the plurality of voltages based at least on a target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal. 
     Example 21 includes the subject matter of example 20, including or omitting optional elements, wherein the target envelope signal includes: voltage domain information that identifies which of the plurality of voltages to select; and time domain information that identifies a time during which to provide the selected voltage to the power amplifier. 
     Example 22 includes the subject matter of example 20, including or omitting optional elements, wherein the voltage source circuitry includes: an inductor having an input configured to be connected to either a supply voltage or ground and a plurality of capacitors each coupled to an output of the inductor. The voltage source circuitry is configured to control one or more switches to charge, with current from the inductor, each capacitor to one of the plurality of voltages. 
     Example 23 includes the subject matter of any of examples 20-22, including or omitting optional elements, including a second selector circuitry configured to select a second one of the plurality of voltages based at least on a second target envelope signal, and further wherein the feed forward DAC circuitry provides the second selected voltage to a supply voltage input of a second power amplifier, different from the first power amplifier. 
     Example 24 includes the subject matter of any of examples 20-22, including or omitting optional elements, including a dual impedance circuitry connected in series an output of the selector circuitry and the supply input, wherein the dual impedance circuitry is configured to provide a relatively high impedance path between the selector circuitry and the supply input when the selector circuitry is initially connected to the supply input and to provide a relatively low impedance path between the selector circuitry and the supply input after a predetermined delay period. 
     Example 25 includes the subject matter of any of examples 20-22, including or omitting optional elements, including a first plurality of bank capacitors coupled to an output of an inductor. The feed forward DAC circuitry is configure to charge, by current from the inductor, each bank capacitor to a designated one of the plurality of voltages, such that a difference between all pairs of voltages in the plurality of voltages is different. A charge pump circuitry includes a pump capacitor and switches configured to selectively connect the pump capacitor between a selected two bank capacitors to charge or discharge one of the two bank capacitors to maintain the voltage of each of the bank capacitors at the designated voltage for the capacitor. 
     Example 26 is an apparatus configured to provide a supply voltage to a power amplifier, including means for generating a plurality of voltages; means for receiving a target envelope signal based on a selected power amplifier supply voltage; means for selecting one of the plurality of voltages based at least on the target envelope signal; and means for providing the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal. 
     Example 27 includes the subject matter of example 26, including or omitting optional elements, including means for providing a relatively high impedance path for the supply voltage when a supply voltage is first connected to the supply voltage input of the power amplifier and means for providing a relatively low impedance path for the supply voltage at an expiration of a predetermined delay period after the supply voltage is first connected to the supply voltage input. 
     Example 28 includes the subject matter of example 26, including or omitting optional elements, including a first plurality of bank capacitors coupled to an output of an inductor and means for charging, by current from the inductor, each bank capacitor to a designated one of the plurality of voltages, such that a difference between all pairs of voltages in the plurality of voltages is different. A charge pump circuitry includes a pump capacitor and switches configured to selectively connect the pump capacitor between a selected two bank capacitors to charge or discharge one of the two bank capacitors to maintain the voltage of each of the bank capacitors at the designated voltage for the capacitor. 
     Various illustrative logics, logical blocks, modules, and circuits described in connection with aspects disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor can be a microprocessor, but, in the alternative, processor can be any conventional processor, controller, microcontroller, or state machine. 
     The above description of illustrated embodiments of the subject disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize. 
     In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below. 
     In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

Metadata:
Filing Date: 20180925
Publication Date: 20201208
Grant Date: 20201208
Priority Date: 20170330
Inventors: HENZLER, STEPHAN
MENKHOFF, ANDREAS
EICHLER, THOMAS
WALTHES, WOLFGANG
BELITZER, ALEXANDER
WANG, YIFAN
Assignee: APPLE INC
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Family ID: 61563508