PATENT DOCUMENT

Publication Number: US-11204534-B2
Application Number: US-202017082613-A
Country: US
Kind Code: B2

Title: Displays with data lines that accommodate openings

Abstract:
To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Claims:
What is claimed is: 
     
       1. A display comprising:
 a substrate having an active area that includes an array of pixels and an opening within the active area, wherein the opening is surrounded by a border region; 
 a plurality of signal lines coupled to the array of pixels, wherein a subset of the plurality of signal lines are rerouted within the border region and wherein the subset of the plurality of signal lines has portions in the border region that are formed from a first metal layer that is formed in a first plane, a second metal layer that is formed in a second plane that is different than the first plane, and a third metal layer that is formed in a third plane that is different than the first and second planes; 
 a first conductive via that electrically connects the third metal layer to a first portion of the second metal layer; and 
 a second conductive via that electrically connects the first metal layer to a second portion of the second metal layer. 
 
     
     
       2. The display defined in  claim 1 , wherein the plurality of signal lines is a plurality of data lines. 
     
     
       3. The display defined in  claim 2 , further comprising:
 a plurality of gate lines that are at least partially formed from a fourth metal layer that is formed in a fourth plane that is different than the first, second, and third planes. 
 
     
     
       4. The display defined in  claim 3 , wherein the plurality of gate lines are at least partially formed from a fifth metal layer that is formed in a fifth plane that is different than the first, second, third, and fourth planes. 
     
     
       5. The display defined in  claim 4 , wherein the fourth and fifth planes are interposed between the first and third planes. 
     
     
       6. The display defined in  claim 1 , further comprising:
 at least a first dielectric layer interposed between the first metal layer and the second metal layer; and 
 at least a second dielectric layer interposed between the second metal layer and the third metal layer. 
 
     
     
       7. The display defined in  claim 6 , wherein the at least first dielectric layer comprises an organic planarization layer and an inorganic passivation layer. 
     
     
       8. The display defined in  claim 6 , wherein the at least second dielectric layer comprises an interlayer dielectric layer and a gate insulator layer. 
     
     
       9. The display defined in  claim 6 , further comprising:
 a buffer layer interposed between the third metal layer and the substrate. 
 
     
     
       10. A display comprising:
 a substrate having an active area that includes an array of pixels and an opening within the active area, wherein the opening is surrounded by a border region; and 
 a plurality of signal lines coupled to the array of pixels, wherein a subset of the plurality of signal lines are rerouted within the border region, wherein the subset of the plurality of signal lines has portions in the border region that are formed from a first metal layer that is formed in a first plane and a second metal layer that is formed in a second plane that is different than the first plane, wherein the first metal layer has a first portion formed in the border region and a second portion that is not electrically connected to the first portion, wherein the first portion of the first metal layer forms some of the subset of the plurality of signal lines, and wherein the second portion of the first metal layer forms at least a portion of a power supply distribution line. 
 
     
     
       11. The display defined in  claim 10 , wherein the second metal layer has a first portion formed in the border region and a second portion formed in the active area, wherein the first portion of the second metal layer forms some of the subset of the plurality of signal lines, and wherein the second portion of the second metal layer forms portions of the plurality of signal lines that are in the active area. 
     
     
       12. The display defined in  claim 10 , further comprising:
 a third metal layer that forms some of the subset of the plurality of signal lines in the border region and that is not present in the active area. 
 
     
     
       13. The display defined in  claim 12 , further comprising:
 an inorganic buffer layer formed on the substrate; and 
 a gate insulator layer formed on the inorganic buffer layer, wherein the third metal layer is interposed between the gate insulator layer and the inorganic buffer layer. 
 
     
     
       14. The display defined in  claim 13 , further comprising:
 first and second interlayer dielectric layers; 
 a fourth metal layer covered by the first interlayer dielectric layer; and 
 a fifth metal layer covered by the second interlayer dielectric layer. 
 
     
     
       15. The display defined in  claim 14 , further comprising:
 an inorganic passivation layer formed on the second interlayer dielectric layer, wherein the second metal layer is interposed between the inorganic passivation layer and the second interlayer dielectric layer; 
 a first organic planarization layer formed on the inorganic passivation layer; and 
 a second organic planarization layer formed on the first organic planarization layer, wherein the third metal layer is interposed between the first and second organic planarization layers. 
 
     
     
       16. A display comprising:
 a substrate having an active area that includes an array of pixels and an opening within the active area, wherein the opening is surrounded by a border region; 
 a plurality of gate lines coupled to the array of pixels, wherein a subset of the plurality of gate lines are rerouted within the border region and wherein the subset of the plurality of gate lines includes portions in the border region that are formed from a first metal layer that is formed in a first plane and a second metal layer that is formed in a second plane that is different than the first plane; and 
 a plurality of data lines coupled to the array of pixels, wherein a subset of the plurality of data lines are rerouted within the border region and wherein the subset of the plurality of data lines includes portions in the border region that are formed from a third metal layer that is formed in a third plane that is different than the first and second planes and a fourth metal layer that is formed in a fourth plane that is different than the first, second, and third planes. 
 
     
     
       17. The display defined in  claim 16 , wherein the first plane is interposed between the third and fourth planes and wherein the second plane is interposed between the third and fourth planes. 
     
     
       18. The display defined in  claim 16 , further comprising:
 at least a first dielectric layer interposed between the first metal layer and the second metal layer; and 
 at least a second dielectric layer interposed between the second metal layer and the third metal layer. 
 
     
     
       19. The display defined in  claim 16 , wherein one of the subset of the plurality of gate lines overlaps one of the subset of the plurality of data lines in the border region. 
     
     
       20. The display defined in  claim 16 , wherein a first data line of the subset of the plurality of data lines overlaps one of the subset of the plurality of gate lines and a second data line of the subset of the plurality of data lines in the border region.

Description:
This application is a continuation of non-provisional patent application Ser. No. 16/505,532, filed Jul. 8, 2019, which claims the benefit of provisional patent application No. 62/720,705, filed Aug. 21, 2018, which are hereby incorporated by reference herein in their entireties. 
    
    
     BACKGROUND 
     This relates generally to displays, and, more particularly, to displays with inactive areas. 
     Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to users. Displays such as organic light-emitting diode displays and liquid crystal displays have light-emitting active areas and inactive areas that do not emit light. If care is not taken, the inactive areas of the display may be larger than desired. 
     SUMMARY 
     A display may have an array of pixels in an active area. The display may include a first inactive area that surrounds the active area. The display may also include a second inactive area that is formed within the active area. The second inactive area may be formed by a physical opening in the display substrate that accommodates an electronic component. 
     The display may include data lines and gate lines that provide signals to the pixels in the display. The data lines and gate lines may need to be rerouted around the inactive area that is formed within the active area of the display. 
     To minimize the width of the non-light-emitting border region around the opening in the active area, data lines may be stacked in the border region. For example, data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. 
     Data line signals may be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display. The electrical connections of the supplemental data line to the data line segments may both be in the inactive area of the display. Alternatively, the electrical connections of the supplemental data line to the data line segments may instead both be in the active area of the display. In yet another arrangement, the electrical connection between the supplemental data line and one data line segment may be in the active area of the display and the electrical connection between the supplemental data line and the other data line segment may be in the inactive area of the display. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of an illustrative electronic device having a display in accordance with an embodiment. 
         FIG. 2  is a schematic diagram of an illustrative display in accordance with an embodiment. 
         FIG. 3  is a diagram of an illustrative pixel circuit in accordance with an embodiment. 
         FIG. 4  is a top view of an illustrative display having an active area that is surrounded by a first inactive area and that has a second inactive area contained within the active area in accordance with an embodiment. 
         FIG. 5  is a top view of an illustrative display having an opening in an active area and signal lines routed through the border region of the opening in accordance with an embodiment. 
         FIG. 6  is a cross-sectional side view of an active area of an illustrative display showing signal paths formed from metal layers in accordance with an embodiment. 
         FIG. 7  is a cross-sectional side view of an active area of an illustrative display showing how data lines formed from metal layers may be stacked in accordance with an embodiment. 
         FIG. 8  is a top view of an illustrative display showing how data lines may include first and second data line segments on opposing sides of an opening in the active area and a supplemental data line that is electrically connected to both the first and second data line segments in the inactive area of the display in accordance with an embodiment. 
         FIG. 9  is a cross-sectional side view of an illustrative display showing the supplemental data line of  FIG. 8  in accordance with an embodiment. 
         FIG. 10  is a top view of an illustrative display showing how data lines may include first and second data line segments on opposing sides of an opening in the active area and a supplemental data line that is electrically connected to both the first and second data line segments in the active area of the display in accordance with an embodiment. 
         FIG. 11  is a top view of an illustrative display showing how data lines may include data line segments on opposing sides of an opening in the active area and a supplemental data line that is electrically connected to one of the data line segments in the active area of the display and the other data line segment in the inactive area of the display in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Electronic devices may be provided with displays. A schematic diagram of an illustrative electronic device with a display is shown in  FIG. 1 . Device  10  of  FIG. 1  may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wrist-watch device (e.g., a watch with a wrist strap), a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user&#39;s head, or other wearable or miniature device, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, equipment that implements the functionality of two or more of these devices, or other electronic equipment. 
     As shown in  FIG. 1 , electronic device  10  may have control circuitry  16 . Control circuitry  16  may include storage and processing circuitry for supporting the operation of device  10 . The storage and processing circuitry may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in control circuitry  16  may be used to control the operation of device  10 . The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc. 
     Input-output circuitry in device  10  such as input-output devices  18  may be used to allow data to be supplied to device  10  and to allow data to be provided from device  10  to external devices. Input-output devices  18  may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device  10  by supplying commands through input-output devices  18  and may receive status information and other output from device  10  using the output resources of input-output devices  18 . 
     Input-output devices  18  may include one or more displays such as display  14 . Display  14  may be a touch screen display that includes a touch sensor for gathering touch input from a user or display  14  may be insensitive to touch. A touch sensor for display  14  may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements. 
     Control circuitry  16  may be used to run software on device  10  such as operating system code and applications. During operation of device  10 , the software running on control circuitry  16  may display images on display  14 . 
     Display  14  may be an organic light-emitting diode display, a display formed from an array of discrete light-emitting diodes each formed from a crystalline semiconductor die, or any other suitable type of display. Configurations in which the pixels of display  14  include light-emitting diodes are sometimes described herein as an example. This is, however, merely illustrative. Any suitable type of display may be used for device  10 , if desired. 
       FIG. 2  is a diagram of an illustrative display. As shown in  FIG. 2 , display  14  may include layers such as substrate layer  26 . Substrate layers such as layer  26  may be formed from rectangular planar layers of material or layers of material with other shapes (e.g., circular shapes or other shapes with one or more curved and/or straight edges). The substrate layers of display  14  may include glass layers, polymer layers, composite films that include polymer and inorganic materials, metallic foils, etc. 
     Display  14  may have an array of pixels  22  for displaying images for a user such as pixel array  28 . Pixels  22  in array  28  may be arranged in rows and columns. The edges of array  28  may be straight or curved (i.e., each row of pixels  22  and/or each column of pixels  22  in array  28  may have the same length or may have a different length). There may be any suitable number of rows and columns in array  28  (e.g., ten or more, one hundred or more, or one thousand or more, etc.). Display  14  may include pixels  22  of different colors. As an example, display  14  may include red pixels, green pixels, and blue pixels. If desired, a backlight unit may provide backlight illumination for display  14 . 
     Display driver circuitry  20  may be used to control the operation of pixels  22 . Display driver circuitry  20  may be formed from integrated circuits, thin-film transistor circuits, and/or other suitable circuitry. Illustrative display driver circuitry  20  of  FIG. 2  includes display driver circuitry  20 A and additional display driver circuitry such as gate driver circuitry  20 B. Gate driver circuitry  20 B may be formed along one or more edges of display  14 . For example, gate driver circuitry  20 B may be arranged along the left and right sides of display  14  as shown in  FIG. 2 . 
     As shown in  FIG. 2 , display driver circuitry  20 A (e.g., one or more display driver integrated circuits, thin-film transistor circuitry, etc.) may contain communications circuitry for communicating with system control circuitry over signal path  24 . Path  24  may be formed from traces on a flexible printed circuit or other cable. The control circuitry may be located on one or more printed circuits in electronic device  10 . During operation, the control circuitry (e.g., control circuitry  16  of  FIG. 1 ) may supply circuitry such as a display driver integrated circuit in circuitry  20  with image data for images to be displayed on display  14 . Display driver circuitry  20 A of  FIG. 2  is located at the top of display  14 . This is merely illustrative. Display driver circuitry  20 A may be located along the bottom edge of display  14 , at both the top and bottom of display  14 , or in other portions of device  10 . 
     To display the images on pixels  22 , display driver circuitry  20 A may supply corresponding image data to data lines D while issuing control signals to supporting display driver circuitry such as gate driver circuitry  20 B over signal paths  30 . With the illustrative arrangement of  FIG. 2 , data lines D run vertically through display  14  and are associated with respective columns of pixels  22 . 
     Gate driver circuitry  20 B (sometimes referred to as gate line driver circuitry or horizontal control signal circuitry) may be implemented using one or more integrated circuits and/or may be implemented using thin-film transistor circuitry on substrate  26 . Horizontal control lines G (sometimes referred to as gate lines, scan lines, emission control lines, etc.) run horizontally through display  14 . Each gate line G is associated with a respective row of pixels  22 . If desired, there may be multiple horizontal control lines such as gate lines G associated with each row of pixels (e.g., a first gate line signal GI and a second gate line signal GW, one or more emission control signals, etc.). Individually controlled and/or global signal paths in display  14  may also be used to distribute other signals (e.g., power supply signals, etc.). 
     Gate driver circuitry  20 B may assert control signals on the gate lines G in display  14 . For example, gate driver circuitry  20 B may receive clock signals and other control signals from circuitry  20 A on paths  30  and may, in response to the received signals, assert a gate line signal on gate lines G in sequence, starting with the gate line signal G in the first row of pixels  22  in array  28 . As each gate line is asserted, data from data lines D may be loaded into a corresponding row of pixels. In this way, control circuitry such as display driver circuitry  20 A and  20 B may provide pixels  22  with signals that direct pixels  22  to display a desired image on display  14 . Each pixel  22  may have a light-emitting diode and circuitry (e.g., thin-film circuitry on substrate  26 ) that responds to the control and data signals from display driver circuitry  20 . 
     An illustrative pixel circuit of the type that may be used for each pixel  22  in array  28  is shown in  FIG. 3 . In the example of  FIG. 3 , pixel circuit  22  has seven transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and TD and one capacitor Cst, so pixel circuit  22  may sometimes be referred to as a  7 T 1 C pixel circuit. Other numbers of transistors and capacitors may be used in pixels  22  if desired (e.g., fewer transistors, more transistors, more capacitors, etc.). The transistors may be p-channel transistors (e.g., p-channel metal-oxide-semiconductor transistors as shown in  FIG. 3 ) and/or may be n-channel transistors or other types of transistors. The active regions of thin-film transistors for pixel circuit  22  and other portions of display  14  may be formed from silicon (e.g., polysilicon channel regions), semiconducting oxides (e.g., indium gallium zinc oxide channel regions), or other suitable semiconductor thin-film layers. 
     As shown in  FIG. 3 , pixel circuit  22  includes light-emitting diode  44  (e.g., an organic light-emitting diode, a crystalline micro-light-emitting diode die, etc.). Light-emitting diode  44  may emit light  46  in proportion to the amount of current I that is driven through light-emitting diode  44  by transistor TD. Transistor TD, transistor T 4 , transistor T 5 , and light-emitting diode  44  may be coupled in series between respective power supply terminals (see, e.g., positive power supply terminal ELVDD and ground power supply terminal ELVSS). Transistor TD may have a source terminal coupled to node Nb, a drain terminal coupled to transistor T 5 , and a gate terminal coupled to node Na. The voltage on node Na at the gate of transistor TD controls the amount of current I that is produced by transistor TD. This current is driven through light-emitting diode  44 , so transistor TD may sometimes be referred to as a drive transistor. 
     Transistors T 4  and T 5  can be turned off to interrupt current flow between transistor TD and diode  44  and transistors T 4  and T 5  may be turned on to enable current flow between transistor TD and diode  44 . Emission enable control signal EM may be applied to the gates of transistors T 4  and T 5  from a shared gate line. During operation, transistors T 4  and T 5  are controlled by emission enable control signal EM and are therefore sometimes referred to as emission transistors or emission enable transistors. Control signals GW and GI which may sometimes be referred to as switching transistor control signals, scan signals, or gate line signals (e.g., gate initialization and gate write signals, gate signals, etc.), are applied to the gates of switching transistors T 1 , T 2 , T 3 , and T 6  and control the operation of transistors T 1 , T 2 , T 3 , and T 6 . 
     Control signals EM, GI, and GW may be controlled by display driver circuitry  20  to place pixels  22  of display  14  in different states during the operation of display  14 . During these different states, image data is loaded into pixels  22  and pixels  22  use light-emitting diodes  44  to emit light  46  in proportion to the loaded pixel data. To minimize threshold voltage variations due to differences in transistor history (e.g., historical Vgs values), each of the pixels can be conditioned by deliberately applying a known voltage stress to drive transistors TD (sometimes referred to as on-bias stress). This example of circuitry used to form each pixel is merely illustrative. In general, each pixel may be formed from any desired circuitry. 
       FIG. 4  is a top view of an illustrative display having an inactive area portion surrounded by the active area of the display. As shown in  FIG. 4 , substrate  26  has an active area AA and inactive areas IA 1  and IA 2 . In the active area, substrate  26  includes pixels (e.g., pixels of the type shown in  FIG. 3 ) that emit light to display images. The inactive area does not contain any pixels and does not display images. The inactive area may include display circuitry such as display driver circuitry  20 A and gate driver circuitry  20 B in  FIG. 2 , for example. This display circuitry may be formed in the first inactive area IA 1  of display  14 . Inactive area IA 1  borders the active area and extends around the periphery of the active area. 
     The display may also include an isolated inactive area IA 2  that is formed within an opening in the active area. In other words, inactive area IA 2  is contained within the active area AA. Inactive area IA 2  is completely laterally surrounded (e.g., within the XY-plane) by active area AA. Inactive area IA 2  may sometimes be referred to as an island-shaped inactive area. There may be a physical hole in substrate  26  within inactive area IA 2  or substrate  26  may be transparent within inactive area IA 2  (with pixel components omitted in the inactive area IA 2 ). An electrical component such as a speaker, camera, light-emitting diode (e.g., a status indicator), light sensor, proximity sensor, strain gauge, magnetic sensor, pressure sensor, force sensor, temperature sensor, or other sensor, button, touch-sensitive component, microphone or other audio component, or other electrical device that produces output and/or gathers input, may be mounted in the inactive area IA 2 . 
     Incorporating an inactive area within the active area of the display may require rerouting of signal lines within the display.  FIG. 5  is a top view of an illustrative display with an opening in the active area and rerouted signals around the opening. As shown in  FIG. 5 , inactive area IA 2  is formed within the active area of the display (with IA 2  being surrounded on all sides by pixels  22 ). Inactive area IA 2  may include a physical opening  52 . Opening  52  may be a physical hole in the display substrate, for example. This example is merely illustrative and opening  52  may instead be a transparent window in the display that does not contain any display pixel or display signal routing components. Opening  52  may accommodate one or more electronic components  54 . Component  54  may be an input-output component such as a speaker, camera, light-emitting diode (e.g., a status indicator), light sensor, proximity sensor, strain gauge, magnetic sensor, pressure sensor, force sensor, temperature sensor, or other sensor, button, touch-sensitive component, microphone or other audio component, or other electrical device that produces output and/or gathers input. In one example, component  54  may occupy the space vacated by physical hole  52 . In another example, component  54  may be positioned below the display substrate with opening  52  and receive external stimulus (e.g., light) through opening  52 . In embodiments where a transparent window is formed in place of opening  52 , the component  54  may be formed underneath the transparent window and receive light through the window, as one example. 
     To minimize the amount of non-light-emitting area in the display, it is desirable for the dimensions of physical opening  52  to define the dimensions of the inactive area IA 2 . However, there may be a non-light-emitting border  56  formed around physical opening  52  to allow space for routing of signal lines within the display. For example, some data lines such as data line D 1  are uninterrupted by the inactive area IA 2 . These data lines may extend vertically across the display without the need to be rerouted around physical opening  52 . Similarly, some gate lines such as gate line G 1  are uninterrupted by the inactive area IA 2 . These gate lines may extend horizontally across the display without the need to be rerouted around physical opening  52 . However, some of the data lines and gate lines will be interrupted by physical opening  52  and therefore need to be rerouted around physical opening  52 . 
     In  FIG. 5 , data line D 2  is interrupted by physical opening  52 . Data line D 2  may have a portion that extends vertically, coupling to each pixel in a given column of pixels in the display. Data line D 2  also has a rerouted portion D 2 -R that curves around physical opening  52  to connect pixel  22 - 1  in the given column of pixels to pixel  22 - 2  in the given column of pixels on the opposite side of the physical opening. Rerouted portion D 2 -R may be formed in a separate plane (and from a separate metal layer) than the vertical portions of data line D 2 . Gate line G 2  is also interrupted by physical opening  52 . Gate line G 2  may have a portion that extends horizontally, coupling to each pixel in a given row of pixels in the display. Gate line G 2  then has a rerouted portion G 2 -R that curves around physical opening  52  to connect pixel  22 - 3  in the given row of pixels to pixel  22 - 4  in the given row of pixels on the opposite side of the physical opening. Rerouted portion G 2 -R may be formed in a separate plane (and from a separate metal layer) than the horizontal portions of gate line G 2 . 
     The rerouted portions of the signal lines may be formed in non-light-emitting border  56  around physical opening  52 . The larger the size of physical opening  52 , the more signal lines will have to be rerouted around physical opening within border  56 . This may undesirably increase the width  58  of border  56 . To help minimize width  58 , signal lines may be stacked in border region  56  (thus reducing the lateral area required to accommodate all of the rerouted signal lines). 
       FIG. 6  is a cross-sectional side view of a portion of a display that has stacked data lines in a border region  56  around a physical opening in an active area (similar to as shown in  FIG. 5 ). The portion of the display shown in  FIG. 6  is positioned in the active area (away from the physical opening), meaning that rerouting of the data lines is not required and the data lines therefore do not need to be stacked. As shown in  FIG. 6 , display  14  includes layers formed on substrate layer  26 . Dielectric layers such as buffer layer  64  and gate insulator layer  66  may be formed on substrate  26 . Buffer layer  64  may be an inorganic buffer layer, for example. Additional interlayer dielectric layers  68  and  70  may be formed over gate insulator layer  66 . A first metal layer  78  may be formed on gate insulator  66  and covered by interlayer dielectric layer  68 . Metal layer  78  may serve as a gate line (e.g., a gate line G in  FIG. 2 ) for display  14 . A second metal layer  80  may be formed on interlayer dielectric layer  68  and covered by interlayer dielectric layer  70 . Metal layer  80  may serve as a gate line (e.g., a gate line G in  FIG. 2 ) for display  14 . Metal layers  78  and  80  may both serve as gate lines for a single row of pixels within the display. For example, metal layer  78  may provide signal GW (see  FIG. 3 ) to pixels in the row whereas metal layer  80  may provide signal GI (see  FIG. 3 ) to pixels in the row. 
     An additional metal layer (metal layer  82 ) may be formed over interlayer dielectric layer  70 . Metal layer  82  (SD 1 ) may serve as a data line (e.g., data line D in  FIG. 2 ) for display  14 . Metal layer  82  may be covered by passivation layer  72 . Passivation layer  72  may be formed from an inorganic material such as silicon nitride or silicon dioxide. Passivation layer  72  may be formed from any other desired material. Organic planarization layers  74  and  76  may be formed over passivation layer  72 . Organic planarization layers  74  and  76  may be formed from any desired material. Organic planarization layers  74  and  76  may be formed from the same material or from different materials. 
     Metal layer  84  (SD 2 ) may be formed between organic planarization layers  74  and  76 . In portions of the display other than the border of the physical hole in the substrate, metal layer  84  may serve as a power supply distribution line for display  14 . For example, metal layer  84  may form a positive power supply distribution line ELVDD (as shown in  FIG. 3 ) or may form a ground power supply distribution line ELVSS (as shown in  FIG. 3 ). 
     As previously mentioned, to minimize the width of border region  56  around opening  52  (see  FIG. 5 ), data lines may be stacked in border region  56 . As shown in  FIG. 6 , in the active area of the display the data lines may be formed by metal layer  82 . To allow the data lines to be stacked in border region  56 , vias may electrically connect metal layer  82  (with data line signals) to additional metal layers in the display. The data lines may therefore have first portions formed by metal layer  82  and additional portions formed from additional metal layers within the display. 
       FIG. 7  is a cross-sectional side view of border region  56  of the display in which data lines are stacked.  FIG. 7  shows substrate  26  with buffer layer  64 , gate insulator  66 , interlayer dielectric layers  68  and  70 , passivation layer  72 , and organic planarization layers  74  and  76 , similar to as in  FIG. 6 . Metal layers  78  and  80  are formed similar to as in  FIG. 6 . However,  FIG. 7  shows opening  52  in substrate  26 . In the embodiment of  FIG. 7 , opening  52  is a physical opening in the substrate and input-output component  54  is formed within the opening. In an alternate embodiment, opening  52  may instead be a transparent window and input-output component  54  may be formed beneath the transparent window. 
     In border region  56 , metal layer  82  may have multiple portions that each carry different data line signals. For example, portion  82 - 1  carries a first data line signal, portion  82 - 2  carries a second data line signal, and portion  82 - 3  carries a third data line signal. In other words, each portion forms part of a respective data line D. Metal layer  82 - 1  may remain above interlayer dielectric layer  70 . However, metal layers  82 - 2  and  82 - 3  may be electrically connected to additional metal layers using vias. For example, metal layer  82 - 2  may be electrically connected to metal layer  84  using conductive via  86 . In this way, the data line signal is electrically connected to metal layer  84  from metal layer  82 - 2 . Therefore, in this portion of the display, metal layer  84  serves as a data line portion instead of a positive power supply distribution line ELVDD as in  FIG. 6 . Conductive via  86  may be formed form the same material (and in the same deposition step) as metal layer  84  if desired. 
     Using both metal layers  82  and  84  for data lines in border region  56  can help reduce the width of border region  56 . However, additional minimizing of the border may be achieved by incorporating an additional metal layer that serves as a data line portion in border region  56 . As shown in  FIG. 7 , metal layer  88  may be formed between gate insulator  66  and buffer layer  64 . Metal layer  82 - 3  may be electrically connected to metal layer  88  using conductive via  90 . In this way, the data line signal is electrically connected to metal layer  88  from metal layer  82 - 3 . Therefore, in this portion of the display, metal layer  88  serves as a data line portion. In the embodiment shown in  FIG. 7 , conductive via  90  has a first portion formed from the same material (and in the same deposition step) as metal layer  82  and a second portion formed from the same material (and in the same deposition step) as metal layer  78 . This example is merely illustrative and conductive via  90  may be formed from any desired number and type of layers of metal. 
     Incorporating metal layer  88  to serve as a data line in border region  56  further reduces the width of border region  56 . If desired, to avoid cross-talk between the overlapped data lines (e.g., metal layer  84 , metal layer  82 - 1 , and metal layer  88  in  FIG. 7  all serving as data lines), two or more of the data lines may follow interlaced paths that reduce the overlap area between the data lines. However, the separation between metal layer  88  and metal layer  84  may be sufficient to protect these data lines from cross-talk. Therefore, metal layer  88  and metal layer  84  may be fully overlapping in border region  56 . Therefore, incorporating metal layer  88  as an additional data line requires no additional border width. 
     Border region  56  of display  14  may also include dam structures  92 . Dam structures  92  may include a portion of organic planarization layer  76 , an additional dielectric layer  94 , and a spacer layer  96 . Additional dielectric layer  94  may be formed from the same material (and in the same deposition step) as a pixel definition layer (PDL) for the display. Spacer layer  96  may be a photospacer layer. These examples of dam structures  92  are merely illustrative. If desired, dam structures  92  may optionally be omitted. Dam structures  92  may also optionally be formed on the inner edge of border region  56 . For example, in  FIG. 7  dam structures  92  are formed on the outer edge of border region  56  and metal layers  84 ,  82 - 1 , and  88  are interposed between dam structures  92  and opening  52 . Alternatively, however, dam structures  92  may be formed on the inner edge of border region  56  and may be interposed between opening  52  and metal layers  84 ,  82 - 1 , and  88 . 
     The example of  FIGS. 5-7  in which data lines are rerouted around physical opening  52  (and stacked in border region  56  around physical opening  52 ) is one option for providing data line signals and gate line signals to pixels on all sides of the physical opening.  FIG. 8  shows an alternate arrangement in which supplemental data line paths are used to provide the data line signals to pixels on an opposite side of the physical opening. 
       FIG. 8  is a top view of an illustrative display having a substrate  26  with a physical opening  52 . As shown in  FIG. 8 , display  14  may have a number of data lines D that provide signals to columns of pixels within the display. Some of the data lines, such as data line D 1 , are uninterrupted by physical opening  52 . These data lines may therefore extend across the display to provide signals to each pixel in a column (similar to as shown in  FIG. 2 , for example). 
     Some of the data lines, such as data lines D 2 , may be interrupted by physical opening  52 . To provide the requisite data line signals to pixels on both sides of physical opening  52 , each of the data lines D 2  may have a first data line segment  102  (sometimes referred to as a data line portion) on a first side of the physical opening and a second data line segment  104  (sometimes referred to as a data line portion) on a second, opposing side of the physical opening. Data line segments  102  and  104  are not electrically connected by rerouting a portion of the data line around the border of the physical opening as in  FIG. 5 . Instead, a supplemental data line  106  (sometimes referred to as supplemental data line path  106 , supplemental data line segment  106 , etc.) is provided. 
     Supplemental data line  106  is electrically connected to data line segment  102  in the inactive area (IA 1 ) of the display at electrical connection  108 . Supplemental data line  106  is then routed through the active area (AA) of the display (e.g., between pixels) to the inactive area of the display on the opposing side of the display. There, the supplemental data line  106  is electrically connected to data line segment  104  in the inactive area of the display at electrical connection  110 . In this way, signals from data line segment  102  are provided to data line segment  104  without requiring rerouting of the data line in the border of physical opening  52 . Therefore, in  FIG. 8 , physical opening  52  can have a very small border region (because no data lines are rerouted through the border region). The gate lines in the display may optionally still be rerouted through the border region of the physical opening. In another possible embodiment, date driver circuitry may be provided on both sides of the display, removing the need to route the gate lines around the physical opening. 
       FIG. 9  is a cross-sectional side view of the inactive area of the display in  FIG. 8  showing supplemental data lines  106 . As shown in  FIG. 9 , layers formed on substrate layer  26  include dielectric layers such as buffer layer  64  and gate insulator layer  66 . Additional interlayer dielectric layers  68  and  70  may be formed over gate insulator layer  66 . A first metal layer  78  may be formed on gate insulator  66  and covered by interlayer dielectric layer  68 . A second metal layer  80  may be formed on interlayer dielectric layer  68  and covered by interlayer dielectric layer  70 . As shown in  FIG. 6 , in the active area of the display metal layers  78  and  80  serve as gate lines (G) for display  14 . However, in the inactive area of the display as shown in  FIG. 9 , metal layers  78  and  80  may serve as signal paths for data line signals (e.g., metal layers  78  and  80  help provide signals to data lines D from a display driver circuit). 
     An additional metal layer (metal layer  82 ) may be formed over interlayer dielectric layer  70 . As shown in connection with  FIG. 6 , in the active area of the display metal layer  82  (SD 1 ) may serve as a data line (e.g., data line D in  FIG. 2 ) for display  14 . However, in the inactive area of the display as shown in  FIG. 9 , metal layer  82  may serve as a power supply distribution line for display  14 . For example, metal layer  82  may form a positive power supply distribution line ELVDD (as shown in  FIG. 3 ) or may form a ground power supply distribution line ELVSS (as shown in  FIG. 3 ). Metal layer  82  may be covered by passivation layer  72 . Passivation layer  72  may be formed from an inorganic material such as silicon nitride or silicon dioxide. Passivation layer  72  may be formed from any other desired material. Organic planarization layers  74  and  76  may be formed over passivation layer  72 . Organic planarization layers  74  and  76  may be formed from any desired material. Organic planarization layers  74  and  76  may be formed from the same material or from different materials. 
     Metal layer  84  (SD 2 ) may be formed between organic planarization layers  74  and  76 . In the inactive area of the display as shown in  FIG. 9 , metal layer  82  may serve as a power supply distribution line for display  14  (similar to as in the active area as shown in FIG.  6 ). For example, metal layer  82  may form a positive power supply distribution line ELVDD (as shown in  FIG. 3 ) or may form a ground power supply distribution line ELVSS (as shown in  FIG. 3 ). In one possible embodiment, both metal layers  82  and  84  form a positive power supply distribution line ELVDD in the inactive area shown in  FIG. 9 . 
     Supplemental data line  106  may be formed from a metal layer that is formed over passivation layer  72 . Organic planarization layer  74  may be formed over supplemental data line  106 . Supplemental data line  106  may be electrically connected to metal layer  80  (which provides the data line signal) using via  112 . In other words, conductive via  112  forms electrical connection  108  between supplemental data line  106  and data line segment  102 . In  FIG. 9 , conductive via  112  is formed from the same material (and in the same deposition step) as supplemental data line  106 . This example is merely illustrative, and conductive via  112  may be formed from any desired number and type of layers of metal. 
     Supplemental data line  106  (e.g., a metal layer between passivation layer  72  and organic planarization layer  74 ) may be routed through the active area of the display. On the other side of the display, another electrical connection ( 110 ) may electrically connect the supplemental data line to data line segment  104 . 
     This example of a metal layer between passivation layer  72  and organic planarization layer  74  being used to form supplemental data line  106  is merely illustrative. If desired, supplemental data line  106  may be formed from another metal layer in the display, may be formed from multiple metal layers within the display, etc. However, using the metal layer between passivation layer  72  and organic planarization layer  74  (and between ELVDD signal paths formed by metal layers  82  and  84 ) may prevent cross-talk. 
     In the example of  FIG. 8 , a supplemental data line is routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display. In  FIG. 8 , the electrical connections of the supplemental data line to the data line segments are both in the inactive area of the display. However, this example is merely illustrative. The electrical connections of the supplemental data line to the data line segments may instead both be in the active area of the display (as in  FIG. 10 ). In yet another embodiment, the electrical connection between the supplemental data line and one data line segment may be in the active area of the display and the electrical connection between the supplemental data line and the other data line segment may be in the inactive area of the display (as in  FIG. 11 ). 
       FIG. 10  is a top view of an illustrative display having a substrate  26  with a physical opening  52 . As shown in  FIG. 10 , display  14  may have a number of data lines D that provide signals to columns of pixels within the display. Some of the data lines, such as data line D 1 , are uninterrupted by physical opening  52 . These data lines may therefore extend across the display to provide signals to each pixel in a column (similar to as shown in  FIG. 2 , for example). 
     Some of the data lines, such as data lines D 2 , may be interrupted by physical opening  52 . To provide the requisite data line signals to pixels on both sides of physical opening  52 , each of the data lines D 2  may have a first data line segment  102  (sometimes referred to as a data line portion) on a first side of the physical opening and a second data line segment  104  (sometimes referred to as a data line portion) on a second, opposing side of the physical opening. Data line segments  102  and  104  are not electrically connected by rerouting a portion of the data line around the border of the physical opening as in  FIG. 5 . Instead, a supplemental data line  106  is provided. 
     Supplemental data line  106  is electrically connected to data line segment  102  in the active area (AA) of the display at electrical connection  108 . Supplemental data line  106  is then routed through the active area of the display to be electrically connected to data line segment  104  at electrical connection  110  in the active area of the display. In this way, signals from data line segment  102  are provided to data line segment  104  without requiring rerouting of the data line in the border of physical opening  52 . Therefore, in  FIG. 10 , physical opening  52  can have a very small border region (because no data lines are rerouted through the border region). The gate lines in the display may optionally still be rerouted through the border region of the physical opening. In another possible embodiment, date driver circuitry may be provided on both sides of the display, removing the need to route the gate lines around the physical opening. 
     In  FIG. 10 , supplemental data lines  106  may be formed from a layer of metal between passivation layer  72  and organic planarization layer  74  (as shown in  FIG. 9 ) or another desired layer of metal. Horizontal portions of supplemental data lines  106  such as horizontal portion  114  may be routed above a signal line that provides an emission enable control signal EM to the pixels (see  FIG. 3  with emission enable control signal EM applied to the gates of transistors T 4  and T 5 ). The signal line that provides emission enable control signal EM may sometimes be referred to as a gate line or an emission line. Routing the horizontal portions of supplemental data lines  106  above a gate line that provides emission enable control signal EM may mitigate cross-talk. Vertical portions of supplemental data lines  106  such as vertical portion  116  may be routed between positive power signal supply paths (e.g., ELVDD supply lines) formed from metal layers  82  and  84  (similar to as shown in  FIG. 9 ) to mitigate cross-talk. 
     In some embodiments, forming the electrical connections between the supplemental data lines and both data line segments in the active area of the display (as in  FIG. 10 ) may be difficult. For example, if physical opening  52  is large (meaning a large number of data lines will be interrupted and therefore a large number of supplemental data lines will be required) and/or if the physical opening is positioned close to the edge of the active area (meaning that space for routing the supplemental data lines to and making electrical connections  110  will be limited), it may be desirable to form electrical connections between the supplemental data lines and one of the data line segments in the inactive area of the display.  FIG. 11  shows an embodiment of this type. 
       FIG. 11  is a top view of an illustrative display having a substrate  26  with a physical opening  52 . As shown in  FIG. 11 , display  14  may have a number of data lines D that provide signals to columns of pixels within the display. Some of the data lines, such as data line D 1 , are uninterrupted by physical opening  52 . Some of the data lines, such as data lines D 2 , may be interrupted by physical opening  52 . To provide the requisite data line signals to pixels on both sides of physical opening  52 , each of the data lines D 2  may have a first data line segment  102  on a first side of the physical opening and a second data line segment  104  on a second, opposing side of the physical opening. Data line segments  102  and  104  are not electrically connected by rerouting a portion of the data line around the border of the physical opening as in  FIG. 5 . Instead, a supplemental data line  106  is provided. 
     Supplemental data line  106  is electrically connected to data line segment  102  in the active area (AA) of the display at electrical connection  108 . Supplemental data line  106  is then routed through the active area of the display to be electrically connected to data line segment  104  at electrical connection  110  in the inactive area of the display. In this way, signals from data line segment  102  are provided to data line segment  104  without requiring rerouting of the data line in the border of physical opening  52 . Therefore, in  FIG. 11 , physical opening  52  can have a very small border region (because no data lines are rerouted through the border region). The gate lines in the display may optionally still be rerouted through the border region of the physical opening. In another possible embodiment, date driver circuitry may be provided on both sides of the display, removing the need to route the gate lines around the physical opening. 
     In  FIG. 11 , supplemental data lines  106  may be formed from a layer of metal between passivation layer  72  and organic planarization layer  74  (as shown in  FIG. 9 ) or another desired layer of metal. As discussed in connection with  FIG. 10 , horizontal portions of supplemental data lines  106  such as horizontal portion  114  may be routed above a signal line that provides an emission enable control signal EM to the pixels. Vertical portions of supplemental data lines  106  such as vertical portion  116  may be routed between positive power signal supply paths (e.g., ELVDD supply lines) formed from metal layers  82  and  84  (similar to as shown in  FIG. 9 ). 
     Two or more of the aforementioned arrangements may be used for data lines in a single display if desired. Each data line may use any of the aforementioned arrangements to provide data signals to pixels on both sides of a physical opening within the active area. 
     The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Metadata:
Filing Date: 20201028
Publication Date: 20211221
Grant Date: 20211221
Priority Date: 20180821
Inventors: YEH, SHIN-HUNG
RIEUTORT-LOUIS, WARREN S.
JAMSHIDI ROUDBARI, ABBAS
LEE, CHIEN-YA
TSAI, LUN
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G2300/0426", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02F1/136286", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3233", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02F1/13629", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/20", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2300/0426", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0262", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0861", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0861", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02F1/13629", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0262", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02F1/136286", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0426", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0404", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L27/3276", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/20", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2300/0404", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L27/3246", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02F1/136286", "inventive": true, "first": true, "tree": "[]"}, {"code": "G02F1/13629", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0404", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02F1/13629", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/044", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/124", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3233", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10K59/122", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/041", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K50/844", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/122", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02F1/136286", "inventive": true, "first": true, "tree": "[]"}, {"code": "G02F1/136286", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09F9/30", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3225", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/36", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 69586060