PATENT DOCUMENT

Publication Number: US-7852046-B2
Application Number: US-54323609-A
Country: US
Kind Code: B2

Title: Power source switchover apparatus and method

Abstract:
An apparatus for switching from a first power supply to a second power supply. Such an apparatus may determine which of the first and second power supplies has a greater voltage, and may power a device from the power supply having the greater voltage or charge. A single boost converter may be used regardless of which power supply is providing power.

Claims:
1. A battery-switching apparatus for switching between at least a first battery and a second battery, comprising:
 a first battery compartment having a first positive terminal and a first negative terminal; 
 a second battery compartment having a second positive terminal and a second negative terminal; 
 a comparator operatively electrically connected to the first negative terminal, electrically connected to the second negative terminal, configured to compare a first voltage at the first negative terminal with a second voltage at the second negative terminal, and configured to generate an output based on such comparison; and 
 a single boost converter electrically connected to each of the first and second battery compartments, the boost converter operative to draw power from a one of the first and second battery compartments based on the output of the comparator; 
 a first transistor operatively connected to the comparator; and 
 a second transistor operatively connected to the comparator, wherein:
 the first and second transistors switch states according to the output of the comparator; 
 the output of the comparator is electrically connected to a gate terminal of the first transistor and to a gate terminal of the second transistor; 
 the first negative terminal is electrically connected to a drain terminal of the first transistor; and 
 the second negative terminal is electrically connected to a drain terminal of the second transistor. 
 
 
     
     
       2. The battery-switching apparatus of  claim 1 , wherein the comparator is operative to switch to one of the first and second battery compartments having a highest voltage based on the comparison in order to supply power to the boost converter. 
     
     
       3. The battery-switching apparatus of  claim 1 , wherein:
 the first and second transistors are each electrically connected to the output of the comparator; and 
 the first transistor switches off when the second transistor switches on. 
 
     
     
       4. A battery-switching apparatus for switching between at least a first battery and a second battery, comprising:
 a first battery compartment having a first positive terminal and a first negative terminal; 
 a second battery compartment having a second positive terminal and a second negative terminal; 
 a comparator operatively electrically connected to the first negative terminal, electrically connected to the second negative terminal, configured to compare a first voltage at the first negative terminal with a second voltage at the second negative terminal, and configured to generate an output based on such comparison; and 
 a single boost converter electrically connected to each of the first and second battery compartments, the boost converter operative to draw power from a one of the first and second battery compartments based on the output of the comparator, wherein:
 the positive terminal of the first battery compartment is connected directly to a first common node; 
 the positive terminal of the second battery compartment is connected directly to the first common node; 
 the negative terminal of the first battery compartment is connected to a first input of the comparator through a second common node; and 
 the negative terminal of the second battery compartment is connected to a second input of the comparator through a third common node. 
 
 
     
     
       5. The battery-switching apparatus of  claim 4 , wherein:
 a voltage at the second common node exceeds a voltage at the third common node when a cell voltage of a first battery in the first battery compartment exceeds a cell voltage of a second battery in the second battery compartment. 
 
     
     
       6. The battery-switching apparatus of  claim 4 , wherein:
 a voltage at the third common node exceeds a voltage at the second common node when a cell voltage of the second battery exceeds a cell voltage of the first battery. 
 
     
     
       7. The battery-switching apparatus of  claim 4 , further comprising:
 a first transistor operatively connected to the comparator; 
 a second transistor operatively connected to the comparator, wherein the first and second transistors switch states according to the output of the comparator; and 
 a third transistor electrically connected to the second transistor and to the third common node. 
 
     
     
       8. The battery-switching apparatus of  claim 4 , further comprising:
 a first pullup resistor electrically connected between the first common node and the second common node; and 
 a second pullup resistor electrically connected between the first common node and the third common node. 
 
     
     
       9. The battery-switching apparatus of  claim 8 , wherein:
 the first pullup resistor is configured to establish a first defined voltage at the second common node when a battery is not installed in the first battery compartment; and 
 the second pullup resistor is configured to establish a second defined voltage at the third common node when a battery is not installed in the second battery compartment. 
 
     
     
       10. The battery-switching apparatus of  claim 4 , further comprising:
 a first transistor operatively connected to the comparator; 
 a second transistor operatively connected to the comparator; wherein the first and second transistors switch states according to the output of the comparator; and 
 a capacitor electrically connected to the first common node and to a third transistor such that the capacitor and the third transistor are in series. 
 
     
     
       11. The battery-switching apparatus of  claim 10 , further comprising:
 a peak detector operatively connected to an output of the boost converter; and 
 a voltage detector operatively connected to the output of the peak detector, the third transistor operatively connected to an output of the voltage detector. 
 
     
     
       12. The battery-switching apparatus of  claim 11 , wherein the voltage detector is configured to output a bias voltage to the third transistor once a voltage output from the peak detector reaches a predetermined threshold of the voltage detector. 
     
     
       13. The battery-switching apparatus of  claim 12 , wherein the bias voltage is invariant. 
     
     
       14. The battery-switching apparatus of  claim 4 , further comprising:
 a first capacitor electrically connected to the second common node at a first side and electrically connected to a ground at a second side, the first capacitor operative to charge from a cell voltage of the first battery; and 
 a second capacitor electrically connected to the third common node at a first side and electrically connected to the ground at a second side, the second capacitor is operative to charge from a cell voltage of the second battery. 
 
     
     
       15. The battery-switching apparatus of  claim 14 , wherein:
 as the first capacitor charges, a voltage of the second common node rises; and 
 as the second capacitor charges, a voltage of the third common node rises. 
 
     
     
       16. The battery-switching apparatus of  claim 15 , wherein:
 as the cell voltage of the first battery drops, the charge of the first capacitor drops and the voltage of the second common node drops; and 
 as the cell voltage of the second battery drops, the charge of the second capacitor drops and the voltage of the third common node drops. 
 
     
     
       17. The battery-switching apparatus of  claim 4 , further comprising:
 a first transistor operatively connected to the comparator; 
 a second transistor operatively connected to the comparator, wherein the first and second transistors switch states according to the output of the comparator; 
 an output transistor electrically connected to an output of the boost converter; and 
 a third transistor operatively connected to the output transistor. 
 
     
     
       18. The battery-switching apparatus of  claim 17 , further comprising:
 a peak detector operatively connected to the output of the boost converter; and 
 a voltage detector operatively connected to the output of the peak detector and operatively connected to the third transistor. 
 
     
     
       19. The battery-switching apparatus of  claim 18 , wherein the voltage detector is configured to output a bias voltage to the third transistor once a voltage output from the peak detector reaches a predetermined threshold of the voltage detector. 
     
     
       20. The battery-switching apparatus of  claim 19 , wherein the bias voltage is invariant. 
     
     
       21. The battery-switching apparatus of  claim 19 , wherein:
 the third transistor is operative to switch on the output transistor upon receipt of the bias voltage from the voltage detector; 
 an output voltage at an output node is zero until the output transistor switches on; and 
 the output voltage at the output node exceeds zero after the output transistor switches on. 
 
     
     
       22. A method for switching between at least a first battery and a second battery, comprising:
 detecting a first voltage at a negative terminal of the first battery; 
 detecting a second voltage at a negative terminal of the second battery; 
 determining which one of the first battery and the second battery has a greater voltage based on the detected first and second voltages; and 
 in response to determining which one of the first battery and the second battery has a greater voltage, supplying power from the one of the first battery and the second battery having the greater voltage to a single boost converter 
 charging a capacitor using an output voltage of the single boost converter; 
 comparing a voltage of the capacitor to a threshold voltage; and 
 when the voltage of the capacitor meets the threshold voltage, activating an output transistor connected to an output of the single boost converter; and 
 in response to activating the output transistor, outputting an output voltage. 
 
     
     
       23. The method of  claim 22 , wherein determining which one of the first battery and the second battery has a greater voltage based on the detected first and second voltages comprises comparing the detected first and second voltages. 
     
     
       24. The method of  claim 22 , further comprising:
 detecting when a voltage of the one of the first battery and the second battery falls below the other of the first and second voltages; 
 in response to detecting when a voltage of the one of the first battery and the second battery falls below the other of the first and second voltages, disabling the one of the first battery and the second battery; and 
 further in response to detecting when a voltage of the one of the first battery and the second battery falls below the other of the first and second voltages, enabling the other of the first battery and the second battery. 
 
     
     
       25. The method of  claim 22 , wherein:
 the single boost converter is electrically connected to both the first battery and second battery; and 
 the operation of supplying power from the one of the first battery and the second battery having the greater voltage comprises enabling the one of the first battery and the second battery and disabling the other of the first battery and the second battery. 
 
     
     
       26. The method of  claim 25 , wherein:
 enabling the one of the first battery and the second battery comprises enabling a first transistor to enable the one of the first battery and the second battery; and 
 disabling the other of the first battery and the second battery comprises enabling a second transistor to disable a third transistor to disable the other of the first battery and the second battery. 
 
     
     
       27. The method of  claim 25 , wherein:
 enabling the one of the first battery and the second battery comprises disabling a first transistor to enable a second transistor to enable the one of the first battery and the second battery; and 
 disabling the other of the first battery and the second battery comprises disabling a third transistor to disable the other of the first battery and the second battery. 
 
     
     
       28. The method of  claim 22 , wherein outputting an output voltage comprises:
 setting a desired output voltage; and 
 after activating the output transistor, charging an output capacitor to a voltage equal to the desired output voltage using a voltage output by the single boost converter. 
 
     
     
       29. The method of  claim 22 , wherein:
 activating the output transistor comprises providing a bias voltage to a transistor operatively connected to the output transistor, the bias voltage enabling the transistor to enable the output transistor. 
 
     
     
       30. The method of  claim 29 , wherein the bias voltage is equal to the threshold voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation patent application of U.S. patent application Ser. No. 11/286,523, filed Nov. 23, 2005 and entitled “Power Source Switchover Apparatus and Method;” the disclosure of which is hereby incorporated herein in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     I. Technical Field 
     The present invention relates generally to electrically-powered devices, and more particularly to a circuit for switching between multiple power sources. 
     II. Background Art 
     Many modern devices are electrically powered. Oftentimes, such power is supplied by one or more portable power sources, such as a battery. As used herein, the term “battery” refers generally to any cell that may store energy and furnish the stored energy as an electrical current. For example, batteries may be electrostatic or electrochemical in nature. 
     Certain devices may use multiple batteries connected in parallel. Often this is done in order to extend the operation of the device; by providing multiple batteries, the device may draw power from one battery individually or both batteries simultaneously. Presuming the device&#39;s operation requires a fixed power, the overall operating life of the device may be extended by using multiple batteries. 
     As electronic devices have become more and more popular, compact, and advanced, they have come to rely heavily on batteries for power. It is not always practicable or useful to power electronic devices from a fixed or corded power supply. For example, wireless computer peripherals such as keyboards and mice that communicate with a computer by infrared or radio frequency, such as Bluetooth, have no hardwired connection through which power may be supplied. Accordingly, these devices generally employ batteries to operate. 
     Many other electronic devices, such as remote controls, calculators, cameras, watches, toys, games, and so forth likewise employ multiple batteries for operation. 
     An ongoing trend (particularly with respect to consumer electronics) is the concept of miniaturization. Electronic devices have become smaller and smaller; many modern electronic devices may perform the same functions as a device multiple times their size could only a few years ago. However, as electronics continue to shrink in size, space for circuitry and electronic components within devices becomes an issue. A premium is thus often placed on fitting the same functionality for a given circuit or component within a small footprint. 
     Given these constraints in battery-powered devices, certain issues may emerge. For example, although many electronic devices employ some form of battery-switching device to ensure power is drawn from the one battery having the highest voltage in an array of batteries, such switching devices typically require one boost converter for each battery (or at least multiple boost converters). Where space and/or cost is at a premium, it may be undesirable to use multiple boost converters in a single switching circuit. 
     Likewise, the use of multiple boost converters in a single battery-switching circuit requires power and voltage to drive each of the boost converters. This adds to the overall power consumption of the circuit, which in turn depletes the batteries faster and shortens the operational life between battery changes of the associated electronic device. 
     Accordingly, there is a need in the art for an improved battery-switching circuit. 
     SUMMARY OF THE INVENTION 
     Generally, one embodiment of the present invention takes the form of an apparatus for switching from a first power supply to a second power supply. The embodiment may detect the charge or voltage of both the first and second power supply, and power a device from the power supply having the greatest voltage or charge. 
     The embodiment may function even where one or both power supplies have a relatively low voltage. For example, the embodiment may function even when one or both power supplies have a voltage of 0.9 volts. Further, the embodiment&#39;s performance does not require a dedicated bias supply under such circumstances. Generally speaking, the embodiment is limited in operation only by the input voltage requirements of an associated boost converter. Further, the present embodiment typically employs a single boost converter despite offering the capability of switching between multiple batteries. 
     The embodiment may, for example, be used to switch between two batteries. Each battery may be placed in an electronic device, such as a computer mouse, other computer peripheral, or any battery-powered object. The batteries may be of any size, and may be the same size or type of battery or may be different in size and/or type. For example, both batteries may be AA batteries. 
     Continuing the example, when the batteries are inserted into the computer mouse, the embodiment determines which battery has a higher initial voltage and draws power for the mouse from that battery. (Alternatively, if only a single battery is inserted, the embodiment may draw power from the single battery.) As power is drawn from this “active battery,” the active battery&#39;s voltage decreases. 
     At some point, the active battery&#39;s voltage will drop below the voltage of the passive battery (i.e., the battery not presently providing power for the computer mouse). When this occurs, the present embodiment may detect that the passive battery&#39;s voltage exceeds that of the active battery, and begin drawing power from the passive battery while ceasing to draw power from the active battery. In effect, at this time the passive battery becomes the active battery and vice versa. 
     In this manner, the present embodiment may alternate between two or more power sources to provide power for a device, drawing the power from the source having the highest charge or voltage. 
     It should be noted that embodiments of the present invention may be used with a variety of power sources and in a variety of apparatuses. The present invention may be used with practically any apparatus powered by a battery, for example. Accordingly, embodiments of the present invention may be employed in computer equipment and/or peripherals, electronics devices (including remote controls), flashlights, battery-operated handheld devices, and so on. 
     Another embodiment of the present invention takes the form of a battery-switching apparatus for switching between at least a first battery and a second battery, including a first battery compartment having a first positive terminal and a first negative terminal, a second battery compartment having a second positive terminal and a second negative terminal, and a single boost converter electrically connected to each of the first and second battery compartments, wherein the boost converter is operative to draw power from a one of the first and second battery compartments having the highest voltage. The embodiment may also include a comparator electrically connected to each of the first and second battery compartments, wherein the comparator is operative to switch a power supply for the single boost converter to a one of the first and second battery compartments having the highest voltage. 
     Still another embodiment of the present invention may take the form of a method for switching between at least a first battery and a second battery, including the operations of detecting a first voltage across the first battery, detecting a second voltage across the second battery, determining which of the first voltage and second voltage is greatest, and, in response to determining which of the first voltage and second voltage is greatest, supplying power from the greatest voltage to a single boost converter. 
     These and other advantages and features of the present invention will become apparent to those of ordinary skill in the art upon reading this disclosure in its entirety. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts an exemplary embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     I. Introduction 
     Generally, one embodiment of the present invention takes the form of an apparatus for switching from a first power supply to a second power supply. The embodiment may detect the charge or voltage of both the first and second power supply, and power a device from the power supply having the greatest voltage or charge. 
     The embodiment may function even where one or both power supplies have a relatively low voltage. For example, the embodiment may function even when one or both power supplies have a voltage of 0.9 volts. Further, the embodiment&#39;s performance does not require a dedicated bias supply under such circumstances. Generally speaking, the embodiment is limited in operation only by the input voltage requirements of an associated boost converter. Further, the present embodiment typically employs a single boost converter despite offering the capability of switching between multiple batteries. 
     The embodiment may, for example, be used to switch between two batteries. Each battery may be placed in an electronic device, such as a computer mouse, other computer peripheral, or any battery-powered object. The batteries may be of any size, and may be the same size or type of battery or may be different in size and/or type. For example, both batteries may be AA batteries. 
     Continuing the example, when the batteries are inserted into the computer mouse, the embodiment determines which battery has a higher initial voltage and draws power for the mouse from that battery. (Alternatively, if only a single battery is inserted, the embodiment may draw power from the single battery.) As power is drawn from this “active battery,” the active battery&#39;s voltage decreases. 
     At some point, the active battery&#39;s voltage will drop below the voltage of the passive battery (i.e., the battery not presently providing power for the computer mouse). When this occurs, the present embodiment may detect that the passive battery&#39;s voltage exceeds that of the active battery, and begin drawing power from the passive battery while ceasing to draw power from the active battery. In effect, at this time the passive battery becomes the active battery and vice versa. Both batteries are connected to a single boost converter, which boosts the output of the active battery to an output voltage level. As the batteries are swapped in and out of the “active battery” role, the batteries are electrically connected to, and provide power to, this single boost converter. 
     In this manner, the present embodiment may alternate between two or more power sources to provide power for a device, drawing the power from the source having the highest charge or voltage. 
     It should be noted that embodiments of the present invention may be used with a variety of power sources and in a variety of apparatuses. The present invention may be used with practically any apparatus powered by a battery, for example. Accordingly, embodiments of the present invention may be employed in computer equipment and/or peripherals, electronics devices (including remote controls), flashlights, battery-operated handheld devices, and so on. 
     II. Physical Configuration 
       FIG. 1  depicts a schematic of an exemplary embodiment  100  of the present invention. A first battery  102  and second battery  104  may be connected to the embodiment  100 . The first battery and second battery, for example, may be placed in respective first and second battery compartments. The positive terminals  106 ,  110  of each battery  102 ,  104  are connected to a first common node  118 . Further, through first common node  118 , the positive terminals  106 ,  110  are connected to a voltage input of a boost converter  116 . The configuration and operation of the boost converter  116  are well known to those of ordinary skill in the art. The boost converter  116  is also connected to a ground  120  and, through its output, to a peak detector  122  and output transistor  124 . Essentially, the boost converter  116  is a switching DC/DC converter producing an output voltage greater than the source voltage. Thus, the boost converter  116  acts to amplify the voltage of the battery  102 ,  104  from which power is presently being drawn. 
     A comparator  126  is operationally connected to the negative terminals of both batteries  102 ,  104 . The negative terminal  108  of the first battery  102  is connected to the comparator&#39;s inverting input. The negative terminal  112  of the second battery  104  is connected to the noninverting input of the comparator  126 . A resistor  128  may be placed between the second battery&#39;s negative terminal  112  and the noninverting input, and is part of a hysteresis circuit. In brief, the hysteresis circuit accounts for recovery of the batteries  102 ,  104  when a load is removed. Essentially, the hysteresis circuit reduces the likelihood that the comparator  126  oscillates between batteries  102 ,  104  as the battery voltages change due to removal of the voltage load. Such oscillation, if permitted, may reduce the efficiency of the embodiment  100 . 
     The comparator  126  is also operationally connected to a number of additional electrical elements. For example, the comparator  126  is connected to the peak detector  122 , which supplies a positive supply voltage, as well as to the ground  120 , which provides a negative supply voltage of zero volts. 
     The comparator&#39;s output is operationally connected to a second resistor  134 , which, in combination with the first resistor  128 , forms the aforementioned hysteresis circuit. 
     The output of the comparator  126  is also connected to the ground  120  and to the gate of a first field-effect transistor  136 . Likewise, the comparator output is connected to the gate of a second field-effect transistor  138 . Generally speaking, the transistors depicted in  FIG. 1  and discussed herein are n-channel metal oxide semiconductor field-effect transistors, or n-channel “MOSFETs.” It should be noted that alternative embodiments may use p-channel MOSFETs, depletion mode MOSFETs, and so on. Typically, although not necessarily, embodiments of the present invention do not employ bipolar junction transistors (“BJT”), insofar as the power required to drive a BJT is relatively high and BJTs can be inefficient with respect to power consumption. Furthermore, BJTs typically have a saturation voltage across their collector-emitter junction when turned on. This saturation voltage causes a reduction in overall efficiency. 
     The first field-effect transistor  136  has three terminals, namely a gate, a drain, and a source terminal. As previously mentioned, the gate terminal of the transistor  136  is connected to the output of the comparator  126 . The source terminal of the transistor  136  is connected to the ground  120 , and the drain terminal of the transistor  136  is connected to a second common node  130 . Through the second common node  130 , the drain terminal is also connected to the negative terminal  108  of the first battery  102  and the inverting input of the comparator  126 . 
     In addition to the first transistor  136 , a first diode  139  and first capacitor  150  are also operationally connected to the second common node  130 . The first diode  139  and first capacitor  150  are both connected between the second common node  130  and the ground  120 . Effectively, the first diode and first capacitor are likewise connected from the drain terminal to the source terminal of the first transistor  136 . 
     A second transistor  138  has its gate terminal connected to the output of the comparator  126 . The second transistor&#39;s source terminal is connected to the ground  120  and its drain terminal is connected to the gate of a third transistor  140 . 
     The source terminal of the third transistor  140  is connected to the ground  120 , while the drain terminal of the third transistor is connected to a third common node  132 . This third common node  132  is likewise connected to the negative terminal  112  of the second battery and the first resistor  128 . Thus, the source-to-drain path of the third transistor  140  stretches between the ground  120  and the third common node  132 . 
     Likewise, a second diode  142  and second capacitor  144  both are connected between the third common node  132  and ground  120 . 
     A first pullup resistor  152  may be connected between the second common node  130  and the first common node  118 . 
     A second pullup resistor  146  may be placed between the third common node  132  and first common node  118 . Accordingly, the second pullup resistor  146  is likewise electrically connected between the third common node  132  and the positive terminal  106  of the first battery  102 . 
     The first and second pullup resistors  152 ,  146  typically have relatively high resistance values, such that they may approximate an open circuit. In one exemplary embodiment, the first and second pullup resistors are one mega-ohm resistors. Generally, the pullup resistors may establish defined voltages at the second and third common nodes  130 ,  132  in case a first battery or second battery is not inserted. More specifically, the pullup resistor  146  may maintain a voltage equal or above ground at the third common node  132  when a first battery is inserted and a second battery is not inserted. Similarly, the pullup resistor  152  may maintain a voltage equal to or above ground at the second common node  130  when a first battery is not inserted and a second battery is inserted. 
     Operationally and electrically connected to the output of the peak detector  122  is a voltage detector  154 . The voltage detector  154  acts as a comparator having a fixed threshold. Once this threshold is met, the detector outputs an invariant voltage. 
     Connected between the first common node  118  and the ground  120  are a third capacitor  156  and fourth transistor  158  in series. That is, the capacitor is connected between the first common node  118  and the drain terminal of the fourth transistor  158 . The source terminal of the transistor, in turn, is connected to the ground  120 . The gate terminal of the fourth transistor is connected to the output of the voltage detector  154 . 
     A diode  178  may serve as a switching element and be wired across the boost converter, between a switch input and the voltage output of the converter. The diode  178  may transfer energy stored in an inductor  180  to one or more output capacitors  162 . Typically, the inductor  180  is electrically connected to the first node and the switch input of the boost converter  116 . 
     Generally, a boost converter  116  includes either an internal switching element (such as a p-channel field effect transistor) or an external pass element (such as a Shottkey diode). Either such converter may be used in the present embodiment  100 , although the embodiment is shown with a boost converter  116  having an external pass element. In an embodiment employing a boost converter with an internal switch element, the diode  178  may not be present. 
     As previously mentioned, the output of the boost converter  116  is electrically connected to an output transistor  124 . Specifically the boost converter&#39;s output is connected to the source terminal of the output transistor. It should be noted that the output transistor is typically a p-channel transistor in the present embodiment, rather than an n-channel transistor. Alternative embodiments may use an n-channel transistor for the output transistor. 
     The gate terminal of the output transistor  124  is electrically connected to the drain terminal of a fifth transistor  160 . This fifth transistor&#39;s source terminal is connected to the ground  120 . The operation of the fifth transistor  124 , including its interaction with the output transistor  124 , is discussed in more detail below. 
     The output capacitor  162  is electrically connected between the output of the output transistor  124  and the ground  120  The output capacitor  162  is disconnected from the output of the boost converter  116  until the output voltage equals Vbias. 
     Additionally, a voltage divider  166  may be used to set the output voltage level of the boost converter  116 . The voltage divider  166  is generally connected between the ground  120  and the output of the boost converter  116 , as shown in  FIG. 1 , with a center tap  182  connected to the boost converter&#39;s feedback pin. It should be noted that the feedback voltage divider  166  is optional. Boost converters having a fixed output voltage may be used in embodiments of the present invention. Such boost converters generally do not require an external feedback divider network  166 . The voltage divider  166  shown is exemplary; alternative voltage dividers as known to those of ordinary skill in the art (for example, incorporating one or more capacitors and/or additional resistive elements) may be used. 
     Having described the general configuration of an exemplary embodiment  100  of the present invention, the operation of the embodiment will now be disclosed. The embodiment  100  may operate in a number of modes, namely an initial mode, a comparator mode, and a switching mode. Further, the switching mode may vary depending on which battery  102 ,  104  is inserted into the embodiment  100 , or if both batteries are present. Each of the operational modes will be discussed in turn. 
     III. Initial Operation 
     When one or both batteries  102 ,  104  are inserted into the embodiment  100 , the embodiment begins operation in an “initial operation mode.” In this mode, the embodiment  100  establishes an initial bias voltage for the switchover transistors (i.e., the first and third transistors  136 ,  140 ). 
     Initially, one battery may be inserted, or both batteries may be inserted. As a first example, presume only the first battery  102  is inserted. 
     In such a case, the voltage across the first capacitor  150  is initially zero. Because the second battery  104  is not present, the second capacitor  144  may be charged through the second pullup resistor  146 . (This occurs because the voltage at the common node  118  equals the voltage of the first battery  102 , while the end of the first capacitor  150  opposite the second pullup resistor  146  is zero, insofar as it is connected to the ground  120 .) 
     When the battery  102  is initially inserted, the voltage at the second common node  130  is zero. This occurs because the first capacitor  150  initially has zero charge. Similarly, the voltage at the third common node  132  is zero, because the second capacitor  144  initially has zero charge. Because the current flows from the ground  120  into the negative battery terminal  108  of the first battery  102  through the second common node  130 , the first capacitor  150  is slowly charged. This, in turn, causes the voltage across the first capacitor  150  to build up in direction of the current flow. Accordingly, the voltage at the second common node  130  drops below the ground  120 . The diode  139  may function as a safety mechanism to prevent the voltage across the first capacitor  150  from dropping below a certain level. When the voltage at the second common node  130  drops below this certain level, the first diode  139  starts conducting and clamps the voltage across the first capacitor  150  to the characteristic forward voltage of diode  139 . During initial operation, this first diode will ideally never conduct. 
     Furthermore, the initial output of the voltage detector  154  is zero volts. Since this output is attached to the gates of the fourth and fifth transistors  158 ,  160 , these transistors remain open and no current may flow from drain to source across these transistors. Accordingly, the gate to source voltage of the output transistor  124  is also zero and no current may flow to the output capacitor  162  or the voltage divider network  166 . Thus, the output capacitor  162  is initially disconnected from the output of the output transistor  124  to prevent the output capacitor  162  from absorbing charge. Similarly, input capacitor  156  is initially disconnected from the input of the boost converter  116  to prevent input capacitor  156  from absorbing charge. 
     In the present embodiment  100 , the peak detector  122  includes a peak capacitor  170  and a peak diode  172  and generally provides a temporary bias voltage (Vbias) for the switchover transistors  136 ,  140  and comparator  126  during initial startup of the boost converter  116 . The peak detector diode  172  may isolate the peak capacitor  170  from the output of the boost converter. In this manner, the peak detector diode prevents charge from being depleted from the peak capacitor  170  when the output transistor  124  is turned on and the embodiment  100  outputs a voltage at the output node  174 . 
     Specifically, the charge of the storage capacitor  168  is initially zero. Once the first battery  102  is inserted, the voltage at the anode of the peak detector diode  172  equals the input voltage. For purposes of this discussion, presume the input voltage is 0.9 volts. 
     When the first battery  102  is initially inserted, the charge across the first capacitor  150  is initially zero. Because current flows from the ground  120  into the negative terminal  108  of the first battery  102 , the voltage across the first capacitor  150  builds up in the same direction. Thus, the voltage at the second common node  130  drops below ground until it reaches its final voltage V c1f , which is established by the time the voltage across the peak detector capacitor  170  reaches the threshold voltage of the voltage detector  154 . For example the threshold voltage may be 1.8 volts. This final voltage is typically relatively low, so that the voltage at the second common node  130  is likewise relatively low. 
     As the boost converter  116  switches on, a storage capacitor  168  and peak capacitor  170  charge to an aggregate voltage V pd , representing the average voltage across the peak detector capacitor and storage capacitor  168  The voltage V pd  may be expressed as the charge of the capacitors  168 ,  170  divided by the capacitance C pd . Expressed mathematically, this is: V pd =Q pd /C pd . The charge stored in the storage capacitor  168  and peak capacitor  170  (Q pd ) thus may be expressed as:
 
 Q   pd   =V   pd   ×C   pd  
 
     During initial startup of the embodiment  100 , the increase in aggregate voltage across the peak capacitor  170  and the storage capacitor  168  is a function of the voltage across the first capacitor  150  and the power consumed by the boost converter  116 . In order to calculate the voltage V CIN  across the first capacitor  150  when the first battery  102  is inserted (or second capacitor  144 , when the second battery  110  is inserted) at the end of the initial operation, i.e. when the aggregate voltage across the storage capacitor  168  and peak capacitor  170  has reached the threshold of voltage comparator  154 , one may relate input power and output power of the boost converter  116 . 
     The efficiency of the boost converter  116  may be stated as: 
     
       
         
           
             
               
                 
                   
                     η 
                     BOOST 
                   
                   = 
                   
                     
                       
                         
                           P 
                           OUT 
                         
                         
                           P 
                           IN 
                         
                       
                       → 
                       
                         P 
                         OUT 
                       
                     
                     = 
                     
                       
                         η 
                         BOOST 
                       
                       · 
                       
                         P 
                         IN 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
     Here, P IN  is the input power into the boost converter  116  and P OUT  is the output power from the boost converter  116 . The efficiency n BOOST  generally takes into account the static power consumed by the internal circuitry of the boost converter necessary to boost the input voltage to the desired output voltage level. 
     The input power P IN  may be defined as follows:
 
 P   IN   =V   IN   ·I   IN   (Equation 2)
 
     In Equation 2, V IN  is the input voltage to the boost converter  116  and I IN  is the boost converter&#39;s input current. 
     The output power from the boost converter  116  (P OUT ) may be defined as:
 
 P   OUT   =V   OUT   ·I   OUT   (Equation 3)
 
     Here, V OUT  is the output voltage of the boost converter  116  and I OUT  is the output current. 
     The boost converter  116  receives its power from the series combination of the first or second battery  102 ,  104  and corresponding first or second capacitor  150 ,  144 , with respect to the ground  120 . Since the current into the first or second capacitor  150 ,  144  flows from the ground  120  into the negative terminals  108 ,  112  of the first or second batteries  102 ,  104 , the voltage V CIN  across the first or second capacitor builds up oppositely to the voltage across the first or second battery. Accordingly, the input voltage of the boost converter  116  may be expressed as:
 
 V   IN   =V   BAT   ·V   CIN   (Equation 4)
 
     Here, V BAT  is the battery voltage of the first or second battery  102 ,  104  (whichever is providing power to the boost converter  116  as the active battery), and V CIN  is the voltage across the corresponding first or second capacitor  150 ,  144  (i.e., the capacitor corresponding to the active battery). 
     The input current I IN  to the boost converter  116  may be expressed as: 
     
       
         
           
             
               
                 
                   
                     I 
                     IN 
                   
                   = 
                   
                     
                       C 
                       IN 
                     
                     · 
                     
                       
                         ⅆ 
                         
                           V 
                           CIN 
                         
                       
                       
                         ⅆ 
                         t 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     5 
                   
                   ) 
                 
               
             
           
         
       
     
     The charge C IN  represents the charge of either the first or second capacitor  144 ,  150  (whichever capacitor corresponds to the active battery). Similarly, dV CIN  is the differential voltage change across C IN  in time interval dt. 
     Further, I OUT  can be expressed as: 
     
       
         
           
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     
                       C 
                       OUT 
                     
                     · 
                     
                       
                         ⅆ 
                         
                           V 
                           COUT 
                         
                       
                       
                         ⅆ 
                         t 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     6 
                   
                   ) 
                 
               
             
           
         
       
     
     Here, C OUT  is the combined capacitance of the storage capacitor  168  and peak capacitor  170 . 
     By substituting equations 4, 5, 6 in equations 1, 2 and 3 and rearranging the resulting equation, the following may be obtained: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         
                           V 
                           BAT 
                         
                         - 
                         
                           V 
                           CIN 
                         
                       
                       ) 
                     
                     · 
                     
                       η 
                       BOOST 
                     
                     · 
                     
                       C 
                       IN 
                     
                     · 
                     
                       
                         ⅆ 
                         
                           V 
                           CIN 
                         
                       
                       
                         ⅆ 
                         t 
                       
                     
                   
                   = 
                   
                     
                       V 
                       COUT 
                     
                     · 
                     
                       C 
                       OUT 
                     
                     · 
                     
                       
                         ⅆ 
                         
                           V 
                           COUT 
                         
                       
                       
                         ⅆ 
                         t 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     7 
                   
                   ) 
                 
               
             
           
         
       
     
     This is a differential equation. By eliminating the dt term and integrating the solution is: 
     
       
         
           
             
               
                 
                   
                     
                       
                         C 
                         IN 
                       
                       · 
                       
                         η 
                         BOOST 
                       
                       · 
                       
                         
                           ∫ 
                           0 
                           VCIN 
                         
                         ⁢ 
                         
                           
                             ( 
                             
                               
                                 V 
                                 BAT 
                               
                               - 
                               
                                 V 
                                 CIN 
                               
                             
                             ) 
                           
                           · 
                           
                               
                           
                           ⁢ 
                           
                             ⅆ 
                             
                               V 
                               CIN 
                             
                           
                         
                       
                     
                     = 
                     
                       
                         C 
                         OUT 
                       
                       · 
                       
                         
                           ∫ 
                           0 
                           VBIAS 
                         
                         ⁢ 
                         
                           
                             V 
                             COUT 
                           
                           · 
                           
                               
                           
                           ⁢ 
                           
                             ⅆ 
                             
                               V 
                               COUT 
                             
                           
                         
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       
                         
                           C 
                           IN 
                         
                         · 
                         
                           V 
                           BAT 
                         
                         · 
                         
                           V 
                           CIN 
                         
                       
                       - 
                       
                         
                           
                             C 
                             IN 
                           
                           · 
                           
                             V 
                             CIN 
                             2 
                           
                         
                         2 
                       
                     
                     = 
                     
                       
                         
                           
                             C 
                             OUT 
                           
                           · 
                           
                             V 
                             BIAS 
                             2 
                           
                         
                         
                           2 
                           · 
                           
                             η 
                             BOOST 
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     8 
                   
                   ) 
                 
               
             
           
         
       
     
     Note that by multiplying both sides of equation 8 by dt, and considering that E=P×dt, the terms in Equation 8 are energies and not powers. 
     From Equation 8, it may be seen that the energy conservation law is satisfied. The right side of the equation is the energy stored in C OUT , which is the sum of the storage capacitor  168  and peak capacitor  170 . V BIAS  is the average voltage across these capacitors (not taking into account the effects of the peak diode  172 ). V BAT  is the battery voltage (from either the first or second battery  102 ,  104 , depending on which is presently supplying power to the boost converter  116 ). C IN  is the charge of either the capacitor  150  or second capacitor  144  and V CIN  is the voltage C IN  charges to when C OUT  has reached V BIAS . The right term of Equation 1 is the energy stored in capacitor C OUT  when charged to the bias voltage. The second term on the left side of Equation 1 is the energy stored in C IN  after C OUT  is charged to the bias voltage. 
     The first term on the left side of Equation 1 is the energy drawn from the active battery after C OUT  is charged to V BIAS . The combined energies stored in charges C IN  and C OUT  are typically supplied by the battery. Realistically, the active battery should provide a higher energy to overcome any inefficiencies of the boost converter  116 . 
     Equation 8 can be rewritten as follows: 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       CIN 
                       2 
                     
                     - 
                     
                       2 
                       · 
                       
                         V 
                         BAT 
                       
                       · 
                       
                         V 
                         CIN 
                       
                     
                     + 
                     
                       V 
                       BAT 
                       2 
                     
                   
                   = 
                   
                     
                       - 
                       
                         
                           
                             C 
                             OUT 
                           
                           · 
                           
                             V 
                             BIAS 
                             2 
                           
                         
                         
                           
                             C 
                             IN 
                           
                           · 
                           
                             η 
                             BOOST 
                           
                         
                       
                     
                     + 
                     
                       V 
                       BAT 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     9 
                   
                   ) 
                 
               
             
           
         
       
     
     This equation has two solutions, as follows: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         
                           V 
                           CIN 
                         
                         - 
                         
                           V 
                           BAT 
                         
                       
                       ) 
                     
                     2 
                   
                   = 
                   
                     
                       
                         
                           V 
                           BAT 
                           2 
                         
                         - 
                         
                           
                             
                               C 
                               OUT 
                             
                             · 
                             
                               V 
                               BIAS 
                               2 
                             
                           
                           
                             
                               C 
                               IN 
                             
                             · 
                             
                               η 
                               BOOST 
                             
                           
                         
                       
                       → 
                       
                         
 
                       
                       ⁢ 
                       
                         V 
                         CIN 
                       
                     
                     = 
                     
                       
                         V 
                         BAT 
                       
                       ± 
                       
                         
                           
                             V 
                             BAT 
                             2 
                           
                           - 
                           
                             
                               
                                 C 
                                 OUT 
                               
                               · 
                               
                                 V 
                                 BIAS 
                                 2 
                               
                             
                             
                               
                                 C 
                                 IN 
                               
                               · 
                               
                                 η 
                                 BOOST 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     10 
                   
                   ) 
                 
               
             
           
         
       
     
     Since V CIN  cannot exceed V BAT , the solution to Equation 10 is: 
     
       
         
           
             
               
                 
                   
                     V 
                     CIN 
                   
                   = 
                   
                     
                       V 
                       BAT 
                     
                     - 
                     
                       
                         
                           V 
                           BAT 
                           2 
                         
                         - 
                         
                           
                             
                               C 
                               OUT 
                             
                             · 
                             
                               V 
                               BIAS 
                               2 
                             
                           
                           
                             
                               C 
                               IN 
                             
                             · 
                             
                               η 
                               BOOST 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     11 
                   
                   ) 
                 
               
             
           
         
       
     
     Given C IN =10 uF, V BAT =0.9V, n BOOST =0.8, C OUT =0.02 uF and V OUT =1.8V, V CIN  would be 4.5 mV. It should be noted other values for any or all of these variables may be used. Additionally, it should be noted that it is possible to reduce V CIN  further by increasing the ratio of C OUT  and C IN  according to Equation 11. 
     The voltage at the first common node  118  should reach (or maintain) a certain value for the boost converter  116  to be active, and thus for the embodiment  100  to produce a output voltage at the output node  174 . That is, the lower the voltage V c1f , the lower the minimum voltage of the battery  102  may be to operate the boost converter  116 . The boost converter  116  may have a minimum voltage threshold, below which it will not operate. Thus, the voltage of the first common node  118  (i.e., the voltage “seen” by the boost converter at the positive terminal  106  of the first battery  102 ) must equal or exceed the boost converter&#39;s minimum voltage threshold for the embodiment  100  to produce an output voltage at the output node  174 . 
     One way to ensure this occurs is to minimize the voltage across the first capacitor  150 , namely V c1f . The capacitances of the first capacitor  150  and the two peak capacitors  168 ,  170  may be selected to minimize the voltage V c1f  according to the equations above. In effect, the voltage of the active battery must exceed the minimum startup voltage threshold of the boost converter by at least at least V c1f , or the final voltage of the first capacitor  150  so the boost converter  116  is able to start up. 
     IV. Comparator Operation 
     The minimum startup voltage of the boost converter  116  in the present embodiment  100  may be expressed as the minimum voltage required to power the regulator (i.e., the minimum voltage requirement for operation of a boost converter of this type and model), plus the voltage V c1f . Accordingly, minimizing V c1f  also decreases the minimum voltage of the first battery  102  necessary to operate the boost converter. 
     A. First Battery Operation 
     Returning to the initial state when the first battery  102  is inserted into the embodiment  100 , it has been noted that the voltage at the second common node  130  is zero since the first capacitor  150  has zero charge and thus shorts the first transistor  136  and first diode  139 . 
     After the first battery  102  is inserted, the first capacitor  150  charges from the current flowing from the ground  120  into the negative battery terminal  108 . This, in turn, causes the voltage at the second common node  130  to drop below ground. By contrast, the second capacitor  144 , which initially holds third common node  132  at the potential of the ground  120  (i.e., zero voltage), charges through the second pullup resistor  146 . Accordingly, the voltage of the third common node  132  rises above ground with time. 
     Thus, because the absolute value of the voltage (i.e., the voltage irrespective of whether it is a positive or negative voltage) at the inverting input, i.e. the voltage at second common node  130 , is below the absolute value of the voltage at the noninverting input, i.e. the voltage at third common node  132 , the comparator  126  outputs a positive voltage, enabling the first transistor  136  and the second transistor  138 . Generally, the first and second transistors turn on when the voltages at their respective gates rise above a certain threshold value. Thus, the output of the comparator  126  should be sufficient to activate the first and second transistors. The second transistor  138 , in turn, disables the third transistor  140 . Thus, the negative terminal  108  of the first battery  102  is connected to the ground  120  by the first transistor  136 , and a current loop through the first battery may be established. In this state, the voltage at the third common node  132  continues to rise as the voltage across the first capacitor  150  is clamped to ground by transistor  136 , thus maintaining the comparator&#39;s  116  output state. In this manner, the boost converter  116  may draw on the voltage of the first battery  102 . This permits the capacitor  168  and the peak detector capacitor  170  to charge. 
     Eventually, the storage capacitor  168  and the peak detector capacitor  170  will charge until their aggregate output voltage V PD  reaches the threshold of the voltage detector  154 . This threshold is called “V bias .” Once this occurs, the voltage detector  154  outputs a voltage (also equal to V bias ). The voltage detector&#39;s output is connected to the gates of the fourth and fifth transistors  158 ,  160 . 
     When the voltage V bias  is applied to the gates of the fourth and fifth transistors  158 ,  160 , current may flow through these transistors. This permits the boost converter  116  to operate in a so-called “normal mode.” In the normal mode, the output transistor  124  is switched on by current flowing from the source terminal to the drain terminal of the fifth transistor  160 , and to the gate of the output transistor  124 . Thus, the output transistor closes and current may flow from the boost converter  116  to the output node  174 . The final voltage V out  (established at the output node  174 ) and the voltage across the output capacitor  162  will rise to the voltage set by the voltage divider  166 . Since the output node  174  is connected to the peak detector, the voltage V bias  may drop by one forward voltage drop (V fw ) below V out . The forward voltage V fw  is the characteristic voltage drop of diode  172 . 
     B. Second Battery Operation 
     Just as the embodiment  100  and, in particular, the comparator  126  may operate when only the first battery  102  is installed, so may the embodiment operate when only the second battery  104  is installed. The general operation is similar to that described above with respect to the operation when only the first battery  102  is present. For example, the operation of the peak detector  122 , voltage detector  154 , and boost converter  116  is generally the same as previously described. 
     However, certain differences are present in the embodiment  100  when the second battery  104  is installed alone, as opposed to when only the first battery  102  is present. When the second battery  104  is inserted into the embodiment  100 , the voltage at the third common node  132  is zero since the second capacitor  144  has zero charge and thus shorts the third transistor  140  and second diode  142 . After the second battery  104  is inserted, the second capacitor  144  charges from current flowing from the ground  120  into the second battery&#39;s negative terminal  112 . Charging the second capacitor  144  generally causes the voltage at the third common node  132  to drop below the voltage at the ground. By contrast, the first capacitor  150 , which initially holds the second common node  130  at zero volts (i.e., ground voltage), charges via the first pullup resistor  152 . As the first capacitor charges, the voltage of the second common node  130  slowly rises above ground. Thus, because the absolute value of the voltage (i.e., the voltage irrespective of whether it is a positive or negative voltage) at the inverting input, i.e. the voltage at node  132 , is below the absolute value of the voltage at the noninverting input, i.e. the voltage at node  130 , the comparator  126  outputs a negative voltage with respect to the ground voltage. 
     Because the comparator  126  has a negative voltage output, neither the first transistor  136  nor the second transistor  138  are active. However, because the second transistor is not active, the third transistor  140  is active. In this manner, the comparator shorts capacitor  144  and enables charging of the second capacitor  150  through pullup resistor  152 . The second capacitor  144  may thus charge from the second battery  104  via pullup resistor  146 . This is exactly the opposite scenario as that described above in Section II.A. (“First Battery Operation”). 
     Essentially, when the second battery  104  is placed in the embodiment  100  and the first battery  102  is not, the comparator  126  reverses the status of the first, second and third transistors  136 ,  138 ,  140  from what was previously described. 
     Although certain voltages are reversed, the operation of the boost converter  116  is not affected, nor are the operations of the peak detector  122 , voltage detector  154 , output transistor  124 , output capacitor  162  or voltage divider  166 . The only difference is that the boost converter may draw charge from the second battery  104  because the comparator  126  acts to complete a current loop with the second battery (and disable any current loop through the first battery  102  terminals) by switching the transistors  136 ,  138 ,  140  to account for the presence of the second battery. 
     C. Operation with Both Batteries 
     If both batteries  102 ,  104  are inserted, the embodiment  100  (by means of the comparator  126 ) will activate the battery having the highest cell voltage. Typically, only one battery  102 ,  104  is activated at any given time. That is, the boost converter  116  generally draws power from one battery or the other, but not both. Once the battery having the highest cell voltage is determined, the embodiment operates as described above. 
     More particularly, after initial startup of the boost converter  116  (i.e. after the boost converter is operating in its active mode), the battery  102 ,  104  that will power the embodiment  100  is the battery with the higher cell voltage. 
     For example, presume the comparator&#39;s output voltage is either high or low (due to the hysteresis circuit associated with the comparator  126 , either the third transistor  140  is on and the first transistor  136  is off or vice versa. Effectively, four different scenarios exist for operation of the embodiment  100  when both batteries  102 ,  104  are inserted. Each is discussed in turn. 
     The first scenario is when the third transistor  140  is active, the first transistor  136  is off and the voltage of the first battery  102  exceeds the voltage of the second battery  104 . In this case, the non-inverting node of the comparator  126  is at ground. Because the batteries  102 ,  104  are connected at their positive terminals (through the first common node  118 ) the voltage at the second common node  130 , and thus at the inverting node of the comparator, equals the voltage of the second battery  104  less the voltage of the first battery  102  (Vbat 2 −Vbat 1 ). Since Vbat  1  exceeds Vbat  2 , the resulting voltage at the second common node  130  is below ground (i.e., negative). Therefore, since the voltage at the inverting node of the comparator  126  is lower than the voltage at the non-inverting, node the output of the comparator is high and a positive voltage is outputted. This positive output voltage turns on the first transistor  136  and second transistor  138 , while turning off the third transistor  140 . Therefore, the embodiment  100  (and particularly the boost converter  116 ) draws power from the first battery  102  and deactivates the second battery  104 , since the first battery has the higher cell voltage. 
     A second scenario is when the third transistor  140  is on, the first transistor  136  is off, and Vbat 1 &lt;Vbat 2 . In this second scenario, the non-inverting input of the comparator  126  is at ground. Because the batteries  102 ,  104  are connected at their positive terminals  106 ,  110  (through the first common node  118 ), the voltage at the second common node  130 , and thus at the inverting input of the comparator  126 , is Vbat 2 −Vbat 1 . Because Vbat  1  is less than Vbat  2 , the resulting voltage at the second common node  130  is positive. Therefore, since the voltage at the inverting input of the comparator  126  is higher than the voltage at the comparator&#39;s non-inverting input, the comparator&#39;s output voltage goes to low (typically, is a negative voltage) and keeps the third transistor  140  on and the first transistor  136  off. Accordingly, the embodiment  100  maintains the same operating state as present at the beginning of this scenario. 
     In a third scenario, the third transistor  140  may be off, the first transistor  136  on, and the voltage of the first battery  102  (Vbat 1 ) may exceed the voltage of the second battery  104  (Vbat 2 ). Accordingly, the inverting input of the comparator  126  (and the second common node  130 ) is at a ground voltage. Since the first and second batteries&#39; positive terminals  106 ,  110  are connected through the first common node  118 , the voltage of the third common node  132  and the non-inverting input of the comparator  126  is (Vbat 1 −Vbat 2 ). Because Vbat  1  is greater than Vbat  2 , the voltage of the third common node  132  is be above ground (i.e., positive). Therefore, since the voltage at the non-inverting input of the comparator  126  is higher than the voltage at the comparator&#39;s inverting input the output of the comparator goes to a high state (i.e., a positive voltage) and enables the second transistor  138  and first transistor  136 , as well as disabling the third transistor  140 . In this manner, the embodiment  100  maintains the state of the transistors  136 ,  138 ,  140  described at the beginning of this third scenario, and draws power from the first battery  102 . 
     The fourth scenario occurs when the third transistor  140  is off, the first transistor  136  is on, and the voltage of the first battery  102  is less than the voltage of the second battery  104 . In this fourth scenario, the voltage at the second common node  130  and inverting input of the comparator  126  are at ground. Because the batteries  102 ,  104  are connected at their positive terminals  106 ,  110  through the first common node  118 , the voltage at the third common node  132  equals Vbat 1 −Vbat 2 . Thus, the voltage of the non-inverting input of the comparator  126  is likewise Vbat 1 −Vbat 2 . Since Vbat  1  is less than Vbat  2 , the voltage of the third node  132  is negative. Therefore, since the voltage of the inverting input exceeds the voltage of the non-inverting input, the output of the comparator  126  goes low. This, in turn, effectively turns off the first and second transistors  136 ,  138  and turns on the third transistor  140 . Accordingly, the embodiment  100  switches to the second battery  104  by enabling the third transistor  140 . This occurs because the second battery&#39;s cell voltage exceeds the first battery&#39;s cell voltage. 
     A specific example may aid in understanding the operation of the embodiment  100  when both batteries  102 ,  104  are inserted. For example, presume the first transistor  136  is active and the third transistor  140  is off. Further presume Vbat 1 =1 volt and Vbat 2 =1.2 volts. In this example, the resulting voltage at the third common node  132  (and thus at the non-inverting input of the comparator  126 ) would be 1V−1.2V, or −0.2V. However, because the voltage at the second common node  130  (and thus at the inverting input of the comparator) would be at ground, the comparator&#39;s output voltage would transition from high to low, effectively enabling the third transistor  140  and disabling the first transistor  136  because the second battery  104  has a cell voltage greater than that of the first battery. Thus, the first battery is switched out of the embodiment  100  and the boost converter  116  may draw power from the second battery. 
     It may be noted from the foregoing that, as the voltages of the first battery  102  and second battery  104  are very close, small changes in their respective voltages may cause the comparator  126  to switch rapidly between the batteries. If, for example, the first battery&#39;s voltage drops just below that of the second battery, the comparator will switch the transistors to bring the second battery into the circuit and drop the first battery out. However, this may only last for a few seconds or even fractions of seconds before the boost converter  116  pulls sufficient charge from the second battery to drop its voltage below that of the first battery. Thus, the embodiment  100  may oscillate rapidly between batteries. 
     To prevent such oscillations, two resistors  128 ,  134  form a hysteresis network. The hysteresis network maintains the operation of the comparator  126  for a time even when the currently active battery&#39;s voltage drops below the voltage of the inactive battery. The hysteresis network smoothes out battery transitions and ensures the voltage difference between batteries is sufficiently significant to prevent constant swapping. In one embodiment, the hysteresis network only permits swapping between batteries when the active battery&#39;s voltage is at least 100 millivolts below the voltage of the inactive battery. Alternative embodiments may vary this value. 
     D. Operational Summary 
     The following table summarizes the states of the comparator inputs and certain transistors, depending on which batteries are present. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 First 
                 Second 
                 Third 
                   
                   
                   
               
               
                   
                 Transistor 
                 Transistor 
                 Transistor 
                 Inverting 
                 Noninverting 
                 Comparator 
               
               
                   
                 136 
                 138 
                 140 
                 Input 
                 Input 
                 126 Output 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 First 
                 Active 
                 Active 
                 Inactive 
                 Zero 
                 Positive 
                 Negative 
               
               
                 Battery 
                 (closed) 
                 (closed) 
                 (open) 
                 Voltage 
                 Voltage 
                 voltage 
               
               
                 102 only 
               
               
                 Second 
                 Inactive 
                 Inactive 
                 Active 
                 Positive 
                 Zero Voltage 
                 Positive 
               
               
                 Battery 
                 (open) 
                 (open) 
                 (closed) 
                 voltage 
                   
                 voltage 
               
               
                 104 only 
               
               
                   
               
            
           
         
       
     
     It should also be noted that the voltage at the third common node  132  always goes above zero when the first battery  102  is inserted, due to the second capacitor  144  charging. Likewise, when the second battery  104  is inserted, the second common node will always become positive, since the first capacitor  150  may charge. 
     If both batteries  102 ,  104  are installed, the embodiment  100  detects the battery having the highest voltage and acts as if that battery were the only one installed, as described above. 
     V. Circuit Elements 
     Generally, the present embodiment  100  has been described with respect to generic circuit elements, such as “transistors” and “diodes.” Certain embodiments may employ certain types of transistors and/or diodes for a variety of reasons. For example, field-effect transistors and particularly MOSFETs may be used for any or all of the transistors discussed herein. Further, it should be understood that the first, second, third, fourth and fifth transistors  136 ,  138 ,  140 ,  158 ,  160  disclosed herein are n-channel devices, while the output transistor  124  is a p-channel device. However, it will be apparent to those of ordinary skill in the art that a p-channel device may be used in place of an n-channel device, and vice versa, by appropriately modifying the embodiment  100 . 
     In one embodiment, n-channel field-effect transistors (FETs) are employed in order to take advantage of the relatively low voltage differential between source and gate required to operate the transistor. Many n-channel FETs may operate when the voltage differential between gate and source is 0.9 volts. Accordingly, because the output of the comparator  126  equals the voltage of the peak detector&#39;s output, which in turn equals the voltage of the battery providing power for the boost converter  116 , the present embodiment may operate when the voltage of such a battery is as low as 0.9 volts. 
     Additionally, although alternative transistors may be employed in alternative embodiments, certain embodiments typically use FETs in order to provide inherent polarity protection. In this manner, the embodiment  100  will not operate if the polarity of the battery  102 ,  104  is reversed (i.e., the battery is inserted upside-down). 
     Likewise, the various diodes mentioned herein are generally Shottkey diodes. However, alternative embodiments may employ a different type of diode as will be appreciated by those of ordinary skill in the art. 
     VI. Conclusion 
     Although the present invention has been described with respect to particular apparatuses, configurations, and methods of operation, it will be appreciated by those of ordinary skill in the art upon reading this disclosure that certain changes or modifications to the embodiments and/or their operations, as described herein, may be made without departing from the spirit or scope of the invention. For example, an alternative embodiment of the present invention may be configured to switch between three separate power sources. The third power source may be electrically connected to one input of a second comparator, for example. The second comparator may have as its second input the output of the comparator  126 . Accordingly, the proper scope of the invention is defined by the appended claims. The various embodiments, operations, and configurations disclosed herein are generally exemplary rather than limiting in scope.

Metadata:
Filing Date: 20090818
Publication Date: 20101214
Grant Date: 20101214
Priority Date: 20051123
Inventors: KRAH CHRISTOPH H.
PATEL RONIL
Assignee: APPLE INC
CPC Classifications: [{"code": "H02J1/10", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02J9/061", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02J9/061", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02J1/10", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 38052849