PATENT DOCUMENT

Publication Number: US-10984727-B2
Application Number: US-201816120076-A
Country: US
Kind Code: B2

Title: High frame rate display

Abstract:
A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

Claims:
What is claimed is: 
     
       1. A display, comprising:
 rows and columns of pixels; 
 gate lines that are configured to supply gate signals to the rows; 
 data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each including one of the odd data lines and an adjacent one of the even data lines, wherein each column of the pixels includes a respective one of the pairs of the data lines; 
 demultiplexer circuitry coupled to the data lines; and 
 display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide the pixels of each column with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry is configured to operate alternately in:
 a first mode in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines while the display driver circuitry asserts a given one of the gate lines; and 
 a second mode in which the demultiplexer circuitry provides data from the display driver circuitry to the even data lines while the display driver circuitry asserts the given one of the gate lines. 
 
 
     
     
       2. The display defined in  claim 1 , wherein the display driver circuitry is configured to supply the demultiplexer circuitry with first and second clock signals. 
     
     
       3. The display defined in  claim 2 , wherein the demultiplexer circuitry comprises a 1:2 demultiplexer in each column. 
     
     
       4. The display defined in  claim 3  wherein the 1:2 demultiplexer in each column has an input and first and second outputs, wherein the first output is coupled to the odd data line of that column and the second output is coupled to the even data line of that column. 
     
     
       5. The display defined in  claim 4  wherein each of the pixels includes a light-emitting diode. 
     
     
       6. The display defined in  claim 5  wherein the pixels comprise thin-film transistors having gates controlled by the gate signals. 
     
     
       7. A display, comprising:
 rows and columns of pixels; 
 gate lines that are configured to supply gate signals to the rows; 
 data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each including one of the odd data lines and an adjacent one of the even data lines, wherein each column of the pixels includes a respective one of the pairs of the data lines; 
 demultiplexer circuitry coupled to the data lines; and 
 display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide the pixels of each column with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry and display driver circuitry are configured to operate in:
 a first state in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines and then leaves the odd data lines floating; 
 a second state in which the demultiplexer circuitry provides data from the display driver circuitry to the even data lines and then leaves the even data lines floating; and 
 a third state following the first and second states in which a given one of the gate signals on a given one of the gate lines is asserted to load data from the odd data lines into a first of the rows of pixels associated with the given one of the gate lines and to simultaneously load data from the even data lines into a second of the rows of pixels associated with the given one of the gate lines. 
 
 
     
     
       8. The display defined in  claim 7  wherein each of the pixels includes a light-emitting diode. 
     
     
       9. The display defined in  claim 7 , wherein the display driver circuitry is configured to supply the demultiplexer circuitry with first and second clock signals. 
     
     
       10. The display defined in  claim 7 , wherein the demultiplexer circuitry comprises a 1:2 demultiplexer in each column. 
     
     
       11. The display defined in  claim 10  wherein the 1:2 demultiplexer in each column has an input and first and second outputs, wherein the first output is coupled to the odd data line of that column and the second output is coupled to the even data line of that column. 
     
     
       12. The display defined in  claim 11  wherein the pixels comprise thin-film transistors having gates controlled by the gate signals. 
     
     
       13. A display, comprising:
 rows and columns of pixels; 
 gate lines that are configured to supply gate signals to the rows; 
 data lines including alternating odd and even data lines, wherein the data lines include pairs of data lines each including one of the odd data lines and an adjacent one of the even data lines, wherein each column of the pixels includes a respective one of the pairs of the data lines; 
 demultiplexer circuitry coupled to the data lines; and 
 display driver circuitry coupled to the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to provide the pixels of each column with data from the display driver circuitry using the pair of data lines for that column and wherein the demultiplexer circuitry and display driver circuitry are configured to operate in:
 a first mode in which the demultiplexer circuitry provides data from the display driver circuitry to the odd data lines; and 
 a second mode in which the demultiplexer circuitry provides data from the display driver circuitry to the even data lines; and 
 a third mode in which the data on the odd data lines and even data lines is simultaneously loaded into the pixels. 
 
 
     
     
       14. The display defined in  claim 13  wherein the demultiplexer circuitry and display driver circuitry are configured to:
 during the third mode, supply a given gate signal with a given one of the gate lines to load the data on the odd data lines and the even data lines into the pixels. 
 
     
     
       15. The display defined in  claim 13  wherein a given one of the gate lines is associated with a first of the rows of pixels and a second of the rows of pixels, and wherein the demultiplexer circuitry and display driver circuitry are configured to:
 during the third mode, supply a given gate signal with the given one of the gate lines to load the data on the odd data lines into the first of the rows of pixels and to load the data on the even data lines into the second of the rows of pixels. 
 
     
     
       16. The display defined in  claim 15 , wherein the demultiplexer circuitry comprises a 1:2 demultiplexer in each column. 
     
     
       17. The display defined in  claim 16  wherein each of the pixels includes a light-emitting diode. 
     
     
       18. The display defined in  claim 17 , wherein the display driver circuitry is configured to supply the demultiplexer circuitry with first and second clock signals. 
     
     
       19. The display defined in  claim 16  wherein the 1:2 demultiplexer in each column has an input and first and second outputs, wherein the first output is coupled to the odd data line of that column and the second output is coupled to the even data line of that column and wherein the pixels comprise thin-film transistors having gates controlled by the gate signals.

Description:
This application claims the benefit of provisional patent application No. 62/561,583, filed Sep. 21, 2017, which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     This relates generally to electronic devices, and, more particularly, to electronic devices with displays. 
     Electronic devices such as cellular telephones, computers, and other electronic devices often contain displays. A display includes an array of pixels for displaying images. Display driver circuitry such as data line driver circuitry may supply data signals to the pixels. Gate line driver circuitry in the display driver circuitry can be used to provide control signals to the pixels. 
     It can be challenging to provide display driver circuitry for a display. If care is not taken, frame rates will be too low or display performance will otherwise not be satisfactory. 
     SUMMARY 
     A display may have rows and columns of pixels. Gate lines may be used to supply gate line signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Columns of pixels with mirrored layouts may flank each pair of data lines. 
     Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately, to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry. 
     Configurations in which pixels in alternating rows are coupled alternately to the odd and even data lines and configurations in which rows of pixels each include multiple gate lines may also be used. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of an illustrative electronic device having a display in accordance with an embodiment. 
         FIG. 2  is a top view of an illustrative display in an electronic device in accordance with an embodiment. 
         FIG. 3  is a circuit diagram of illustrative multiplexer and pixel circuitry in a display in accordance with an embodiment. 
         FIG. 4  is a timing diagram of illustrative control signals in a display in accordance with an embodiment. 
         FIG. 5  is an illustrative pixel circuit in a display in accordance with an embodiment. 
         FIG. 6  is a flow chart of illustrative operations associated with operating a display in accordance with an embodiment. 
         FIG. 7  is a top view of a portion of a display with power supply lines, data lines, and control lines in accordance with an embodiment. 
         FIG. 8  is a cross-sectional side view of an illustrative display in accordance with an embodiment. 
         FIG. 9  is a diagram showing how display demultiplexer circuitry may be operated during data loading in accordance with an embodiment. 
         FIG. 10  is a diagram showing how display demultiplexer circuitry may be operated during current sensing operations in accordance with an embodiment. 
         FIG. 11  is a timing diagram of illustrative data loading control signals for two successive frames in accordance with an embodiment. 
         FIG. 12  is a diagram corresponding to pixel loading patterns in successive frames using the signals of  FIG. 11  in accordance with an embodiment. 
         FIG. 13  is a timing diagram of additional illustrative data loading control signals for two successive frames in accordance with an embodiment. 
         FIG. 14  is a diagram corresponding to pixel loading patterns in successive frames using the signals of  FIG. 13  in accordance with an embodiment. 
         FIG. 15  is a timing diagram of illustrative current sensing control signals for two successive frames in accordance with an embodiment. 
         FIG. 16  is a diagram corresponding to pixels being sensed during the successive frames of  FIG. 15  in accordance with an embodiment. 
         FIG. 17  is a diagram of illustrative pixels in a display in accordance with an embodiment. 
         FIG. 18  is a timing diagram of illustrative control signals for operating the circuitry of  FIG. 17  in accordance with an embodiment. 
         FIGS. 19, 20, and 21  illustrate data loading operations in accordance with embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     An illustrative electronic device of the type that may be provided with a display is shown in  FIG. 1 . Electronic device  10  of  FIG. 1  may be a tablet computer, laptop computer, a desktop computer, a monitor that includes an embedded computer, a monitor that does not include an embedded computer, a display for use with a computer or other equipment that is external to the display, a cellular telephone, a media player, a wristwatch device or other wearable electronic equipment, or other suitable electronic device. 
     As shown in  FIG. 1 , electronic device  10  may have control circuitry  16 . Control circuitry  16  may include storage and processing circuitry for supporting the operation of device  10 . The storage and processing circuitry may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in control circuitry  16  may be used to control the operation of device  10 . The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc. 
     Input-output circuitry in device  10  such as input-output devices  12  may be used to allow data to be supplied to device  10  and to allow data to be provided from device  10  to external devices. Input-output devices  12  may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device  10  by supplying commands through input-output devices  12  and may receive status information and other output from device  10  using the output resources of input-output devices  12 . 
     Input-output devices  12  may include one or more displays such as display  14 . Display  14  may be a touch screen display that includes a touch sensor for gathering touch input from a user or display  14  may be insensitive to touch. A touch sensor for display  14  may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements. 
     Control circuitry  16  may be used to run software on device  10  such as operating system code and applications. During operation of device  10 , the software running on control circuitry  16  may display images on display  14  using an array of pixels in display  14 . 
     Display  14  may have a rectangular shape (i.e., display  14  may have a rectangular footprint and a rectangular peripheral edge that runs around the rectangular footprint) or may have other suitable shapes. Display  14  may be planar or may have a curved profile. Display  14  may be an organic light-emitting diode display or other suitable type of display. 
     A top view of a portion of display  14  is shown in  FIG. 2 . As shown in  FIG. 2 , display  14  may have an array of pixels  22  formed from substrate structures such as substrate  36 . Substrates such as substrate  36  may be formed from glass, metal, plastic, ceramic, or other substrate materials. Pixels  22  may receive data signals over signal paths such as data lines D and may receive one or more control signals over control signal paths such as gate lines G (sometimes referred to as control lines, scan lines, emission enable control lines, gate signal paths, etc.). There may be any suitable number of rows and columns of pixels  22  in display  14  (e.g., tens or more, hundreds or more, or thousands or more). Pixels  22  may have different colors (e.g., red, green, and blue) to provide display  14  with the ability to display color images. Pixels  22  may contain respective light-emitting diodes and pixel circuits that control the application of current to the light-emitting diodes. The pixel circuits in pixels  22  may contain transistors (e.g., thin-film transistors on substrate  36 ) having gates that are controlled by gate line signals on gate lines G. 
     Display driver circuitry  20  may be used to control the operation of pixels  22 . Display driver circuitry  20  may be formed from integrated circuits, thin-film transistor circuits, or other suitable circuitry. Thin-film transistor circuitry for display driver circuitry  20  and pixels  22  may be formed from polysilicon thin-film transistors, semiconducting-oxide thin-film transistors such as indium gallium zinc oxide transistors, or thin-film transistors formed from other semiconductors. 
     Display driver circuitry  20  may include display driver circuits such as display driver circuitry  20 A and gate driver circuitry  20 B. Display driver circuitry  20 A may include a display driver circuit  20 A- 1  that is formed from one or more display driver integrated circuits (e.g., timing controller integrated circuits) and/or thin-film transistor circuitry and may include demultiplexer circuitry  20 A- 2  (e.g., a demultiplexer formed from thin-film transistor circuitry or formed in an integrated circuit). Gate driver circuitry  20 B may be formed from gate driver integrated circuits or may be formed from thin-film transistor circuitry. 
     Display driver circuitry  20 A may contain communications circuitry for communicating with system control circuitry such as control circuitry  16  of  FIG. 1  over path  32 . Path  32  may be formed from traces on a flexible printed circuit or other conductive lines. During operation, the control circuitry (e.g., control circuitry  16  of  FIG. 1 ) may supply circuitry  20 A with information on images to be displayed on display  14 . 
     To display images on display pixels  22 , display driver circuitry  20 A may supply image data to data lines D while issuing control signals (e.g., clock signals, a gate start pulse, etc.) to supporting display driver circuitry such as gate driver circuitry  20 B over path  38 . Circuitry  20 A may also dynamically adjust demultiplexer circuitry  20 A- 2  by supplying clock signals (select signals) and other control signals to demultiplexer circuitry  20 A- 2 . 
     In some configurations for display  14 , each column of pixels  22  may include multiple data lines (e.g., at least two, at least three, etc.). An illustrative configuration for display  14  in which each column of pixels  22  include a pair of data lines D is shown in  FIG. 3 . A gate line may be associated with each row of pixels  22 . Nodes N show where data lines D are coupled to the pixel circuits of pixels  22 . Along each column, pixels are alternately coupled to odd and even data lines in each pair of data lines. As shown in  FIG. 3 , demultiplexer circuitry  20 A- 2  may contain switches SW that are controlled using control signals CLK 1  and CLK 2 .  FIG. 4  is a timing diagram showing signals that may be used in controlling display  14  of  FIG. 3 . 
     In high frame rate configurations for display  14 , the row time (“1H” of  FIG. 4 ) associated with controlling rows of pixels  22  tends to decrease. This can make it difficult to complete desired control operations (e.g., to load data into each row of pixels  22 ). By using multiple data lines per column of pixels  22 , the control signals (e.g., the gate signals of  FIG. 4 ) in successive rows can be staggered and can overlap in time, allowing each gate signal to be asserted for more than one row time (e.g., more than 1H). Consider, as an example, the loading of pixel  22 - 1  in row n−1 of  FIG. 3  and the loading of pixel  22 - 2  in row n of  FIG. 3 . As shown in  FIG. 4 , gate signal gate(n−1) is taken low at time t 1 . Pixel  22 - 1  can then be loaded via data line D 1 . Loading can start during time period TP 1  and can finish during time period TP 2 . At time t 2 , before the signal gate(n−1) is deasserted at time t 3 , gate signal gate(n) is asserted in row n. This allows pixel  22 - 2  to be loaded by data line D 2 . It is not necessary for gate signal gate(n−1) to complete before gate signal gate(n) is asserted, because pixel  22 - 1  is not coupled to data lines D 2  (pixel  22 - 1  is coupled to data line D 1  by a node N, but no nodes N couple pixel  22 - 1  to data line D 2 ). As shown in  FIG. 4 , each gate signal may have a pulse width that is greater than the pulse widths of clocks CLK 1  and CLK 2 . 
     Any suitable pixel circuit may be used for forming pixels  22  in display  14 . An illustrative pixel circuit is shown in  FIG. 5 . Other pixel circuitry may be used, if desired. 
     In the illustrative configuration of  FIG. 5 , pixel circuit  40  has switching transistors T 1  and T 2 , drive transistor TD, and emission enable transistor TE. Transistors T 1  and T 2  are controlled by gate signals from gate driver circuitry  20 B while data is provided via data line D. Storage capacitor Cst is used to retain data on node ND during emission operations. Reference voltage line Vref may be used in supplying a reference voltage Vref to pixel circuit  40 . During sensing operations (for threshold voltage compensation measurements), data line D may be used to sense the current associated with the pixel. Drive transistor TD and enable transistor TE are coupled in series between positive power supply terminal Vddel and negative (ground) power supply terminal Vssel. When transistor TE is on, emission is enabled and the amount of light  42  that is emitted from light-emitting diode  48  is determined by the current flowing through transistor TD. This current is determined based on the magnitude of the signal on node ND, which is coupled to the gate of transistor TD. 
     A flow chart of illustrative operations involved in displaying an image frame using pixels  22  (e.g., pixels  22  with pixel circuit  40  of  FIG. 5 ) is shown in  FIG. 6 . During the operations of block  50 , transistors T 1  and T 2  are turned on and reference data Vdata-ref is loaded onto node ND. During the operations of block  52 , sensors (e.g., current sensors) in circuitry  20 A are used to sense pixel currents via data lines D. During pixel sensing operations, transistor T 2  is turned off, transistor TE is turned on. Transistor T 1  is on and allows the pixel current to flow through transistors TE and T 1  to data line D for sensing. The sensed current is indicative of the threshold voltage of transistor TD. Following the sensing operations of block  52 , a frame of corresponding pixel compensation values (e.g., digital values) can be produced by circuitry  20 A. This frame of compensation data can be used to compensate an image frame for threshold voltage variations among pixels  22 . The image frame (e.g., an image frame of data values for each pixel that have been compensated with the compensation data in the frame of compensation data) can be loaded into pixels  22  during the operations of block  54 . During the operations of block  54 , transistors T 1  and T 2  may be turned on for data loading while transistor TE is turned off. Compensated data is loaded into each pixel using data lines D. During the operations of block  56 , transistors T 1  and T 2  are off and transistor TIE is on to enable current to flow through light-emitting diode  44 . The amount of current that flows through diode  44  and therefore the amount of light  42  that is emitted by diode  44  is determined by the current flowing through drive transistor TD, which is determined by the data on node ND. 
       FIG. 7  is a top view of a portion of display  14  showing an illustrative layout for power supply lines Vssel and Vddel and for reference line  46  and data lines DATA (sometimes referred to as data lines D). The illustrative layout of  FIG. 8  allows each reference line  46  to be shared between an adjacent even column of pixels  22  and odd column of pixels  22  and allows each power supply line Vssel and each power supply line Vddel to be shared between adjacent even and odd columns of pixels  22 . The layout of each pixel circuit  40  in each even column may have mirror symmetry with the layout of each pixel circuit  40  in an adjacent odd column. Data lines DATA may extend vertically through pixels  22  in pairs. Each pair of data lines may include a first data line for loading data into an odd column of pixels  22  and a second data line for loading data into an even column of pixels  22 . 
     A cross-sectional side view of display  14  of  FIG. 14  is shown in  FIG. 8 . As shown in  FIG. 8 , dielectric layer  62  may be formed on lower thin-film transistor circuitry layers, a substrate layer and/or other layers (see, e.g., layer  60 ). Power supply lines Vddel and reference lines  46  may be formed on layer  62 . Planarization layer  64  may cover these lines and layer  62 . Power supply lines Vssel and data lines D (e.g., data lines running parallel to each other in pairs) may be formed on layer  64 . 
     In configurations for display  14  with mirror symmetry pixel layouts and pairs of data lines of the type shown in  FIGS. 7 and 8 , the space consumed by signal lines can be reduced by consolidating signal lines such as the power supply lines and reference voltage lines. However, parasitic capacitances between adjacent data lines D in each pair of data lines may arise (see, e.g., parasitic capacitances Cp of  FIG. 9 ). If care is not taken (e.g., if odd and even columns of pixels are loaded separately), there is a potential for capacitive coupling between the even column data lines and the odd column data lines to adversely affect the accuracy of loaded data. 
     To address this concern, data can be driven onto the data lines of each pair of data lines simultaneously. Demultiplexing circuitry  20 A- 2  may be used to reduce fanout between circuit  20 A- 1  and data lines D. To accommodate the use of demultiplexing circuitry  20 A- 2  in a configuration for display  14  with pairs of simultaneously driven data lines, demultiplexing circuitry  20 A- 2  can alternate between a first state in which odd pairs of columns are loaded and a second state in which even pairs of columns are loaded. 
     This type of arrangement is shown in  FIG. 9 . As shown in  FIG. 9 , demultiplexing circuitry  20 A- 2  may be dynamically configured in accordance with control signals (sometimes referred to as clock signals CLK 1  and CLK 2 ) such as SEL_A and SEL_B. When SEL_A is taken low, data is loaded from demultiplexer circuitry  20 A- 2  into odd pairs of columns and when SEL_B is taken low data is loaded into even pairs of columns. For example, when SEL_A is taken low, data is located into pixels  22 A and  22 B of each odd column pair using data lines D(ODD PAIR) and when SEL_B is taken low, data is located into pixels  22 C and  22 D of each even column pair using data lines D(EVEN PAIR). The alternating column pair loading pattern used in  FIG. 9 , which may be used during the operations of blocks  50  and  54  of  FIG. 6 , may help enhance data loading accuracy. 
     As shown in  FIG. 10 , pixel sensing (e.g., sensing operations to measure currents for threshold voltage compensation during the operations of block  52  of  FIG. 6 ), may use a different pattern of data lines. In particular, during sensing operations, demultiplexer circuitry  20 A may be configured to alternate between a first state in which first and second odd data lines D_O from first and second adjacent column pairs (e.g., ODD PAIR and EVEN PAIR) are used to provide current measurements to circuitry  20 A- 1  and a second state in which first and second even data lines D_E from the first and second adjacent columns pairs are switched into use for current sensing. Differential current sensing may be used to mitigate the impact of potential fabrication variations (e.g., variations that might make the capacitive coupling different between a gate line G and a first data line relative to the capacitive coupling between that gate line and a second data line that is paired with the first data line). The use of differential sensing may help remove common mode noise from horizontal lines such as gate lines G that overlap the data lines. 
     The patterns used for loading and sensing may, if desired, vary between frames. As shown in the timing diagram of  FIG. 11  and the corresponding pixel loading patterns for frames m and m+1 in  FIG. 12 , for example, the column pairs that are loaded may vary between frames. In frame in, odd column pairs may be loaded. In frame m+1, even column pairs may be loaded. This alternating pattern can help reduce artifacts from capacitive coupling between adjacent pairs of columns (and associated adjacent pairs of data lines).  FIGS. 13 and 14  show an arrangement in which both column pair and row alternations are used (e.g., to form an alternating checkerboard pattern of loaded sets of pixels between respective frames). Other time varying patterns may be used, if desired. 
     An illustrative arrangement for varying the pattern of data lines used during sensing between successive frames is shown in the timing diagram of  FIG. 15  and the corresponding pixel and data line diagrams for frames m and m+1 in  FIG. 16 . As shown in  FIGS. 15 and 16 , in the mth frame, odd data lines D_O (e.g., pairs of lines for differential sensing) may be switched into use before switching even data lines D_E into use. In the m+1 st  frame, this pattern is reversed and even data lines D_E are used before odd data lines D_O. 
     An alternative configuration for loading pixels  22  is shown in the pixel diagram of  FIG. 17  and the corresponding timing diagram of  FIG. 18 . In this arrangement, each row of pixels  22  shares two gate lines (or sets of gate lines) such as odd gate lines G_O and even gate lines G_E. When CLK 1  is asserted (e.g., taken low), odd pairs of columns are selected by demultiplexer circuitry  20 A- 2 . When CLK 2  is asserted (e.g., taken low), even pairs of columns are selected. Gate signals on odd lines G_O are asserted and deasserted in accordance with the falling edges of CLK 1  and CLK 2 , respectively. Gate signals on even lines G_E are asserted and deasserted in accordance with the falling edges of CLK 2  and CLK 1 , respectively. During the period of time in which each pair of data lines is loaded with data, first the odd gate line and then the even gate line is asserted, thereby loading the left-hand pixel  22  and then the right-hand pixel associated with that pair of data lines. 
       FIGS. 19, 20, and 22  show additional illustrative arrangements for loading pixels  22  in display  14 . In the configuration of  FIG. 19 , a gate line G in a given row is asserted while (in a first demultiplexer state) odd date lines D_O are used in providing data to a first row of pixels  22 ′ that are associated with the asserted gate line G and (in a second demultiplexer state) even data lines D_E are used in providing data to a second row of pixels  22 ″ that are associated with the asserted gate line G. 
       FIG. 20  shows an illustrative configuration in which (1) odd date lines D_O are provided with data and are then left floating, (2) even data lines D_E are provided with data and are then left floating, and (3) gate control signal SC is asserted on a gate line G to load data from the odd data lines into a first row of pixels  22 ′ associated with the gate line and to load data from the even data lines into a second row of pixels  22 ″ associated with the gate line. 
       FIG. 21  shows an illustrative configuration in which demultiplexer  20 A- 2  uses 1:2 demultiplexer circuits. Demultiplexer  20 A- 2  first provides odd data lines D_O with data while both the odd and even lines are coupled to the input of each 1:2 demultiplexer. After switching the state of demultiplexer  20 A- 2 , data is provided to even data lines D_E. After loading the odd and even data lines with data in this way, the pixels are loaded (programmed). During programming, gate line G supplies signal SC (signal SC is taken low) and a first row of pixels  22 ′ associated with the gate line G is loaded with data from the odd data lines D_O while a second row of pixels  22 ″ is loaded with data from the even data lines D_E. 
     The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Metadata:
Filing Date: 20180831
Publication Date: 20210420
Grant Date: 20210420
Priority Date: 20170921
Inventors: CHANG, TING-KUO
JAMSHIDI ROUDBARI, ABBAS
TSAI, TSUNG-TING
RIEUTORT-LOUIS, WARREN S.
ONO, SHINYA
YEH, SHIN-HUNG
LEE, CHIEN-YA
YANG, SHYUAN
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G3/20", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/0205", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0297", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0252", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0252", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0205", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0218", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0219", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0209", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3266", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3275", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G3/3233", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/0218", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0209", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0213", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0297", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/08", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/20", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/021", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3275", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2310/0205", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0218", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0297", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0213", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3266", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3233", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/08", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/20", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/021", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0219", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0252", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0209", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3275", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 63678677