PATENT DOCUMENT

Publication Number: US-7834599-B2
Application Number: US-48689109-A
Country: US
Kind Code: B2

Title: Rapid supply voltage ramp using charged capacitor and switch

Abstract:
In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor, and a voltage source configured to charge the first capacitor. The switch is coupled to receive a control signal that is asserted, during use, if the supply voltage to an integrated circuit is to be increased. The switch is configured to electrically couple the first capacitor to the node in response to an assertion of the control signal. When electrically coupled to the node, the first capacitor supplies charge to the bypass capacitors. A system comprising the apparatus, the node, the integrated circuit, and the bypass capacitors is also contemplated in some embodiments.

Claims:
1. A method comprising:
 powering down a supply voltage to an integrated circuit; 
 charging a first capacitor; 
 detecting that the supply voltage is to be powered up; 
 electrically coupling the charged first capacitor to a supply voltage node of the integrated circuit responsive to the detecting, the charged first capacitor charging the supply voltage node; and 
 activating a voltage source that is coupled to the supply voltage node responsive to the detecting. 
 
     
     
       2. The method as recited in  claim 1  wherein the charging of the first capacitor is performed during a time period that the supply voltage on the supply voltage node is being provided by the voltage source. 
     
     
       3. The method as recited in  claim 1  further comprising electrically isolating the first capacitor from a voltage source that charges the first capacitor responsive to the detecting. 
     
     
       4. The method as recited in  claim 1  further comprising causing the integrated circuit to begin operation subsequent to the detecting and prior to the voltage source supplying the supply voltage on the supply voltage node, and wherein, subsequent to the detecting and prior to the supplying by the voltage source, the supply voltage on the supply voltage node is provided from the charged first capacitor and one or more bypass capacitors that are coupled to the supply voltage node in parallel with the integrated circuit. 
     
     
       5. The method as recited in  claim 4  wherein an initial supply voltage magnitude of the supply voltage provided from the charged first capacitor is greater than a minimum supply voltage magnitude at which the integrated circuit is operable. 
     
     
       6. The method as recited in  claim 5  wherein the initial supply voltage magnitude is determined based on a first capacitance of the first capacitors and a second capacitance of the bypass capacitors. 
     
     
       7. The method as recited in  claim 6  wherein a voltage magnitude on the charged first capacitor prior to the electrically coupling is greater than the initial supply voltage magnitude. 
     
     
       8. In a system including an integrated circuit coupled to a supply voltage node to receive a supply voltage, an apparatus comprising:
 a first capacitor; 
 a first switch coupled to the first capacitor and the supply voltage node, wherein the first switch is coupled to receive a first control signal, wherein the first switch is configured to electrically couple the first capacitor to the supply voltage node in response to an assertion of the first control signal; 
 a second capacitor; 
 a second switch coupled to the second capacitor and to the supply voltage node, wherein the second switch is coupled to receive a second control signal, wherein the second switch is configured to electrically couple the second capacitor to the supply voltage node in response to an assertion of the second control signal; 
 a control unit coupled to the first switch and the second switch, wherein the control unit is coupled to receive a third signal indicative, when asserted, that the supply voltage of the integrated circuit is to be powered up, and wherein the control unit is configured to assert a first one of the first control signal and the second control signal and to deassert a second one of the first control signal and the second control signal in response to a first assertion of the third signal, and wherein the control unit is configured to assert the second one and to deassert the first one responsive to a successive assertion of the third signal. 
 
     
     
       9. The apparatus as recited in  claim 8  further comprising a voltage source coupled to the first switch, wherein the first switch is configured to electrically couple the voltage source to the first capacitor responsive to a deassertion of the first control signal. 
     
     
       10. The apparatus as recited in  claim 9  wherein the voltage source is coupled to the second switch, wherein the second switch is configured to electrically couple the voltage source to the second capacitor responsive to a deassertion of the second control signal. 
     
     
       11. The apparatus as recited in  claim 8  wherein the first switch comprises a first transistor coupled between the first capacitor and the supply voltage node, the first transistor having a gate coupled to receive the first control signal. 
     
     
       12. The apparatus as recited in  claim 11  wherein the first switch further comprises a second transistor coupled between the voltage source and the first capacitor, the second transistor having a gate coupled to receive an inversion of the first control signal. 
     
     
       13. The apparatus as recited in  claim 12  wherein the second switch comprises a third transistor coupled between the second capacitor and the supply voltage node, the second transistor having a gate coupled to receive the second control signal. 
     
     
       14. The apparatus as recited in  claim 13  wherein the second switch further comprises a fourth transistor coupled between the voltage source and the second capacitor, the fourth transistor having a gate coupled to receive an inversion of the second control signal. 
     
     
       15. The apparatus as recited in  claim 8  further comprising a voltage regulator configured to generate the supply voltage. 
     
     
       16. A system comprising:
 an integrated circuit having one or more supply voltage inputs; 
 one or more bypass capacitors coupled to the one or more supply voltage inputs; 
 a plurality of capacitors; 
 a plurality of switches, each switch coupled between a respective capacitor of the plurality of capacitors and the one or more supply voltage inputs, wherein each switch is coupled to receive a respective control signal of a plurality of control signals; and 
 a control unit coupled to the plurality of switches, wherein the control unit is configured to assert different ones of the plurality of control signals in response to successive power-up events for the integrated circuit, wherein different ones of the plurality of switches are configured to couple different ones of the plurality of capacitors in parallel with the one or more bypass capacitors during different ones of the successive power up events responsive to assertion of the different ones of the plurality of control signals. 
 
     
     
       17. The system as recited in  claim 16  further comprising a voltage source coupled to the plurality of switches, wherein each switch is configured to electrically couple the respective capacitor to the voltage source responsive to a deassertion of the respective control signal. 
     
     
       18. The system as recited in  claim 16  wherein the respective capacitor is coupled in parallel with the one or more bypass capacitors responsive to the assertion of the respective control signal to the respective switch. 
     
     
       19. A method comprising:
 detecting that a supply voltage of an integrated circuit is to be powered up from a powered-down state; 
 asserting a first control signal to a first switch that is coupled to a supply voltage node of the integrated circuit and is further coupled to a first capacitor, wherein the asserting is responsive to the detecting; 
 powering-down the supply voltage; 
 detecting that the supply voltage is to be powered up again; and 
 asserting a second control signal to a second switch that is coupled to the supply voltage node and to a second capacitor, wherein the asserting is responsive to the detecting that the supply voltage is to be powered up again. 
 
     
     
       20. The method as recited in  claim 19  wherein the asserting causes the first switch to electrically couple the first capacitor to the supply voltage node. 
     
     
       21. The method as recited in  claim 20  further comprising charging the first capacitor during times that the first control signal is deasserted. 
     
     
       22. The method as recited in  claim 19  wherein, responsive to the assertion of the first control signal, the first capacitor is in parallel with one or more bypass capacitors that are coupled to the integrated circuit.

Description:
This application is a continuation of U.S. application Ser. No. 11/173,582, filed Jul. 1, 2005 now U.S. Pat. No. 7,564,226. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     This invention is related to the field of electronic systems and, more particularly, to providing a supply voltage to an integrated circuit in an electronic system. 
     2. Description of the Related Art 
     As the number of transistors included on a single integrated circuit “chip” has increased and as the operating frequency of the integrated circuits has increased, the management of power consumed by an integrated circuit has continued to increase in importance. If power consumption is not managed, meeting the thermal requirements of the integrated circuit (e.g. providing components required to adequately cool the integrated circuit during operation to remain within thermal limits of the integrated circuit) may be overly costly or even infeasible. Additionally, in some applications such as battery powered (e.g. portable) devices such as laptops, personal digital assistants (PDAs), mobile phones, etc., managing power consumption in an integrated circuit may be key to providing acceptable battery life. 
     For those devices that include a processor, or central processing unit (CPU), a common power management technique is to power down the processor if there are no computation requirements for the processor. In the powered-down state, the supply voltage has been deactivated (or “turned off”). However, when the user of the device requires an operation that involves the processor, the response time must be very fast to avoid the appearance of low performance to the user. To support a rapid response to user input from the powered-down state, the processor&#39;s supply voltage must rise rapidly (e.g. in the range of 1-10 microseconds) so that the processor can start executing instructions. Increasing the magnitude of the supply voltage (e.g. from ground to the specified voltage magnitude for the processor) is also referred to as “ramping” the supply voltage. 
     Currently, DC-DC converters are typically used in mobile devices to provide rapid ramp of the supply voltage. The efficiency of DC-DC converters is typically high, but the size and cost of the devices involved in a fast converter is often prohibitive for cost sensitive applications or volume sensitive applications. The ramp time is generally limited by the amount of bypass capacitance required by the CPU to operate and by the size of the transistors used in the switcher of the DC-DC converter. The efficiency of the DC-DC converter depends on the switching losses in the transistor (i.e. the larger the transistor, the higher the loss). To provide a fast ramp time, the converter analog circuits need to have a wide bandwidth and operate at fast switching frequencies, which increases the losses. On top of that, the circuits are typically high order circuits that cause overshoot in the supply voltage. The overshoot can damage the CPU. 
     SUMMARY 
     In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor, and a voltage source configured to charge the first capacitor. The switch is coupled to receive a control signal that is asserted, during use, if the supply voltage to the integrated circuit is to be increased. The switch is configured to electrically couple the first capacitor to the node in response to an assertion of the control signal. When electrically coupled to the node, the first capacitor supplies charge to the bypass capacitors. A system comprising the apparatus, the node, the integrated circuit, and the bypass capacitors is also contemplated in some embodiments. 
     In another embodiment, a method comprises detecting that a supply voltage to an integrated circuit is to be increased and electrically coupling a first capacitor to a supply voltage node to the integrated circuit responsive to the detecting. One or more bypass capacitors are also coupled to the power supply node in parallel with the integrated circuit, and the capacitor provides charge to the bypass capacitors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG. 1  is a block diagram of one embodiment of a system including an integrated circuit and apparatus to provide a supply voltage to the integrated circuit. 
         FIG. 2  is a formula for the supply voltage. 
         FIG. 3  is a timing diagram illustrating certain signals and voltages for one embodiment of the system shown in  FIG. 1 . 
         FIG. 4  is a block diagram of a second embodiment of a system including an integrated circuit and apparatus to provide a supply voltage to the integrated circuit. 
     
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Turning now to  FIG. 1 , a block diagram of a system  10  is shown. In one embodiment, the system  10  includes an integrated circuit  12  (which includes at least one processor  14 , in some embodiments), bypass capacitors such as bypass capacitors  16 A- 16 B, a main voltage regulator  18 , a switch  20 , a control circuit  22 , a restart voltage regulator  24 , and a capacitor  26 . The integrated circuit  12  is coupled to a supply voltage node  34  that is to be driven to the supply voltage (V dd ) during normal operation (e.g. a powered-up state). Specifically, the integrated circuit  12  may include one or more input “pins”  36  coupled to the node  34 . The pins may be any external conductors that provide connection with the integrated circuit  12 . The integrated circuit  12  may also be coupled to ground via other pins (not shown). The bypass capacitors  16 A- 16 B are coupled in parallel with the integrated circuit  12  between the node  34  and ground. The main regulator  18  is also coupled to the node  34 . The switch  20  is coupled to the node  34 , and is also coupled to the capacitor  26  and to receive a voltage V Reg  from the restart regulator IS  24 . The switch  20  is further coupled to receive a control signal (Ramp_Fast in  FIG. 1 ) from the control circuit  22 , which is coupled to receive a wakeup signal. The main regulator  18  is coupled to receive the wakeup signal as well. The control circuit  22  is further coupled to provide a start signal to the integrated circuit  12 . 
     In a powered-down state, the main regulator  18  has deactivated the V out  output and the voltage on the supply node  34  drains to ground. Circuitry in the system  10  (not shown in  FIG. 1 ) may detect that the integrated circuit  12  is to be restarted (that is, changed from the powered-down state to a powered-up state). For example, in embodiments in which the integrated circuit  12  includes a processor  14 , a user input or other system activity may be detected which requires instruction execution by the processor  14 . The circuitry may assert the wakeup signal to the control circuit  22  and the main regulator  18 . 
     In response to the wakeup signal, the control circuit  22  may assert the Ramp_Fast signal to the switch  20 . In response to the asserted Ramp_Fast signal, the switch  20  electrically couples the capacitor  26  to the node  34 . The capacitor  26  has a capacitance C Charge , and may be precharged prior to being coupled to the node  34  with a voltage (e.g. V Reg , in the illustrated embodiment). When the switch  20  electrically couples the capacitor  26  to the node  34 , the capacitor  26  is effectively in parallel with the bypass capacitors  16 A- 16 B, and rapidly provides charge to the bypass capacitors  16 A- 16 B. Accordingly, a rapid ramp of the node  34  from ground to a voltage magnitude referred to herein as V ddramp  may be provided. For example, in some implementations, a ramp to the V ddramp  may occur on the order of  1  microsecond, although faster or slower ramp times may be supported in other embodiments. Generally, the ramp time may depend on the equivalent series inductance (ESL) and equivalent series resistance (ESR) of the capacitors and the series resistance of the switch  20  (e.g. the series resistance of the transistor  28 , for the embodiment of the switch  20  illustrated in  FIG. 1 ). Additionally, the capacitor  26 , the bypass capacitors  16 A- 16 B, and the switch  20  may be a first order circuit, and thus the supply voltage may not overshoot the V ddramp  voltage. The integrated circuit  12  may thus be protected from excessive supply voltage even though a relatively fast ramp time is supported. 
     The control circuit  22  may be configured to assert the start signal to the integrated circuit  12  after asserting the Ramp_Fast signal, with enough delay to ensure that the node  34  has been ramped to V ddramp . Responsive to the start signal, the integrated circuit  12  may begin operating (e.g. the processor  14  may begin executing instructions). Thus, the integrated circuit  12  may begin operating rapidly. In some embodiments, the integrated circuit  12  may begin operating prior to the main regulator  18  providing the supply voltage on the node  34 . The bypass capacitors  16 A- 16 B may supply the voltage until the main regulator  18  outputs the supply voltage. In some embodiments, a regulator that is relatively slow to turn on may be used as the main regulator  18 , since the bypass capacitors  16 A- 16 B supply the voltage for rapid wakeup of the integrated circuit  12  (and thus the main regulator  18  may be less expensive then may otherwise required for fast ramp of the supply voltage). For example, a regulator with a turn on time on the order of 100 microseconds may be used, although faster or slower turn times may be implemented in other embodiments. 
     The capacitance C charge  of the capacitor  26  may be selected dependent on the total bypass capacitance C byp  to provide a voltage V ddramp  sufficient to ensure that integrated circuit  12  operates correctly.  FIG. 2  is an equation  40  that illustrates the approximate value Of V ddramp  based on the capacitances and the voltage on the capacitor  26  at the time the switch  20  electrically couples the capacitor to the node  34  (e.g. V Reg  in the illustrated embodiment). For example, in one embodiment, the integrated circuit  12  may be operable at several operating frequencies. The capacitance of the capacitor  26  may be selected so that the V ddramp  voltage exceeds, by a desired margin, the minimum supply voltage specified for the integrated circuit  12  to operate at its lowest operating frequency. The minimum specified supply voltage will be referred to herein as V ddspec . The main regulator  18  may subsequently supply V ddspec  on the node  34 . 
     By selecting the capacitances so that V ddramp  exceeds V ddspec  by some margin, the input voltage that charges the capacitor  26  (V Reg ) need not be carefully regulated, in some embodiments. For example, while the embodiment of  FIG. 1  includes the restart regulator  24 , other embodiments may have any voltage source for the V Reg  voltage used to charge the capacitor  26 . The voltage source may limit (or bound) the V Reg  voltage, but may not regulate it. 
     Generally, the switch  20  may comprise any components which electrically couple the capacitor  26  to the node  34  in response to an assertion of the control signal (Ramp_Fast in  FIG. 1 ). The switch  20  may also electrically isolate the capacitor  26  from the node  34  in response to deassertion of the control signal. In some embodiments, the switch  20  may electrically isolate the capacitor  26  from the V Reg  voltage source in response to assertion of the control signal and may electrically couple the capacitor  26  to the V Reg  voltage source (to charge the capacitor  26 ) in response to deassertion of the control signal. The series resistance of the switch  20  between the capacitor  26  and the node  34  when electrically coupling the capacitor  26  to the node  34  may be as low as possible to enhance the ramp time for the node  34  to the V ddramp  voltage. On the other hand, the series resistance of the switch  20  between the capacitor  26  and the V Reg  voltage source, when electrically coupled, may be higher. In some cases, it may be desirable that the series resistance between the capacitor  26  and the V Reg  voltage source is higher. For example, if the restart regulator  24  also supplies voltage to other circuitry (e.g. an input voltage to the main regulator  18 , illustrated by dotted line  38 ), having a higher series resistance may reduce the current draw of the capacitor  26  when charging, which may minimize the disturbance of the V Reg  voltage when charging the capacitor  26 . 
     In one embodiment, the switch  20  comprises transistors  28  and  30  and an inverter  32 . The transistor  20  may have its gate coupled to receive the control signal Ramp_Fast and may be coupled between the capacitor  26  and the node  34 . The transistor  30  may be coupled between the capacitor  26  and the V Reg  voltage output from the restart regulator  24 , and its gate may be coupled to receive the inversion of the control signal Ramp_Fast through the inverter  32 . 
     If the control signal is deasserted, the transistor  28  not actively conducting current and the capacitor  26  is electrically isolated from the node  34 . The transistor  30 , receiving an inversion of the control signal, is conductive, and the capacitor  26  is charged to the V Reg  voltage through the transistor  30 . If the control signal is asserted, the transistor  28  is conductive and electrically couples the capacitor  26  to the node  34 . The transistor  30  is not actively conducting current, and electrically isolates the capacitor  26  from the V Reg  voltage source. In one embodiment, the series resistance of the transistor  28 , when conductive, is less than the series resistance of the transistor  30 . 
     In the illustrated embodiment, the transistors  28  and  30  are N-type metal-oxide-semiconductor (NMOS) transistors. In other embodiments, other transistors/transistor-types may be used. For example, P-type MOS (PMOS) transistors may be used as one or both of the transistors  28  and  30 . Alternatively, passgates may be used in place of the transistors  28  and/or  30  (in which an NMOS and a PMOS are connected in parallel and the gate of the PMOS is controlled by an inversion of the signal that controls the NMOS or vice versa). In some embodiments, the transistor  30  may not be included and the V Reg  voltage source may be coupled directly to the capacitor  26 . 
     The regulators  18  and  24  may be any type of voltage regulator (e.g. switching regulators, linear regulators such as low drop out voltage regulators, series regulators, etc.). In some embodiments, the regulator  24  may provide the input voltage to the regulator  18 , as illustrated by dotted line  38 . For example, in one implementation, the regulator  24  may receive the input voltage to the system  10  (e.g. a battery input) and may regulate the voltage down to the V Reg  voltage. The regulator  18  may regulate the V Reg  voltage down to the V dd  voltage. In one particular embodiment, the battery input may be 19 volts, the V Reg  voltage may be 3.3 volts, and the V dd  voltage may be between 0.5 and 1 volt depending on a voltage ID output from the integrated circuit  12 . 
     The bypass capacitors  16 A- 16 B may be provided in close physical proximity to the integrated circuit  12 , and may serve to filter voltage variations on the node  34  to help stabilize the V dd  supply voltage provided to the integrated circuit  12 . Any number of bypass capacitors may be provided in various embodiments. 
     The integrated circuit  12  may be any type of integrated circuit, implementing any set of desired functions. In the illustrated embodiment, the integrated circuit  12  includes at least one processor  14 . For example, the integrated circuit  12  may be a discrete single processor. The integrated circuit  12  may be a chip multiprocessor (CMP) including two or more processors. The integrated circuit  12  may integrate one or more processors and other components in a system on a chip configuration. 
     The node  34  may comprise any conductive material capable of conducting the supply voltage to the points  36  of the integrated circuit  12  and capable of carrying enough current to supply the current needs of the integrated circuit  12 . For example, the node  34  may comprise a conductor, multiple conductors, a plane of conductive material, or combinations thereof. 
     It is noted that, while the above description refers to ramping the supply voltage on the node  34  from ground to V ddramp , other embodiments may ramp the supply voltage from one voltage to another. Generally, a powered-down state may refers to any state in which the power supply voltage is at a lower level from which it may be increased (e.g. to increase the frequency of operation, to restart operation, etc.). The supply voltage magnitude for the powered-down state may be zero volts (ground) or any other voltage magnitude. For example, a powered-down state may comprise a low voltage that retains data in memory circuits in the integrated circuit  12  but does not permit operation of the integrated circuit  12 . Powering up from the powered down state may include increasing the voltage from the lowered voltage to a voltage at which the integrated circuit  12  may operate. Powering up may also include increasing the voltage from any lowered voltage (e.g. a lower voltage at which the integrated circuit  12  may operate at a lower frequency) to a higher voltage (e.g. a voltage at which the integrated circuit  12  may operate at a higher frequency). It is noted that, in the present description, voltages may be described as higher or lower than other voltages, or greater than or less than other voltages. Ramping of voltages to certain levels may also be referred to. Such terminology may refer to the magnitudes of the voltages. 
     It is noted that, while the control circuit  22  generates the Ramp_Fast signal in the illustrated embodiment responsive to the Wakeup signal, other embodiments may use any other control signal for the switch  30 . For example, the Wakeup signal may be used directly as the Ramp_Fast signal. 
       FIG. 3  is a timing diagram illustrating various signals and voltages shown in  FIG. 1  for one embodiment. Time increases from left to right in  FIG. 3 , using arbitrary units. Illustrated in  FIG. 3  is V dd  (the voltage on the node  34 ), V CCharge  (the voltage on the capacitor  26 ), and V Out  (the voltage generated by the main regulator  18 ). V Out  is shown in  FIG. 3  to illustrate the ramp of the voltage generated by the main regulator  18 , and thus does not illustrate the effects of other voltages on the node  34 , even though V Out  is shown as the output of the main regulator  18  to the node  34  in  FIG. 1 . 
     On the left in  FIG. 3 , the V dd  voltage and V Out  voltage are at ground (GND) and the V CCharge  voltage is at V Reg . The Ramp_Fast, Wakeup, and Start signals are deasserted. Subsequently, the Wakeup signal is asserted and the control circuit  22  asserts the Ramp_Fast signal in response. The V dd  voltage rapidly ramps to the V ddramp  voltage (and the V CCharge  voltage drops to the V ddramp  voltage) responsive to assertion of the Ramp_Fast signal (dotted line  50 ). The main regulator  18  also responds to the assertion of the Wakeup signal by ramping the V Out  voltage to V ddspec , at a slower rate than V dd  ramps to V ddramp . The Wakeup signal deasserts, and the control circuit  22  deasserts the Ramp_Fast signal in response. Additionally, after a predetermined period of time from the assertion of the Ramp_Fast signal, the control circuit  22  asserts the Start signal. The period of time may be sufficient to ensure that the node  34  has ramped to the V ddramp  voltage. Note that the Start signal is asserted prior to the time that the main regulator  18  is able to generate the V out  voltage at the V ddspec  level. 
     The V dd  voltage begins decaying from the V ddramp  level as the integrated circuit  12  consumes power during operation, responsive to assertion of the start signal (dotted line  52 ). The V dd  voltage stabilizes at the V ddspec  level via the operation of the main regulator  18 . Additionally, the V CCharge  voltage begins recovering from the V ddramp  voltage to the V Reg  voltage responsive to deassertion of the Ramp_Fast signal (dotted line  54 ). 
     Horizontal dotted lines are illustrated in  FIG. 3  to help illustrates the changes in voltage magnitudes that have a shallow slope in  FIG. 3 . It is noted that, while V Out  and V dd  are initially at ground in the example of  FIG. 3 , in other embodiments V Out  and V dd  may be at any starting voltage (e.g. a lower voltage that retains memory state in the integrated circuit  12  but at which the integrated circuit  12  is not in operation). 
     Turning next to  FIG. 4 , a second embodiment of the system  10  is shown. The embodiment of  FIG. 4  includes the components  12 ,  16 A- 16 B,  18 ,  20 ,  22 ,  24 , and  26 , coupled in a similar fashion to the like-numbered components in  FIG. 1 . The Ramp_Fast signal to the switch  20  is labeled Ramp_Fast 1  in the embodiment of  FIG. 4 . Additionally, a second switch  60  and a second capacitor  62  is shown coupled in parallel with the switch  20  and capacitor  26 . That is, the switch  60  is coupled to the node  34  and to receive the V Reg  voltage from the restart regulator  24 . The switch  60  is coupled to the capacitor  62  and is coupled to receive a Ramp_Fast 2  control signal from the control circuit  22 . The capacitor  62  has a capacitance C Charge , similar to the capacitor  26 . 
     The switch  60  and the capacitor  62  may operate in similar fashion to the switch  20  and the capacitor  26 , as described above. By providing the switch  60  and the capacitor  62 , successive assertions of the Wakeup signal may be handled alternately between the switch  20 /capacitor  26  and the switch  60 /capacitor  62 . That is, the control circuit  22  may assert the Ramp_Fast 1  signal in response to a first assertion of the Wakeup signal, assert the Ramp_Fast 2  signal in response to a second assertion of the Wakeup signal, assert the Ramp_Fast 1  signal in response to a third assertion of the Wakeup signal, etc. 
     By including the switch  60  and the capacitor  62 , the charge time for the capacitors  26  and  62  may be relatively long and still provide the V ddramp  voltage even if the system  10  is “woken up” more than once within the recharge time of the capacitors, in some embodiments. While two sets of switches and capacitors are shown in  FIG. 4 , any number may be included in other embodiments. 
     The switch  60  may be similar to the switch  20 . For example, in the illustrated embodiment, the switch  60  includes a pair of transistors and an inverter, similar to the transistors  28  and  30  and inverter  32  in  FIG. 1 . 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Metadata:
Filing Date: 20090618
Publication Date: 20101116
Grant Date: 20101116
Priority Date: 20050701
Inventors: VON KAENEL VINCENT R.
Assignee: APPLE INC
CPC Classifications: [{"code": "Y10S323/901", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F1/26", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02J7/345", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02J7/345", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F1/26", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 37588710