PATENT DOCUMENT

Publication Number: US-8572335-B2
Application Number: US-201213476605-A
Country: US
Kind Code: B2

Title: Copyback optimization for memory system

Abstract:
In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory.

Claims:
What is claimed is: 
     
       1. A method comprising:
 receiving a data page, wherein the data page includes data, metadata, an Error Correction Code (ECC) for the data, and an ECC for the metadata; 
 computing an initial data change indicator (DCI) for the received data page; 
 storing the data page in a non-volatile memory of a memory subsystem; 
 retrieving the data page from the non-volatile memory; 
 determining if the data page has changed; 
 sending the data page to a controller responsive to the determination that the data page has changed; and 
 sending a portion of the data page to the controller responsive to the determination that the data page has not changed, wherein the portion of the data page excludes the data. 
 
     
     
       2. The method of  claim 1 , further comprising storing the computed initial DCI for the received data page. 
     
     
       3. The method of  claim 2 , wherein the determining if the data page has changed comprises reading the stored initial DCI. 
     
     
       4. An apparatus, comprising:
 a non-volatile memory including a memory array, and a register; and 
 a controller coupled to the non-volatile memory and configured to: 
 receive a data page, wherein the data page includes data, metadata, an Error Correction Code (ECC) for the data, and an ECC for the metadata; 
 store the data page in the register; 
 compute an initial data change indicator (DCI) for the received data page; 
 store the initial DCI in the memory array; 
 transfer the data page from the register to the memory array responsive to the storing of the initial DCI in the memory array; 
 retrieve the data from the memory array; 
 determine if the data page has changed; and 
 
       perform an operation on the data page responsive to the determination that the data page has changed. 
     
     
       5. The apparatus of  claim 4 , wherein the non-volatile memory further includes an internal state machine configured to transfer the data page from the memory array to the register. 
     
     
       6. The apparatus of  claim 4 , wherein the controller further includes an error correction code (ECC) engine. 
     
     
       7. The apparatus of  claim 6 , wherein the controller is further configured to perform an operation on the metadata included in the data page responsive to the determination that the data page has not changed. 
     
     
       8. The apparatus of  claim 7 , wherein the ECC engine is configured to generate an ECC dependent upon the initial DCI. 
     
     
       9. A memory subsystem, comprising:
 means for receiving a data page, wherein the data page includes data, metadata, an Error Correction Code (ECC) for the data, and an ECC for the metadata; 
 means for computing an initial data change indicator (DCI) for the data page; 
 means for storing the data page in a non-volatile memory of a memory subsystem; 
 means for retrieving the data page from the non-volatile memory; 
 means for determining if the data page has changed; 
 means for sending the data page to a controller responsive to determining the data page has changed; and 
 means for sending a portion of the data page to the controller responsive to determining the data page has not changed, wherein the portion of the data page excludes the data. 
 
     
     
       10. The memory subsystem of  claim 9 , wherein the means for storing the data page comprises means for storing the initial data change indicator in the non-volatile memory. 
     
     
       11. The memory subsystem of  claim 9 , wherein the initial DCI comprises an error correction code. 
     
     
       12. The memory subsystem of  claim 9 , wherein the means for retrieving the data page comprises means for storing the data page in a memory register. 
     
     
       13. A method, comprising:
 receiving a data page for storage in a memory, wherein the data page includes data, metadata, an Error Correction Code (ECC) for the data, and an ECC for the metadata; 
 transferring the received data page into a register; 
 computing an initial data change indicator (DCI) for the received data page; 
 storing the computed initial DCI in the memory; and 
 transferring the data page from the register to the memory responsive to the storing of the computed DCI in the memory. 
 
     
     
       14. The method of  claim 13 , wherein the initial DCI comprises an error detection code (EDC). 
     
     
       15. The method of  claim 14 , wherein the EDC comprises cyclic redundancy check (CRC). 
     
     
       16. The method of  claim 14 , wherein the EDC comprises an error correction code (ECC). 
     
     
       17. The method of  claim 13 , wherein the memory comprises a non-volatile memory.

Description:
RELATED APPLICATION 
     This application is a continuation (and claims the benefit of priority under 35 USC 120) of U.S. application Ser. No. 12/193,638, filed Aug. 18, 2008, now allowed, which claims the benefit of priority from U.S. Provisional Application No. 61/049,330, for “Copyback Optimization for Memory System,” filed Apr. 30, 2008. Both of these prior applications are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     This subject matter is generally related to memory systems. 
     BACKGROUND 
     Flash memory is a type of electrically erasable programmable read-only memory (EEPROM). Because flash memories are non-volatile and relatively dense, they are used to store files and other persistent objects in handheld computers, mobile phones, digital cameras, portable music players, and many other devices in which other storage solutions (e.g., magnetic disks) are inappropriate. When data stored in flash memory is processed, a data page is read out of flash memory and stored in a register. The register contents is transferred to a controller that is external to the non-volatile memory for processing. The processed data page is placed back in the register so that the processed data page can be written back to flash memory. 
     SUMMARY 
     In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1A  is a block diagram of an example memory system for implementing an optimized copyback process. 
         FIG. 1B  is a block diagram of another example memory system for implementing an optimized copyback process. 
         FIG. 2  is a flow diagram of an example optimized copyback process  200  for computing and storing data change indicators used by the memory systems of  FIGS. 1A and 1B . 
         FIGS. 3A-3C  are flow diagrams of an example optimized copyback process implemented by the memory systems of  FIGS. 1A and 1B . 
         FIG. 4  is a flow diagram of an example optimized read operation implemented by the memory systems of  FIGS. 1A and 1B . 
         FIG. 5  illustrates example data structures used by the copyback process of  FIGS. 3A-3C . 
     
    
    
     DETAILED DESCRIPTION 
     Examples of Memory Subsystems 
       FIG. 1A  is a block diagram of an example memory system  100  for implementing an optimized copyback process. In some implementations, the system  100  can include a memory subsystem  102  coupled to a host device  124  through an external bus  122  (e.g., Open NAND Flash Interface (ONFI), ATA). The host device  124  can be any electronic device including but not limited to smart phones, media players, text messaging devices, portable computers, solid state drives, digital cameras, etc. The memory subsystem  102  can be any non-volatile memory subsystem (e.g., managed NAND). 
     The host device  124  can include a system-on-chip (SoC)  126  and volatile memory  128 . The SoC  126  can include hardware and software for interacting with the memory subsystem  102 , such as transmitting read and write requests made by applications running on the host device  124 . 
     The memory subsystem  102  can include non-volatile memory  104  (also referred to as “raw memory”) and an external controller  116 . The memory  104  can include a memory cell array  106 , an internal state machine  108 , a memory register  110  and data change indicator (DCI)  130 . The controller  116  can include a processor  118 , volatile memory  114  and error correction code (ECC) engine  120 . Other configurations for the memory subsystem  102  are possible. For example, a cache register can be included in the data path between the memory cell array  106  and the memory register  110  to allow the internal state machine to read the next data page from the memory cell array  106  while transferring the current page to the controller  116  over internal bus  112 . 
       FIG. 1B  is a block diagram of another example memory system  130  for implementing an optimized copyback process. The system  130  shows only the memory subsystem  102 , the operation of which was described in reference to  FIG. 1A . 
     Copyback Operations 
     Copyback can be a memory subsystem command to move data from one page to another page. Copyback can be used in wear leveling and other non-volatile memory management operations. In a typical copyback operation, a data page is read from the memory cell array  106  and stored in the memory register  110  by the internal state machine. The external controller  116  reads or clocks the data page out of the memory register  110  so that the processor  118  can perform a desired operation on the data page (e.g., an ECC operation). The processed data page can be written back to the memory register  110  by the controller  116 . The internal state machine  108  can write the contents of the memory register  110  into a new data page in the memory cell array  106 . By avoiding the transfer of the entire contents of register  110  to the external controller  116 , processing times and power consumption can be reduced. 
     Example Process For Writing New Data Pages 
       FIG. 2  is a flow diagram of an example optimized copyback process  200  for computing and storing data change indicators used by the memory systems of  FIGS. 1A and 1B . In some implementations, the process  200  can begin when new data page is transferred into a memory register of a memory subsystem ( 202 ). A DCI can be computed for the data page and stored in the memory subsystem ( 204 ). Some examples of data change indicators can include error detection codes (EDCs), including but not limited to: checksum, Hamming code, parity bit, cyclic redundancy check (CRC), polarity symbol reversal, Turbo code, etc. An EDC can also be part of an ECC, such as Reed-Solomon code, Reed-Muller code, Binary Golay code, and low-density parity-check codes. After the DCIs are computed and stored, the register contents can be written to non-volatile memory ( 206 ). DCIs can be used for the optimized copyback process described in reference to  FIGS. 3A-3C . 
     Example Optimized Copyback Process 
       FIGS. 3A-3C  are flow diagrams of an example optimized copyback process  300  implemented by the memory systems of  FIGS. 1A and 1B . In some implementations, the process  300  can begin by reading a data page from non-volatile memory (e.g., memory cell array  106 ) and storing the data page in a memory register ( 302 ) (e.g., register  110 ). A DCI (e.g., DCI  130 ) can be verified for the data page in the memory register ( 304 ). In some implementations, the DCI can be previously computed and stored in the memory subsystem when the data page is first written to non-volatile memory (e.g., using process  200 ). In other implementations, the DCI can be computed “on the fly” as part of the read operation or as a separate operation. The memory subsystem can report to an external controller (e.g., external controller  116 ) that the read operation has completed ( 306 ). 
     If the DCI for the data page in the register indicates that the data page has changed ( 308 ), the data page can be transferred to the external controller ( 310 ), an ECC can be computed for the data page ( 312 ) and the ECC information for the data page can be corrected in the external controller ( 314 ). The data page and associated ECC can be transferred back to the memory register ( 316 ). A new DCI can be computed for the data page in the memory register ( 318 ). 
     If the DCI for the data page in the register indicates that the data page has not changed ( 308 ), an ECC can be computed for new metadata associated with the data page ( 320 ). The new metadata and associated ECC can be transferred to the memory register ( 322 ). A new DCI can be computed for the metadata in the memory register ( 324 ). The memory register contents can be written to a new data page in non-volatile memory ( 326 ). 
     Optimized Read Operation 
       FIG. 4  is a flow diagram of an example optimized read operation implemented by the memory systems of  FIGS. 1A and 1B . In some implementations, the process  400  can begin by reading a data page from non-volatile memory and storing the data page in a memory register ( 402 ). A pre-computed DCI associated with the data page can be clocked into the memory register from a storage location in the memory subsystem and verified ( 404 ). The DCI can also be computed “on the fly.” The status of the DCI can be read to determine if the data page has changed ( 406 ). 
     If the data page has changed ( 408 ), an ECC for the new metadata associated with the data page can be computed and transferred, together with the new metadata to the memory register ( 412 ). A new DCI can be computed for the metadata in the memory register and the register contents can be written to a new data page in non-volatile memory ( 414 ). 
     If the data page has not changed ( 408 ), the memory register contents can be transferred to an external controller and an ECC can be computed by the external controller ( 410 ). An ECC for the new metadata associated with the data page can be computed and transferred by the external controller, together with the new metadata to the memory register ( 412 ). A new DCI can be computed for the metadata in the memory register and the register contents can be written to a new data page in non-volatile memory ( 414 ). 
     Example Data Structures 
       FIG. 5  illustrates example data structures used by the copyback process of  FIGS. 3A-3C . In the example shown, a data page  500  in non-volatile memory includes metadata  502 , metadata ECC  504 , data  506  and data ECC  508 . If the data has not changed than only the metadata  502  and the metadata ECC  504  are transferred from the register to the external controller  510  for processing. The processed metadata  502  and metadata ECC  504  are transferred back to the memory subsystem and stored in the memory register. The data page can the be written to a new data page in non-volatile memory (e.g., a memory cell array). 
     A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, elements of one or more implementations may be combined, deleted, modified, or supplemented to form further implementations. As yet another example, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

Metadata:
Filing Date: 20120521
Publication Date: 20131029
Grant Date: 20131029
Priority Date: 20080430
Inventors: WAKRAT NIR JACOB
HELM MARK ALAN
Assignee: APPLE INC
CPC Classifications: [{"code": "G11C16/06", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F11/10", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F11/1068", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F11/1068", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 40801795