PATENT DOCUMENT

Publication Number: US-8332543-B2
Application Number: US-201213359533-A
Country: US
Kind Code: B2

Title: Command queue for peripheral component

Abstract:
In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Claims:
1. An apparatus to control an external interface in an integrated circuit, the apparatus comprising:
 a controller configured to communicate on the external interface; 
 a command queue configured to store a plurality of commands that cause a transfer on the external interface; 
 a macro memory configured to store a second plurality of commands forming a macro; and 
 a control circuit coupled to the command queue, the macro memory, and the controller, wherein the control circuit is configured to read the plurality of commands from the command queue and is configured to initiate corresponding operations in the controller to perform the transfer, and wherein the control circuit is configured to invoke the macro responsive to detecting a macro command within the plurality of commands from the command queue, wherein the macro command includes a length operand specifying a length of the macro, and wherein the control circuit is configured to return to the plurality of commands in the command queue responsive to completing the macro as specified by the length operand, and wherein the macro excludes an explicit return command. 
 
     
     
       2. The apparatus as recited in  claim 1  further comprising a plurality of control registers coupled to the controller and the control circuit, wherein the controller is configured to communicate on the external interface responsive to a content of the plurality of control registers, and wherein the plurality of commands include one or more commands that cause the control circuit to update one or more of the plurality of control registers. 
     
     
       3. The apparatus as recited in  claim 2  wherein the second plurality of commands include one or more commands that cause the control circuit to update one or more of the plurality of control registers. 
     
     
       4. The apparatus as recited in  claim 2  wherein the control circuit is configured to receive an operation on an internal interface within the integrated circuit, wherein the operation indicates a direct update of one of the plurality of control registers, and wherein the control circuit is configured to update one of the control registers in response to receiving the operation. 
     
     
       5. The apparatus us recited in  claim 4  wherein the control circuit is further configured to receive the plurality of commands on the internal interface, and wherein the control circuit is configured to write the plurality of commands into the command queue responsive to receiving the plurality of commands. 
     
     
       6. The apparatus as recited in  claim 1  wherein the external interface is a memory interface, and wherein the plurality of commands include a first command that causes the controller to drive an address to one or more memory devices that are coupled to the memory interface. 
     
     
       7. The apparatus as recited in  claim 6  wherein the plurality of commands include a second command that causes the controller to drive a specified one or more chip enable signals to the one or more memory devices. 
     
     
       8. The apparatus as recited in  claim 6  wherein the plurality of commands include a second command that causes the controller to transfer a page of data between the integrated circuit and one or more memory devices. 
     
     
       9. A method comprising:
 reading a plurality of commands from a command queue in a memory interface unit of an integrated circuit; and 
 causing a controller to communicate on an external interface of the integrated circuit to one or more memory devices coupled to the external interface responsive to the plurality of commands in the command queue, wherein the plurality of commands cause a memory transfer between the one or more memory devices and the integrated circuit, wherein a memory transfer comprises one or more pages of data; 
 detecting a macro command in the plurality of commands; 
 invoking a second plurality of commands in a macro memory responsive to the macro command, wherein the second plurality of commands form a macro, and wherein the macro command includes a length operand specifying a length of the macro; and 
 returning to the plurality of commands in the command queue responsive to completing the macro as specified by the length operand, and wherein the macro excludes an explicit return command. 
 
     
     
       10. The method as recited in  claim 9  wherein the plurality of commands include a first command that causes the controller to transmit an address to the one or more memory devices, a second command that causes the controller to transmit a set of chip enables to the one or more memory devices, and at least one third command that causes the controller to transfer a page of data. 
     
     
       11. The method as recited in  claim 9  wherein the plurality of commands comprise a first command that causes the controller to transmit a corresponding command to the one or more memory devices on the interface, the corresponding command defined in a memory interface protocol for the one or more memory devices. 
     
     
       12. The method as recited in  claim 11  wherein the one or more memory devices comprise one or more flash memory devices, and wherein the corresponding command comprises a command byte defined on a flash memory interface supported by the one or more flash memory devices. 
     
     
       13. The apparatus as recited in  claim 1  wherein the length operand specifies a number of words in the macro. 
     
     
       14. The apparatus as recited in  claim 1  wherein the length operand specifies a number of commands in the macro. 
     
     
       15. A flash memory interface unit comprising:
 a flash memory controller configured to communicate with a flash memory; 
 a command queue configured to store a plurality of commands; 
 a macro memory configured to store a second plurality of commands forming a macro; and 
 a control circuit coupled to the command queue, the macro memory, and the flash memory controller, wherein the control circuit is configured to read the plurality of commands from the command queue, and wherein the control circuit is configured to invoke the macro responsive to detecting a macro command within the plurality of commands from the command queue, wherein the macro command includes a length operand specifying a length of the macro, and wherein the control circuit is configured to return to the plurality of commands in the command queue responsive to completing the macro as specified by the length operand, and wherein the macro excludes an explicit return command. 
 
     
     
       16. The flash memory interface unit as recited in  claim 15  wherein the length operand specifies a number of words in the macro. 
     
     
       17. The flash memory interface unit as recited in  claim 15  wherein the length operand specifies a number of commands in the macro. 
     
     
       18. A non-transitory computer accessible storage medium storing a plurality of instructions executable by a processor in a system with a flash memory interface unit that includes a flash memory controller configured to communicate with a flash memory; a command queue configured to store a plurality of commands; a macro memory configured to store a second plurality of commands forming a macro; and a control circuit coupled to the command queue, the macro memory, and the flash memory controller; wherein the plurality of instructions, when executed by the processor:
 write the plurality of commands to the command queue, wherein the plurality of commands include a macro command, wherein the macro command includes a length operand specifying a length of the macro; and 
 write the macro to the macro memory, wherein the macro excludes an explicit return command because the control circuit is configured to return to the plurality of commands in the command queue responsive to completing the macro as specified by the length operand. 
 
     
     
       19. The non-transitory computer accessible storage medium as recited in  claim 18  wherein the plurality of instructions, when executed, write a plurality of operands to an operand queue in the flash memory controller, wherein the operands are accessible by both the plurality of commands in the command queue and the macro.

Description:
This application is a divisional application of U.S. patent application Ser. No. 12/615,587, filed Nov. 10, 2009, now U.S. Pat. No. 8,131,889. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     This invention is related to the field of integrated circuits and, more particularly, to command processing in a peripheral component in an integrated circuit. 
     2. Description of the Related Art 
     In a peripheral interface controller that has significant data bandwidth, one of the challenges that can occur is providing the control input to the peripheral interface controller from an external processor. Typically, the same internal interface to the peripheral controller that transfers data between the peripheral interface controller and memory is used to provide the control input from the external processor (e.g. via a series of writes to control registers in the peripheral interface controller). While the data transfers are occurring, the memory to peripheral interface can be saturated with the data transfers. Accordingly, control inputs to arrange for the next set of data transfers can be effectively locked out until the current data transfers complete. During the time that the control inputs are being provided, the external peripheral interface controlled by the peripheral interface controller can be idle. 
     One mechanism for reducing the contention on the peripheral to memory interface is to include a processor in the peripheral interface controller, executing a program to control the peripheral interface controller hardware. However, such a mechanism is expensive in a number of ways: in monetary terms to acquire the processor (either as a discrete component or as intellectual property that can be incorporated into the peripheral interface controller design); in terms of space occupied by the peripheral interface controller when the processor is included; and in terms of power consumed by the processor. Additionally, the program to be executed is stored in the system memory, and thus instruction fetches can compete with the data transfers on the peripheral to memory interface. 
     SUMMARY 
     In an embodiment, an integrated circuit includes a peripheral component configured to control an external interface of the integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. 
     In an embodiment, the commands in the command queue may be downloaded to the command queue at times that data transfers are not occurring on the internal interface. The commands may be available in the command queue to perform the next transfer, for example, when the current transfer completes. The internal and external interfaces may be used efficiently, in some embodiments, even in the face of contention between data transfers and control transfers on the internal interface. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG. 1  is a block diagram of one embodiment of an integrated circuit, a memory, and a flash memory. 
         FIG. 2  is a block diagram of one embodiment of a flash memory interface illustrated in  FIG. 1 . 
         FIG. 3  is a flowchart illustrating operation of one embodiment of a flash memory interface control circuit illustrated in  FIG. 2  in response to receiving a write operation. 
         FIG. 4  is a table illustrating one embodiment of commands supported by the flash memory interface control circuit. 
         FIG. 5  is a flowchart illustrating operation of one embodiment of the flash memory interface control circuit shown in  FIG. 2  in response to reading a command from the command first-in, first-out buffer (FIFO). 
         FIG. 6  is a block diagram of an example use of a macro memory. 
         FIG. 7  is a flowchart illustrating operation of one embodiment of flash memory interface code executed by one embodiment of a processor shown in  FIG. 1 . 
         FIG. 8  is a block diagram of one embodiment of a system including the apparatus illustrated in  FIG. 1 . 
         FIG. 9  is a block diagram of one embodiment of a computer accessible storage medium. 
     
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to. 
     Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits and/or memory storing program instructions executable to implement the operation. The memory can include volatile memory such as static or dynamic random access memory and/or nonvolatile memory such as optical or magnetic disk storage, flash memory, programmable read-only memories, etc. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph six interpretation for that unit/circuit/component. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Turning now to  FIG. 1 , a block diagram of one embodiment of an integrated circuit  10  coupled to an external memory  12  and one or more flash memory devices  28 A- 28 B is shown. In the illustrated embodiment, the integrated circuit  10  includes a memory controller  14 , a system interface unit (SIU)  16 , a set of peripheral components such as components  18 A- 18 B, a flash memory interface unit  30 , a central DMA (CDMA) controller  20 , a processor  22  including a level 1 (L1) cache  24 , a level 2 (L2) cache  26 , and an input/output (I/O) processor (IOP)  32 . The memory controller  14  is coupled to a memory interface to which the memory  12  may be coupled, and is coupled to the SIU  16 . The CDMA controller  20 , the L2 cache  26 , and the processor  22  (through the L2 cache  26 ) are also coupled to the SIU  16  in the illustrated embodiment. The L2 cache  26  is coupled to the processor  22 , and the CDMA is coupled to the components  18 A- 18 B, the flash memory interface unit  30 , and the IOP  32 . One or more peripheral components  18 A- 18 B may be coupled to external interfaces as well, such as the peripheral component  18 A. In other embodiments, other components may be coupled to the SIU  16  directly (e.g. other peripheral components). 
     The CDMA controller  20  may be configured to perform DMA operations between the memory  12 , various peripheral components  18 A- 18 B, and/or the flash memory interface unit  30 . Various embodiments may include any number of peripheral components and/or flash memory interface units  30  coupled through the CDMA controller  20 . The processor  22  (and more particularly, instructions executed by the processor  22 ) may program the CDMA controller  20  to perform DMA operations. Various embodiments may program the CDMA controller  20  in various ways. For example, DMA descriptors may be written to the memory  12 , describing the DMA operations to be performed, and the CDMA controller  20  may include registers that are programmable to locate the DMA descriptors in the memory  12 . Multiple descriptors may be created for a DMA channel, and the DMA operations described in the descriptors may be performed as specified. Alternatively, the CDMA controller  20  may include registers that are programmable to describe the DMA operations to be performed, and programming the CDMA controller  20  may include writing the registers. 
     Generally, a DMA operation may be a transfer of data from a source to a target that is performed by hardware separate from a processor that executes instructions. The hardware may be programmed using instructions executed by the processor, but the transfer itself is performed by the hardware independent of instruction execution in the processor. At least one of the source and target may be a memory. The memory may be the system memory (e.g. the memory  12 ), the flash memory devices  28 A- 28 B, or may be an internal memory in the integrated circuit  10 , in some embodiments. Some DMA operations may have memory as a source and a target (e.g. a DMA operation between the memory  12  and the flash memory devices  28 A- 28 B, or a copy operation from one block of the memory  12  to another). Other DMA operations may have a peripheral component as a source or target. The peripheral component may be coupled to an external interface on which the DMA data is to be transferred or on which the DMA data is to be received. For example, the peripheral component  18 A may be coupled to an interface onto which DMA data is to be transferred or on which the DMA data is to be received. Thus, a DMA operation may include the CDMA controller  20  reading data from the source and writing data to the destination. The data may flow through the CDMA controller  20  as part of the DMA operation. Particularly, DMA data for a DMA read from the memory  12  may flow through the memory controller  14 , over the SIU  16 , through the CDMA controller  20 , to the peripheral component  18 A- 18 B or the flash memory interface unit  30  (and possibly on the interface to which the peripheral component is coupled, if applicable). Data for a DMA write to memory may flow in the opposite direction. 
     In one embodiment, instructions executed by the processor  22  and/or the IOP  32  may also communicate with the peripheral components  18 A- 18 B and the flash memory interface unit  30  using read and/or write operations referred to as programmed input/output (PIO) operations. The PIO operations may have an address that is mapped by the integrated circuit  10  to a peripheral component  18 A- 18 B or the flash memory interface unit  30  (and more particularly, to a register or other readable/writeable resource in the component). The address mapping may be fixed in the address space, or may be programmable. Alternatively, the PIO operation may be transmitted in a fashion that is distinguishable from memory read/write operations (e.g. using a different command encoding than memory read/write operations on the SIU  16 , using a sideband signal or control signal to indicate memory vs. PIO, etc.). The PIO transmission may still include the address, which may identify the peripheral component  18 A- 18 B or the flash memory unit  30  (and the addressed resource) within a PIO address space, for such implementations. 
     In one embodiment, PIO operations may use the same interconnect as the CDMA controller  20 , and may flow through the CDMA controller  20 , for peripheral components  18 A- 18 B and the flash memory interface unit  30 . Thus, a PIO operation may be issued by the processor  22  onto the SIU  16  (through the L2 cache  26 , in this embodiment), to the CDMA controller  20 , and to the targeted peripheral component/flash memory interface unit. Similarly, the IOP  32  may issue PIO operations to the CDMA controller  20 , which may transmit the PIO operation over the same interconnect to the peripheral components  18 A- 18 B or the flash memory interface unit  30 . 
     Accordingly, data transfers for a DMA operation to/from a peripheral component  18 A- 18 B or the flash memory interface unit  30  may conflict with PIO operations to/from the same peripheral component  18 A- 18 B or the flash memory interface unit  30 . For example, the flash memory interface unit  30  may be programmed via PIO operations to perform memory transfers to/from the flash memory devices  28 A- 28 B. For write operations, the CDMA controller  20  may DMA the data to be written to the flash memory interface unit  30 . For read operations, the CDMA controller  20  may DMA the data to be read from the flash memory interface unit  30 . In an embodiment, flash memory devices  28 A- 28 D may support a page of data transfer to/from the devices. The size of the page is device-dependent, and may not be the same as the page size used for virtual-to-physical address translation for the memory  12 . For example, page sizes of 512 bytes, 2048 bytes, and 4096 bytes are often used. Accordingly, a page may be the unit of transfer of data for the memory device, in this context. 
     The flash memory interface unit  30  may be programmed to perform a page of data transfer, and the CDMA unit  20  may perform the DMA operations to transfer the data. If multiple pages are to be transferred, additional PIO operations may be used to program the flash memory interface unit  30  to perform the next transfer. However, the DMA operations may effectively lock out the additional PIO operations until the current page completes. Thus, the time elapsing while programming the flash memory interface unit  30  for the next page may result in idle time on the interface to the flash memory devices. 
     In one embodiment, the flash memory interface unit  30  may support a command queue. Commands to program the flash memory interface unit  30  for a set of pages to be transferred may be queued in the command queue. Once the DMA operations for the first page begin, the data to program the flash memory interface unit  30  for subsequent pages may already be stored in the command queue. Accordingly, there may be no conflict between the PIO operations to program the flash memory interface unit  30  and the DMA operations to transfer the data. The utilization on the interface to the flash memory devices  28 A- 28 B may be increased due to the ability to process the commands from the command queue to configure the flash memory controller  30  for the next page to be transferred while the CDMA unit  30  completes the DMA operations for the current page. 
     In an embodiment, the flash memory interface unit  30  may support a macro memory to store one or more macros. A macro may be a sequence of two or more commands that may be invoked via a macro command. For example, the macro command may be written to the command queue, and may invoke the macro when the macro command is performed by the flash memory interface unit  30 . Macros that implement frequently-used sequences of commands may be downloaded to the macro memory, and thus fewer commands need be downloaded subsequently. That is, macro commands may be written to the command queue instead of repeatedly writing the commands that are stored in the macro. In one embodiment, the macro command may specify a starting address of the macro and a number of words in the macro. Once the number of words have been read from the macro and the corresponding commands have been performed, the next command in the command queue after the macro command may be performed. Accordingly, return commands may be avoided in the macro, permitting more dense macros in an embodiment. Other embodiments may use the starting address and a number of commands as operands. Still other embodiments may implement a return command and the macro command may include the starting address (but not word/command count) as an operand. In an embodiment, the macro command may also include a loop count operand. The loop count operand may specify a number of iterations of the macro that are to be performed. Thus, performing the macro command may include reading the number of words beginning at the starting address and performing the commands, iterated the loop count number of times, before proceeding with the next command in the command queue after the macro command. 
     Commands in the command queue and/or commands in the macro memory may use operands to control their operation. In some cases, the operands may be stored in the command queue. In other cases, the operands may be stored in an operand queue. Commands in the command queue or in the macro memory may specify that the flash memory interface unit  30  load operands from the operand queue and operate on the operands. The operand queue may be used with a macro to supply instance-specific data for the generic macro (e.g. flash memory addresses, chip enables, etc.). Similarly, the operand queue may supply operands for the commands in the command queue. 
     A memory transfer, as used herein, may refer to the transfer of data to/from a memory device (via the interface to the memory device). Thus, a memory transfer to/from the flash memory devices  28 A- 28 B may occur over the interface between the flash memory devices  28 A- 28 B and the flash memory interface unit  30 . Similarly, a memory transfer to/from the memory  12  may occur over the interface between the memory  12  and the memory controller  14 . The memory transfer may occur using a protocol defined by the memory devices. Additionally, a command may refer to one or more bytes of data that are interpreted by the hardware in the peripheral component (e.g. the flash memory interface unit  30 ) as specifying a particular operation to be performed by the hardware. 
     Generally, a peripheral component may be any desired circuitry to be included on the integrated circuit  10  with the processor. A peripheral component may have a defined functionality and interface by which other components of the integrated circuit  10  may communicate with the peripheral component. For example, peripheral components may include video components such as display controllers, graphics processors, etc.; audio components such as digital signal processors, mixers, etc.; networking components such as an Ethernet media access controller (MAC) or a wireless fidelity (WiFi) controller; controllers to communicate on various interfaces such as universal serial bus (USB), peripheral component interconnect (PCI) or its variants such as PCI express (PCIe), serial peripheral interface (SPI), flash memory interface, etc. The flash memory interface unit  30  may be one example of a peripheral component, and the general properties of a peripheral component described herein may be applicable to the flash memory interface unit  30 . 
     The processor  22  may implement any instruction set architecture, and may be configured to execute instructions defined in that instruction set architecture. The processor  22  may employ any microarchitecture, including scalar, superscalar, pipelined, superpipelined, out of order, in order, speculative, non-speculative, etc., or combinations thereof. The processor  22  may include circuitry, and optionally may implement microcoding techniques. In the illustrated embodiment, the processor  22  may include an L1 cache  24  to store data and instructions for use by the processor  22 . There may be separate L1 data and instruction caches. The L1 cache(s) may have any capacity and organization (set associative, direct mapped, etc.). In the illustrated embodiment, an L2 cache  26  is also provided. The L2 cache  26  may have any capacity and organization, similar to the L1 cache(s). 
     Similarly, the IOP  32  may implement any instruction set architecture, and may be configured to execute instructions defined in that instruction set architecture. The instruction set architecture implemented by the IOP  32  need not be the same instruction set architecture implemented by the processor  22 . In one embodiment, the IOP  32  may be a lower power, lower performance processor than the processor  22 . The IOP  32  may handle various I/O interface issues (configuring peripheral components to perform desired operations, certain error handling, etc.). The IOP  32  may execute instructions to write commands to the command queue in the flash memory interface unit  30 , write macros to the macro memory in the flash memory interface unit  30 , and/or write operands to the operand queue in the flash memory interface  30 . The IOP  32  may further execute instructions to service other peripheral components  18 A- 18 B. Thus, the processor  22  may perform other computing tasks, or many be powered down to conserve power if there are no other computing tasks to be performed. The IOP  32  may employ any microarchitecture, including scalar, superscalar, pipelined, superpipelined, out of order, in order, speculative, non-speculative, etc., or combinations thereof. The IOP  32  may include circuitry, and optionally may implement microcoding techniques. 
     The SIU  16  may be an interconnect over which the memory controller  14 , the processor  22  (through the L2 cache  26 ), the L2 cache  26 , and the CDMA controller  20  may communicate. The SIU  16  may implement any type of interconnect (e.g. a bus, a packet interface, point to point links, etc.). The SIU  16  may be a hierarchy of interconnects, in some embodiments. 
     The memory controller  14  may be configured to receive memory requests from the system interface unit  16 . The memory controller  14  may be configured to access the memory  12  to complete the requests (writing received data to the memory  12  for a write request, or providing data from the memory  12  in response to a read request) using the interface defined for the attached memory  12 . The memory controller  14  may be configured to interface with any type of memory  12 , such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. The memory may be arranged as multiple banks of memory, such as dual inline memory modules (DIMM5), single inline memory modules (SIMMs), etc. In one embodiment, one or more memory chips are attached to the integrated circuit  10  in a package on package (POP) or chip-on-chip (COC) configuration. 
     The memory  12  may include one or more memory devices. Generally, a memory device may be any component that is designed to store data according to an address provided with the data in a write operation, and to supply that data when the address is used in a read operation. Any of the examples of memory types mentioned above may be implemented in a memory device, and the flash memory devices  28 A- 28 B may be memory devices as well. A memory device may be a chip, multiple chips connected to a substrate such as a printed circuit board (e.g. a SIMM or DIMM, or directly connected to a circuit board to which the IC  10  is coupled), etc. 
     The flash memory interface unit  30  may include circuitry configured to receive read and write requests for the flash memory devices  28 A- 28 B, and configured to interface to the flash memory devices  28 A- 28 B to complete the read/write requests. In one embodiment, the read/write requests may be sourced from the CDMA controller  20 . The flash memory interface unit  30  may be programmable via one or more control registers (see  FIG. 2  described below) to perform memory transfers to/from the flash memory devices  28 A- 28 B (e.g. via PIO operations). Flash memory devices  28 A- 28 B may be flash memory, a type of non-volatile memory that is known in the art. In other embodiments, other forms of non-volatile memory may be used. For example, battery-backed SRAM, various types of programmable ROMs such as electrically-erasable programmable ROMs (EEPROMs), etc. may be used. In still other embodiments, volatile memory may be used similar to memory  12 . 
     While the present embodiment describes using the command queue (FIFO), macro memory, and/or operand queue (FIFO) in the flash memory interface unit  30 , other embodiments may implement the features in any peripheral component, with any type of memory or peripheral interface. 
     It is noted that other embodiments may include other combinations of components, including subsets or supersets of the components shown in  FIG. 1  and/or other components. While one instance of a given component may be shown in  FIG. 1 , other embodiments may include one or more instances of the given component. 
     Turning now to  FIG. 2 , a block diagram of one embodiment of the flash memory interface unit  30  is shown. In the illustrated embodiment, the flash memory interface unit  30  includes a command FIFO  40 , a flash memory interface (FMI) control circuit  42 , a macro memory  44 , an operand FIFO  46 , a flash memory controller (FMC)  48 , a set of FMC control registers  50 , data buffers  52 A- 52 B, and an error checking/correction (ECC) unit  54 . The command FIFO  40 , FMI control circuit  42 , macro memory  44 , operand FIFO  46 , and buffers  52 A- 52 B are all coupled to an internal interface to the CDMA controller  20 . The FMI control circuit  42  is further coupled to the command FIFO  40 , the macro memory  44 , the operand FIFO  46 , and the FMC control registers  50 . The FMC control registers  50  are further coupled to the FMC  48 , which is coupled to an external interface to the flash memory devices. The FMC  48  is further coupled to the buffers  52 A- 52 B. The ECC unit  54  is also coupled to the buffers  52 A- 52 B. 
     The FMI control circuit  42  may be configured to receive PIO operations from the CDMA controller  20 . Some PIO operations may be directed to the command FIFO  40 , the macro memory  44 , or the operand FIFO  46 . For example, PIO writes may be used to write commands into the command FIFO  40 , to download macros into the macro memory  44 , or to write operands into the operand FIFO  46 . Addresses may be assigned to each of the FIFO  40 , the macro memory  44 , and the operand FIFO  46 , which may be used in the PIO operands to address the desired resource. For example, the FIFOs  40  and  46  may have a single assigned address since they may operate in a first-in, first-out manner. A PIO write to the address may cause the FMI control circuit  42  to store the data provided with the write in the next open entry in the FIFO  40  or  46 . That is, the data may be appended to the tail of the FIFO  40  or  46 , where commands or operands are removed from the head of the FIFO  40  or  46 . The macro memory  44  may have a range of addresses assigned to it, e.g. an address per word of the macro memory  44 . PIO writes to the addresses may store the provided data word into the addressed word of the macro memory  44 . 
     The FMI control circuit  42  may process the commands in the command FIFO  40  to program various FMC control registers  50  to cause the FMC  48  to perform a particular memory transfer to/from the flash memory devices  28 A- 28 B. In one embodiment, the FMC  48  is configured to receive relatively low-level control via the FMC control registers  50 , including address, chip enables, transfer commands, etc. Commands in the command FIFO  40  may be interpreted by the FMI control circuit  42  and the corresponding FMC control registers  50  may be written by the FMI control circuit  42 . Similarly, commands to wait for an event may be interpreted by the FMI control circuit  42  to read one or more FMC control registers  50  to detect the event. There may also be direct control signals between the FMI control circuit  42  to the FMC  48 , in some embodiments (not shown in  FIG. 2 ) which may be driven by the FMI control circuit  42  responsive to commands and/or monitored by the FMI control circuit  42  responsive to commands. 
     The FMI control circuit  42  may be configured to read the commands from the command FIFO  40  in the order written. More generally, a command queue may be supported (e.g. the command FIFO  40  may not be specifically constructed as a FIFO, such that each entry in the queue may be concurrently visible to the FMI control circuit  42 ). Similarly, the operand FIFO  46  may be an operand queue, and the FMI control circuit  42  may read operands from the operand FIFO  46  responsive to the commands in the command queue or the macro memory  44  in the order the operands were written. 
     As mentioned previously, a macro command may be in the command FIFO  40 , and the FMI control circuit  42  may perform commands from the macro memory  44  in response to the macro command. In other embodiments, the macro command may be transmitted as a PIO operation to the FMI control circuit  42 . In still other embodiments, macro commands may be encountered in the command FIFO  40  or in PIO operations. The macro command may include a starting address in the macro memory and a word count indicating the number of words to read from the macro memory  44 . The FMI control circuit  42  may perform the commands in the macro prior to reading the next command in the command FIFO  40 . The words in the macro may include operands in addition to commands, in one embodiment. Other embodiments may use a command count rather than a word count. As mentioned above, the macro command may also include a loop count and the macro may be iterated the number of times indicated by the loop count. 
     Reading words from the command FIFO  40  and the operand FIFO  46  may include the FMI control circuit  42  deleting those words from the FIFO. Reading words from the macro memory  44 , on the other hand, may not involve deleting the words so that macros may be repeatedly performed. 
     The FMC  48  may perform memory transfers in response to the contents of the FMC control registers  50 , writing data read from the flash memory devices  28 A- 28 B to the buffers  52 A- 52 B or writing data read from the buffers  52 A- 52 B to the flash memory devices  28 A- 28 B. The buffers  52 A- 52 B may be used in a ping-pong fashion, in which one of the buffers  52 A- 52 B is being filled with data while the other is being drained. For example, reads from the flash memory devices  28 A- 28 B may include the FMC  48  filling one of the buffers  52 A- 52 B while the other buffer  52 A- 52 B is being drained by the CDMA controller  20  performing DMA operations to memory  12 . Writes to the flash memory devices  28 A- 28 B may include the CDMA controller  20  filling one of the buffers  52 A- 52 B with data while the FMC  48  drains the other buffer  52 A- 52 B. The ECC unit  54  may generate ECC data for writes to the flash memory devices  28 A- 28 B, and may check the ECC data for reads from the flash memory devices  28 A- 28 B. 
     Turning now to  FIG. 3 , a flowchart is shown illustrating operation of one embodiment of the FMI control circuit  42  in response to receiving a PIO operation from the CDMA controller  20 . While the blocks are shown in a particular order for ease of understanding, other orders may be used. Blocks may be performed in parallel in combinatorial logic in the FMI control circuit  42 . For example, the decision blocks illustrated in  FIG. 3  may be independent and may be performed in parallel. Blocks, combinations of blocks, and/or the flowchart as a whole may be pipelined over multiple clock cycles. The FMI control circuit  42  may be configured to implement the operation illustrated in  FIG. 3 . 
     If the PIO write is addressed to the command FIFO  40  (decision block  60 , “yes” leg), the FMI control circuit  42  may be configured to update the next entry in the command FIFO  40  with the data from the PIO write (block  62 ). That is, the data from the PIO write may be appended to the tail of the command FIFO  40 . If the PIO write is addressed to the macro memory  44  (decision block  64 , “yes” leg), the FMI control circuit  42  may be configured to update the addressed entry in the macro memory  44  with the data from the PIO write (block  66 ). If the PIO write is addressed to the operand FIFO  46  (decision block  68 , “yes” leg), the FMI control circuit  42  may be configured to update the next entry in the operand FIFO  46  with the data from the PIO write (block  70 ). That is, the data from the PIO write may be appended to the tail of the operand FIFO  46 . If the PIO write is addressed to a register within the FMC control registers  50  (or other registers in the flash memory interface unit  30 , in various embodiments—decision block  72 , “yes” leg), the FMI control circuit  42  may be configured to update the addresses register (block  74 ). 
     Turning next to  FIG. 4 , a table  76  is shown illustrating an exemplary command set that may be supported by one embodiment of the flash memory interface unit  30 , and more particularly the FMI control circuit  42 . Other embodiments may support any other set of commands, including subsets of the commands shown in  FIG. 4 , subsets of the commands and other commands, and/or a superset of the commands and other commands. The table includes a “command” column listing each command, an “operands” column indicating the operands for a given command, and a “words” column indicating the number of words in the command FIFO  40  that are occupied by the command. 
     The format of the commands may vary from embodiment to embodiment. For example, in one embodiment, each command may include an opcode byte that identifies the command within the command set (that is, each entry in the table  76  may be identified via a different opcode encoding). Remaining bytes in the word or words forming the command may be used to specify operands for the command. The commands may be stored in the command FIFO  40  or the macro memory  44 , in various embodiments. 
     The address commands (addr0 to addr7 in table  76 ) may be used to issue address bytes on the interface to the flash memory devices  28 A- 28 B (more succinctly referred to as the flash memory interface). The digit after “addr” indicates the number of address bytes transmitted, starting with byte 0 of the address on the flash memory interface. The FMI control circuit  42  may be configured to pause until the address bytes have been transmitted before performing the next command, in one embodiment. The addrX commands may be equivalent to programming the following FMC control registers  50 , in one embodiment: one or more address registers with the address bytes, and programming a transfer number and read/write mode in one or more registers. Responsive to the read/write mode, the FMC  48  may transmit the address bytes on the flash memory interface and may signal an address done interrupt in a status register within the FMC control registers  50 . Additionally, the addrX commands may further include waiting for and clearing and address done interrupt in the status register. The addr0 command may differ from the addrl through addr7 commands in that the address registers and address transfer number register are not programmed. Instead these registers may be preprogrammed using other commands such as the load_next_word or load_from_fifo commands described below. 
     The cmd command may be used to send a flash memory interface command out on the flash memory interface. In one embodiment, flash memory interface commands are one byte. Accordingly, the operand of the cmd command may be the command byte may be transmitted on the flash memory interface. The FMI control circuit  42  may be configured to pause until the cmd command is completed on the flash memory interface. The cmd command may be equivalent to programming a command register in the FMC control registers  50  with the command byte; setting a command mode bit in another FMC control register  50 ; and waiting for and clearing a cmd done interrupt in a status register within the FMC control registers  50 . Responsive to the setting of the command mode bit, the FMC  48  may be configured to transmit the command byte on the flash memory interface and may write the cmd done interrupt to the status register. 
     The enable_chip command may be used to write a chip enable register of the FMC control registers  50 , which may cause the FMC  48  to drive chip enable signals on the flash memory interface based on the chip enable operand. 
     The xfer_page command may be used to initiate a page transfer to/from the flash memory devices  28 A- 28 B. In response to the xfer_page command, the FMI control circuit  42  may be configured to set a start bit in an FMC control register  50  and wait for and clear a page done interrupt bit in another FMC control register  50 . In response to the start bit, the FMC  48  may be configured to perform the specified page transfer, and set the page done interrupt upon completion. 
     There may be various synchronizing command supported by the FMI control circuit  42 . Generally, a synchronizing command may be used to specify an event that the FMI control circuit  42  is to monitor for, and may cause the FMI control circuit  42  to wait for the event to occur (i.e. wait until the FMI control circuit  42  detects the event) prior to performing the next command. Thus, synchronizing commands may permit sequences of commands to be preprogrammed, and the synchronizing commands may help ensure the correct timing. For example, multiple page transfers may be preprogrammed, and synchronizing commands may be used to delay programming of the FMC control registers  50  for the next page until the registers are no longer needed for the current page (e.g. after the last data from the page is loaded into the buffer  52 A- 52 B for a read). 
     In the embodiment of  FIG. 4 , the synchronizing commands may include wait_for_rdy, pause, timed_wait, and wait_for_int. The wait_for_rdy command may be used to monitor the status of the flash memory devices  28 A- 28 B during a page transfer. The wait_for_rdy command may include waiting for and clearing a specific “done” interrupt (e.g. page done) in the status register of the FMC control registers  50 ; masking a status byte in the status register with the mask operand, and comparing the masked status byte to the condition operand. If the masked status byte matches the condition operand, the FMI control circuit  42  may be configured to perform the next command. Otherwise, the FMI control circuit  42  may signal an interrupt (e.g. to the IOP  32  or the processor  22 , in various embodiments) and may stop performing additional commands until the IOP  32 /processor  22  services the interrupt. 
     The pause command may be used to pause command performance by the FMI control circuit  42 . The FMI control circuit  42  may cease performing commands until specifically unpaused by software executing on the IOP  32 /processor  22  writing a specified enable bit in one of the FMC control registers  50 . 
     The FMI control circuit  42  may be configured to pause and resume after a number of clock cycles via the timed_wait command. The number of clock cycles is specified as the operand of the timed_wait command. In some embodiments, the timed_wait command may be used to slow down the flash memory interface unit  30 , because the performance possible using the command FIFO  40 , the macro memory  44 , and the operand FIFO  46  may exceed the rate at which activities may be performed by the flash memory devices  28 A- 28 B. 
     The wait_for_int command may be used to cause the FMI control circuit  42  to wait for a specified interrupt value. The operands may specify the interrupt (irq) to be waited on, and the state of the irq bit to be waited on (e.g. set or clear), using the “bit” operand. 
     The send_interrupt command may be used to send a specified interrupt to the IOP  32  or processor  22 . The operand of the send_interrupt command may specify an interrupt code to write into an interrupt code register of the FMC control registers  50 , which may cause the interrupt to be sent. 
     The load_next_word and load_from_fifo commands may be used to program various registers in the FMC control registers  50 . One of the operands of these commands is the register address of the control register to be written. In response to the load_next_word command, the FMI control circuit  42  may read the next word from the command FIFO  40  and write the word to the addressed register. In response to the load_from_fifo command, the FMI control circuit  42  may be configured to read the word at the head of the operand FIFO  46  and write the word to the addressed register. 
     The macro command may be used to cause the FMI control circuit  42  to read commands from the macro memory  44 . The macro command includes an address operand, a length operand, and a loop count operand. The address may identify the first word to be read from the macro memory  44 , and the length may identify the length of the macro (e.g. in terms of number of commands or number of words). In one embodiment, the length is the number words. The loop count may indicate a number of iterations of the macro to be performed. In one embodiment, the loop count operand may be one less than the number of iterations (e.g. a loop count of zero is one iteration, a loop count of one is two iterations, etc.). Once a macro completes the next command FIFO  42  may be read (i.e. there may be no return command in the macro). 
     The poll command may be to poll any register in the FMC control registers  50  for a specified value (after masking the value read from the register using the mask field). The FMI control circuit  42  may poll the register until the specified value is detected, then proceed to the next command. 
     As noted in the above description, the FMI control circuit  42  may monitor for various interrupts recorded in one or more status registers within the FMC control registers  50  as part of performing certain commands. The FMI control circuit  42  may clear the interrupt and complete the corresponding command. In the absence of commands in the command FIFO  40 , the interrupts may instead be forwarded to the IOP  32 /processor  22  (if enabled). Accordingly, PIO write operations to the FMC control registers  50  and interrupts to the IOP  32 /processor  22  may be another mechanism to perform memory transfers to/from the flash memory devices  28 A- 28 B. 
     Turning now to  FIG. 5 , a flowchart is shown illustrating operation of one embodiment of the FMI control circuit  42  to process a command. While the blocks are shown in a particular order for ease of understanding, other orders may be used. Blocks may be performed in parallel in combinatorial logic in the FMI control circuit  42 . Blocks, combinations of blocks, and/or the flowchart as a whole may be pipelined over multiple clock cycles. The FMI control circuit  42  may be configured to implement the operation illustrated in  FIG. 5 . 
     The FMI control circuit  42  may be configured to read a command from the command FIFO  40  (block  80 ). If the command is not a macro command (decision block  82 , “no” leg), the FMI control circuit  42  may be configured to perform the command (block  84 ). Once the command completes, the FMI control circuit  42  may be configured to check a word count used to determine if a macro has reached its end. If the command is not part of a macro, the word count may be zero (decision block  86 , “no” leg). The FMI control circuit may be configured to check the loop count associated with the macro command. If the command is not part of a macro, the loop count may be zero (decision block  95 , “no” leg). The FMI control circuit  42  may be configured to determine if there is another valid command in the command FIFO  40  (decision block  88 ). That is, the FMI control circuit  42  may be configured to determine if the command FIFO  40  is empty. If there is another valid command (decision block  88 , “yes” leg), the FMI control circuit  42  may be configured to read and process the next command. Otherwise, the FMI control circuit  42 ′s command processing circuitry may be idle until another valid command is written to the command FIFO  40  (decision block  88 , “no” leg). 
     If the command is a macro command (decision block  82 , “yes” leg), the FMI control circuit  42  may be configured to initialize the word count to the length operand of the macro command and to initialize the loop count to the loop count operand of the macro command (block  90 ). The FMI control circuit  42  may also read a command from the macro memory  44  (block  92 ). Specifically, in this case, the FMI control circuit  42  may read the first word from the address in the macro memory  44  provided as the address operand of the macro command. The FMI control circuit  42  may be configured to perform the command (block  84 ), and may be configured to check the word count. The word count may be greater than zero (decision block  86 , “yes” leg), and the FMI control circuit  42  may be configured to decrement the word count and to read the next command from the macro memory  44  (e.g. by incrementing the address) (blocks  94  and  96 ). The FMI control circuit  42  may be configured to process the next command (returning to decision block  82  in the flowchart of  FIG. 5 ). If the word count is zero (decision block  86 , “no” leg), the FMI control circuit  42  may be configured to check the loop count. If the loop count is greater than zero (decision block  95 , “yes” leg), another iteration of the macro is to be performed. The FMI control circuit  42  may decrement the loop count (block  97 ), reinitialize the word count and the macro address (block  99 ), and read the next command from the macro memory  44  (i.e. the first command of the macro) (block  96 ). If both the word count and loop count are zero (decision block  86  and  88 , “no” legs), the macro is complete and the FMI control circuit  42  may check for the next valid command in the command queue  40  (decision block  88 ). 
     It is noted that, since each command is checked for being a macro command, macro commands may be stored in the macro memory  44  as well. Accordingly, macros may be “nested”, although the last macro to be performed returns to the command FIFO  40  so there isn&#39;t true nesting in the sense that macros do not return to macros that called them. 
     Turning now to  FIG. 6 , a block diagram of an example of a use of macros to perform a multiple page write to a flash memory device  28 A or  28 B is shown. A contents of the macro memory  44  is shown, including three sections of commands. Between macro memory address 0 and N−1, N words of macro  100  to complete a write to the previous page are stored. Between macro memory address N and N+M−1, M words of macro  102  to start a write to a next page are stored. Between macro memory address N+M and N+M+P−1, P words of macro  104  are stored to finish a last page of a write to memory. 
     A set of commands in the command FIFO  40  are illustrated in  FIG. 6 , with a head of the FIFO at the top of the command FIFO  42  and the subsequent commands in the FIFO proceeding in order down the command FIFO  40  as illustrated in  FIG. 6 . The first command is macro N, M. The command calls the macro  104 , beginning at word N, and performs M words (i.e. the macro  102  as illustrated in  FIG. 6 ). Thus, the write to the first page is initialized. Subsequent page writes may be performed using the macro 0, N+M commands. These commands cause the macro  100  and the macro  102  to be performed. The write to the previous page may be completed (macro  100 ) and the write to the next page may be started (macro  102 ). The last page may be written using the macro 0, N+M+P command. This command causes the macros  100 ,  102 , and  104  to be performed, completing the write to the second to last page (macro  100 ), performing the write to the last page (macro  102 ), and completing the write to the last page and closing the flash memory device  28 A or  28 B (macro  104 ). In this example, the loop count operand of each macro command is zero (one iteration). However, in another example, shown below the first example in  FIG. 6 , the loop count operand may be used to make the commands in the command queue even more efficient. The loop count of the macro N, M command for the first page and the macro 0, N+M+P command for the last page may still be zero, specifying one iteration. However, the middle pages of the write may all be accomplished using one macro command (macro 0, N+M) with a loop count operand equal to the page count (C) minus 3. The loop count is C−3 to account for the first and last page, as well as the fact that the loop count operand is one less than the desired number of iterations in this embodiment. As the macros  100 ,  102 , and  104  illustrate, through careful arrangement of the macros in the macro memory  44 , dense and efficient macros may result. The macros may employ load_from_fifo commands to use different operands for each page write operand, and the operands for each page may be loaded into the operand FIFO  46  prior to initiating the commands in the command FIFO  40 . 
     The commands included in the macro  102  may establish the address to be written, chip enables, etc. The commands included in the macro  100  may include xfer_page to transfer the previous page to the memory, and commands to check for errors and synchronize the next page transfer (which may be initialized via the macro  102 ). The macro  104  may include the final xfer_page command, as well as commands to check for errors and to close the flash memory device that was the target of the writes, deactivating the active page/region and/or performing any other operations as specified for the flash memory device. 
     Turning now to  FIG. 7 , a flowchart illustrating operation of a flash code to be executed by the IOP  32  and/or the processor  22  is shown. While the blocks are shown in a particular order for ease of understanding, other orders may be used. The flash code may include instructions which, when executed by the IOP  32  and/or the processor  22 , may implement the operation illustrated in  FIG. 7 . 
     The flash code may be executed at any time during operation of the integrated circuit  10 . For example, the flash code may be executed to initialize the flash memory interface unit  30 . The flash code may also be executed at any time that the flash memory  30  has been idle but is to be accessed, to reconfigure the macros in the macro memory  44 , etc. 
     The flash code may download any desired macros to the macro memory  44  (block  110 ). If the macros already stored in the macro memory  44  are the desired macros, or if there are no desired macros, block  110  may be skipped. The flash code may also download any operands to be used by the commands or the macros (block  112 ), and block  112  may be skipped if there are no operands to be downloaded. The flash code may download the commands to be performed (block  114 ), and command performance may begin in the flash memory interface unit  30 . If additional commands are ready to be downloaded (decision block  116 , “yes” leg), the flash code may download the additional commands (block  114 ). If new operands or macros are ready to be downloaded (decision block  118 , “yes” leg), the flash code may return to blocks  110  and/or  112  to download them. 
     System and Computer Accessible Storage Medium 
     Turning next to  FIG. 8 , a block diagram of one embodiment of a system  150  is shown. In the illustrated embodiment, the system  150  includes at least one instance of an integrated circuit  10  (from  FIG. 1 ) coupled to one or more peripherals  154  and an external memory  158 . The external memory  158  may include the memory  12 . A power supply  156  is also provided which supplies the supply voltages to the integrated circuit  10  as well as one or more supply voltages to the memory  158  and/or the peripherals  154 . In some embodiments, more than one instance of the integrated circuit  10  may be included (and more than one external memory  158  may be included as well). 
     The peripherals  154  may include any desired circuitry, depending on the type of system  150 . For example, in one embodiment, the system  150  may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals  154  may include devices for various types of wireless communication, such as wifi, Bluetooth, cellular, global positioning system, etc. The peripherals  154  may also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals  154  may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system  150  may be any type of computing system (e.g. desktop personal computer, laptop, workstation, net top etc.). 
     The external memory  158  may include any type of memory. For example, the external memory  158  may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM, etc. The external memory  158  may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMM5), etc. 
     Turning now to  FIG. 9 , a block diagram of a computer accessible storage medium  200  is shown. Generally speaking, a computer accessible storage medium may include any storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium may include storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media may further include volatile or non-volatile memory media such as RAM (e.g. synchronous dynamic RAM (SDRAM), Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, Flash memory, non-volatile memory (e.g. Flash memory) accessible via a peripheral interface such as the Universal Serial Bus (USB) interface, a flash memory interface (FMI), a serial peripheral interface (SPI), etc. Storage media may include microelectromechanical systems (MEMS), as well as storage media accessible via a communication medium such as a network and/or a wireless link. The computer accessible storage medium  200  in  FIG. 5  may store flash code  202 , which may include code by the IOP  32  and/or the processor  22 . The flash code  202  may include instructions which, when executed, implement the operation described above with regard to  FIG. 7 . Generally, the computer accessible storage medium  200  may store any set of instructions which, when executed, implement a portion or all of the operation shown in  FIG. 7 . Furthermore, the computer accessible storage medium  200  may store one or more macros  204  to be downloaded to the macro memory  44 , one or more operands to be downloaded to the operand FIFO  36 , and/or one or more commands to be downloaded to the command FIFO  40 . A carrier medium may include computer accessible storage media as well as transmission media such as wired or wireless transmission. 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Metadata:
Filing Date: 20120127
Publication Date: 20121211
Grant Date: 20121211
Priority Date: 20091110
Inventors: LEE DOUGLAS C.
ROSS DIARMUID P.
TOELKES TAHOMA M.
Assignee: APPLE INC
CPC Classifications: [{"code": "G06F13/1642", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F13/126", "inventive": true, "first": false, "tree": "[]"}, {"code": "Y02D10/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F13/126", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F13/1642", "inventive": true, "first": true, "tree": "[]"}, {"code": "Y02D10/00", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 43530829