PATENT DOCUMENT

Publication Number: US-10217402-B1
Application Number: US-201615247634-A
Country: US
Kind Code: B1

Title: Driving circuitry for micro light emitting diode electronic displays

Abstract:
Methods and devices useful in compensating for V DD  and V TH  variations in a micro light-emitting diode (micro-LED) display are provided. By way of example, an LED driver includes a first transistor having a first source coupled to an upper voltage rail (V DD ), a first gate, and a first drain. The LED driver includes a second transistor having a second source coupled to the first drain of the first transistor, a second gate, and a second drain coupled to the LED. The second transistor is configured to receive the drive current signal from the first transistor and supply the drive current signal to the LED. The LED driver includes compensation circuitry configured to adjust the drive current signal such that the drive current signal is independent of the upper voltage rail (V DD ) and a threshold voltage (V TH ) of the first transistor or the second transistor.

Claims:
What is claimed is: 
     
       1. A micro light-emitting diode (micro-LED) display panel, comprising:
 an LED driver configured to supply and regulate power to an LED, comprising:
 a first transistor having a first source coupled to an upper voltage rail, a first gate, and a first drain, wherein the first transistor is configured to pass a drive current signal from the upper voltage rail; 
 a second transistor having a second source coupled to the first drain of the first transistor, a second gate, and a second drain coupled to the LED, wherein the second transistor is configured to receive the drive current signal from the first transistor and supply the drive current signal to the LED; and 
 compensation circuitry configured to adjust the drive current signal such that the drive current signal is independent of the upper voltage rail and a threshold voltage of the first transistor or the second transistor, wherein the compensation circuitry comprises a third transistor coupled between the first drain of the first transistor and an additional upper voltage rail that is independent of the upper voltage rail. 
 
 
     
     
       2. The micro-LED display panel of  claim 1 , wherein the first transistor comprises a p-type metal-oxide-semiconductor. 
     
     
       3. The micro-LED display panel of  claim 1 , wherein the second transistor comprises a p-type metal-oxide-semiconductor. 
     
     
       4. The micro-LED display panel of  claim 1 , wherein the compensation circuitry comprises a capacitance configure to store a compensation voltage based on a second upper voltage rail and a sampling of the threshold voltage. 
     
     
       5. The micro-LED display panel of  claim 1 , wherein the compensation circuitry is configured to adjust the drive current signal over a plurality of phase periods. 
     
     
       6. The micro-LED display panel of  claim 1 , wherein the compensation circuitry is configured to adjust the drive current signal for each LED of a same color of a plurality of LEDs of the micro-LED display panel. 
     
     
       7. The micro-LED display panel of  claim 1 , wherein the compensation circuitry is configured to provide the adjusted drive current signal for each of various color LEDs of the micro-LED display panel. 
     
     
       8. The micro-LED display panel of  claim 1 , wherein the compensation circuitry is configured to adjust the drive current signal to render the drive current signal immune to variations in the upper voltage rail and the threshold voltage based on current-resistance drop. 
     
     
       9. The micro-LED display panel of  claim 1 , comprising a plurality of LED drivers each configured to supply and regulate power to one or more respective LEDs. 
     
     
       10. An electronic device, comprising:
 a device driver configured to:
 generate a drive current to supply to light-emitting diode (LED) pixels of a micro light-emitting diode (micro-LED) display, wherein the device driver comprises a plurality of p-type metal-oxide-semiconductor (PMOS) transistors; and 
 adjust the drive current such that the drive current is independent of an upper voltage rail voltage and a threshold voltage of the plurality of PMOS transistors; and 
 
 a compensation transistor configured to receive a compensation voltage from a compensation upper voltage rail and to inject the compensation voltage between two PMOS transistors of the plurality of PMOS transistors, wherein the compensation upper voltage rail is independent of the upper voltage rail. 
 
     
     
       11. The electronic device of  claim 10 , wherein the device driver is configured to adjust the drive current to render the drive current immune to signal variations of the upper voltage rail. 
     
     
       12. The electronic device of  claim 10 , wherein the device driver is configured to adjust the drive current to render the drive current immune to signal variations of the threshold voltage. 
     
     
       13. The electronic device of  claim 10 , wherein the device driver is configured to adjust the drive current to eliminate a possible occurrence of image artifacts becoming apparent on the micro-LED display. 
     
     
       14. A method, comprising:
 generating, using driving circuitry, a drive current to supply to a light-emitting diode (LED) of a micro light-emitting diode (micro-LED) display, wherein the drive current is expressed by:
     I   LED   =K ( V   Ref   +V   DD     -CL   ) 2 , 
 
 
       wherein I LED  is the drive current, K is a function coefficient, V Ref  is a reference current voltage of micro-drivers of the micro-LED display, and V DD   _   CL  is a voltage of a compensation voltage potential rail that is independent of a voltage potential rail of the micro-LED display; and
 driving a micro-LED of the micro-LED display using the drive current. 
 
     
     
       15. The method of  claim 14 , wherein generating the drive current comprises generating the drive current over at least three phase periods. 
     
     
       16. The method of  claim 15 , wherein generating the drive current comprises generating the drive current based on a voltage at a gate of a transistor coupled to the LED during a second phase period of the at least three phase periods, wherein the voltage is expressed as:
     VB=V   DD   −V   Ref   +V   DD     CL     −V   TH , 
 wherein VB is the voltage at the gate, V DD  is the voltage potential rail of the micro-LED display, and V TH  is a threshold voltage of the transistor or another transistor in the micro-LED display. 
 
     
     
       17. The method of  claim 14 , wherein generating the drive current comprises generating a second drive current prior to generating the drive current is expressed as:
     I   LED   =K ( V   DD −( V   DD   −V   Ref   +V   DD   _   CL   −V   TH )− V   TH ) 2 ,
 
 wherein V DD  is the voltage potential rail of the micro-LED display, and V TH  is a threshold voltage of the transistor, and wherein generating the drive current comprises eliminating a dependence of the drive current on an upper voltage rail and the threshold voltage. 
 
     
     
       18. The method of  claim 14 , wherein generating the drive current comprises generating a second drive current expressed as: I M1 =I 0 , wherein the I M1  comprises a current across an n-type metal-oxide-semiconductor transistor of the micro-LED display and I 0  comprises a reference current, and wherein generating the second drive current comprises eliminating a dependence of the second drive current on a lower voltage rail and a threshold voltage.

Description:
BACKGROUND 
     The present disclosure relates generally to electronic displays and, more particularly, to electronic displays with reduced or eliminated mura artifacts. 
     This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. 
     Electronic displays may be found in a variety of devices, such as computer monitors, televisions, instrument panels, mobile phones, and clocks. One type of electronic display is known as a micro light-emitting diode (uLED) display, which includes pixels of LEDs for displaying image data. The uLED display may include micro drivers that may utilize p-type metal-oxide-semiconductor (PMOS) drivers used to drive the LED devices. For example, PMOS drivers may be used as part of the micro drivers in order to conserve physical area of the uLED display by avoiding level shifters that may be otherwise involved. However, utilizing PMOS drivers as part of the micro drivers may lead to image artifacts (e.g., flicker) becoming present on the uLED display. 
     SUMMARY 
     A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below. 
     Various embodiments of the present disclosure relate to methods and devices useful in compensating for V DD  and V TH  variations in a micro light-emitting diode (micro-LED) display. By way of example, an LED driver includes a first transistor having a first source coupled to an upper voltage rail (V DD ), a first gate, and a first drain. The LED driver includes a second transistor having a second source coupled to the first drain of the first transistor, a second gate, and a second drain coupled to the LED. The second transistor is configured to receive the drive current signal from the first transistor and supply the drive current signal to the LED. The LED driver includes compensation circuitry configured to adjust the drive current signal such that the drive current signal is independent of the upper voltage rail (V DD ) and a threshold voltage (V TH ) of the first transistor or the second transistor. 
     Various refinements of the features noted above may exist in relation to various aspects of the present disclosure. Further features may also be incorporated in these various aspects as well. These refinements and additional features may exist individually or in any combination. For example, various features discussed below in relation to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present disclosure alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which: 
         FIG. 1  is a block diagram of components of an electronic device that may include a micro light emitting diode (μ-LED) display, in accordance with an embodiment; 
         FIG. 2  is a perspective view of the electronic device in the form of a fitness band, in accordance with an embodiment; 
         FIG. 3  is a front view of the electronic device in the form of a slate, in accordance with an embodiment; 
         FIG. 4  is a perspective view of the electronic device in the form of a notebook computer, in accordance with an embodiment; 
         FIG. 5  is a block diagram of a μ-LED display that employs micro-drivers (μDs) to drive μ-LED sub-pixels with control signals from row drivers (RDs) and data signals from column drivers (CDs), in accordance with an embodiment; 
         FIG. 6  is a block diagram schematically illustrating an operation of one of the micro-drivers (μDs), in accordance with an embodiment; 
         FIG. 7  is a timing diagram illustrating an example operation of the micro-driver (μD) of  FIG. 6 , in accordance with an embodiment; 
         FIG. 8  illustrates plots and of the drive current variation due to IR drop supplied to the subpixels, in accordance with an embodiment; 
         FIG. 9  is an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs including VDD and VTH compensation circuitry, in accordance with an embodiment; 
         FIG. 10  is a timing diagram, which depicts VDD and VTH compensation phases (e.g., “PH 1 ,” “PH 2 ,” and “PH 3 ”), in accordance with an embodiment; 
         FIG. 11 , is another embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs including VDD and VTH compensation circuitry, in accordance with an embodiment; 
         FIG. 12  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs including V DD  and V TH  compensation circuitry included as part of the backplane of the display, in accordance with an embodiment; 
         FIG. 13  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs including V DD  and V TH  compensation circuitry included as part of the micro drivers, in accordance with an embodiment; 
         FIG. 14  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs including noise reduction circuitry, in accordance with an embodiment; 
         FIG. 15 , is another embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs including V DD  and V TH  compensation circuitry, in accordance with an embodiment; 
         FIG. 16  illustrates a plot diagram for a compensation capacitor illustrating the reset phases, in accordance with an embodiment; 
         FIG. 17  is a timing diagram, which depicts V DD  and V TH  compensation phases (e.g., “PH 1 ,” “PH 2 ,” and “PH 3 ”), in accordance with an embodiment; 
         FIG. 18  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) including dedicated compensation circuitry for each subpixel; and 
         FIG. 19  is a timing diagram, which depicts V SS  and V TH  compensation phases, in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. 
     When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. 
     Embodiments of the present disclosure relate to upper voltage rail V DD  and threshold voltage V TH  compensation circuitry that may be used to compensate for the V DD  and V TH  variations that may be due to, for example, IR drop (e.g., voltage drops across the resistance R of the power supply between supply pins and one or more components drawing a current I) associated the high voltage potential rail (e.g., “V DD ”) in micro light-emitting diode (uLED) displays. In certain embodiments, the micro drivers including p-type metal-oxide-semiconductor (PMOS) devices may be set to operate over one or more phases of the drive currents (e.g., “I LED ”) of the LED devices to compensate for the V DD  and V TH  variations, and may generate a drive current for the LED devices independent of V DD  and V TH . In another embodiment, the micro drivers including n-type metal-oxide-semiconductor (NMOS) devices may be set to operate over one or more phases of the drive currents (e.g., “I LED ”) to compensate for the lower voltage rail V SS  and threshold voltage V TH  variations, and may generate a drive current for the LED devices independent of V SS  and V TH  In this way, any possible occurrence of image artifacts becoming apparent on the uLED display due to V DD , V SS , and V TH  signal variations may be reduced or substantially eliminated. 
     A general description of suitable electronic devices that may include a micro-LED (μ-LED) display and corresponding circuitry of this disclosure are provided. One example of a suitable electronic device  10  may include, among other things, processor(s) such as a central processing unit (CPU) and/or graphics processing unit (GPU)  12 , storage device(s)  14 , communication interface(s)  16 , a μ-LED display  18 , input structures  20 , and an energy supply  22 . The blocks shown in  FIG. 1  may each represent hardware, software, or a combination of both hardware and software. The electronic device  10  may include more or fewer components. It should be appreciated that  FIG. 1  merely provides one example of a particular implementation of the electronic device  10 . 
     The CPU/GPU  12  of the electronic device  10  may perform various data processing operations, including generating and/or processing image data for display on the display  18 , in combination with the storage device(s)  14 . For example, instructions that can be executed by the CPU/GPU  12  may be stored on the storage device(s)  14 . The storage device(s)  14  thus may represent any suitable tangible, computer-readable media. The storage device(s)  14  may be volatile and/or non-volatile. By way of example, the storage device(s)  14  may include random-access memory, read-only memory, flash memory, a hard drive, and so forth. 
     The electronic device  10  may use the communication interface(s)  16  to communicate with various other electronic devices or components. The communication interface(s)  16  may include input/output (I/O) interfaces and/or network interfaces. Such network interfaces may include those for a personal area network (PAN) such as Bluetooth, a local area network (LAN) or wireless local area network (WLAN) such as Wi-Fi, and/or for a wide area network (WAN) such as a long-term evolution (LTE) cellular network. 
     Using pixels containing an arrangement μ-LEDs, the display  18  may display images generated by the CPU/GPU  12 . The display  18  may include touchscreen functionality to allow users to interact with a user interface appearing on the display  18 . Input structures  20  may also allow a user to interact with the electronic device  10 . For instance, the input structures  20  may represent hardware buttons. The energy supply  22  may include any suitable source of energy for the electronic device. This may include a battery within the electronic device  10  and/or a power conversion device to accept alternating current (AC) power from a power outlet. 
     As may be appreciated, the electronic device  10  may take a number of different forms. As shown in  FIG. 2 , the electronic device  10  may take the form of a fitness band  30 . The fitness band  30  may include an enclosure  32  that houses the electronic device  10  components of the fitness band  30 . A strap  30  may allow the fitness band  30  to be worn on the arm or wrist. The display  18  may display information related to the fitness band operation. Additionally or alternatively, the fitness band  30  may operate as a watch, in which case the display  18  may display the time. Input structures  20  may allow a person wearing the fitness band  30  navigate a graphical user interface (GUI) on the display  18 . 
     The electronic device  10  may also take the form of a slate  40 . Depending on the size of the slate  40 , the slate  40  may serve as a handheld device such as a mobile phone. The slate  40  includes an enclosure  42  through which several input structures  20  may protrude. The enclosure  42  also holds the display  18 . The input structures  20  may allow a user to interact with a GUI of the slate  40 . For example, the input structures  20  may enable a user to make a telephone call. A speaker  44  may output a received audio signal and a microphone  46  may capture the voice of the user. The slate  40  may also include a communication interface  16  to allow the slate  40  to connect via a wired connection to another electronic device. 
     A notebook computer  50  represents another form that the electronic device  10  may take. It should be appreciated that the electronic device  10  may also take the form of any other computer, including a desktop computer. The notebook computer  50  shown in  FIG. 4  includes the display  18  and input structures  20  that include a keyboard and a track pad. Communication interfaces  16  of the notebook computer  50  may include, for example, a universal service bus (USB) connection. 
     A block diagram of the architecture of the μ-LED display  18  appears in  FIG. 5 . In the example of  FIG. 5 , the display  18  uses an RGB display panel  60  with pixels that include red, green, and blue μ-LEDs as subpixels. Support circuitry  62  thus may receive RGB-format video image data  64 . It should be appreciated, however, that the display  18  may alternatively display other formats of image data, in which case the support circuitry  62  may receive image data of such different image format. In the support circuitry  62 , a video timing controller (TCON)  66  may receive and use the image data  64  in a serial signal to determine a data clock signal (DATA_CLK) to control the provision of the image data  64  in the display  18 . The video TCON  66  also passes the image data  64  to serial-to-parallel circuitry  68  that may deserialize the image data  64  signal into several parallel image data signals  70 . That is, the serial-to-parallel circuitry  68  may collect the image data  64  into the particular data signals  70  that are passed on to specific columns among a total of M respective columns in the display panel  60 . As such, the data  70  is labeled DATA[ 0 ], DATA[ 1 ], DATA[ 2 ], DATA[ 3 ] . . . DATA[M−3], DATA[M−2], DATA[M−1], and DATA[M]. The data  70  respectively contain image data corresponding to pixels in the first column, second column, third column, fourth column . . . fourth-to-last column, third-to-last column, second-to-last column, and last column, respectively. The data  70  may be collected into more or fewer columns depending on the number of columns that make up the display panel  60 . 
     As noted above, the video TCON  66  may generate the data clock signal (DATA_CLK). An emission timing controller (TCON)  72  may generate an emission clock signal (EM_CLK). Collectively, these may be referred to as Row Scan Control signals, as illustrated in  FIG. 5 . These Row Scan Control signals may be used by circuitry on the display panel  60  to display the image data  70 . 
     In particular, the display panel  60  includes column drivers (CDs)  74 , row drivers (RDs)  76 , and micro-drivers (μDs or uDs)  78 . Each uD  78  drives a number of pixels  80  having μ-LEDs as subpixels  82 . Each pixel  80  includes at least one red μ-LED, at least one green μ-LED, and at least one blue μ-LED to represent the image data  64  in RGB format. Although the uDs  78  of  FIG. 5  is shown to drive six pixels  80  having three subpixels  82  each, each μD  78  may drive more or fewer pixels  80 . For example, each μD  78  may respectively drive  1 ,  2 ,  3 ,  4 ,  5 ,  6 ,  7 ,  8 ,  9 ,  10 ,  11 ,  12 , or more pixels  80 . 
     A power supply  84  may provide a reference voltage (VREF)  86  to drive the μ-LEDs, a digital power signal  88 , and an analog power signal  90 . In some cases, the power supply  84  may provide more than one reference voltage (VREF)  86  signal. Namely, subpixels  82  of different colors may be driven using different reference voltages. As such, the power supply  84  may provide more than one reference voltage (VREF)  86 . Additionally or alternatively, other circuitry on the display panel  60  may step the reference voltage (VREF)  86  up or down to obtain different reference voltages to drive different colors of μ-LED. 
     To allow the μDs  78  to drive the μ-LED subpixels  82  of the pixels  80 , the column drivers (CDs)  74  and the row drivers (RDs)  76  may operate in concert. Each column driver (CD)  74  may drive the respective image data  70  signal for that column in a digital form. Meanwhile, each RD  76  may provide the data clock signal (DATA_CLK) and the emission clock signal (EM_CLK) at an appropriate to activate the row of μDs  78  driven by the RD  76 . A row of uDs  78  may be activated when the RD  76  that controls that row sends the data clock signal (DATA_CLK). This may cause the now-activated uDs  78  of that row to receive and store the digital image data  70  signal that is driven by the column drivers (CDs)  74 . The uDs  78  of that row then may drive the pixels  80  based on the stored digital image data  70  signal based on the emission clock signal (EM_CLK). 
     A block diagram shown in  FIG. 6  illustrates some of the components of one of the μDs  78 . The μD  78  shown in  FIG. 6  includes pixel data buffer(s)  100  and a digital counter  102 . The pixel data buffer(s)  100  may include sufficient storage to hold the image data  70  that is provided. For instance, the μD  78  may include pixel data buffers to store image data  70  for three subpixels  82  at any one time (e.g., for 8-bit image data  70 , this may be 24 bits of storage). It should be appreciated, however, that the μD  78  may include more or fewer buffers, depending on the data rate of the image data  70  and the number of subpixels  82  included in the image data  70 . The pixel data buffer(s)  100  may take any suitable logical structure based on the order that the column driver (CD)  74  provides the image data  70 . For example, the pixel data buffer(s)  100  may include a first-in-first-out (FIFO) logical structure or a last-in-first-out (LIFO) structure. 
     When the pixel data buffer(s)  100  has received and stored the image data  70 , the RD  76  may provide the emission clock signal (EM_CLK). A counter  102  may receive the emission clock signal (EM_CLK) as an input. The pixel data buffer(s)  100  may output enough of the stored image data  70  to output a digital data signal  104  represent a desired gray level for a particular subpixel  82  that is to be driven by the μD  78 . The counter  102  may also output a digital counter signal  106  indicative of the number of edges (only rising, only falling, or both rising and falling edges) of the emission clock signal (EM_CLK)  98 . The signals  104  and  106  may enter a comparator  108  that outputs an emission control signal  110  in an “on” state when the signal  106  does not exceed the signal  104 , and an “off” state otherwise. The emission control signal  110  may be routed to driving circuitry (not shown) for the subpixel  82  being driven, which may cause light emission  112  from the selected subpixel  82  to be on or off. The longer the selected subpixel  82  is driven “on” by the emission control signal  110 , the greater the amount of light that will be perceived by the human eye as originating from the subpixel  82 . 
     A timing diagram  120 , shown in  FIG. 7 , provides one brief example of the operation of the μD  78 . The timing diagram  120  shows the digital data signal  104 , the digital counter signal  106 , the emission control signal  110 , and the emission clock signal (EM_CLK) represented by numeral  122 . In the example of  FIG. 7 , the gray level for driving the selected subpixel  82  is gray level  4 , and this is reflected in the digital data signal  104 . The emission control signal  110  drives the subpixel  82  “on” for a period of time defined as gray level  4  based on the emission clock signal (EM_CLK). Namely, as the emission clock signal (EM_CLK) rises and falls, the digital counter signal  106  gradually increases. The comparator  108  outputs the emission control signal  110  to an “on” state as long as the digital counter signal  106  remains less than the data signal  104 . When the digital counter signal  106  reaches the data signal  104 , the comparator  108  outputs the emission control signal  110  to an “off” state, thereby causing the selected subpixel  82  no longer to emit light. 
     It should be noted that the steps between gray levels are reflected by the steps between emission clock signal (EM_CLK) edges. That is, based on the way humans perceive light, to notice the difference between lower gray levels, the difference between the amount of light emitted between two lower gray levels may be relatively small. To notice the difference between higher gray levels, however, the difference between the amount of light emitted between two higher gray levels may be comparatively much greater. The emission clock signal (EM_CLK) therefore may use relatively short time intervals between clock edges at first. To account for the increase in the difference between light emitted as gray levels increase, the differences between edges (e.g., periods) of the emission clock signal (EM_CLK) may gradually lengthen. The particular pattern of the emission clock signal (EM_CLK), as generated by the emission TCON  72 , may have increasingly longer differences between edges (e.g., periods) so as to provide a gamma encoding of the gray level of the subpixel  82  being driven. 
     Various components of the electronic device  10  may be used to control the current signal supplied to drive LED devices  102  of the uLED display  18 . For example, as will be further appreciated, the uDs  78  may include a p-type metal-oxide-semiconductor (PMOS) device, an n-type metal-oxide-semiconductor (NMOS) device, or some combination of PMOS and NMOS devices. 
     In certain embodiments, the number of LED devices  208 A may each be coupled to a high voltage potential rail (e.g., “V DD ”) and a low voltage potential rail or ground (e.g., “V SS ” or “GND”). For example, the high voltage potential rail (e.g., “V DD ”) may be set to a voltage of 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V, or other similar voltage that may be used to supply power to the Subpixels  82  for operation. Similarly, the low voltage potential rail or ground (e.g., “V SS ” or “GND”)  212 A may be generally set to a ground voltage (e.g., 0 V or approximately 0 V). 
     In some embodiments, the uDs  78  may each include a PMOS driver used to drive the Subpixels  82 . For example, PMOS drivers may be used as part of the uDs  78  in order to conserve physical area of the uLED display  18  by avoiding level shifters that may be otherwise involved. However, in some embodiments, utilizing PMOS drivers as part of the uDs  78  may lead to image artifacts (e.g., flicker) becoming present on the uLED display  18 , as the PMOS drivers may be sensitive to variations of the high voltage potential rail (e.g., “V DD ”)  210 A. The variations of the high voltage potential rail (e.g., “V DD ”)  210 A may be caused by IR drop (e.g., voltage drops across the resistance R of the power supply  198 A between supply pins and one or more components drawing a current I). For example,  FIG. 8  illustrates plots  214 A and  214 B of the drive current (e.g., “I LED ”) variation due to IR drop supplied to the subpixels  82 . As illustrated, the IR drop may cause the drive current (e.g., “I LED ”) of the subpixels  82  to vary by N % (e.g. 5-10% or otherwise significantly enough for the variation to appear as visible artifacts to a user of the uLED display  18 ). 
     Indeed, the V DD  variations may vary depending on the incoming image data and the image pattern, as the luminance of the uLED display  18  and the characteristics of the subpixels  82  may also be variable. Furthermore, variations in the threshold voltage (e.g., “V TH ”) of the subpixels  82  may also adversely impact the drive currents (e.g., “I LED ”) of the subpixels  82 . As may be further appreciated, the V DD  and V TH  variations may be exacerbated for larger area uLED displays  18 . Thus, as will be further appreciated with respect to  FIGS. 9-20 , it may be useful to provide V DD  and V TH  compensation circuitry  205  as part of the uDs  78  to compensate for the aforementioned V DD  and V TH  adverse variations. In this way, any possible occurrence of image artifacts becoming apparent on the uLED display  18  may be reduced or substantially eliminated. 
     Turning now to  FIG. 9 , which illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs  78  including V DD  and V TH  compensation circuitry  205  that may be used to compensate for the V DD  and V TH  variations that may be due to, for example, IR drop (e.g., voltage drops across the resistance R of the power supply  198 A between supply pins and one or more components drawing a current I) associated the high voltage potential rail (e.g., “V DD ”)  210 A. In certain embodiments, the uDs  78  may be set to operate over one or more phases of the drive currents (e.g., “I LED ”) of the subpixels  82 . 
     For example, in an initial phase (e.g., “Phase  1 ”), the voltage VB may be low (e.g., approximately “GND” or 0 V). Thus, a PMOS transistor  224 A (e.g., “M 1 ”) coupled (e.g., in series) between a PMOS transistor  226 A (e.g., “M 2 ”) and the high voltage potential rail (e.g., “V DD ”)  210 A coupled directly to the high voltage potential rail (e.g., “V DD ”)  210 A may be “ON” (e.g., activated). The PMOS transistor  226 A (e.g., “M 2 ”) may also be “ON,” as the voltage EM may also be low (e.g., approximately “GND” or 0 V) in the initial phase (e.g., “Phase  1 ”). Accordingly, a drive current may be allowed to flow from the high voltage potential rail (e.g., “V DD ”)  210 A to the LED device  208 A. In some embodiments, the PMOS transistor  224 A (e.g., “M 1 ”) may be susceptible to V DD  voltage variations, while the PMOS transistor  226 A (e.g., “M 2 ”) may be susceptible to V TH  voltage variations. 
     In certain embodiments, in a reset phase  229  (e.g., “Phase  2 ”), the voltage EM may be low (e.g., approximately “GND” or 0 V), while the voltages VA and VB may be expressed as: 
     
       
         
           
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     A 
                   
                   = 
                   
                     
                       V 
                       Ref 
                     
                     . 
                   
                 
               
               
                 
                   equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     1 
                     ) 
                   
                 
               
             
             
               
                 
                   VB 
                   = 
                   
                     
                       V 
                       
                         DD 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         _ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         CL 
                       
                     
                     - 
                     
                       
                         V 
                         TH 
                       
                       . 
                     
                   
                 
               
               
                 
                   equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     2 
                     ) 
                   
                 
               
             
           
         
       
     
     Specifically, in equation (1), V Ref  may be the reference supply voltage for the LED device  208 A that may be controlled by the PMOS  228 A. In equation (2), V DD   _   CL  may be an additional high voltage potential rail (e.g., “V DD   _   CL ”)  217 A (e.g., independent of the high voltage potential rail (“V DD   _   CL” )  210 A). Thus, in the reset phase (e.g., “Phase  2 ”), when V A =V Ref  and V B =V DD   _   CL  V TH , the following condition may exist:
 
 VB=V   DD   _   CL   −V   TH ,for  VB   &lt;   V   TH   _   LED   equation (3).
 
     In this case, the LED device  208 A may not turn “ON.” Furthermore, in the reset phase (e.g., “Phase  2 ”), the voltage VC (e.g., voltage across a compensation capacitance  230 A) may be expressed as:
 
 VC=V   Ref   −V   DD   _   CL   −V   TH   equation (4).
 
     As may be appreciated from equation (4), the voltage VC may be a voltage across a compensation capacitance  230 A that may, in some embodiments, be the difference between the reference voltage V Ref  and the voltage VB. 
     In certain embodiments, in another reset phase  231  (e.g., “Phase  3 ”), the voltages VA and VB may be then expressed as: 
     
       
         
           
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     A 
                   
                   = 
                   
                     
                       V 
                       DD 
                     
                     . 
                   
                 
               
               
                 
                   equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     5 
                     ) 
                   
                 
               
             
             
               
                 
                   VB 
                   = 
                   
                     
                       V 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       A 
                     
                     - 
                     
                       VC 
                       . 
                     
                   
                 
               
               
                 
                   equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     6 
                     ) 
                   
                 
               
             
           
         
       
     
     Expanding equations (5) and (6) based on equations (1), (2), and (4), the voltage VB may be then expressed as:
 
 VB=V   DD   −V   Ref   +V   DD   _   CL   −V   TH   equation (7).
 
     Thus, when VB&lt;V DD −V TH  and V TH &lt;V DD   _   CL &lt;V Ref , the PMOS transistor  216 A (e.g., “M 1 ”), the PMOS transistor  224 A (e.g., “M 5 ”), and the PMOS transistor  228 A (e.g., “M 6 ”) may each be “ON” (e.g., conductive or in the saturation mode). Indeed, further, when V Ref &lt;V TH &lt;V TH Diode , the LED device  208 A drive current I LED  may be expressed as:
 
 I   LED   =K ( V   GS   −V   TH ) 2   =K ( V   DD   −VB−V   TH ) 2   equation (8).
 
     Expanding equation (8) based on equation (7), the LED device  208 A drive current I LED  may be then expressed as:
 
 I   LED   =K ( V   DD −( V   DD   −V   Ref   +V   DD   _   CL   −V   TH )− V   TH ) 2   equation (9).
 
     Lastly, simplifying equation (9), the LED device  208 A drive current I LED  may be expressed as:
 
 I   LED   =K ( V   Ref   +V   DD   _   CL ) 2   equation (10).
 
     Accordingly, equation (10) illustrates that LED device  208 A drive current I LED  may be independent of the high voltage potential rail (e.g., V DD ) and the threshold voltage (e.g., V TH ), and may thus compensate for V DD  and V TH  variations that may otherwise adversely affect drive current I LED  (e.g., due to IR drop). Indeed, instead of being a function of V DD  and V TH  (e.g., as expressed by equation (8)) and, by extension, being susceptible to V DD  and V TH  variations (e.g., due to IR drop), the LED device  208 A drive current I LED  may be function of the uDs  78  reference voltage V Ref  and the compensation voltage potential rail V DD   _   CL . In this way, any possible occurrence of image artifacts becoming apparent on the uLED display  18  may be reduced or substantially eliminated. 
     As a further example of the presently disclosed embodiments,  FIG. 10  illustrates a timing diagram  232 A, which depicts each of the aforementioned V DD  and V TH  compensation phases (e.g., “PH 1 ,” “PH 2 ,” and “PH 3 ”). Specifically,  FIG. 10  illustrates an emission clock reset signal  232 A (e.g., “EM_CLK_RST”), the LED device  208 A drive current signal  236 A (e.g., “EM_CLK”), LED device  208 A emission signal  238 A (e.g., “Emission”), and compensation phases timing signal  240 A. As depicted in  FIG. 10 , during phase  1  (e.g., “PH 1 ”), VB=0. During phase  2  (e.g.,  229 , “PH 2 ”), corresponding to a period of time in which the uD  78  generates the emission clock reset signal  232 A (e.g., “EM_CLK_RST”), VA=V Ref  and VB=V DD   _   CL −V TH . In certain embodiments, during phase  3  (e.g., “PH 3 ”), VA=V DD  and VB=V DD −V Ref +V DD   _   CL −V TH . As illustrated, during phase  3  (e.g., “PH 3 ”), the LED device  208 A drive current signal  236 A (e.g., “EM_CLK”) may be activated, in which over the period of phase  3  (e.g.,  231 , “PH 3 ”) the duty cycle of the pulses of the of drive current signal  236 A (e.g., “EM_CLK”) may vary (e.g., corresponding to a period in which the LED device  208 A is emitting as illustrated by the emission signal  238 A) based on, for example, the incoming image data and the image pattern. 
     Turning now to  FIG. 11 , which illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs  78  including V DD  and V TH  compensation circuitry  205  that may be used to compensate for the V DD  and V TH  variations that may be due to, for example, IR drop associated the high voltage potential rail (e.g., “V DD ”)  210 A. Specifically,  FIG. 11  illustrates that the V DD  and V TH  compensation is shared between all LED device  208 A with the same color (e.g., for each respective R, G, and B LED device  208 A). For example, the uD  78  may provide V DD  and V TH  compensation for each color red LED device  208 A of the uLED display  18 , green LED device  208 A of the uLED display  18 , and blue LED device  208 A of the uLED display  18 . 
       FIG. 12  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs  78  including V DD  and V TH  compensation circuitry  205  included as part of the backplane  248 A (e.g., as opposed to being included as part of the uDs  78 ). Similarly, as discussed in  FIG. 11 , the uD  78  may provide V DD  and V TH  compensation for each color red LED device  208 A of the uLED display  18 , green LED device  208 A of the uLED display  18 , and blue LED device  208 A of the uLED display  18 . 
       FIG. 13  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs  78  including V DD  and V TH  compensation circuitry  205  included as part of the uDs  78 . Specifically,  FIG. 13  illustrates that the V DD  and V TH  compensation circuitry  205  may be used to generate a shared current source (e.g., allowing the same reference current to be shared across multiple color subpixels  82  by scaling the singular reference current source) locally at the uD  78 . For example, the uD  78  may provide V DD  and V TH  compensation for each of the red LED device  208 A, green LED device  208 A, and blue LED device  208 A. Such a configuration may allow the each uD  78  to include respective V DD  and V TH  compensation circuitry  205 . 
       FIG. 14  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs  78  including noise reduction circuitry  270 . Indeed, in some embodiments, V DD  noise could be generated by sparks emanating from on/off of each subpixel  82 .  FIG. 14  illustrates that a voltage reference  272  (e.g., “V Ref ”) and a clean ground voltage (e.g., “GND”)  274  that may be included as part of each uD  78 . Furthermore,  FIG. 14  illustrates the current may be generated locally by the uD  78  and used as a reference for each subpixel  82 . 
     Turning now to  FIG. 15 , which illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) of the uDs  78  including V SS  and V TH  compensation circuitry  205  that may be used to compensate for V SS  and V TH  variations including NMOS devices. In certain embodiments, the uDs  78  may be set to operate over one or more phases of the drive currents (e.g., “I LED ”) of the subpixels  82 . For example, in an initial phase (e.g., “PH 1 ”), the voltage VA=V Ref  and =V DD . In the sampling phase (e.g., “PH 2 ”), VB=V Ref +V TH , and the drive current may flow as depicted by the phase  1  path  281 . Lastly, in the operation phase (e.g., “PH 3 ”), the drive current I M1 =I 0 . The phase  2  path  282  and phase  3  path  284  are depicted passing through the NMOS transistors  278  (e.g., “M 1 ”), compensation capacitor  280 , and NMOS transistors  286  (e.g., “M 7   a ”) and  288  (e.g., “M 7   b ”), which includes a clean ground voltage for phase  2  (e.g., “PH 2 ”). Thus, I M1  (e.g., the drive current across the NMOS transistor  278 ) may not be dependent upon V SS  and V TH , and instead dependent upon only the reference current I 0 .  FIG. 16  illustrates the corresponding plot diagram  300  for the compensation capacitor  280  illustrating the reset phases  302  and  304 , and compensation capacitor period  306 . 
     As a further example,  FIG. 17  illustrates a timing diagram  308 , which depicts each of the aforementioned V SS  and V TH  compensation phases (e.g., “PH 1 ,” “PH 2 ,” and “PH 3 ”). Specifically,  FIG. 17  illustrates an emission clock reset signal  310  (e.g., “EM_CLK_RST”), the LED device  208 A drive current signal  312  (e.g., “EM_CLK”), LED device  208 A emission signal  314  (e.g., “Emission”), LED device  208 A emission signal  316  (e.g., “Emission_B”), and compensation phases timing signal  318 . As depicted in  FIG. 17 , during phase  1  (e.g., “PH 1 ”), VA=V Ref  and VB=V DD . During phase  2  (e.g., “PH 2 ”), corresponding to a period of time in which the uD  78  generates the emission clock reset signal  310  (e.g., “EM_CLK_RST”), VB=V Ref +V Ref . In certain embodiments, during phase  3  (e.g., “PH 3 ”), I M1 =I 0 . Thus, I M1  may not be dependent upon V SS  and V TH . 
       FIG. 18  illustrates an embodiment of a circuit diagram (e.g., equivalent circuit) including dedicated compensation circuitry  205  for each subpixel  82 . In this embodiment, V Ref  and V DD  may include one or more clean pin swaps. Specifically, in phase  2  (e.g., “PH 2 ”), the left plate of the sampling capacitor  328  (e.g., “C s ”) may be connected to the source terminal of the EM switch  326  (e.g., node VSRC). In this way, any AV DD  IR variation due to the finite resistance of the EM switch  330  may be eliminated and/or substantially reduced. In some embodiments, the voltage “VINIT” may be a ground voltage (e.g., GND) or a negative polarity voltage.  FIG. 19  illustrates the corresponding timing diagram for the initiation phase  338  (e.g., “Init”), phase  1   340  (e.g., “PH 1 ”), and phase  2   342  (e.g., “PH 2 ), and the emission pulse  344  (e.g., EM_Pulse). 
     The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

Metadata:
Filing Date: 20160825
Publication Date: 20190226
Grant Date: 20190226
Priority Date: 20150925
Inventors: VAHID FAR, MOHAMMAD B.
BI, YAFEI
ONO, SHINYA
BAE, HOPIL
LIN, CHIEH-CHIEN
AKYOL, HASAN
WANG, XIAOFENG
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G2320/02", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2330/021", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/2003", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/0272", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/22", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2300/08", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0272", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/32", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G3/2088", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/32", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G3/2014", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0233", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0223", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/045", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0861", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0842", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/045", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0233", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2320/0223", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0861", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0842", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0819", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/2014", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/2088", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2330/021", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0272", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 65410919