PATENT DOCUMENT

Publication Number: US-8436863-B2
Application Number: US-201213532358-A
Country: US
Kind Code: B2

Title: Switch for graphics processing units

Abstract:
Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval.

Claims:
What is claimed is: 
     
       1. A method of operating a display system, comprising:
 determining whether a first graphics processing unit (GPU) has undergone a horizontal blanking interval (HBI); 
 incrementing a counter responsive to the determination whether the first GPU has undergone a HBI; 
 receiving a switch request; 
 determining whether a second GPU is undergoing a vertical blanking interval (VBI) responsive to receiving the switch request and to the determination whether the first GPU has undergone a HBI; and 
 calibrating the second GPU responsive to the determination that the second GPU is undergoing a vertical blanking interval. 
 
     
     
       2. The method of  claim 1 , further comprising providing an indication to a multiplexer that the first GPU is undergoing a HBI and the second GPU is undergoing a VBI. 
     
     
       3. The method of  claim 1 , wherein in calibrating the second GPU is dependent upon a value in the counter. 
     
     
       4. The method of  claim 1 , wherein calibrating the second GPU further comprises offsetting a display image from the second GPU by a value in the counter. 
     
     
       5. The method of  claim 1 , wherein the display system further comprises a chipset, wherein the first GPU is internal to the chipset and the second GPU is external to the chipset. 
     
     
       6. The method of  claim 1 , further comprising maintaining image data from the first GPU while switching from the first GPU to the second GPU. 
     
     
       7. A display system, comprising:
 means for determining whether a first graphics processing unit (GPU) has undergone a horizontal blanking interval (HBI); 
 means for incrementing a counter responsive to the determination that the first GPU has undergone a HBI; 
 means for receiving a switch request; 
 means for determining whether a second GPU is undergoing a vertical blanking interval (VBI) responsive to receiving the switch request and to the determination that the first GPU has undergone a HBI; and 
 means for calibrating the second GPU responsive to the determination that the second GPU is undergoing a VBI. 
 
     
     
       8. The display system of  claim 7 , further comprising means for providing an indication to a multiplexer that the first GPU is undergoing a HBI and the second GPU is undergoing a VBI. 
     
     
       9. The display system of  claim 7 , wherein the means for calibrating the second GPU is dependent upon a value in the counter. 
     
     
       10. The display system of  claim 7 , wherein the means for calibrating the second GPU includes means for offsetting a display image from the second GPU by a value in the counter. 
     
     
       11. The display system of  claim 7 , further comprising means for switching between the first GPU and the second GPU. 
     
     
       12. The display system of  claim 11 , wherein the means for switching between the first GPU and the second GPU includes means for maintaining image data from the first GPU.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 12/347,364, entitled “Switch for Graphics Processing Units,” filed on Dec. 31, 2008, now U.S. Pat. No. 8,207,974, which is incorporated by reference as fully disclosed herein. 
     This application is related to, and incorporates by reference, the following applications: U.S. patent application Ser. No. 12/347,312, entitled “Timing Controller Capable of Switching Between Graphics Processing Units,” filed on Dec. 31, 2008; U.S. patent application Ser. No. 12/347,413, entitled “Display System With Improved Graphics Abilities While Switching Graphics Processing Units,” filed on Dec. 31, 2008; and U.S. patent application Ser. No. 12/347,491, entitled “Timing Controller for Graphics System” filed on Dec. 31, 2008. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to graphics processing units (GPUs) of electronic devices, and more particularly to switching between multiple GPUs during operation of the electronic devices. 
     2. Background 
     Electronic devices are ubiquitous in society and can be found in everything from wristwatches to computers. The complexity and sophistication of these electronic devices usually increase with each generation, and as a result, newer electronic devices often include greater graphics capabilities their predecessors. For example, electronic devices may include multiple GPUs instead of a single GPU, where each of the multiple GPUs may have different graphics capabilities. In this manner, graphics operations may be shared between these multiple GPUs. 
     Often in a multiple GPU environment, it may become necessary to swap control of a display device among the multiple GPUs for various reasons. For example, the GPUs that have greater graphics capabilities may consume greater power than the GPUs that have lesser graphics capabilities. Additionally, since newer generations of electronic devices are more portable, they often have limited battery lives. Thus, in order to prolong battery life, it is often desirable to swap between the high-power GPUs and the lower-power GPUs during operation in an attempt to strike a balance between complex graphics abilities and saving power. 
     Regardless of the motivation for swapping GPUs, swapping GPUs during operation may cause defects in the image quality, such as image glitches. Although techniques have been developed for switching between GPUs during the vertical or horizontal blanking periods, such approaches often involve circuitry with complex performance requirements, additional power usage, and/or increased cost. This may be especially true when switching between an internal GPU and an external GPU. Accordingly, methods and apparatuses that more efficiently switch between GPUs are needed. 
     SUMMARY 
     Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval. 
     Other embodiments may include a method of switching between GPUs during operation of a display system, the method may include determining if a switching window exists, in the event that a switching window exists, determining if a host computer requested a GPU switch, in the event that a host computer requests a GPU switch, switching from a first GPU to a second GPU, determining if the second GPU enters a blanking interval that is subsequent to the switching window, and in the event that the second GPU enters a blanking window that is subsequent to the switching window, displaying at least one image on a display from the second GPU. 
     Still other embodiments may include a method of switching between GPUs during operation of a display system, the method may include determining if the first GPU has undergone a horizontal blanking interval (HBI) a predetermined number of times, in the event that the first GPU has undergone an HBI a predetermined number of times, determining if a second GPU is undergoing a VBI, and in the event that the second GPU is undergoing a VBI, calibrating the second GPU such that an image of the second GPU is substantially synchronous with another image of the first GPU. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an exemplary display system. 
         FIG. 2  illustrates exemplary operations that may be performed by the display system. 
         FIG. 3  illustrates an exemplary switch window. 
         FIG. 4  illustrates exemplary switching operations during a horizontal blanking interval. 
     
    
    
     The use of the same reference numerals in different drawings indicates similar or identical items. 
     DETAILED DESCRIPTION OF THE INVENTION 
     The following discussion describes various embodiments that allow greater flexibility in switching between GPUs during operation of a display system without introducing visual artifacts into the image being displayed. Some embodiments may implement an analog multiplexer that switches between GPUs during a switching window. The switching window may include an overlapping time frame of the vertical and/or horizontal blanking intervals of the GPUs being switched. One or more blocks within the display system, such as a timing controller, may indicate to the analog multiplexer when this switching window occurs. Unlike conventional multiplexer approaches, the analog multiplexer need not decode and/or encode the images to be displayed to determine an appropriate switching window. As a result, the graphics multiplexer may have less stringent performance requirements, consume less power, and/or cost less to manufacture than conventional approaches. 
     Although one or more of these embodiments may be described in detail, the embodiments disclosed should not be interpreted or otherwise used as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application. Accordingly, the discussion of any embodiment is meant only to be exemplary and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these embodiments. 
       FIG. 1  illustrates an exemplary display system  100  that may be implemented in one embodiment. Prior to delving into the specifics of  FIG. 1 , it should be noted that the components listed in  FIG. 1 , and referred to below, are merely examples of one possible implementation. Other components, buses, and/or protocols may be used in other implementations without departing from the spirit and scope of the detailed description. Also, although one or more components of the display system  100  are represented using separate blocks, it should be appreciated that one or more of the components of the display system  100  may be part of the same integrated circuit. 
     Referring now to  FIG. 1 , the display system  100  may include a host computer system  105 . In some embodiments, the host computer  105  may be a laptop computer operating on battery power. In other embodiments, the host computer  105  may be a desktop computer, enterprise server, or networked computer device that operates off of wall power. During operation, the host computer  105  may communicate control signals and other communication signal to various devices within the system. 
     The display system also may include multiple GPUs  110 A- 110   n . These GPUs  110 A- 110   n  may exist within the computer system  100  in a variety of forms and configurations. In some embodiments, the GPU  110 A may be implemented as part of another component within the system  100 . For example, the GPU  110 A may be part of a chipset in the host computer  105  (as indicated by the dashed line  115 ) while the other GPUs  110 B- 110   n  may be external to the chipset. The chipset may include any variety of integrated circuits, such as a set of integrated circuits responsible for establishing a communication link between the GPUs  110 -A- 110   n  and the host computer  105 , such a Northbridge chipset. 
     A graphics multiplexer (G-MUX)  120  may be coupled to both the host computer  105  and the GPUs  110 A- 110   n . As will be described in greater detail below, during operation, the G-MUX  120  may effectuate switching between the GPUs  110 A- 110   m . In some embodiments, the G-MUX  120  may be an analog switch rather than a digital switch. Also, the G-MUX  120  may be integrated within other components within the display system  100 , such as a microprocessor within the host computer  105  or any of the GPUs  110 A- 110   n.    
     The G-MUX  120  may be further coupled to a timing controller (T-CON)  125 , which may receive video image and frame data from various components in the system. As the T-CON  125  receives these signals, it may process them and send them out in a format that is compatible with a display  130  coupled to the T-CON  125 . The display  130  may be any variety including liquid crystal displays (LCDs), plasma displays, cathode ray tubes (CRTs) or the like. Likewise, the format of the video data communicated from the T-CON  125  to the display  130  may include a wide variety of formats, such as display port (DP), low voltage differential signaling (LVDS), etc. 
     During operation of the video system  100 , the GPUs  110 A- 110   n  may generate video image data along with frame and line synchronization signals. For example, the frame synchronization signals may include a vertical blanking interval (VBI) in between successive frames of video data. Further, the line synchronization signals may include a horizontal blanking interval (HBI) in between successive lines of video data. Data generated by the GPUs  110 A- 110   n  may be communicated to the T-CON  125 . 
     When the T-CON  125  receives these signals, it may process them and send them out in a format that is compatible with a display  130  coupled to the T-CON  125 , such as DP, LVDS, etc. 
     Referring still to  FIG. 1 , the GPUs  110 A- 110   n  may have different operational capabilities. For example, as mentioned above, the GPU  110 A may be integrated within another device in the display system  100 , such as a chipset in the host computer  105 , and as such, the GPU  110 A may not be as graphically capable as the GPU  110 B, which may be a stand alone discrete integrated circuit. In addition to having different operational capabilities, the GPUs  110 A- 110   n  may consume different amounts of power. Because of this, it may be necessary to balance the desire to use the GPU  110 B (i.e., have more graphical capabilities) with the desire to use the GPU  110 A (i.e., consume less power) by switching among the GPUs  110 A- 110   n.    
     In order to perform switching between the GPUs  110 A- 110   n  without introducing visual artifacts such as glitches or screen tearing, the switching between the GPUs  110 A- 110   n  should occur during either the VBI and/or during the HBI. Conventional switching techniques often employ a graphics multiplexer or switch that decodes the video data to determine the location of the VBI or HBI within the video data. Conventional graphics multiplexers then switch during this time and then re-encode the video data before sending it along to the T-CON  125 . However such conventional approaches often increase performance requirements, power usage, and cost of the graphics multiplexer. 
     In some embodiments, however, the analog G-MUX  120  may not need to decode and/or re-encode the signals to effectuate a GPU switch. For example, as shown in the embodiment of  FIG. 1 , the T-CON  125  may provide one or more switching window signals to the G-MUX  120  to indicate a blanking interval (e.g., VBI or HBI) in which the GPU switch may be performed. Since the T-CON  125  may already know where the blanking interval occurs in the video signal, providing this switching window indication to the G-MUX  120  may not require additional circuitry or power consumption. In some embodiments, other blocks such as the host controller  105  and/or one or more of the GPUs  110 A- 110   n  may provide the switching window signal. 
       FIG. 2  illustrates exemplary operations that may be performed by the display system  100  during a GPU switch. In block  202 , the operations may begin with the display  130  being updated from a current GPU. Next, in block  205 , the G-MUX  120  may await indication that a switching window exists. If a switching window does not exist, then control may flow back to block  202  where the display  130  is updated from the current GPU. In some embodiments, the indication as to whether a switching window exists may come from the T-CON  125 , while in other embodiments this indication may come from other blocks within the display system  100 . Thus, the G-MUX  120  does not decode the incoming video data to determine when the a blanking interval occurs, but instead may rely on another block, such as the T-CON  125 , to provide an indication of when the switching window exists. Because of this, the G-MUX  120  does not need to re-encode the video data before sending it to the display  130 , and therefore, the performance requirements of the G-MUX  120  may be simplified. This also may allow the G-MUX  120  to consume less power and cost less than conventional approaches. 
       FIG. 3  illustrates exemplary switching windows  210  and  215 . In some embodiments, the switching window may mirror the VBI as shown by the switching window  210 . During the switching window, the T-CON  125  may be prepared to lose the incoming signal due to a GPU switch. Because of the finite time available for a GPU switch, in some embodiments, the switching window may be smaller than the blanking interval as shown by the switching window  215 . 
     Referring again to  FIG. 2 , in the event that the T-CON  125  does detect that a switching window exists, control may flow to block  220 , where the G-MUX  120  may wait for the host computer  105  to request a GPU switch. As mentioned above, the GPU switch request may occur because the host computer  105  is consuming too much power or because the host computer  105  needs greater graphics processing abilities. 
     After the T-CON  125  indicates that a switching window exists, the T-CON  125  may enter an “expecting switch” mode and hold the present screen. For example, in one embodiments, the T-CON  125  may repaint the display  130  with an image from a frame buffer (not specifically shown in  FIG. 1 ) repetitively until the G-MUX  120  completes the GPU switch. This may reduce the overall number of visual artifacts resulting from a GPU switch. 
     Referring still to  FIG. 2 , as shown in block  220 , in the event that the host computer  105  has yet to request a GPU switch, control may flow back to block  205 , where it is determined whether a switching window exists. If, however, the host computer  105  has requested the GPU switch while the switching window exists, then the switch may be performed as shown in block  225 . 
     Once the G-MUX  120  has switched GPUs, the T-CON  125  may wait until it sees a blanking interval in the new video data before it stops repainting the display  130  with the old image from the frame buffer and begins painting the image from the new GPU. As shown in block  230 , the T-CON  125  may wait until the new GPU enters a blanking period before it begins painting the display  130  from the new GPU (as shown in block  235 ). In this manner, control may flow back to the block  230  while the T-CON  125  waits for the new GPU to enter a blanking period. 
     As mentioned previously, the GPU switch may occur during the VBI or HBI.  FIG. 4  illustrates exemplary operations for performing the GPU switch during the HBI. Frames of video data may be painted on the display at a predetermined rate—e.g., 60 times per second—where a VBI may be present between successive frames. Each frame also may include a plurality of scan lines of video data in pixel form where an HBI may be present between successive scan lines. In block  420 , the T-CON  125  may determine whether the current GPU is undergoing an HBI. For example, the T-CON  125  may operate on the display system&#39;s  100  pixel clock (not specifically shown in the figures) and note when a predetermined number of pixels representing a scan line have been painted on the display  130  and the current GPU is in an HBI. 
     Switching between GPUs during an HBI may be more complicated than switching during a VBI because of synchronization of the new GPU with the correct scan line. For example, if the GPU switch occurs after the current GPU paints display scan line n, then the new GPU may need to start updating the display  130  at the beginning of the display scan line n+1. In this manner, the new GPU may need to count back the number of scan lines that have transpired since the GPU switch. Thus, if the current GPU is undergoing an HBI then a counter  410  within the T-CON  125  (shown in  FIG. 1 ) may be incremented per block  421  to note the overall number of HBIs that have occurred since the switch to the current GPU. 
     Next, the G-MUX  120  may determine if a switch request has occurred in block  422 . As shown in  FIG. 1 , this switch request may come from the host computer  105 , although other embodiments are possible where the switch request originates from another block with the system  100 . In the event that a switch request has yet to occur, then the T-CON  125  may determine if the current GPU is still undergoing an HBI per block  423 . If the current GPU is still undergoing an HBI, then control may loop back to block  422  to again determine if a switch request has occurred. If the current GPU is not still undergoing an HBI, then control may loop back to block  420 , where the T-CON  125  may monitor for the condition where the current GPU enters HBI. 
     Referring still to block  422 , in the event that a switch request has occurred, then a glitch-free GPU switch may be performed per block  424 . If the new GPU has not yet reached VBI, the control may flow back to block  425  until the new GPU enters VBI. On the other hand, when the new GPU enters VBI, then the value in counter  410  may be read and used to count back the number of scan lines from the VBI for the new GPU to synchronize per block  430 . As shown, control may loop back to block  425  until the new GPU is in VBI. In other words, the value in counter  410  may be used as an offset from the VBI to determine the location in the frame of video data from which the new GPU should start painting data so that a glitch free switch occurs on the display  130 . After this synchronization, the T-CON  125  may use the new GPU to drive the display  130 .

Metadata:
Filing Date: 20120625
Publication Date: 20130507
Grant Date: 20130507
Priority Date: 20081231
Inventors: SAKARIYA KAPIL V.
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G2360/06", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2360/06", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2360/08", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G5/363", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2360/08", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G5/363", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 42284359