PATENT DOCUMENT

Publication Number: US-10943935-B2
Application Number: US-201715682255-A
Country: US
Kind Code: B2

Title: Methods for transferring charge in an image sensor

Abstract:
Apparatuses and methods for charge transfer in image sensors are disclosed. One example of an image sensor pixel may include a first charge storage node and a second charge storage node. A transfer circuit may be coupled between the first and second charge storage nodes, and the transfer circuit may have a first region proximate the first charge storage node and configured to have a first potential. The transfer circuit may also have a second region proximate the second charge storage node configured to have a second, higher potential. An input node may be configured to control the first and second potentials based on a transfer signal provided to the input node.

Claims:
What is claimed is: 
     
       1. A method of transferring charge from a first storage node to a second storage node in an integrated circuit (IC), the method comprising:
 turning off an initial transfer gate to electrically isolate a photodiode from the first storage node; 
 accumulating a photon-generated charge in the photodiode during an integration time; 
 applying, at a transfer gate, a first potential to a first region of the IC and to a second region of the IC, wherein:
 the first region of the IC is between the first storage node and the second region of the IC, the first region and the second region being positioned adjacent to the transfer gate; 
 the first region is configured to maintain a first variable potential less than a second variable potential of the second region; 
 a virtual barrier region of the IC is between the second region and the second storage node, and is configured to have a virtual barrier potential less than a potential of the second storage node; and 
 the first potential causes the first variable potential to be less than a fixed potential of the first storage node; 
 
 accumulating a quantity of charge in the first storage node by turning on the initial transfer gate and transferring at least a portion of the photon-generated charge from the photodiode to the first storage node; 
 electrically isolating the first storage node from the photodiode by turning off the initial transfer gate; 
 applying, at the transfer gate, a second potential to the first region and to the second region so that:
 the first variable potential is greater than the fixed potential of the first storage node; and 
 a portion of the accumulated quantity of charge in the first storage node is transferred into the second region; and 
 
 applying, at the transfer gate, a third potential to the first region and to the second region so that the second variable potential is less than the virtual barrier potential and the portion of the accumulated quantity of charge is transferred from the second region into the second storage node. 
 
     
     
       2. The method of  claim 1 , further comprising initially depleting the first storage node of an initial charge. 
     
     
       3. The method of  claim 1 , wherein the portion of the accumulated quantity of charge is a first portion of the accumulated quantity of charge, the method further comprising applying the first, second, and third potentials so that a second portion of the accumulated quantity of charge is transferred from the first storage node into the second storage node. 
     
     
       4. The method of  claim 3 , further comprising iteratively applying the first, second, and third potentials until a final portion of the accumulated quantity of charge has been transferred to the second storage node. 
     
     
       5. The method of  claim 1 , further comprising iteratively applying the first, second, and third potentials for a fixed time period. 
     
     
       6. The method of  claim 1 , wherein the fixed potential of the first storage node is greater than the potential of the second storage node. 
     
     
       7. The method of  claim 1 , further comprising, before accumulating the photon-generated charge in the photodiode, depleting a first initial charge in the photodiode and a second initial charge in the first storage node. 
     
     
       8. The method of  claim 1 , further comprising repeatedly applying the first, second, and third potentials at the transfer gate to cause subsequent portions of the accumulated quantity of charge in the first storage node to be transferred to the second storage node. 
     
     
       9. The method of  claim 8 , wherein the first, second, and third potentials are applied until the accumulated quantity of charge in the first storage node is substantially completely transferred to the second storage node. 
     
     
       10. The method of  claim 8 , further comprising:
 transferring the portions of the accumulated charge that were transferred into the second storage node to a third storage node. 
 
     
     
       11. The method of  claim 10 , wherein transferring the portions of the accumulated charge that were transferred into the second storage node to the third storage node includes applying a transfer signal to a third transfer gate, separate from the transfer gate and the initial transfer gate, to isolate the second storage node from the third storage node. 
     
     
       12. The method of  claim 10 , further comprising generating an output signal based on the portion of the accumulated charge that was transferred into the second storage node and was transferred to the third storage node.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. Nonprovisional patent application Ser. No. 13/787,094, filed Mar. 6, 2013, the disclosures of which are hereby incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to image sensors, and, more specifically, to charge transfer in image sensors. 
     BACKGROUND 
     In image sensors, charge frequently needs to be transferred between a plurality of different nodes. For example, in a global shutter complementary metal oxide semiconductor (CMOS) image sensor, charge accumulated in a photodiode from incident photons may need to be transferred from the photodiode to a storage node, and then, subsequently, to a floating diffusion node for global shutter read out. 
     In order to accomplish the charge transfer from one node to another node, the nodes are frequently designed such that during operation, the node to which the charge is to be transferred (i.e., the destination node) has a greater electric potential than the node from which the charge is to be transferred (i.e., the source node). A transistor may be coupled between the two nodes, with the transistor controlling the electric potential of a region between the nodes such that a barrier can be created and removed responsive to a transfer signal provided to the transistor&#39;s input gate. When the barrier between two nodes is removed, the charge typically flows to the node with the higher potential until that node is “full,” and any remaining charge may spill back into the other node. Thus, in order to fully transfer charge from one node to another, the destination node may need to have a potential that is greater than the potential of the source node by an amount equal to or exceeding the amount of charge to be transferred. In other words, the destination node may need to have sufficient well capacity to hold the charge from the source node without sharing the charge back with the source node when the barrier between the nodes is removed. In order to achieve full charge transfer between a plurality of nodes, the electric potential is thus increased for successive nodes, with the increase in electric potential between each successive node generally equaling or exceeding the full well capacity for the pixel. 
     Increasing the potential for each successive node, however, typically requires higher power supply voltages to be provided to the image sensor. The higher power supply voltage may result in higher power consumption, may require specialized processes to manufacture, and/or may require mitigation of electrostatic discharge issues. Alternatively, rather than using higher power supply voltages to obtain the higher potentials for each successive node, the conversion gain between nodes may be reduced. Reducing the conversion gain, however, may result in more noise and less sensitivity in operation of the image sensor. 
     Some recent improvements in image sensor pixel design include additional nodes in image sensor pixels—for example, an image sensor formed by having two or more silicon chips stacked together. The interconnections between the silicon chips may require additional contacts and storage nodes for charge to be transferred between the silicon chips. The additional nodes exacerbate the need to increase the potential of subsequent storage nodes. 
     SUMMARY 
     One example of the present disclosure may take the form of an image sensor pixel. The image sensor pixel may include a first charge storage node and a second charge storage node. A transfer circuit may be coupled between the first and second charge storage nodes, with the transfer circuit having a first region proximate the first charge storage node and configured to have a first potential. The transfer circuit may also have a second region proximate the second charge storage node configured to have a second, higher potential. An input node may be configured to control the first and second potentials based on a transfer signal provided to the input node. 
     Another example of the present disclosure may take the form of an integrated circuit with a first node configured to store charge and a second node coupled to the first node and configured to receive charge from the first node. The integrated circuit may also include a transfer circuit coupling the first node to the second node. The transfer circuit may include a storage region with a first variable potential configured to be controlled by a transfer signal and a barrier with a second variable potential is also configured to be controlled by the transfer signal. 
     Another example of the present disclosure may take the form of a method of transferring charge from a first node with a first electric potential to a second node with a second electric potential in an image sensor pixel. The method may include increasing, responsive to a transfer signal, a third electric potential of a barrier proximate the first node such that the third electric potential is greater than the first electric potential. The method may further include increasing, responsive to the transfer signal, a fourth electric potential of a storage region coupled between the barrier and the second node such that the fourth electric potential is greater than the third electric potential. The method may also include decreasing, responsive to the transfer signal, the fourth electric potential of the storage region such that the fourth electric potential is less than the second electric potential. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a front perspective view of an electronic device including one or more cameras. 
         FIG. 1B  is a rear perspective view of the electronic device of  FIG. 1A . 
         FIG. 2  is a simplified block diagram of the electronic device of  FIG. 1A . 
         FIG. 3  is a simplified schematic cross-section view of the electronic device of  FIG. 1A  taken along line  3 - 3  in  FIG. 1A . 
         FIG. 4A  is a simplified diagram of an image sensor architecture for a camera of the electronic device. 
         FIG. 4B  is an enlarged view of a pixel architecture of  FIG. 4A  illustrating a single pixel. 
         FIG. 5  is a simplified schematic view of a pixel cell. 
         FIG. 6A  is a simplified schematic cross-section view of one embodiment of a portion of an image sensor pixel. 
         FIG. 6B  is a simplified potential profile of the image sensor pixel portion shown in  FIG. 6A . 
         FIG. 6C  is a simplified potential profile of the image sensor pixel portion shown in  FIG. 6A . 
         FIGS. 7A through 7G  are simplified potential profiles of the image sensor pixel portion shown in  FIG. 6A , illustrating its operation. 
         FIG. 8  is a timing diagram illustrating the operation of the image sensor pixel portion shown in  FIG. 6A . 
         FIG. 9  is a simplified potential profile of another image sensor pixel. 
         FIG. 10  is a simplified potential profile of another image sensor pixel. 
     
    
    
     SPECIFICATION 
     Overview 
     In some embodiments disclosed herein, apparatuses and methods for transferring charge from one node of an image sensor pixel to another node of the image sensor pixel are disclosed. Typically, charge transfer between nodes in image sensors is effectuated using nodes with different potentials separated by transfer gates. For charge to move from one node to another, the potential of the destination node needs to be greater than the potential of the source node. The transfer gate may be turned on, which causes the charge to “fall” to the node with a higher potential, much like water poured from a pitcher falls to a glass as a result of gravity acting on the water. For image sensors where charge needs to be serially transferred along more than 2 nodes, this operation can be challenging due to the need to continue increasing the potential for each subsequent node/region. 
     Therefore, in this disclosure, one transfer gate between two nodes is modified to create a mechanism to transfer charge from one node to another without needing a greatly increased potential in the destination node. One example where this may be particularly useful is for charge transfer among a plurality of nodes in a stacked-die image sensor, although the disclosure is not limited to this example. The modified transfer gate includes two differently doped regions—with the region closest to the destination node having a potential that is greater than the potential of the region closest the origination node, thus forming a variable barrier and a mini-storage region, both under the transfer gate. A virtual barrier is also formed between the transfer gate and the destination node. The potentials of the variable barrier and the mini-storage region are controlled in part by the voltage applied to the transfer gate. As the voltage applied to the transfer gate increases, the potentials of the barrier and the mini-storage region also increase so that some of the charge from the source node flows into the mini-storage region. Then, the voltage applied to the transfer gate is decreased so that the charge in the mini-storage region flows into the destination node. Several iterations may be required as the mini-well may only transfer a portion of the total charge in each cycle. 
     Turning now to the figures, an image sensor and an illustrative electronic device for incorporating the image sensor will be discussed in more detail.  FIG. 1A  is a front elevation view of an electronic device  100  including one or more image sensors.  FIG. 1B  is a rear elevation view of the electronic device  100 . The electronic device  100  may include any or all of a first camera  102 , a second camera  104 , an enclosure  106 , a display  110 , and an input/output button  108 . The electronic device  100  may be substantially any type of electronic or computing device, such as, but not limited to, a computer, a laptop, a tablet, a smart phone, a digital camera, a printer, a scanner, a copier, or the like. The electronic device  100  may also include one or more internal components (not shown) typical of a computing or electronic device, such as, but not limited to, one or more processors, memory components, network interfaces, and so on. Examples of such internal components will be discussed with respect to  FIG. 2 . 
     As shown in  FIG. 1 , the enclosure  106  may form an outer surface and protective case for the internal components of the electronic device  100  and may at least partially surround the display  110 . The enclosure  106  may be formed of one or more components operably connected together, such as a front piece and a back piece, or may be formed of a single piece operably connected to the display  110 . 
     The input member  108  (which may be a switch, button, capacitive sensor, or other input mechanism) allows a user to interact with the electronic device  100 . For example, the input member  108  may be a button or switch to alter the volume, return to a home screen, and the like. The electronic device  100  may include one or more input members  108  and/or output members, and each member may have a single input or output function or multiple input/output functions. 
     The display  110  may be operably connected to the electronic device  100  or may be communicatively coupled thereto. The display  110  may provide a visual output for the electronic device  100  and/or may function to receive user inputs to the electronic device  100 . For example, the display  110  may be a multi-touch capacitive sensing screen that may detect one or more user inputs. 
     The electronic device  100  may also include a number of internal components.  FIG. 2  is a simplified block diagram of the electronic device  100 . The electronic device  100  may also include one or more processors  114 , a storage or memory component  116 , an input/output interface  118 , a power source  120 , and one or more sensors  122 , each will be discussed in turn below. 
     The processor  114  may control operation of the electronic device  100 . The processor  114  may be in communication, either directly or indirectly, with substantially all of the components of the electronic device  100 . For example, one or more system buses  124  or other communication mechanisms may provide communication between the processor  114 , the cameras  102 ,  104 , the display  110 , the input member  108 , the sensors  122 , and so on. The processor  114  may be any electronic device cable of processing, receiving, and/or transmitting instructions. For example, the processor  114  may be a microprocessor or a microcomputer. As described herein, the term “processor” is meant to encompass a single processor or processing unit, multiple processors, or multiple processing units, or other suitably configured computing element(s). 
     The memory  116  may store electronic data that may be utilized by the electronic device  100 . For example, the memory  116  may store electrical data or content e.g., audio files, video files, document files, and so on, corresponding to various applications. The memory  116  may be, for example, non-volatile storage, a magnetic storage medium, optical storage medium, magneto-optical storage medium, read only memory, random access memory, erasable programmable memory, or flash memory. 
     The input/output interface  118  may receive data from a user or one or more other electronic devices. Additionally, the input/output interface  118  may facilitate transmission of data to a user or to other electronic devices. For example, in embodiments where the electronic device  100  is a phone, the input/output interface  118  may be used to receive data from a network, or may be used to send and transmit electronic signals via a wireless or wired connection (Internet, WiFi, Bluetooth, and Ethernet being a few examples). In some embodiments, the input/output interface  118  may support multiple network or communication mechanisms. For example, the network/communication interface  118  may pair with another device over a Bluetooth network to transfer signals to the other device, while simultaneously receiving data from a WiFi or other network. 
     The power source  120  may be substantially any device capable of providing energy to the electronic device  100 . For example, the power source  120  may be a battery, a connection cable that may be configured to connect the electronic device  100  to another power source such as a wall outlet, or the like. 
     The sensors  122  may include substantially any type of sensor. For example, the electronic device  100  may include one or more audio sensors (e.g., microphones), light sensors (e.g., ambient light sensors), gyroscopes, accelerometers, or the like. The sensors  122  may be used to provide data to the processor  114 , which may be used to enhance or vary functions of the electronic device  100 . 
     With reference again to  FIGS. 1A and 1B , the electronic device  100  may also include one or more cameras  102 ,  104  and optionally a flash  112  or light source for the cameras  102 ,  104 .  FIG. 3  is a simplified cross-section view of the first camera  102 , taken along line  3 - 3  in  FIG. 1A . Although  FIG. 3  illustrates the first camera  102 , it should be noted that the second camera  104  may be substantially similar to the first camera  102 . In some embodiments, one camera may include a global shutter configured image sensor and one camera may include a rolling shutter configured image sensor. In other examples, one camera may have an image sensor with a higher resolution than the other. Likewise, it should be appreciated that the structure shown in  FIG. 3  is but one possible structure for either of the first and second cameras. 
     With reference to  FIG. 3 , the cameras  102 ,  104  may include a lens  126  in optical communication with an image sensor  130 . The lens  126  may be operably connected to the enclosure  106  and positioned above the image sensor  130 . The lens  126  may direct or transmit light  128  within its field of view onto a photodiode (discussed in more detail below) of the image sensor  130 . The image sensor  130  may convert light  128  into electrical signals that may represent the light from the captured scene. In other words, the image sensor  130  captures the light  128  optically transmitted via the lens  126  into electrical signals. 
     Image Sensor Architecture 
     An illustrative architecture for the image sensor  130  will now be discussed in more detail.  FIG. 4A  is a simplified schematic of one possible architecture for the image sensor  130 .  FIG. 4B  is an enlarged view of a pixel of the pixel architecture of  FIG. 4A .  FIG. 5  is a simplified schematic view of the pixels  136  of  FIG. 4A . With reference to  FIGS. 4A-5 , the electronic device  100  may include an image processing component having a pixel architecture defining one or more pixels  136  and/or groups of pixel cells  138  (e.g., groups of pixels  136  grouped together to form a Bayer pixel or other set of pixels). The pixel architecture  134  may be in communication with a column select  140  through one or more column output lines  146  and a row select  144  through one or more row select lines  148 . 
     The row select  144  and/or the column select  140  may be in communication with an image processor  142 . The image processor  142  may process data from the pixels  136  and provide that data to the processor  114  and/or other components of the electronic device  100 . It should be noted that in some embodiments, the image processor  142  may be incorporated into the processor  114  or separate therefrom. The row select  144  may selectively activate a particular pixel  136  or group of pixels, such as all of the pixels  136  on a certain row. The column select  140  may selectively receive the data output from select pixels  136  or groups of pixels  136  (e.g., all of the pixels with a particular column). 
     With reference to the simplified schematic of one embodiment of a pixel  136  illustrated in  FIG. 5 , each pixel  136  may include a photodiode  154 . The photodiode  154  may be in optical communication with the lens  126  to receive light transmitted therethrough. The photodiode  154  may absorb light and convert the absorbed light into an electrical signal. The photodiode  154  may be an electron-based photodiode or a hole-based photodiode. Additionally, it should be noted that the term “photodiode,” as used herein, is meant to encompass substantially any type of photon or light detecting component, such as a photogate or other photo-sensitive region. 
     The photodiode  154  may be coupled to a first storage node SN 1   172  through a first transfer gate TX 1   170 . The first storage node  172  may in turn be coupled to a second storage node SN 2   176  through a second transfer gate TX 2   174 . The second storage node  176  may be coupled to a third storage node, such as a floating diffusion node FD  180  through a third transfer gate TX 3   178 . The storage nodes  172 ,  176 ,  180  may store charge from the photodiode  154 , and may in some examples be electrically and/or optically shielded so as to prevent any stray charge and/or light form corrupting the contents of the storage nodes  172 ,  176 ,  180 . The floating diffusion node  180  is provided as the gate input to a source follower gate SF  160 . A row select gate  162  and the source follower gate  160  may be coupled to a reference voltage source (Vdd) node  166 . The row select gate  162  may further be coupled to a row select line (e.g.,  148  in  FIG. 4B ) for the pixel  136 . The control circuitry for the pixel  136  may additionally or alternatively include one or more other gates. For example, an anti-blooming gate  173  may be coupled to the first storage node  172 . 
     In some embodiments, the photodiode  154  and the gates  170 ,  173 ,  174 ,  178 ,  156 ,  160 ,  162  of the pixel  136  may all be positioned on a single semiconductor chip or die, whereas in other embodiments, some components of the pixel  136  may be on one semiconductor chip with other components on a second chip. For example, the photodiode  154  may be on a first semiconductor chip, with the transfer gate  170  being a vertical transfer gate coupled between the first and second semiconductor chips. The first storage node  172  may be a stack contact on the second semiconductor chip to which the vertical transfer gate  170  is coupled. In these embodiments, the second storage node  176  may be a global shutter storage node, which enables global shutter readout of the pixels  136  on the image sensor. In general, the components of the pixel  136  may be spread across one or a plurality of chips. Several examples of image sensor architecture that may be used in connection with the present disclosure are described for example in co-pending application Ser. No. 13/756,459 entitled “Vertically Stacked Image Sensor” filed on Jan. 31, 2013, the entirety of which is hereby incorporated by reference for all purposes 
     In operation, when one of the cameras  102 ,  104  is actuated to capture an image, the anti-blooming gate  173  and the transfer gate  170  are turned on in order to deplete charge from the photodiode  154  and/or the storage node  172 . In some embodiments, the cameras  102 ,  104  may not include a shutter over the lens  126 , and so the image sensor  130  may be constantly exposed to light. In these embodiments, the photodiode  154  may need to be reset or depleted (e.g., via the anti-blooming gate  173 ) before a desired image is to be captured. 
     Once the photodiode  154  has been depleted, the transfer gate  170  may be turned off, thereby isolating the photodiode  154 . The photodiode  154  may then begin collecting light transmitted to the image sensor  130  from the lens  126  and integrating charge derived therefrom. As the photodiode  154  receives light, it starts to collect charge generated by incident photons. The charge remains in the photodiode  154  because the transfer gate  170  connecting the photodiode  154  to the first storage node  172  is turned off. While the photodiode  154  integrates charge, the anti-blooming gate  173  may remain on in order to reset the storage node  172  and/or in order to prevent blooming from the photodiode  154 . 
     Once integration is nearly complete, the anti-blooming gate  173  may be turned off so as to isolate the first storage node  172  (as the second transfer gate  174  is also turned off). The first transfer gate  170  may then be pulsed to a high voltage to transfer accumulated charge from the photodiode  154  to the first storage node  172 . The second storage node  176  may also be reset by turning on the third transfer gate  178  and the reset gate  156  to deplete the second storage node  176 . 
     After the charge has been transferred to the first storage node  172  and the second storage node  176  has been reset, the charge from the first storage node  172  may be transferred to the second storage node  176  through the second transfer gate  174 . The charge may be transferred to the second storage node  176  through the second transfer gate  174  by several short pulses of the transfer signal TX 2  provided to the second transfer gate, as described in more detail below. The charge from the photodiode  154  may be held at the second storage node  176  until the pixel  136  is ready to be read out. In the global shutter operation, each row within the pixel architecture  134  may be reset and exposed (i.e., integrate charge generated by light transmitted through the lens  126 ) at substantially the same time. 
     Once the charge has been transferred to the second storage node  176  and is ready to be read out, the reset gate  156  may be turned on to reset the floating diffusion node  180 . The third transfer gate  178  may then be turned on and the charge from the second storage node  176  may be transmitted to the floating diffusion node  180 . Once the charge is transferred to the floating diffusion node  180 , the row select gate  162  may be activated, and the SF gate  160  amplifies the charge in the floating diffusion node  180  and provides a signal indicative thereof through the row select gate  162 . 
     Charge Transfer Circuit 
       FIG. 6A  illustrates one embodiment of a charge transfer circuit  182  that may be used in the pixel  136 , and  FIGS. 6B and 6C  illustrate simplified electric potential diagrams for the charge transfer circuit  182  when different transfer signals are provided to the charge transfer circuit  182 . Although the charge transfer circuit  182  is illustrated in  FIG. 6A  and described herein as an example of how the second transfer gate  174  may be implemented, it will be understood that the charge transfer circuit  182  may alternatively or additionally be used to transfer charge between any two nodes. For example, the charge transfer circuit  182  illustrated in  FIG. 6A  may be used as the first transfer gate  170 , the second transfer gate  174 , and/or the third transfer gate  178 , or in any other region of the image sensor  130  where charge needs to be transferred between two nodes. In some examples, multiple charge transfer circuits  182  may be used for a plurality of nodes in series to transfer charge therebetween, whereas in other embodiments, a single charge transfer circuit  182  may be used between a single pair of nodes. 
     Referring to  FIG. 6A , the charge transfer circuit  182  may be coupled between first and second charge storage nodes  172 ,  176 . In one embodiment, the two charge storage nodes  172 ,  176  may be n-doped regions in a p-type substrate or a p-well of a semiconductor chip. Of course, in other embodiments, different types of doping or substrate may be used. 
     The two charge storage nodes  172 ,  176  may have similar or different potentials. As illustrated in  FIGS. 6B and 6C , the electric potential of the second storage node  176  may be slightly greater than the electric potential of the first charge storage node  172 , though it may not be so much greater than the electric potential of the first charge storage node  172  that it would be able to store charge transferred from the first charge storage node  172  through a conventional transistor without sharing the charge with the first charge storage node  172 . In other embodiments, however, the electric potential of the second storage node  176  may be the same as the electric potential of the first storage node  172  (see  FIG. 9 ), or in some embodiments, the electric potential of the second charge storage node  176  may be less than the electric potential of the first charge storage node  172  (see  FIG. 10 ). 
     The charge transfer circuit  182  is partitioned into two parts, a first region  184  and a second region  186 . The first region  184  may be configured to have a first variable potential, and may be referred to as a variable barrier. The second region  186  may be configured to have a second variable potential, and may be referred to as a storage region. The variable potentials of both the first and second regions  184 ,  186  may be controlled by a transfer signal provided to the charge transfer circuit  182 , for example, a transfer signal TX 2  that is provided to the input node  174  or transfer gate  174  of the charge transfer circuit  182 . 
     As illustrated in  FIG. 6A , the second region  186  may be laterally offset from the first region  184 , with the first region  184  being proximate one charge storage node  172 , and the second region  186  being proximate the other charge storage node  176 . The first and second regions  184 ,  186  may thus not overlap in depth beneath the transfer gate  174  in some embodiments. In other embodiments, however (not shown), the first and second regions  184 ,  186  may be offset from each other in depth in a silicon die, in which case each region  184 ,  186  may or may not extend across the entire width underneath the transfer gate  174 . 
     Still referring to  FIG. 6A , in the example where the charge transfer circuit  182  is formed in a p-well with the nodes  172 ,  176  being n-doped, the first region  184  may not be doped other than the p-well doping. This may cause the first region  184  to have a relatively low potential during operation of the pixel  136 ; hence the first region  184  may be referred to as a barrier. The second region  186 , however, may be lightly n-doped, such that the second region  186  has a higher potential than the first region  184  during operation. Because the second region  186  has a higher potential than the first region, and because the second region  186  is positioned between the first region  184  and a virtual barrier  188  described in more detail below, the second region  186  may form a storage region capable of holding charge. The capacity of the second region  186  to store charge, however, may be less than the capacity of either of the nodes  172 ,  176  in some embodiments, and thus, as described in more detail below, the second region  186  may need to be used a plurality of times to transfer charge between the nodes  172 ,  176 . In other words, the junction between the first and second regions  184 ,  186  may form a p-n junction, thus providing the capacity to store charge in the second region  186 . In other embodiments, of course, other capacitive structures may be used to store charge in the second region  186 . 
     As mentioned above, the charge transfer circuit  182  also includes an input node  174 , which may be for example a transistor gate. As illustrated in  FIG. 6A , the input node  174  may be a polysilicon-oxide gate structure. In other examples, the input node  174  may be a metal-oxide gate structure, or any other type of input node. Referring to the example shown in  FIG. 6A , the input node  174 , together with the first and second regions  184 ,  186 , may act as a modified field-effect transistor (FET). In other examples, other types of transistors or transfer circuits may be used, such as a bipolar junction transistor. Also, referring to  FIG. 6A , a single input node  174  may be used in the charge transfer circuit  182 , with the input node  174  partitioned into two portions because of the different characteristics of the first and second regions  184 ,  186 . For example, the input node  174  illustrated in  FIG. 6A  is a modified FET gate with two regions underneath due to the different doping profiles of the first and second regions  184 ,  186  of the charge transfer circuit  182 . That single gate  174  may be used to change the electric potential of both the first and second regions  184 ,  186  responsive to a single transfer signal TX 2 . In this example, a relative difference between the variable electric potential of the first and second regions  184 ,  186  may be constant across a plurality of different transfer signal TX 2  voltages. In other examples, however, a plurality of different input nodes may be used—for example, one gate may be used to control the electric potential of the first region  184 , with a separate gate used to control the electric potential of the second region  186 . In either event, the input node  174  (or input nodes) controls the variable potentials of the first and second regions  184 ,  186 . 
     Still with reference to  FIG. 6A , and as mentioned above, a virtual barrier  188  may be formed as part of the charge transfer circuit  182 . The virtual barrier  188  may be formed by extending the doping of the second region  186  beyond the transfer gate  174  and underneath a pinning layer  190 . In other words, the virtual barrier  188  and the second, storage region  186  may together form a commonly doped region of the charge transfer circuit  182 , with the storage region  186  formed where the transfer gate  174  is positioned over the commonly doped region and the virtual barrier  188  formed where a pinned layer is positioned over the commonly doped region. In addition to facilitating the use of the second region  186  as a storage region as described above, the virtual barrier  188  may in some examples help prevent charge that is transferred to node  176  from returning to the source node  172  from which it came because the electric potential of the virtual barrier  188  is less than the electric potential of the destination node  176 . This may allow the full capacity of the node  176  to be used (e.g., not just the capacity of the node  176  above the potential of the source node  172 ). In effect, the virtual barrier  188 , together with the charge transfer circuit  182 , may allow charge to be transferred to the node  176  irrespective of the potential of the node  172 . 
     Referring now to  FIGS. 6B and 6C  in particular, simplified electric potential diagrams are shown for the charge transfer circuit  182 .  FIG. 6B  illustrates the electric potential diagram for the charge transfer circuit  182  when a low voltage is provided to the input node  174 , and  FIG. 6C  illustrates the electric potential for the charge transfer circuit  182  when a high voltage is provided to the input node  174 . In both  FIGS. 6B and 6C , the electric potential of the first and second charge storage nodes  172 ,  176 , and the electric potential of the virtual barrier  188  may be fixed and may not change responsive to different transfer signals provided to the input node  174 . However, the electric potentials of the first and second regions  184 ,  186  do change responsive to different transfer signals provided to the input node. When a low voltage is provided to the input node  174 , as in  FIG. 6B , the storage region  186  may have an electric potential that is slightly less than the electric potential of the virtual barrier  188  (which in turn is less than the electric potential of the second or destination node  176 ). The low voltage provided to the input node  174  also causes the electric potential of the first region  184  to decrease such that it is less than the electric potential of the first or source node  172 . As mentioned above, because of the different doping profiles of the first and second regions  184 ,  186  of the charge transfer circuit  182 , the electric potential of the second/storage region  186  is greater than the electric potential of the first/barrier region  184 . 
     When a higher voltage is provided to the input node  174 , as in  FIG. 6C , the storage region  186  may have an electric potential that is greater than the electric potential of the virtual barrier  188 , and which is also greater than the electric potential of the first region  184 , thus forming a mini-well that can store a portion of charge. The low voltage provided to the input node  174  also causes the electric potential of the first region  184  to be increased above the electric potential of the first charge storage node  172  so that charge can flow into the storage region  186 , as described in more detail below. 
     Although  FIGS. 6B and 6C  have illustrated one example of electric potential profiles, it will be understood that the profiles may or may not be to scale, and that the precise electric potential of any given region in an image sensor  130  will depend on the physical characteristics of that region as well as voltages or other signals that bias or deplete those regions. 
     Referring now to the series of illustrations in  FIGS. 7A through 7G  together with the timing diagram in  FIG. 8  and the schematic of  FIG. 5 , the operation of one embodiment of the charge transfer circuit  182  will now be described for a pixel  136 , wherein the charge transfer circuit of  FIG. 6A  is implemented as the second transfer gate  174  between the first and second storage nodes  172 ,  176 . 
     As described above, to begin, the anti-blooming gate  173  and the first transfer gate  170  may be turned on in order to deplete charge from the photodiode  154  and/or the storage node  172 , as illustrated at times t 1  and t 2 , respectively. Once the charge from the photodiode  154  has been depleted, the first transfer gate  170  may be turned off at time t 3 , thereby isolating the photodiode. The photodiode  154  may then begin collecting light transmitted to the image sensor  130  from the lens  126  and integrating charge derived therefrom during its integration time  820   t . While the photodiode  154  integrates charge, the anti-blooming gate  173  may remain on in order to reset the storage node  172  and/or in order to prevent blooming from the photodiode  154 . 
     Once integration is nearly complete, the anti-blooming gate  173  may be turned off at time t 4  so as to isolate the first storage node  172 . The first transfer gate  170  may then be pulsed to a high voltage between times t 5  and t 6  to transfer accumulated charge from the photodiode  154  to the first storage node  172 , as illustrated in the potential profile in  FIG. 7A . Also, at time t 5 , the third transfer gate  178  and the reset gate  156  may be turned on to reset the second storage node  176 , after which the third transfer gate  178  and the reset gate  156  may again be turned off to isolate the second storage node  176 . 
     After the charge has been transferred to the first storage node  172  and the second storage node  176  has been reset and isolated, the charge from the first storage node  172  may be transferred to the second storage node  176  through the second transfer gate  174  by a series of pulses of the second transfer signal TX 2  provided to the second transfer gate  174 . At time t 6 , the potentials of the first and second regions  184 ,  186  may be increased responsive to the positive voltage TX 2  provided to the input node  174 , and, with reference to  FIG. 7B , the increase in potential may cause charge from the first storage node  172  to be transferred (e.g., may “fall”) to the storage region  186  because the electric potential of the first and second regions is increased to be greater than the electric potential of the first storage node  172 . When the voltage of the second transfer signal TX 2  is decreased at time t 7 , with reference to  FIGS. 7C and 7D , the potentials of the first and second regions  184 ,  186  begin to decrease ( FIG. 7C  illustrates the potentials of the first and second regions  184 ,  186  when the voltage of the second transfer signal TX 2  is half decreased, and  FIG. 7D  illustrates the potentials of the first and second regions  184 ,  186  when the voltage of the second transfer signal TX 2  is completely decreased). In general, the electric potentials of the first and second regions  184 ,  186  may increase and/or decrease at substantially the same time in some embodiments, and may increase and/or decrease responsive to a common transfer signal provided to a single input node  174  of the charge transfer circuit  182 , or may increase and/or decrease responsive to a plurality of transfer signals provided to the charge transfer circuit  182 . 
     When the potentials of the first and second regions  184 ,  186  decrease—particularly when the potential of the second region  186  decreases below the potential of the virtual barrier  188  and/or the potential of the second node  176 , as illustrated in  FIG. 7D —the charge stored in the second region  186  is transferred over the virtual barrier  188  and into the second charge storage node  176 . Once the charge is transferred into the second charge storage node  176 , the virtual barrier  188  may prevent charge from returning to the second storage region  186  and/or to the first node  172 . 
       FIGS. 7E through 7G  are similar to  FIGS. 7B through 7D , except that some charge has already been transferred to the second node  176  in  FIG. 7E . As described above, the capacity of the second region  186  to store charge may be limited such that multiple iterations of pulsing the transfer signal to the input node  174  may be required in some embodiments in order to fully transfer charge from the first node  172  to the second node  176 . Therefore, the operations of increasing and decreasing the potentials of the first and second regions  184 ,  186  to attract charge into the second region  186 , and to then dump the charge into the second node  176 , may be repeated for a plurality of pulses. This pulsing of the transfer signal may be referred to as pumping, and, is somewhat similar to sending a bucket down into a well and then bringing it back up to draw up water out of the well. 
     Still referring to  FIG. 8 , following transfer of the charge to the second charge storage node  176 , the reset gate  156  may be turned on at time t 8  to reset the floating diffusion node  180 . The third transfer gate  178  may then be turned on at time t 9  and the charge from the second storage node  176  may be transferred to the floating diffusion node  180 . Once the charge is stored in the floating diffusion node  180 , the row select gate  162  may be activated, and the SF gate  160  amplifies the charge in the floating diffusion node  180  and provides a signal indicative thereof through the row select gate  162 . 
     In this manner, the embodiments of the charge transfer circuit  182  described herein do not require the electric potential of the second charge transfer node  176  to be drastically greater than the electric potential of the first charge transfer node  172 , and indeed, it may even be less than the electric potential of the first charge transfer node  172 . Also, by using embodiments of the charge transfer circuit  182  described herein, the entire capacity of the second or destination charge storage node  176  can be used, rather than only the capacity beyond the potential of the first or source charge storage node  172 . 
     Conclusion 
     The foregoing description has broad application. For example, while examples disclosed herein may focus on particular architectures of image sensors (e.g., photodiode, global shutter, CMOS sensors, etc.), it should be appreciated that the concepts disclosed herein may equally apply to substantially any other type of image sensor with or without appropriate modifications as would be appreciated by one skilled in the art of image sensors. Moreover, although certain examples have been described with reference to particular dopants (e.g., nodes  172  and  176  in  FIG. 6A  are doped with n-type dopant in a p-well or on a p-substrate), it will be understood that other dopants are also within the scope of this disclosure and the appended claims. For example, referring back to  FIG. 6A , the nodes  172 ,  176  may be doped with p-type dopant in an n-type substrate. 
     Furthermore, the various embodiments described herein may find application in many different implementations. Accordingly, the discussion of any embodiment is meant only to be exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples.

Metadata:
Filing Date: 20170821
Publication Date: 20210309
Grant Date: 20210309
Priority Date: 20130306
Inventors: LI, XIANGLI
FAN, XIAOFENG
WAN, CHUNG CHUN
Assignee: APPLE INC
CPC Classifications: [{"code": "H04N25/587", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N25/587", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N25/79", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N25/771", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N25/75", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N25/771", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N25/79", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/80377", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/80377", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/803", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10F39/803", "inventive": true, "first": true, "tree": "[]"}, {"code": "H04N25/77", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N5/378", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/14616", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N5/35572", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N5/37452", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N5/379", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/14609", "inventive": true, "first": true, "tree": "[]"}, {"code": "H04N25/78", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 50272713