PATENT DOCUMENT

Publication Number: US-12197020-B2
Application Number: US-202218079672-A
Country: US
Kind Code: B2

Title: Photonics integrated circuit architecture

Abstract:
This disclosure relates to the layout of optical components included in a photonics integrated circuit (PIC) and the routing of optical traces between the optical components. The optical components can include light sources, a detector array, and a combiner. The optical components can be located in different regions of a substrate of the PIC, where the regions may include one or more types of active optical components, but also may exclude other types of active optical components. The optical traces can include a first plurality of optical traces for routing signals between light sources and a detector array, where the first plurality of optical traces can be located in an outer region of the substrate. The optical traces can also include a second plurality of optical traces for routing signals between the light sources and a combiner, where the second plurality of optical traces can be located in regions between banks of the light sources.

Claims:
What is claimed is: 
     
       1. A photonics integrated chip comprising:
 a plurality of light source banks; 
 a combiner; and 
 a detector array; wherein: 
 each light source bank of the plurality of light source banks comprises:
 a set of light sources; 
 a first optical trace connected to the combiner; 
 a second optical trace connected to the detector array; and 
 a crossing at which the first trace of the light source bank crosses the second trace. 
 
 
     
     
       2. The photonics integrated chip of  claim 1 , wherein:
 the combiner combines inputs received from the first optical traces of the plurality of light source banks and outputs a combined signal. 
 
     
     
       3. The photonics integrated chip of  claim 2 , comprising a splitter positioned to receive the combined signal and configured to split the combined signal into a plurality of signals. 
     
     
       4. The photonics integrated chip of  claim 3 , comprising a plurality of emission regions from which the plurality of signals exit the photonic integrated chip. 
     
     
       5. The photonics integrated chip of  claim 4 , wherein:
 the plurality of emission regions comprises a plurality of outcouplers. 
 
     
     
       6. The photonics integrated chip of  claim 4 , comprising:
 a controller that receives detector signals from the detector array and monitors and controls a frequency of light emitted the plurality of emission regions. 
 
     
     
       7. The photonics integrated chip of  claim 1 , wherein:
 each light source bank of the plurality of light source banks comprises a third optical trace connected to the detector array. 
 
     
     
       8. The photonics integrated chip of  claim 7 , wherein:
 each light source bank of the plurality of light source banks comprises a photonic component that is configured to receive signals from the set of light sources and to output a corresponding signal output to each of the first, second, and third trace of the light source bank. 
 
     
     
       9. The photonics integrated chip of  claim 8 , wherein:
 the photonic component is an arrayed waveguide grating. 
 
     
     
       10. A photonics integrated chip comprising:
 a plurality of light source banks; 
 a combiner; and 
 a detector array; wherein: 
 each light source bank of the plurality of light source banks comprises:
 a plurality of light sources; 
 a first optical trace connected to the combiner; 
 a second optical trace connected to the detector array; and 
 a multiplexer that connects the plurality of light sources to each of the first optical trace and the second optical trace. 
 
 
     
     
       11. The photonics integrated chip of  claim 10 , wherein:
 the combiner combines inputs received from the first optical traces of the plurality of light source banks and outputs a combined signal. 
 
     
     
       12. The photonics integrated chip of  claim 11 , comprising a splitter positioned to receive the combined signal and configured to split the combined signal into a plurality of signals. 
     
     
       13. The photonics integrated chip of  claim 12 , comprising a plurality of emission regions from which the plurality of signals exit the photonic integrated chip. 
     
     
       14. The photonics integrated chip of  claim 13 , wherein:
 the plurality of emission regions comprises a plurality of outcouplers.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/582,838, filed Sep. 25, 2019, which claims the benefit under 35 USC 119(e) of U.S. Patent Application No. 62/738,712, filed Sep. 28, 2018, entitled “Photonics Integrated Circuit (PIC) Architecture,” the contents of which are herein incorporated by reference in their entirety for all purposes. 
    
    
     FIELD 
     This relates generally to an architecture for a plurality of optical components included in a photonics integrated circuit. 
     BACKGROUND 
     Devices can be useful for many applications, such as trace gas detection, environmental monitoring, biomedical diagnostics, telecommunications, and industrial process controls. Some applications may benefit from having a large spectral range with multiple integrated light sources that can stabilize with high precision. These applications may make use of a compact, portable electronic device, which may benefit from densely-packed optical components and a floorplan that reduces optical losses. 
     SUMMARY 
     This disclosure relates to the layout of a plurality of optical components included in a photonics integrated circuit (PIC) and the routing of optical traces between the plurality of optical components. The plurality of optical components can include a plurality of light sources, a detector array, and a combiner. The plurality of optical components can be located in different regions of a substrate of the PIC, where the regions may include one or more types of active optical components, but also may exclude other types of active optical components. The optical traces can include a first plurality of optical traces for routing signals between a plurality of light sources and a detector array, where the first plurality of optical traces can be located in an outer region of the substrate. The optical traces can also include a second plurality of optical traces for routing signals between the plurality of light sources and a combiner, where the second plurality of optical traces can be located in regions between banks of the plurality of light sources. Examples of the disclosure also include the PIC including a plurality of multi-taps for crossing signals on the first plurality of optical traces and signals on the second plurality of optical traces for matching and reduction of optical losses. 
     A photonics integrated chip may include: a plurality of active optical components integrated into a substrate of the photonics integrated chip, the plurality of active optical components including: a plurality of light sources located in a first region and a second region of the substrate, a detector array located in a third region of the substrate, and a combiner located in a fourth region of the substrate; a first plurality of optical traces for routing the plurality of light sources to the detector array, the first plurality of optical traces located in a fifth region of the substrate; and a second plurality of optical traces for routing the plurality of light sources to the combiner, the second plurality of optical traces located in a sixth region of the substrate. Additionally or alternatively, in some examples, the photonics integrated chip may further include: a plurality of light source banks, where the plurality of light sources is arranged as sets of light sources. 
     Additionally or alternatively, in some examples, the plurality of light source banks includes a first light source bank, the first light source bank including light sources that emit light having different wavelengths relative to the other light sources in the first light source bank. Additionally or alternatively, in some examples, the plurality of light source banks includes a plurality of photonics components, the plurality of photonics components: receiving and combining a plurality of signals from the plurality of light source banks; selecting from the combined plurality of signals, and outputting the selected signal along the second plurality of optical traces; and outputting non-selected signals along the first plurality of optical traces. 
     Additionally or alternatively, in some examples, the combiner: receives a plurality of signals from the plurality of photonics components along the second plurality of optical traces, and combines the received plurality of signals and outputs the combined signal. Additionally or alternatively, in some examples, each of the non-selected signals output from the same photonics component includes different wavelengths. Additionally or alternatively, in some examples, the non-selected signals are tapped portions of the fundamental modes of light from the combined plurality of signals. Additionally or alternatively, in some examples, the detector array includes a plurality of detectors, each detector receiving the non-selected signals and outputting detector signals, the photonics integrated chip may further include: a controller that receives the detector signals and monitors and determines a locked wavelength based on an intersection wavelength of the detector signals. 
     Additionally or alternatively, in some examples, the sixth region includes regions of the substrate between the plurality of light source banks. Additionally or alternatively, in some examples, the detector array includes a plurality of detectors, each detector connected to a set of the plurality of light sources, the set including light sources unique from other light sources included in other sets, each detector monitoring a locked wavelength of the set. Additionally or alternatively, in some examples, each of the plurality of light sources is a laser bar. Additionally or alternatively, in some examples, the first region, the second region, the third region, and the fourth region each exclude different respective types of active optical components. Additionally or alternatively, in some examples, the third region is located between the first region and the second region. Additionally or alternatively, in some examples, the fifth region includes an outside region of the substrate, the outside region located closer to edges of the substrate than the plurality of active optical components. Additionally or alternatively, in some examples, the photonics integrated chip may further include: a plurality of multi-taps connected to the plurality of light sources and the detector array, each multi-tap including a crossing to allow one of the first plurality of optical traces to cross one of the second plurality of routing traces. 
     A method for operating a device is disclosed. The method can include: generating light using one or more laser bars; combining the generated light using a plurality of photonics components; tapping first portions of the combined generated light using the plurality of photonics components; transmitting the tapped first portions along a first plurality of optical traces; combining and multiplexing second portions of the generated light using the plurality of photonics components; transmitting the combined and multiplexed second portions along a second plurality of optical traces; detecting the first portions of the generated light using a plurality of detectors; and combining the second portions using a combiner, where the one or more laser bars, the plurality of photonics components, the first plurality of optical traces, the second plurality of optical traces, the plurality of detectors, and the combiner are included in the same photonics integrated chip of the device. 
     Additionally or alternatively, in some examples, the method may further include: crossing the tapped first portions and the combined and multiplexed second portions using a plurality of multi-taps, the plurality of multi-taps included in the photonics integrated chip. Additionally or alternatively, in some examples, the transmission of the tapped first portions along the first plurality of optical traces includes transmitting signals along outer regions of the photonics integrated chip. Additionally or alternatively, in some examples, the transmission of the combined and multiplexed second portions along the second plurality of traces includes transmitting signals along regions between banks of the one or more laser bars. Additionally or alternatively, in some examples, the detection of the first portions of the generated light using the plurality of detectors includes: receiving a plurality of signals along the first plurality of optical traces; determining an intersection of wavelengths of the generated light in the plurality of signals; and determining a locked wavelength based on the intersection of wavelengths. 
     Also disclosed herein is a plurality of photonics components that can be multi-purpose components. The plurality of photonics components can combine and multiplex signals received from the plurality of light sources. The plurality of photonics components can also tap portions of the light generated from the plurality of light sources. The tapped portions can be detected by a plurality of light detectors included in the detector array. A controller can determine an intersection of the detected tapped portions and can determine and control a locked wavelength based on the intersection for frequency stabilization. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a cross-sectional view of a portion of an example device; 
         FIG.  2 A  illustrates a floorplan of optical components of an example PIC architecture; 
         FIG.  2 B  illustrates a block diagram of a portion of an example PIC architecture included in a device; 
         FIG.  3    illustrates a block diagram of an example photonics component; 
         FIG.  4 A  illustrates a floorplan of optical components and optical traces of an example PIC; 
         FIG.  4 B  illustrates a top view of an example multi-tap component; and 
         FIG.  5    illustrates an example operation of a device including a PIC. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description of examples, reference is made to the accompanying drawings in which it is shown by way of illustration specific examples that can be practiced. It is to be understood that other examples can be used and structural changes can be made without departing from the scope of the various examples. One or more components of the same type can be collectively referred to by a three-digit reference number (e.g., light source  202 ), where individual components of that type can be referred to by a three-digital reference number followed by a letter (e.g., light source  202 A). 
     Various techniques and process flow steps will be described in detail with reference to examples as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects and/or features described or referenced herein. It will be apparent, however, to one skilled in the art, that one or more aspects and/or features described or referenced herein may be practiced without some or all of these specific details. In other instances, well-known process steps and/or structures have not been described in detail in order to not obscure some of the aspects and/or features described or referenced herein. 
     Further, although process steps or method steps can be described in a sequential order, such processes and methods can be configured to work in any suitable order. In other words, any sequence or order of steps that can be described in the disclosure does not, in and of itself, indicate a requirement that the steps be performed in that order. Further, some steps may be performed simultaneously despite being described or implied as occurring non-simultaneously (e.g., because one step is described after the other step). Moreover, the illustration of a process by its description in a drawing does not imply that the illustrated process is exclusive of other variations and modification thereto, does not imply that the illustrated process or any of its steps are necessary to one or more of the examples, and does not imply that the illustrated process is preferred. 
     This disclosure relates to the layout of a plurality of optical components included in a photonics integrated circuit (PIC) and the routing of optical traces between the plurality of optical components. The plurality of optical components can include a plurality of light sources, a detector array, and a combiner. The plurality of optical components can be located in different regions of a substrate of the PIC, where the regions may include one or more types of active optical components, but also may exclude other types of active optical components. In some examples, the active optical components may include, but are not limited to lasers, detectors, variable optical attenuators, phase shifters, polarization controllers, optical amplifiers, and so forth. The optical traces can include a first plurality of optical traces for routing signals between the plurality of light sources and the detector array, where the first plurality of optical traces can be located in the outer region of the substrate. The optical traces can also include a second plurality of optical traces for routing signals between the plurality of light sources and the combiner, where the second plurality of optical traces can be located in regions between banks of the plurality of light sources. Examples of the disclosure also include the PIC including a plurality of multi-taps for crossing signals on the first plurality of optical traces and signals on the second plurality of optical traces for matching and reduction of optical losses. 
     Also disclosed herein is a plurality of photonics components that can be multi-purpose components. The plurality of photonics components can combine and multiplex signals received from the plurality of light sources. The plurality of photonics components can also tap portions of the light generated from the plurality of light sources. The tapped portions can be detected by a plurality of light detectors included in the detector array. A controller can determine an intersection of the detected tapped portions and can monitor and determine a locked wavelength and in some examples can determine an adjustment (which may be transmitted to the plurality of light sources), based on the intersection for frequency stabilization. 
     Representative applications of methods and apparatus according to the present disclosure are described in this section. These examples are being provided solely to add context and aid in the understanding of the described examples. It will thus be apparent to one skilled in the art that the described examples may be practiced without some or all of the specific details. Other applications are possible, such that the following examples should not be taken as limiting. 
     Overview of an Example Device 
       FIG.  1    illustrates a cross-sectional view of a portion of an example device. The device  100  can include a plurality of components. The term “device” as used herein can refer to a single standalone component that can operate alone for a given function, or can refer to a system including multiple components that operate together to achieve the same functions. The device  100  can include optical components and/or active optical components such as a plurality of light sources  102 , a detector  130 , and an optics unit  129 . 
     The light sources  102  can be configured to emit light  141 . The light sources  102  can be any type of source capable of generating light including, but not limited to, a laser, a light emitting diode (LED), an organic light emitting diode (OLED), an electroluminescent (EL) source, a quantum dot (QD) light source, a super-luminescent diode, a super-continuum source, a fiber-based source, or any combination of one or more of these sources, and so forth. In some examples, one or more light sources  102  can be capable of emitting a plurality of wavelengths (e.g., a range of wavelengths) of light. In some examples, one or more of the light sources  102  can emit a different wavelength range of light (e.g., different colors in the spectrum) than the other light sources  102 . 
     Light from the light sources  102  can be combined using one or more integrated tuning elements  104 , optical traces (not shown), one or more multiplexers (not shown), and/or other optical components and/or active optical components. In some examples, the integrated tuning elements  104 , the optical traces, and the multiplexer(s) can be disposed on a substrate  142 . The substrate  142  can be included in a single optical platform, such as an integrated silicon photonics chip. An integrated silicon photonics chip can also be known as a photonics integrated chip (PIC). The device  100  can also include a thermal management unit  101  for controlling (e.g., heating or cooling, including stabilization) the temperature of the light sources  102 . In some examples, the thermal management unit  101  may be co-packaged with the substrate  142 . One or more outcouplers  109  can be coupled to the integrated tuning elements  104 , optical traces, and/or multiplexers. The outcouplers  109  can be configured to focus, collect, collimate, and/or condition (e.g., shape) an incident light beam to form light  150 , which can be directed towards the system interface (e.g., the external housing of the device  100 ). 
     Light can be light emitted from the light sources  102 , collimated by the outcouplers  109 , and in some examples, transmitted through the optics unit  129  (not illustrated in  FIG.  1   ). At least a portion of light  150  can return to the device  100 . The return light can be transmitted through the optics unit  129  and can be incident on the detector  130 . In some examples, the return light may transmit through different optical components which may be included in the optics unit  129 , than light  150  due to the different optical paths of the return light and the light  150 . 
     Some applications may benefit from having a large spectral range with multiple integrated light sources that can stabilize with high precision. These applications may make use of a compact, portable electronic device, which may benefit from densely-packed optical components and a floorplan that reduces optical losses. 
     Example Floorplan 
       FIG.  2 A  illustrates a floorplan of optical components of an example PIC architecture. The PIC  200  can include a plurality of light source banks  203 , a detector array  230 , and a combiner  207  located on a substrate  242 . The plurality of light source banks  203  can be located in multiple regions of the device. For example, the light source banks  203 A- 203 E can be located in a first region  221 A, such as the left region, of the PIC  200 . The light source banks  203 F- 203 J can be located in a second region  221 B, such as the right region of the PIC  200 . The detector array  230  can be located in a third region  223 , such as the central region of the PIC  200  between the light source banks  203 A- 203 E and the light source banks  203 F- 203 J. In some examples, the detector array  230  can be located at the bottom region of the PIC  200 . 
     The combiner  207  can also be located between the light source banks  203 A- 203 E and the light source banks  203 F- 203 J. The combiner  207  can be located in a fourth region  225  above region  223  (which may include the detector array  230 ), for example. In some examples, the PIC  200  may also include a region  211  for other components or for other purposes including but not limited to, radiation and or electronically controlled optical amplitude, phase and polarization, or any combination thereof, and so forth. 
     In some examples, the light source banks  203 , the detector array  230 , and the combiner  207  may be limited to being located in their respective regions, where one or more types of active optical components may be included in a region, while other active optical components may not be included in the same region. In this manner, all of the detectors, for example, may be located in a common region. An “active optical component” refers to an optical component that changes the properties of light using an electrical means. For example, a light source, a detector, and a combiner are active optical components, whereas optical routing traces may not be active optical components. 
     Examples of the disclosure can include a floorplan where regions are respectively arranged differently from the floorplan illustrated in the figure. For example, the light source banks  203  can all be located on one side (e.g., the left side, the right side, etc.), and the combiner  207  can be located on the other side from the light source banks  203 . As another example, the light source banks  203 A- 203 E can be located on top, and the detector array  230  can be located in the left region. The components can be placed such that optical losses from the light source banks  203  to the emission regions are minimized and matched, and optical losses from the light source banks  203  to the detectors in the detector array  230  are minimized and matched. In some examples, the PIC  200  may include one or more emission regions where light may exit the PIC  200  perpendicular to the PIC substrate or in-plane from the edge of the PIC substrate. For example, a fiber optic array may be coupled to the output of combiner  207 , which may be an emission region. In some examples, reducing optical losses may be achieved via the placement and configuration of the optical routing traces, as discussed below. 
       FIG.  2 B  illustrates a block diagram of a portion of an example PIC architecture included in a device. The PIC  200  can include a plurality of light source banks  203 , which can include a plurality of light sources  202 . For example, the light source bank  203 A can include the light source  202 A and the light source  202 B, and the light source bank  203 N can include the light source  202 M and the light source  202 N. A light source  202  can include a laser bar, for example. In some instances, a light source  202  can generate light having multiple wavelengths. The plurality of light sources  202  can be associated with different sets  213  of light sources  202 . For example, the light source  202 A and the light source  202 B can be associated with the set  213 A, and the light source  202 M and the light source  202 N can be associated with the set  213 N. The light sources  202  in a given set  213  may emit light  248  having different wavelengths relative to the light emitted by the other light sources in the same set, for example. 
     A light source bank  203  can also include a photonics component  210  that can facilitate in the measurement of the optical properties of light  248  to ensure that the light sources  202  are tuned to a targeted wavelength range and/or have a certain amount of wavelength stability (e.g., frequency stability). In some systems, the photonics component  210  can be a multi-purpose component that serves as a multiplexer for combining the signals from the plurality of light sources into a single output signal, in addition to frequency stability. 
     As discussed in more detail herein, each light source bank  203  can have a photonics component  210  unique from the other light source banks  203 . A photonics component  210  can be connected to the plurality of light sources  202  within its respective light source bank  203 . A photonics component  210  can also be connected to a detector  230  and a combiner  207 . A photonics component  210  can generate a plurality (e.g., three) of output signals. Some (e.g., two) of the output signals can be transmitted along traces  249 A and  249 C to be input signals into a corresponding detector (e.g., detector  230 A). The other output signal(s) can be transmitted along trace(s)  249 B to be input signals into a combiner  207 . Although for discussion purposes and with respect to  FIG.  2 B , three signals may be output from the photonics component  210 , more or fewer signals may be output from the photonics component  210 . The detector can receive the signals along traces  249 A and  249 C such that the detector  230  can be a channel monitor for wavelength locking. The operation of the detectors included in the detector array  230  is discussed in more detail herein. 
     The combiner  207  can receive a plurality of signals along traces  249 B from the plurality of light source banks  203 . The combiner  207  can combine the input signals and can generate an output signal to a splitter  215 . The splitter  215  can receive the combined signal from the combiner  207  and split the combined signal into a plurality of signals. In some examples, the splitter  215  can be a broadband splitter, such as (but not limited to) an interleaved Y-junction splitter. The device can include a plurality of emission regions  219  that can receive signals output from the splitter  215 . The emission regions  219  can refer to locations or components where light may exit the PIC  200 . For example, the emission regions  219  can include a plurality of outcouplers. 
     As discussed herein, the combination of the photonics component  210  and the combiner  207  can result in a two-stage combiner that allows for optimization of the wavelength locking in addition to reducing optical losses. 
     Example Broadband Combiner 
     The combiner  207  can be an optical multiplexer, such as (but not limited to) an arrayed waveguide grating (AWG). In some examples, the combiner  207  can be a broadband combiner that may receive light having a wide range of frequencies and/or wavelengths. In some examples, the number of inputs to the combiner  207  can be equal to the number of associated light sources  202  multiplied by the number of photonics components  210 . 
     In some instances, the combiner  207  can be used to combine the plurality of input signals into a fewer number of output signals. The combiner  207  can, additionally or alternatively, output signals from one light source bank  203  at a given time such as, e.g., per measurement period. In some examples, the combiner  207  can have one or more components and/or one or more functions similar to the photonics component  210  and the detector  230 . For example, the combiner  207  may be used for frequency stability. In some examples, the combiner  207  may also be used for monitoring the power of the PIC  200  by, e.g., monitoring the sum of the intensity of its input signals. 
     Example Detector Array 
     The detector array  230  can include a plurality of detectors, such as detector  230 A, detector  230 N, etc. At least some, and in some examples all, of the detectors included in the detector array  230  can be located in a single region of the PIC  200 , as shown in  FIG.  2 A . By locating the detectors in a single region, the size (e.g., footprint) of the PIC  200  can be reduced. Additionally, having a common place for all the detectors can facilitate in matching the optical losses. 
     The detectors can receive signals transmitted along traces  249 A and  249 C from the photonics components  210  included in the same light source bank  203 . In some examples, the signals transmitted along the traces  249 A and  249 C can be tapped portions of the fundamental modes of the light combined by the photonics component  210 . The signal from the trace  249 A can include a first range of wavelengths, and the signal from the trace  249 C can include a second range of wavelengths, for example. The first range of wavelengths and the second range of wavelengths may be different, at least in part. 
     A controller (not illustrated in  FIG.  2 B ) can receive the signals from each detector associated with the same photonics components  210 . The controller can take the ratio of the signals, which can be used to determine an intersection of the signals. The intersection can be located at the locked wavelength. The ratio can be also be used to control any chirping that may occur with the light sources  202 . The signals may also be used for obtaining more signal parameters. For example, the absorption can be determined by taking the derivative of the two signals. 
     In some instances, each detector  230  can receive a unique output from the photonics component  210 , thereby allowing dedicated channel monitoring. Dedicated channel monitoring can allow the device the ability to control the frequency as well as the intensity of the light emitted from the emission region(s). 
     Example Photonics Component 
     The photonics component can be a multi-purpose component that can be used for, at least, frequency stabilization and multiplexing.  FIG.  3    illustrates a block diagram of an example photonics component. The photonics component  310  can include one or more passive photonics components such as a filter, resonator, multiplexer, an arrayed waveguide grating (AWG), Mach-Zehnder interferometer (MZI), a Fabry-Perot cavity, a nanobeam cavity, a ring resonator, a Distributed Bragg Reflector (DBR), or the like for combining, selecting, and/or filtering input light. 
     The photonics component  310  can include an input section, for example, that receives and combines signals received along a plurality of traces  348  from a plurality of light sources (e.g., light sources  202  illustrated in  FIG.  2 B ). The input section can output the combined signals into a plurality of waveguides to an output section, which can generate at least three signals to be output along traces  349 . One signal (along trace  349 B) can be the result from a multiplexing function of the photonics component  310  and can be output to a combiner (e.g., combiner  207  illustrated in  FIGS.  2 A- 2 B ). The other signals (along traces  349 A and  349 C) can be tapped portions of the fundamental mode of the combined light. The signal output along trace  349 A can include a first range of wavelengths, and the signal output along trace  349 C can include a second range of wavelengths. The trace  349 A and the trace  349 C can be connected to a detector array (e.g., detector array  230  illustrated in  FIGS.  2 A- 2 B ), and signals can be output to the detector array accordingly. 
     By using a single component that performs multiple functions, the size, cost, and complexity of the PIC can be decreased. Although the figure illustrates a block diagram similar to an AWG, examples of the disclosure can include any other type of passive photonic component. Additionally or alternatively, the photonics component  310  can include one or more additional components not illustrated in the figures. 
     Example Optical Routing 
       FIG.  4 A  illustrates a floorplan of optical components and optical traces of an example PIC architecture. The PIC  400  can include a plurality of light source banks  403 , a detector array  430 , a combiner  407 , and a region  411  that can have correspondingly similar functions and components as the plurality of light source banks  203 , the detector array  230 , the combiner  207 , and the region  211  discussed herein and in  FIGS.  2 A and  2 B . 
     The signals from the plurality of light source banks  403  can be routed to the combiner  407  and to the detector array  430  using one or more configurations to minimize optical losses. The amount of optical loss in transmitting signals from one component to another can depend on the number of bends in the routing traces and propagation loss along the total length of the optical traces. In general, a greater number of bends can lead to a greater amount of optical loss. In addition to reducing the optical loss, the optical routing can be such that the amount of space occupied by the components and the routing traces along the substrate can be minimized. 
     The traces from the light source bank  403  can be output to a multi-tap  445 . The details of multi-tap  445  are discussed herein. Although  FIG.  4 A  illustrates the multi-tap  445  and corresponding routing on the left side, examples of the disclosure further include additional multi-taps and corresponding routing on the right side (and are merely excluded for purposes of simplicity). The multi-tap  445  can route a plurality (e.g., two) of the traces, such as trace  449 A and trace  449 C, to the other side from where its inputs are received. For example, the traces can be received from the left of the light source banks  403 A- 403 E (located on the left side), or right of the light source banks  403 F- 403 J (located on the right side). The optical traces  449 A and  449 B can then be routed towards the detector array  430 . 
     In the PIC  400  shown in the figure, the detector array  430  can be located at the bottom region of the PIC  400 , so the optical traces can be routed down the sides of the substrate  442  and then towards the inside of region  433  at the bottom of the PIC  200 . The region  433  can be a fifth region of the substrate  442 . The region  433  for the optical traces can be located around the outside (e.g., closer to the edge of the PIC  400  than the other components, such as the detector array  430  and the light source banks  403 ) portions of the PIC  400 . 
     The multi-tap  445  can route another trace, such as trace  449 B, to a second side of the multi-tap  445 . The second side can be a side opposite from that of which the trace  449 A and trace  449 C are output. Since  FIG.  4 A  illustrates an example floorplan which shows the traces  449 A and  449 C as being routed down, the multi-tap  445  can route the trace  449 B up. The trace  449 B can then be routed towards the combiner  407  in a sixth region of the PIC  400 . The sixth region can be a region located between the light source banks  403  and a region between the plurality of light source banks  403  and the combiner  407 , illustrated as region  435  in the figure. The combiner  407  can be located in a center (e.g., surrounded by components) region of the PIC  400 . 
     In this manner, the optical traces between the plurality of light source banks  403  and the combiner  407  can be routed between the light source banks  403 , thereby creating boundaries between adjacent light source banks  403 . Additionally, the optical traces between the plurality of light source banks  403  and the detector array  430  can be routed in the outer region  433  of the PIC  400 . 
       FIG.  4 B  illustrates a top view of an example multi-tap component. Multi-tap  445  can receive a plurality of input signals from trace  449 A, trace  449 B, and trace  449 C. The trace  449 A can be located on top of the trace  449 B when received as input into the multi-tap  445 . The multi-tap  445  can include a crossing  441 , where a first optical trace, such as the trace  449 A, can cross (e.g., intersect) a second optical trace, such as trace  449 B. Before the crossing  441 , the traces  449 A and  449 B can change in one or more properties, such as its width. The traces  449 A and  449 B can have an increase in width that starts before the crossing  441 , and then a decrease in width that starts at the crossing  441 . That is, the traces  449 A and  449 B can be tapered. The traces may also have portions before and after the crossing  441  which are straight. The straight portions can be located between the bends and the beginning point of any change in width. 
     After the crossing  441 , the trace  449 A can be routed below the multi-tap  445  along with trace  449 C. Additionally, after the crossing  441 , the trace  449 B can be routed above the crossing  441 . 
       FIG.  4 B  illustrates the configuration of a multi-tap  445  for light source banks located on the left side of the substrate. For example, the multi-tap  445  illustrated in  FIG.  4 B  can be connected to light source bank  403 A with input signals received on the right side of the crossing  441  and output signals transmitted on the left side of the crossing  441 . Examples of the disclosure can include a multi-tap  445  that has a mirrored configuration for light source banks located on the right side of the substrate. For example, light source banks  403 F- 403 J can be connected to multi-taps  445  having the mirrored configuration. With the mirrored configuration (not shown), the input signals from the light source banks can be received on the left side of the crossing, and output signals can be transmitted on the right side of the crossing. 
     Example Device Operation 
       FIG.  5    illustrates an exemplary operation of a device including a PIC. Process  550  begins by generating light using one or more laser bars (e.g., light source  202 A, light source  202 B illustrated in  FIG.  2 B ) (step  552  of process  550 ). The generated light (e.g., light  248 A, light  248 B illustrated in  FIG.  2 B ) can be input to a plurality of photonics components (e.g., photonics component  210 A illustrated in  FIG.  2 B ) (step  554  of process  550 ). One or more of the photonics components can combine and multiplex the inputs, outputting the signals on the second traces (e.g., trace  349 B illustrated in  FIG.  3   , trace  449 B illustrated in  FIG.  4 B ) of a plurality of multi-taps (e.g., multi-tap  445  illustrated in  FIG.  4 B ) (step  556  of process  550 ). 
     The photonics component(s) may also provide additional outputs to first traces (e.g., trace  449 A and trace  449 C illustrated in  FIG.  4 B ) of the plurality of multi-taps (step  558  of process  550 ). The multi-taps can cross the signals on the first traces with the signals on the second traces at crossings (e.g., crossing  441  illustrated in  FIG.  4 B ) (step  560  of process  550 ). The multi-taps can transmit signals along an outer region of a PIC (e.g., region  433  illustrated in  FIG.  4 A ) to detectors in a detector array (e.g., detector array  430  illustrated in  FIG.  4 A ) (step  562  of process  550 ). The detectors can receive the signals, and a controller can determine the locked wavelength for frequency stabilization (step  564  of process  550 ). 
     The multi-taps can also transmit signals in regions between light source banks (e.g., region  435  illustrated in  FIG.  4 A ) to a combiner (e.g., combiner  207  illustrated in  FIG.  2 B , combiner  407  illustrated in  FIG.  4 A ) (step  566  of process  550 ). The combiner can combine the signals, and a splitter (e.g., splitter  215  illustrated in  FIG.  2 B ) can split the combined signal into a plurality of signals (step  568  of process  550 ). The split signals can be transmitted to a plurality of emission regions (e.g., emission regions  219  of  FIG.  2 B ) (step  570  of process  550 ). 
     In some examples, the light generated in step  552  and detected in step  562  can occur at certain regions of the PIC such as region  221 A and region  223 , respectively. 
     Although the disclosed examples have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the disclosed examples as defined by the appended claims.

Metadata:
Filing Date: 20221212
Publication Date: 20250114
Grant Date: 20250114
Priority Date: 20180928
Inventors: BISMUTO, ALFREDO
ARBORE, MARK
PELC, Jason
ABEDIASL, Hooman
TRITA, Andrea
Assignee: APPLE INC
CPC Classifications: [{"code": "G02B6/4206", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02B6/29301", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02B6/2938", "inventive": true, "first": false, "tree": "[]"}, {"code": "G01N2021/3181", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02B6/29379", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02B6/29346", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02B6/4215", "inventive": true, "first": true, "tree": "[]"}, {"code": "G01N21/255", "inventive": true, "first": true, "tree": "[]"}, {"code": "G02B6/4206", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02B6/2938", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02B6/29301", "inventive": true, "first": false, "tree": "[]"}, {"code": "G02B6/4215", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 84426586