PATENT DOCUMENT

Publication Number: US-8400858-B2
Application Number: US-201113214257-A
Country: US
Kind Code: B2

Title: Memory device with reduced sense time readout

Abstract:
A method for data storage includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout configurations is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout configuration.

Claims:
1. A method for data storage, comprising:
 providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time; 
 evaluating a condition with respect to a read operation that is to be performed over a group of the memory cells; 
 selecting one of the first and second readout configurations responsively to the evaluated condition; and 
 reading the storage values from the group of the memory cells using the selected readout configuration. 
 
     
     
       2. The method according to  claim 1 , wherein the memory cells in the group belong to respective bit lines, wherein the first readout configuration sets at least one of the bit lines to have a first conductivity, and wherein the second readout configuration sets the at least one of the bit lines to have a second conductivity, greater than the first conductivity. 
     
     
       3. The method according to  claim 1 , wherein the memory cells in the group belong to a word line selected from among multiple word lines, wherein the first readout configuration applies first pass voltages to the word lines other than the selected word lines while reading the group of memory cells, and wherein the second readout configuration applies second pass voltages to the word lines other than the selected word lines, such that at least one of the second pass voltages is higher than a corresponding one of the first pass voltages. 
     
     
       4. The method according to  claim 1 , wherein the first readout configuration reads the storage values using a first set of read thresholds, and wherein the second readout configuration reads the storage values using a second set of read thresholds, such that at least one of the second read thresholds is higher than a corresponding one of the first read thresholds. 
     
     
       5. The method according to  claim 1 , wherein the memory cells in the group belong to a word line in a memory block that comprises multiple word lines, and wherein evaluating the condition comprises assessing a number of the word lines in the memory block that are programmed with data. 
     
     
       6. The method according to  claim 1 , wherein the first readout configuration reads the storage values with a first accuracy, and wherein the second readout configuration reads the storage values with a second accuracy that is coarser than the first accuracy. 
     
     
       7. The method according to  claim 1 , wherein evaluating the condition comprises assessing a wear level of the group of the memory cells. 
     
     
       8. The method according to  claim 1 , wherein evaluating the condition and selecting the one of the readout configurations comprise selecting the second readout configuration responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process. 
     
     
       9. The method according to  claim 1 , wherein evaluating the condition and selecting the one of the readout configurations comprise selecting the second readout configuration responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells. 
     
     
       10. The method according to  claim 1 , wherein each of the memory cells in the group stores at least first and second bits, and wherein evaluating the condition and selecting the one of the readout configurations comprise selecting the second readout configuration responsively to determining that the read operation reads the first bits from the memory cells, and selecting the first readout configuration responsively to determining that the read operation reads the second bits from the memory cells. 
     
     
       11. The method according to  claim 1 , wherein evaluating the condition and selecting the one of the readout configurations comprise selecting the second readout configuration responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells. 
     
     
       12. The method according to  claim 1 , wherein the storage values represent stored data, and wherein evaluating the condition and selecting the one of the readout configurations comprise making an attempt to read the storage values from the memory cells in the group using the second readout configuration and to reconstruct the stored data from the read storage values, and selecting the first readout configuration upon a failure of the attempt. 
     
     
       13. The method according to  claim 12 , wherein the stored data is encoded with an Error Correction Code (ECC), and wherein making the attempt comprises decoding the ECC. 
     
     
       14. The method according to  claim 12 , and comprising re-attempting to reconstruct the stored data using both the storage values read by the first readout configuration and the storage values read using the second readout configuration. 
     
     
       15. Apparatus for data storage, comprising:
 a plurality of analog memory cells; and 
 circuitry, which is configured to evaluate a condition with respect to a read operation that is to be performed over a group of the memory cells, to select, responsively to the evaluated condition, between at least first and second readout configurations for reading storage values from the analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values at a second sense time that is shorter than the first sense time, and to read the storage values from the group of the memory cells using the selected readout configuration. 
 
     
     
       16. The apparatus according to  claim 15 , wherein the memory cells in the group belong to respective bit lines, wherein the first readout configuration sets at least one of the bit lines to have a first conductivity, and wherein the second readout configuration sets the at least one of the bit lines to have a second conductivity, greater than the first conductivity. 
     
     
       17. The apparatus according to  claim 15 , wherein the memory cells in the group belong to a word line selected from among multiple word lines, wherein the first readout configuration applies first pass voltages to the word lines other than the selected word lines while reading the group of memory cells, and wherein the second readout configuration applies second pass voltages to the word lines other than the selected word lines, such that at least one of the second pass voltages is higher than a corresponding one of the first pass voltages. 
     
     
       18. The apparatus according to  claim 15 , wherein the first readout configuration reads the storage values using a first set of read thresholds, and wherein the second readout configuration reads the storage values using a second set of read thresholds, such that at least one of the second read thresholds is higher than a corresponding one of the first read thresholds. 
     
     
       19. The apparatus according to  claim 15 , wherein the memory cells in the group belong to a word line in a memory block that comprises multiple word lines, and wherein the circuitry is configured to evaluate the condition by assessing a number of the word lines in the memory block that are programmed with data. 
     
     
       20. The apparatus according to  claim 15 , wherein the first readout configuration reads the storage values with a first accuracy, and wherein the second readout configuration reads the storage values with a second accuracy that is coarser than the first accuracy. 
     
     
       21. The apparatus according to  claim 15 , wherein the circuitry is configured to evaluate the condition by assessing a wear level of the group of the memory cells. 
     
     
       22. The apparatus according to  claim 15 , wherein the circuitry is configured to select the second readout configuration responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process. 
     
     
       23. The apparatus according to  claim 15 , wherein the circuitry is configured to select the second readout configuration responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells. 
     
     
       24. The apparatus according to  claim 15 , wherein each of the memory cells in the group stores at least first and second bits, and wherein the circuitry is configured to select the second readout configuration responsively to determining that the read operation reads the first bits from the memory cells, and to select the first readout configuration responsively to determining that the read operation reads the second bits from the memory cells. 
     
     
       25. The apparatus according to  claim 15 , wherein the circuitry is configured to select the second readout configuration responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells. 
     
     
       26. The apparatus according to  claim 15 , wherein the storage values represent stored data, and wherein the circuitry is configured to make an attempt to read the storage values from the memory cells in the group using the second readout configuration and to reconstruct the stored data from the read storage values, and to select the first readout configuration upon a failure of the attempt. 
     
     
       27. The apparatus according to  claim 26 , wherein the stored data is encoded with an Error Correction Code (ECC), and wherein the circuitry is configured to make the attempt by decoding the ECC. 
     
     
       28. The apparatus according to  claim 26 , wherein the circuitry is configured to re-attempt to reconstruct the stored data using both the storage values read by the first readout configuration and the storage values read using the second readout configuration. 
     
     
       29. Apparatus for data storage, comprising:
 an interface for communicating with a memory that includes a plurality of analog memory cells; and 
 circuitry, which is configured to evaluate a condition with respect to a read operation that is to be performed over a group of the memory cells, to select, responsively to the evaluated condition, between at least first and second readout configurations for reading storage values from the analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values at a second sense time that is shorter than the first sense time, and to read the storage values from the group of the memory cells using the selected readout configuration.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation in part of U.S. patent application Ser. No. 12/405,275, filed Mar. 17, 2009, which claims the benefit of U.S. Provisional Patent Application 61/037,327, filed Mar. 18, 2008, and U.S. Provisional Patent Application 61/119,929, filed Dec. 4, 2008. The disclosures of all these related applications are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to memory devices, and particularly to methods and systems for reading data from analog memory cells. 
     BACKGROUND OF THE INVENTION 
     Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell holds a certain level of a given physical quantity such as an electrical charge or voltage, which represents the data stored in the cell. The levels of this physical quantity are also referred to as storage values or analog values. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a programming state that represents one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. 
     Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states. 
     Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells. 
     Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24 th  International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference. 
     SUMMARY OF THE INVENTION 
     An embodiment that is described herein provides a method for data storage. The method includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout configurations is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout configuration. 
     In some embodiments, the memory cells in the group belong to respective bit lines, the first readout configuration sets at least one of the bit lines to have a first conductivity, and the second readout configuration sets the at least one of the bit lines to have a second conductivity, greater than the first conductivity. 
     In an embodiment, the memory cells in the group belong to a word line selected from among multiple word lines, the first readout configuration applies first pass voltages to the word lines other than the selected word lines while reading the group of memory cells, and the second readout configuration applies second pass voltages to the word lines other than the selected word lines, such that at least one of the second pass voltages is higher than a corresponding one of the first pass voltages. 
     In a disclosed embodiment, the first readout configuration reads the storage values using a first set of read thresholds, and the second readout configuration reads the storage values using a second set of read thresholds, such that at least one of the second read thresholds is higher than a corresponding one of the first read thresholds. 
     In another embodiment, the memory cells in the group belong to a word line in a memory block that includes multiple word lines, and evaluating the condition includes assessing a number of the word lines in the memory block that are programmed with data. In yet another embodiment, the first readout configuration reads the storage values with a first accuracy, and the second readout configuration reads the storage values with a second accuracy that is coarser than the first accuracy. 
     In some embodiments, evaluating the condition includes assessing a wear level of the group of the memory cells. In another embodiment, evaluating the condition and selecting the one of the readout configurations include selecting the second readout configuration responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process. In yet another embodiment, evaluating the condition and selecting the one of the readout configurations include selecting the second readout configuration responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells. 
     In an example embodiment, each of the memory cells in the group stores at least first and second bits, and evaluating the condition and selecting the one of the readout configurations include selecting the second readout configuration responsively to determining that the read operation reads the first bits from the memory cells, and selecting the first readout configuration responsively to determining that the read operation reads the second bits from the memory cells. In another embodiment, evaluating the condition and selecting the one of the readout configurations include selecting the second readout configuration responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells. 
     In some embodiments, the storage values represent stored data, and evaluating the condition and selecting the one of the readout configurations include making an attempt to read the storage values from the memory cells in the group using the second readout configuration and to reconstruct the stored data from the read storage values, and selecting the first readout configuration upon a failure of the attempt. In an embodiment, the stored data is encoded with an Error Correction Code (ECC), and making the attempt comprises decoding the ECC. In a disclosed embodiment, the method includes re-attempting to reconstruct the stored data using both the storage values read by the first readout configuration and the storage values read using the second readout configuration. 
     There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage including a plurality of analog memory cells and circuitry. The circuitry is configured to evaluate a condition with respect to a read operation that is to be performed over a group of the memory cells, to select, responsively to the evaluated condition, between at least first and second readout configurations for reading storage values from the analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values at a second sense time that is shorter than the first sense time, and to read the storage values from the group of the memory cells using the selected readout configuration. 
     There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage including an interface and circuitry. The interface is configured to communicate with a memory that includes a plurality of analog memory cells. The circuitry is configured to evaluate a condition with respect to a read operation that is to be performed over a group of the memory cells, to select, responsively to the evaluated condition, between at least first and second readout configurations for reading storage values from the analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values at a second sense time that is shorter than the first sense time, and to read the storage values from the group of the memory cells using the selected readout configuration. 
     The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention; 
         FIGS. 2 and 3  are flow charts that schematically illustrate methods for retrieving data from analog memory cells using read commands having different accuracy levels, in accordance with embodiments of the present invention; 
         FIG. 4  is a flow chart that schematically illustrates a method for retrieving data from analog memory cells with reduced sense time, in accordance with an embodiment of the present invention; and 
         FIG. 5  is a graph showing programming levels in a group of analog memory cells and associated normal and reduced-sense-time read thresholds, in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Overview 
     Data is typically stored in analog memory cells by programming the cells with certain storage values (e.g., threshold voltages) that represent the data. The data is retrieved by reading the storage values from the cells. Usually, a trade-off exists between the accuracy with which the storage values are read and the time needed to read them. Highly-accurate read operations tend to be relatively long and may limit the overall data retrieval speed. 
     In practice, however, highly-accurate readout is not always mandatory. Some readout tasks can be carried out successfully with reduced accuracy, and therefore with higher speed. Reduced accuracy can be sufficient, for example, when the memory cells are at the beginning of their life cycle and thus have gone through only few programming and erasure cycles. As another example, when canceling interference in given memory cells based on the storage values of neighboring cells, the given cells are typically read with high accuracy. The neighboring cells, however, can often be read with lower accuracy with little or no degradation in cancellation performance. 
     As yet another example, when programming the cells using a Program and Verify (P&amp;V) process, the programmed storage values can be verified with a lower accuracy than the accuracy used for data retrieval. Read operations for estimating the statistical distribution of the storage values (e.g., for adjusting read thresholds) can often be performed with lower accuracy, as well. 
     Embodiments of the present invention that are described hereinbelow provide improved methods and systems for reading data from analog memory cells. These methods and systems use multiple readout configurations having different sense times. For a memory cell belonging to a certain bit line, the sense time used for reading the memory cell is defined as the time duration over which the bit line voltage or current is integrated. 
     Typically, in preparation for reading the storage values from a group of analog memory cells, a condition related to the read operation is evaluated. An appropriate readout configuration is selected from among the available readout configurations based on the evaluated condition. The storage values are read using the selected readout configuration. The condition may depend, for example, on the age or wear level of the memory cells to be read, on whether the purpose of the readout operation is to retrieve data, to estimate interference, to verify a previous programming operation or to estimate the storage value statistics. 
     Several example techniques of implementing readout configurations having different sense times are described herein. Some of these techniques modify the electrical conductivity of the bit lines to which the read memory cells belong. When the bit line conductivity is improved (i.e., increased—bit line resistance reduced), the bit line current increases and readout can be performed with a shorter sense time. In practice, however, improving the bit line conductivity may degrade other system performance measures, and therefore the improvement is performed only selectively. 
     Typically, the memory cells in the group that is to be read with a given readout configuration belong to a certain selected word line in a memory block that includes multiple word lines. In some embodiments, the group of memory cells is read by sensing the bit lines while applying a read voltage to the selected word line and certain pass voltages to the other word lines. In some embodiments, the readout configurations differ from one another in at least one of the pass voltages that are applied to the unselected word lines. By increasing the pass voltage, the bit line conductivity can be improved and the sense time shortened. 
     In another embodiment, the sense time is set based on the number of word lines in the memory block that are already programmed with data. When the memory block has only a few programmed word lines, the bit line conductivity is typically better since a large number of the memory cells along the bit line are erased. In this case, a shorter sense time can typically be used. When a larger number of word lines are programmed, the bit line conductivity is typically poorer, and a longer sense time may be needed to achieve reliable readout. 
     Typically, the memory cells are read by comparing their storage values to one or more read thresholds. In some embodiments, the readout configurations differ from one another in at least one of the read threshold positions. By increasing a given read threshold, possibly at the expense of higher read error probability, the bit line conductivity can be improved and the sense time shortened. 
     When using the methods and systems described herein, some readout tasks (e.g., tasks that require high accuracy) are performed with a longer sense time. Other readout tasks, or when conditions permit, are carried out with a shorter sense time. Thus, the disclosed methods provide a considerable increase in average readout speed from analog memory cells, with little or no degradation in other performance measures. 
     System Description 
       FIG. 1  is a block diagram that schematically illustrates a memory system  20 , in accordance with an embodiment of the present invention. System  20  can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (“disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved. 
     System  20  comprises a memory device  24 , which stores data in a memory cell array  28 . The memory cell array comprises multiple analog memory cells  32 . Memory device and memory controller  52  may support multiple read commands, which read memory cells  32  at different accuracy levels and have different execution times. The use of these multiple read commands is addressed in detail hereinbelow. Additionally or alternatively, memory device  24  and memory controller  52  may support multiple readout configurations having different sense times. In some embodiments, the memory device and memory controller communicate with each other using a dedicated command interface in order to implement the multiple read commands or configurations defined herein. 
     In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog level of a physical quantity, such as an electrical voltage or charge. Array  28  may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. Memory cells  32  may comprise Single-Level Cells (SLC) or Multi-Level Cells (MLC, also referred to as multi-bit cells). 
     Memory cells  32  of array  28  are typically arranged in a grid having multiple rows and columns, commonly referred to as word lines and bit lines, respectively. Cells are typically erased in groups of word lines that are referred to as erasure blocks. In some embodiments, a given memory device comprises multiple memory cell arrays, which may be fabricated on separate dies. 
     The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values. 
     System  20  stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming states are selected from a finite set of possible states, and each state corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming states by writing one of four possible nominal storage values to the cell. 
     Memory device  24  comprises Reading/Writing (R/W) circuitry, which converts data for storage in the memory device to storage values and writes them into memory cells  32 . In alternative embodiments, the R/W circuitry does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. When reading data out of array  28 , the R/W circuitry converts the storage values of memory cells  32  into digital samples having a resolution of one or more bits. The R/W circuitry typically reads data from cells  32  by comparing the storage values of the cells to one or more read thresholds. Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W circuitry can erase a group of cells  32  by applying one or more negative erasure pulses to the cells. 
     In the present example, the R/W circuitry comprises Word Line (WL) circuitry  36  and sense circuitry  40 . The WL circuitry is connected to the word lines of array  28 , and the sense circuitry is connected to the bit lines of the array. Among other tasks, WL circuitry  36  applies appropriate bias voltages to the different word lines during read operations, and applies appropriate programming pulses to word lines during programming operations. Sense circuitry  40 , among other functions, senses the voltages or currents of the bit lines during read operations. 
     The R/W circuitry typically reads a group of memory cells  32  along a certain word line simultaneously. In a typical read operation, WL circuitry  36  applies the appropriate bias voltages to the read word line and to the other word lines in the same erasure block. Sense circuitry  40  senses the voltage or current of each bit line. The sensed voltage or current of a given bit line is indicative of the storage value of the memory cell that belongs to this bit line and to the read word line. The sense circuitry typically compares the sensed bit line voltages or currents to one or more read thresholds, and outputs the comparison results. 
     In some embodiments, memory device  24  comprises a signal processing unit  44 , which applies various signal processing mechanisms to the read and/or programmed data or storage values. In particular, unit  44  may apply signal processing mechanisms that enhance the accuracy of reading the storage values from memory cells  32 , such as interference cancellation or read threshold adaptation. The use of these mechanisms is addressed in greater detail below. Signal processing unit  44  communicates with WL circuitry  36  and with sense circuitry  40 . Additionally, the signal processing circuitry communicates with elements external to device  24  via an interface  48 . 
     The storage and retrieval of data in and out of memory device  24  is performed by a memory controller  52 . Controller  52  comprises an interface  60  for communicating with device  24 , and a processor  64  that carries out the memory control functions described herein. In some embodiments, memory controller  52  comprises an Error Correction Code (ECC) unit  68 , which encodes the data for storage using a suitable ECC, and decodes the ECC of data read from the memory device. In some embodiments, controller  52  produces the storage values for storing in the memory cells and provides these values to device  24 . Alternatively, controller  52  may provide the data for storage, and the conversion to storage values is carried out in the memory device. 
     Memory controller  52  communicates with a host  56 , for accepting data for storage in the memory device and for outputting data retrieved from the memory device. In some embodiments, some or even all of the functions of controller  52  may be implemented in hardware. Alternatively, controller  52  may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements. 
     The configuration of  FIG. 1  is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. For example, in some embodiments signal processing unit  44  may be omitted, and its functions performed by the memory controller. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity. 
     In the exemplary system configuration shown in  FIG. 1 , memory device  24  and memory controller  52  are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and the memory controller may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC). Further alternatively, some or all of the circuitry of the memory controller may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of controller  52  can be implemented in software and carried out by a processor or other element of the host system. In some implementations, a single memory controller may be connected to multiple memory devices  24 . In yet another embodiment, some or all of the memory controller functionality may be carried out by a separate unit, referred to as a memory extension, which acts as a slave of memory device  24 . Typically, processor  64  in controller  52  comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory. 
     Trade-Off Between Readout Accuracy and Speed 
     Typically, a trade-off exists between the accuracy at which memory device  24  reads the storage values from memory cells  32 , and the speed at which the storage values are read. Highly-accurate readout tends to be relatively slow, whereas fast readout often has a reduced accuracy. In the present context, the term “accuracy” means any measure of the certainty or fidelity at which the storage values read by the circuitry of memory device represent the actual storage values stored in the memory cells. In an accurate read operation, the differences between the read storage values and the respective actual storage values of the memory cells are small, and vice versa. Since any read operation has some inherent uncertainty, different read operations can be characterized by their reading accuracies. Several examples of read commands having different accuracies are described further below. The terms “high accuracy” and “fine accuracy” are used interchangeably herein. 
     In many practical cases, highly-accurate readout is not always needed. Some readout tasks can be carried out successfully at a reduced reading accuracy, and therefore at a higher speed. In some embodiments, memory device  24  and memory controller  52  support multiple predefined types of read commands for reading the storage values from memory cells  32 . The different commands read the storage values at different accuracies. Each command has a respective execution time, which is typically longer for higher-accuracy commands and shorter for lower-accuracy commands. 
     Typically, when memory controller  52  prepares to read the storage values from a certain group of memory cells (e.g., a memory page), the controller evaluates a condition related to the read operation to be performed. Based on the evaluated condition, the memory controller selects one of the predefined read commands, and instructs the memory device to read the storage values in question using the selected command. Several examples of readout tasks that can be performed at different accuracy levels, of conditions that can be evaluated so as to select the appropriate read command, and of read commands having different accuracies and execution times, are described in detail below. 
       FIG. 2  is a flow chart that schematically illustrates a method for retrieving data from analog memory cells  32  using read commands having different accuracy levels, in accordance with an embodiment of the present invention. The method begins with memory controller  52  initiating readout of a certain memory page, which is stored in a group of memory cells  32 , at an initiation step  70 . The memory controller assesses the desired readout accuracy by evaluating a condition related to the read operation to be performed, at an accuracy assessment step  74 . The memory controller selects one of the predefined read commands, which has the desired accuracy, and reads the storage values corresponding to the page using the selected command, at a reading step  78 . The memory controller typically reconstructs the stored data from the read storage values and outputs the reconstructed data to host  56 . 
     Example Readout Tasks, Selection Criteria and Read Commands 
     The different read commands supported by memory device  24  and memory controller  52  may differ from one another in various ways, in order to provide different accuracy/speed trade-offs. For example, different read commands may have different sense times. The sense time is defined as the time duration over which sense circuitry  40  measures the bit line voltages or currents during a read operation. As can be appreciated, integrating the bit line current or voltage over a longer time duration averages the read noise and improves the readout accuracy. On the other hand, a longer sense time increases the execution time of the read command. Thus, device  24  and controller  52  may support a high-accuracy but relatively slow read command having a long sense time, and a lower-accuracy but relatively fast read command having a short sense time. In a certain NAND Flash device, for example, the long sense time may be on the order of 25 μS and the short sense time may be on the order of 10 μS, although any other suitable values can also be used. In some embodiments, the long sense time may be approximately twice the length of the short sense time, although any other suitable ratio can also be used. 
     As another example, different read commands may read the storage values using different numbers of read thresholds. As noted above, the R/W circuitry typically reads the storage values from memory cells  32  by comparing them to one or more read thresholds. In some embodiments, signal processing unit  44  can improve the reading accuracy by re-reading a certain set of storage values multiple times, using different read thresholds. For example, the multiple read results can be combined to form soft metrics of the read storage values, and these metrics can be used by ECC unit  68  in the memory controller to decode the ECC. Some aspects of data readout using multiple read thresholds are addressed in PCT International Publications WO 2007/132457, WO 2008/053472, WO 2008/111058 and WO 2008/139441, whose disclosures are incorporated herein by reference. 
     Typically, the readout accuracy improves as the number of read thresholds increases. On the other hand, re-reading a group of memory cells using a large number of read thresholds increases execution time. Thus, read commands that use different numbers of read thresholds will typically have different reading accuracies and execution times. In an embodiment, the memory device and memory controller may support a read command that reads the storage values using a small number of read thresholds (e.g., a single read threshold), and another read command that reads the storage values using a higher number of read thresholds (e.g., between two and five read thresholds). 
     When a given read commands uses a single read threshold, the read results can be viewed as hard metrics of the storage values. When a given read command uses multiple read thresholds, the read results can be combined or otherwise processed to produce soft metrics of the storage values. ECC unit  68  may decode the ECC based on these hard or soft metrics. Thus, a relatively fast command can be specified to produce hard metrics. A slower command may be specified to produce soft metrics, which generally enable higher accuracy in decoding the ECC. Alternatively, different commands that use different numbers of read thresholds can be viewed as producing soft metrics having different accuracies. 
     Typically, multiple-threshold readout is carried out by unit  44  internally to the memory device. In a typical process, the memory controller selects and sends the appropriate read command to the memory device, and the memory device executes the command by reading the storage values using the appropriate number of read thresholds. 
     In some embodiments, signal processing unit  44  applies certain signal processing mechanisms to the read storage values in order to increase their accuracy. For example, unit  44  may apply an interference cancellation process for canceling interference that distorts the read storage values. Techniques for estimating and cancelling distortion in memory cells are described, for example, in PCT International Publications WO 2007/132452, WO 2007/132453 and WO 2008/026203, whose disclosures are incorporated herein by reference, and in PCT International Publications WO 2007/132457, cited above. As another example, signal processing unit  44  may apply a mechanism that adaptively adjusts the positions of the read thresholds that are used for reading the storage values. Techniques for adaptively adjusting read threshold values are described, for example, in PCT International Publications WO 2008/053472 and WO 2008/111058, cited above. 
     Signal processing mechanisms, such as interference cancellation or adaptive threshold adjustment, improve the readout accuracy. On the other hand, these mechanisms are typically computationally intensive and therefore increase execution time and readout speed. Thus, in some embodiments, different read commands can apply signal processing mechanisms having different execution times, or refrain from applying such mechanisms, and as a result provide different accuracy/speed trade-offs. 
     For example, a given read command may apply interference cancellation to the read storage values, and another read command may read the storage values without applying interference cancellation. As another example, a given read command may adjust the read thresholds before reading the storage values, and another read command may read the storage values without adjusting the read thresholds. 
     In some embodiments, both unit  44  and memory controller  52  have signal processing capabilities. For example, an interference cancellation process or threshold adjustment process can be split between unit  44  and processor  52 , such that each entity carries out a subset of the signal processing tasks. Memory controller is often capable of carrying out complex signal processing tasks as it often has a higher processing power than unit  44 . Thus, moving signal processing functions from unit  44  to controller  52  may improve the readout accuracy. On the other hand, performing signal processing tasks by the memory controller often involves transferring larger volumes of data from the memory device to the memory controller, which increases the execution time. Thus, the partitioning of signal processing tasks between the memory controller and the memory device may provide different accuracy/speed trade-offs. Therefore, different read commands may split the signal processing tasks differently between the memory controller and the memory device. 
     For example, a certain read command may apply a fast but limited-accuracy threshold adaptation process internally to the memory device. Another read command may apply a more complex and higher-accuracy threshold adaptation process by the memory controller. The latter command is typically slower, since it involves transferring of larger amounts of data (results of re-read operations) from the memory device to the memory controller. 
     As another example, unit  44  in the memory device may be configurable to perform a limited-performance interference cancellation process on the data read from the memory cells. Memory controller  52  may be configurable to perform a high-performance interference cancellation process, which may be slower than the process applied internally to the memory device. A certain read commands may use only the interference cancellation process applied in the memory device. Another read command may use only the controller&#39;s interference cancellation process. Yet another read command may apply both processes to the read data. 
     The read commands described above are chosen purely by way of example. In alternative embodiments, memory device  24  and memory controller  52  may use any other suitable set of two or more predefined read commands, which have different readout accuracies and execution times. In particular, the example techniques described above can be combined to produce commands having various accuracy/trade-offs. For example, a highly-accurate read command may use a long sense time, apply interference cancellation and read the storage values using multiple thresholds that are adjusted adaptively. A low-accuracy but high-speed read command may use a short sense time and read the storage values using a single, fixed read threshold. 
     Memory controller  52  may evaluate different conditions in order to select one of the predefined read commands for performing a given readout task. For example, a group of memory cells that has gone through a large amount of wear (e.g., a large number of programming and erasure cycles and/or long retention periods) may suffer from a high level of distortion, and should therefore be read at high accuracy. A group of memory cells that has gone through a small amount of wear may be read successfully at a lower accuracy and at a higher speed. Thus, in some embodiments, the memory controller selects the read command based on the wear level of the memory cells to be read. Any suitable measure or estimate of the wear level can be used, such as the actual or estimated number of programming and erasure cycles applied to the cells, and/or the time that elapsed since the last programming operation. 
     This sort of condition may be applied to each individual group of cells, assuming that wear level information is available per cell group. Alternatively, the memory controller may apply the selection jointly for an entire block or even to the entire memory device. For example, the memory controller may use a fast but low-accuracy read command at the beginning of the memory device&#39;s lifetime, and switch to a higher-accuracy but slower read command at a later point along the lifetime of the memory device. 
     As another example, the memory controller may initially select a fast read command by default. If the data cannot be reconstructed successfully using this read command (e.g., if ECC decoding fails), the memory controller may re-attempt to read the storage values using a slower but higher-accuracy command. 
     In some embodiments, the read command is selected internally in the memory device, such as by signal processing unit  44  or by the R/W circuitry. For example, applying interference cancellation to a certain group of memory cells typically involves reading the storage values from both the interfered memory cells and other memory cells (typically neighboring cells) that potentially cause the interference. In many practical cases, the interference can be canceled successfully even if the storage values of the interfering memory cells are known at a low accuracy. Thus, when applying interference cancellation, the memory device may read the storage values of the potentially-interfering cells using a fast but low-accuracy command. 
     In some embodiments, memory cells  32  comprise multi-level cells, each storing multiple data bits. In many data storage schemes, different bits in a group of memory cells are used for storing different memory pages. Consider, for example, a group of 3 bit/cell memory cells. Each memory cell stores three bits, which are referred to as a Least Significant Bit (LSB), a Center Significant Bit (CSB) and a Most Significant Bit (MSB). The LSBs of the cells in the group are used for storing a certain page, the CSBs store a different page, and yet another page is stored in the MSBs. In these embodiments, the pages stored in different significance bits often have different error probabilities. Therefore, different significance bits can be read using different read commands. This selection can be performed either by the memory controller or by the memory device, as appropriate. 
     As yet another example, the R/W circuitry may program the memory cells using an iterative Program and Verify (P&amp;V) process. In a typical P&amp;V process, an entire memory page is written by applying a sequence of programming pulses to the group of memory cells that are mapped to this page. The amplitude of the programming pulses increases incrementally from pulse to pulse. The storage values programmed into the cells are read (“verified”) after each pulse, and the iterations continue until the desired levels are reached. Typically, programming verification can be performed successfully even if the storage values are read at a low accuracy. Thus, the R/W circuitry may read the storage values during verification reading tasks using a fast but low-accuracy command. 
     As another example, in some embodiments the memory device or the memory controller adjusts the read thresholds used in read operations, based on the statistical distribution of the storage values stored in the memory cells. For example, device  24  or controller  52  may perform one or more read operations for estimating the Cumulative Distribution Function (CDF) of the cell storage values, and then adjust the read thresholds based on the estimated CDF. Techniques of this sort are described, for example, in PCT International Publication WO 2008/111058, cited above. Typically, read operations performed in order to estimate the storage value distribution can be performed at low accuracy. 
     Further alternatively, the appropriate predefined read command for performing a certain readout task can be selected based on any other suitable condition. For example, two or more of the above-mentioned conditions can be combined. Although certain conditions are referred to above as being evaluated by the memory controller, the condition evaluation and/or command selection can be performed by the memory controller or by circuitry internal to the memory device, as desired. 
     In some embodiments, the memory controller configures the memory device so as to set various attributes of the read commands. The memory controller may configure any read command attribute, such as, for example, the number and values of read thresholds, sense times and/or interference cancellation parameters. The controller may configure attributes of a single read command, all commands or a subset of the commands. In some embodiments, the memory controller may estimate the impairments in the memory cells along the memory device&#39;s life cycle, and adapt the read command attributes accordingly. 
     Progressive Selection of Read Commands 
     In some embodiments, memory controller  52  initially reads data from memory device  24  using fast and limited-accuracy read commands. The memory controller reverts to higher-accuracy but slower read commands only if data readout fails. 
       FIG. 3  is a flow chart that schematically illustrates a method for retrieving data from analog memory cells  32  using read commands having different accuracy levels, in accordance with an embodiment of the present invention. The method begins by defining multiple read commands having respective different accuracy levels, at a definition step  80 . These commands are supported by both memory device  24  and memory controller  52 . 
     When preparing to read the storage values from a certain group of memory cells (e.g., to read a certain memory page), the memory controller initially selects the read command having the lowest accuracy, at an initial selection step  84 . This command typically has the shortest execution time. 
     The memory controller instructs the memory device to read a certain page using the currently-selected read command, at a reading step  88 . The memory device reads the requested page using this command and provides the read results to the memory controller. 
     The memory controller attempts to decode the ECC based on the read results provided by the memory device, in order to reconstruct the data, at an ECC decoding step  92 . The memory controller checks whether ECC decoding is successful, at a decoding checking step  96 . If successful, the memory controller output the reconstructed data to host  56 , at an output step  100 , and the method terminates. 
     If, on the other hand, ECC decoding has failed, the memory controller checks whether the currently-selected read command is the command having the highest accuracy, at an accuracy checking step  104 . If the currently-selected read command is the highest-accuracy command, the memory controller declares that the page read operation has failed, at a failure step  108 , and the method terminates. 
     Otherwise, the memory controller selects a different read command, whose accuracy is higher than that of the currently-selected command, at a selection update step  112 . The method then loops back to step  88  above, in which the memory controller reads the requested page using the newly-selected read command. The memory controller continues to read the requested page using read commands that progressively increase in accuracy, until ECC decoding is successful or until all predefined commands have been exhausted. 
     Using the progressive method of  FIG. 3 , the readout accuracy is matched to the actual characteristics of the page in question. The memory controller attempts to read the data using fast read commands first, and reverts to slower commands only if higher accuracy is needed. 
     When the memory controller re-reads a certain page using a high-accuracy command after failure of a lower-accuracy command, the memory controller can still use the results of the lower-accuracy command that failed. For example, the results of the lower-accuracy command can be combined with (or otherwise used to refine) the read results of the higher-accuracy command. Consider, for example, the above-mentioned configuration in which both the controller and the memory device are capable of performing interference cancellation. In such a configuration, the controller may initially read the page with a fast read command that performs no interference cancellation. If the ECC fails, the controller re-reads the page with a command that activates the memory device&#39;s interference cancellation mechanism. If the ECC fails again, the memory controller may apply both the memory device&#39;s and the memory controller&#39;s interference cancellation mechanisms. 
     In some embodiments, the memory device and memory controller support a command interface, using which the memory controller instructs the memory device to execute the appropriate read commands. Such commands may instruct the memory controller to apply a certain predefined read command (e.g., a command having a certain sense time), to activate or deactivate a certain signal processing mechanism implemented internally to the memory device, to set attribute values such as read thresholds or interference cancellation parameters, and/or to instruct the memory device to perform any suitable action or configure any suitable attribute in order to execute the read commands described herein. 
     Readout Configurations with Reduced Sense Time 
     In some embodiments, system  20  employs multiple readout configurations having different sense times, i.e., different time durations over which sense circuitry  40  measures the bit line voltages or currents during a read operation. When preparing to retrieve data from a certain group of memory cells, the system evaluates a certain condition, and selects the appropriate readout configuration based on this condition. Several examples of such readout configurations are described below. 
     Although the embodiments described below refer to two readout configurations—a normal configuration and a reduced-sense-time configuration—the disclosed techniques can be used with any other suitable number of readout configurations having different sense times. In some embodiments, memory controller  52  and memory device  24  support one or more readout commands using which the memory controller specifies the readout configuration to be used for retrieving certain data. In alternative embodiments, the memory device evaluates the condition and selects the appropriate readout configuration irrespective of the memory controller. 
       FIG. 4  is a flow chart that schematically illustrates a method for retrieving data from analog memory cells  32  with reduced sense time, in accordance with an embodiment of the present invention. The method begins with memory controller  52  accepting a request from host  56  to retrieve certain data, at a request step  120 . The data in question is stored in a certain group of memory cells  32 , e.g., in a certain page that belongs to a certain word line. 
     The memory controller holds a definition of two or more readout configurations that differ from one another in sense time. The present example refers to two readout configurations—a normal configuration and a reduced-sense-time configuration. The memory controller evaluates a condition that indicates whether the memory cell group in question is to be read using the normal or the reduced-sense-time readout configuration, at a condition evaluation step  124 . Any suitable condition can be used for this purpose. For example, the memory controller may use any of the above-described conditions used for selecting read commands. 
     If the memory cell group is to be read using a normal sense time, the memory controller sets memory device  24  to the normal readout configuration, at a normal setting step  128 . If, on the other hand, the memory cell group is to be read using a reduced sense time, the memory controller sets the memory device to reduced-sense-time readout configuration, at a reduced-time setting step  132 . The memory device then reads the memory cells in the group using the selected readout configuration, at a readout step  136 . The memory controller outputs the read data, at an output step  140 . 
     The embodiments described herein refer to a certain partitioning of tasks between the memory device and the memory controller. This choice, however, is made purely by way of example. In alternative embodiments, the tasks of evaluating the condition, selecting and setting the appropriate readout configuration and reading the memory cells can be divided in any desired way between the memory device and memory controller, or even performed exclusively by only one of them. 
     Typically, each of the memory cells belongs to a respective bit line. Readout is performed by pre-charging the bit lines, allowing them to discharge, and sensing the bit line currents or voltages after a certain discharge period. Thus, the sensed storage values depend on the bit line conductivity. In some of the disclosed techniques, the choice of readout configuration affects the electrical conductivities of the bit lines to which the memory cells in the group belong. Consequently, longer or shorter sense times can be set. 
     When the bit line conductivity is better (i.e., higher—meaning smaller bit line resistance), the bit line discharges at a faster rate and therefore can be sensed with a shorter sense time. When the bit line conductivity is poorer, the bit line discharges at a slower rate and therefore a longer sense time may be needed. Lower bit line conductivity is typically set only selectively, when possible or when required, because improving the bit line conductivity may degrade other system performance measures. 
     Various techniques can be used to selectively increase the bit line conductivity during readout. In some embodiments, the readout configurations differ from one another in the pass voltages (V PASS ) that are applied during readout to unselected word lines in the memory block, i.e., to the word lines other than the word line being read. In one embodiment, the normal readout configuration sets a certain default set of pass voltages. The reduced-sense-time readout configuration sets another set of pass voltages, at least one of which is higher than the corresponding pass voltage in the normal readout configuration. 
     Setting a higher pass voltage helps to improve the bit line conductivity, and therefore enables shorter sense time. On the other hand, increasing the pass voltage may increase the probability of over-programming, read disturb or other impairments. Therefore, this technique is typically used only selectively, e.g., when conditions permit, when other impairments are tolerable or when short sense time is particularly important. 
     In alternative embodiments, the readout configurations differ from one another in the read thresholds used for reading the group of memory cells. In one embodiment, the normal readout configuration sets a certain default set of (one or more) read thresholds. The reduced-sense-time readout configuration sets another set of read thresholds, at least one of which is higher than the corresponding read threshold in the normal readout configuration. 
       FIG. 5  is a graph showing programming levels in a group of analog memory cells and associated normal and reduced-sense-time read thresholds, in accordance with an embodiment of the present invention. The example of  FIG. 5  refers to a group of four-level, 2 bits/cell memory cells. After programming, the storage values (in the present example threshold voltages) of the memory cells are distributed in four programming level distributions  150 A . . .  150 D, which correspond to the four possible two-bit combinations. Device  24  typically retrieves the data stored in these memory cells by positioning three read thresholds between the programming level distributions, and comparing the cell storage values to the read thresholds. 
     In some embodiments, normal read thresholds  154  are marked in the figure with solid lines. Reduced-sense-time read thresholds  158  are marked in the figure with dashed lines. As can be seen in the figure, the reduced-sense-time read thresholds are higher than the respective normal read thresholds. 
     Increasing a given read threshold helps to improve the bit line conductivity, and therefore enables the use of shorter sense time. On the other hand, the reduced-sense-time read thresholds may increase the probability of read errors, since they are typically closer to the programming level distributions in comparison with the corresponding normal read thresholds. 
     In the example of  FIG. 5 , the normal read thresholds are positioned approximately at the mid-way points between adjacent programming level distributions. This setting typically yields low error probability. The reduced-sense-time read thresholds, on the other hand, are positioned at the upper edges of the boundary regions separating the adjacent programming level distributions. This setting is typically sub-optimal in terms of error probability, but may be preferred in some cases in order to improve bit line conductivity and enable short sense time. In some embodiments, the reduced-sense-time read thresholds may be positioned even further higher, slightly within the programming level distributions. This setting further shortens sense time at the expense of read errors (which can be corrected, for example, using an error correction code). 
     In some embodiments, memory controller  52  sets the sense time for reading a certain word line depending on the number of other word lines in the same block that are programmed with data. The rationale behind this technique is that erased (non-programmed) memory cells improve the bit line conductivity, whereas programmed memory cells degrade it. When a memory block has only a small number of programmed word lines, the conductivity of the bit lines in the block is typically good, and it is typically possible to read the desired word line with a short sense time. If, on the other hand, the block has many programmed word lines (i.e., few erased cells per bit line), the bit line conductivities may be poorer and a longer sense time may be needed. 
     It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Metadata:
Filing Date: 20110822
Publication Date: 20130319
Grant Date: 20130319
Priority Date: 20080318
Inventors: MEIR AVRAHAM
SOMMER NAFTALI
GURGI EYAL
Assignee: APPLE INC
CPC Classifications: [{"code": "G11C8/12", "inventive": true, "first": true, "tree": "[]"}, {"code": "G11C27/005", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C27/005", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C13/004", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/26", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/349", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/26", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C29/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C29/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C13/0061", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C13/0061", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C11/5642", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/349", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C8/12", "inventive": true, "first": true, "tree": "[]"}, {"code": "G11C2211/5641", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C13/0035", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C11/5642", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C13/004", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C13/0035", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C2211/5641", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 47353557