PATENT DOCUMENT

Publication Number: US-10715094-B2
Application Number: US-201916538887-A
Country: US
Kind Code: B2

Title: Amplification circuit, apparatus for amplifying, low noise amplifier, radio receiver, mobile terminal, base station, and method for amplifying

Abstract:
Embodiments provide an amplification circuit, an apparatus for amplifying, a low noise amplifier, a radio receiver, a mobile terminal, a base station, and a method for amplifying. An amplification circuit for amplifying a radio signal comprises a first amplification stage configured to amplify an input signal, Vin(t), to obtain an intermediate signal. The amplification circuit further comprises a cascoding circuit configured to amplify the intermediate signal to obtain a first output signal Voutn(t). The amplification circuit further comprises a second amplification stage configured to amplify the intermediate signal to obtain a second output signal, Voutp(t).

Claims:
What is claimed is: 
     
       1. An amplification circuit for amplifying a radio signal, comprising
 a first amplification stage configured to amplify an input signal to generate an intermediate signal; 
 a cascoding circuit configured to amplify the intermediate signal to generate a first output signal; and 
 a second amplification stage configured to amplify the intermediate signal to generate a second output signal; 
 wherein each of the first amplification stage, the cascoding circuit, and the second amplification stage comprises at least two transistors of different channel types, 
 a first transistor of the first amplification stage is configured to couple to a negative power supply voltage or a reference potential, 
 the first transistor of the first amplification stage is coupled to a first transistor of the cascoding circuit, 
 the first transistor of the cascoding circuit is coupled to a second transistor of the cascoding circuit, 
 the second transistor of the cascoding circuit is coupled to a second transistor of the first amplification stage, 
 the second transistor of the first amplification stage is configured to couple to a positive power supply voltage, 
 the input terminals of the first and second transistors of the first amplification stage are configured to receive the input signal, and 
 input terminals of the first and second transistor of the cascoding circuit are configured to couple to the reference potential, 
 wherein the first transistor of the first amplification stage is configured to couple to the negative power supply voltage or the reference potential through a first resistor and the second transistor of the first amplification stage is configured to couple to the positive power supply voltage through a second resistor. 
 
     
     
       2. The amplification circuit of  claim 1 , wherein the first amplification stage comprises a push-pull stage cascoded with the cascoding circuit. 
     
     
       3. The amplification circuit of  claim 1 , wherein the first output signal and the second output signal form a differential output of the amplification circuit. 
     
     
       4. The amplification circuit of  claim 1 , wherein the input signal is coupled to an input terminal of the first transistor of the first amplification stage through at least one capacitor, and the input signal is coupled to an input terminal of the second transistor of the first amplification stage through at least one other capacitor. 
     
     
       5. The amplification circuit of  claim 1 , wherein an input terminal of the first transistor of the cascoding circuit is coupled to the reference potential through at least one capacitor, and an input terminal of the second transistor of the cascoding circuit is coupled to the reference potential through at least one other capacitor. 
     
     
       6. The amplification circuit of  claim 1 , wherein the second amplification stage comprises a second push-pull stage configured to amplify the intermediate signal. 
     
     
       7. The amplification circuit of  claim 6 , wherein
 a first transistor of the second amplification stage is coupled to a negative power supply voltage or a reference potential, 
 a second transistor of the second amplification stage is coupled to a positive power supply voltage, 
 the first transistor of the second amplification stage is coupled to the first transistor of the first amplification stage and to the first transistor of the cascoding circuit, and 
 the second transistor of the second amplification stage is coupled to the second transistor of the first amplification stage and to the second transistor of the cascoding circuit. 
 
     
     
       8. The amplification circuit of  claim 7 , wherein input terminals of the first and second transistors of the second amplification stage are coupled by at least one capacitor. 
     
     
       9. The amplification circuit of  claim 7  wherein an input terminal of the first transistor of the second amplification stage is coupled to the intermediate signal through at least one capacitor, and an input terminal of the second transistor of the second amplification stage is coupled to the intermediate signal through at least one other capacitor. 
     
     
       10. The amplification circuit of  claim 7  wherein the first transistor of the second amplification stage is coupled to the negative power supply voltage or the reference potential through at least one resistor and the second transistor of the second amplification stage is coupled to the positive power supply voltage through at least one another resistor. 
     
     
       11. The amplification circuit of  claim 1 , wherein one of the first amplification stage and the second amplification stage is an inverting amplification stage and the other is a non-inverting amplification stage. 
     
     
       12. The amplification circuit of  claim 1 , wherein the at least two transistors of the first amplification stage, the cascoding circuit, and the second amplification stage are two metal-oxide-semiconductor field effect transistors (MOSFETs) with different channel types. 
     
     
       13. The amplification circuit of  claim 1 , wherein the input signal is coupled to a drain terminal of the first transistor of the cascoding circuit and a drain terminal of the second transistor of the cascoding circuit through a resistor and a capacitor. 
     
     
       14. The amplification circuit of  claim 1 , wherein the input signal is a single-ended signal. 
     
     
       15. A method for amplifying a radio signal, comprising:
 amplifying an input signal with a first amplification stage to generate an intermediate signal; 
 amplifying the intermediate signal with a cascading circuit to generate a first output signal; and 
 amplifying the intermediate signal with a second amplification stage to generate a second output signal, 
 wherein each of the first amplification stage, the cascoding circuit, and the second amplification stage comprises at least two transistors of different channel types, 
 a first transistor of the first amplification stage is coupled to a negative power supply voltage or a reference potential, 
 the first transistor of the first amplification stage is coupled to a first transistor of the cascoding circuit, 
 the first transistor of the cascoding circuit is coupled to a second transistor of the cascoding circuit, 
 the second transistor of the cascoding circuit is coupled to a second transistor of the first amplification stage, 
 the second transistor of the first amplification stage is coupled to a positive power supply voltage, and 
 the input signal is coupled to a drain terminal of the first transistor of the cascoding circuit and a drain terminal of the second transistor of the cascoding circuit through a resistor and a capacitor, 
 wherein the first transistor of the first amplification stage is coupled to the negative power supply voltage or the reference potential through a first resistor and the second transistor of the first amplification stage is coupled to the positive power supply voltage through a second resistor. 
 
     
     
       16. The method of  claim 15 , wherein the first amplification stage comprises a push-pull stage cascoded with the cascoding circuit. 
     
     
       17. The method of  claim 15 , wherein the first output signal and the second output signal form a differential output. 
     
     
       18. A mobile terminal comprising the amplification circuit of  claim 1 .

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 15/593,347 filed on May 12, 2017, which claimed priority to European Application 16174226.7 filed on Jun. 13, 2016. The contents of the earlier filed applications are incorporated by reference herein in their entirety. 
    
    
     FIELD 
     Examples relate to amplification of signals and in particular, but not exclusively, to low noise amplification reusing a single ended low noise current signal to obtain an amplified differential output signal. 
     BACKGROUND 
     Many receivers use Low Noise Amplifiers (LNA) to enhance receive signal levels prior to further signal processing. For example, an LNA may be coupled to a receive antenna with potential filter circuitry in between. The LNA at an input of Radio Frequency (RF) receivers may be considered essential for any modern transceiver with challenging sensitivity requirements. Fully differential LNAs (outputting differential signals, basically two signals with opposite polarity) may be used because they can be connected with a double balance mixer which inherently possesses lower second order nonlinearity than single balance mixers, and may also effectively suppress any kind of common mode noise sourcing from supply or ground. 
     Because of the increasing amount of RF input ports in a transceiver, most multi-mode and multi-band transceivers use single-ended LNAs with single ended outputs potentially saving input balls and chip area. Therefore, single balance mixers are utilized which increases the second order nonlinearity of mixers and causing, at least in some cases, a complex mixer calibration, further utilization of bulky and large blocking capacitors for supplies noises, respectively. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which 
         FIG. 1  illustrates an example of an amplification circuit or amplification device, and an example of a low noise amplifier; 
         FIG. 2  shows another example of an amplification circuit or amplification device; 
         FIG. 3  illustrates examples of a radio transceiver, a mobile transceiver and a base station transceiver; 
         FIG. 4  shows a block diagram of an example of a method for amplifying; and 
         FIG. 5  shows a diagram of an example mobile transceiver. 
     
    
    
     DETAILED DESCRIPTION 
     Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity. 
     Accordingly, while further examples are capable of various modifications and alternative forms, some examples thereof are shown by way of example in the figures and will herein be described in detail. It should be understood, however, that there is no intent to limit examples to the particular forms disclosed, but on the contrary, examples are to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
     The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of further examples. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which examples belong. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, unless expressly defined otherwise herein. 
     In the following some examples will be described. Some examples introduce a single ended low noise amplifier with build in active balun functionality to generate a differential output, enabling the application of double balance mixer. Examples may hence further enable having reduced second order nonlinearity compared to a single balanced mixer. 
       FIG. 1  illustrates an example of an amplification circuit or amplification device, and an example of a low noise amplifier.  FIG. 1  shows an amplification circuit  10  for amplifying a radio or input signal.  FIG. 1  further illustrates an LNA  100  comprising the amplification circuit  10  (shown in dotted lines as it may comprise further components besides the example of the amplification circuit). 
     In examples an LNA may be used at the RF frontend of a receiver, e.g. being coupled to one or more receive antennas with its input, with optional filter circuitry, a diplexer, a duplexer in between, respectively. Signal level at an LNA input can be assumed to be very low power and noisy. It is therefore one design goal for LNAs to add as low additional noise power to the input signal as possible in order to keep a Signal-to-Noise-Ratio (SNR) of an output signal as high as possible. 
     As shown in  FIG. 1  the amplification circuit  10  comprises a first amplification stage  12 , which is configured to amplify the input signal, V in (t), to obtain an intermediate signal. The amplification circuit further comprises a cascoding circuit  14 , which is configured to amplify the intermediate signal to obtain a first output signal V outn (t). The amplification circuit  10  further comprises a second amplification stage  16  configured to amplify the intermediate signal to obtain a second output signal, V outp (t). 
     In the example depicted in  FIG. 1  a single-ended LNA with a differential-good balanced-output signal but minimal additional current consumption may be implemented without sacrificing linearity or noise figure of the LNA. The first and second output signals, V outn (t), V outp (t), may then form a differential output of the amplifier circuit  10 . The differential output may correspond to two signals with differing phases, e.g. the phase may differ by 90, 120, 150, 160, 170, 180 degrees, although a differential signal may per definition only the 180 degrees out of phase signal portion, (V outp (t)−V outn (t))/2, hence, while theoretically the signal components of a differential signal may have a phase shift of 180 degrees, in examples this may only be approximately true. In a further example one of the first amplification stage  12  and the second amplification stage  16  is an inverting amplification stage and the other is a non-inverting amplification stage. Because of one amplification stage being inverting but not the other, a phase shift of approximately 180 degrees or within the above boundaries may be achieved between the two output signals. 
       FIG. 1  also illustrates an apparatus  10  for amplifying a radio signal. The apparatus comprises first means  12  for amplifying an input signal, V in (t), to obtain an intermediate signal. The apparatus  10  further comprises cascoding means  14  for amplifying the intermediate signal to obtain a first output signal, V outn (t). The apparatus  10  further comprises second means  16  for amplifying the intermediate signal from the cascoding means  14  to obtain a second output signal, V outp (t). The amplifying means, cascoding means, amplifier stages or cascoding circuits may correspond to any one or more amplifier devices, units or modules, for which different variants are conceivable. For example, transistor circuits may be used. The first and second output signals, V outn n(t), V outp (t), may form a differential output of the amplifier device  10 , in line with the above. One of the first means  12  for amplifying and the second means  16  for amplifying is an inverting amplification stage and the other is a non-inverting amplification stage in another example. 
     In an example, the circuit  10  or device  10  generates a differential output without using a passive transformer that could be very bulky and area costly. Additionally compared to a conventional active balun comprised of two branches, in case of a common-source and a common gate amplification stage for Field Effect Transistor (FET) circuits, an example may merely utilize two common source stages. Because of that a noise figure of an example LNA may be untouched and as good as a common source LNA. Further examples may build the out of phase signal with only one additional amplifying branch, compared to conventional active balun using two additional branches. Examples may save additional current consumption. 
       FIG. 2  shows another example of an amplification circuit  10  or amplification device  10 . In this example the amplification stages or means are implemented using transistors, where the circuit shown in  FIG. 2  will be explained in detail subsequently. The example of  FIG. 2  comprises similar functional components as the example depicted in  FIG. 1 , namely a first amplification stage  12 , a second amplification stage  16 , and a cascoding circuit  14 . In the example shown in  FIG. 2  Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are used, which is an example. In further examples other types of transistors may be used as well. Other types of transistors are FET, bipolar transistors, Bipolar Junction Transistor (BJT), etc. 
     As shown in  FIG. 2  the first amplification stage  12  comprises a push-pull stage cascoded with the cascoding circuit  14 . As shown in  FIG. 2  the two transistors are set up to alternately provide current, using a complementary set of transistors, which is referred to as push-pull concept. The first amplification stage  12  comprises a first push-pull stage cascoded with the cascoding circuit  14 , and the second amplification stage  16  comprises a second push-pull stage configured to amplify the intermediate signal. 
     The cascoding circuit  14  may correspond to another amplifier stage, however, in a different configuration compared to the first amplification stage  12 , as shown in  FIG. 2 . The transistors of the cascoding circuit  14  are in common gate configuration while the transistors of the first amplification stage  12  are in common source configuration. The cascoding circuit  14  may also be referred to as a transconductance amplifier followed by a current buffer. The cascoding circuit  14  may in the configuration with the first amplification stage  12  provide higher input-output isolation (transconductance), higher input impedance, high output impedance, higher gain and/or higher bandwidth. The current generated by the first amplification stage  12  is converted into a voltage signal by the cascoding circuit  14  in the example shown in  FIG. 2 . The cascode corresponds to a cascade of the cathode and may achieve a high input impedance (input signal V in (t) is coupled to the gate connectors of the transistors in  FIG. 2 , which is biased with certain reference voltage). The cascode may further achieve very low coupling between the input and the output. Moreover, as the cascoding circuit is in common gate configuration. Because at operating frequencies the gate is effectively grounded, the source voltage (and therefore the input transistor&#39;s drain) is held at nearly constant voltage during operation. In other words, the cascoding transistor experiences a low input resistance to the transistor of the first amplification stage  12 , making the voltage gain of the amplification transistor small, which may reduce a Miller feedback capacitance from drain to gate of the transistors of the amplification stage. This loss of voltage gain may be recovered by the cascoding transistor. Thus, the cascoding transistor may allow the transistor of the amplification stage to operate with reduced Miller feedback, which may improve its bandwidth. 
     In the example depicted in  FIG. 2 , the first amplification stage  12  comprises at least two transistors, M 1N , M 1P , which are coupled in a push-pull arrangement. The cascoding circuit  14  comprises at least two transistors, M 2N , M 2P  in the example of  FIG. 2 , which are coupled in a push-pull arrangement between the at least two transistors, M 1N , M 1P , of the first amplification stage  12 . Furthermore, the at least two transistors, M 1N , M 1P , of the first amplification stage  12  are two MOSFETs with different channel types. M 1N , M 1P  are hence complementary in the present example. The at least two transistors, M 2N , M 2P , of the cascoding circuit  14  are also two (complementary) MOSFETs with different channel types. 
     As further shown in the example a first transistor, M 1N , of the first amplification stage  12  is coupled to a reference potential or negative power supply voltage. In some examples the reference potential may correspond to ground, in other examples the negative power supply may be a symmetrical voltage as compared to a positive power supply voltage and differ in its negative polarization. A second transistor, M 1P , of the first amplification stage  12  is coupled to a positive supply voltage. A first transistor, M 2N , of the cascoding circuit  14  is coupled to the first transistor, M 1N , of the first amplification stage  12 . The first transistor, M 2N , of the cascoding circuit  14  is coupled to a second transistor, M 2P , of the cascoding circuit  14 , and the second transistor, M 2P , of the cascoding stage  14  is coupled to the second transistor, M 1P , of the first amplification stage  12 . 
     Moreover, the second amplification stage  16  comprises a push-pull stage comprising at least two transistors, M 3N , M 3P , as shown in the example in  FIG. 2 . The at least two transistors, M 3N , M 3P , of the second amplification stage  16  are two (complementary) MOSFETs with different channel types. The at least two transistors, M 3N , M 3P , of the second amplification stage  16  are coupled to each other in a push-pull arrangement and may be considered parallel with respect to an output terminal, wherein a first transistor, M 3N , of the second amplification stage  16  is coupled to a negative power supply voltage or a reference potential in line with the above. A second transistor, M 3P , of the second amplification stage  16  is coupled to a positive power supply voltage. 
     In the circuit depicted in the example of  FIG. 2  the second amplification stage  16  comprises a push-pull stage comprising two transistors, M 3N , M 3P . The two transistors, M 3N , M 3P , of the second amplification stage  16  are coupled to each other in a push-pull arrangement. A first transistor, M 3N , of the second amplification stage  16  is coupled to a negative power supply voltage or a reference potential, and a second transistor, M 3P , of the second amplification stage  16  is coupled to a positive power supply voltage. The first transistor, M 3N , of the second amplification stage  16  is coupled to the first transistor, M 1N , of the first amplification stage  12  and to the first transistor, M 2N , of the cascoding circuit  14 . The second transistor, M 3P , of the second amplification stage  16  is coupled to the second transistor, M 1P , of the first amplification stage  12  and to the second transistor, M 2P , of the cascoding circuit. 
     In more detail, in an example the first amplification stage  12  comprises at least two MOSFETs, a first MOSFET, M 1N , of n-channel type and a second MOSFET, M 1P , of p-channel type. The cascoding circuit  14  also comprises at least two MOSFETs, a first MOSFET, M 2N , of n-channel type and a second MOSFET, M 2P , of p-channel type. Each of the MOSFETs, M 1N , M 1P , M 2N , and M 2P  comprises at least a gate, a source and a drain connector. These connectors are shown in  FIG. 2  by the respective letters, “G”, “D”, and “S”. In the example of  FIG. 2  a source connector of the first MOSFET, M 1N , of the first amplification stage  12  is coupled to a negative power supply voltage or a reference potential, in line with the above. A drain connector of the first MOSFET, M 1N , of the first amplification stage  12  is coupled to a source connector of the first MOSFET, M 2N , of the cascoding circuit  14 . A drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  is coupled to a drain connector of the second MOSFET, M 2P , of the cascoding circuit  14 . A source connector of the second MOSFET, M 2P , of the cascoding circuit  14  is coupled to a drain connector of the second MOSFET, M 1P , of the first amplification stage  12 . A source connector of the second MOSFET, M 1P , of the first amplification stage  12  is coupled to a positive power supply voltage. 
     As further shown in  FIG. 2  the source connector of the first MOSFET, M 1N , of the first amplification stage  12  is coupled to the negative power supply voltage or the reference potential through at least one resistor, R S1N , which may allow tuning or biasing the source potential of M 1N . The source connector of the second MOSFET, M 1P , of the first amplification stage  12  is coupled to the positive power supply voltage through at least another resistor, R S1P , which may allow for resistive source degradation of the amplification circuit  10  to increase the linearity and which may be programmed in demand. The input signal V in (t) is coupled to the gate connectors of the first and second MOSFETs, M 1N  and M 1P , of the first amplification stage  12 . Gate connectors of the first and second MOSFETs, M 2N  and M 2P , of the cascoding circuit  14  are coupled to a reference potential, which may be ground in an example, or supply voltage in NMOS (n-type MOS) case, respectively. It is to be noted that biasing of the amplifier stages and the cascoding circuits can be applied separately. In other words, depending on the transistor type and implementation, to all of the gates as shown in  FIG. 2  certain potentials may be applied to tune the circuit to the required needs. Such potentials may be equal or different, in some examples each gate may be biased to a different potential. 
     In the example of  FIG. 2  the input signal is coupled to the gate connector of the first MOSFET, M 1N , of the first amplification stage  12  through at least one capacitor, C 1N , which may also be chosen according to the actual requirements, e.g. bandwidth or frequency of a desired receive signal. The input signal is further coupled to the gate connector of the second MOSFET, M 1P , of the first amplification stage  12  through at least one other capacitor, C 1P . In examples the capacitors C 1N  and C 1P  may have the same or different capacities. 
     The gate connector of the first MOSFET, M 2N , of the cascoding circuit  14  is coupled to the reference potential through at least one capacitor, C 2N . The gate connector of the second MOSFET, M 2P , of the cascoding circuit  14  is coupled to the reference potential through at least one other capacitor, C 2P . These capacitors may filter any modulation into the reference potential, just as radio frequency shortening of the gates. The reference potentials for gate biasing are connected directly to the gates. In examples the capacitors C 2N  and C 2P  may have the same or different capacities, in some examples they may even equal the capacitors C 1N  and C 1P . 
     The second amplification circuit  16  may comprise at least two MOSFETs, a first MOSFET, M 3N , of n-channel type and a second MOSFET, M 3P , of p-channel type in the example of  FIG. 2 . Each of the MOSFETs, M 3N , M 3P , of the second amplification stage  16  comprises at least a gate, a source and a drain connector. A source connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to a negative power supply voltage or a reference potential, in line with the above. A drain connector of the first MOSFET, M 3N , of the second amplification stage is coupled to a drain connector of the second MOSFET, M 3P , of the second amplification stage  16 . A source connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to a positive power supply. The source connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the negative power supply voltage or the reference potential through at least a resistor, R S2N , which allows for resistive source degradation of MOSs. 
     The source connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the positive power supply voltage through at least another resistor, R S2P , which allows for resistive source degradation of MOSs. A gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the drain connector of the first MOSFET, M 1N , of the first amplification stage  12 . The gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the source connector of the first MOSFET, M 2N , of the cascoding circuit  14 . In this example the intermediate signal corresponds to a current signal as output by the first amplification stage  12 . The current signal is the input of the cascoding circuit  14  and a voltage signal, which is evoked by the current signal being applied to the cascoding circuit  14  is input into the second amplification stage  16 . The input impedance of the second amplification stage  16  is high (two gate connectors) which is why the current output by the first amplification stage  12  flows through the cascoding circuit  14 . Likewise, a gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the drain connector of the second MOSFET, M 1P , of the first amplification stage  12 , and the gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the source connector of the second MOSFET, M 2P , of the cascoding circuit  14 . 
     As further shown in  FIG. 2  the gate connectors of the first and second MOSFETs, M 3N  and M 3P , of the second amplification stage  16  are coupled by at least one capacitor, C AC . This capacitor can be used to shorten or attenuate certain high frequencies at the input of the second amplification stage  16 . The capacitor can also be used balance gains for the output signals V outn (t) and V outp (t), which form a differential output pair. The gain of the first output is influenced by the first amplification stage  12  (common source with higher gain) and the cascoding circuit  14  (common gate with lower gain). The gain of the second output signal V outp (t) is influenced by the gain of the second amplification stage  16  (common source with high gain) and the capacitor C AC . By tuning the capacitor C AC  the gains or symmetry of the differential output signal (first and second output signals) can be tuned. 
     Furthermore, the gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the drain connector of the first MOSFET, M 1N , of the first amplification stage  12  through at least one capacitor, C 3N . The gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the source connector of the first MOSFET, M 2N , of the cascoding circuit  14  through the capacitor, C 3N . Therewith the second amplification stage  16  is decoupled with respect to DC (Direct Current) from the first amplification stage  12  and the cascoding circuit  14 . It should be noted that the capacitor C 3N  and also the capacitor C 3P  as will be introduced subsequently, may also influence a gain for the second output signal V outp (t) with their relation to the capacitor C AC . As shown in the example, the gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the drain connector of the second MOSFET, M 1P , of the first amplification stage  12  through at least another capacitor, C 3P . The gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is also coupled to the source connector of the second MOSFET, M 2P , of the cascoding circuit  14  through the other capacitor, C 3P . For example, the capacitors C 3N  and C 3P  may have the same capacity. In some examples they may as well have different capacities. 
     The first output signal is provided by the drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  and the drain connector of the second MOSFET, M 2P , of the cascoding circuit  14 . The second output signal is provided by the drain connector of the first MOSFET, M 3N , of the second amplification stage  16  and the drain connector of the second MOSFET, M 3P , of the second amplification stage  16 . The input signal is coupled to the drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  and the drain connector of the second MOSFET, M 2P , of the cascoding circuit  14 . The input signal is coupled to the drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  and the drain connector of the second MOSFET, M 2P , of the cascoding circuit  14  through at least a resistor, R FB , and a capacitor, C FB . In the example of  FIG. 2  the resistor, R FB , and the capacitor, C FB  allow setting an input impedance or transconductance of the amplification circuit  10 . The amplification circuit can be part of an LNA  100  in an example, cf.  FIG. 1   
     The topology of the example LNA in  FIG. 2  is neglecting the biasing circuitry. As already indicated above, in an application or implementation the gates of the transistors may be biased using a certain DC potential in order to fine tune the amplification stages  12 ,  16  and the cascoding circuit to the respective application. In the example of  FIG. 2  the first stage  12  comprises a push-pull stage M 1N , M 1P  Metal Oxide Semiconductor (MOS) transistors and the cascoding circuit comprises M 2N , M 2P  MOS transistors. A resistive and capacitive feedback, R FB  and C FB , supplies for the required input impedance matching. The output of that branch is directly fed to LNA output V outn (t). 
     The out of phase signal is generated by the second push-pull stage  16  comprising MOS transistors M 3P , M 3N . The input signal of second stage is created in particular way. It is derived from the output of gm (transconductance) stages of the first push-pull stage  12 , M 1N  and M 1P , respectively. Both signals are AC (Alternating current) shortened with capacitor C AC  to a single input signal for the second stage  16 , M 3N , M 3P . This may essentially improve the phase balancing behavior of the LNA. The output of the second push-pull stage  16  is finally fed to V outp (t) of the LNA. The cascoding stage  14  in the first stage  12 , M 2N , M 2P  results in low or even minimal isolation between the two stages  12 ,  14  in a current-consumption neutral way, additionally they can be used to match the gain of V outn (t) with V outp (t) branch to ensure good amplitude balance between two branches. Further gain matching can be achieved by adjusting the source degenerating resistors in the first and second amplification stages, R S1N , R S1P , R S2N , and R S2P . 
     Since creation of the output differential signal is accomplished after the input push-pull stage M 1N  and M 1P , the noise figure of this structure may be as good as that of a conventional single ended LNA, but outperforming a conventional active balun in noise figure and current consumption. 
     Further examples are shown in  FIG. 3 .  FIG. 3  illustrates examples of a radio receiver  200 ,  300  in general, a mobile transceiver  200  and a base station transceiver  300 .  FIG. 3  shows an example of a mobile transceiver  200  comprising an example of an LNA  100   a .  FIG. 3  further shows an example of base station transceiver  300  comprising another example of an LNA  100   b . The mobile transceiver  200  and the base station transceiver  300  from a mobile communication system, which is another example. The mobile communication system may correspond, for example, to one of the Third Generation Partnership Project (3GPP)-standardized mobile communication networks, where the term mobile communication system is used synonymously to mobile communication network. The mobile or wireless communication system may correspond to a mobile communication system of the 5th Generation (5G) and may use mm-Wave technology. The mobile communication system may correspond to or comprise, for example, a Long-Term Evolution (LTE), an LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM) or Enhanced Data rates for GSM Evolution (EDGE) network, a GSM/EDGE Radio Access Network (GERAN), or mobile communication networks with different standards, for example, a Worldwide Inter-operability for Microwave Access (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11, generally an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc. 
     A base station or base station transceiver  300  can be operable to communicate with one or more active mobile transceivers  200  and a base station transceiver  300  can be located in or adjacent to a coverage area of another base station transceiver, e.g. a macro cell base station transceiver or small cell base station transceiver. Hence, examples may provide a mobile communication system comprising one or more mobile transceivers  200  and one or more base station transceivers  300 , wherein the base station transceivers  300  may establish macro cells or small cells, as e.g. pico-, metro-, or femto cells. A mobile transceiver  200  may correspond to a smartphone, a cell phone, user equipment, a laptop, a notebook, a personal computer, a Personal Digital Assistant (PDA), a Universal Serial Bus (USB)-stick, a car, etc. A mobile transceiver  200  may also be referred to as User Equipment (UE) or mobile in line with the 3GPP terminology. 
     A base station transceiver  300  can be located in the fixed or stationary part of the network or system. A base station transceiver  300  may correspond to a remote radio head, a transmission point, an access point, a macro cell, a small cell, a micro cell, a femto cell, a metro cell etc. A base station transceiver  300  can be a wireless interface of a wired network, which enables transmission of radio signals to a UE or mobile transceiver  200 . Such a radio signal may comply with radio signals as, for example, standardized by 3GPP or, generally, in line with one or more of the above listed systems. Thus, a base station transceiver  300  may correspond to a NodeB, an eNodeB, a Base Transceiver Station (BTS), an access point, a remote radio head, a transmission point etc., which may be further subdivided in a remote unit and a central unit. 
       FIG. 4  shows a block diagram of an example of a method for amplifying. The method for amplifying a radio signal obtained at an input to provide an amplified signal at an output comprises amplifying  22  an input signal, V in (t), to obtain an intermediate signal. The method further comprises cascoding  24  the intermediate signal to obtain a first output signal, V outn (t), and amplifying  26  the intermediate signal to obtain a second output signal, V outp (t). The first and second output signals, V outn (t), V outp (t), form a differential output of the amplifier circuit  10 . The amplifying  22  of the input signal or the amplifying of the intermediate signal further may comprise inverting the input signal. In an example the amplification stage  12  comprises a push-pull stage, and the cascoding comprises cascoding the push-pull stage. The amplifying  22  of the input signal may use a first push-pull stage, the cascoding  24  may refer to the first push-pull stage, and the amplifying  26  of the intermediate signal, may use a second push-pull stage. 
     In another example, the amplifying  22  of the input signal uses a first amplification stage  12 , which comprises at least two transistors, M 1N , M 1P , being coupled in a push-pull arrangement, and the cascoding  24  uses at least two transistors, M 2N , M 2P , being coupled in a push-pull arrangement between the transistors, M 1N , M 1P , of the first amplification stage  12 . In some examples, the at least two transistors, M 1N , M 1P , of the first amplification stage  12  are two MOSFETs with different channel types. The at least two transistors, M 2N , M 2P , used by the cascoding may be two MOSFETs with different channel types. In a further example the method may further comprise coupling a first transistor, M 1N , of the first amplification stage  12  to a negative power supply voltage or reference potential and coupling a second transistor, M 1P , of the first amplification stage  12  to a positive supply voltage. 
     The method may further comprise coupling a first transistor, M 2N , for cascoding to the first transistor, M 1N , of the first amplification stage  12 , and coupling the first transistor, M 2N , for cascoding to a second transistor, M 2P , for cascoding. The method may further comprise coupling the second transistor, M 2P , for cascoding to the second transistor, M 1P , of the first amplification stage  12 . The amplifying  26  of the intermediate signal may use a push-pull stage comprising at least two transistors, M 3N , M 3P . The at least two transistors, M 3N , M 3P , may be two MOSFETs with different channel types being comprised in a second amplification stage  16 . The method for amplification may further comprise coupling the at least two transistors, M 3N , M 3P , of the second amplification stage  16  to each other in a push-pull arrangement, further comprising coupling a first transistor, M 3N , of the second amplification stage  16  to a negative power supply voltage or reference potential, and coupling a second transistor, M 3P , of the second amplification stage  16  to a positive power supply voltage. 
     In line with the example explained with respect to  FIG. 2  the method may further comprise coupling the two transistors, M 3N , M 3P , of the second amplification stage  16  to each other in a push-pull arrangement, and coupling a first transistor, M 3N , of the second amplification stage  16  to a negative power supply voltage or reference potential. The method may further comprise coupling a second transistor, M 3P , of the second amplification stage  16  to a positive power supply voltage, and coupling the first transistor, M 3N , of the second amplification stage  16  to the first transistor, M 1N , of the first amplification stage  12  and to the first transistor, M 2N , for cascoding. The method may further comprise coupling the second transistor, M 3P , of the second amplification stage  16  to the second transistor, M 1P , of the first amplification stage  12  and to the second transistor, M 2P , for cascoding. 
       FIG. 5  shows a diagram of an example mobile transceiver  200 , which comprises an RF processing part  200   a , a baseband processor module  170  and a power supply module  180 . As exemplified in  FIG. 5  an antenna is coupled to the RF-processing part  200   a , which comprises an example of an LNA  100   a . The LNA  100   a  comprises an example of the above described amplification circuit. It is to be noted that the RF-processing part  200   a  may comprise further filters or RF components, e.g. input filters, RF-band filters, intermediate filters, output filters, diplexers, duplexers, etc. The output of the LNA  100   a  is then down-converted by the converter  110  and filtered by filter  120 —again there may be further components involved. The output of the filter  120  is then provided to the baseband processor module  170 . The baseband processor module  170  is configured to further process the baseband receive signal. Additionally, the mobile transceiver comprises a power supply unit  180  supplying at least the RF-processing part and the baseband processor module  170  with power. 
     The examples as described herein may be summarized as follows: 
     A first example is an amplification circuit  10  for amplifying a radio signal comprising a first amplification stage  12  configured to amplify an input signal, V in (t), to obtain an intermediate signal. The circuit  10  further comprises a cascoding circuit  14  configured to amplify the intermediate signal to obtain a first output signal V outn (t), and a second amplification stage  16  configured to amplify the intermediate signal to obtain a second output signal, V outp (t). 
     In example 2 the first and second output signals, V outn (t), V outp (t), form a differential output of the amplifier circuit  10 . 
     In example 3 one of the first amplification stage  12  and the second amplification stage  16  is an inverting amplification stage and the other is a non-inverting amplification stage. 
     In example 4 the first amplification stage  12  comprises a push-pull stage cascoded with the cascoding circuit  14 . 
     In example 5 the first amplification stage  12  comprises a first push-pull stage cascoded with the cascoding circuit  14 , and the second amplification stage  16  comprises a second push-pull stage configured to amplify the intermediate signal. 
     In example 6 the first amplification stage  12  comprises at least two transistors, M 1N , M 1P , being coupled in a push-pull arrangement, and the cascoding circuit  14  comprises at least two transistors, M 2N , M 2P , being coupled in a push-pull arrangement between the at least two transistors, M 1N , M 1P , of the first amplification stage  12 . 
     In example 7 the at least two transistors, M 1N , M 1P , of the first amplification stage  12  are two MOSFETs, Metal-Oxide-Semiconductor Field-Effect Transistors, with different channel types. 
     In example 8 the at least two transistors, M 2N , M 2P , of the cascoding circuit  14  are two MOSFETs with different channel types. 
     In example 9 a first transistor, M 1N , of the first amplification stage  12  is coupled to a reference potential or negative power supply voltage and wherein a second transistor, M 1P , of the first amplification stage  12  is coupled to a positive supply voltage. 
     In example 10 a first transistor, M 2N , of the cascoding circuit  14  is coupled to the first transistor, M 1N , of the first amplification stage  12 , the first transistor, M 2N , of the cascoding circuit  14  is coupled to a second transistor, M 2P , of the cascoding circuit  14 , and the second transistor, M 2P , of the cascoding stage  14  is coupled to the second transistor, M 1P , of the first amplification stage  12 . 
     In example 11 the second amplification stage  16  comprises a push-pull stage comprising at least two transistors, M 3N , M 3P . 
     In example 12 the at least two transistors, M 3N , M 3P , of the second amplification stage  16  are two MOSFETs with different channel types. 
     In example 13 the at least two transistors, M 3N , M 3P , of the second amplification stage  16  are coupled to each other in a push-pull arrangement, wherein a first transistor, M 3N , of the second amplification stage  16  is coupled to a negative power supply voltage or a reference potential and wherein a second transistor, M 3P , of the second amplification stage  16  is coupled to a positive power supply voltage. 
     In example 14 the second amplification stage  16  comprises a push-pull stage comprising two transistors, M 3N , M 3P , the two transistors, M 3N , M 3P , of the second amplification stage  16  are coupled to each other in a push-pull arrangement, a first transistor, M 3N , of the second amplification stage  16  is coupled to a negative power supply voltage or a reference potential, a second transistor, M 3P , of the second amplification stage  16  is coupled to a positive power supply voltage, the first transistor, M 3N , of the second amplification stage  16  is coupled to the first transistor, M 1N , of the first amplification stage  12  and to the first transistor, M 2N , of the cascoding circuit  14 , the second transistor, M 3P , of the second amplification stage  16  is coupled to the second transistor, M 1P , of the first amplification stage  12  and to the second transistor, M 2P , of the cascoding circuit  14 . 
     In example 15 the first amplification stage  12  comprises at least two MOSFETs, a first MOSFET, M 1N , of n-channel type and a second MOSFET, M 1P , of p-channel type. The cascoding circuit  14  comprises at least two MOSFETs, a first MOSFET, M 2N , of n-channel type and a second MOSFET, M 2P , of p-channel type, each of the MOSFETs, M 1N , M 1P , M 2N , M 2P  comprising at least a gate, a source and a drain connector. A source connector of the first MOSFET, M 1N , of the first amplification stage  12  is coupled to a negative power supply voltage or a reference potential, and a drain connector of the first MOSFET, M 1N , of the first amplification stage  12  is coupled to a source connector of the first MOSFET, M 2N , of the cascoding circuit  14 . A drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  is coupled to a drain connector of the second MOSFET, M 2P , of the cascoding circuit  14 . A source connector of the second MOSFET, M 2P , of the cascoding circuit  14  is coupled to a drain connector of the second MOSFET, M 1P , of the first amplification stage  12 , and a source connector of the second MOSFET, M 1P , of the first amplification stage  12  is coupled to a positive power supply voltage. 
     In example 16 the source connector of the first MOSFET, M 1N , of the first amplification stage  12  is coupled to the negative power supply voltage or the reference potential through at least one resistor, R S1N . The source connector of the second MOSFET, M 1P , of the first amplification stage  12  is coupled to the positive power supply voltage through at least another resistor, R S1P . 
     In example 17 the input signal, V in (t), is coupled to the gate connectors of the first and second MOSFETs, M 1N  and M 1P , of the first amplification stage  12 , and gate connectors of the first and second MOSFETs, M 2N  and M 2P , of the cascoding circuit  14  are coupled to a reference potential. 
     In example 18 the input signal is coupled to the gate connector of the first MOSFET, M IN , of the first amplification stage  12  through at least one capacitor, C 1N , and the input signal is coupled to the gate connector of the second MOSFET, M 1P , of the first amplification stage  12  through at least one other capacitor, C 1P . 
     In example 19 the gate connector of the first MOSFET, M 2N , of the cascoding circuit  14  is coupled to the reference potential through at least one capacitor, C 2N . The gate connector of the second MOSFET, M 2P , of the cascoding circuit  14  is coupled to the reference potential through at least one other capacitor, C 2P . 
     In example 20 the second amplification circuit  10  comprises at least two MOSFETs, a first MOSFET, M 3N , of n-channel type and a second MOSFET, M 3P , of p-channel type. Each of the MOSFETs, M 3N , M 3P , of the second amplification stage  16  comprises at least a gate, a source and a drain connector. A source connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to a negative power supply voltage or a reference potential. A drain connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to a drain connector of the second MOSFET, M 3P , of the second amplification stage  16 . A source connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to a positive power supply. 
     In example 21 the source connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the negative power supply voltage or the reference potential through at least a resistor, R S2N . The source connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the positive power supply voltage through at least another resistor, R S2P . 
     In example 22 a gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the drain connector of the first MOSFET, M 1N , of the first amplification stage  12 . The gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the source connector of the first MOSFET, M 2N , of the cascoding circuit  14 . A gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the drain connector of the second MOSFET, M 1P , of the first amplification stage  12 . The gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the source connector of the second MOSFET, M 2P , of the cascoding circuit  14 . 
     In example 23 the gate connectors of the first and second MOSFETs, M 3N  and M 3P , of the second amplification stage  16  are coupled by at least one capacitor, C AC . 
     In example 24 the gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the drain connector of the first MOSFET, M 1N , of the first amplification stage  12  through at least one capacitor, C 3N . The gate connector of the first MOSFET, M 3N , of the second amplification stage  16  is coupled to the source connector of the first MOSFET, M 2N , of the cascoding circuit  14  through the capacitor, C 3N . The gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the drain connector of the second MOSFET, M 1P , of the first amplification stage  12  through at least another capacitor, C 3P . The gate connector of the second MOSFET, M 3P , of the second amplification stage  16  is coupled to the source connector of the second MOSFET, M 2P , of the cascoding circuit  14  through the other capacitor, C 3P . 
     In example 25 the first output signal V outn (t) is provided by the drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  and the drain connector of the second MOSFET, M 2P , of the cascoding circuit  14 . 
     In example 26 the second output signal V outp (t) is provided by the drain connector of the first MOSFET, M 3N , of the second amplification stage  16  and the drain connector of the second MOSFET, M 3 p, of the second amplification stage  16 . 
     In example 27 the input signal V in (t) is coupled to the drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  and the drain connector of the second MOSFET, M 2P , of the cascoding circuit  14 . 
     In example 28 the input signal V in (t) is coupled to the drain connector of the first MOSFET, M 2N , of the cascoding circuit  14  and the drain connector of the second MOSFET, M 2P , of the cascoding circuit  14  through at least a resistor, R FB , and a capacitor, C FB . 
     In example 29 an apparatus  10  for amplifying a radio signal comprises first means  12  for amplifying an input signal, V in (t), to obtain an intermediate signal. The apparatus  10  further comprises cascoding means  14  for amplifying the intermediate signal to obtain a first output signal, V outn (t). The apparatus  10  further comprises second means  16  for amplifying the intermediate signal from the cascoding means  14  to obtain a second output signal, V outp (t). 
     In example 30 the first and second output signals, V outn (t), V outp (t), form a differential output of the amplifier device  10 . 
     In example 31 one of the first means  12  for amplifying and the second means  16  for amplifying is an inverting amplification stage and the other is a non-inverting amplification stage. 
     In example 32 a low noise amplifier  100 ,  100   a ,  100   b  comprises the amplification circuit  10  the apparatus  10  according to one of the above examples. 
     In example 33 a radio receiver  200 ,  300  comprises the low noise amplifier  100  of the previous example. 
     In example 34 a mobile terminal  200  comprises the low noise amplifier  100   a  of an example. 
     In example 35 a base station  300  comprises the low noise amplifier  100   b  of an example. 
     In example 36 a method for amplifying a radio signal obtained at an input to provide an amplified signal at an output comprises amplifying  22  an input signal, V in (t), to obtain an intermediate signal. The method further comprises cascoding  24  the intermediate signal to obtain a first output signal, V outn (t). The method further comprises amplifying  26  the intermediate signal to obtain a second output signal, V outp (t). 
     In example 37 the first and second output signals, V outn (t), V outp (t), form a differential output of the amplifier circuit  10 . 
     In example 38 the amplifying  22  of the input signal or the amplifying of the intermediate signal further comprises inverting. 
     In example 39 an amplification stage  12  comprises a push-pull stage, and the cascoding comprises cascoding the push-pull stage. 
     In example 40 the amplifying  22  of the input signal, V in (t), uses a first push-pull stage, the cascoding  24  refers to the first push-pull stage, and the amplifying  26  of the intermediate signal uses a second push-pull stage. 
     In example 41 the amplifying  22  of the input signal, V in (t), uses a first amplification stage  12 , which comprises at least two transistors, M 1N , M 1P , being coupled in a push-pull arrangement, and wherein the cascoding  24  uses at least two transistors, M 2N , M 2P , being coupled in a push-pull arrangement between the transistors, M 1N , M 1P , of the first amplification stage ( 12 ). 
     In example 42 the at least two transistors, M 1N , M 1P , of the first amplification stage  12  are two MOSFETs, Metal-Oxide-Semiconductor Field-Effect Transistor, with different channel types. 
     In example 43 the at least two transistors, M 2N , M 2P , used by the cascoding are two MOSFETs with different channel types. 
     In example 44 the method further comprises coupling a first transistor, M 1N , of the first amplification stage  12  to a negative power supply voltage or reference potential and coupling a second transistor, M 1P , of the first amplification stage  12  to a positive supply voltage. 
     In example 45 the method further comprises coupling a first transistor, M 2N , for cascoding to the first transistor, M 1N , of the first amplification stage  12 , coupling the first transistor, M 2N , for cascoding to a second transistor, M 2P , for cascoding, and coupling the second transistor, M 2P , for cascoding to the second transistor, M 1P , of the first amplification stage  12 . 
     In example 46 the amplifying  26  of the intermediate signal uses a push-pull stage comprising at least two transistors, M 3N , M 3P . 
     In example 47 the at least two transistors, M 3N , M 3P , are two MOSFETs with different channel types being comprised in a second amplification stage  16 . 
     In example 48 the method comprises coupling the at least two transistors, M 3N , M 3P , of the second amplification stage  16  to each other in a push-pull arrangement, further comprising coupling a first transistor, M 3N , of the second amplification stage  16  to a negative power supply voltage or reference potential, and coupling a second transistor, M 3P , of the second amplification stage  16  to a positive power supply voltage. 
     In example 49 the method further comprises coupling the two transistors, M 3N , M 3P , of the second amplification stage  16  to each other in a push-pull arrangement, and coupling a first transistor, M 3N , of the second amplification stage  16  to a negative power supply voltage or reference potential. The method further comprises coupling a second transistor, M 3P , of the second amplification stage  16  to a positive power supply voltage, and coupling the first transistor, M 3N , of the second amplification stage  16  to the first transistor, M 1N , of the first amplification stage  12  and to the first transistor, M 2N , for cascoding. The method further comprises coupling the second transistor, M 3P , of the second amplification stage  16  to the second transistor, M 1P , of the first amplification stage  12  and to the second transistor, M 2P , for cascoding. 
     The description and drawings merely illustrate the principles of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, exemplify the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof. 
     Functional blocks denoted as “means for . . . ” (performing a certain function) shall be understood as functional blocks comprising circuitry that is configured to perform a certain function, respectively. Hence, a “means for s.th.” may as well be understood as a “means configured to or suited for s.th.”. A means configured to perform a certain function does, hence, not imply that such means necessarily is performing the function (at a given time instant). 
     Functions of various elements shown in the figures, including any functional blocks labeled as “means”, “means for amplifying”, “means for cascoding”, etc., may be provided through the use of dedicated hardware, such as “an amplifier”, “a cascoder”, etc. as well as hardware capable of executing software in association with appropriate software. Moreover, any entity described herein as “means”, may correspond to or be implemented as “one or more modules”, “one or more devices”, “one or more units”, etc. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included. 
     It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry exemplify the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. 
     Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that—although a dependent claim may refer in the claims to a specific combination with one or more other claims—other examples may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim. 
     It is further to be noted that methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods. 
     Further, it is to be understood that the disclosure of multiple acts or functions disclosed in the specification or claims may not be construed as to be within the specific order. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act may include or may be broken into multiple sub acts. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

Metadata:
Filing Date: 20190813
Publication Date: 20200714
Grant Date: 20200714
Priority Date: 20160613
Inventors: NAEINI, ASHKAN
KOSTACK, ROBERT
STOCKINGER, HERBERT
Assignee: APPLE INC
CPC Classifications: [{"code": "H03F3/189", "inventive": true, "first": true, "tree": "[]"}, {"code": "H03F3/193", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F1/223", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03H11/32", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F1/223", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F2200/294", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03H11/32", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/265", "inventive": true, "first": true, "tree": "[]"}, {"code": "H03F2200/411", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03F3/189", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/193", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F2200/294", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03F2200/411", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03F3/193", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/265", "inventive": true, "first": true, "tree": "[]"}, {"code": "H03F3/189", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03H11/32", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F2200/294", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03F1/223", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F1/26", "inventive": true, "first": true, "tree": "[]"}, {"code": "H03F3/193", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/3001", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/45179", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/68", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F2200/294", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03F2200/451", "inventive": false, "first": false, "tree": "[]"}, {"code": "H03F3/189", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F3/265", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03H11/32", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F1/223", "inventive": true, "first": false, "tree": "[]"}, {"code": "H03F2200/411", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 56120971