PATENT DOCUMENT

Publication Number: US-9208733-B2
Application Number: US-201213601547-A
Country: US
Kind Code: B2

Title: Systems and methods for monitoring LCD display panel resistance

Abstract:
Systems and methods for monitoring internal resistance of a display. The method may include supplying the display via a capacitor with a first voltage configured to enable the display to receive one or more touch inputs. After supplying the display with the first voltage, the method may include discharging the capacitor to a second voltage configured to enable the display to display image data. The method may then monitor a discharge waveform that corresponds to when the capacitor discharges from the first voltage to the second voltage. Based at least in part on the discharge waveform, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

Claims:
What is claimed is: 
     
       1. A display driver circuit comprising:
 a capacitor configured to provide a plurality of voltages to a display via a supply rail, wherein the capacitor is coupled in series with a chip on glass (COG) circuit and a flex on glass (FOG) circuit of the display;
 a plurality of switches associated with a plurality of resistance values, wherein each resistance value is different, wherein each switch is configured to couple the capacitor to ground when closed, and wherein each resistance value of the plurality of resistance values is associated with a different display manufacturer, one of which is the manufacturer of the display; and 
 
 a processor configured to: 
 enable the display to receive one or more touch inputs and display image data by charging and discharging the capacitor via a first switch of the plurality of switches; 
 periodically measure a COG resistance value of the COG circuit and a FOG resistance value of the FOG circuit by: 
 closing the first switch, thereby discharging the capacitor; 
 measuring a first amount of time between when the capacitor has a first voltage value and when the capacitor discharges to a second voltage value via the first switch; 
 opening the first switch after the capacitor discharges to the second voltage value;
 closing a second switch of the plurality of switches; 
 
 measuring a second amount of time that corresponds to an amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the second switch; and 
 determining the COG resistance value and the FOG resistance value based at least in part on the first amount of time and the second amount of time; and 
 enable the display to again receive the inputs and display the image data by charging and discharging the capacitor via the first switch after measuring the COG resistance value and the FOG resistance value. 
 
     
     
       2. The display driver circuit of  claim 1 , wherein the first voltage value corresponds to a voltage value configured to enable the display to receive one or more touch inputs. 
     
     
       3. The display driver circuit of  claim 1 , wherein the second voltage value corresponds to a voltage value configured to enable the display to display image data. 
     
     
       4. The display driver circuit of  claim 1 , comprising:
 a comparator circuit configured to switch states when the capacitor reaches the second voltage value; and 
 a counter circuit configured to measure the first and second amounts of time based at least in part on when the comparator circuit switches states and a clock input. 
 
     
     
       5. The display driver circuit of  claim 4 , wherein the counter circuit is coupled to the plurality of switches and is configured to open the first switch when the capacitor discharges to the second voltage value. 
     
     
       6. The display driver circuit of  claim 1 , wherein the processor is configured to measure the COG resistance value and the FOG resistance value periodically. 
     
     
       7. The display driver circuit of  claim 6 , wherein the processor is configured to:
 store each COG resistance value and FOG resistance value in a log; and 
 send the log to a server. 
 
     
     
       8. The display driver circuit of  claim 1 , wherein the processor is configured to determine the COG resistance value and FOG resistance value based on:
     R   COG   +R   FOG   +R   SW1   =t   1   /C /(−ln( V   1   /V   0 )); and
 
     R   COG   +R   FOG   +R   SW2   =t   2   /C /(−ln( V   1   /V   0 ));
 
 
       wherein R COG  corresponds to the COG resistance value, R FOG  corresponds to the FOG resistance value, R SW1  corresponds to a resistance value of the first switch, R SW2  corresponds to a resistance value of the second switch, t 1  corresponds to the first amount of time, t 2  corresponds to the second amount of time, C corresponds to a capacitance value of the capacitor, V 0  corresponds to the first voltage value, and V 1  corresponds to the second voltage value. 
     
     
       9. A system comprising:
 a display configured to display image data and receive one or more touch inputs; 
 
       a capacitor configured to provide a plurality of voltages to the display via a supply rail, wherein the supply rail couples the capacitor in series with an internal resistance of the display;
 a plurality of switches associated with a plurality of resistance values, wherein each resistance value is different, wherein each switch is configured to couple the capacitor to ground when closed, and wherein each resistance value of the plurality of resistance values is associated with a different display manufacturer, one of which is the manufacturer of the display; and 
 a controller configured to: 
 enable the display to receive one or more touch inputs and display image data by charging and discharging the capacitor via a first switch of the plurality of switches; 
 measure an internal resistance value of the display by: 
 closing the first switch, thereby discharging the capacitor; 
 measuring a first amount of time between when the capacitor has a first voltage value and when the capacitor discharges to a second voltage value via the first switch; 
 opening the first switch after the capacitor discharges to the second voltage value; 
 closing a second switch of the plurality of switches; 
 measuring a second amount of time between when the capacitor has the first voltage value and when the capacitor discharges to a third voltage value via the second switch; and 
 determining the internal resistance value based at least in part on the first amount of time and the second amount of time; and 
 enable the display to again receive the inputs and display the image data by charging and discharging the capacitor via the first switch after measuring the internal resistance value. 
 
     
     
       10. The system of  claim 9 , comprising a comparator circuit coupled to the supply rail via a first resistor and to a voltage source via a second resistor, wherein the comparator circuit switches states when the capacitor discharges to the second voltage value. 
     
     
       11. The system of  claim 10 , wherein the controller measures the second amount of time by adjusting a resistance value of the first resistor or the second resistor, thereby adjusting a ratio of the first resistor to the second resistor, wherein the comparator circuit is configured to switch states when the capacitor discharges to the third voltage value after the ratio is adjusted. 
     
     
       12. The system of  claim 10 , wherein the first resistor, the second resistor, or any combination thereof is a variable resistor. 
     
     
       13. The system of  claim 9 , wherein each switch of the plurality of switches is associated with a different display manufacturer. 
     
     
       14. The system of  claim 9 , wherein the controller is configured to acquire a plurality of measurements of the internal resistance a plurality of times. 
     
     
       15. The system of  claim 14 , wherein one or more changes in the plurality of measurements of the internal resistance corresponds to a decreased quality of the display. 
     
     
       16. The system of  claim 9 , wherein the controller is configured to measure the internal resistance value based on:
     R   COG   +R   FOG   +R   SW1   =t   1   /C /(−ln( V   1   /V   0 )); and
 
     R   COG   +R   FOG   +R   SW2   =t   2   /C /(−ln( V   2   /V   0 ))
 
 
       wherein R COG +R FOG  corresponds to the internal resistance value, R SW1  corresponds to a resistance value of the first switch, R SW2  corresponds to a resistance value of the second switch, t 1  corresponds to the first amount of time, t 2  corresponds to the second amount of time, C corresponds to a capacitance value of the capacitor, V 0  corresponds to the first voltage value, V 1  corresponds to the second voltage value, and V 2  corresponds to the third voltage value. 
     
     
       17. An electronic device comprising:
 a display configured to display image data and receive one or more touch inputs; 
 a capacitor configured to provide a plurality of voltages to the display via a supply rail, wherein the supply rail couples the capacitor in series with chip on glass (COG) resistance and a flex on glass (FOG) resistance of the display; 
 a plurality of switches associated with a plurality of resistance values, wherein each resistance value is different and is associated with a different display manufacturer, and wherein each switch is configured to couple the capacitor to ground when closed; 
 a comparator circuit coupled to the capacitor via a first resistor and to a reference voltage source via a second resistor; and 
 a processor configured to measure a COG resistance value and a FOG resistance value of the display by: 
 closing a first switch of the plurality of switches, thereby discharging the capacitor; 
 measuring an amount of time between when the comparator circuit changes states, wherein the comparator circuit changes states after the capacitor discharges from a first voltage value to a second voltage value; 
 opening the first switch after the capacitor discharges to the second voltage value; 
 adjusting a ratio of the first resistor to the second resistor to cause the comparator circuit to change states after the amount of time elapses when the capacitor is discharged from the first voltage value using a second switch of the plurality of switches; 
 determining a third voltage value that corresponds to a voltage of the capacitor when the comparator circuit changes states after the amount of time elapses when the capacitor is discharged using the second switch; and 
 determining the COG resistance and FOG resistance values based at least in part on the amount of time, the second voltage value, and the third voltage value. 
 
     
     
       18. The electronic device of  claim 17 , wherein the processor is configured to adjust the ratio by modifying a resistance value of the first resistor, the second resistor, or any combination thereof. 
     
     
       19. The electronic device of  claim 17 , wherein the processor is configured to determine the COG resistance and FOG resistance values based on:
     R   COG   +R   FOG   +R   SW1   =t   1   /C /(−ln( V   1   /V   0 )); and
 
     R   COG   +R   FOG   +R   SW2   =t   1   /C /(−ln( V   2   /V   0 ))
 
 
       wherein R COG  corresponds to the COG resistance value, R FOG  corresponds to the FOG resistance value, R SW1  corresponds to a resistance value of the first switch, R SW2  corresponds to a resistance value of the second switch, t 1  corresponds to the amount of time, C corresponds to a capacitance value of the capacitor, V 0  corresponds to the first voltage value, V 1  corresponds to the second voltage value, and V 2  corresponds to the third voltage value. 
     
     
       20. A liquid crystal display (LCD), comprising:
 a display driver circuit configured to provide the LCD with a plurality of voltages via a supply rail, wherein the display driver circuit comprises: 
 
       an external voltage source coupled to the supply rail;
 a plurality of switches coupled between the external voltage source and an internal resistance of the display, wherein each switch is associated with a different resistance value and is configured to couple the external voltage source to ground when closed, and wherein each different resistance value is associated with a different display manufacturer; 
 a first resistor coupled to the supply rail at a node, wherein the node is between the internal resistance and the first resistor; 
 a second resistor coupled between the first resistor and a reference voltage source; and 
 a controller configured to measure an internal resistance value of the LCD by: 
 closing one of the plurality of switches; 
 
       measuring a current value through the one of the switches; and
 determining the internal resistance value based at least in part on: 
 a difference between a first voltage value of the external voltage source and a second voltage value that corresponds to a voltage at the node; and 
 the current value. 
 
     
     
       21. The LCD of  claim 20 , wherein the controller is configured to determine the voltage at the node based at least in part on a voltage of the reference voltage source and a ratio of a resistance value of the first resistor to a resistance value of the second resistor. 
     
     
       22. The LCD of  claim 20 , wherein the external voltage source is a direct current (DC) voltage source.

Description:
BACKGROUND 
     The present disclosure relates generally to methods for monitoring various characteristics of a liquid crystal display (LCD) panel, and more specifically, to measuring and monitoring a resistance within the LCD panel over time. 
     This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. 
     After a liquid crystal display (LCD) panel is manufactured, the LCD panel is tested to determine whether it meets certain quality or performance standards. A common test for determining the quality of a manufactured LCD panel includes testing a resistance of a chip on glass (COG) circuit and a flex on glass (FOG) circuit in the LCD panel. For instance, the quality of the LCD panel can be assessed based on the COG resistance value and the FOG resistance value of the LCD panel. To measure the COG and FOG resistance values, dedicated input/output (I/O) pads on a display driver integrated circuit (IC) in the LCD panel and dedicated I/O pads on a flexible printed circuit (FPC) in the LCD panel are coupled to a separate test glass panel. The test glass panel measures the COG and FOG resistance values via the I/O pads of the display driver IC and the FPC. 
     Although the separate test glass panel provides a way to measure the COG and FOG resistance values of an LCD panel, the test glass panel can just be used during the development or production of the LCD panel. As such, the COG and FOG resistance values cannot be monitored after the LCD panels are assembled into their respective products. Since COG and FOG resistance values can vary as the LCD panel ages, information related to how the COG and FOG resistance values vary over time may be useful in further assessing the quality of the LCD panel. 
     SUMMARY 
     A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below. 
     The present disclosure generally relates to monitoring internal resistance values of a liquid crystal display (LCD) panel over time. More specifically, the present disclosure relates to measuring resistances in a chip on glass (COG) circuit and a flex on glass (FOG) circuit in the LCD panel over time. In certain embodiments, an electronic device may use an LCD panel as a display and as an interface to receive touch inputs via touch-sensing circuitry within the LCD panel. To simultaneously display image data and detect touches, the LCD panel may frequently alternate between a display period mode (e.g., when a frame of image data is rendered on an active display region of the LCD panel) and touch period mode (e.g., when the active display region detects touch inputs). The display period and touch period modes for the LCD panel may be characterized by two different sets of voltages applied to the active display region of the LCD panel via two supply rails (e.g., high and low). 
     During the display period, the active display region may receive a first set of voltages from the high and low supply rails such that the active display region may be capable of displaying the image data. During the touch period, the active display region may receive a second set of voltages from the high and low supply rails such that the active display region may be capable of detecting touch inputs. The first and second sets of voltage values may be provided on the high and low supply rails by charging and discharging capacitors that may be coupled to each supply rail. In addition to the capacitor, each supply rail may be in series with the COG circuit, the FOG circuit, and a number of switches coupled to ground (i.e., discharge circuitry). When transitioning from a touch period voltage to a display period voltage, one of the switches in series with the supply rail may be closed until the voltage of the capacitor on the supply rail is discharged to the display period voltage. After reaching the display period voltage, the respective switch may be opened for some period of time (e.g., display period) until the capacitor is to be discharged again. This process may be continuously repeated (i.e., discharge cycles), thereby enabling the LCD panel to simultaneously display image data and detect touch inputs. 
     In one embodiment, when transitioning between the touch and display period voltages, the discharge circuitry may discharge the capacitor using a first switch during a first discharge cycle and then the discharge circuitry may discharge the same capacitor using a second switch during a subsequent discharge cycle. By monitoring the discharge waveforms using the two different switches, a processor coupled to the LCD panel may determine the resistances of the COG circuit and the FOG circuit in the LCD panel at any time while the LCD panel is in operation. That is, since the touch period voltage, the display period voltage, the resistance values of the first and second switches, and amounts of time elapsed to reach the display period voltage in each discharge cycle are known, the processor may determine the total COG and FOG resistance values by solving a system of equations based on the natural response of a resistor-capacitor (RC) circuit (i.e., discharge circuitry). Accordingly, the processor may monitor the COG and FOG resistance values at any time while the LCD panel is in operation to further assess the quality of the LCD panel as the LCD panel ages. 
     Various refinements of the features noted above may exist in relation to various aspects of the present disclosure. Further features may also be incorporated in these various aspects as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present disclosure alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which: 
         FIG. 1  is a block diagram of exemplary components of an electronic device, in accordance with an embodiment; 
         FIG. 2  is a front view of a handheld electronic device, in accordance with an embodiment; 
         FIG. 3  is a front view of a tablet electronic device, in accordance with an embodiment; 
         FIG. 4  is a view of a computer, in accordance with an embodiment; 
         FIG. 5  is a block diagram of a display in the electronic device of  FIG. 1 , in accordance with an embodiment; 
         FIG. 6  is a block diagram of a display driver integrated circuit (IC) in the display of  FIG. 5 , in accordance with an embodiment; 
         FIG. 7  is a graph of supply rail voltages over time as controlled by the display driver IC of  FIG. 6 , in accordance with an embodiment; 
         FIG. 8  is a flow chart that depicts a method for determining a chip on glass (COG) resistance value and a flex on glass (FOG) resistance value in the display of  FIG. 5  using a single voltage value, in accordance with an embodiment; 
         FIG. 9  is a graph of a supply rail voltage over time that corresponds with the method of  FIG. 8 , in accordance with an embodiment; 
         FIG. 10  is a flow chart that depicts a method for determining the COG resistance value and the FOG resistance value in the display of  FIG. 5  using two voltage values, in accordance with an embodiment; 
         FIG. 11  is a graph of a supply rail voltage over time that corresponds with the method of  FIG. 10 , in accordance with an embodiment; 
         FIG. 12  is a flow chart that depicts a method for determining the COG resistance value and the FOG resistance value using various resistance ratios in the display driver IC of  FIG. 6 , in accordance with an embodiment; 
         FIG. 13  is a graph of a supply rail voltage over time that corresponds with the method of  FIG. 12 , in accordance with an embodiment; 
         FIG. 14  is a block diagram of a display driver IC in the display of  FIG. 5  that includes an external voltage supply, in accordance with an embodiment; and 
         FIG. 15  is a flow chart that depicts a method for determining the COG resistance value and the FOG resistance value using the display driver IC of  FIG. 15 , in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS 
     One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. 
     The present disclosure is directed to systems and methods for determining chip on glass (COG) and flex on glass (FOG) resistance values of a liquid crystal display (LCD) panel over time. Different LCD manufacturers produce different LCD panels that have different COG and FOG resistance values. In certain embodiments, electronic devices may use a single display driver integrated circuit (IC) to drive different LCD panels provided by different LCD manufacturers. As such, the single display driver IC may include a voltage supply rail that may couple in series to a COG circuit, a FOG circuit, and a number of switches. Each switch in the display driver IC may have a different resistance value and may be associated with a different LCD manufacturer. 
     Keeping the foregoing in mind, in one embodiment, a processor may use two different switches in the display driver IC at two different times to discharge a capacitor in series with the COG circuit and the FOG circuit on the supply line from a touch period voltage (i.e., to enable the LCD panel to detect touch inputs) to a display period voltage (i.e., to enable the LCD panel to display image data). The processor may then determine the resistance values of the COG and FOG circuits based on the two discharge waveforms that corresponds to the two different switches. Additional details with regard to how the processor may determine the COG and FOG resistance values of the LCD panel will be discussed below with reference to  FIGS. 1-16 . 
     A variety of electronic devices may incorporate systems and methods for determining the COG and FOG resistance values of an LCD panel. An example of a suitable electronic device may include various internal and/or external components, which contribute to the function of the device.  FIG. 1  is a block diagram illustrating the components that may be present in such an electronic device  10  and which may allow the electronic device  10  to function in accordance with the methods discussed herein. Those of ordinary skill in the art will appreciate that the various functional blocks shown in  FIG. 1  may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium), or a combination of both hardware and software elements. It should further be noted that  FIG. 1  is merely one example of a particular implementation and is merely intended to illustrate the types of components that may be present in the electronic device  10 . For example, in the presently illustrated embodiment, these components may include a display  12 , I/O ports  14 , input structures  16 , one or more processors  18 , a memory device  20 , a non-volatile storage  22 , a networking device  24 , a power source  26 , a chip on glass (COG) circuit  28 , a flex on glass (FOG) circuit  30 , and the like. 
     With regard to each of these components, the display  12  may be used to display various images generated by the electronic device  10 . Moreover, the display  12  may be a touch-screen liquid crystal display (LCD), for example, which may enable users to interact with a user interface of the electronic device  10 . In some embodiments, the display  12  may be a MultiTouch™ display that can detect multiple touches at once. 
     The I/O ports  14  may include ports configured to connect to a variety of external I/O devices, such as a power source, headset or headphones, peripheral devices such as keyboards or mice, or other electronic devices  10  (such as handheld devices and/or computers, printers, projectors, external displays, modems, docking stations, and so forth). 
     The input structures  16  may include the various devices, circuitry, and pathways by which user input or feedback is provided to the processor  18 . Such input structures  16  may be configured to control a function of the electronic device  10 , applications running on the electronic device  10 , and/or any interfaces or devices connected to or used by the electronic device  10 . 
     The processor(s)  18  may provide the processing capability to execute the operating system, programs, user and application interfaces, and any other functions of the electronic device  10 . The instructions or data to be processed by the processor(s)  18  may be stored in a computer-readable medium, such as the memory  20 . The memory  20  may be provided as a volatile memory, such as random access memory (RAM), and/or as a non-volatile memory, such as read-only memory (ROM). The components may further include other forms of computer-readable media, such as the non-volatile storage  22 , for persistent storage of data and/or instructions. The non-volatile storage  22  may include flash memory, a hard drive, or any other optical, magnetic, and/or solid-state storage media. The non-volatile storage  22  may be used to store firmware, data files, software, wireless connection information, and any other suitable data. In certain embodiments, the processor  18  may control the operation of various switches and hardware components that may be located within the electronic device  10  including the COG circuit  26  and the FOG circuit  28 . 
     The network device  24  may include a network controller or a network interface card (NIC). Additionally, the network device  24  may be a Wi-Fi device, a radio frequency device, a Bluetooth® device, a cellular communication device, or the like. The network device  24  may allow the electronic device  10  to communicate over a network, such as a Local Area Network (LAN), Wide Area Network (WAN), or the Internet. The power source  26  may include a variety of power types such as a battery or AC power. 
     With the foregoing in mind,  FIG. 2  and  FIG. 3  illustrate an electronic device  10  in the form of a handheld device  34  and a tablet device  40 , respectively.  FIG. 2  illustrates a cellular telephone, but it should be noted that while the depicted handheld device  34  is provided in the context of a cellular telephone, other types of handheld devices (such as media players for playing music and/or video, personal data organizers, handheld game platforms, and/or combinations of such devices) may also be suitably provided as the electronic device  10 . As discussed with respect to the general electronic device  10  of  FIG. 1 , the handheld device  34  and the tablet device  40  may allow a user to connect to and communicate through the Internet or through other networks, such as local or wide area networks. The handheld electronic device  34  and the tablet device  40 , may also communicate with other devices using short-range connections, such as Bluetooth® and near field communication. By way of example, the handheld device  34  may be a model of an iPod® or iPhone® available from Apple Inc. of Cupertino, Calif. Similarly, by way of example, the tablet device  40  may be a model of an iPad® from Apple Inc. of Cupertino, Calif. 
     The handheld device  34  and the tablet device  40  include an enclosure or body that protects the interior components from physical damage and shields them from electromagnetic interference. The enclosure may be formed from any suitable material such as plastic, metal or a composite material and may allow certain frequencies of electromagnetic radiation to pass through to wireless communication circuitry within the handheld device  34  and the tablet device  40  to facilitate wireless communication. In the depicted embodiment, the enclosure includes user input structures  16  through which a user may interface with the device. Each user input structure  16  may be configured to help control a device function when actuated. 
     In the depicted embodiment, the handheld device  34  and the tablet device  40  include the display  12 . The display  12  may be a touch-screen LCD used to display a graphical user interface (GUI) that allows a user to interact with the handheld device  34  and the tablet device  40 . The handheld electronic device  34  and the tablet device  40  also may include various input and output (I/O) ports that allow connection of the handheld device  34  and the tablet device  40  to external devices. 
     In addition to handheld device  34  and the tablet device  40 , the electronic device  10  may also take the form of a computer or other type of electronic device. Such computers may include computers that are generally portable (such as laptop, notebook, and tablet computers) as well as computers that are generally used in one place (such as conventional desktop computers, workstations, and/or servers). In certain embodiments, the electronic device  10  in the form of a computer may be a model of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, iPad® or Mac Pro® available from Apple Inc. By way of example, an electronic device  10  in the form of a laptop computer  50  is illustrated in  FIG. 4  in accordance with one embodiment. The depicted computer  50  includes a housing  52 , a display  12 , input structures  16 , and input/output ports  14 . 
     In one embodiment, the input structures  16  (such as a keyboard and/or touchpad) may be used to interact with the computer  50 , such as to start, control, or operate a GUI or applications running on the computer  50 . For example, a keyboard and/or touchpad may allow a user to navigate a user interface or application interface displayed on the display  12 . 
     As depicted, the electronic device  10  in the form of the computer  50  may also include various input and output ports  14  to allow connection of additional devices. For example, the computer  50  may include an I/O port  14 , such as a USB port or other port, suitable for connecting to another electronic device, a projector, a supplemental display, and so forth. The computer  50  may include network connectivity, memory, and storage capabilities, as described with respect to  FIG. 1 . As a result, the computer  50  may store and execute a GUI and other applications. 
     With the foregoing discussion in mind,  FIG. 5  depicts a block diagram  70  of the display  12  in the electronic device  10 . As shown in  FIG. 5 , the display  12  includes an active display region  72 , the chip on glass (COG) circuit  26 , and the flex on glass (FOG) circuit  28 . The COG circuit  26  may be directly coupled to a glass layer of the active display region  72 . The COG circuit  26  includes a display driver integrated circuit (IC)  74  that is coupled in series with the COG circuit  26  and the FOG circuit  78 . The FOG circuit  78  is a flexible printed circuit (FPC) coupled on one end to the glass layer of the active display region  72 . 
     The COG circuit  26  and the FOG circuit  28  may include a COG resistance  76  and a FOG resistance  78 , respectively. The COG resistance  76  is a measure of internal resistance within the COG circuit  26 . Similarly, the FOG resistance  78  is a measure of internal resistance within the FOG circuit  28 . As the display  12  ages, the COG resistance  76  and the FOG resistance  78  may vary significantly. In some cases, these significant variations in the COG resistance  76  and the FOG resistance  78  may cause the display  12  to perform abnormally, display artifacts, and the like. By monitoring the COG resistance  76  and the FOG resistance  78  over time, electronic device manufacturers may assess the quality of the display  12  (e.g., LCD panel) over time. Accordingly, this information may prove useful in evaluating the manufacturers of the display  12 . 
     In one embodiment, the circuitry of the display driver IC  74  may be used to determine the COG resistance  76  and the FOG resistance  78  over time.  FIG. 6  depicts a block diagram  90  of the display driver IC  74 . As shown in  FIG. 6 , the display driver IC  74  may include the COG resistance (R COG )  76 , the FOG resistance (R FOG )  78 , a capacitor  92 , a supply rail  93 , a number of switches  94  (e.g., switch  96  and switch  98 ), a resistor  99 , ground  100 , a variable resistor  101 , a comparator circuit  102 , a flip flop circuit  104 , and a counter/controller circuit  106 . The COG resistance  76 , the FOG resistance  78 , and the capacitor  92  are coupled to the display driver IC  74  via the supply rail  93 . As mentioned above, to simultaneously display image data and detect touches, the display  12  may frequently alternate between a display period mode (e.g., when a frame of image data is rendered on the active display region  72 ) and touch period mode (e.g., when the active display region  72  detects touch inputs). The display period and touch period modes for the LCD panel may be characterized by two different sets of voltages applied to the active display region  72  of the LCD panel via two supply rails (e.g., high and low). 
     Keeping this in mind,  FIG. 7  depicts an example of a graph  110  depicting how the voltages on a low voltage supply rail (V CPL ) and a high voltage supply rail (V CPH ) may change between display periods and touch periods. Referring to the graph  110 , between time T 0  and time T 1 , the voltages on the low and high supply rails are set to a display period voltage value (e.g., V CPL     —     D , V CPH     —     D ). At time T 1 , the voltage on each supply rail changes to touch period voltage values (e.g., V CPL     —     T , V CPH     —     T ) until time T 2 . Between time T 2  and time T 3 , the voltage on the low voltage supply rail (e.g., supply rail  93 ) decreases back to the display period voltage V CPL     —     D . In one embodiment, the voltage drop that occurs between time T 2  and time T 3  is caused by discharging the capacitor  92 . The capacitor  92  may be discharged by closing one of the switches  94 , thereby coupling the capacitor  92  to ground  100 . The display driver IC  74  may include a number of switches  94  such that the display driver IC  74  may couple to a variety of types of the display  12  produced by a variety of manufacturers. That is, each different manufacturer of the display  12  may specify a different switch resistance with which the capacitor  92  should be discharged. As such, the display driver IC  74  may include a number of switches  94  that have a number of different resistance values such that a single display driver IC  74  may be compatible with a number of different types of displays  12 . 
     In one embodiment, the COG resistance  76  and the FOG resistance  78  may be determined based on discharge waveforms that correspond to when the capacitor  92  on the supply rail  93  (i.e., low voltage supply rail) is discharged using different switches  94  between time T 2  and time T 3 . For instance, the capacitor  92  may be discharged from the touch period voltage to the display period voltage using a first switch (e.g., switch  96 ) during a first discharge cycle and using a second switch (e.g., switch  98 ) during a second discharge cycle. The processor  18  may compare the two discharge waveforms and determine the COG resistance  76  and the FOG resistance  78  based on the two discharge waveforms. Various methods in which the processor  18  may determine the COG resistance  76  and the FOG resistance  78  of the display  12  is described below with reference to  FIGS. 8-15 . Although the methods below are described with reference to when the capacitor  92  discharges on the low voltage supply rail between time T 2  and time T 3 , it should be noted that the methods described below may also be performed on the high voltage supply rail between time T 1  and time T 4 , when the capacitor on the high voltage supply rail is discharged between the display period and the touch period. 
     Some of the methods described below, which may be used to determine the COG resistance  76  and the FOG resistance  78 , may be based on a voltage response of the capacitor  92  in the display driver IC  74  as it discharges. For example, it is well known that for a resistor-capacitor (RC) circuit like that of the display driver IC  74 , that the voltage at the capacitor (e.g., capacitor  92 ) will follow the following equation:
 
 V   C   =V   0 *exp(− t/RC )  (1)
 
where V C  is the instantaneous voltage at the capacitor of the RC circuit, V 0  is the initial voltage at the capacitor of the RC circuit, t is an amount of time for the capacitor to discharge from voltage V 0  to voltage VC, R is the resistance of the RC circuit, and C is the capacitance of the capacitor of the RC circuit.
 
     Keeping Equation 1 in mind, the COG resistance  76  and the FOG resistance  78  of the display  12  may be determined based on how the voltage at the capacitor  92  in the display driver IC  74  changes as it discharges. That is, the display driver IC  74  may correspond to an RC circuit having a total resistance that includes the COG resistance  76 , the FOG resistance  78 , and a resistance (R SW ) of a switch used to discharge the capacitor. Further, the display driver IC  74  may correspond to an RC circuit having a total capacitance equal to the capacitance value of the capacitor  92 . In this manner, Equation 1 may be applied to the display driver IC  74  and may be characterized as follows:
 
 V   C   =V   0 *exp(− t /( R   COG   +R   FOG   +R   SW )* C )  (2)
 
 t =−ln( V   C   /V   0 )*( R   COG   +R   FOG   +R   SW )* C   (3)
 
 R   COG   +R   FOG   +R   SW   =t/C /(−ln( V   C   /V 0))  (4)
 
where V C  is the instantaneous voltage at the capacitor  92 , V 0  is the initial voltage at the capacitor  92 , R COG  is the COG resistance  76 , R FOG  is the FOG resistance  78 , and R SW  is the resistance of the switch used to discharge the capacitor  92 .
 
     In one embodiment, a method  120  ( FIG. 8 ) for determining the COG resistance  76  and the FOG resistance  78  of the display  12  may be based on the voltage response of the capacitor  92  as described above in Equations 2-4. The following description of the method  120  is provided with reference to the display driver IC  74  of  FIG. 6  and the low voltage supply rail curve (V CPL ) in the graph  110  of  FIG. 7 . Referring now to  FIG. 8 , at block  122 , the processor  18  may receive a voltage value (V 1 ), which may be a voltage value between the initial voltage V 0  of the capacitor  92  (e.g., touch period voltage) and the display period voltage (i.e., between time T 2  and time T 3 ) or the display period voltage. 
     At block  124 , the processor  18  may discharge the capacitor  92  to the voltage value V 1  received at block  122  using a first switch (e.g., switch  96 ). For example, the processor  18  may close the switch  96 , thereby coupling the capacitor  92  to ground  100  and discharging the capacitor  92 . 
     The processor  18  may then, at block  126 , measure a time (t 1 ) it takes for the capacitor  92  to discharge from its initial voltage value V 0  to the voltage value V 1 . To measure the time t 1 , the processor  18  may adjust the variable resistor  101  of the display driver IC  74  such that the comparator  102  changes its state when the voltage of the capacitor  92  reaches the voltage value V 1 . The comparator circuit  102  may change states when a voltage (V trip ) at node  108  becomes greater than zero. As such, the processor  18  may adjust the resistance of the variable resistor  101  such that the voltage at node  108  is sufficient to cause the comparator circuit  102  to switch states (i.e., trip) when the voltage of the capacitor  92  reaches the voltage value V 1 . 
     After the comparator circuit  102  changes states, the processor  18  may then calculate the time t 1  for the capacitor  92  to discharge from its initial voltage value V 0  to the voltage value V 1  based on a number of counts between when the switch  96  was closed and when the comparator  102  changed states, as determined by the counter/controller circuit  106 . That is, once the comparator  102  changes states, the flip flop circuit  104  may provide an output signal to the counter/controller circuit  106  indicating that the comparator circuit  102  changed states. In one embodiment, the counter/controller circuit  106  may also receive an input from an accurate and high-speed clock such that it may keep an accurate track of time between when the comparator circuit  102  changes states in the form of counts. 
     The counter/controller  106  may also control the operation of each of the switches  94 . As such, at block  128 , after the processor  18  determines that the capacitor  92  has reached the voltage value V 1 , the processor  18  may open the switch  96  via the counter/controller circuit  106 . 
     At block  130 , after the capacitor  92  has been recharged to its initial voltage value V 0 , the processor  18  may discharge the capacitor  92  to the voltage value V 1  using a second switch (e.g., switch  98 ). The processor  18  may then, at block  132 , measure a time (t 2 ) for the capacitor  92  to discharge from its initial voltage value V 0  to the voltage value V 1  using a similar process as described above. In one embodiment, the resistance of the switch  98  may be smaller than the resistance of the switch  96 . As such, the time t 2  for the capacitor  92  to discharge to the voltage value V 1  using the switch  98  may be smaller than the time t 1  for the capacitor  92  to discharge to the voltage value V 1  using the switch  96 .  FIG. 9  illustrates a graph  140  that depicts how the capacitor  92  may discharge using the switch  96  (SW 1 ) and the switch  98  (SW 2 ). 
     Using the two times (i.e., t 1  and t 2 ) for the capacitor  92  to discharge from the initial voltage value V 0  to the voltage value V 1 , the processor  18 , at block  134 , may determine values for the COG resistance  76  and the FOG resistance  78  using the voltage response of the capacitor  92 , as shown in Equations 2-4. That is, since the initial voltage value V 0 , the voltage value V 1 , the capacitance of the capacitor  92 , the times t 1  and t 2 , and the resistance of each switch (e.g., switch  96  and switch  98 ) are known, the processor  18  may generate two equations based on Equation 4 to determine the two unknown resistance values: R COG  and R FOG . For instance, Equation 4 may be written based on the above information as follows:
 
 R   COG   +R   FOG   +R   SW1   =t   1   /C /(−ln( V   1   /V   0 ))  (5)
 
 R   COG   +R   FOG   +R   SW2   =t   2   /C /(−ln( V   1   /V   0 ))  (6)
 
     The processor  18  may then use Equations 5-6 to solve for R COG  and R FOG , thereby monitoring the values of the COG resistance  76  and the FOG resistance  78  after the display  12  has been assembled into its respective electronic device  10 . In one embodiment, the processor  18  may periodically perform the method  120  to determine the values of the COG resistance  76  and the FOG resistance  78  over time as the display  12  ages. As such, the processor  18  may store logs that include the values of the COG resistance  76  and the FOG resistance  78  over time. The processor  18  may also send the logs of the COG resistance  76  and the FOG resistance  78  values to a server for review by the manufacturer of the electronic device  10 , the manufacturer of the display  12 , or the like. In this manner, the performance of the display  12  may be monitored over time. The logs of the COG resistance  76  and the FOG resistance  78  values over time may be useful in comparing the performances of various types of the display  12 , which may be produced by different manufacturers. Further, the processor  18  may determine the COG resistance  76  and the FOG resistance  78  values at any time after the display  12  has been placed in its respective product without the use of a separate non-functioning glass. 
     In addition to the method  120  of  FIG. 8 , the processor  18  may determine the COG resistance  76  and the FOG resistance  78  values employing a method  150  of  FIG. 10 . As such, at block  152 , the processor  18  may receive two voltage values (V 1  and V 2 ), which may be voltages between the initial voltage V 0  of the capacitor  92  (e.g., touch period voltage) and the display period voltage (i.e., between time T 2  and time T 3 ) or the display period voltage. 
     At block  154 , the processor  18  may discharge the capacitor  92  to the voltage value V 1  received at block  152  using a first switch (e.g., switch  96 ). That is, the processor  18  may close the switch  96 , thereby coupling the capacitor  92  to ground  100  and discharging the capacitor  92 . 
     The processor  18  may then, at block  156 , measure a time (t 1 ) it takes for the capacitor  92  to discharge from the voltage value V 0  to the voltage value V 1 . As mentioned above, to measure the time t 1 , the processor  18  may adjust the variable resistor  101  of the display driver IC such that the comparator  102  changes state when the voltage of the capacitor  92  reaches the voltage value V 1 . The processor may then calculate the time t 1  for the capacitor  92  to discharge from its initial voltage value V 0  to the voltage value V 1  based on a number of counts between when the switch  96  was closed and when the comparator  102  changed states, as determined by the counter/controller circuit  106 . At block  158 , after the processor  18  determines that the capacitor  92  has reached the voltage value V 1 , the processor  18  may open the switch  96 . 
     At block  160 , after the capacitor  92  has been recharged to its initial voltage value V 0 , the processor  18  may discharge the capacitor  92  to the voltage value V 2  using a second switch (e.g., switch  98 ). The processor  18  may then, at block  162 , measure a time (t 2 ) for the capacitor  92  to discharge from its initial voltage value V 0  to the voltage value V 2  using a similar process as described above. In one embodiment, the resistance of the switch  98  may be smaller than the switch  96 . As such, the time t 2  for the capacitor  92  to discharge to the voltage value V 2  using the switch  98  may be smaller than the time t 1  for the capacitor  92  to discharge to the voltage value V 1  using the switch  96 .  FIG. 11  illustrates a graph  170  that depicts how the capacitor  92  may discharge using the switch  96  (SW 1 ) and the switch  98  (SW 2 ) in accordance with method  150 . 
     Using the two times (i.e., t 1  and t 2 ) for the capacitor  92  to discharge to the voltage value V 1  and the voltage value V 2 , the processor  18 , at block  164 , may determine the COG resistance  76  and the FOG resistance  78  values using the voltage response of the capacitor  92 . That is, since the initial voltage value V 0 , the voltage value V 1 , the voltage value V 2 , the capacitance of the capacitor  92 , the times t 1  and t 2 , and the resistance of each switch (e.g., switch  96  and switch  98 ) are known, the processor  18  may generate two equations based on Equation 4 to determine the two unknown resistance values: R COG  and R FOG . For instance, Equation 4 may be written based on the above information as follows:
 
 R   COG   +R   FOG   +R   SW1   =t   1   /C /(−ln( V   1   /V   0 ))  (7)
 
 R   COG   +R   FOG   +R   SW2   =t   2   /C/ (−ln( V   2   /V   0 ))  (8)
 
     The processor  18  may then use Equations 7-8 to solve for R COG  and R FOG , thereby monitoring the values of the COG resistance  76  and the FOG resistance  78  after the display  12  has been assembled into its respective electronic device  10 . Like method  120 , the processor  18  may periodically perform the method  150  to determine the values of the COG resistance  76  and the FOG resistance  78  over time as the display  12  ages, which may be useful in assessing the quality and durability of the display  12 . Further, the processor  18  may send the COG resistance  76  and the FOG resistance  78  values to a server, which may be accessed by a display manufacturer, an electronic device manufacturer, or the like. 
     Keeping the foregoing in mind, the processor  18  may also determine the COG resistance  76  and the FOG resistance  78  values based on the initial voltage value V 0 , the voltage value V 1 , the voltage value V 2 , the capacitance of the capacitor  92 , the times t 1  and t 2 , the resistance of each switch (switch  96  and switch  98 ), and the voltage (V trip ) at the node  108  when the voltage value of the capacitor  92  is equal to the voltage value V 1  and the voltage value V 2 . That is, since the voltage (V trip ) may be known based on the ratio of the resistance of the resistor  99  to the variable resistor  101  and the reference voltage value (V ref ), the voltage (V trip ) at the node  108  may be used to determine the COG resistance  76  and the FOG resistance  78  values according to the following equations:
 
 V   trip   =V   1 *( R   SW1 /( R   COG   +R   FOG   +R   SW1 )  (9)
 
 R   SW1 =( R   COG   +R   FOG )* V   trip /( V   1   −V   trip )  (10)
 
 R   COG   +R   FOG =(1 −V   trip   /V   1 )*(− t   1   /C /ln( V   1   /V   0 )  (11)
 
 R   COG   +R   FOG =(1 −V   trip   /V   2 )*(− t   2   /C/ ln( V   2   /V   0 )  (12)
 
     The processor  18  may then use Equations 11-12 to solve for R COG  and R FOG , thereby monitoring the values of the COG resistance  76  and the FOG resistance  78  after the display  12  has been assembled into its respective electronic device  10 . As mentioned above, the processor  18  may periodically determine the COG resistance  76  and the FOG resistance  78  values over time as the display  12  ages, which may be useful in assessing the quality and durability of the display  12 . 
     In another embodiment, the processor  18  may determine the COG resistance  76  and the FOG resistance  78  values employing a method  180  of  FIG. 12 . As such, at block  182 , the processor  18  may receive a voltage value (V 1 ), which may be a voltage between the initial voltage value V 0  of the capacitor  92  (e.g., touch period voltage) and the display period voltage (i.e., between time T 2  and time T 3 ) or the display period voltage. 
     At block  184 , the processor  18  may discharge the capacitor  92  to the voltage value V 1  received at block  182  using a first switch (e.g., switch  96 ). That is, the processor  18  may close the switch  96 , thereby coupling the capacitor  92  to ground  100  and discharging the capacitor  92 . 
     The processor  18  may then, at block  186 , measure a time (t 1 ) it takes for the capacitor  92  to discharge to the voltage value V 1 . The processor may then calculate the time t 1  for the capacitor  92  to discharge from its initial voltage value V 0  to the voltage value V 1  based on a number of counts between when the switch  96  was closed and when the comparator circuit  102  changed states, as described above. 
     At block  188 , the processor  18  may open the switch  96 . After the capacitor  92  has been recharged to its initial voltage value V 0 , at block  190 , the processor  18  may adjust the variable resistor  101  to modify the trip voltage (V trip ) for the comparator  102  such that the comparator  102  changes states at time t 1  when the capacitor  92  is being discharged using a different switch (e.g., switch  98 ) (SW 2 ).  FIG. 13  illustrates a graph  200  that depicts how the capacitor  92  may discharge according to the method  180  using the switch  96  (SW 1 ) and the switch  98  (SW 2 ). 
     As indicated in the graph  200 , the processor  18  may discharge the capacitor  92  using a second switch (e.g., switch  98 ) until time t 1  expires, at which time the comparator  102  switches states. In this manner, the capacitor  92  may discharge to voltage value V 2 , as shown on the graph  200 . Using the time (t 1 ), the voltage value V 1 , and the voltage value V 2 , the processor  18 , at block  194 , may determine the COG resistance  76  and the FOG resistance  78  values using the voltage response of the capacitor  92 . That is, since the initial voltage value V 0 , the voltage value V 1 , the voltage value V 2 , the capacitance of the capacitor  92 , the time t 1 , and the resistance of each switch (switch  96  and switch  98 ) are known, the processor  18  may generate two equations based on equation 4 to determine the two unknown resistance values: R COG  and R FOG . For instance, Equation 4 may be written based on the above information as follows:
 
 R   COG   +R   FOG   +R   SW1   =t   1   /C /(−ln( V   1   /V   0 ))  (13)
 
 R   COG   +R   FOG   +R   SW2   =t   1   /C /(−ln( V   2   /V   0 ))  (14)
 
     The processor  18  may use Equations 13-14 to solve for R COG  and R FOG , thereby monitoring the values of the COG resistance  76  and the FOG resistance  78  after the display  12  has been assembled into its respective electronic device  10 . Like methods  120  and  150 , the processor  18  may periodically perform the method  180  to determine the COG resistance  76  and the FOG resistance  78  values over time as the display  12  ages, which may be useful in assessing the quality and durability of the display  12 . Further, the processor  18  may send the COG resistance  76  and the FOG resistance  78  values to a server, which may provide access to the COG resistance  76  and the FOG resistance  78  values to other entities (e.g., manufacturer). 
     In yet another embodiment, an external direct current (DC) voltage source may replace the capacitor  92  of the display driver IC  74  as shown in block diagram  210  of  FIG. 14 . Here, an external voltage source  212  may be coupled to the supply rail  93  in series with the switches  94  and the resistor  99  and the variable resistor  101 . In one embodiment, the external voltage source  212  may be disposed on the FOG circuit  28  and coupled to the supply rail  93  via test points (not shown). Since a voltage (V 3 ) at node  109  may be determined based on the reference voltage (V REF ) and a ratio of the resistor  99  and the variable resistor  101 , the processor  18  may determine the total resistance of the COG resistance  76  and the FOG resistance  78  by applying Ohm&#39;s law, as shown in Equation 15 below:
 
 R   COG   +R   FOG =( V   EXT   −V   3 )/ I   EXT   (15)
 
where V EXT  is the DC voltage value of the external voltage source  212 , V 3  is the voltage at the node  109  between the COG resistance  76  and the resistor  99  of the block diagram  210 , and I EXT  is the DC current on the supply rail  93 . Although the resistor  99  has been described throughout this disclosure as a static resistor, it should be noted that in certain embodiments and for any method described herein, the resistor  99  and the variable resistor  101  may be standard resistor or a variable resistor.
 
     Keeping the block diagram  210  of  FIG. 14  in mind,  FIG. 15  illustrates a method  220  for determining values of the COG resistance  76  and the FOG resistance  78  in the display  12  using the external voltage source  212  of  FIG. 14 . Referring now to  FIG. 15 , at block  222 , the processor  18  may connect the external voltage source  212  to the supply rail  93  via test points in the FOG circuit  28 . 
     At block  224 , the processor  18  may close one of the switches  94  such that a DC current (I EXT ) conducts through the closed switch. At block  226 , the processor  18  may measure the DC current (I EXT ) across the COG resistance  76  and the FOG resistance  78 . The DC current may be measured using a current probe, source measurement units (SMU), or the like. The processor  18  may then, at block  228 , adjust the variable resistor  101  such that the comparator  102  trips. By tripping the comparator  102 , the processor  18  may determine the voltage V 3  at node  109  based on the known trip voltage (V trip ) and the resistance values of the resistor  99  and the variable resistor  101 . Using the voltage V 3 , the trip voltage (V trip ), and the value of the resistor  99 , the processor  18  may determine the DC current value by applying Ohm&#39;s law. At block  230 , the processor may determine the R COG  and R FOG  values based on the Equation 15 provided above. Like the methods described above, the processor  18  may periodically perform the method  220  to determine the values of the COG resistance  76  and the FOG resistance  78  over time as the display  12  ages, which may be useful in assessing the quality and durability of the display  12 . 
     The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

Metadata:
Filing Date: 20120831
Publication Date: 20151208
Grant Date: 20151208
Priority Date: 20120831
Inventors: AL-DAHLE AHMAD
BI YAFEI
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G3/006", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2330/12", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0408", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/36", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2300/0408", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/36", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G3/006", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2330/12", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 50186872