PATENT DOCUMENT

Publication Number: US-10122275-B2
Application Number: US-201715403255-A
Country: US
Kind Code: B2

Title: Constant off-time control method for buck converters using coupled inductors

Abstract:
A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to through first and second coupled inductors, respectively, to a power supply node of a circuit block. The first phase unit may be configured to discharge, for a first period of time, the power supply node through the first inductor in response to determining a sense current is greater than a demand current. The operation of the second phase unit may follow that of the first phase unit after a second period of time has elapsed.

Claims:
What is claimed is: 
     
       1. An apparatus, comprising:
 a first inductor coupled to a power supply node of a circuit block; 
 a second inductor coupled to the power supply node of the circuit block and inductively coupled to the first inductor; 
 a first phase unit includes a first driver circuit coupled to the first inductor, wherein the first phase unit is configured to:
 discharge, for a first time period, the power supply node through the first inductor; and 
 charge the power supply node through the first inductor in response to a determination that the first time period has expired; 
 determine a first average voltage at a first output terminal of the first driver circuit while charging the power supply node through the first inductor; and 
 
 a second phase unit including a second driver circuit coupled to the second inductor, wherein the second phase unit is configured to:
 discharge, for a second time period, the power supply node through the second inductor; 
 charge the power supply node through the second inductor in response to a determination that a third time period has expired since the first phase unit began to charge the power supply node through the first inductor; 
 determine a second average voltage at a second output terminal of the second driver circuit while charging the power supply node through the second inductor; and 
 adjust the second time period using the first average voltage and the second average voltage. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the first phase unit includes a first filter circuit coupled to the first output terminal, wherein the first filter circuit is configured to generate a first filtered voltage using a voltage level of first output terminal, wherein the second phase unit includes a second filter circuit coupled to the second output terminal, wherein the second filter circuit is configured to generate a second filtered voltage using a voltage level of the second output terminal, wherein to adjust the second time period, the second phase unit is further configured to compare the first filtered voltage and the second filtered voltage. 
     
     
       3. The apparatus of  claim 1 , wherein the first phase unit is further configured to:
 generate a demand current using a reference voltage and a voltage level of the power supply node; 
 compare the demand current to a current being sourced to the power supply node through the first inductor; and 
 discharge, for the first time period, the power supply node through the first inductor in response to a determination that current being source to the power supply node is greater than the demand current. 
 
     
     
       4. A method for operating a voltage regulator unit, the method comprising:
 discharging, for a first time period, a power supply node of a circuit block through a first inductor; 
 in response to determining the first time period has expired:
 charging the power supply node through the first inductor; and 
 discharging, for a second time period, the power supply node through a second inductor, wherein the second inductor is inductively coupled to the first inductor; 
 
 determining a first average voltage at a first output terminal of a first driver circuit coupled to the first inductor during the charging of the power supply node through the first inductor; 
 charging the power supply node through the second inductor in response to determining that a third time period has expired since initiating the charging of the power supply node through the first inductor; 
 determining a second average voltage at a second output terminal of a second driver circuit coupled to the second inductor during the charging of the power supply node through the second inductor; and 
 adjusting the second time period using the first average voltage and the second average voltage. 
 
     
     
       5. The method of  claim 4 , wherein determining the first average voltage includes filtering a first voltage level at the first output terminal of the first driver circuit and filtering a second voltage level at the second output terminal of the second driver circuit. 
     
     
       6. The method of  claim 5 , wherein adjusting the second time period using the first average voltage and the second average voltage includes performing a comparison between the first voltage level and the second voltage level, and updating a count value using a result of the comparison. 
     
     
       7. The method of  claim 4 , further comprising generating a pulse signal using a result of comparing a demand current and a current being sourced to the power supply node of the circuit block through the first inductor. 
     
     
       8. The method of  claim 7 , further comprising:
 generating a demand current using a reference voltage and a voltage level of the power supply node; 
 comparing the demand current and a current being sourced to the power supply node through the first inductor; and 
 discharging, for the first time period, the power supply node in response to determining that the current being sourced to the power supply node is greater than the demand current. 
 
     
     
       9. A system, comprising:
 a plurality of circuit blocks; and 
 a regulator unit including a first inductor coupled to a power supply node of a particular circuit block, a first driver circuit coupled to the first inductor, a second inductor coupled to the power supply node, a second driver circuit coupled to the second inductor, wherein the second inductor is inductively coupled to the first inductor, and wherein the regulator unit is configured to:
 discharge, for a first time period, the power supply node through the first inductor; 
 charge the power supply node through the first inductor in response to a determination that the first time period has expired; and 
 discharge, for a second time period, the power supply node through the second inductor; 
 determine a first average voltage at a first output terminal of the first driver circuit while charging the power supply node through the first inductor; 
 charge the power supply node through the second inductor in response to a determination that a third time period has expired since a charging of the power supply node through the first inductor was initiated; 
 determine a second average voltage at a second output terminal of the second driver circuit while charging of the power supply node through the second inductor; and 
 adjust the second time period using the first average voltage and the second average voltage. 
 
 
     
     
       10. The system of  claim 9 , wherein the regulator unit includes:
 a first filter circuit coupled to the first output terminal, wherein the first filter circuit is configured to generate a first filtered voltage using a voltage level of first output terminal; and 
 a second filter circuit coupled to the second output terminal, wherein the second filter circuit is configured to generate a second filtered voltage using a voltage level of the second output terminal; and 
 wherein to adjust just the second time period, the regulator unit is further configured to compare the first filtered voltage and the second filtered voltage. 
 
     
     
       11. The system of  claim 9 , wherein the regulator unit is further configured to generate a pulse signal using a result of comparing a demand current and a current being sourced to the power supply node of a particular circuit block of the plurality of circuit blocks through the first inductor. 
     
     
       12. The system of  claim 9 , wherein the regulator unit is further configured to;
 generate a demand current using a reference voltage and a voltage level of a power supply node; 
 compare the demand current and a current being sourced to the power supply node of a particular circuit block of the plurality of circuit blocks through the first inductor; and 
 discharge, for the first time period, the power supply node in response to a determination that the current being sourced to the power supply node is greater than the demand current.

Description:
PRIORITY INFORMATION 
     The present application claims benefit of priority to U.S. Provisional Application No. 62/398,312 titled “A CONSTANT OFF-TIME CONTROL METHOD FOR BUCK CONVERTERS USING COUPLED INDUCTORS” and filed on Sep. 22, 2016, which is hereby incorporated by reference in it entirety as though fully and completely set forth herein. 
    
    
     BACKGROUND 
     Technical Field 
     Embodiments described herein relate to integrated circuits, and more particularly, to techniques for generating regulated power supply voltages. 
     Description of the Related Art 
     A variety of electronic devices are now in daily use with consumers. 
     Particularly, mobile devices have become ubiquitous. Mobile devices may include cell phones, personal digital assistants (PDAs), smart phones that combine phone functionality and other computing functionality such as various PDA functionality and/or general application support, tablets, laptops, net tops, smart watches, wearable electronics, etc. 
     Such mobile devices may include multiple integrated circuits, each performing different tasks. In some cases, circuits that perform different tasks may be integrated into a single integrated forming a system on a chip (SoC). The different functional units within a SoC may operate at different power supply voltage levels. In some designs, power supply or regulator circuits may be included in, or external to, the SoC to generate different voltage levels for the myriad functional units included in the SoC. 
     Regulator circuits may include one or more reactive circuit components. For example, individual regulator sub-assemblies may employ a combination of inductors or capacitors. The reactive circuit components may be fabricated on an integrated circuit with the regulator circuits, or they may be included as discrete components in a semiconductor package or circuit board. 
     SUMMARY OF THE EMBODIMENTS 
     Various embodiments of a system including an integrated circuit die and decoupling unit are disclosed. Broadly speaking, a system is contemplated in which a first inductor is coupled to a power supply node of a circuit block, and a second inductor is coupled to the power supply node and is inductively coupled to the first inductor. A first phase unit may be configured to generate a demand current using a reference voltage and a voltage level of the power supply node, and to compare the demand current to a current being source to the power supply node through the first inductor. The first phase unit may be further configured to discharge, for a first time period, the power supply node through the first inductor in response to a determination that the current being sourced to the power supply node is greater than the demand current. Additionally, the first phase unit may charge the power supply node through the first inductor in response to a determination that the first time period has expired. The second phase unit may be configured to discharge, for a second time period, the power supply node through the second inductor and charge the power supply node through the second inductor in response to a determination that a third time period has expired since the first phase unit began to charge the power supply node through the first inductor. 
     In one embodiment, the first phase unit may include a first driver circuit coupled to the first inductor. The first phase unit may be further configured to determine a first average voltage at a first output terminal of the first driver circuit while charging the power supply node through the first inductor. 
     In a further embodiment, the second phase unit may include a second driver circuit coupled to the second inductor. The second phase unit may be further configured to determine a second average voltage at a second output terminal of the second driver circuit while charging of the power supply node through the second inductor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG. 1  illustrates an embodiment of a computing system. 
         FIG. 2  illustrates an embodiment of a regulator unit. 
         FIG. 3  illustrates an embodiment of a phase unit of a regulator unit. 
         FIG. 4  illustrates another embodiment of a phase unit of a regulator unit. 
         FIG. 5  depicts an embodiment of a filter circuit. 
         FIG. 6  depicts examples waveforms associated with operating an embodiment of a regulator unit. 
         FIG. 7  depicts a flow diagram illustrating an embodiment of a method for operating a regulator unit. 
     
    
    
     While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the disclosure to the particular form illustrated, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to. 
     Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, paragraph (f) interpretation for that unit/circuit/component. More generally, the recitation of any element is expressly intended not to invoke 35 U.S.C. § 112, paragraph (f) interpretation for that element unless the language “means for” or “step for” is specifically recited. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Computing systems may include multiple functional units or circuit blocks. These circuit blocks may be mounted together in a common integrated circuit package, or circuit board. Some computing systems may include multiple circuit blocks on a single integrated circuit, commonly referred to as a “System-on-a-chip” or “SoC.” Each circuit block within a computing system, may operate at a different voltage levels, which may be different than a voltage level of a master power supply of the computing system. In order to generate the desired voltage levels, one or more regulator units may be employed. 
     In some computing systems, DC-DC switching regulators are used to generate the desired voltage levels. Switching regulators rapidly switch a series of devices, such as, e.g., transistors, on and off in order to transfer charge to or from a load through an inductor (commonly referred to as a “charge cycle” and “discharge cycle,” respectively). The load may include one or more of the aforementioned circuit blocks. By adjusting the duration of the time individual devices are switched on and off, the voltage level at the load may be kept within a predetermined range of a desired value. 
     To control how the devices are switched on and off in order to maintain the desired value voltage level at the load, regulators employ varying control methods. For example, in current mode control methods, slope compensation may be required to maintain stability of the current loop. The circuits associated with performing slope compensation add area, power consumption, and complexity to a regulator. 
     In cases were multiple coupled inductors are employed, slope compensation circuits may become even more complicated. The embodiments illustrated in the drawings and described below may provide techniques for using multiple coupled inductors with a constant off-time control mechanism in a regulator unit while limiting the impact on design complexity, area, and power consumption. 
     A block diagram of a computing system including multiple devices or functional units is illustrated in  FIG. 1 . In the illustrated embodiment, computing system  100  includes regulator unit  101 , and Circuit Blocks  102   a  and  102   b . Regulator Unit  101  is coupled to power supply  105 , and regulated power supply  103 . Circuit Blocks  102   a  and  102   b  are also coupled to regulated power supply  103 . Additionally, Circuit Block  102   a  is coupled to Circuit Block  102   b  via communication bus  104 . 
     As described below in more detail, Regulator Unit  101  may, in various embodiments, be configured to generate regulated power supply  103  using power supply  105 . A voltage level of regulated power supply  103  may be less than, equal to, or greater than a voltage level of power supply  105  dependent upon the needs of Circuit Blocks  102   a  and  102   b . Although only a single regulated power supply is depicted in the embodiment illustrated in  FIG. 1 , in other embodiments, multiple regulated power supplies may be employed. In such cases, different devices may be coupled different regulated power supplies. Alternatively, a single device may be coupled to multiple regulated power supplies. 
     In the illustrated embodiment, either of Circuit Blocks  102   a  or  102   b  may include a processor, processor complex, or a memory. In some embodiments, Circuit Blocks  102   a  and  102   b  may include Input/Output (I/O) circuits or analog/mixed-signal circuits. In various embodiments, computing system  100  may be configured for use in a desktop computer, server, or in a mobile or wearable computing application. It is noted that although  FIG. 1  illustrates only two circuit blocks, in other embodiments, any suitable number of circuit blocks may be employed. Additional communication busses may also be employed to connect the various devices. 
     As used and described herein, a processor or processor complex having one or more processors or processor cores may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, a processor may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). 
     In the present disclosure, a memory may describe any suitable type of memory such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a Read-only Memory (ROM), Electrically Erasable Programmable Read-only Memory (EEPROM), or a non-volatile memory, for example. 
     Analog/mixed-signal circuits may include a variety of circuits including, for example, a crystal oscillator, a phase-locked loop (PLL), an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC) (all not shown). In other embodiments, analog/mixed-signal circuits included in one of devices  102   a  or  102   b  may include, radio frequency (RF) circuits that may be configured for operation with wireless networks. 
     As used herein, I/O circuits may be configured to coordinate data transfer between computing system  100  and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, I/O circuits may be configured to implement a version of Universal Serial Bus (USB) protocol, IEEE 1394 (Firewire®) protocol, or an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet. 
     In some embodiments, each of the aforementioned circuit blocks may include multiple circuits, each of which may include multiple devices, such as, e.g., metal-oxide semiconductor field-effect transistors (MOSFETs) connected via multiple wires fabricated on multiple conductive layers. The conductive layers may be interspersed with insulating layers, such as, silicon dioxide, for example. Each circuit may also contain wiring, fabricated on the conductive layers, designated for a power supply net (or node) or a ground supply net (or node). 
     Each of Regulator Unit  101  and Circuit Blocks  102   a  and  102   b  may, in various embodiments, be fabricated on a silicon wafer (or simply “wafer”) along with numerous identical copies of Regulator Unit  101  and Circuit Blocks  102   a  and  102   b , each of which may be referred to as a “chip” or “die.” During manufacture, various manufacturing steps may be performed on each chip in parallel. Once the manufacturing process has been completed, the individual chips may be removed from the wafer by cutting or slicing through unused areas between each chip. 
     In other embodiments, Regulator Unit  101  may be fabricated on a separate chip than Circuit Blocks  102   a  and  102   b . In such cases, Regulator Unit  101  and Circuit Blocks  102   a  and  102   b  may be coupled together inside a semiconductor package. 
     Alternatively, Regulator Unit  101  and Circuit Blocks  102   a  and  102   b  may be mounted on a common circuit board or other suitable substrate. In such cases, wiring for regulated power supply  103  and communication bus  104  may include multiple metal layers fabricated into the package or circuit board. 
     Turning now to  FIG. 2 , an embodiment of a regulator unit is illustrated. Regulator unit  200  may, in various embodiments, correspond to Regulator Unit  101  as depicted in  FIG. 1 . In the illustrated embodiment, regulator unit  200  includes phase units  201   a - b , Reference Generator  205 , filters  210   a - b , and inductors  211   a - b.    
     Each of phase units  201   a  and  201   b  may be configured to charge or discharge Regulated Supply  204 , by sourcing to or sinking current from Regulated Supply  204 , through inductors  211   a  and  211   b , respectively. As described below in more detail in regard to  FIG. 3  and  FIG. 4 , each phase unit of phase units  201   a - d  may operate differently. 
     In the illustrated embodiment, Phase- 0  Unit  201   a  may initiate a discharge cycle (also referred to as an “off cycle”) in response to a determination that the current being sourced to Regulated Supply  204  is greater than current being demanded by a load circuit coupled to Regulated Supply  204 . Phase- 0  Unit  201   a  may then sink current, i.e., discharge Regulated Supply  204 , through inductor  211   a  for a predetermined period of time. This period of time is commonly referred to as a “constant off time.” Since Phase- 0  Unit  201   a  begins to discharge Regulated Supply  204  based on current measurements, it may be referred to as a “Master Phase Unit.” 
     Phase- 1  Unit  201   b , however, begins a discharge of Regulated Supply  204 , by sinking current through inductor  211   b , in response to the discharge by Phase- 0  Unit  201   a . The initiation of charging and discharging by Phase- 1  Unit  201   b  tracks that of Phase- 0  Unit  201   a  after a predetermined delay. Since the operation of Phase- 1  Unit  201   b  tracks that of Phase- 0  Unit  201   a , Phase- 1  Unit  201   b  may referred to as a “Slave Phase Unit.” 
     As described below in more detail in regard to  FIG. 3  and  FIG. 4 , each of Phase- 0  Unit  201   a  and Phase- 0  Unit  201   b  includes a driver circuit configured to source current to or sink current from Regulated Supply  204  through a respective one of inductors  211   a  and  211   b . Due to on-die variations, or other manufacturing effects, the DC currents sourced by the two different phase units may be different. 
     To compensate for an offset between the two DC currents, the delay by which Phase- 1  Unit  201   b  tracks Phase- 0  Unit  201   a  may be adjusted. The adjustment is made based on a comparison of average voltages at the outputs of the two phase units. To generate the average voltages, Filters  210   a  and  210   b  are coupled to the output terminals of the driver circuits of Phase- 0  Unit  201   a  and Phase- 1  Unit  201   b , respectively. As described below in regard to  FIG. 5 , each of Filters  210   a  and  210   b  is configured to perform a low-pass filter function in order to generate Filter signals  208  and  209 , respectively. Filter signals  208  and  209  are coupled to Phase- 1  Unit  201   b  to allow for the adjust the delay between the two phase units. 
     Inductor  211   a  is coupled between an output terminal of Phase- 0  Unit  201   a  and Regulated Supply  204 . In a similar fashion, inductor  211   b  is coupled between an output terminal of Phase- 1  Unit  201   b  and Regulated Supply  204 . Inductors  211   a  and  211   b  are also inductively coupled to each other. The amount of coupling is specified by Coupling coefficient  212 . In various embodiments, the amount of coupled between inductors  211   a  and  211   b  may be determined based on the physical proximity between the two inductors. In some cases, additional materials may be deposited between the two inductors to enhance inductive coupling between the two inductors. 
     Inductors  211   a  and  211   b  may be included in an integrated circuit with the remaining circuits blocks of regulator unit  200 . In other embodiments, inductors  211   a  and  211   b  may be fabricated on a separate integrated circuit die, which may then be coupled to an integrated circuit die including regulator unit  200  during a package assembly process. 
     Reference Generator  205  may be configured to generate a predetermined voltage level (also referred to herein as a “reference voltage level”) for reference voltage  207 . The reference voltage level may, in various embodiments, be adjustable upon completion of a manufacturing process. Alternatively, or additionally, the reference voltage level may be adjustable during operation by the programming of one or more registers (not shown) in response to changes in operating mode of a computing system, or in response to the execution of one or more software instructions by a processor included in the computing system. 
     In various embodiments, Reference Generator  205  may include a band gap reference circuit, or other suitable reference circuit, for generating a temperature and/or power supply independent reference voltage. Reference Generator  205  may also include one or more current mirrors, amplifiers, or other suitable analog circuitry necessary to adjust an initially generated voltage level to a desired level. 
     It is noted that the embodiment depicted in  FIG. 2  is merely an example. In other embodiments, different functional units, and different arrangements of functional units are possible and contemplated. 
     An embodiment of Phase- 0  Unit  201   a  is illustrated in  FIG. 3 . In the illustrated embodiment, Phase- 0  Unit  201   a  includes transconductance amplifier  301 , comparator  320 , Pulse Generator  316 , Delay Circuit  302 , latch  303 , driver circuit  313 , pre-driver  318 , and Current Sensor  306 . 
     Transconductance amplifier  301  may be configured to convert a difference between reference voltage  207  and Regulated Supply  204  to i demand  current flowing in node  314 . In general, a value of i demand  current may be proportional to a difference between reference voltage  207  and Regulated Supply  204 . In some embodiments, transconductance amplifier  301  is operated without negative feedback, i.e., is may be operated “open loop.” 
     Comparator  320  may be configured to generate an output signal on node  309  based upon a difference between i demand  current and i sense  current flowing in node  315 . In various embodiments, a voltage level of the signal on node  309  may be proportional to the difference between the values of the two aforementioned currents. In other embodiments, comparator  320  may generate a digital signal whose logic low level corresponds to a ground potential and whose high logic high level corresponds to a voltage level sufficient to enable a n-channel metal-oxide field-effect transistor (MOSFET). 
     In some embodiments, Pulse generator  316  may be configured to generate a pulse on reset  317  based on the voltage level of the signal on node  309 . Pulse generator may, in various embodiments, includes delay circuits, and logic gates arranged to generate pulses from either one or the other of rising or falling edges of the signal on node  309 . 
     Latch circuit  303  may, in various embodiments, correspond to a specific embodiment of a reset-set (RS) latch, and may be designed in accordance with one of varying design styles, including, but not limited to, both static and dynamic implementations. In the illustrated embodiment, the complementary output of latch  303 , denoted as Q-bar, may be set to a low logic value in response to the assertion of a particular pulse occurring on set  307 . Latch  303  may be reset, i.e., output Q-bar set to a high logic level, in response to the assertion of reset  317 . 
     Delay Circuit  302  is configured to delay reset  317  in order to generate set  307 . In various embodiments, Delay Circuit  302  may include multiple delay lines through which reset  317  is routed. The selection of which delay lines are employed may be configurable during operation or during an initialization routine for Phase- 0  Unit  201   a . In other embodiments, Delay Circuit  302  may include an analog delay circuit whose delay value is determined by a voltage level of a control signal (not shown). 
     In some embodiments, pre-driver circuit  318  may include circuitry configured to generate control signals  319   a  and  319   b , coupled to transistors  304  and  305 , respectively. In response to changes in the logic level on node  312 , pre-driver  318  may independently assert and de-assert control signals  319   a  and  319   b . In some embodiments, an asserted one of control signals  319   a  and  318   b  may be de-asserted prior to assertion of the de-asserted control signal. By independently asserting and de-asserting control signals  319   a  and  319   b , current flow from the power supply to ground through the driver (commonly referred to as “shoot through” current) may be reduced in various embodiments. 
     Driver circuit  313  may, in various embodiments, includes transistor  304  and transistor  305 . In some embodiments, transistor  304  may correspond to a p-channel MOSFET, and may be configured to source current to Output  308 , thereby charging Regulated Supply  204 , in response to a low logic level on control signal  319   a . Transistor  305  may, in various embodiments, correspond to an n-channel MOSFET, and may be configured to sink current from Output  308 , thereby discharging Regulated Supply  204 , in response to a high logic level on control signal  319   b . It is noted that although driver circuit  313  is depicted as using MOSFETs, in other embodiments, any suitable transconductance device may be employed. 
     Current Sensor  306  is configured to determine a current flowing from transistor  304  into Output  308 . The determined current is then sent to the input of Comparator  320  via node  315  as i sense . In various embodiments, Current Sensor  306  may include a resistor in series with transistor  304  and Output  308 . A voltage drop across the resistor may be used to generate i sense . Current Sensor  306  may also include one or more active devices, such as, e.g., MOSFETs, to form current mirrors, or any other suitable circuits than may be employed to generate i sense . 
     It is noted that the embodiment of the capacitor model illustrated in  FIG. 3  is merely an example. In other embodiments, different circuit elements and different configurations of circuit elements may be employed. 
     Turning to  FIG. 4 , an embodiment of Phase- 1  Unit  201   b  is depicted. In the illustrated embodiments, Phase- 1  Unit  201   b  includes Comparator  407 , Counter  409 , Delay Circuit  403 , Delay Circuit  404 , latch  411 , pre-driver  417 , and driver  417 . 
     Comparator  407  may be configured to compare Filter signals  208  and  209 . As described below in regard to  FIG. 5 , Filter signals  208  and  209  are generated by filter circuits, which average the variations in the voltages output by Phase- 0  Unit  201   a  and Phase- 0  Unit  201   b . Depending on which of the two filter signals is greater, Comparator  407  may assert or de-assert signal  408 . In various embodiments, Comparator  407  may include a differential amplifier, or any other circuit suitable for comparing voltage levels. 
     Using the logical state of signal  408 , Counter  409  may increment or decrement a count value. Counter  409  may be incremented or decremented when the signal on node  414  is asserted. In various embodiments, Counter  409  may include any suitable number of bits and may be reset during initialization of the Phase- 1  Unit  201   b . Although not shown, in some embodiments, a particular value may be loaded into Counter  409  following a reset. 
     The output of Counter  409 , signal  410 , is used to control the value of Delay Circuit  403 . Although depicted in  FIG. 4  as a single signal, in various embodiments, signal  410  may include any suitable number of data bits. Delay Circuit  403  may include multiple delay lines, or other suitable circuits that generate delay. A selection of which of the multiple delay lines reset  317  is directed may be dependent upon the value signal  410 . In other embodiments, the value of signal  410  may be used as input to a digital-to-analog converter (DAC) that generates a voltage level used to control an analog delay line through which reset  317  is routed. By adjusting the delay through Delay Circuit  403 , compensation for any difference between the DC currents on Phase- 0  Unit  201   a  and Phase- 1  Unit  201   b  may be realized. 
     In a similar fashion to Delay Circuit  403 , Delay Circuit  404  may generate set  413 , which is a delayed version of set  307  from Phase- 0  Unit  201   a . Delay Circuit  403  may include multiple delay lines, or an analog delay line. In various embodiments, an amount of delay generated by Delay Circuit  403  may be adjustable during operation. 
     Latch  411  is a particular embodiment of an reset-set (RS) latch that is set in response to an assertion of set  413 , and reset in response to an assertion of reset  412 . When latch  411  is set, the complement output of latch  411 , i.e., Q-bar, is at a high logic level, and when latch  411  is reset, Q-bar is at a low logic level. Latch  411  may, in various embodiments, include any suitable combination of logic gates and/or transistors configured to implement the desired function. 
     Pre-driver circuit  415  may include circuitry configured to generate control signals  416   a  and  416   b , coupled to transistors  418   a  and  418   b , respectively. In response to changes in the logic level on node  414 , pre-driver  415  may independently assert and de-assert control signals  416   a  and  416   b . In some embodiments, an asserted one of control signals  416   a  and  416   b  may be de-asserted prior to assertion of the de-asserted control signal. By independently asserting and de-asserting control signals  416   a  and  416   b , shoot through current from the power supply to ground through driver  417  may be reduced. 
     Driver circuit  417  includes transistor  418   a  and transistor  418   b . In some embodiments, transistor  418   a  may correspond to a p-channel MOSFET, and may be configured to source current to Output  419  in response to a low logic level on control signal  416   a . Transistor  418   b  may, in various embodiments, correspond to an n-channel MOSFET, and may be configured to sink current from Output  419  in response to a high logic level on control signal  416   b . It is noted that although driver circuit  417  is depicted as using MOSFETs, in other embodiments, any suitable transconductance device may be employed. 
     It is noted that the embodiment depicted in  FIG. 4  is merely an example. In other embodiments, different circuits and different arrangements of circuits may be included in Phase- 1  Unit  201   b.    
     As described above, the average currents of the two phase units may be employed to compensate for any offset in the DC currents of the two phase units. To generate the average currents, a filter circuit may be used. An embodiment of such a filter circuit is illustrated in  FIG. 5 . In various embodiments, filter  500  may correspond to either of Filters  210   a  or  210   b  as depicted in  FIG. 2 . In the illustrated embodiment, filter  500  includes resistor  503  and capacitor  504 . 
     Resister  503  is coupled to Input signal  501  and Filtered signal  502 . In various embodiments, Input Signal may correspond to the output signal of either Phase Unit  201   a  or Phase Unit  201   b , and Filtered signal  502  may correspond to either of filter signals  208  or  209 . Capacitor  504  is coupled to Filter signal  502  and a ground node. 
     Values of resistor  503  and capacitor  504  may be selected to provide a desired impedance between Input Signal  501  and the ground node at a particular frequency. The desired impedance may result in high frequency components included in Input signal  501  to be shorted to the ground node, thereby providing a low frequency components included in Input signal  501  to appear on Filtered signal  502 . As described above in regard to  FIG. 2  and  FIG. 4 , Filtered signal  502  may be used to determine any current mismatch between Phase Units  201   a  and  201   b.    
     It is noted that the embodiment depicted in  FIG. 5  is merely an example. Although a single resistor and capacitor as show in the embodiment depicted in  FIG. 5 , in other embodiments, different numbers and different arrangements of the resistors and capacitors may be employed. Additionally, or alternatively, other reactive circuit elements, such as, e.g., inductors, may be used to implement the desired filter effect. 
     As an aid in the explanation of the operation of Phase- 0  Unit  201   a  and Phase- 1  Unit  201   b , example waveforms are depicted in  FIG. 6 . At time t 0 , reset  317  is asserted. As described above in regard to  FIG. 3 , the assertion of reset  317  is the result of a determination that i sense  is greater than i demand . Phase- 0  unit  201   a  will begin a discharge of Regulated Supply  204  in response to the assertion of reset  317 . 
     The discharge Regulated Supply  204  by Phase- 0  Unit  201   a  continues until time t 1 , at which point set  307  is asserted, resulting in Phase- 0  Unit  201   a  to stop discharging and begin charging Regulated Supply  204 . The delay from from t 0  to t 1  is determined by the value of Delay Circuit  302 . In various embodiments, Delay Circuit  302  may be adjustable or programmable depending on one or more system operating parameters. 
     At time t 2 , reset  412  is asserted in response to the assertion of reset  317 . The delay from time t 0  to t 2  is determined by the value of Delay Circuit  403 . During operation, the value of Delay Circuit  403  may be adjusted. As described above in regard to  FIG. 4 , a new value of Delay Circuit  403  may be based upon a comparison of the Filter signal  208  and Filter signal  209 . Such an adjustment may compensate for an offset in the DC currents between Phase- 0  Unit  201   a  and Phase- 1  Unit  201   b.    
     As with the assertion of reset  317  triggering the assertion of reset  412  at a later time, the assertion of set  307  triggers the assertion of set  413  at time t 3 . The difference between time t 1  and t 3  is determined by the value of Delay Circuit  404 . Between time t 2  and t 3 , Phase- 1  Unit  201   b  is discharging Regulated Supply  204  through inductor  211   b . Once set  412  is asserted, Phase- 1  Unit  201   b  halts discharging and begins to charge Regulated Supply  204  by sourcing a current to the supply through inductor  211   b.    
     It is noted that the waveforms depicted in  FIG. 6  are merely examples. In other embodiments, different relative timing between the various signals may be possible. 
     Turning to  FIG. 7 , a flow diagram depicting an embodiment of a method for operating a regulator unit is illustrated. Referring collectively to the embodiments of  FIG. 2 ,  FIG. 3 , and  FIG. 4 , and the flow diagram of  FIG. 7 , the method begins in block  701 . For the purposes of explanation, it is assumed that Phase- 0  Unit  201   a  is charging Regulated Supply  204  as the method begins. 
     Transconductance device  301  may generate i demand  (block  702 ). As described above, to generate i demand , transconductance device  301  may determine a different in the voltage levels of Reference  201  and Regulated Supply  204 . The difference in the voltage levels may then be converted into a current. 
     I demand  may then be compared to i sense  (block  703 ). I sense  may be determined using Current sensor  306 . In various embodiments, Current sensor  306  may include a small value resistor, whose voltage drop is measured in order to determined i sense    315 . Current sensor  306  may, in other embodiments, include any suitable circuit capable of measuring a current moving in Output voltage  308 . 
     Based on a result of the comparison between i demand  and i sense , Phase- 0  Unit  201   a  may initiate a discharge cycle (block  704 ). In various embodiments, when i sense  is greater than i demand , Pulse Generator  316  may create a pulse on reset  317 , which, in turn, resets latch  303 . Once latch  303  is reset, signal  312  may transition to a high logic level, activating device  305  discharging Output  308 . The reduction in the voltage level of Output  308  resulting from the activation of device  305  causes a discharge of Regulated Supply  204  through inductor  211   a.    
     After a first time period has elapsed, the discharge cycle being performed by Phase- 0  Unit  201   a  may be halted (block  705 ). The pulse on reset  317  may be delayed by Delay circuit  302  to generate a pulse on set  307 . An amount of delay provided by Delay circuit  302  may be selected such that once pulse on reset  317  has completed, the pulse on set  307  begins. In response to the pulse on set  307 , latch  303  may be set, resulting in a low logic level on node  312 . Pre-driver circuit  318  may transition nodes  319   a - b  to low logic levels, deactivating device  305  and activating device  304 . Current may then flow from the power supply through device  304  to output  308 , through inductor  211   a , resuming the charging of Regulated Supply  204 . Once charging of Regulated Supply  204  has resumed, the method may conclude in block  708 . 
     In parallel to the operations performed in association with block  705 , Phase- 1  Unit  201   b  may initiate a discharge of Regulated Supply  204  through inductor  211   b  after a second time period has elapsed since the initiation of the phase- 0  discharge (block  706 ). The pulse on reset  317  may be delayed by Delay Circuit  403  to generate a delayed pulse on reset  412 . As described above, the second time period is determined by the amount of delay provided by Delay Circuit  403 , which may be adjusted based on a comparison between filter signal  208  and filter signal  209 . In response to the delayed pulse on reset  412 , latch  411  resets causing node  414  to be set to a high logic level. In response to the transition on node  414 , Pre-driver  415  may transition signals  416   a  and  416   b  to high logic levels deactivating device  418   a  and activating device  418   b . The activation of device  418   b  sinks current from Output  419  to ground, which, in turn, discharges Regulated Supply  204  through inductor  211   b.    
     After a third time period has elapsed, Phase- 1  Unit  201   b  may halt the discharge of Regulated Supply  204  through inductor  211   b  and begin to charge Regulated Supply  204  through inductor  211   b  (block  707 ). Set  307  may be delayed by Delay Circuit  404  to generate set  413 . When set  413  is asserted, latch  411  may be set, resulting in a transition on node  414  to a low logic level. In response to the transition of node  414  to a low logic level, pre-driver  415  may transition signals  416   a  and  416   b  to low logic levels, deactivating device  418   b  and activating device  418   a . The activation of device  418   a  sources a current to Output  419 , which, in turn, charges Regulated Supply  204  through inductor  211   b . With the charging of Regulated Supply  204 , the method concludes in block  708 . 
     It is noted that the embodiment of the method depicted in the flow diagram of  FIG. 7  is merely an example. In other embodiments, different operations, and different orders or operations are possible and contemplated. 
     Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure. 
     The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

Metadata:
Filing Date: 20170111
Publication Date: 20181106
Grant Date: 20181106
Priority Date: 20160922
Inventors: PANT, SANJAY
GOZZINI, FABIO
FLETCHER, JAY B.
SEARLES, SHAWN
Assignee: APPLE INC
CPC Classifications: [{"code": "H02M3/1584", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02M3/158", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02M1/08", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02M3/1584", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02M2003/1586", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M2001/0009", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M1/08", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02M3/158", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02M3/1584", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02M3/1586", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M3/1586", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M1/0009", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M1/0009", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 61621416