PATENT DOCUMENT

Publication Number: US-9847284-B2
Application Number: US-201313753027-A
Country: US
Kind Code: B2

Title: Stacked wafer DDR package

Abstract:
A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.

Claims:
What is claimed is: 
     
       1. A semiconductor device package, comprising:
 a first memory die at least partially encapsulated in an encapsulant with at least one surface of the first memory die exposed through the encapsulant; 
 a redistribution layer coupled to the exposed surface of the first memory die, the redistribution layer having a single layer of metal; 
 a second memory die coupled to the redistribution layer, wherein the second memory die is coupled on an opposing surface of the redistribution layer from the first memory die, and wherein the second memory die is offset from the first memory die; 
 a plurality of terminals coupled to the opposing surface of the redistribution layer, wherein the couplings between the redistribution layer and the terminals lie in substantially the same plane as the coupling between redistribution layer and the second memory die; and 
 routing in the redistribution layer, the routing consisting of a first routing and a second routing in the single layer of metal, the first routing consisting of routing between a first set of the terminals and the first memory die and the second routing consisting of routing between a second set of the terminals and the second memory die, wherein the first routing and the second routing are electrically isolated from each other; 
 wherein the first memory die and the second memory die are individually connectable to an additional semiconductor device package through the first set of terminals and the second set of terminals, respectively, and wherein the first memory die and the second memory die independently communicate with the additional package during use due to the electrical isolation of the first routing and the second routing. 
 
     
     
       2. The package of  claim 1 , wherein the terminals are coupled to the redistribution layer on a periphery of the first memory die and a periphery of the second memory die. 
     
     
       3. The package of  claim 1 , wherein the second memory die is flip-chip coupled to the redistribution layer. 
     
     
       4. The package of  claim 1 , wherein the second memory die is coupled to the redistribution layer with a non-conductive paste. 
     
     
       5. The package of  claim 1 , wherein the second memory die is coupled to the redistribution layer with a capillary underfill material. 
     
     
       6. The package of  claim 1 , further comprising a first set of connections between the first memory die and the redistribution layer and a second set of connections between the second memory die and the redistribution layer, wherein the first set of connections are offset from the second set of connections. 
     
     
       7. The package of  claim 1 , wherein the first die and the second die are substantially identical in function. 
     
     
       8. A semiconductor device package, comprising:
 a mold material with a first memory die at least partially enclosed in the mold material; 
 a redistribution layer coupled to a bottom surface of the mold material, the redistribution layer having a single layer of metal; 
 a second memory die coupled to a bottom surface of the redistribution layer, wherein the bottom surface of the redistribution layer is substantially planar, and wherein the second memory die is offset from the first memory die; 
 a plurality of terminals coupled to the substantially planar bottom surface of the redistribution layer on a periphery of the first memory die and a periphery of the second memory die; and 
 routing in the redistribution layer, the routing consisting of a first routing and a second routing in the single layer of metal, wherein the first routing consists of routing that couples the first memory die to a first set of the terminals and the second routing consists of routing that couples the second memory die to a second set of the terminals, the first routing and the second routing being electrically isolated from each other, wherein the first memory die and the second memory die are individually connectable to an additional semiconductor device package through the first set of terminals and the second set of terminals, respectively, and wherein the first memory die and the second memory die independently communicate separately with the additional package during use due to the electrical isolation of the first routing and the second routing. 
 
     
     
       9. The package of  claim 8 , further comprising a non-conductive paste between the second memory die and the redistribution layer. 
     
     
       10. The package of  claim 8 , further comprising a capillary underfill material between the second memory die and the redistribution layer. 
     
     
       11. The package of  claim 8 , wherein the first set of terminals are electrically isolated from the second set of terminals. 
     
     
       12. The package of  claim 8 , wherein the first die and the second die are substantially identical in function. 
     
     
       13. The package of  claim 8 , wherein the first die and the second die have staggered bump patterns. 
     
     
       14. A method for forming a semiconductor device package, comprising:
 at least partially encapsulating a first memory die in an encapsulant with at least one surface of the first memory die exposed through the encapsulant; 
 coupling a first surface of a redistribution layer to the first memory die, the redistribution layer having a single layer of metal, wherein the redistribution layer comprises routing in the single layer of metal, the routing consisting of a first routing and a second routing in the single layer of metal, the first routing and the second routing being electrically isolated from each other; 
 coupling a plurality of terminals to a second surface of the redistribution layer, wherein the first routing consists of routing coupling a first set of the terminals to the first memory die; and 
 coupling a second memory die to the second surface of the redistribution layer, wherein the coupling between the second memory die and the second surface of the redistribution layer and the couplings between the terminals and the second surface of the redistribution layer lie in substantially the same horizontal plane, wherein the second memory die is offset from the first memory die, and wherein the second routing consists of routing coupling a second set of the terminals to the second memory die, wherein the first memory die and the second memory die are individually connectable to an additional semiconductor device package through the first set of terminals and the second set of terminals, respectively, and wherein the first memory die and the second memory die independently communicate with the additional package during use due to the electrical isolation of the first routing and the second routing. 
 
     
     
       15. The method of  claim 14 , further comprising coupling the second memory die to the redistribution layer using reflow of a capillary underfill material. 
     
     
       16. The method of  claim 14 , further comprising coupling the second memory die to the redistribution layer using thermal compression bonding with a non-conductive paste. 
     
     
       17. The method of  claim 14 , further comprising coupling the redistribution layer to the encapsulant. 
     
     
       18. The method of  claim 14 , wherein the redistribution layer is positioned between the first memory die and the second memory die. 
     
     
       19. The method of  claim 14 , wherein the first die and the second die are substantially identical in function. 
     
     
       20. The method of  claim 14 , further comprising coupling the first routing in the redistribution layer to a first set of connections on the first memory die, and coupling the second routing in the redistribution layer to a second set of connections on the second memory die, wherein the first set of connections are offset from the second set of connections.

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a top package of a PoP (package-on-package) for memory die. 
     2. Description of Related Art 
     Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages. Such pre-stacking has become a critical component for thin and fine pitch PoP packages. 
     One limitation in reducing the size of a package (e.g., either the top package (the memory package) or the bottom package (the SoC package) in the PoP package) is the size of the substrate used in the package. Thin substrates and/or coreless substrates (e.g., laminate substrates) have been used to reduce the size of the packages to certain levels. Further reductions in size, however, may be needed in order to provide even smaller packages for next generation devices. 
     One or more memory die are typically placed in the top package of a PoP package. Using a single memory die (e.g., a single 8 GB (gigabyte) DDR (double date rate) memory die) in the top package is achieved relatively easy (e.g., connections to terminals on the package are reliable and simple to make and the top package has a relatively thin profile). The single memory die, however, may not provide sufficient capability for newer and more powerful devices. Thus, devices requiring larger memory capability typically need two or more die in the top package (e.g., two or more 8 GB DDR memory die). 
     A typical configuration for putting two memory die in a top package is to vertically stack the memory die (e.g., stack one memory die directly on top of another memory die). Vertically stacking the memory die reduces the overall thickness of the top package. Stacking the die vertically, however, creates problems with connecting both die to terminals on the package. Typically, the die are connected to the terminals using wire bonding between the top of the memory die (with at least part of the bottom memory die in the stack protruding beyond the edge of the top memory die) and terminals on the substrate of the top package. Using wire bonding, however, increases the height of the top package as the wire bond paths are spaced to prevent shorting of the different wire bonds from each memory die. In addition, wire bonding may provide a high impedance path that reduces signal integrity and/or power integrity between the memory die and the terminals. A possible solution to overcome the problems with wire bonding is to provide through silicon vias (TSVs) from the memory die to the terminals in the top package. Providing TSVs, however, requires special memory die, adds several additional process steps, and is relatively expensive. 
     SUMMARY 
     In certain embodiments, a top package of a PoP package includes two memory die. A first memory die may be at least partially encapsulated in an encapsulant. A bottom surface of the first memory die may be coupled to a redistribution layer (RDL). A second memory die may be coupled to the bottom surface of the RDL. In some embodiments, the second memory die is coupled to the RDL using reflow of a capillary underfill material. In some embodiments, the second memory die is coupled to the RDL using thermal compression bonding with a non-conductive paste. 
     The RDL may include routing between the first memory die and one or more first terminals coupled to the RDL on a periphery of the die. The RDL may also include electrically separate routing between the second memory die and one or more second terminals coupled to the RDL on a periphery of the die. The routing between the first memory die and the first terminals may be electrically isolated from the routing between the second memory die and the second terminals. The RDL reduces the overall thickness of the top package and improves signal and power integrity in the top package. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features and advantages of the methods and apparatus of the present invention will be more fully appreciated by reference to the following detailed description of presently preferred but nonetheless illustrative embodiments in accordance with the present invention when taken in conjunction with the accompanying drawings in which: 
         FIG. 1  depicts a cross-sectional representation of an encapsulated memory die with a redistribution layer coupled to the memory die. 
         FIG. 2  depicts a cross-sectional representation of an embodiment of the encapsulated memory die of  FIG. 1  being coupled to a second memory die. 
         FIG. 3  depicts a cross-sectional representation of an embodiment of a top package with two offset memory die coupled with a redistribution layer. 
         FIG. 4  depicts a bottom view representation of the embodiment depicted in  FIG. 3 . 
         FIG. 5  depicts a cross-sectional representation of another embodiment of a top package with two memory die coupled with a redistribution layer. 
     
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. The drawings may not be to scale. It should be understood that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but to the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
       FIGS. 1-3  depict cross-sectional representations of steps of an embodiment of a process flow for forming a top package used in a PoP (“package-on-package”) package.  FIG. 1  depicts a cross-sectional representation of an encapsulated memory die with a redistribution layer coupled to the memory die used in forming top package  100 . Memory die  102 A is at least partially encapsulated in encapsulant  104 . In certain embodiments, a bottom surface of die  102 A is exposed (uncovered) by encapsulant  104 . Die  102 A may be, for example, a semiconductor chip such as a wire-bond die or a flip chip die. In certain embodiments, die  102 A is a DDR (double data rate) die (e.g., an 8 GB DDR die). Encapsulant  104  may be, for example, a polymer or a mold compound such as an overmold or exposed mold. 
     In certain embodiments, redistribution layer (RDL)  106  is coupled to die  102 A. RDL  106  may be coupled to a bottom surface of die  102 A. RDL  106  may also be coupled to encapsulant  104 . RDL  106  may include materials such as, but not limited to, PI (polyimide), PBO (polybenzoxazole), BCB (benzocyclobutene), and WPRs (wafer photo resists such as novolak resins and poly(hydroxystyrene) (PHS) available commercially under the trade name WPR including WPR-1020, WPR-1050, and WPR-1201 (WPR is a registered trademark of JSR Corporation, Tokyo, Japan)). RDL  106  may be formed on die  102 A and encapsulant  104  using techniques known in the art (e.g., techniques used for polymer deposition). 
     In certain embodiments, die  102 A and RDL  106  are coupled using one or more connections  108 A. Connections  108 A may include landing pads or other terminals that couple die  102 A to routing  110 A in RDL  106 . For example, connections  108 A may include aluminum or copper landing pads or solder-coated or Sn-coated landing pads for coupling to routing  110 A to die  102 A. 
     After formation of RDL  106 , terminals  112 A,  112 B may be coupled to the RDL, as shown in  FIG. 1 . Terminals  112 A,  112 B may be located on a periphery of die  102 A. Terminals  112 A,  112 B may be used to couple top package  100  to a bottom package (e.g., a SoC package) to form a PoP package. Terminals  112 A,  112 B may include aluminum, copper, or another suitable conductive material. In some embodiments, terminals  112 A,  112 B are solder-coated or Sn-coated. In certain embodiments, terminals  112 A are coupled to die  102 A through routing  110 A and connections  108 A. 
       FIG. 2  depicts a cross-sectional representation of an embodiment of die  102 B being coupled to die  102 A and RDL  106 . Die  102 B may be, for example, a flip-chip semiconductor chip. In certain embodiments, die  102 B is a DDR (double data rate) die (e.g., an 8 GB DDR die). In some embodiments, die  102 B is identical to die  102 A. Die  102 B may be flipped so that terminals  114  (typically located on the bottom of the die) can be coupled to connections  108 B on RDL  106 . Terminals  114  may be copper or aluminum terminals. In some embodiments, terminals  114  are solder-coated or Sn-coated. 
     After terminals  114  are contacted to connections  108 B, die  102 B may be coupled to RDL  106  and die  102 A with material  116 , as shown in  FIG. 3 . Die  102 B may be coupled to a bottom surface of RDL  106  (e.g., a surface of the RDL opposite the surface coupled to die  102 A). Material  116  may be an electrically insulating material. In certain embodiments, material  116  is pre-applied to the surface of RDL  106  or die  102 B before contacting the RDL and the die. Material  116  may be, for example, a polymer or epoxy material such as an underfill material or a non-conductive paste. For example, material  116  may be a capillary underfill material used in flip-chip bonding processes such as a snap cure underfill material or a low profile underfill material. Typically, material  116  is an electrically insulating material that cures at or lower than the melting temperatures of the materials used in terminals  114  and connections  108 B (e.g., the solder melting temperature). 
     In some embodiments, if terminals  114  are copper, material  116  is a non-conductive paste and terminals  114  are coupled (bonded) to connections  108 B using a thermal compressing bonding process (e.g., a flip-chip thermal compression bonding process). An example of a flip-chip thermal compression bonding apparatus that may be used is an FC3000 Flip Chip Bonder available from Toray Engineering Co., Ltd. (Tokyo, Japan). In some embodiments, material  116  is a capillary underfill material and terminals  114  are coupled (bonded) to connections  108 B using a mass reflow process (e.g., using a solder reflow oven). 
     In some embodiments, terminals  112 A,  112 B are coupled to RDL  106  after coupling terminals  114  and connections  108 B. The same process used to couple terminals  114  and connections  108 B may be used to couple terminals  112 A,  112 B to RDL  106 . For example, terminals  112 A,  112 B may be coupled using the same mass reflow process used to couple terminals  114  and connections  108 B. 
     Coupling terminals  114  on die  102 B to connections  108 B in RDL  106  couples die  102 B to routing  110 B in the RDL. Routing  110 B may provide connection to terminals  112 B for die  102 B while routing  110 A provides connections between terminals  112 A and die  102 A. Routing  110 A and routing  110 B may be, for example, metal lines in RDL  106 . In certain embodiments, routing  110 B is electrically isolated from routing  110 A in RDL  106 . Electrically isolating routing  110 A and routing  110 B allows die  102 A and die  102 B to be individually connected to a bottom package through terminals  112 A and terminals  112 B, respectively. 
     Routing  110 A and routing  110 B, shown in  FIGS. 1-3 , are only shown for one terminal  112 A coupled to die  102 A and one terminal  112 B coupled to die  102 B for simplicity in the drawings. It is to be understood that additional routing exists for each of the terminals coupled to each memory die and that the routing may be in any configuration contemplated by one skilled in the art. 
     As shown in  FIG. 3 , die  102 B is offset from die  102 A. Offsetting die  102 A and die  102 B offsets connections  108 A from connections  108 B (e.g., creating a staggered bump pattern between the die). Offsetting connections  108 A and connections  108 B allows a single layer of routing (e.g., a single layer of metal lines that define routing  110 A and routing  110 B) in RDL  106  (e.g., RDL  106  is a single layer RDL). Single layer RDL  106  is possible because connections  108 A and  108 B do not overlap, which allows routing  110 A and routing  110 B to be in the same layer without any electrical connection between the individual routings for die  102 A and die  102 B. 
       FIG. 4  depicts a bottom view representation of the embodiment of top package  100  depicted in  FIG. 3 . Routing  110 A couples connections  108 A to terminals  112 A and routing  110 B couples connections  108 B to terminals  112 B. As shown in  FIG. 4 , the offset between die  102 A and die  102 B offsets connections  108 A from connections  108 B. Because connections  108 A and connections  108 B are offset (not overlapped), routing  110 A and routing  110 B may both be in the same layer in RDL  106  without the separate routings electrically connecting (shorting). 
     In some embodiments, die  102 A and die  102 B are not offset and connections  108 A and connections  108 B are aligned (e.g., the connections overlap).  FIG. 5  depicts a cross-sectional representation of an embodiment of top package  100 ′ with die  102 A and die  102 B coupled with no offset between the die. Because connections  108 A and  108 B overlap in top package  100 ′, RDL  106 ′ may include two or more layers of routing (e.g., RDL  106 ′ is a 2 L (two layer) RDL). The multiple layers of routing (e.g., routing  110 A is in one layer and routing  110 B is in another layer) may be used to inhibit electrical contact between the individual routings (e.g., electrically isolate routing  110 A from routing  110 B) and allow die  102 A and die  102 B to be individually connected to a bottom package through terminals  112 A and terminals  112 B, respectively. 
     As shown in  FIGS. 3 and 5 , the presence of RDL  106  (or RDL  106 ′) in top package  100  allows for bonding and electrical coupling of die  102 A,  102 B to a bottom package through terminals  112 A,  112 B. Terminals  112 A,  112 B may be located on the periphery of die  102 A,  102 B. Using RDL  106  to couple die  102 A,  102 B to terminals  112 A,  112 B on the periphery of the die reduces an overall thickness of top package  100  by eliminating the use of wire bonding or other connection techniques that add height to the top package. 
     In addition, RDL  106  may be a relatively thin layer compared to substrates typically used for memory packages (e.g., top packages in PoP packages). For example, a single layer RDL may have a thickness of less than about 10 μm (e.g., about 5 μm) while typical organic substrates have thicknesses of about 200 μm or more. Thus, using RDL  106  in top package  100  reduces the overall thickness of the top package and a PoP package containing the top package, especially for the single layer RDL. For example, top package  100  may have a thickness between about 200 μm and 300 μm with a substantial majority of the thickness of the top package being due to the combined thickness of die  102 A and die  102 B. Reducing the thickness of top package  100  may allow increases in circuit density or package density and improve performance of a device using the top package. 
     Using routing  110 A,  110 B in RDL  106  may also decrease the impedance between die  102 A,  102 B and terminals  112 A,  112 B compared to connections made using wire-bonding techniques. The impedance may be decreased through the use of high conductivity metal lines in RDL  106  and/or reduced path lengths between the connections on the die and the terminals (e.g., shorter interconnects between the die and the terminals). Wire-bonding typically includes looped or rounded paths to allow for connections to upper surfaces of the dies and the substrate. Thus, the path length may be shorter using routing in the RDL because more direct connections between the die and the terminals are provided (e.g., no rounded or looped paths are needed). Additionally, couplings between die  102 A,  102 B, connections  108 A,  108 B, routing  110 A,  110 B, and/or terminals  112 A,  112 B may be more robust than wire-bonding connections. 
     Reducing the impedance between die  102 A,  102 B and terminals  112 A,  112 B may provide better signal and power integrity in top package  100  (or top package  100 ′) compared to top packages made using wire-bonding between the die and the terminals. Providing better signal and power integrity may improve device performance. In addition, utilization of RDL  106  in top package  100  may reduce yield losses (compared to top packages using wire-bonding) and potentially reduce manufacturing costs with the improved yield. 
     Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.

Metadata:
Filing Date: 20130129
Publication Date: 20171219
Grant Date: 20171219
Priority Date: 20130129
Inventors: ZHAI JUN
Assignee: APPLE INC
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Family ID: 50071752