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US-12219387-B2
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US-202017439661-A
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US
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B2
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Adaptation layer enhancement in relay networks
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Disclosed are methods, systems, apparatus, and computer programs for adaptation layer enhancements in new radio (NR) integrated access and backhaul (IAB) networks. In one aspect, a method includes performing, by an adaptation layer of an IAB node of the IAB network, header compression on one or more headers of a packet for transmission in the IAB network; and transmitting the packet with the one or more compressed headers to a destination IAB node of the IAB network.
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What is claimed is:
1. In an integrated access and backhaul (IAB) network comprising an IAB node, a method comprising:
performing, by an adaptation layer of the IAB node, an end-to-end header compression on one or more headers of a packet for transmission over an end-to-end backhaul link in the IAB network between the IAB node and a destination IAB access node, wherein performing header compression on the one or more headers comprises:
determining a load status of the IAB network with respect to a number of contexts required by UE bearers served by the IAB network; and
determining, based on the load status, a context identifier of an ROHC channel,
wherein a number of bits of the context identifier is one of 8 bits, 16 bits, or 24 bits; and
transmitting the packet with the one or more compressed headers over the end-to-end backhaul link to the destination IAB access node.
2. The method of claim 1 , wherein the packet is transmitted via a user equipment (UE) bearer, and wherein the IAB network implements UE bearer to backhaul channel mapping and routing.
3. The method of claim 1 , wherein the one or more headers are at least one of a General Packet Radio Service (GPRS) Tunneling Protocol (GTP) header, a User Datagram Protocol (UDP) header, or an Internet Protocol (IP) header.
4. The method of claim 1 , wherein performing header compression on the one or more headers comprises compressing a message type field in the one or more headers.
5. The method of claim 1 , wherein the header compression is based on a Robust Header Compression (ROHC) framework, and wherein the header compression is performed using an ROHC compression profile.
6. The method of claim 1 , wherein the ROHC channel corresponds to the end-to-end backhaul link between the IAB node and the destination IAB access node, and wherein the method further comprises:
determining, based on the context identifier, a routing path ID of the end-to-end backhaul link, wherein the routing path ID identifies each hop in the end-to-end backhaul link between the IAB node and the destination IAB access node.
7. The method of claim 1 , wherein the IAB node is an IAB-Donor, and wherein the packet is transmitted over the end-to-end backhaul link between the IAB-Donor and the destination IAB access node.
8. The method of claim 7 , wherein the IAB network further comprises an intermediate IAB node between the IAB-Donor and the destination IAB access node, and wherein the method further comprises:
routing the packet through adaptation layers of the intermediate IAB node and the IAB-Donor node, wherein the packet is routed through the adaptation layers without going through an upper Internet Protocol (IP) layer.
9. The method of claim 7 , wherein the one or more headers are at least one of a User Datagram Protocol (UDP) header or an Internet Protocol (IP) header, and wherein the header compression of the UDP header or the IP header is UDP/IP header compression that uses a Robust Header Compression (ROHC) framework.
10. The method of claim 9 , wherein the one or more headers further comprises a General Packet Radio Service (GPRS) Tunneling Protocol (GTP) header, and wherein the UDP/IP header compression is aggregated with GTP header compression.
11. The method of claim 10 , further comprising:
categorizing GTP header fields based on the ROHC framework by assigning each GTP header field to one of the following categories: INFERRED, STATIC, STATIC-DEF, STATIC-KNOWN, and CHANGING.
12. In an integrated access and backhaul (IAB) network comprising an IAB node, one or more processors configured to perform operations comprising:
performing, by an adaptation layer of the IAB node, header compression on one or more headers of a packet for transmission in the IAB network;
determining a respective compression efficiency for a respective backhaul link in each hop between the IAB node and a destination IAB node; and
transmitting the packet with the one or more compressed headers to the destination IAB node, wherein the header compression is configured independently over the respective backhaul link in each hop between the IAB node and the destination IAB node.
13. The one or more processors of claim 12 , wherein the one or more headers are at least one of a General Packet Radio Service (GPRS) Tunneling Protocol (GTP) header, a User Datagram Protocol (UDP) header, or an Internet Protocol (IP) header.
14. The one or more processors of claim 12 , wherein performing header compression on the one or more headers comprises compressing a message type field in the one or more headers.
15. The one or more processors of claim 12 , wherein the header compression is based on a Robust Header Compression (ROHC) framework, and wherein the header compression is performed using an ROHC compression profile.
16. An integrated access and backhaul (IAB) system comprising:
an IAB node; and
one or more processors and one or more storage devices storing instructions that are operable, when executed by the one or more processors, to cause the one or more processors to perform operations comprising:
performing, by an adaptation layer of the IAB node, header compression on one or more headers of a packet for transmission in the IAB system;
determining a respective compression efficiency for a respective backhaul link in each hop between the IAB node and a destination IAB node; and
transmitting the packet with the one or more compressed headers to the destination IAB node, wherein the header compression is configured independently over the respective backhaul link in each hop between the IAB node and the destination IAB node.
17. The IAB system of claim 16 , the operations further comprising:
determining, based at least on the respective compression efficiency of a first backhaul link, whether to perform header compression over the first backhaul link.
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CLAIM OF PRIORITY
This application is a U.S. National Phase Application under 35 U.S.C. § 371 and claims the benefit of priority to International Application No. PCT/US2020/032152, filed on May 8, 2020, which claims priority to U.S. Provisional Patent Application No. 62/844,974 filed May 8, 2019, entitled “METHODS FOR ADAPTATION LAYER ENHANCEMENT IN RELAY NETWORK,” the entirety of which is incorporated herein by reference.
BACKGROUND
User equipment (UE) can wirelessly communicate data using wireless communication networks. To wirelessly communicate data, the UE connects to a node of a radio access network (RAN) and synchronizes with the network.
SUMMARY
The present disclosure is directed towards methods, systems, apparatus, computer programs, or combinations thereof, for adaptation layer enhancements in new radio (NR) integrated access and backhaul (IAB) networks.
In accordance with one aspect of the present disclosure, a method includes performing, by an adaptation layer of an IAB node of the IAB network, header compression on one or more headers of a packet for transmission in the IAB network; and transmitting the packet with the one or more compressed headers to a destination IAB node of the IAB network.
Other versions include corresponding systems, apparatus, and computer programs to perform the actions of methods defined by instructions encoded on computer readable storage devices. These and other versions may optionally include one or more of the following features.
In some implementations, the packet is transmitted via a user equipment (UE) bearer, and the IAB network implements UE bearer to backhaul channel mapping and routing.
In some implementations, the one or more headers are at least one of a General Packet Radio Service ((GPRS) Tunneling Protocol (GTP) header, a User Datagram Protocol (UDP) header, or an Internet Protocol (IP) header.
In some implementations, performing header compression on the one or more headers includes compressing a message type field in the one or more headers.
In some implementations, the header compression is based on a Robust Header Compression (ROHC) framework, and the header compression is performed using an ROHC compression profile.
In some implementations, performing header compression on the one or more headers includes: determining a load status of the IAB network with respect to a number of contexts required by UE bearers served by the IAB network; and determining, based on the load status, a context identifier of an ROHC channel, wherein a number of bits of the context identifier is one of 8 bits, 16 bits, or 24 bits.
In some implementations, an ROHC channel corresponds to an end-to-end backhaul link between the IAB node and the destination IAB node, and the process further includes: determining, based on the context identifier, a routing path ID of the end-to-end backhaul link, wherein the routing path ID identifies each hop in the end-to-end backhaul link between the IAB node and the destination IAB node.
In some implementations, the packet is transmitted over an end-to-end backhaul link between an IAB-Donor and an IAB access node, the IAB node is one of the IAB-Donor and the IAB access node, and the destination IAB node is the other one of the IAB-Donor and the IAB access node.
In some implementations, the IAB network further includes an intermediate node between the IAB-Donor and the IAB access node, and the process further includes: routing the packet through adaptation layers of the intermediate IAB node and the IAB-Donor node, where the packet is routed through the adaptation layers without going through the upper Internet Protocol (IP) layer.
In some implementations, the one or more headers are at least one of a User Datagram Protocol (UDP) header or an Internet Protocol (IP) header, and the header compression of the UDP header or the IP header is UDP/IP header compression that uses a Robust Header Compression (ROHC) framework.
In some implementations, the one or more headers further include a General Packet Radio Service (GPRS) Tunneling Protocol (GTP) header, and the UDP/IP header compression is aggregated with GTP header compression.
In some implementations, the process further includes: categorizing GTP header fields based on the ROHC framework by assigning each GTP header field to one of the following categories: INFERRED, STATIC, STATIC-DEF, STAT-KNOWN, and CHANGING.
In some implementations, the header compression is configured independently over a respective backhaul link in each hop between the IAB node and the destination IAB node.
In some implementations, the process further includes determining respective compression efficiencies for the backhaul links between the IAB node and the destination IAB node.
In some implementations, the process further includes determining, based the respective compression efficiency of a first backhaul link, whether to perform header compression over the first backhaul link.
DESCRIPTION OF DRAWINGS
FIG. 1 illustrates an example integrated access and backhaul (IAB) network, according to some implementations of the present disclosure.
FIG. 2 illustrates an example of UDP/IP header compression over an end-to-end (E2E) backhaul link, according to some implementations of the present disclosure.
FIG. 3 illustrates an example 300 of header compression per backhaul link between adjacent IAB nodes, according to some implementations of the present disclosure.
FIG. 4 illustrates a flowchart of an example method, according to some implementations of the present disclosure.
FIG. 5 illustrates an example architecture of a system of a network, according to some implementations of the present disclosure.
FIG. 6 illustrates an example architecture of a system including a CN, according to some implementations of the present disclosure.
FIG. 7 illustrates a block diagram of an example of infrastructure equipment, according to some implementations of the present disclosure.
FIG. 8 illustrates a block diagram of various protocol functions that may be implemented in a wireless communication device, according to some implementations of the present disclosure.
FIG. 9 illustrates a block diagram illustrating components able to read instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and perform any one or more of the methodologies described herein, according to some implementations of the present disclosure.
Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
The present disclosure is related to Integrated Access and Backhaul (IAB) networks, which is a feature that enables multi-hop routing (e.g. as described in 3GPP Release 16 (Rel-16)). An architecture of IAB networks generally includes an IAB-Donor node (or “IAB-Donor”) that serves a plurality of IAB nodes that operate as relays. The IAB-Donor is a network node (e.g., a base station) that terminates new generation (NG) interfaces In particular, the IAB-Donor may serve as an interface for a user equipment (UE) to a core network and/or may provide wireless backhauling functionality to the plurality of IAB nodes. The plurality of IAB nodes can serve as access nodes to UEs and can provide backhaul links to other IAB nodes.
IAB support in new radio (NR) may include enhancements to wireless transport by introducing a layer called an “adaptation layer,” which is located above the radio link control (RLC) layer. One of the functionalities of the adaptation layer is to forward the traffic across wireless backhaul (BH) links of an IAB network. For this purpose, the adaptation layer may include an identifier depending on the data forwarding that will be executed. This identifier could, for example, be a path identifier (ID) that is indicative of an entire backhaul path between an IAB-Donor and an IAB access node. As such, this identifier may be used within the IAB network (e.g. under one donor central unit (CU)) and the same identifier may be reused in another IAB network.
According to the existing protocol stack architecture of IAB networks, IAB networks may transmit General Packet Radio Services (GPRS) Tunneling Protocol/User Datagram Protocol/Internet Protocol (GTP/UDP/IP) based encapsulated IP packets. In this architecture, the adaptation layer of the IAB nodes is responsible for routing and data forwarding. However, the existing architecture does not account for limited radio resources. Due to their limited nature, it is important to efficiently utilize backhaul radio resources.
This disclosure describes an enhancement for backhaul packet transmission that enables efficient utilization of backhaul radio resources. Specifically, this disclosure describes methods and systems that employ header compression for backhaul packets in order to further enhance the spectrum efficiency of BH communications. The header compression functions may be applied in the adaptation layer of one or more IAB nodes of the IAB network. This enhancement is particularly useful when the IAB network is delivering a large amount of small backhaul packets.
In a first method, header compression is applied over an end-to-end backhaul link between an IAB-Donor and an IAB access node. In this method, the IAB access node and the IAB-Donor have access to different layers of GTP/UDP/IP based backhaul packets. As such, backhaul layer headers (e.g., GTP, UDP, and IP) can be compressed so as to enhance the backhaul spectrum efficiency. In a first implementation of the method, a Robust Header Compression (ROHC) framework is used to compress UDP and IP headers based on ROHC UDP/IP compression profiles (e.g., defined in RFC 3095, RFC 4815 and RFC 5225). In a second implementation of the method, an ROHC profile used for UDP/IP header compression is further aggregated by GTP header compression.
In a second method, header compression as applied per backhaul link between adjacent IAB nodes in the IAB network. In this method, header compression is configured independently over the backhaul channel (also called a “backhaul link) in each hop of the IAB network. However, because intermediate IAB nodes and the IAB-Donor distributed unit (DU) only have access to the IP layer of the backhaul traffic flows, only IP header compression is performed. In particular, the adaptation layer of each IAB node can perform IP header compression, perhaps based on RFC 3843, RFC 4815 and RFC 5225. In some examples, whether header compression is performed for a particular backhaul link (e.g., between adjacent IAB nodes) may depend on the achievable compression efficiency for that backhaul channel.
Both of these methods enable header compression functionalities in the adaptation layer of IAB nodes so that the backhaul spectrum efficiency can be improved, particularly for small backhaul packet transmission in the IAB network. Note that, in some implementations, a data transmission is considered a small packet if the data does not exceed a predetermined threshold, e.g., transmissions that are less than N bytes, where N is a predetermined value, e.g., 100, 128, 256, 512, and 1024. Other values for N are possible. Also note that although this disclosure generally describes header compression, the disclosed methods and systems can also be configured for header decompression.
FIG. 1 illustrates an example IAB network 100 , according to some implementations. As shown in FIG. 1 , the IAB network 100 includes IAB-Donor 102 and four children nodes. The four children nodes three intermediate IAB nodes 104 (“IAB-#1”) 106 (“IAB-#2”), and 109 (“IAB-#3”). Additionally, the children nodes also include an IAB access node 110 that serves a user equipment (UE) 112 . In this example, IAB-#1 is a parent of IAB-#2 and IAB-#3. Conversely, IAB-#2 and IAB-#3 are both children of IAB-#1. IAB-#2 and IAB-#3 are both parents of IAB access node 112 . IAB access node 112 is a child of IAB-#2 and IAB-#3. Further, the IAB network 100 may have a network architecture that includes a central unit-distributed unit (CU-DU) split In this architecture, the IAB-Donor 102 includes a central unit and a distributed unit (not illustrated in FIG. 1 ). Furthermore, each IAB node holds a DU and a Mobile Termination (MT) function. Generally, an IAB node may use the MT function to connect to its parent IAB node or the IAB-Donor 102 . And an IAB node may use the DU function to communicate with UEs and MTs of child IAB nodes. In an example, to the IAB network 100 may implement UE barer (based on tunnel-endpoint ID (TEID)) to backhaul channel mapping and routing.
In an embodiment, in addition to UE bearer to backhaul channel mapping and routing, an adaptation layer in the IAB nodes can be enhanced to include a header compression (HC) function in order to improve the spectrum efficiency of backhaul link communication in the IAB network. In particular, header compression can be performed between different peer-entities in the IAB network. Disclosed are two methods of header compression that can be implemented in the IAB network.
Method 1: Header Compression Ever End-to-End Backhaul Link Between IAB-Donor CU and IAB-Access Mode
In a first method, header compression is applied over an end-to-end backhaul (E2E) link between IAB-Donor CU and IAB access node. The IAB access node and the IAB-Donor have access to different layers of GTP/UDP/IP based backhaul UE packets. As such, in this method, the backhaul layer headers (e.g., GTP, UDP, and IP) are compressed so as to enhance backhaul spectrum efficiency. This is particular useful when the IAB network delivers low latency critical data with medium to small payload size.
In an implementation of the first method, a Robust Header Compression (ROHC) framework is used by an adaptation layer (of the IAB access node or the IAB-Donor) to compress UDP and/or IP headers by virtue of ROHC UDP/IP compression profiles, such as the ROHC profiles defined in RFC 3095, RFC 4815 or RFC 5225.
FIG. 2 illustrates an example of UDP/IP header compression over an end-to-end (E2E) backhaul link, according to some implementations In this example, an IAB network 200 includes an IAB-Donor 202 , an intermediate IAB node 204 (IAB-#1), and an IAB access node 206 . As illustrated in FIG. 2 , the access IAB node 206 serves a UE 208 . In an embodiment, header compression/decompression can be performed in IAB-Donor CU-User Plane (CU-UP) 210 and IAB access node MT 212 for downlink (DL) and/or uplink (UL) packets. More specifically, adaptation layers 214 , 216 of the IAB-Donor CU-UP 210 and the IAB access node MT 212 , respectively, may be configured with a header compression function for UDP/IP header compression/decompression.
Furthermore, for UE bearers with header compression over the E2E backhaul channel, the compressed packets are exchanged between the respective adaptation layers of the respective DU-MT pair of intermediate IAB nodes and the DU-CU pair of the IAB-Donor, without going through the upper IP layer. For example, as shown in FIG. 2 , a compressed packet may be transmitted through the adaptation layers of the DU-MT pair 218 of the IAB-#1 and to the adaptation layers of the DU-CU pair of the IAB-Donor 202 , without going through the upper IP layer.
Further, a context identifier associated with each ROHC channel corresponding to a directional E2E backhaul channel between an IAB-Donor CU-UP and an IAB access MT can be used as a routing path ID uniquely allocated within the IAB network under the IAB-Donor CU-UP. It particular the context ID (i.e., the routing path ID) of each UE bearer can be allocated by the IAB-Donor CU and be used as an identifier of that UE bearer. For example, a context identifier associated with an ROHC channel corresponding to the E2E backhaul channel between the IAB-Donor CU-UP 210 and the IAB access node MT 212 can be used as a routing path ID uniquely allocated within the IAB network.
In another implementation of the first method, the ROHC profile used for UDP/IP header compression can be further aggregated with GTP header compression. In this implementation, based on the ROHC framework, the following classes can be used to categorize GTP header fields: INFERRED; STATIC; STATIC-DEF; STATIC-KNOWN; CHANGING INFERRED fields contain values that can be inferred from other values, and thus, do not need to be transmitted. As an example, the size of the frame carrying the packet can be categorized as an INFERRED field. STATIC fields are expected to be constant throughout the lifetime of the packet flow. Static information is communicated once, for example, by an initialisation and refresh (IR) packet. STATIC-DEF fields are STATIC fields whose values define a packet flow. They are generally handled as STATIC. STATIC-KNOWN are STATIC fields that are expected to have known values, and therefore, do not need to be communicated. CHANGING fields are expected to vary in some way (e.g., randomly, within a limited value set or range, or in some other manner).
Table 1 shows the classification of GTP header fields using the described ROHC classification.
Table 1 shows the classification of GTP header fields using the described ROHC classification
Header Field
Classification
Version (3 bits)
STATIC-DEF
Protocol Type (1 bit)
STATIC-DEF
Reserved (1 bit)
STATIC-DEF
Extension Header Flag (1 bit)
CHANGING
Sequence Number Flag (1 bit)
CHANGING
N-PDU Number Flag (1 bit)
STATIC-KNOWN (set to 0)
Message Type (8 bits)
CHANGING
Tunnel Endpoint Identifier (32 bits)
STATIC-DEF
Sequence Number (Optional, 16 bits)
CHANGING if present.
N-PDU Number (Optional, 8 bits)
INFERRED
Next Extension Header Type (Optional, 8 bits)
CHANGING if present.
In an embodiment, the number of bits of a context identifier (CID) can be determined based a load of the IAB network, perhaps in terms of the number of contexts required by all UE bearers served by the IAB-Donor. For example, the content ID can be selected from 8 bits, 16 bits and 24 bits depending on the load status of the IAB network. More specifically, an 8 bit context ID can be selected for a low-load IAB network, a 16 bit context ID can be selected for a medium-load IAB network, and a 24 bit context ID can be selected for a large-load IAB network. The thresholds for each type of load may be predetermined In the case of a low-load IAB network, the compression efficiency by virtue of having a CID of 8 bits (and therefore header size is reduced from 64 bits to 34 bits) may reach nearly 50%. Moreover, a message type field (e.g., of 8 bits) can be further compressed if a new message type definition is used for NR IAB network, which then allows removal of messages used for other radio access network (RAN) systems.
Method 2: Header Compression Per BH Link Between Adjacent IAB Nodes
In a second method, header compression can be configured independently over the respective backhaul channels of each hop in the IAB network.
FIG. 3 illustrates an example 300 of header compression per backhaul link between adjacent IAB nodes, according to some implementations. In this example, an IAB network 300 includes an IAB-Donor 302 , an intermediate IAB node 304 (IAB-#1), and an IAB access node 306 . As illustrated in FIG. 3 , the access IAB node 306 serves a UE 308 . In an embodiment, the header compression functionality can be configured for the adaption layers of the IAB nodes of the IAB network 300 . As shown in FIG. 3 , the adaptation layers of the IAB-Donor 302 , the intermediate IAB node 304 , and the IAB access node 306 may be configured with a header compression functionality. Because intermediate IAB nodes and IAB-Donor DU only have access to the IP layer of traffic flows, the header compression functionality can only perform IP header compression, e.g., based on RFC 3843, RFC 4815 and RFC 5225. Within examples, the IAB network 300 may execute the second method in order to implement header compression over one or more backhaul channels between IAB nodes of the IAB network 300 .
In an embodiment, whether header compression is performed for a particular backhaul hop depends on the achievable compression efficiency for that hop. As such, within an IAB network, header compression can be performed for some backhaul hops and not others. In an example, the achievable compression efficiency for a backhaul channel (e.g., for a hop of the IAB network) may be determined based on a configured context identifier associated with the adaptation layer entity of a particular IAB node. For instance, the configured context identifier for the adaptation layer entity of a particular IAB node can correspond to the local path ID used by the IAB node. As such, for IAB nodes serving a small number of child nodes, the length of CID can be small and lead to a better compression efficiency. On the other hand, for an IAB node serving large number of child nodes (e.g., IAB-Donor), the size of required CID if HC is configured can be large, and thus, an acceptable compression efficiency is less likely. In this case, whether to use header compression can depend on the achievable compression efficiency.
For one or more embodiments, at least one of the components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the example section below. As an example, the baseband circuitry as described above in connection with one or more of the preceding figures may be configured to operate in accordance with one or more of the examples set forth below. As another example, circuitry associated with a UE, base station, network element, etc. as described above in connection with one or more of the preceding figures may be configured to operate in accordance with one or more of the examples set forth below in the example section.
FIG. 4 illustrates a flowchart of an example process 400 , according to some implementations. For clarity of presentation, the description that follows generally describes the processes in the context of the other figures in this description. For example, process 400 can be performed by an IAB node or entity thereof (e.g., an IAB node of FIG. 1 , 2 , or 3 ). However, it will be understood that the processes may be performed, for example, by any suitable system, environment, software, and hardware, or a combination of systems, environments, software, and hardware, as appropriate. In some implementations, various steps of the processes can be run in parallel, in combination, in loops, or in any order.
FIG. 4 is a flowchart of an example process 400 for header compression in an IAB network. At step 402 , the process involves performing, by an adaptation layer of an IAB node, header compression on one or more headers of a packet for transmission in the IAB network. At step 404 , the process involves transmitting the packet with the compressed one or more headers to a destination IAB node. Note that the example process 400 and the description herein can be adapted for header decompression. For example, upon receipt of the compressed packet, the destination IAB may perform header decompression on the one or more headers of the compressed packet.
In some implementations, the packet is transmitted via a user equipment (UE) bearer, and the IAB network implements UE bearer to backhaul channel mapping and routing.
In some implementations, the one or more headers are at least one of a General Packet Radio Service (GPRS) Tunneling Protocol (GTP) header, a User Datagram Protocol (UDP) header, or an Internet Protocol (IP) header.
In some implementations, performing header compression on the one or more headers includes compressing a message type field in the one or more headers.
In some implementations, the header compression is based on a Robust Header Compression (ROHC) framework, and the header compression is performed using an ROHC compression profile.
In some implementations, performing header compression on the one or more headers includes: determining a load status of the IAB network with respect to a number of contexts required by UE bearers served by the IAB network; and determining, based on the load status, a context identifier of an ROHC channel, wherein a number of bits of the context identifier is one of 8 bits, 16 bits, or 24 bits.
In some implementations, an ROHC channel corresponds to an end-to-end backhaul link between the IAB node and the destination IAB node, and the process further includes: determining, based on the context identifier, a routing path ID of the end-to-end backhaul link, wherein the rowing path ID identifies each hop in the end-to-end backhaul link between the IAB node and the destination IAB node.
In some implementations, the packet is transmitted over an end-to-end backhaul link between an IAB-Donor and an IAB access node, the IAB node is one of the IAB-Donor and the IAB access node, and the destination IAB node is the other one of the IAB-Donor and the IAB access node.
In some implementations, the IAB network further includes an intermediate node between the IAB-Donor and the IAB access node, and the process further includes: routing the packet through adaptation layers of the intermediate IAB node and the IAB-Donor node, where the packet is routed through the adaptation layers without going through the upper Internet Protocol (IP) layer.
In some implementations, the one or more headers are at least one of a User Datagram Protocol (UDP) header or an Internet Protocol (IP) header, and the header compression of the UDP header or the IP header is UDP/IP header compression that uses a Robust Header Compression (ROHC) framework.
In some implementations, the one or more headers further include a General Packet Radio Service (GPRS) Tunneling Protocol (GTP) header, and the UDP/IP header compression is aggregated with GTP header compression.
In some implementations, the process further includes: categorizing GTP header fields based on the ROHC framework by assigning each GTP header field to one of the following categories: INFERRED, STATIC, STATIC-DEF, STATIC-KNOWN, and CHANGING.
In some implementations, the header compression is configured independently over a respective backhaul link in each hop between the IAB node and the destination IAB node.
In some implementations, the process further includes determining respective compression efficiencies for the backhaul links between the IAB node and the destination IAB node.
In some implementations, the process further includes: determining, based the respective compression efficiency of a first backhaul link, whether to perform header compression over the first backhaul link.
The example process shown in FIG. 4 can be modified or reconfigured to it include additional, fewer, or different steps (not shown in FIG. 4 ), which can be performed in the order shown or in a different order.
FIG. 5 illustrates an example architecture of a system 500 of a network, in accordance with various embodiments. The following description is provided for an example system 500 that operates in conjunction with the LTE system standards and 5G or NR system standards as provided by 3GPP technical specifications. However, the example embodiments are not limited in this regard and the described embodiments may apply to other networks that benefit from the principles described herein, such as future 3GPP systems (e.g. Sixth Generation (6G)) systems, IEEE 802.16 protocols (e.g., WMAN, WiMAX, etc.), or the like.
As shown by FIG. 5 , the system 500 includes UE 501 a and UE 501 b (collectively referred to as “UEs 501 ” or “UE 501 ”). In this example, UEs 501 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but may also comprise any mobile or non-mobile computing device, such as consumer electronics devices, cellular phones, smartphones, feature phones, tablet computers, wearable computer devices, personal digital assistants (PDAs), pagers, wireless handsets, desktop computers, laptop computers, in-vehicle infotainment (IVI), in-car entertainment (ICE) devices, an Instrument Cluster (IC), head-up display (HUD) devices, onboard diagnostic (OBD) devices, dashtop mobile equipment (DME), mobile data terminals (MDTs), Electronic Engine Management System (EEMS), electronic/engine control units (ECUs), electronic/engine control modules (ECMs), embedded systems, microcontroller, control modules, engine management systems (EMS), networked or “smart” appliances, MTC devices, M2M, IoT devices, and/or the like.
In some embodiments, any of the UEs 501 may be IoT UEs, which may comprise a network access layer designed for low-power IoT applications utilizing short-lived UE connections. An IoT UE can utilize technologies such as M2M or MTC for exchanging data with an MTC server or device via a PLMN, ProSe or D2D communication, sensor networks, or IoT networks. The M2M or MIC exchange of data may be a machine-initiated exchange of data. An IoT network describes interconnecting IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections. The IoT UEs may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the it connections of the IoT network.
The UEs 501 may be configured to connect, for example, communicatively couple, with an or RAN 510 . In embodiments, the RAN 510 may be an NG RAN or a 5G RAN, an E-UTRAN, or a legacy RAN, such as a UTRAN or GERAN. As used herein, the term “NG RAN” or the like may refer to a RAN 510 that operates in an NR or 5G system 500 , and the term “E-UTRAN” or the like may refer to a RAN 310 that operates in an LTE or 4G system 500 . The UEs 501 utilize connections (or channels) 503 and 504 , respectively, each of which comprises a physical communications interface or layer (discussed in further detail below).
In this example, the connections 303 and 504 are illustrated as an air interface to enable communicative coupling, and can be consistent with cellular communications protocols, such as a GSM protocol, a CDMA network protocol, a PTT protocol, a POC protocol, a UMTS protocol, a 3GPP LTE protocol, a 5G protocol, a NR protocol, and/or any of the other communications protocols discussed herein. In embodiments, the UEs 501 may directly exchange communication data via a ProSe interface 305 . The ProSe interface 505 may alternatively be referred to as a SL interface 505 and may comprise one or more logical channels, including but not limited to a PSCCH, a PSSCH, a PSDCH, and a PSBCH.
The UE 501 b is shown to be configured to access an AP 506 (also referred to as “WLAN node 506 ,” “WLAN 506 ,” “WLAN Termination 506 ,” “WT 506 ” or the like) via connection 507 . The connection 507 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 506 would comprise a wireless fidelity (Wi-Fi®) router. In this example, the AP 506 is shown to be connected to the Internet without connecting to the core network of the wireless system (described in further detail below). In various embodiments, the UE 501 b , RAN 510 , and AP 506 may be configured to utilize LWA operation and/or LWIP operation. The LWA operation may involve the UE 500 b in RRC_CONNECTED being configured by a RAN node 511 a - b to utilize radio resources of LTE and WLAN. LWIP operation may involve the UE 501 b using WLAN radio resources (e.g., connection 507 ) via IPsec protocol tunneling to authenticate and encrypt packets (e.g., IP packets) sent over the connection 507 . IPsec tunneling may include encapsulating the entirety of original IP packets and adding a new packet header, thereby protecting the original header of the IP packets.
The RAN 510 can include one or more AN nodes or RAN nodes 511 a and 511 b (collectively referred to as “RAN nodes 511 ” or “RAN node 511 ”) that enable the connections 503 and 504 . As used herein, the terms “access node,” “access point,” or the like may describe equipment that provides the radio baseband functions for data and/or voice connectivity between a network and one or more users. These access nodes can be referred to as BS, gNBs, RAN nodes, eNBs, NodeBs, RSUs, TRxPs or TRPs, and so forth, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell). As used herein, the term “NG RAN node” or the like may refer to a RAN node 511 that operates in an NR or 5G system 500 (for example, a gNB), and the term “E-UTRAN node” or the like may refer to a RAN node 511 that operates in an LTE or 4G system 500 (e.g., an eNB). According to various embodiments, the RAN nodes 511 may be implemented as one or more of a dedicated physical device such as a macrocell base station, and/or a low power (LP) base station for providing femtocells, picocells or other like cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells.
In some embodiments, all or parts of the RAN nodes 511 may be implemented as one or more software entities running on server computers as part of a virtual network, which may be referred to as a CRAN and/or a virtual baseband unit pool (vBBUP). In these embodiments, the CRAN or vBBUP may implement a RAN function split, such as a PDCP split wherein RRC and PDCP layers are operated by the CRAN/vBBUP and other L2 protocol entities are operated by individual RAN nodes 511 ; a MAC/PHY split wherein RRC, PDCP, RLC, and MAC layers are operated by the CRAN/vBBUP and the PHY layer is operated by individual RAN nodes 511 ; or a “lower PHY” split wherein RRC, PDCP, RLC, MAC layers and upper portions of the PHY layer are operated by the CRAN/vBBUP and lower portions of the PHY layer are operated by individual RAN nodes 511 . This virtualized framework allows the freed-up processor cores of the RAN nodes 511 to perform other virtualized applications. In some implementations, an individual RAN node 511 may represent individual gNB-DUs that are connected to a gNB-CU via individual F1 interfaces (not shown by FIG. 5 ). In these implementations, the gNB-DUs may include one or more remote radio heads or RFEMs (see, e.g., FIG. 7 ), and the gNB-CU may be operated by a server that is located in the RAN 510 (not shown) or by a server pool in a similar manner as the CRAN/vBBUP. Additionally or alternatively, one or more of the RAN nodes 511 may be next generation eNBs (ng-eNBs), which am RAN nodes that provide E-UTRA user plane and control plane protocol terminations toward the UEs 501 , and are connected to a 5GC via an NG interface (discussed infra).
In V2X scenarios one or more of the RAN nodes 511 may be or act as RSUs. The term “Road Side Unit” or “RSU” may refer to any transportation infrastructure entity used for V2X communications. An RSU may be implemented in or by a suitable RAN node or a stationary (or relatively stationary) UE, where an RSU implemented in or by a UE may be referred to as a “UE-type RSU,” an RSU implemented in or by an eNB may be referred to as an “eNB-type RSU,” an RSU implemented in or by a gNB may be referred to as a “gNB-type RSU,” and the like. In one example, an RSU is a computing device coupled with radio frequency circuitry located on a roadside that provides connectivity support to passing vehicle UEs 501 (vUEs 501 ). The RSU may also include internal data storage circuitry to store intersection map geometry, traffic statistics, media, as well as applications/software to sense and control ongoing vehicular and pedestrian traffic. The RSU may operate on the 5.9 GHz Direct Short Range wo Communications (DSRC) band to provide very low latency communications required for high speed events, such as crash avoidance, traffic warnings, and the like. Additionally or alternatively, the RSU may operate on the cellular V2X band to provide the aforementioned low latency communications, as well as other cellular communications services. Additionally or alternatively, the RSU may operate as a Wi-Fi hotspot (2.4 GHz band) and/or provide connectivity to one or more cellular networks to provide uplink and downlink communications. The computing device(s) and some or all of the radiofrequency circuitry of the RSU may be packaged in a weatherproof enclosure suitable for outdoor installation, and may include a network interface controller to provide a wired connection (e.g., Ethernet) to a traffic signal controller and/or a backhaul network.
Any of the RAN nodes 511 can terminate the air interface protocol and can be the first point of contact for the UEs 501 . In some embodiments, any of the RAN nodes 511 can fulfill various logical functions for the RAN 510 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.
In embodiments, the UEs 501 can be configured to communicate using OFDM communication signals with each other or with any of the RAN nodes 511 over a multicarrier communication channel in accordance with various communication techniques, such as, but not limited to, an OFDMA communication technique (e.g., for downlink communications) or a SC-FDMA communication technique (e.g., for uplink and ProSe or sidelink communications), although the scope of the embodiments is not limited in this respect. The OFDM signals can comprise a plurality of orthogonal subcarriers.
In some embodiments, a downlink resource grid can be used for downlink transmissions from any of the RAN nodes 511 to the UEs 501 , while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in a radio frame. The smallest time-frequency unit in a resource grid is denoted as a resource element. Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a collection of resource elements, in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated. There are several different physical downlink channels that are conveyed using such resource blocks.
According to various embodiments, the UEs 501 and the RAN nodes 511 communicate data (for example, transmit and receive) data over a licensed medium (also referred to as the “licensed spectrum” and/or the “licensed band”) and an unlicensed shared medium (also referred to as the “unlicensed spectrum” and/or the “unlicensed band”). The licensed spectrum may include channels that operate in the frequency range of approximately 400 MHz to approximately 3.8 GHz, whereas the unlicensed spectrum may include the 5 GHz band.
To operate in the unlicensed spectrum, the UEs 501 and the RAN nodes 511 may operate using LAA, eLAA, and/or feLAA mechanisms. In these implementations, the UEs 501 and the RAN nodes 511 may perform one or more known medium-sensing operations and/or carrier-sensing operations in order to determine whether one or more channels in the unlicensed spectrum is unavailable or otherwise occupied prior to transmitting in the unlicensed spectrum. The medium/carrier sensing operations may be performed according to a listen-before-talk (LBT) protocol.
LBT is a mechanism whereby equipment (for example, UEs 501 RAN nodes 511 , etc.) senses a medium (for example, a channel or carrier frequency) and transmits when the medium is sensed to be idle (or when a specific channel in the medium is sensed to be unoccupied). The medium sensing operation may include CCA, which utilizes at least ED to determine the presence or absence of other signals on a channel in order to determine if a channel is occupied or clear. This LBT mechanism allows cellular/LAA networks to coexist with incumbent systems in the unlicensed spectrum and with other LAA networks. ED may include sensing RF energy across an intended transmission band for a period of time and comparing the sensed RF energy to a predefined or configured threshold.
Typically, the incumbent systems in the 5 GHz band are WLANs based on IEEE 802.11 technologies. WLAN employs a contention-based channel access mechanism, called CSMA/CA. Here, when a WLAN node (e.g., a mobile station (MS) such as UE 501 , AP 506 , or the like) intends to transmit, the WLAN node may first perform CCA before transmission Additionally, a backoff mechanism is used to avoid collisions in situations where more than one WLAN node senses the channel as idle and transmits at the same time. The backoff mechanism may be a counter that is drawn randomly within the CWS, which is increased exponentially upon the occurrence of collision and reset to a minimum value when the transmission succeeds. The LRT mechanism designed for LAA is somewhat similar to the CSMA/CA of WLAN. In some implementations, the LBT procedure for DL or UL transmission bunts including PDSCH or PUSCH transmissions, respectively, may have an LAA contention window that is variable in length between X and Y ECCA slots, where X and Y are minimum and maximum values for the CWSs for LAA. In one example, the minimum CWS for an LAA transmission may be 9 microseconds (μs); however, the size of the CWS and a MCOT (for example, a transmission burst) may be based on governmental regulatory requirements.
The LAA mechanisms are built upon CA technologies of LTE-Advanced systems. In CA, each aggregated carrier is referred to as a CC. A CC may have a bandwidth of 1, 4, 3, 5, 10, 15 or 20 MHz and a maximum of five CCs can be aggregated, and therefore, a maximum aggregated bandwidth is 100 MHz. In FDD systems, the number of aggregated carriers can be different tor DL and UL, where the number of UL CCs is equal to or lower than the number of DL component carriers. In some cases, individual CCs can have a different bandwidth than other CCs. In TDD systems, the number of CCs as well as the bandwidths of each CC is usually the same for DL and UL.
CA also comprises individual serving cells to provide individual CCs. The coverage of the serving cells may differ, for example, because CCs on different frequency bands will experience different pathloss. A primary service cell or PCell may provide a PCC for both UL and DL, and may handle RRC and NAS related activities. The other serving cells are referred to as SCells, and each SCell may provide an individual SCC for both UL and DL The SCCs may be added and removed as required, while changing the PCC may require the UE 501 to undergo a handover. In LAA, eLAA, and feLAA, some or all of the SCells may operate in the unlicensed spectrum (referred to as “LAA SCells”), and the LAA SCells are assisted by a PCell operating in the licensed spectrum. When a UE is configured with more than one LAA SCell, the UE may receive UL grants on the configured LAA SCells indicating different PUSCH starting positions within a same subframe.
The PDSCH carries user data and higher-layer signaling to the UEs 501 . The PDCCH carries information about the transport format and resource allocations related to the PDSCH channel, among other things. It may also inform the UEs 501 about the transport format, resource allocation, and HARQ information related to the uplink shared channel. Typically, downlink scheduling (assigning control and shared channel resource blocks to the UE 501 b within a cell) may be performed at any of the RAN nodes 511 based on channel quality information fed back from any of the UEs 501 . The downlink resource assignment information may be sent on the PDCCH used for (e.g., assigned to) each of the UEs 501 .
The PDCCH uses CCEs to convey the control information. Before being to mapped to resource elements, the PDCCH complex-valued symbols may first be organized into quadruplets, which may then be permuted using a sub-block interleaver for rate matching. Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as REGs. Four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. The PDCCH can be transmitted using one or more CCEs, depending on the size of the DCI and the channel condition. There can be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L=1, 2, 4, or 8).
Some embodiments may use concepts for resource allocation for control channel information that are an extension of the above-described concepts. For example, some embodiments may utilize an EPDCCH that uses PDSCH resources for control information transmission. The EPDCCH may be transmitted using one or more ECCEs. Similar to above, each ECCE may correspond to nine sets of four physical resource elements known as an EREGs. An ECCE may have other numbers of EREGs in some situations.
The RAN nodes 511 may be configured to communicate with one another via interface 512 . In embodiments where the system 500 is an LTE system (e.g. when CN 520 is an EPC 620 as in FIG. 6 ), the interface 512 may be an X2 interface 512 . The X2 interface may be defined between two or more RAN nodes 511 (e.g., two or more eNBs and the like) that connect to EPC 520 , and/or between two eNBs connecting to EPC 520 . In some implementations, the X2 interface may include an X2 user plane interface (X2-U) and an X2 control plane interface (X2-C). The X2-U may provide flow control mechanisms for user data packets transferred over the X2 interface, and may be used to communicate information about the delivery of user data between eNBs. For example, the X2-U may provide specific sequence number information for user data transferred from a MeNB to an SeNB; information about successful in sequence delivery of PDCP PDUs to a UE 501 from an SeNB for user data; information of PDCP PDUs that were not delivered to a UE 501 ; information about a current minimum desired buffer size at the SeNB for transmitting to the UE user data; and the like. The X2-C may provide intra-LTE access mobility functionality, including context transfers from source to target eNBs, user plane transport control, etc.; load management functionality; as well as inter-cell interference coordination functionality.
In embodiments where the system 500 is a 5G or NR system, the interface 512 may be an Xn interface 512 . The Xn interface is defined between two or more RAN nodes 511 (e.g., two or more gNBs and the like) that connect to 5GC 520 , between a RAN node 511 (e.g., a gNB) connecting to 5GC 520 and an eNB, and/or between two eNBs connecting to 5GC 520 . In some implementations, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. The Xn-U may provide non-guaranteed delivery of user plane PDUs and support/provide data forwarding and flow control functionality. The Xn-C may provide management and error handling functionality, functionality to manage the Xn-C interface; mobility support for UE 501 in a connected mode (e.g., CM-CONNECTED) including functionality to manage the UE mobility for connected mode between one or more RAN nodes 511 . The mobility support may include context transfer from an old (source) serving RAN node 511 to new (target) serving RAN node 511 ; and control of user plane tunnels between old (source) serving RAN node 511 to new (target) serving RAN node 511 . A protocol stack of the Xn-U may include a transport network layer built on Internet Protocol (IP) transport layer, and a GTP-U layer on top of a UDP and/or IP layer(s) to carry user plane PDUs. The Xn-C protocol stack may include an application layer signaling protocol (referred to as Xn Application Protocol (Xn-AP)) and a transport network layer that is built on SCTP. The SCTP may be on top of an IP layer, and may provide the guaranteed delivery of application layer messages. In the transport IP layer, point-to-point transmission is used to deliver the signaling PDUs. In other implementations, the Xn-U protocol stack and/or the Xn-C protocol stack may be same or similar to the user plane and/or control plane protocol stack(s) shown and described herein.
The RAN 510 is shown to be communicatively coupled to a cue network—in this embodiment, core network (CN) 520 . The CN 520 may comprise a plurality of network elements 522 , which are configured to offer various data and telecommunications services to customers/subscribers (e.g., users of UEs 501 ) who are connected to the CN 520 via the RAN 510 . The components of the CN 520 may be implemented in tone physical node or separate physical nodes including components to read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In some embodiments, NFV may be utilized to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage mediums (described in further detail below) A logical instantiation of the CN 520 may be referred to as a network slice, and a logical instantiation of a portion of the CN 520 may be referred to as a network sub-slice. NFV architectures and infrastructures may be used to virtualize one or more network functions, alternatively performed by proprietary hardware, onto physical resources comprising a combination of industry-standard server hardware, storage hardware, or switches. In other words, NFV systems can be used to execute virtual or reconfigurable implementations of one or more EPC components/functions.
Generally, the application server 530 may be an element offering applications that use IP bearer resources with the core network (e.g., UMTS PS domain, LTE PS data services, etc.). The application server 530 can also be configured to support one or more communication services (e.g., VoIP sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 501 via the EPC 520 .
In embodiments, the CN 520 may be a 5GC (referred to as “5GC 520 ” or the like), and the RAN 510 may be connected with the CN 520 via an NG interface 513 . In embodiments, the NG interface 513 may be split into two parts, an NG user plane (NG-U) interface 514 , which carries traffic data between the RAN nodes 511 and a UPF, and the S1 control plane (NG-C) interface 515 , which is a signaling interface between the RAN nodes 511 and AMFs.
In embodiments, the CN 520 may be a 5G CN (referred to as “5GC 520 ” or the like), while in other embodiments, the CN 520 may be an EPC). Where CN 520 is an EPC (referred to as “EPC 520 ” or the like), the RAN 510 may be connected with the CN 520 via an S1 interface 513 . In embodiments, the S1 interface 313 may be split into two parts, an S1 user plane (S1-U) interface 514 , which carries traffic data between the RAN nodes 511 and the S-GW, and the S1-MME interface 515 , which is a signaling interface between the RAN nodes 511 and MMEs.
FIG. 6 illustrates an example architecture of a system 600 including a first CN 620 , in accordance with various embodiments. In this example, system 600 may implement the LTE standard wherein the CN 620 is an EPC 620 that corresponds with CN 520 of FIG. 5 . Additionally, the UE 601 may be the same or similar as the UEs 50 of FIG. 5 , and the E-UTRAN 610 may be a RAN that is the same or similar to the RAN 510 of FIG. 5 , and which may include RAN nodes 511 discussed previously. The CN 620 may comprise MMEs 621 , an S-GW 622 , a P-GW 623 , a HSS 624 , and a SGSN 625 .
The MMEs 621 may be similar in function to the control plane of legacy SGSN, and may implement MM functions to keep track of the current location of a UE 601 . The MMEs 621 may perform various MM procedures to manage mobility aspects in access such as gateway selection and tracking area list management. MM (also referred to as “EPS MM” or “EMM” in E-UTRAN systems) may refer to all applicable procedures, methods, data storage, etc. that are used to maintain knowledge about a present location of the UE 601 , provide user identity confidentiality, and/or perform other like services to users/subscribers. Each UE 601 and the MME 621 may include an MM or EMM sublayer, and an MM context may be established in the UE 601 and the MME 621 when an attach procedure is successfully completed. The MM context may be a data structure or database object that stores MM-related information of the UE 601 . The MMEs 621 may be coupled with the HSS 624 via an S6a reference point, coupled with the SGSN 625 via an S3 reference point, and coupled with the S-GW 622 via an S11 reference point.
The SGSN 625 may be a node that serves the UE 601 by tracking the location of an individual UE 601 and performing security functions. In addition, the SGSN 625 may perform Inter-EPC node signaling for mobility between 2G/3G and E-UTRAN 3GPP access networks; PDN and S-GW selection as specified by the MMEs 621 ; handling of UE 601 time zone functions as specified by the MMEs 621 ; and MME selection for handovers to E-UTRAN 3GPP access network. The S3 reference point between the MMEs 621 and the SGSN 625 may enable user and bearer information exchange for inter-3GPP access network mobility in idle and/or active states.
The HSS 624 may comprise a database for network users, including subscription-related information to support the network entities' handling of communication sessions. The EPC 620 may comprise one or several HSSs 624 , depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc. For example, the HSS 624 can provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, etc. An S6a reference point between the HSS 624 and the MMEs 621 may enable transfer of subscription and authentication data for authenticating/authorizing user access to the EPC 620 between HSS 624 and the MMEs 621 .
The S-GW 622 may terminate the S1 interface 513 (“S1-U” in FIG. 6 ) toward the RAN 610 , and routes data packets between the RAN 610 and the E-PC 620 . In addition, the S-GW 622 may be a local mobility anchor point for inter-RAN node handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement. The S11 reference point between the S-GW 622 and the MMEs 621 may provide a control plane between the MMEs 621 and the S-GW 622 . The S-GW 622 may be coupled with the P-GW 623 via an S5 reference point.
The P-GW 623 may terminate an SGi interface toward a PDN 630 . The P-GW 623 may route data packets between the EPC 620 and external networks such as a network including the application server 530 (alternatively referred to as an “AF”) via an IP interface 525 (see e.g., FIG. 5 ). In embodiments, the P-GW 623 may be communicatively coupled to an application server (application server 530 of FIG. 5 or PDN 630 in FIG. 6 ) via an IP communications interface 525 (see e.g. FIG. 5 ). The S5 reference point between the P-GW 623 and the S-GW 622 may provide user plane tunneling and tunnel management between the P-GW 623 and the S-GW 622 . The S5 reference point may also be used for S-GW 622 relocation due to UE 601 mobility and if the S-GW 622 needs to connect to a non-collocated P-GW 623 for the required PDN connectivity. The P-GW 623 may further include a nude for policy enforcement and charging data collection (e.g., PCEF (not shown)). Additionally, the SGi reference point between the P-GW 623 and the packet data network (PDN) 630 may be an operator external public, a private PDN, or an intra operator packet data network, for example, for provision of MS services. The P-GW 623 may be coupled with a PCRF 626 via a Gx reference point.
PCRF 626 is the policy and charging control element of the EPC 620 . In a non-roaming scenario, there may be a single PCRF 626 in the Home Public Land Mobile Network (HPLMN) associated with a UE 601 's Internet Protocol Connectivity Access Network (IP-CAN) session. In a roaming scenario with local breakout of traffic, there may be two PCRFs associated with a UE 601 's IP-CAN session, a Home PCRF (H-PCRF) within an HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). The PCRF 626 may be communicatively coupled to the application server 630 via the P-GW 623 . The application server 630 may signal the PCRF 626 to indicate a new service flow and select the appropriate QoS and charging parameters. The PCRF 626 may provision this rule into a PCEF (not shown) with the appropriate TFT and QCI, which commences the QoS and charging as specified by the application server 630 . The Gx reference point between the PCRF 626 and the P-GW 623 may allow for the transfer of QoS policy and charging rules from the PCRF 626 to PCEF in the P-GW 623 . An Rx reference point may reside between the PDN 630 (or “AF 630 ”) and the PCRF 626 .
FIG. 7 illustrates an example of infrastructure equipment 700 in accordance with various embodiments. The infrastructure equipment 700 (or “system 700 ”) may be implemented as a base station, radio head, RAN node such as the RAN nodes 511 and/or AP 506 shown and described previously, application server(s) 530 , and/or any other element-device discussed herein. In other examples, the system 700 could be implemented in or by a UE.
The system 700 includes application circuitry 705 , baseband circuitry 710 , one or more radio front end modules (RFEMs) 715 , memory circuitry 720 , power management integrated circuitry (PMIC) 725 , power tee circuitry 730 , network controller circuitry 735 , network interface connector 740 , satellite positioning circuitry 745 , and user interface 750 . In some embodiments, the device 700 may include additional elements such as, for example, memory/storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, die components described below may be included in more than one device. For example, said circuitries may be separately included in more than one device for CRAN, vBBU, or other like implementations.
Application circuitry 705 includes circuitry such as, but not limited to one or more processors (or processor cures), cache memory, and one or more of low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose input/output (I/O or IO), memory card controllers such as Secure Digital (SD) MultiMediaCard (MMC) or similar, Universal Serial Bus (USB) interface, Mobile Industry Processor Interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports. The processors (or cores) of the application circuitry 705 may be coupled with or may include memory/storage elements and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the system 700 . In some implementations, the memory/storage elements may be on-chip memory circuitry, which may include any suitable volatile and/or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, Flash memory, solid-state memory, and/or any other type of memory device technology, such as those discussed herein.
The processor(s) of application circuitry 705 may include, for example, one or more processor cores (CPUs), one or more application processors, one or more graphics processing units (GPUs), one or more reduced instruction set computing (RISC) processors, one or more Acorn RISC Machine (ARM) processors, one or more complex instruction set computing (CISC) processors, one or more digital signal processors (DSP), one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, or any suitable combination thereof. In some embodiments, the application circuitry 705 may comprise, or may be, a special-purpose processor/controller to operate according to the various embodiments herein. As examples, the processor(s) of application circuitry 705 may include one or more Intel Pentium®, Core®, or Xeon® processor(s); Advanced Micro Devices (AMD) Ryzen® processor(s), Accelerated Processing Units (APUs), or Epyc® processors; ARM-based processor(s) licensed from ARM Holdings, Ltd. such as the ARM Cortex-A family of processors and the ThunderX2® provided by Cavium™, Inc.; a MIPS-based design from MIPS Technologies, Inc. such as MIPS Warrior P-class processors; and/or the like. In some embodiments, the system 700 may not utilize application circuitry 705 , and instead may include a special-purpose processor/controller to process IP data received from an EPC or 5GC, for example.
In some implementations, the application circuitry 705 may include one or more hardware accelerators, which may be microprocessors, programmable processing devices, or the like. The one or more hardware accelerators may include, for example, computer vision (CV) and/or deep learning (DL) accelerators. As examples, the programmable processing devices may be one or mom a field-programmable devices (FPDs) such as field-programmable gate arrays (FPGAs) and the like; programmable logic devices (PLDs) such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs), and the like; ASICs such as structured ASICs and the like; programmable SoCs (PSoCs); and the like. In such implementations, the circuitry of application circuitry 705 may comprise logic blocks or logic fabric, and other interconnected resources that may be programmed to perform various functions, such as the procedures, methods, functions, etc. of the various embodiments discussed herein. In such embodiments, the circuitry of application circuitry 705 may include memory cells (e.g., erasable programmable read-only memory (EPROM), eclectically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), anti-fuses, etc.)) used to store logic blocks, logic fabric, data, etc. in look-up-tables (LUTs) and the like.
The baseband circuitry 710 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.
User interface circuitry 740 may include one or more user interfaces designed to enable user interaction with the system 700 or peripheral component interfaces designed to enable peripheral component interaction with the system 700 . User interfaces may include, but are not limited to, one or more physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., light emitting diodes (LEDs)), a physical keyboard or keypad, a mouse, a touchpad, a touchscreen, speakers or other audio emitting devices, microphones, a pointer, a scanner, a headset, a display screen or display device, etc. Peripheral component interfaces may include, but are not limited to, a nonvolatile memory port, a universal serial bus (USB) port, an audio jack, a power supply interface, etc.
The radio front end modules (RFEMs) 713 may comprise a millimeter wave (mmWave) RFEM and one or more sub-mmWave radio frequency integrated circuits (RFICs). In some implementations, the one or more sub-mmWave RFICs may be physically separated from the mmWave RFEM. The RFICs may include connections to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In alternative implementations, both mmWave and sub-mmWave radio functions may be implemented in the same physical RFEM 715 , which incorporates both mmWave antennas and sub-mmWave.
The memory circuitry 720 may include one or more of volatile memory including dynamic random access memory (DRAM) and/or synchronous dynamic random access memory (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc., and may incorporate the three-dimensional (3D) cross-point (XPOINT) memories from Intel® and Micron®. Memory circuitry 720 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.
The PMIC 725 may include voltage regulators, surge protectors, power alarm detection circuitry, and one or more backup power sources such as a battery or capacitor. The power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions. The power tee circuitry 730 may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the infrastructure equipment 700 using a single cable.
The network controller circuitry 735 may provide connectivity to a network using a standard network interface protocol such as Ethernet, Ethernet over GRE Tunnels, Ethernet over Multiprotocol Label Switching (MPLS), or some other suitable protocol. Network connectivity may be provided to/from the infrastructure equipment 700 via network interface connector 740 using a physical connection, which may be electrical (commonly referred to as a “copper interconnect”) optical, or wireless. The network controller circuitry 735 may include one or more dedicated processors and/or FPGAs to communicate using one or more of the aforementioned protocols. In some implementations, the network controller circuitry 735 may include multiple controllers to provide connectivity to other networks using the same or different protocols.
The positioning circuitry 745 includes circuitry to receive and decode signals transmitted/broadcasted by a positioning network of a global navigation satellite system (GNSS). Examples of navigation satellite constellations (or GNSS) include United States' Global Positioning System (GPS), Russia's Global Navigation System (GLONASS), the European Union's Galileo system, China's BeiDou Navigation Satellite System, a regional navigation system or GNSS augmentation system (e.g., Navigation with Indian Constellation (NAVIC), Japan's Quasi-Zenith Satellite System (QZSS), France's Doppler Orbitography and Radio-positioning Integrated by Satellite (DORIS), etc.), or the like. The positioning circuitry 745 comprises various hardware elements (e.g. including hardware devices such as switches, filters, amplifiers, antenna elements, and the like to facilitate OTA communications) to communicate with components of a positioning network, such as navigation satellite constellation nodes. In some embodiments, the positioning circuitry 740 may include a Micro-Technology for Positioning, Navigation, and Timing (Micro-PNT) IC that uses a master timing clock to perform position tracking/estimation without GNSS assistance. The positioning circuitry 745 may also be pan of, or interact with, the baseband circuitry 710 and/or RFEMs 715 to communicate with the nodes and components of the positioning network. The positioning circuitry 745 may also provide position data and/or time data to the application circuitry 705 , which may use the data to synchronize operations with various infrastructure (e.g., RAN nodes 511 , etc.), or the like.
The components shown by FIG. 7 may communicate with one another using interface circuitry, which may include any number of bus and/or interconnect (IX) technologies such as industry standard architecture (ISA), extended ISA (EISA), peripheral component interconnect (PCI), peripheral component interconnect extended (PCIx). PCI express (PCIe), or any number of other technologies. The bus/IX may be a proprietary bus, for example, used in a SoC based system. Other bus/IX systems may be included, such as an I2C interface, an SPI interface, point to point interfaces and a power bus, among others.
FIG. 8 illustrates various protocol functions that may be implemented in a wireless communication device according to various embodiments. In particular, FIG. 8 includes an arrangement 800 showing interconnections between various protocol layers/entities. The following description of FIG. 8 is provided for various protocol layers/entities that operate in conjunction with the 5G/NR system standards and LTE system standards, but some or all of the aspects of FIG. 8 may be applicable to other wireless communication network systems as well.
The protocol layers of arrangement 800 may include one or more of PHY 810 , MAC 820 , RLC 830 , PDCP 840 , SDAP 847 , RRC 855 , and NAS layer 857 , in addition to other higher layer functions not illustrated. The protocol layers may include one or more service access points (e.g., items 859 , 856 , 850 , 849 , 845 , 835 , 825 , and 1015 in FIG. 8 ) that may provide communication between two or more protocol layers.
The PHY 1010 may transmit and receive physical layer signals 805 that may be received from or transmitted to one or more other communication devices. The physical layer signals 805 may comprise one or more physical channels, such as those discussed herein. The PHY 1010 may further perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as the RRC 855 . The PHY 1010 may still further perform error detection on the transport channels, forward error correction (FEC) coding/decoding of the transport channels, modulation/demodulation of physical channels, interleaving, rate matching, mapping onto physical channels, and MIMO antenna processing. In embodiments, an instance of PHY 1010 may process requests from and provide indications to an instance of MAC 820 via one or mom PHY-SAP 1015 . According to some embodiments, requests and indications communicated via PHY-SAP 1015 may comprise one or more transport channels.
Instance(s) of MAC 820 may process requests from, and provide indications to, an instance of RLC 830 via one or mom MAC-SAPs 825 . These requests and indications communicated via the MAC-SAP 825 may comprise one or more logical channels. The MAC 820 may perform mapping between the logical channels and transport channels, multiplexing of MAC SDUs from one or more logical channels onto TBs to be delivered to PHY 1010 via the transport channels, de-multiplexing MAC SDUs to one or more logical channels from TBs delivered from the PHY 1010 via transport channels, multiplexing MAC SDUs onto TBs, scheduling information reporting, error connection through HARQ, and logical channel prioritization.
Instance(s) of RLC 830 may process requests from and provide indications to an instance of PDCP 40 via one or more radio link control service access points (RLC-SAP) 835 . These requests and indications communicated via RLC-SAP 835 may comprise one or more RLC channels. The RLC 830 may operate in a plurality of modes of operation, including: Transparent Mode (TM), Unacknowledged Mode (UM), and Acknowledged Mode (AM). The RLC 830 may execute transfer of upper layer protocol data units (PDUs), error correction through automatic repeat request (ARQ) for AM data transfers, and concatenation, segmentation and reassembly of RLC SDUs for UM and AM data transfers. The RLC 830 may also execute re-segmentation of RLC data PDUs for AM data transfers, reorder RLC data PDUs for UM and AM data transfers, detect duplicate data for UM and AM data transfers, discard RLC SDUs for UM and AM data transfers, detect protocol errors for AM data transfers, and perform RLC re-establishment.
Instance(s) of PDCP 840 may process requests from and provide indications to instance(s) of RRC 855 and/or instance(s) of SDAP 847 via one or more packet data convergence protocol service access points (PDCP-SAP) 845 . These requests and indications communicated via PDCP-SAP 845 may comprise one or more radio bearers. The PDCP 840 may execute header compression and decompression of IP data, maintain PDCP Sequence Numbers (SNs), perform in-sequence delivery of upper layer PDUs at re-establishment of lower layers, eliminate duplicates of lower layer SDUs at re-establishment of lower layers for radio bearers mapped on RLC AM, cipher and decipher control plane data, perform integrity protection and integrity verification of control plane data, control timer-based discard of data, and perform security operations (e.g., ciphering, deciphering, integrity protection, integrity verification, etc.).
Instance(s) of SDAP 847 may process requests from and provide indications to one or more higher layer protocol entities via one or more SDAP-SAP 849 . These requests and indications communicated via SDAP-SAP 849 may comprise one or more QoS flows. The SDAP 847 may map QoS flows to DRBs, and vice versa, and may also mark QFIs in DL and UL packets A single SDAP entity 847 may be configured for an individual PDU session. In the UL direction, the NG-RAN 510 may control the mapping of QoS Flows to DRB(s) in two different ways, reflective mapping or explicit mapping. For reflective mapping, the SDAP 847 of a UE 501 may monitor the QFIs of the DL packets for each DRB, and may apply the same mapping for packets flowing in the UL direction. For a DRB, the SDAP 847 of the UE 501 may map the UL packets belonging to the QoS flows(s) corresponding to the QoS flow ID(s) and PDU session observed in the DL packets for that DRB. To enable reflective mapping, the NG-RAN may mark DL packets over the Uu interface with a QoS flow ID. The explicit mapping may involve the RRC 855 configuring the SDAP 847 with an explicit QoS flow to DRB mapping rule, which may be stored and followed by the SDAP 847 . In embodiments, the SDAP 847 may only be used in NR implementations and may not be used in LTE implementations.
The RRC 855 may configure, via one or more management service access points (M-SAP), aspects of one or more protocol layers, which may include one or more instances of PHY 1010 , MAC 820 , RLC 830 , PDCP 840 and SDAP 847 . In embodiments, an instance of RRC 835 may process requests from and provide indications to one or more NAS entities 857 via one or more RRC-SAPs 856 . The main services and functions of the RRC 855 may include broadcast of system information (e.g., included in MIBs or SIBs related to the NAS) broadcast of system information so related to the access stratum (AS), paging, establishment, maintenance and release of an RRC connection between the UE 501 and RAN 510 (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance and release of point to point Radio Bearers, security functions including key management, inter-RAT mobility, and measurement configuration for UE measurement reporting. The MIBs and SIBs may comprise one or more IEs, which may each comprise individual data fields or data structures.
The NAS 857 may form the highest stratum of the control plane between the UE 501 and the AMF The NAS 857 may support the mobility of the UEs 501 and the session management procedures to establish and maintain IP connectivity between the UE 501 and a P-GW in LTE systems.
According to various embodiments, one or more protocol entities of arrangement 800 may be implemented in UEs 501 , RAN nudes 511 , AMF in NR implementations or MME 621 in LTE implementations, UPF in NR implementations or S-GW 622 and P-GW 623 in LTE implementations, or the like to be used for control plane or user plane communications protocol stack between the aforementioned devices. In such embodiments, one or more protocol entities that may be implemented in one or more of UE 501 , gNB 511 , AMP, etc. may communicate with a respective peer protocol entity that may be implemented in or on another device using the services of respective lower layer protocol entities to perform such communication. In some embodiments, a gNB-CU of the gNB 511 may best the RRC 855 , SDAP 847 , and PDCP 840 of the gNB that controls the operation of one or more gNB-DUs, ad the gNB-DUs of the gNB 511 may each host the RLC 330 , MAC 820 , and PHY 1010 of the gNB 511 .
In a first example, a control plane protocol stack may comprise, in order from highest layer to lowest layer, NAS 1057 , RRC 1055 , PDCP 840 , RLC 830 , MAC 1020 , and PHY 1010 . In this example, upper layers 860 may be built on top of the NAS 1057 , which includes an IP layer 861 , an SCTP 862 , and an application layer signaling protocol (AP) 863 .
In NR implementations, the AP 863 may be an NG application protocol layer (NGAP or NG-AP) 363 for the NG interface 513 defined between the NG-RAN node 511 and the AMF, or the AP 863 may be an Xn application protocol layer (XnAP or Xn-AP) 863 for the Xn interface 512 that is defined between two or more RAN nodes 511 .
The NG-AP 863 may support the functions of the NG interface 513 and may comprise Elementary Procedures (EPs). An NG-AP EP may be a unit of interaction between the NG-RAN node 511 and the AMF. The NG-AP 863 services may comprise two groups UE-associated service (e.g., services related to a UE 501 ) and non-UE-associated services (e.g., services related to the whole NG interface instance between the NG-RAN node 511 and AMF). These services may include functions including, but not limited to: a paging function for the sending of paging requests to NG-RAN nodes 511 involved in a particular paging area; a UE context management function for allowing the AMF to establish, modify, and/or release a UE context in the AMF and the NG-RAN node 511 ; a mobility function for UEs 501 in ECM-CONNECTED mode for intra-system HOs to support mobility within NG-RAN and inter-system HOs to support mobility from/to EPS systems; a NAS Signaling Transport function for transporting or rerouting NAS messages between UE 501 and AMF; a NAS node selection function for determining an association between the AMF and the UE 501 ; NG interface management function(s) for setting up the NG interface and monitoring for errors over the NG interface; a warning massage transmission function for providing means to transfer warning messages via NG interface or cancel ongoing broadcast of warning messages; a Configuration Transfer function for requesting and transferring of RAN configuration information (e.g., SON information, performance measurement (PM) data, etc.) between two RAN nodes 511 via CN 520 ; and/or other like functions.
The XnAP 863 may support the functions of the Xn interface 512 and may comprise XnAP basic mobility procedures and XnAP global procedures. The XnAP basic mobility procedures may comprise procedures used to handle UE mobility within the NG RAN 511 (or E-UTRAN 610 ), such as handover preparation and cancellation procedures, SN Status Transfer procedures, UE context retrieval and UE context release procedures, RAN paging procedures, dual connectivity related procedures, and the like. The XnAP global procedures may comprise procedures that are not related to a specific UE 501 , such as Xn interface setup and reset procedures, NG-RAN update procedures, cell activation procedures, and the like.
In LTE implementations, the AP 863 may be an S1 Application Protocol layer (S1-AP) 863 for the S1 interface 513 defined between an E-UTRAN node 511 and an MME, or the AP 863 may be an X2 application protocol layer (X2AP or X2-AP) 863 for the X2 interface 512 that is defined between two or more E-UTRAN nodes 511 .
The S1 Application Protocol layer (S1-AP) 863 may support the functions of the S1 interface, and similar to the NG-AP discussed previously, the S1-AP may comprise S1-AP EPs. An S1-AP EP may be a unit of interaction between the E-UTRAN node 511 and an MME 621 within an LTE CN 520 . The S1-AP 863 services may comprise two groups: UE-associated services and non UE-associated services. These services perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transport, RAN Information Management (RIM), and configuration transfer.
The X2AP 863 may support the functions of the X2 interface 512 and may comprise X2AP basic mobility procedures and X2AP global procedures. The X2AP basic mobility procedures may comprise procedures used to handle UE mobility within the E-UTRAN 520 , such as handover preparation and cancellation procedures, SN Status Transfer procedures. UE context retrieval and UE context release procedures, RAN paging procedures, dual connectivity related procedures, and the like. The X2AP global procedures may comprise procedures that are not related to a specific UE 501 , such as X2 interface setup and reset procedures, load indication procedures, error indication procedures, cell activation procedures, and the like.
The SCTP layer (alternatively referred to as the SCTP/IP layer) 862 may provide guaranteed delivery of application layer messages (e.g., NGAP or XnAP messages in NR implementations, or S1-AP or X2AP messages in LTE implementations). The SCTP 862 may ensure reliable delivery of signaling messages wo between the RAN node 511 and the AMF/MME 621 based, in part, on the IP protocol, supported by the IP 361 . The Internet Protocol layer (IP) 861 may be used to perform packet addressing and routing functionality. In some implementations the IP layer 861 may use point-to-point transmission to deliver and convey PDUs. In this regard, the RAN node 511 may comprise L2 and L1 layer communication links (e.g., wired or wireless) with the MME/AMF to exchange information.
In a second example, a user plans protocol stack may comprise, in order from highest layer to lowest layer, SDAP 847 , PDCP 840 , RLC 830 , MAC 1020 , and PHY 1010 . The user plane protocol stack may be used for communication between the UE 501 , the RAN node 511 , and UPF in NR implementations or an S-GW 622 and P-GW 623 in LTE implementations. In this example, upper layers 851 may be built on top of the SDAP 847 , and may include a user datagram protocol (UDP) and IP security layer (UDP/IP) 852 , a General Packet Radio Service (GPRS) Tunneling Protocol for the user plane layer (GTP-U) 853 , and a User Plane PDU layer (UP PDU) 863 .
The transport network layer 854 (also referred to as a “transport layer”) may be built on IP transport, and the GTP-U 853 may be used on top of the UDP/IP layer 852 (comprising a UDP layer and IP layer) to carry user plane PDUs (UP-PDUs). The IP layer (also referred to as the “Internet layer”) may be used to perform packet addressing and routing functionality. The IP layer may assign IP addresses to user data packets in any of IPv4, IPv6, or PPP formats, for example.
The GTP-U 853 may be used for carrying user data within the GPRS core network and between the radio access network and the core network. The user data transported can be packets in any of IPv4, IPv6, or PPP formats, for example. The UDP/IP 852 may provide checksums for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication on the selected data flows. The RAN node 511 and the S-GW 622 may utilize an S1-U interface to exchange user plane data via a protocol stack comprising an L1 layer (e.g., PHY 1010 ), an L2 layer (e.g., MAC 820 , RLC 830 , PDCP 840 , and/or SDAP 847 ), the UDP/IP layer 852 , and the GTP-U 853 . The S-GW 622 and the P-GW 623 may utilize an S5/S8a interface to exchange user plane data via a protocol stack comprising an L1 layer, an L2 layer, the UDP/IP layer 852 , and the GTP-U 853 . As discussed previously, NAS protocols may support the mobility of the UE 501 and the session management procedures to establish and maintain IP connectivity between the UE 501 and the P-GW 623 .
Moreover, although not shown by FIG. 8 , an application layer may be present above the AP 363 and/or the transport network layer 854 . The application layer may be a layer in which a user of the UE 501 , RAN node 511 , or other network element interacts with software applications being executed, for example, by application circuitry 705 or application circuitry 805 , respectively. The application layer may also provide one or more interfaces for software applications to interact with communications systems of the UE 501 or RAN node 511 . In some implementations the IP layer and/or the application layer may provide the same or similar functionality as layers 5-7, or portions thereof, of the Open Systems Interconnection (OSI) model (e.g., OSI Layer 7—the application layer, OSI Layer 6— the presentation layer, and OSI Layer 5—the session layer).
FIG. 9 is a block diagram illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically, FIG. 9 shows a diagrammatic representation of hardware resources 900 including one or more processors (or processor cores) 910 , one or more memory/storage devices 920 , and one it or more communication resources 930 , each of which may be communicatively coupled via a bus 940 . For embodiments where node virtualization (e.g., NFV) is utilized, a hypervisor 902 may be executed to provide an execution environment for one or more network slices/sub-slices to utilize the hardware resources 900 .
The processors 910 may include, for example, a processor 912 and a processor 914 . The processor(s) 910 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a DSP such as a baseband processor, an ASIC, an FPGA, a radio-frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.
The memory/storage devices 920 may include main memory, disk storage, or any suitable combination thereof. The memory/storage devices 920 may include, but are not limited to, any type of volatile or nonvolatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), Flash memory, solid-state storage, etc.
The communication resources 930 may include interconnection or network interface components or other suitable devices to communicate with one or more peripheral devices 904 or one or more databases 906 via a network 908 . For example, the communication resources 930 may include wired communication components (e.g., for coupling via USB), cellular communication components, NFC components, Bluetooth® (or Bluetooth® Low Energy) components, Wi-Fi® components, and other communication components.
Instructions 950 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least any of the processors 910 to perform any one or more of the methodologies discussed herein. The instructions 950 may reside, completely or partially, within at least one of the processors 910 (e.g., within the processor's cache memory), the memory/storage devices 920 , or any suitable combination thereof. Furthermore, any portion of the instructions 950 may be transferred to the hardware resources 900 from any combination of the peripheral devices 904 or the databases 906 . Accordingly, the memory of processors 910 , the memory/storage devices 920 , the peripheral devices 904 , and the databases 906 are examples of computer-readable and machine-readable media.
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| 20,250,204
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[
"MIAO, HONGLEI"
] |
APPLE INC
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70919118
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US-12216515-B2
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US-202318497443-A
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US
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B2
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Current measurement for power converter circuits
|
A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.
|
What is claimed is:
1. An apparatus comprising:
a power converter configured to generate a regulated supply voltage, wherein the power converter includes a first phase circuit configured to generate a first demand current, wherein the first phase circuit includes:
a current sampling circuit configured to generate a stream of digital samples of the first demand current;
a first memory circuit configured to store a plurality of data words, wherein a given one of the plurality of data words comprises a plurality of digital samples; and
a trigger circuit configured to generate a trigger signal in response to detecting a trigger event in the stream of digital samples; and
a sample circuit coupled to the first phase circuit, wherein the sample circuit includes:
a control circuit configured to generate a timestamp value in response to generation of the trigger signal and further configured to generate an address indicative of a location in the first memory circuit storing a particular one of the plurality of digital samples corresponding to the trigger event.
2. The apparatus of claim 1 , wherein the current sampling circuit includes:
a comparator configured to generate a demand current signal based on comparing a reference voltage to the regulated supply voltage; and
an analog-to-digital converter circuit configured to, in accordance with a clock signal, generate the stream of digital samples based on the demand current signal.
3. The apparatus of claim 2 , wherein the first phase circuit further includes:
a first-in first-out (FIFO) memory configured to receive and store digital samples of the stream of digital samples to form the plurality of digital samples, and, in response to determining all storage locations of the FIFO are full, transfer the plurality of digital samples to the first memory circuit as a given one of the plurality of data words; and
a pointer circuit configured to generate a pointer to a location in the FIFO memory in which a next one of the plurality of digital samples is to be stored.
4. The apparatus of claim 2 , wherein the sample circuit further includes a second memory circuit configured to store timestamp values corresponding to trigger events indicated by assertions of the trigger signal.
5. The apparatus of claim 2 , wherein the sample circuit further includes a register circuit configured to store trigger information received from a communication bus, wherein the trigger information is usable to initiate the trigger event.
6. The apparatus of claim 1 , wherein the power converter includes a plurality of phase circuits including the first phase circuit, and wherein the power converter further includes a second control circuit configured to activate selected ones of the plurality of phase circuits based on the first demand current.
7. The apparatus of claim 6 , further comprising a communication bus coupled to the power converter, wherein the power converter is configured to generate a power control command in response to a determination that the first demand current exceeds a threshold for one or more of the plurality of phase circuits, and further configured to transmit the power control command onto the communication bus.
8. The apparatus of claim 7 , further comprising a load circuit coupled to receive the regulated supply voltage from the power converter, and further configured to receiver the power control command via the communication bus, wherein the load circuit is further configured to modify one or more operating parameters in response to receiving the power control command.
9. The apparatus of claim 8 , wherein the one or more operating parameters include a frequency of a clock signal at which the load circuit operates.
10. A method comprising:
generating, using a power converter, a regulated supply voltage;
generating, using a first phase circuit of the power converter, a first demand current;
generating, using a current sampling circuit of the first phase circuit, a stream of digital samples of the first demand current;
storing, in a first memory circuit, a plurality of data words, wherein a given one of the plurality of data words comprises a plurality of digital samples;
generating a trigger signal, using a trigger circuit, in response to detecting a trigger event in the stream of digital samples;
generating, using a sample circuit and in response to the generation of the trigger signal, a timestamp value; and
generating, using the sample circuit, an address indicative of a location in the first memory circuit storing a particular one of the plurality of digital samples corresponding to the trigger event.
11. The method of claim 10 , further comprising:
generating, using a comparator of the sampling circuit, a demand current signal based on a comparison of the regulated supply voltage to a reference voltage; and
generating, using the demand current signal and an analog-to-digital converter, the stream of digital samples.
12. The method of claim 11 , further comprising:
storing in a first-in first-out (FIFO) memory, digital samples of the stream of digital samples to form the plurality of digital samples,
transferring the plurality of digital samples to the first memory circuit as a given one of the plurality of data words in response to determining all storage locations of the FIFO are full, transfer; and
generating, using a pointer circuit, a pointer to a location in the FIFO memory in which a next one of the plurality of digital samples is to be stored.
13. The method of claim 11 , further comprising storing, in a second memory circuit, timestamp values corresponding to trigger events indicated by assertions of the trigger signal.
14. The method of claim 11 , further comprising storing, in a register circuit, trigger information received from a communication bus, wherein the trigger information is usable to initiate the trigger event.
15. The method of claim 10 , further comprising conveying, from the power converter to a load circuit coupled to receive the regulated supply voltage, a power command.
16. The method of claim 15 , further comprising conveying the power command via a communication bus.
17. The method of claim 16 , further comprising the load circuit adjusting one or more operating parameters in response to receiving the power command.
18. A system comprising:
a load circuit;
a power converter configured to provide a regulated supply voltage to the load circuit, wherein the power converter includes a plurality of phase circuits, wherein ones of the plurality of phase circuits are configured to generate a demand current, and wherein a given one of the plurality of phase circuits includes:
a current sampling circuit configured to generate a stream of digital samples of the demand current;
a first memory circuit configured to store a plurality of data words, wherein a given one of the plurality of data words comprises a plurality of digital samples; and
a trigger circuit configured to generate a trigger signal in response to detecting a trigger event in the stream of digital samples; and
a sample circuit coupled to the plurality of phase circuits, wherein the sample circuit includes:
a first control circuit configured to generate a timestamp value in response to generation of the trigger signal by at least one of the plurality of phase circuits, and further configured to generate and address indicative of a location in the first memory circuit storing a particular one of the plurality of digital samples corresponding to the trigger event.
19. The system of claim 18 , wherein, in response to the trigger event, the power converter is configured to convey a power command to the load circuit, and wherein the load circuit is configured to, in response to receiving the power command, adjust one or more operating parameters.
20. The system of claim 18 , wherein the power converter includes a second control circuit configured to activate and deactivate ones of the plurality of phase circuits based on the demand current.
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PRIORITY CLAIM
The present application is a continuation of U.S. application Ser. No. 17/211,527, entitled “Current Measurement for Power Converter Circuits,” filed Mar. 24, 2021, the disclosure of which is incorporated by reference herein in its entirety.
BACKGROUND
Technical Field
This disclosure relates to power management in computer systems, and more particularly to voltage regulator circuit operation.
Description of the Related Art
Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include processors or processor cores configured to execute software or program instructions. Additionally, the circuit blocks may include memory circuits, mixed-signal or analog circuits, and the like.
In some computer systems, the circuit blocks may be designed to operate using different power supply voltage levels. For example, in some computer systems, power management circuits (also referred to as “power management units”) may generate and monitor various power supply signals.
Power management circuits often include one or more power converter circuits configured to generate regulator voltage levels on respective power supply signal lines using a voltage level of an input power supply signal. Such converter circuits may employ multiple reactive circuit elements, such as inductors, capacitors, and the like.
SUMMARY OF THE EMBODIMENTS
Various embodiments for a power converter circuit are disclosed. Broadly speaking, a phase circuit included in the power converter circuit is configured to generate a demand current using a comparison of a voltage level of a regulated power supply node and a reference voltage. The phase circuit is further configured to adjust the voltage level of the regulated power supply node using the demand current. Additionally, the phase circuit is configured to digitize the demand current to create a stream of current samples, and store the stream of current samples in a first memory circuit. A sample circuit included in the power converter circuit is configured, in response to a detection of a trigger event, generate timestamp information that includes an address corresponding to a location in the first memory circuit where a particular current sample that corresponds to the trigger event it stored, and store the timestamp information in a second memory circuit. By storing the stream of current samples along with timestamps identifying when particular events occur, real-time behavior of the power converter circuit may be analyzed and changes in the operating parameters of the power converter circuit may be made. The stored data may also be used to improve subsequent designs of the power converter circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an embodiment of a power converter circuit for a computer system.
FIG. 2 illustrates a block diagram of a phase circuit included in a power converter circuit.
FIG. 3 illustrates a block diagram of an embodiment of a sample circuit for a power converter circuit.
FIG. 4 illustrates a block diagram of an embodiment of a system including a power management unit.
FIG. 5 illustrates a flow diagram depicting an embodiment of another method for operating a power converter circuit.
FIG. 6 is a block diagram of an embodiment of a computer system.
FIG. 7 is a block diagram of an embodiment of a system.
DETAILED DESCRIPTION OF EMBODIMENTS
Computer systems may include multiple circuit blocks configured to perform specific functions. Such circuit blocks may be fabricated on a common substrate and may employ different power supply voltage levels. Power management units (commonly referred to as “PMUs”) may include multiple power converter or voltage regulator circuits configured to generate regulated voltage levels for various power supply signals. Such voltage regulator circuits may employ both passive circuit elements (e.g., inductors, capacitors, etc.) as well as active circuit elements (e.g., transistors, diodes, etc.).
Many power converter and voltage regulator circuits employ a control loop, which senses a particular characteristic of a regulated power supply signal and compares a value of the particular characteristic to a threshold value. Based on results of the comparison, charging or discharging of a load circuit by a power converter or voltage regulator circuit may be altered. One characteristic that is often employed is a demand current, that is derived from the difference between a voltage level of a regulated power supply node and a reference voltage level. The demand current represents an altered output current the power converter or voltage regulator will ultimately resolve.
In many computer systems, it is desirable to know how much current a power converter circuit is delivering to a load circuit at any given time. Such knowledge can be used to adjust operation of the power converter circuit (e.g., adding or shedding a phase circuit), overall system operation, or may be used for analysis to improve subsequent power converter and system circuit designs. In some cases, information regarding the load current can be used to allocate power to different load circuits to optimize run-time performance of the overall system. In other cases, the information regarding the load current can be to determine if the power converter circuit is close to exceeding a maximum output rating, so that overall system performance can be adjusted accordingly.
To measure the current delivered by a power converter circuit, small sensor resistors (referred to as “sense resistors”) whose values are in the milliohm range, may be placed in series in power supply nodes between the power converter circuit and the load circuit. The voltage drops across such resistors can be used to determine the current being delivered by the power converter circuit. The quality of results using sense resistors is limited due to the bandwidth of measurements that can be made across the resistors. Moreover, the sense resistor solution makes it difficult to determine how changes in power state and the execution of different software or application programs affect the current load on the power converter circuit. Sense resistors can also compromise the performance of the power delivery solution, thereby limiting their use in some applications. Techniques described in the present disclosure allow for measuring the current delivered by a power converter circuit in real time without use of sense resistors, as well as marking the measured current data with time information to match changes in the current to events within a computer system.
A block diagram depicting an embodiment of a power converter circuit is depicted in FIG. 1 . As illustrated, power converter circuit 100 includes phase circuit 101 and sample circuit 102 . Phase circuit 101 includes memory circuit 103 , while sample circuit 102 includes memory circuit 104 .
Phase circuit 101 is configured to generate demand current 106 using a comparison of a voltage level of regulated power supply node 105 and reference voltage level 109 . In various embodiments, phase circuit 101 is further configured to adjust the voltage level of regulated power supply node 105 using the demand current.
Phase circuit 101 is also configured to digitize demand current 106 to create a stream of current samples 107 , and to store stream of current samples 107 in memory circuit 103 . In various embodiments, memory circuit 103 may be implemented as a static random-access memory (SRAM) or any other suitable type of memory circuit.
Sample circuit 102 is configured, in response to a detection of trigger event 110 , to generate timestamp information 108 that includes a pointer to a location in the first memory circuit where a particular current sample of stream of current samples 107 that corresponds to the trigger event is stored. In various embodiments, sample circuit 102 is further configured to store timestamp information 108 in memory circuit 104 . In various embodiments, memory circuit 104 may be implemented as a SRAM or any other suitable type of memory circuit. During data retrieval, timestamp information 108 stored in memory circuit 104 can be used to access particular locations in memory circuit 103 .
By storing the stream of current samples 107 along with timestamp information 108 , current samples relating to specific events (e.g., a change in power state) may be retrieved from memory circuit 103 using timestamp information 108 . The retrieved current samples can be used to determine power consumption, or they may be used to adjust operating parameters (e.g., clock frequency) of phase circuit 101 . Since the stream of current samples 107 is gathered in real time, the behavior of demand current 106 can be analyzed prior to certain events, such as a sudden drop in the voltage level of regulated power supply node 105 .
In various embodiments, phase circuit 101 may be part of a buck converter where phase circuit 101 is coupled to regulated power supply node via an inductor. In such cases, in order to modify the voltage level of regulated power supply node 105 , phase circuit 101 can be enabled by a timing or clock signals. Once enabled, phase circuit 101 is configured to source current to regulated power supply node 105 . A duration of how long current is sourced to regulated power supply node 105 is determined based on current sensed through the inductor using a process commonly referred to as pulse width modulation or “PWM.”
In other cases, phase circuit 101 may employ pulse frequency modulation or “PFM” to determine the duration of sourcing current to regulated power supply node 105 . When PFM is employed, the timing of the PFM event, along with its duration, should be stored in memory circuits 103 and 104 . Rather than increasing the size of memory circuit 103 to accommodate additional bits in the stream of current samples 107 that denote PWM versus PFM operation, an encoding scheme is applied to the stream of current samples 107 . To encode entry into PFM mode, a particular sequence of current samples in the stream of current samples 107 may be employed. In a similar fashion, another sequence of current sample in the stream of current samples 107 may be used. By using such dedicated sequences, a start and a stop of PFM mode can be identified for subsequent processing.
It is noted that the dedicated sequences may employ a dummy current sample that corresponds to an end of a given dedicated sequence. In some cases, the dummy current sample may be a set of bits of a particular logic value. For example, the dummy current sample may include multiple logical-0 values that correspond to a zero current. The use of such a dummy current sample can present problems when attempting to determine an amount of charge transferred to a load during PFM operation. Unlike when phase circuit 101 is operating in PWM mode, in which integration of the stream of current samples 107 leads to an amount of transferred charge, during PFM operation, such integration will yield a lower value due to the dummy current samples used to encode the start and stop of the PFM event. To remediate this problem, when a PFM is detected, additional charge is added to account for the deficit in the charge determined by integrating the current samples. In various cases, the added amount of charge may be determined empirically based on characteristics of a given power converter circuit. Many other encoding schemes may be employed to uniquely represent the PFM event, some of which may include reducing the charge to account for a surplus of charge defined by the chosen encoding scheme.
Turning to FIG. 2 , a block diagram of an embodiment of phase circuit 101 is depicted. As illustrated, phase circuit 101 includes comparator circuit 201 , analog-to-digital converter circuit 202 , first-in first-out circuit 203 , pointer circuit 204 , trigger circuit 205 and memory circuit 103 .
Comparator circuit 201 is configured to generate demand current 206 using the voltage level of regulated power supply node 105 and reference voltage level 109 . In various embodiments, comparator circuit 201 is configured to generate demand current 206 such that a magnitude of demand current 206 is related to a difference between the voltage level of regulated power supply node 105 and reference voltage level 109 and may be proportional to the output current that will flow in regulated power supply node 105 . In some embodiments, comparator circuit 201 may be implemented as a differential amplifier circuit or other suitable amplifier circuit.
Analog-to-digital converter circuit 202 is configured to generate a stream of current samples 107 using demand current 206 and clock signal 210 . In various embodiments, analog-to-digital converter circuit 202 may be implemented as a flash analog-to-digital converter circuit configured to sample demand current during active periods of clock signal 210 . It is noted that in some embodiments, comparator circuit 201 and analog-to-digital converter circuit 202 may be implemented as a single circuit block configured to implement the functions described above.
First-in first-out circuit 203 is configured to store different current samples of the stream of current samples 107 into corresponding locations within first-in first-out circuit 203 . The location into which a given current sample is stored is controlled by pointer 207 , which is generated by pointer circuit 204 . In response to a determination that all storage locations are occupied, first-in first-out circuit 203 is configured to transfer the stored current samples to memory circuit 103 as a data word, so that current samples can be stored in memory circuit 103 at a lower frequency than what is generated by analog-to-digital converter circuit 202 . In various embodiments, first-in first-out circuit 203 may be implemented using multiple latch circuits, flip-flop circuits, or any other suitable type of storage circuit.
Pointer circuit 204 is configured to generate pointer 207 using clock signal 211 . In various embodiments, to generate pointer 207 , pointer circuit 204 is configured to modify a value of pointer 207 at the conclusion of an active period of clock signal 211 . In some cases, to modify the value of pointer 207 , pointer circuit 204 may be further configured to increment the value of pointer 207 . A given value of pointer 207 corresponds to a storage location within first-in first-out circuit 203 . Once a maximum value for pointer 207 has been reached, pointer circuit 204 is configured to reset to a minimum value. In various embodiments, pointer circuit 204 may be implemented as a counter circuit or other suitable sequential logic circuit. A frequency of clock signals 210 is selected to capture transients on demand current 206 of particular durations. Rather than running the rest of the circuitry at such a frequency, the stream of current samples 107 is converted to data words that can be processed at low frequencies. As such, in various embodiments, a frequency of clock signal 211 is less than a frequency of clock signal 210 .
Trigger circuit 205 is configured to generate trigger signal 208 using the stream of current samples 107 and pointer 207 . In various embodiments, trigger circuit 205 is configured to generate trigger signal 208 in response to various conditions. For example, the various conditions can include when a particular current sample of the stream of current samples 107 exceeds a threshold value, or when a moving average of the stream of current samples 107 exceeds a different threshold value. Alternatively, trigger circuit 205 is configured to track changes in the stream of current samples 107 and generate trigger signal 208 in response to a rising or falling transition in the stream of current samples exceeding respective threshold values. In some cases, the various threshold values, or other criteria to use may be programable by storing values in control-status registers (CSRs).
In various embodiments, trigger signal 208 may include multiple bits. Some of the bits may encode information indicative that a trigger event has occurred. Other bits may encode a phase relationship between the a given current sample and clock signal 211 .
Turning to FIG. 3 , a block diagram of an embodiment of sample circuit 102 is depicted. As illustrated, sample circuit 102 includes control circuit 301 , register circuit 302 , and memory circuit 104 .
Control circuit 301 is configured to generate timestamp information 108 using trigger signal 208 . In various embodiments, control circuit 301 may additionally use clock signal 211 and pointer 207 to generate timestamp information 108 . Pointer 207 includes a phase relationship of the stream of current samples 107 to clock signal 211 . Using this information, control circuit 301 can generate an address value of where a current sample that occurred at the time of the trigger is located in memory circuit 103 that can be included in a timestamp. Once a timestamp has been generated, control circuit 301 may generate data 305 , address 306 , and clock signal 307 , which are used to store the timestamp in memory circuit 104 .
In addition to using trigger signal 208 to generate timestamp information 108 , control circuit 301 may additionally use control signal 303 and contents of register circuit 302 to generate other timestamps for storage into memory circuit 104 . In some cases, control circuit 301 may generate and store a timestamp in response to particular values being written into particular ones of register circuits 302 . Additionally, control circuit 301 may be configured to generate and store a timestamp in response to an activation of control signal 303 .
In various embodiments, control signal 303 may be connected to a general-purpose input-output (GPIO) bus that is connected to board-level hardware of a computer system. Using control signal 303 allows such board-level hardware to initiate triggers in order to capture demand current 106 during various board-level events. Using control signal 303 , start timestamps, stop timestamps, or toggle timestamps for recording may be generated. In various embodiments, different functions may be assigned to a rising edge or a falling edge of control signal 303 .
In various embodiments, control circuit 301 may be implemented as a microcontroller, state machine, or other suitable sequential logic circuit. It is noted, that control circuit 301 is configured to employ clock signal 304 to operate clocked circuit elements within control circuit 301 . In various embodiments, a frequency of clock signal 304 is less than a frequency of clock signal 211 .
Register circuit 302 may include one or more storage circuits configured to receive and store trigger information. For example, register circuit 302 may include a first register that may be written with a particular value via a communication bus. When the first register is written to the particular value, a trigger event is initiated and a timestamp generated. Initiating a trigger in this fashion allows time synchronization back to a program counter and a state of an SoC. This can provide insight into how processor load or particular application of software programs affect current demand with power converter circuit 100 . It is noted that different values written into the first register circuit may correspond to different triggers and that the different values may be encoded into the corresponding timestamp. In some cases, writing one value into the first register may generate a timestamp that indicates the start of a recording period of the stream of current samples 107 , and writing another value may generate a timestamp that indicates the end of the recording period.
Register circuit 302 may also include a second register that is written to various values by a microcontroller included in a power management unit (PMU). The microcontroller can generate more complex triggers similar to what might be employed in a logic analyzer. Different values written into the second register circuit may correspond to different triggers. Such values may be encoded in corresponding timestamp. Like the first register, writing one value into the second register may generate a timestamp that indicates the start of a recording period of the stream of current samples 107 , and writing another value may generate a timestamp that indicates the end of the recording period.
Memory circuit 104 is configured to store timestamp information. As such, memory circuit 104 may be referred to as a “timestamp memory.” In various embodiments memory circuit 104 is configured to store, using clock signal 307 , data 305 at a location corresponding to address 306 . In various embodiments, memory circuit 104 is coupled to memory bus 209 and can be accessed by a controller or other circuit coupled to memory bus. For example, a controller may access memory circuit 104 to retrieve information relating to a given timestamp. Using that information, the controller can access memory circuit 103 to retrieve the current information associated with a given timestamp.
In some cases, once a telemetry test has been completed, memory circuit 104 must be cleared to prevent old timestamp data from interfering with new timestamp data. As used herein, a telemetry test refers to the generation of one or more timestamps used to record current samples over a given period of time. In some cases, the period of time may be limited by a storage capacity of memory circuit 104 . To clear memory circuit 104 , control circuit 301 is configured to sequentially write particular value (e.g., logical-0) to address locations in memory circuit 104 .
In some computer systems, power converter circuits may be located on separate integrated circuits from their load circuits. A block diagram of an embodiment of such a computer system is depicted in FIG. 4 . As illustrated, computer system 400 includes power converter circuit 401 and load circuit 402 . In various embodiments, power converter circuit 401 may be located on a different integrated circuit than load circuit 402 , which may include processor circuits, memory circuits, analog circuits, etc. In some cases, load circuit 402 may be a system-on-a-chip (SoC).
Power converter circuit 401 includes phase circuits 403 A and 403 B, sample circuit 404 , and control circuit 411 . In various embodiments, phase circuits 403 A and 403 B may correspond to phase circuit 101 as depicted in FIG. 1 . As illustrated, phase circuit 403 A includes memory circuit 405 A, and phase circuit 403 B includes memory circuit 405 B. In some embodiments, memory circuits 405 A and 405 B may be telemetry memories and may correspond to memory circuit 103 as depicted in FIG. 1 . Power converter circuit 401 is configured to generate a particular voltage level on regulated power supply node 406 for load circuit 402 . Although only two phase-circuits are depicted in the embodiment of FIG. 4 , in other embodiments, any suitable number of phase circuits may be employed.
Control circuit 411 is configured to generate control signals 412 , which may, in various embodiments, control the activation of phase circuits 403 A and 403 B. In some cases, control circuit 411 may be configured to activate different ones of phase circuits 403 A and 403 B based on an amount of current demanded by load circuit 402 . Control circuit 411 may be implemented, in various embodiments, as a state machine or any other suitable sequential logic circuit.
Memory circuit 405 A is coupled to memory circuit 405 B via bus 413 . In various embodiments, bus 413 may include multiple wires for address, data, and control signals. By coupling the telemetry memory circuits of phase circuits 403 A and 403 B together as depicted in FIG. 4 , the overall storage capacity available to store current samples increases. The increased storage capacity allows for more data to be recorded for a given trigger event. In various embodiments, memory circuit 405 A and 405 B may occupy different address ranges within an overall telemetry memory address space. Alternatively, memory circuits 405 A and 405 B may employ separate enable signals that are treated as a most-significant address bit.
Sample circuit 404 includes memory circuit 410 . In various embodiments, sample circuit 404 may correspond to sample circuit 102 , and memory circuit 410 may correspond to memory circuit 104 as depicted in FIG. 1 . In some embodiments, memory circuit 410 is configured to store multiple timestamps relating to different sets of current samples stored in memory circuits 405 A and 405 B. In some cases, additional information corresponding to different operating modes may be stored in memory circuit 401 or memory circuits 405 A and 405 B. For example, special symbols may be stored along with the current samples to denote how many phase circuits where operating when the data was gathered. Such special symbols may be particular patterns of bits that would otherwise not occur within the current samples. For example, repeated alternating minimum and maximum values may be used as a special symbol. In some cases, a number of times the minimum/maximum pattern is repeated may correspond to a number of phase circuits that were active was the current samples were gathered.
Power converter circuit 401 is also configured to generate power control signal 407 . In various embodiments, power converter circuit 401 is configured to activate power control signal 407 in response to a determination that one or both of corresponding demand currents associated with phase circuits 403 A and 403 B have exceeded a threshold value. In response to an activation of power control signal 407 , load circuit 402 is configured to modify one or more operating parameters (e.g., clock frequency) to reduce power consumption. It is noted that although a single power control signal is depicted in the embodiment of FIG. 4 , in other embodiments, power converter circuit 401 may generate multiple power control signals.
Both power converter circuit 401 and load circuit 402 are coupled to communication bus 408 , which may be used to transmit messages between different circuit blocks included in a computer system. Although only two circuit blocks are depicted as being coupled to communication bus 408 , in other embodiments, any suitable number of circuit blocks may be coupled to communication bus 408 .
In addition to, or in lieu of, power control signal 407 , power converter circuit 401 is configured to generate power control command 409 , in response to a determination that one or both of corresponding demand currents associated with phase circuits 403 A and 403 B have exceeded a threshold value. Power converter circuit 401 is further configured to transmit power control command 409 to load circuit 402 via communication bus 408 . In response to receiving power control command 409 via communication bus 408 , load circuit 402 is configured to modify one or more operating parameters to reduce power consumption. It is noted that given communication traffic on communication bus 408 , there may be a latency between the time that power converter circuit 401 generates power control command 409 and the time that load circuit 402 responds.
Turning to FIG. 5 , a flow diagram depicting an embodiment of a method for operating a power converter circuit is illustrated. The method, which may be applied to power converter circuit 100 , begins in block 501 .
The method includes performing, by a power converter circuit, a comparison of a reference voltage and a voltage level of a regulated power supply node to generate a demand current (block 502 ). In various embodiments, the power converter circuit may include a plurality of phase circuits. The method may further include adjusting operating parameters of one or more of the plurality of phase circuits using data retrieved from the first memory circuit and the second memory circuit.
The method also includes adjusting the voltage level of the regulated power supply node based on the demand current (block 503 ). In various embodiments, adjusting the voltage level of the regulated power supply node includes sourcing a current to the regulated power supply node via an inductor coupled between the power converter circuit and the regulated power supply node.
The method further includes sampling the demand current to generate a stream of current samples (block 504 ). In some embodiments, a given current sample of the stream of current samples includes a plurality of bits, whose values encode a magnitude of the demand current at a corresponding time point.
The method also includes storing the stream of current samples in a first memory circuit (block 505 ). In various embodiments, storing the stream of current samples includes combining a given number of current samples to form a data word and storing the data word in the first memory circuit. In other embodiments, combining the given number of samples to form the data word includes storing a subset of the stream of current samples into corresponding locations in a first-in first-out circuit. In some embodiments, storing the data word includes storing the data word into the first memory circuit in response to determining the first-in first-out circuit is full, and incrementing a pointer in response to storing the data word in the first memory circuit.
The method further includes, in response to detecting a trigger event, generating timestamp information that includes a pointer to a location in the first memory where a particular current sample that correspond to the trigger event is stored (block 506 ). In various embodiments, the method includes generating the timestamp information using a value of the pointer when the trigger event occurs.
The method also includes, in response to detecting the trigger event, storing the timestamp information in a second memory circuit (block 507 ). In various embodiments, the method further includes detecting the trigger event evening in response to determining that a moving average of the stream of current samples exceeds a threshold value. In other embodiments, the method also includes, in response to completing a telemetry test, clearing the second memory circuit, wherein clearing the second memory circuit includes sequentially storing logical-0 values at each address location in the second memory circuit. The method concludes in block 508 .
A block diagram of a computer system is illustrated in FIG. 6 . In the illustrated embodiment, computer system 600 includes power management unit 601 , processor circuit 602 , memory circuit 603 , and input/output circuits 604 , each of which is coupled to power supply node 605 . In various embodiments, computer system 600 may be a system-on-a-chip (SoC) and/or be configured for use in a desktop computer, server, or in a mobile computing application such as, e.g., a tablet, laptop computer, or wearable computing device.
Power management unit 601 includes power converter circuit 100 which is configured to generate a regulated voltage level on power supply node 606 in order to provide power to processor circuit 602 , input/output circuits 604 , and memory circuit 603 . Although power management unit 601 is depicted as including a single power converter circuit, in other embodiments, any suitable number of power converter circuits may be included in power management unit 601 , each configured to generate a regulated voltage level on a respective one of multiple power supply nodes included in computer system 600 .
Processor circuit 602 may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, processor circuit 602 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).
Memory circuit 603 may, in various embodiments, include any suitable type of memory such as a Dynamic Random-Access Memory (DRAM), a Static Random-Access Memory (SRAM), a Read-Only Memory (ROM), an Electrically Erasable Programmable Read-only Memory (EEPROM), or a non-volatile memory, for example. It is noted that although a single memory circuit is illustrated in FIG. 6 , in other embodiments, any suitable number of memory circuits may be employed.
Input/output circuits 604 may be configured to coordinate data transfer between computer system 600 and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, input/output circuits 604 may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol.
Input/output circuits 604 may also be configured to coordinate data transfer between computer system 600 and one or more devices (e.g., other computing systems or integrated circuits) coupled to computer system 600 via a network. In one embodiment, input/output circuits 604 may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet, for example, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, input/output circuits 604 may be configured to implement multiple discrete network interface ports.
Turning now to FIG. 7 , various types of systems that may include any of the circuits, devices, or systems discussed above are illustrated. System or device 700 , which may incorporate or otherwise utilize one or more of the techniques described herein, may be utilized in a wide range of areas. For example, system or device 700 may be utilized as part of the hardware of systems such as a desktop computer 710 , laptop computer 720 , tablet computer 730 , cellular or mobile phone 740 , or television 750 (or set-top box coupled to a television).
Similarly, disclosed elements may be utilized in a wearable device 760 , such as a smartwatch or a health-monitoring device. Smartwatches, in many embodiments, may implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device may also be designed solely to perform health-monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to an emergency medical service, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or a helmet designed to provide computer-generated reality experiences such as those based on augmented and/or virtual reality, etc.
System or device 700 may also be used in various other contexts. For example, system or device 700 may be utilized in the context of a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service 770 . Still further, system or device 700 may be implemented in a wide range of specialized everyday devices, including devices 780 commonly found in the home such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Elements may also be implemented in various modes of transportation. For example, system or device 700 could be employed in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles 790 .
The applications illustrated in FIG. 7 are merely exemplary and are not intended to limit the potential future applications of disclosed systems or devices. Other example applications include, without limitation: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.
The present disclosure includes references to “embodiments,” which are non-limiting implementations of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. Not all embodiments will necessarily manifest any or all of the potential advantages described herein.
Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.
Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to include any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
For example, while the appended dependent claims are drafted such that each depends on a single other claim, additional dependencies are also contemplated. Where appropriate, it is also contemplated that claims drafted in one statutory type (e.g., apparatus) suggest corresponding claims of another statutory type (e.g., method).
Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Public notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how to interpret claims that are drafted based on this disclosure.
References to the singular forms such “a,” “an,” and “the” are intended to mean “one or more” unless the context clearly dictates otherwise. Reference to “an item” in a claim thus does not preclude additional instances of the item.
The word “may” is used herein in a permissive sense (i.e., having the potential to, being able to) and not in a mandatory sense (i.e., must).
The terms “comprising” and “including,” and forms thereof, are open-ended and mean “including, but not limited to.”
When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the other hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.
A recitation of “w, x, y, or z, or any combination thereof” or “at least one of w, x, y, and z” is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrasings cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “at least one of . . . w, x, y, and z” thus refers to at least one of element of the set [w, x, y, z], thereby covering all possible combinations in this list of options. This phrase is not to be interpreted to require that there is at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.
Various “labels” may proceed nouns in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. The labels “first,” “second,” and “third” when applied to a particular feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.
Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.
The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function. This unprogrammed FPGA may be “configurable to” perform that function, however.
Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.
The phrase “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”
The phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.
| 20,231,030
| 20,250,204
| 20,250,204
| 20,210,324
|
[
"SEARLES, SHAWN",
"GOZZINI, FABIO",
"PANT, SANJAY",
"SODHI, INDER M."
] |
APPLE INC
|
[
{
"code": "G01R15/146",
"inventive": true,
"first": false,
"tree": []
},
{
"code": "G11C7/1096",
"inventive": false,
"first": false,
"tree": []
},
{
"code": "G06F1/26",
"inventive": true,
"first": false,
"tree": []
},
{
"code": "G01R19/2506",
"inventive": false,
"first": false,
"tree": []
},
{
"code": "G11C5/147",
"inventive": false,
"first": false,
"tree": []
},
{
"code": "G06F1/26",
"inventive": true,
"first": true,
"tree": []
},
{
"code": "G05F1/46",
"inventive": true,
"first": true,
"tree": []
},
{
"code": "G11C7/1096",
"inventive": false,
"first": false,
"tree": []
},
{
"code": "G01R15/146",
"inventive": true,
"first": false,
"tree": []
},
{
"code": "G06F1/26",
"inventive": true,
"first": true,
"tree": []
}
] |
83364678
|
US-12217060-B1
|
US-202318176457-A
|
US
|
B1
|
Instruction fusion
| "Techniques are disclosed that relate to executing pairs of instructions. A processor may include fu(...TRUNCATED)
| "What is claimed is: \n \n 1. A processor, comprising:\n fusion detector circuitry configu(...TRUNCATED)
| "CROSS-REFERENCE TO RELATED APPLICATIONS \n The present application claims priority to U.S. Prov(...TRUNCATED)
| 20,230,228
| 20,250,204
| 20,250,204
| 20,220,923
| ["SPADINI, FRANCESCO","SRINIVASA, SKANDA K.","PANDA, REENA","MOKRZYCKI, BRIAN T.","JIA, HAOYAN","JIN(...TRUNCATED)
|
APPLE INC
| [{"code":"G06F9/30181","inventive":true,"first":false,"tree":[]},{"code":"G06F9/3001","inventive":tr(...TRUNCATED)
|
94392042
|
US-12219003-B2
|
US-202318236943-A
|
US
|
B2
|
Multi-path connection management
| "A device implementing a system for multipath connection management may include first and second loc(...TRUNCATED)
| "What is claimed is: \n \n 1. A method comprising:\n attempting, by a device, to establish(...TRUNCATED)
| "CROSS REFERENCE TO RELATED APPLICATIONS \n This application is a continuation of U.S. patent ap(...TRUNCATED)
| 20,230,822
| 20,250,204
| 20,250,204
| 20,190,909
| ["POLLACK, DANIEL B.","BHOOMA, Padmavathy","ZHANG, Jingyao","LU, CHIEH","SANTHANAM, KARTHICK","GARRI(...TRUNCATED)
|
APPLE INC
| [{"code":"H04L69/167","inventive":true,"first":false,"tree":[]},{"code":"H04L1/0002","inventive":tru(...TRUNCATED)
|
74851354
|
US-12219545-B2
|
US-202318474692-A
|
US
|
B2
|
Multi-TRP beam indication using TCI state
| "A user equipment (UE) is configured to use multiple beams for transmission or reception. The UE rec(...TRUNCATED)
| "What is claimed: \n \n 1. A user equipment (UE), comprising:\n a transceiver configured t(...TRUNCATED)
| "BACKGROUND \n In 5G new radio (NR) wireless communications, the 5G NR network may utilize multi(...TRUNCATED)
| 20,230,926
| 20,250,204
| 20,250,204
| 20,210,406
| ["ZHANG, YUSHU","YE, CHUNXUAN","ZHANG, DAWEI","SUN, HAITONG","HE, HONG","NIU, HUANING","OTERI, OGHEN(...TRUNCATED)
|
APPLE INC
| [{"code":"H04L5/0053","inventive":true,"first":false,"tree":[]},{"code":"H04L5/0048","inventive":tru(...TRUNCATED)
|
83545131
|
US-12217342-B1
|
US-202217659792-A
|
US
|
B1
|
Devices, methods and graphical user interfaces for goal-based animation
| "A computer-generated environment may include a virtual agent and a plurality of targets. Movements (...TRUNCATED)
| "The invention claimed is: \n \n 1. A method comprising:\n at an electronic device in comm(...TRUNCATED)
| "CROSS-REFERENCE TO RELATED APPLICATIONS \n This application claims the benefit of U.S. Provisio(...TRUNCATED)
| 20,220,419
| 20,250,204
| 20,250,204
| 20,210,610
|
[
"DUQUESNE, GREGORY",
"CACHELIN, ARNOLD H."
] |
APPLE INC
| [{"code":"G06T11/00","inventive":true,"first":false,"tree":[]},{"code":"G06T2200/24","inventive":fal(...TRUNCATED)
|
94392098
|
US-12216254-B2
|
US-202418412914-A
|
US
|
B2
|
Wide field of view five element lens system
| "Lens systems are described that may be used in small form factor cameras. An imaging lens system ma(...TRUNCATED)
| "What is claimed is: \n \n 1. A lens system, comprising:\n a plurality of optical elements(...TRUNCATED)
| "This application is a continuation of U.S. patent application Ser. No. 17/175,431, filed Feb. 12, 2(...TRUNCATED)
| 20,240,115
| 20,250,204
| 20,250,204
| 20,171,026
|
[
"YAO, YUHONG"
] |
APPLE INC
| [{"code":"G02B9/60","inventive":true,"first":false,"tree":[]},{"code":"G02B7/09","inventive":false,"(...TRUNCATED)
|
66244858
|
US-12219720-B2
|
US-202318244287-A
|
US
|
B2
|
Glass enclosure
| "A handheld computing device that includes an enclosure having structural walls formed from a glass (...TRUNCATED)
| "What is claimed is: \n \n 1. A portable electronic device comprising:\n an enclosure comp(...TRUNCATED)
| "CROSS-REFERENCE TO RELATED APPLICATION(S) \n This application is a continuation patent applicat(...TRUNCATED)
| 20,230,910
| 20,250,204
| 20,250,204
| 20,100,917
|
[
"PREST, CHRISTOPHER",
"SANFORD, EMERY A."
] |
APPLE INC
| [{"code":"H05K5/0017","inventive":true,"first":false,"tree":[]},{"code":"H04M2201/38","inventive":fa(...TRUNCATED)
|
45817589
|
US-12215747-B1
|
US-202318381482-A
|
US
|
B1
|
Vibration control system
| "An apparatus includes a retainer, a rotational portion that is connected to the retainer so that it(...TRUNCATED)
| "What is claimed is: \n \n 1. A wheel end assembly comprising:\n a brake rotor comprising:(...TRUNCATED)
| "CROSS-REFERENCE TO RELATED APPLICATIONS \n This application is a continuation of United States (...TRUNCATED)
| 20,231,018
| 20,250,204
| 20,250,204
| 20,200,707
|
[
"HALL, JONATHAN L.",
"SHAWKI, ISLAM MOHSEN",
"Dawson, Jacob L."
] |
APPLE INC
| [{"code":"F16D65/18","inventive":true,"first":false,"tree":[]},{"code":"F16D2055/0012","inventive":f(...TRUNCATED)
|
88878221
|
US-12217379-B2
|
US-202318205883-A
|
US
|
B2
|
Virtual object kit
| "In some implementations, a method includes obtaining a virtual object kit that includes a set of vi(...TRUNCATED)
| "What is claimed is: \n \n 1. A method comprising:\n at a device including a display, a no(...TRUNCATED)
| "CROSS REFERENCE TO RELATED APPLICATIONS \n This application is a continuation application of Se(...TRUNCATED)
| 20,230,605
| 20,250,204
| 20,250,204
| 20,180,830
|
[
"GREASLEY, JACK R."
] |
APPLE INC
| [{"code":"G06T2219/2008","inventive":false,"first":false,"tree":[]},{"code":"G06T2200/24","inventive(...TRUNCATED)
|
69641410
|
End of preview. Expand
in Data Studio
Apple patent dataset associated with: https://docs.sutro.sh/examples/large-scale-embeddings
dataset_info: features: - name: publication_number dtype: large_string - name: application_number dtype: large_string - name: country_code dtype: large_string - name: kind_code dtype: large_string - name: patent_title dtype: large_string - name: patent_abstract dtype: large_string - name: patent_claims dtype: large_string - name: patent_description dtype: large_string - name: filing_date dtype: int64 - name: publication_date dtype: int64 - name: grant_date dtype: int64 - name: priority_date dtype: int64 - name: inventor large_list: large_string - name: assignee_name dtype: large_string - name: cpc large_list: - name: code dtype: large_string - name: inventive dtype: bool - name: first dtype: bool - name: tree large_list: large_string - name: family_id dtype: large_string splits: - name: train num_bytes: 3171060155 num_examples: 31598 download_size: 1073160356 dataset_size: 3171060155 configs: - config_name: default data_files: - split: train path: data/train-* license: mit
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