PATENT DOCUMENT

Publication Number: US-8166324-B2
Application Number: US-10334908-A
Country: US
Kind Code: B2

Title: Conserving power by reducing voltage supplied to an instruction-processing portion of a processor

Abstract:
One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.

Claims:
1. A method of transitioning to a nap mode in a processor, comprising:
 monitoring a load on the processor while the processor is operating; 
 determining if the processor is to be needed soon by:
 determining a power usage during a current execution pattern; 
 determining a cost in power usage of entering and recovering from a nap mode; and 
 determining if the cost is greater than the power usage during the current execution pattern, wherein the processor is to be needed soon when the cost is greater; 
 
 when the processor is to be needed soon, resuming monitoring the load on the processor without transitioning the processor to a nap mode; and 
 when the processor is not to be needed soon, determining if the processor has been taking long naps recently;
 if not, transitioning the processor to a normal nap mode, which comprises halting a clock signal to a core power area of the processor without reducing an input voltage to the processor; 
 otherwise, transitioning the processor to a deep nap mode, which comprises saving state information from the core power area, halting the clock signal to the core power area of the processor, and reducing a voltage supplied to the core power area. 
 
 
     
     
       2. The method of  claim 1 , wherein the method further comprises:
 after halting the clock signal to the core power area of the processor, awaiting at least one of an interrupt or a signal to restart the processor; 
 upon receiving the at least one of the interrupt or the signal to start the processor, restarting instruction processing and resuming monitoring the load on the processor.

Description:
RELATED APPLICATIONS 
     This application is a continuation of pending U.S. patent application Ser. No. 11/213,215, filed 25 Aug. 2005, which is itself a continuation of U.S. patent application Ser. No. 11/103,911, filed 11 Apr. 2005 (U.S. Pat. No. 6,973,585 B2), which is itself a continuation of U.S. patent application Ser. No. 10/135,116, (U.S. Pat. No. 6,920,574 B2) filed 29 Apr. 2002. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to techniques for conserving power usage in computer systems. More specifically, the present invention relates to a method and an apparatus for reducing power consumption in a processor by reducing voltage supplied to an instruction-processing portion of the processor, while maintaining voltage to other portions of the processor. 
     2. Related Art 
     Dramatic advances in integrated circuit technology have led to corresponding increases in processor clock speeds. Unfortunately, these increases in processor clock speeds have been accompanied by increased power consumption. Increased power consumption is undesirable, particularly in battery-operated devices such as laptop computers, for which there exists a limited supply of power. Any increase in power consumption decreases the battery life of the computing device. 
     Modern processors are typically fabricated using Complementary Metal Oxide Semiconductor (CMOS) circuits. CMOS circuits typically consume more power while the circuits are switching, and less power while the circuits are idle. Designers have taken advantage of this fact by reducing the frequency of (or halting) clock signals to certain portions of a processor when the processor is idle. Note that some portions of the processor must remain active, however. For example, a cache memory with its associated snoop circuitry will typically remain active, as well as interrupt circuitry and real-time clock circuitry. 
     Although reducing the frequency of (or halting) a system clock signal can reduce the dynamic power consumption of a processor, static power consumption is not significantly affected. This static power consumption is primarily caused by leakage currents through the CMOS devices. As integration densities of integrated circuits continue to increase, circuit devices are becoming progressively smaller. This tends to increase leakage currents, and thereby increases static power consumption. This increased static power consumption results in reduced battery life, and increases cooling system requirements for battery operated computing devices. 
     What is needed is a method and an apparatus that reduces static power consumption for a processor in a battery operated computing device. 
     SUMMARY 
     One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode. 
     In one embodiment of the present invention, reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor. 
     In one embodiment of the present invention, reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero. 
     In one embodiment of the present invention, the system saves state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor. This state information can either be saved in the remaining portion of the processor or to the main memory of the computer system. 
     In one embodiment of the present invention, upon receiving a wakeup signal, the system: restores full voltage to the instruction-processing portion of the processor; restores state information to the instruction-processing portion of the processor; and resumes processing of computer instructions. 
     In one embodiment of the present invention, maintaining full voltage to the remaining portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, so that the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode. 
     In one embodiment of the present invention, the system also reduces the voltage to a cache memory portion of the processor. In this embodiment, the system writes cache memory data to main memory prior to reducing the voltage. 
     In one embodiment of the present invention, the remaining portion of the processor includes a control portion of the processor containing interrupt circuitry and clock circuitry. 
     In one embodiment of the present invention, the remaining portion of the processor includes a cache memory portion of the processor. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1A  illustrates different power areas within processor  102  in accordance with an embodiment of the present invention. 
         FIG. 1B  illustrates alternate power areas within processor  102  in accordance with an embodiment of the present invention. 
         FIG. 2  is a flowchart illustrating the process of monitoring processor load and switching to power saving modes in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     Processor  102   
       FIG. 1A  illustrates different power areas within processor  102  in accordance with an embodiment of the present invention. Processor  102  is divided into a core power area  126 , and a non-core power area  124 . Core power area  126  includes the instruction-processing portion of processor  102 . Specifically, core power area  126  includes arithmetic-logic unit  104 , register files  106 , pipelines  108 , and possibly level one (L1) caches  110 . Note that L1 caches  110  can alternatively be located in non-core power area  124 . 
     Arithmetic-logic unit  104  provides computational and logical operations for processor  102 . Register files  106  provide source operands, intermediate storage, and destination locations for instructions being executed by arithmetic-logic unit  104 . Pipelines  108  provides a steady stream of instructions to arithmetic-logic unit  104 . Instructions in pipelines  108  are decoded in transit. Therefore, pipelines  108  may contain instructions in various stages of decoding and execution. L1 caches  110  include data caches and instruction caches for arithmetic-logic unit  104 . L1 caches  110  are comprised of very high-speed memory to provide fast access for instructions and data. In one embodiment of the present invention, L1 caches  110  includes a write-through data cache. 
     Non-core power area  124  comprises the remaining portion of processor  102  and includes interrupt processor  112 , real-time clock  114 , clock distribution circuitry  116 , level two (L2) caches  118 , cache tags  120 , and cache snoop circuitry  122 . In general, non-core power area  124  includes portions of processor  102  that are not directly involved in processing instructions, and that need to operate while instruction processing is halted. 
     Interrupt processor  112  monitors interrupts  128  and periodically interrupts the execution of applications to provide services to external devices requiring immediate attention. Interrupt processor  112  can also provide a wake-up signal to core power area  126  as described below. Real-time clock  114  provides time-of-day services to processor  102 . Typically, real-time clock  114  is set upon startup from a battery operated real-time clock in the computer and thereafter provides time to the system. Clock distribution circuitry  116  provides clock signals for processor  102 . Distribution of these clock signals can be switched off or reduced for various parts of processor  102 . For example, clock distribution to core power area  126  can be stopped while the clock signals to non-core power area  124  continue. The acts of starting and stopping of these clock signals are known in the art and will not be described further. Real-time clock  114  and clock distribution circuitry  116  receive clock signal  130  from the computer system. Clock signal  130  is the master clock signal for the system. 
     L2 cache  118  provides a second level cache for processor  102 . Typically, an L2 cache is larger and slower that an L1 cache, but still provides faster access to instructions and data than can be provided by main memory. Cache tags  120  provide an index into data stored in L2 cache  118 . Cache snoop circuitry  122  invalidates cache lines base primarily on other processors accessing their own cache lines, or I/O devices doing memory transfers, even when instruction processing has been halted. L2 cache  118 , cache tags  120 , and cache snoop circuitry  122  communicate with the computer system through memory signals  132 . 
     Non-core power area  124  receives non-core power  136  and core power area  126  receives core power  134 . The voltage applied for non-core power  136  remains at a voltage that allows circuitry within non-core power area  124  to remain fully active at all times. In contrast, non-core power  136  may provide different voltages to non-core power area  124  based upon the operating mode of processor  102 . For example, if processor  102  is a laptop attached to external electrical power, the voltage provided to non-core power  136  (and to core power  134  during instruction processing) may be higher than the minimum voltage, thus providing faster execution of programs. 
     The voltage applied to core power  134  remains sufficiently high during instruction processing so that core power area  126  remains fully active. However, when processor  102  receives a signal that processing can be suspended, the voltage supplied by core power  134  can be reduced. 
     In one embodiment of the present invention, the voltage in core power  134  is reduced to the minimum value that will maintain state information within core power area  126 , but this voltage is not sufficient to allow processing to continue. In another embodiment of the present invention, the voltage at core power  134  is reduced to zero. In this embodiment, the state of core power area  126  is first saved before the voltage is reduced to zero. This state can be saved in a dedicated portion of L2 cache  118 , in main memory, or in another dedicated storage area. Upon receiving an interrupt or other signal indicating that processing is to resume, the voltage in core power  134  is restored to a normal level, saved state is restored, and processing is restarted. 
       FIG. 1B  illustrates an alternative partitioning of power areas within processor  102  in accordance with an embodiment of the present invention. As shown in  FIG. 1B , L2 cache  118 , cache tags  120 , and cache snoop circuitry  122  are included in core power area  126  rather than in non-core power area  124 . In this embodiment, the voltage supplied as core power  134  is reduced or set to zero as described above, however, the cache circuitry within processor  102  is also put into the reduced power mode. Prior to reducing the voltage supplied to core power area  126 , data stored in L2 cache  118  is flushed to main memory. Additionally, if the voltage at core power  134  is reduced to zero, the state of processor  102  is first saved in main memory. 
     Monitoring and Switching 
       FIG. 2  is a flowchart illustrating the process of monitoring processor load and switching to power saving modes in accordance with an embodiment of the present invention. The system starts by monitoring the processor load (step  202 ). Next, the system determines if the processor will be needed soon (step  204 ). This determination is made based on the current execution pattern and the cost of entering and recovering from nap mode. This cost, calculated in power usage, must be less than the power wasted by not going into nap mode. If the processor will be needed soon at step  204 , the process returns to step  202  to continue monitoring the processor load. 
     If the processor will not be needed soon at step  204 , the system determines if the processor has been taking long naps recently (step  206 ). If not, the system enters a normal nap mode, which involves halting the processor without reducing any voltages (step  208 ). Typically, halting the processor involves removing the clock signals to the core power area of the processor. After halting the processor, the system waits for an interrupt (step  210 ). Upon receiving an interrupt or other signal requiring a restart, the system restarts instruction processing (step  212 ). After restarting instruction processing, the process returns to step  202  to continue monitoring the processor load. 
     If the processor has recently been taking long naps at step  206 , the system enters a deep nap mode, which involves saving the state information from the core power area (step  214 ), halting the processor (step  216 ), and then reducing the voltage supplied to the core power area (step  218 ). After reducing the voltage, the system waits for an interrupt (step  220 ). 
     Upon receiving the interrupt or other signal requiring a restart, the system restores the voltage to the core power area (step  222 ). Next, the modules within the core power area are restarted (step  224 ). The system then restores the state information that was saved at step  214  (step  226 ). After the processor has been restarted, the process returns to step  202  to continue monitoring the processor load. Note that the above description applies when the processor is used to save and restore the state information. In cases where dedicated hardware saves and restores the state information, steps  214  and  216 , and steps  224  and  226  can be reversed. Note also that if the voltage supplied to the core power area  126  is reduced but maintained at a level where modules in the core power do not lose state information, steps  216  and  224  are not required. 
     The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.

Metadata:
Filing Date: 20080415
Publication Date: 20120424
Grant Date: 20120424
Priority Date: 20020429
Inventors: YOUNGS LYNN R.
Assignee: APPLE INC
CPC Classifications: [{"code": "G06F1/3228", "inventive": true, "first": false, "tree": "[]"}, {"code": "Y02D30/50", "inventive": false, "first": false, "tree": "[]"}, {"code": "Y02D10/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "Y02D30/50", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F1/3275", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3287", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F1/3203", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3287", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3203", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3228", "inventive": true, "first": false, "tree": "[]"}, {"code": "Y02D10/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F1/3275", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 29249379