PATENT DOCUMENT

Publication Number: US-8999771-B2
Application Number: US-201213631385-A
Country: US
Kind Code: B2

Title: Protection layer for halftone process of third metal

Abstract:
A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor.

Claims:
We claim: 
     
       1. A method for forming a thin-film transistor, comprising:
 forming a via in a planarization layer; 
 depositing a protection layer over the planarization layer; 
 depositing a common electrode layer over the protection layer; 
 depositing a metal layer over the common electrode layer; 
 etching a portion of the common electrode layer and the metal layer to form a remainder of the metal layer; 
 depositing a passivation layer over a portion of the protection layer, a portion of the common electrode and the remainder of the metal layer; 
 etching a portion of the passivation layer and a second portion of the protection layer; and 
 coating the via with a conductive material. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming, with the conductive material, an electrical connection between the pixel electrode layer and a drain. 
 
     
     
       3. The method of  claim 1 , wherein the operations of patterning a common electrode layer and a metal layer are performed with a single mask. 
     
     
       4. The method of  claim 1 , wherein the etching of the passivation layer and the second portion of the protection layer, occurs as part of a single etching process. 
     
     
       5. The method of  claim 1 , wherein the protection layer is formed from one of silicon nitride and silicon oxide. 
     
     
       6. The method of  claim 5 , wherein each of the passivation layer and the protection layer are formed from the same material. 
     
     
       7. The method of  claim 6 , wherein the protection layer is from 50-2000 Angstroms thick. 
     
     
       8. The method of  claim 6 , wherein the protection layer is from 100-500 Angstroms thick. 
     
     
       9. The method of  claim 1 , wherein the protection layer protects the planarization layer during the operation of at least one of photoresist ashing for single mask process of the common electrode and the metal layer, or etching a portion of the common electrode layer and the metal layer to form a remainder of the metal layer. 
     
     
       10. A method for forming a thin-film transistor, comprising:
 forming a via in a planarization layer, the planarization layer overlaying a first passivation layer; 
 depositing a protection layer over the planarization layer; 
 depositing a metal layer over the protection layer; 
 depositing a common electrode layer over the metal layer; 
 etching a portion of the common electrode layer and the metal layer to form a remainder of the metal layer; 
 depositing a second passivation layer over a portion of the protection layer, a portion of the common electrode and the remainder of the metal layer; and 
 etching a portion of the second passivation layer, a second portion of the protection layer, and a portion of the first passivation layer to extend the via to a drain of the thin-film transistor.

Description:
TECHNICAL FIELD 
     Embodiments described herein relate generally to a manufacturing process for a display element, and more particularly to a manufacturing process providing a protection layer for a metal layer of a display pixel, while reducing complexity of the manufacture process. 
     BACKGROUND 
     Multi-step mask process flows may be used to manufacture thin-film transistor devices, including thin-film transistors that operate pixels in an electronic display. Pixel thin-film transistors may include a common voltage electrode. This common voltage electrode (V COM  electrode) may have a relatively high sheet resistance, which is undesirable. 
     Accordingly, some pixel thin-film transistors employ a third metal layer to reduce the sheet resistance of the V COM  electrode. (Generally, the first and second metal layers correspond to the gate and source/drain of the transistor.) The implementation of a third metal layer may add an additional mask to the process flow, thereby increasing the cost of manufacture and reducing the manufacturing yield. Generally, any increase in the number of masks required to create a transistor has an adverse effect on manufacturing. 
     The number of masks may be reduced by using a halftone process etch both the common electrode and third metal. However, such a halftone process may result in a loss of thickness in the planarization layer during an ashing process used to remove the photoresist that forms the halftone. This may result in, ultimately, a mis-formed via hole between a pixel conductive upper layer and the source/drain or gate metal. Thus, it may be desirable to protect the planarization layer during manufacturing. 
     SUMMARY 
     One embodiment described herein takes the form of a thin-film transistor, comprising: a gate; a gate insulator overlaying the gate; an active layer overlaying the gate insulator; a source/drain overlaying the gate insulator; a first passivation layer overlaying the source/drain; a planarization layer overlaying the first passivation layer; and a protection layer overlaying the planarization layer. 
     Another embodiment described herein takes the form of a method for forming a thin-film transistor, comprising: forming a via in a planarization layer; depositing a protection layer over the planarization layer; depositing a common electrode layer over the protection layer; depositing a third metal layer over the common electrode layer; etching a portion of the common electrode layer and the metal layer to form a remainder of the metal layer; depositing a second passivation layer over a portion of the protection layer, a portion of the common electrode and the remainder of the metal layer; etching a portion of the second passivation layer, a second portion of the protection layer, a portion of the planarization layer, and a portion of first passivation layer to extend the via to a drain of the thin-film transistor; and coating the via with a conductive material. 
     These and other embodiments will be more fully understood upon reading the specification in its entirety. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1  depicts a schematic cross-section of a thin-film transistor device for a display pixel, in accordance with an embodiment. 
         FIG. 2  depicts a schematic cross-section of the thin-film transistor device of  FIG. 1  after deposition of a planarization layer. 
         FIG. 3  depicts a schematic cross-section of the thin-film transistor device of  FIG. 2  after formation of a via hole. 
         FIG. 4  depicts a schematic cross-section of the thin-film transistor device of  FIG. 3  after formation of a protection layer. 
         FIG. 5  depicts a schematic cross-section of the thin-film transistor device of  FIG. 4  after a common electrode, third metal and photoresist layer have been deposited. 
         FIG. 6  depicts a schematic cross-section of the thin-film transistor device of  FIG. 5  after an etching process. 
         FIG. 7  depicts a schematic cross-section of the thin-film transistor device of  FIG. 6  after an ashing process. 
         FIG. 8  depicts a schematic cross-section of the thin-film transistor device of  FIG. 7  after another etching process acting on the third metal layer. 
         FIG. 9  depicts a schematic cross-section of the thin-film transistor device of  FIG. 8  after deposition of a second passivation layer and a photoresist layer. 
         FIG. 10  depicts a schematic cross-section of the thin-film transistor device of  FIG. 9  after another etching process. 
     
    
    
     DETAILED DESCRIPTION 
     Generally, embodiments described herein take the form of a method for manufacturing a display element, through using a protective layer overlying a planarization layer. The finished pixel cross-section, for example, may include a planarization layer overlying a first passivation layer, a source and drain of an associated pixel thin-film transistor (TFT) an active layer of the pixel, a gate insulator, and a gate. The protective layer may overlie the planarization layer at least partially. The planarization layer may be an organic material, such as a photoresist material. In some embodiments, the first passivation layer is optional and may be omitted. 
     Currently, a multi-mask process flow is used to manufacture thin film transistor devices. In the specific context of thin film transistor display panels, this manufacturing process includes making a connection to a V COM  signal line that provides a reference for the backplane or back plate of the panel.  FIG. 1  is a cross-sectional area of semiconductor device  100  that represents a portion of one sample thin film transistor display panel. 
     The semiconductor device  100  shown in  FIG. 1  may take the form of at least one thin film transistor  100 , including a V COM  electrode. The TFT  100  and other structures of the device include elements that are located in a first metal layer disposed on a substrate  102 . The first metal layer includes a gate  108  for the thin-film transistor  100 . The thin-film transistor  100  additionally includes a semiconductor  114  that forms the active layer of the TFT. The semiconductor  114  sits on a gate insulation layer  110 , which is disposed on the first metal layer (not shown in  FIG. 1 ). The semiconductor  114  is connected to a source  116  electrode and to a drain  117  electrode, each of which is formed in a second metal layer. The terms “thin film transistor,” “TFT,” and “semiconductor device” are generally used interchangeably herein. 
     A via hole  124  provides a connection to the drain  117 . As shown in  FIG. 1 , the via hole  124  extends through a first passivation layer  112 , an organic layer  120 , and a second passivation layer  122 . The via hole  124  makes electrical contact with the drain  117  through a thin film of transparent conducting oxide  128  that is deposited on an interior of the via hole  124 . 
     As mentioned above, the semiconductor device  100  may be a portion of a thin film transistor display panel. In this case, the transistor  100  may implement or otherwise be associated with one of a number of pixels in the display panel. In addition to transistors that implement pixels, a thin film transistor display panel will also typically include a V COM  signal line (e.g., electrode). The V COM  signal provides a reference for the backplane or back plate of the panel. The semiconductor device  100  shown in  FIG. 1  includes a V COM  signal line  106  that is routed beneath a third metal layer  104 . The third metal layer  104  may function to reduce the sheet resistance of the V COM  electrode. 
     Generally, manufacture of the pixel TFT up to the planarization layer  120  occurs as known with respect to prior art display pixel TFTs.  FIG. 2  depicts the pixel TFT with the planarization layer  120  deposited as the most recent mask step. The planarization layer may be formed from any suitable material, including an organic material. Accordingly, manufacture of the pixel TFT  100 , including the use of a protective layer to minimize reduction of the planarization layer during later etching processes, will now be described. 
     Following deposition of the planarization layer  120  as shown in  FIG. 2 , the via hole  124  may be formed. Generally, the planarization layer  120  may be formed from an organic material, such as a photoresist material. Accordingly, the via hole  124  may be formed by appropriately masking the planarization layer and then exposing the planarization layer to light. If the planarization layer is formed from a positive photoresist, the area in which the via hole  124  is to be formed will not be masked, but the rest of the planarization layer surface will be masked. When a light source is activated, light impacts the unwanted portion of the planarization layer. The photoresist of the planarization layer is rendered soluble to an etching or developing agent by the light. The rest of the passivation layer is shielded from etching effects by the photoresist. After light exposure, the developing agent is applied to the upper surface of the pixel TFT  100  to remove the soluble portion of the planarization layer. 
     The result is that the undesired portion of the planarization layer  120  is consumed. Thus, via hole  124  is formed in a small region of the planarization layer but the rest of the layer remains untouched. This results in the configuration shown in  FIG. 3 , with the via hole  124  in the planarization layer  120 . 
     What has been described is a positive photoresist. A positive photoresist generally is insoluble to a developing agent initially but becomes soluble when exposed to light. Certain embodiments may use a negative photoresist instead, which begins as soluble to the developing agent, but becomes insoluble when light impacts it. Depending on the type of photoresist chosen, the light may be manipulated accordingly to provide solubility and insolubility where desired. For example, if the planarization layer  120  is formed from a negative photoresist, the area in which the via hole  124  is to be formed may be masked while the rest of the planarization layer surface is not. Thus, after exposure of the planarization layer to light and removal of the mask, the area to be formed into the via hole  124  may remain soluble to an etchant while the rest of the planarization layer will resist etching. 
     After forming the via hole  124 , which provides a connection between the source/drain metal and the pixel ITO layer, a protection layer  103  may be deposited. The protection layer  103  overlies the planarization layer  120  and also the sides and bottom of the via hole  124 , forming a continuous coating. As will be discussed below, the protection layer may prevent the planarization layer from being inadvertently etched away during a later mask process. The protection layer may be formed from silicon nitride (SiNx), in some embodiments. In other embodiments, silicon oxide (SiO2) may be used. 
     Following deposition of the protection layer, the V COM  electrode  106  (in the present embodiment, formed from ITO) may be formed atop the protection layer  103 . A third metal layer  104  may be deposited on the V COM  electrode  106 . Next, a photoresist layer  500  may be placed on a portion of the third metal layer. This creates the configuration shown in  FIG. 5 . The third metal layer and V COM  electrode layer also overlie the sides of the via hole  124 , as shown in  FIG. 5 . 
     With respect to  FIG. 5 , it should be noted that the photoresist layer does not cover the via hole  124  or a portion of the third metal  104  around or adjacent the via hole. Further, the photoresist is thicker over a segment of the third metal layer  104  than over other areas (shown to the right-hand side of  FIG. 5 ). The thicker area represents a full photoresist coating, while the thinner photoresist coating areas are a halftone coating. This halftone process will be used to combine the mask for the third metal layer  104  and V COM  electrode  106  as shown previously with respect to  FIG. 1 . The etching of the third metal layer will be discussed later. 
     Next, the third metal layer  104  and V COM  electrode layer  106  are etched away in the areas not covered by the photoresist, thus removing these layers in those areas. This etching process removes the third metal layer and V COM  electrode layer from the via hole  124 . The etching is stopped by the protection layer, which is insoluble to the etching process. Thus, the planarization layer  120  is not etched away when the third metal and electrode layers are removed. Without the protection layer  103 , the planarization layer  120  may be affected by the etching process. The results of the etching operation are shown in  FIG. 6 . The etching process does not affect the photoresist layer  500 , as also shown in  FIG. 6 . 
     An ashing process is now performed. The ashing process removes the photoresist layer  500  in the halftone regions but leaves a small photoresist deposit  700  at one location above the third metal layer  104 . Without the protection layer  103 , the planarization layer  120  may be affected by the ashing process.  FIG. 7  depicts the pixel TFT cross-section after ashing. 
     Next, the third metal layer  104  is etched. The etching removes the third metal anywhere it is not protected by photoresist deposit  700 . The photoresist deposit  700  may also be removed. Following etching of the third metal layer, the third metal  104  is exposed, a portion of the V COM  electrode  106  is exposed, and the protection layer  103  is exposed around and along the sidewalls of the via hole  124 . This configuration is depicted in  FIG. 8 . 
     Following the third metal etching process, a second passivation layer  122  may be formed atop portions of the third metal  104 , V COM  electrode  106  and protection layer  103 . The second passivation layer  122  may extend into the via hole  124 . Next, a photoresist layer  900  may be deposited on the second passivation layer  122 , except in the area of the second passivation layer corresponding to the via hole  124 .  FIG. 9  depicts a cross-section of the pixel TFT showing the second passivation layer  122  and photoresist layer  900 . A single mask may be used to pattern the passivation layer. 
     Given the foregoing, an etching process may be performed to form the via hole  124  into its final shape and depth. This etching process may extend the via hole  124  to abut the source/drain layer  117 . The etching process may be a dry etch, in some embodiments. Generally, the etchant removes the first passivation layer  112 , the protection layer  103  and the second passivation layer  122 . The etchant may act on all three layers because, in some embodiments, all may be formed from SiNx or SiO2. One mask may be used to pattern all three layers. 
     The etchant is generally ineffective against metal, and so stops etching once it reaches the source/drain metal layer. This finally forms the via hole  124  and establishes the hole as reaching to the source/drain metal layer. The pixel electrode  128  (ITO or another suitable conductive material) may be deposited in the via hole  124 . This permits electrical contact with the drain  117  through the thin film of transparent conducting material  128  that is deposited on an interior of the via hole  124 . This configuration is shown generally in  FIG. 10 . The pixel electrode  128  may be patterned through use of another mask. 
     The pixel electrode  128  may serve as a bridge between the source/drain metal and the V COM  electrode  106 . (This connection is not visible in the cross-section of  FIG. 10 ). [Accordingly, the planarization layer may be protected from negative impacts of manufacturing operations while a via hole  124  is still provided between the upper layers of the pixel TFT and the source/drain metal. The final cross-section of the pixel TFT is that shown in  FIG. 1  and discussed above. 
     As previously mentioned, several of the layers may be formed from silicon nitride or silicon oxide. For example, in some embodiments, each of the second passivation layer, protection layer and first passivation layer may be silicon nitride or silicon oxide. In one embodiment, the first and second passivation layers may be approximately from 500 to 3000 Angstroms thick, while the protection layer is approximately 50-2000 Angstroms thick. In certain embodiments, the protection layer may be 100-500 Angstroms thick. Thus, the protection layer may be sufficiently thick to prevent an ashing process from damaging the planarization layer, but need not add great thickness to the overall cross-section of the TFT structure  100 . 
     In alternative embodiments, the common electrode layer  106  may overlie the third metal layer  104 . That is, the V COM  electrode and third metal may switch places in the pixel TFT stackup. In such embodiments, it may not be necessary to employ the halftone process described herein to form the third metal layer  104 ; the halftone may be omitted. 
     Although embodiments have been described herein with respect to certain physical structures and processes, it should be appreciated that alternative embodiments may add to, omit or alter both structures and processes without departing from the spirit and scope of this disclosure. Accordingly, the proper scope of protection is set forth in the following claims.

Metadata:
Filing Date: 20120928
Publication Date: 20150407
Grant Date: 20150407
Priority Date: 20120928
Inventors: HUNG MING-CHIN
YANG BYUNG DUK
KIM KYUNG WOOK
CHANG SHIH CHANG
Assignee: APPLE INC
CPC Classifications: [{"code": "H01L21/76838", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/768", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L21/76802", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10D86/451", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10D86/0231", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10D86/60", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10D86/0231", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10D86/60", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10D86/451", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L27/1288", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/768", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L27/1248", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/76838", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/76802", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 50384368