PATENT DOCUMENT

Publication Number: US-11431250-B2
Application Number: US-202117140919-A
Country: US
Kind Code: B2

Title: Voltage regulator with multi-level, multi-phase buck architecture

Abstract:
A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

Claims:
What is claimed is: 
     
       1. A circuit comprising:
 a first two-level buck converter configured to generate one of two voltage levels, the first two-level buck converter including a first inductor coupled to receive one of the two voltage levels and configured to provide a corresponding first current on an output node; 
 a first N-level buck converter configured to generate one of N voltage levels, wherein N is an integer value of three or more, and wherein the first N-level buck converter includes a second inductor coupled to receive one of the N voltage levels and configured to provide a corresponding second current on the output node; 
 at least one M-level buck converter configured to provide a corresponding current to the output node, wherein M is an integer value of three or more and wherein M is different than N, wherein the at least one M-level buck converter is configured to provide a corresponding third current on the output node; and 
 a control circuit coupled to receive a feedback signal based on a voltage present on the output node and configured to control respective states of transistors in the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter to cause the voltage on the output node to be maintained at a desired value. 
 
     
     
       2. The circuit of  claim 1 , wherein the control circuit is configured to control switching sequences for the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter independently of one another. 
     
     
       3. The circuit of  claim 1 , wherein the circuit includes a second two-level buck converter, wherein the control circuit is configured to control switching sequences for the first and second two-level buck converters such that their duty cycles are different from one another. 
     
     
       4. The circuit of  claim 1 , wherein the circuit includes a second N-level buck converter, wherein the control circuit is configured to control switching sequences for the first and second N-level buck converters such that their duty cycles are different from one another. 
     
     
       5. The circuit of  claim 1 , wherein the control circuit is configured to cause the first two-level buck converter to operate with a duty cycle of 50% and further configured to cause the first N-level buck converter to operate with a duty cycle that is not equal to 50%. 
     
     
       6. The circuit of  claim 1 , further comprising a feedback circuit, wherein the control circuit is configured to control respective duty cycles of the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter based on the desired value of the voltage on the output node and a feedback voltage generated by the feedback circuit. 
     
     
       7. The circuit of  claim 1 , further comprising a plurality of two-level buck converters including the first two-level buck converter. 
     
     
       8. The circuit of  claim 1 , further comprising a plurality of N-level buck converters including the first N-level buck converter. 
     
     
       9. The circuit of  claim 1 , wherein the N-level buck converter is a three-level buck converter. 
     
     
       10. The circuit of  claim 9 , wherein the three-level buck converter includes:
 a pull-up stack having a first and second transistors coupled in series between a first terminal of the second inductor and an input voltage node, the first transistor having a source terminal coupled to the input voltage node and the second transistor having a drain terminal coupled to the first terminal of the second inductor; 
 a pull-down stack having third and fourth transistors coupled in series between the first terminal of the second inductor and a ground node, the third transistor having a drain terminal coupled to the first terminal of the second inductor, and the fourth transistor having a source terminal coupled to the ground node; and 
 a capacitor coupled between the drain terminal of the first transistor and the drain terminal of the fourth transistor. 
 
     
     
       11. A method comprising:
 providing a first current on an output node, wherein the first current is generated by a first two-level buck converter alternatively generating one of two voltage levels and converting the two voltage levels into the first current using a first inductor; 
 providing a second current on the output node, wherein the second current is generated by a first N-level buck converter generating one of N voltage levels in a predefined sequence and converting the N voltage levels into the second current using a second inductor, wherein N is an integer value of at least three 
 providing a third current on the output node using at least one M-level buck converter, wherein M is an integer value of three or more, and where M is not equal to N; and 
 a control circuit controlling respective duty cycles of transistors in each of the first two-level buck converter and the first N-level buck converter based on a desired output voltage and a feedback signal generated using a voltage present on the output node. 
 
     
     
       12. The method of  claim 11 , further comprising controlling switching sequences for the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter independently of one another. 
     
     
       13. The method of  claim 11 , further comprising the controlling switching sequences for the first two-level buck converter and a second two-level buck converter such that their duty cycles are different from one another. 
     
     
       14. The method of  claim 11 , further comprising causing the first two-level buck converter to operate with a duty cycle of 50% the first N-level buck converter to operate with a duty cycle that is not equal to 50%. 
     
     
       15. The method of  claim 11 , further comprising controlling respective duty cycles of the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter based on desired value of the output voltage and a feedback voltage generated by a feedback circuit. 
     
     
       16. A system comprising:
 a load circuit; 
 a hybrid voltage regulator configured to provide a supply voltage to the load circuit, the hybrid voltage regulator comprising:
 a first two-level buck converter configured to provide a corresponding first current on an output node; 
 a first N-level buck converter configured to provide a corresponding second current on the output node, wherein N is an integer value greater than two; 
 a first M-level buck converter configured to provide a corresponding third current on the output node, wherein M is an integer value great than two and different from N; and 
 a control circuit configured to control switching sequences of transistors in the first two-level buck converter, the first N-level buck converter, and the first M-level buck converters, independently of one another, to generate the supply voltage at a desired voltage value on the output node. 
 
 
     
     
       17. The system of  claim 16 , wherein the hybrid voltage regulator includes a second two-level buck converter, wherein the control circuit is configured to control respective switching sequences of the first and second two-level buck converters such that their respective duty cycles are different from one another. 
     
     
       18. The system of  claim 16 , wherein the hybrid voltage regulator includes a second N-level buck converter, wherein the control circuit is configured to control respective switching sequences of the first and second N-level buck converters such that their respective duty cycles are different from one another. 
     
     
       19. The system of  claim 16 , wherein the control circuit is configured to cause the first two-level buck converter to operate with a duty cycle of 50% and further configured to cause the first N-level buck converter to operate with a duty cycle that is not equal to 50%. 
     
     
       20. The system of  claim 16 , wherein N=3, and wherein the first N-level buck converter includes:
 a pull-up stack having a first and second transistors coupled in series between a first terminal of an inductor and an input voltage node, the first transistor having a source terminal coupled to the input voltage node and the second transistor having a drain terminal coupled to the first terminal of the inductor; 
 a pull-down stack having third and fourth transistors coupled in series between the first terminal of the inductor and a ground node, the third transistor having a drain terminal coupled to the first terminal of the inductor, and the fourth transistor having a source terminal coupled to the ground node; and 
 a capacitor coupled between the drain terminal of the first transistor and the drain terminal of the fourth transistor.

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 16/570,805, filed Sep. 13, 2019 (now U.S. Pat. No. 10,886,851), which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     Technical Field 
     This disclosure is directed to electronic circuits, and more particularly, to voltage regulator circuits. 
     Description of the Related Art 
     Voltage regulators are commonly used in a wide variety of circuits in order to provide a desired voltage to particular circuits. To this end, a wide variety of voltage regulator circuits are available to suit various applications. Linear voltage regulators are used in a number of different applications in which the available supply voltages exceed an appropriate value for the circuitry to be powered. Another type of voltage regulator is a switched-mode voltage regulator, more commonly referred to a switching power supply, or alternatively, a DC-DC converter. Switching power supplies can be subdivided into two categories, buck converters and boost converters. A buck converter, from its supply to its load, steps down an input voltage, while stepping up current. A boost converter, from its supply to its load, steps up the input voltage while stepping down the current. 
     A basic switching power supply includes a switch, an energy storage element (such as an inductor), and a diode. Operation in a basic switching power supply includes an on state (when the switch is closed) and an off state (when the switch is open). During the on state, the energy storage element begins to store energy. For example, when the energy storage element is an inductor, current increases and responsive thereto, the inductor produces an opposing voltage across its terminals. During the off state, the switch is open and the inductor becomes a current source. Over time, the changing voltage of the switching power supply is averaged out to a substantially DC voltage. 
     SUMMARY 
     A voltage regulator having a multi-level, multi-phase architecture is disclosed. In one embodiment, a circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level. 
     In various embodiments, the circuit may include multiple instances of the two-level buck converter, the N-level buck converter, or both. Some embodiments may also include one or more M-level buck converters coupled to the output node, wherein M is an integer value of three or more and different than N. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG. 1  is a block diagram of one embodiment of a hybrid buck converter having a two-level buck converter and an N-level buck converter. 
         FIG. 2  is a schematic diagram of one embodiment of a hybrid converter having a two-level buck converter and an N-level buck converter. 
         FIG. 3  illustrates the timing of operation for various embodiments of a buck converter. 
         FIG. 4  is a block diagram of another embodiment of a hybrid buck converter. 
         FIG. 5  is a block diagram of another embodiment of a hybrid buck converter. 
         FIG. 6  is a flow diagram illustrating operation of one embodiment of a hybrid buck converter. 
         FIG. 7  is a block diagram of one embodiment of an example system. 
     
    
    
     Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described herein in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, this application is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure of the present application as defined by the appended claims. 
     This disclosure includes references to “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” or “an embodiment.” The appearances of the phrases “in one embodiment,” “in a particular embodiment,” “in some embodiments,” “in various embodiments,” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. 
     Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “credit distribution circuit configured to distribute credits to a plurality, of processor cores” is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible. 
     The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function after programming. 
     Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, none of the claims in this application as filed are intended to be interpreted as having means-plus-function elements. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct. 
     As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.” 
     As used herein, the phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B. 
     As used herein, the terms “first,” “second,” etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1. 
     When used in the claims, the term “or” is used as an inclusive or and not as an exclusive or. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, as well as any combination thereof. 
     In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosed embodiments. One having ordinary skill in the art, however, should recognize that aspects of disclosed embodiments might be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instruction, and techniques have not been shown in detail to avoid obscuring the disclosed embodiments. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The present disclosure is directed to a hybrid buck converter, including multiphase and multi-level elements. Traditional multiphase buck converters are two-level buck converter that drive two different voltage levels in the inductor depending on the state of the switches therein. Multiple instances of a two-level buck converters may be implemented in the same voltage regulator to form a multiphase buck converter. These converters may provide a flat efficiency across the full current range of the converter. Multi-level buck converters that output three or more levels and may be more efficient at low currents. Various embodiment of a hybrid voltage regulator having both two-level and N-level buck converters (where N is an integer value of three or more) are disclosed herein. The present disclosure also contemplates embodiments in which N-level and M-level (where M is an integer value of three or more and not equal to N) combined with a two-level disclosure are also possible and contemplated. 
       FIG. 1  is a block diagram of one embodiment of a hybrid voltage regulator including a two-level buck converter and an N-level buck converter. In the embodiment shown, voltage regulator  100  includes two-level buck converter  102 , an N-level buck converter  104  (where N is an integer value of three or more) each coupled to an output node upon which an output voltage, Vout, is conveyed. Both 2-level buck converter  102  and N-level buck converter  104  are coupled to receive a supply voltage Vdd and are also coupled to a ground node (which may alternatively be referred to as Vss). Voltage regulator  100  also includes a control circuit  106  coupled to control the switching operation in each of the buck converters in the illustrated embodiment. A feedback circuit  108  is coupled between the output voltage node and control circuit  106 , and is configured to generate a feedback signal, Vfb. Voltage regulator  100  also includes a capacitor, VC, coupled between the output node and ground. The voltage generated by voltage regulator  100  is provided to a load circuit  121 , which may be virtually any type of circuitry which may be powered by a regulated supply voltage. 
     Two-level buck converter  102  in the embodiment shown is configured to generate one of two different voltages, depending on the states of switches therein, and provide these voltages to an inductor. The inductor integrates the voltages into a current which is conveyed onto the output node. N-level buck converter  104  generates one of N (e.g., three) different voltages and provides these to a corresponding inductor therein. Similar to two-level buck converter  102 , an inductor therein converts these voltages to corresponding currents, which are conveyed onto the output node. These currents are summed on the output node, and in turn converted back into a voltage by capacitor VC. 
     Feedback circuit  108  is configured to convert the output voltage, Vout, into a feedback signal, Vfb. Various circuit topologies may be used to implement feedback circuit  108 . One example topology includes a resistive voltage divider and an error amplifier. The error amplifier may receive a voltage from the resistive voltage divider on one input and a reference voltage on another input. The reference voltage may correspond to a desired output voltage, Vout. The error amplifier may output the feedback signal, Vfb, which may be indicative of a difference between the desired and actual output voltages. 
     Control circuit  106  in the embodiment shown may control the switching of various transistors in two-level buck converter  102  and N-level buck converter  104 , based on the received feedback signal. More particularly, the duty cycle of each transistors on/off time may be controlled in such a manner as to adjust the output voltage, Vout, and maintain it at the desired value. The switching of the transistors in each of the buck converters may by synchronized by a clock signal, Clk, which is provided to control circuit  106 . Control circuit  106  may be implemented using various types of circuitry, including (but not limited to) sequential logic circuitry, combinational logic circuitry, analog circuitry, and mixed signal circuitry. 
       FIG. 2  is a schematic diagram of one embodiment of a hybrid converter having a two-level buck converter and an N-level buck converter. In the embodiment shown, the N-level buck converter is three-level buck converter  204 , although the disclosure is not limited to this number of levels. 
     Two-level buck converter  102  in the embodiment shown includes a pull-up transistor P 1  and a pull-down transistor N 1 . The pull-up transistor P 1  includes a drain terminal coupled to lx 1  and a source terminal coupled to the voltage supply node Vdd. The pull-down transistor N 1  includes a drain terminal coupled to node lx 1  and a source terminal coupled to ground (or Vss). The gate terminal of P 1 , node pg, is coupled to an output of an optional buffer B 1 , while the gate terminal of N 1 , ng, is coupled to the output of another optional buffer B 3 . Both buffer B 2  and B 3  are coupled to an output of another optional buffer B 1 , which has an input coupled to other circuitry within control circuit  106 . Inductor L 1  of two-level buck converter  102  is coupled to node lx 1  at one terminal, and coupled to the output node, Vout, at the other terminal. 
     Three-level buck converter  204  in the embodiment shown includes a pull-up stack including transistors P 2  and P 3 , and a pull-down stack including transistors N 2  and N 3 . The drain terminal of P 3  is coupled to node lx 2 , while the source terminal of P 3  and the drain terminal of P 2  are coupled to one another. The source terminal of P 2  is coupled to the supply voltage node Vdd. With respect to the pull-down stack, the drain terminal of N 2  is coupled to node lx 2 , while the source terminal of N 2  is coupled to the drain terminal of N 3 . The source terminal of N 3  is coupled to ground or Vss. Inductor L 2  has a first terminal coupled to node lx 2  and a second terminal coupled to the output node, Vout. Three-level buck converter  204  also includes a capacitor, Cfly, which is coupled between the source terminal of P 3  and the source terminal of N 2 . 
     During operation of two-level buck converter  102 , only one of transistors P 1  or P 2  is active at any given time. When a high is input into buffer B 1  (and thus propagates to the gate terminals of P 1  and N 1 ), transistor N 1  is active while P 1  is inactive. When N 1  is active, the voltage on node lx 1  is pulled low to ground/Vss. Energy stored in inductor L 1  may be discharged through N 1  to ground/Vss. Meanwhile, an opposing voltage is developed across inductor L 1 . When a low is input into buffer B 1 , transistor P 1  is activated while transistor N 1  is turned off. When P 1  is active, node lx 1  is pulled high toward Vdd. Inductor L 1  discharges current to the output node, while an opposing voltage is developed there across. 
     Control circuit  106  may adjust the current provided by two-level buck converter  102 , to the output node, by adjusting its duty cycle, e.g. by changing the amount of time within a given cycle that each transistor is active. This can cause a corresponding adjustment to the voltage on output node Vout. 
     Three-level buck converter  204  in the embodiment shown may output one of three different voltages—zero volts, Vdd, and a third voltage based on the voltage across the capacitor, Cfly. The voltage on node lx 2  may be pulled low toward ground/Vss when both transistors of the pull-down stack, N 2  and N 3 , are active. The voltage on node lx 2  may be pulled toward Vdd when both transistors of the pull-up stack, P 2  and P 3 , are active. When the transistors of three-level buck converter are switched at a 50% duty cycle, the third voltage on lx 2 , which is the voltage across Cfly, is Vdd/2. As will be discussed in further detail below, this third voltage may be adjusted by varying the duty cycle of the transistors in three-level buck converter  204 . As with the embodiment discussed above, the current into lx 2  may vary with the voltage on the node at any given time. Similarly, inductor L 2  may discharge current in one direction or another depending on the switching states of the transistors, with an opposing voltage developed there across. 
     The currents generated by two-level buck converter  102  and three-level buck converter  204  are summed on the output node, Vout. Due to the presences of capacitor VC, the currents, and thus the voltage on this node may be averaged out to a DC voltage that is provided to load circuit  121 . 
     The timing of operation of embodiments of the buck converters discussed above are shown in  FIG. 3 . In the uppermost timing diagram, the timing of an embodiment of a two-level buck converter operating at a 50% duty cycle is shown. The bottom two timing diagrams illustrate the operation of an embodiment of a three level buck converter with duty cycles of less than 50% and greater than 50% are shown. 
     In the two-level buck example at the top of the diagram, nodes pg and ng correspond to the gate terminals of transistor P 1  and N 1 , respectively, of the embodiment of two-level buck converter  102  shown in  FIG. 2 . The voltage on node lx 1  resulting from these switching states is also illustrated. When pg and ng are both low, transistor P 1  is active and N 1  is inactive. The voltage on lx 1  is thus pulled up toward Vdd. When pg and ng are both high, transistor P 1  is turned off while transistor N 1  is turned on. The voltage on lx 1  is thus pulled down toward ground/Vss. 
     With respect to the illustrations directed to the three-level buck converter, it is noted that the widths of the pulses depicted are not necessarily to scale. Nevertheless, the states shown are those through which the circuit progresses for their respectively labeled duty cycle. 
     The three-level states corresponding to the output of three-level buck converter  204  are as follows. A first state, SA, corresponds to node lx 2  being equal to Vdd−VCfly (VCfly being the voltage across capacitor Cfly) with the flow of current being from Vdd, through Cfly and L 2  to the output node Vout. The SB state correspond to lx 2  being equal to Vss, with the current path from Vss, through L 2 , to Vout. The SC state corresponds to the voltage across lx 2  being equal to the voltage across Cfly, with the current path being from Vss, through Cfly and L 2  to Vout. The SD state corresponds to the voltage on lx 2  being equal to Vdd, with the current path existing from Vdd, through L 2 , to Vout. The states may also be described in terms of particular transistor configurations (on/off). For example, the SB state corresponds to transistors N 2  and N 3  being turned on, with P 2  and P 3  turned off (and thus, the pull-down path is fully activated). Similarly, the SD state corresponds to transistors N 2  and N 3  being turned off while P 2  and P 3  are both turned on (and thus, the pull-up path being fully activated). These transistor configurations are described in the timing diagrams in conjunction with their respective states. 
     In the timing diagram corresponding to a duty cycle of less than 50%, the voltages on node lx 2  varies between a low of Vss and Vdd−VCfly, with VCfly being the third voltage level, which is less than Vdd/2 in this case. The SA state occurs when both transistors P 2  and N 2  are on, while P 3  and N 3  are off. The next state, SB, occurs with both P 2  and P 3  turned off, while N 2  and N 3  are both turned on. The SC state follows, and occurs when P 2  and N 2  are turned off, while P 3  and N 3  are turned on. The final state in the cycle is SB. Thereafter, the cycle may repeat as operation continues. 
     In the timing diagram corresponding to a duty cycle greater than 50%, the cycle is as follows. The first state produced in the cycle is the SD cycle, which occurs with P 2  and P 3  on, while N 2  and N 3  are off. The next state is the SA state, with P 2  and N 2  on, while P 3  and N 3  are off. The SD state follows the SA state. The final state in this sequence is the SC state, which occurs with transistors P 2  and N 2  being turned off, while P 3  and N 3  are turned on. 
       FIG. 4  is a block diagram of another embodiment of a voltage regulator having multiple instances of both a two-level and N-level buck converters. In the embodiment shown, voltage regulator  400  includes two instances of a two-level buck converter  102  and two instances of an N-level buck converter  104 . Generally speaking, a voltage regulator in accordance with the present disclosure may be implemented with any number of 2-level buck converters  102  and any number of N-level buck converters. Furthermore, the control circuit  106  in such embodiments may independently control the switching sequences for each of the buck converters may be switched independent of one another. Thus, the two-level buck converters may be switches using different duty cycles from one another. Similarly, the two N-level buck converters  104  may be switched with different duty cycles with respect to each other. Any number of two-level buck converters  102  and any number of N-level buck converters may be implemented in various embodiments, according to the specifications of the particular implementation in which voltage regulator  400  is used. 
       FIG. 5  is another embodiment of a voltage regulator. In this particular embodiment, in addition to multiple two-level buck converters  102 , an N-level buck converter  104  and an M-level buck converter  504  are also included. In this example, M is also an integer number of three or more, and is also different from N. For example, N could equal three while M could equal five, and thus a corresponding embodiment would include both a three-level and a five-level buck converter as well as the two-level buck converters  102  shown here. Furthermore, embodiments that includes multiple instances of the N-level buck converter  104 , M-level buck converter  504 , or both (in addition to the two-level buck converters  102 ) are also possible and contemplated. 
       FIG. 6  is a flow diagram illustrating operation of one embodiment of a hybrid buck converter. Method  600  may be performed using various embodiments of a voltage regulator as discussed above and illustrated in  FIGS. 1-5 . Embodiments of a voltage regulator not explicitly discussed in this disclosure may fall within the scope of this disclosure. 
     Method  600  includes providing a first current on an output node, wherein the first current is generated by a first two-level buck converter alternatively generating one of two voltage levels and converting the two voltage levels into the first current using a first inductor (block  605 ). The method further includes providing a second current on the output node, wherein the second current is generated by a first N-level buck converter generating one of N voltage levels in a predefined sequence and converting the N voltage levels into the second current using a second inductor, wherein N is an integer value of at least three (block  610 ). During performance of the method, a control circuit controls respective duty cycles of transistors in each of the first two-level buck converter and the first N-level of the buck converter based on a feedback signal based on a voltage present on the output node and a desired voltage (block  615 ). 
     In various embodiments, the method includes the control circuit varying a duty cycle of activation of various transistors in the first two-level buck converter and the first N-level buck controller. In some embodiments a plurality of two-level buck converters provide respective currents on the output node, the plurality of two-level buck including the first two-level buck converter. Embodiments are also possible and contemplated in which a plurality of N-level buck converters provide respective currents on the output node, the plurality of N-level buck converters including the first N-level buck converter, as well as those having at least one M-level buck converter providing a respective current on the output node, wherein M is an integer value of three or more, and where M is not equal to N. 
     Turning next to  FIG. 7 , a block diagram of one embodiment of a system  150  is shown. In the illustrated embodiment, the system  150  includes at least one instance of an integrated circuit  10  coupled to external memory  158 . The integrated circuit  10  may include a memory controller that is coupled to the external memory  158 . The integrated circuit  10  is coupled to one or more peripherals  154  and the external memory  158 . A power supply  156  is also provided which supplies the supply voltages to the integrated circuit  10  as well as one or more supply voltages to the memory  158  and/or the peripherals  154 . In some embodiments, more than one instance of the integrated circuit  10  may be included (and more than one external memory  158  may be included as well). 
     The peripherals  154  may include any desired circuitry, depending on the type of system  150 . For example, in one embodiment, the system  150  may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals  154  may include devices for various types of wireless communication, such as WiFi, Bluetooth, cellular, global positioning system, etc. The peripherals  154  may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals  154  may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system  150  may be any type of computing system (e.g. desktop personal computer, laptop, workstation, tablet, etc.). 
     In various embodiments, integrated circuit  10  and/or peripherals  154  may include implementations of the hybrid DC-DC converters discussed above in  FIGS. 1-5 . 
     The external memory  158  may include any type of memory. For example, the external memory  158  may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. The external memory  158  may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Metadata:
Filing Date: 20210104
Publication Date: 20220830
Grant Date: 20220830
Priority Date: 20190913
Inventors: FLETCHER, JAY B.
Assignee: APPLE INC
CPC Classifications: [{"code": "H02M3/1584", "inventive": true, "first": false, "tree": "[]"}, {"code": "H02M3/156", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02M3/1584", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02M3/1584", "inventive": true, "first": true, "tree": "[]"}, {"code": "H02M1/08", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M3/07", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M3/158", "inventive": false, "first": false, "tree": "[]"}, {"code": "H02M1/04", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 72039664