PATENT DOCUMENT

Publication Number: US-9781823-B2
Application Number: US-201615273110-A
Country: US
Kind Code: B2

Title: Trace border routing

Abstract:
The border routing of conductive traces in devices, such as displays, touch sensor panels, and touch screens, to improve border area space usage, thereby reducing device size, and to reduce trace resistance, thereby improving device operation, is disclosed. The conductive traces can form a staggered stair-step configuration in the device border area, in which the average widths of the traces can be different from each other and each trace can have segments with different widths. The conductive traces can be coupled to an active area of the device to transmit signals to and from the active area in accordance with a device operation. The varying widths can help improve the border area space usage, reduce trace resistance, and reduce the differences in resistance between traces.

Claims:
What is claimed is: 
     
       1. A display comprising:
 an active area configured to display data; 
 a border area located outside of the active area, the border area including a first region and a second region; 
 a plurality of rows in the active area, each row forming at least a portion of one or more display pixels; 
 a connector in the second region of the border area; and 
 multiple routing traces in a plane disposed along a length of the plane, each routing trace electrically connected to one of the plurality of rows in the first region and configured to route a signal from the one of the plurality of rows to the connector, 
 the multiple routing traces including:
 first and second routing traces located in the first and second regions, the first routing trace located closer to the active area than the second routing trace, 
 wherein the first routing trace includes one or more bends in the second region, 
 wherein a number of bends of the first routing trace in the second region is greater than a number of bends of other routing traces in the second region. 
 
 
     
     
       2. The display of  claim 1 , wherein resistances of the multiple routing traces match. 
     
     
       3. The display of  claim 1 , wherein the one or more bends of the first routing trace include sections with greater slope than one or more bends of the second routing trace. 
     
     
       4. The display of  claim 3 , wherein one of the multiple routing traces is located adjacent to and has one less bend than the first routing trace in the second region. 
     
     
       5. The display of  claim 1 , wherein a number of bends of the multiple routing traces decreases from the first routing trace to the second routing trace. 
     
     
       6. The display of  claim 1 , wherein the second routing trace has no bends in the second region. 
     
     
       7. The display of  claim 1 , wherein a length of the first routing trace in the second region is greater than a length of an adjacent routing trace in the second region. 
     
     
       8. The display of  claim 1 , wherein lengths of the multiple routing traces decrease from the first routing trace to the second routing trace. 
     
     
       9. The display of  claim 1 , wherein at least one bend of the first routing trace borders a third region, included in the second region, and further wherein at least a portion of a bend of an adjacent routing trace is located in the third region. 
     
     
       10. The display of  claim 1 , wherein each bend includes two straight sections intersecting at non-orthogonal angles. 
     
     
       11. The display of  claim 1 , wherein the first routing trace includes a first bend and a second bend, the second bend located closer to the connector and including a smaller angle than the first bend. 
     
     
       12. A touch sensor panel comprising:
 an active area configured to display data; 
 a border area located outside of the active area, the border area including a first region and a second region; 
 multiple rows of touch pixels in the active area and configured to sense a touch or hover; 
 a connector in the first region of the border area; and 
 multiple routing traces in a plane disposed along a length of the plane, each routing trace electrically connected to one of the multiple rows of touch pixels in the first region and configured to route a signal from the one of the plurality of rows to the connector, 
 the multiple routing traces including:
 first and second routing traces located in the first and second regions, the first routing trace located closer to the active area than the second routing trace, 
 wherein the first routing trace includes one or more bends in the second region, 
 wherein a number of bends of the first routing trace in the second region is greater than a number of bends of other routing traces in the second region. 
 
 
     
     
       13. The touch sensor panel of  claim 12 , wherein the one or more bends of the first routing trace include sections with greater slope than one or more bends of the second routing trace. 
     
     
       14. The touch sensor panel of  claim 12 , wherein the second routing trace has no bends in the second region. 
     
     
       15. The touch sensor panel of  claim 12 , wherein a length of the first routing trace in the second region is greater than a length of an adjacent routing trace in the second region. 
     
     
       16. The touch sensor panel of  claim 12 , wherein the first routing trace includes a first bend and a second bend, the second bend located closer to the connector and including a smaller angle than the first bend. 
     
     
       17. The touch sensor panel of  claim 12 , wherein the multiple routing traces are coupled to both sides of the touch sensor panel to drive the touch sensor panel from both sides to cause the touch sensor panel to sense the touch or hover. 
     
     
       18. A method of routing conductive traces in a border area of a device, the method comprising:
 routing the conductive traces in a plane disposed along a length of the plane, each routing trace electrically connected to one or more touch pixels in a first region of the border area and configured to route a signal from the one or more touch pixels to the connector, the connector located in a second region of the border area, 
 the routing comprising:
 locating first and second conductive traces in the first and second regions of the border area, 
 creating one or more bends in the first conductive traces in the second region of the border area, wherein a number of bends of the first routing trace in the second region is greater than a number of bends of other routing traces in the second region, and 
 locating the first conductive trace closer to an active area of the device than the second conductive trace. 
 
 
     
     
       19. The method of  claim 18 , further comprising:
 creating one or more bends in the second conductive trace. 
 
     
     
       20. The method of  claim 18 , further comprising:
 creating one or more straight conductive traces; and 
 locating the first routing trace closer to the active area of the device than the one or more straight conductive traces.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 13/007,493, filed Jan. 14, 2011 and published as U.S. Patent Publication No. 2012-0092273 on Apr. 19, 2012, which claims the benefit of U.S. Provisional Application No. 61/393,818, filed Oct. 15, 2010, the disclosures of which are herein incorporated by reference in their entirety for all intended purposes. 
    
    
     FIELD 
     This relates generally to conductive traces and more particularly to improved routing of conductive traces in a border area of a device. 
     BACKGROUND 
     Many types of devices are presently available for performing operations in a computing system, such as displays, touch sensor panels, and touch screens. Displays can display graphics and/or text information to a user. Touch sensor panels can sense an object, e.g., the user&#39;s hand, touching or hovering over the panel, causing the computing system to perform some operation based on the touch or hover. Touch screens can include both a display and a touch sensor panel and can allow a user to perform various functions by touching or hovering over the touch sensor panel at a location dictated by a user interface (UI) being displayed by the display, causing the computing system to perform some operation based on the touch or hover and in accordance with the graphics and/or text information appearing at the time of the touch or hover. 
     Portable computing systems are becoming increasingly popular because of their ease and versatility of operation, mobility, and declining price. As such, it is desirable to produce a smaller, thinner system, while maintaining easy and versatile operation. 
     SUMMARY 
     This relates to border routing of conductive traces in devices, such as displays, touch sensor panels, and touch screens, to improve border area space usage, thereby reducing device size, and to reduce trace resistance, thereby improving device operation. The conductive traces can form a staggered stair-step configuration in which the average widths of the traces can be different from each other and each trace can have segments with different widths. The conductive traces can be coupled to an active area of the device to transmit signals to and from the active area in accordance with an operation of the device. The varying widths can help improve the border area space usage, reduce trace resistance, and reduce the differences in resistance between traces. This border routing can advantageously provide smaller border areas and improved device performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an exemplary device having border routing of conductive traces according to various embodiments. 
         FIG. 2  illustrates an exemplary border routing of the conductive traces of  FIG. 1  according to various embodiments. 
         FIG. 3  illustrates an exemplary touch screen having border routing of common electrode voltage lines according to various embodiments. 
         FIG. 4  illustrates an exemplary touch sensor panel having border routing of stimulation signal lines according to various embodiments. 
         FIG. 5  illustrates an exemplary display having border routing of AC common electrode voltage lines according to various embodiments. 
         FIG. 6  illustrates an exemplary one chip display having border routing of gate signal lines according to various embodiments. 
         FIG. 7  illustrates an exemplary display with gate drivers having border routing of gate driver control lines according to various embodiments. 
         FIG. 8  illustrates an exemplary border routing of the conductive traces of  FIG. 1  with extended distal ends according to various embodiments. 
         FIGS. 9 a  through 9 c    illustrate exemplary stackups of conductive traces that can have border routing according to various embodiments. 
         FIG. 10  illustrates an exemplary mobile telephone having a display that includes border routing of conductive traces according to various embodiments. 
         FIG. 11  illustrates an exemplary digital media player having a display that includes border routing of conductive traces according to various embodiments. 
         FIG. 12  illustrates an exemplary personal computer having a display that includes border routing of conductive traces according to various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description of example embodiments, reference is made to the accompanying drawings in which it is shown by way of illustration specific embodiments that can be practiced. It is to be understood that other embodiments can be used and structural changes can be made without departing from the scope of the various embodiments. 
     This relates to border routing of conductive traces in devices, such as displays, touch sensor panels, and touch screens, to optimize or otherwise improve border area space usage, thereby reducing device size, and to minimize or otherwise reduce trace resistance, thereby improving device operation. The conductive traces can form a staggered stair-step configuration in which the average widths of the traces can be different from each other and each trace can have segments with different widths. The conductive traces can be coupled to an active area of the device to transmit signals to and from the active area in accordance with a device operation. The varying widths can help optimize or improve the border area space usage, minimize or reduce trace resistance, and minimize or reduce the differences in resistance between traces. This border routing can advantageously provide smaller border areas and improved device performance. 
       FIG. 1  illustrates an exemplary device having border routing of conductive traces according to various embodiments. In the example of  FIG. 1 , electronic device  100  can include active area  110  for performing an operation of the device and border area  120  for routing conductive traces  102  between the active area and signal processing circuitry (not shown). The conductive traces  102  can transmit electrical signals to and from the active area  110  in association with the performing operation. Each conductive trace  102  can be coupled to a particular location of the active area  110  and routed in the border area  120  from that location to the signal processing circuitry. For example, conductive traces  102 - a ,  102 - f  can be coupled to location A of the active area  110  to transmit signals to and from this location and can be routed in the border area  120  to the signal processing circuitry, which is disposed above location E in this example. Conductive traces  102 - b ,  102 - g  can be coupled to location B of the active area  110  to transmit signals to and from this location and can be in the border area  120  from this location up to the signal processing circuitry. Conductive traces  102 - c ,  102 - h  can be coupled to location C of the active area  110  to transmit signals to and from this location and can be routed in the border area  120  from this location up to the signal processing circuitry. Conductive traces  102 - d ,  102 - i  can be coupled to location D of the active area  110  to transmit signals to and from this location and can be routed in the border area  120  from this location up to the signal processing circuitry. Conductive traces  102 - e ,  102 - j  can be coupled to location E of the active area  110  to transmit signals to and from this location and can be routed in the border area  120  from this location up to the signal processing circuitry. 
     Trace resistance can be a function of trace width. Generally, the wider the conductive trace, the lower the resistance. In this example, each trace can be formed to have segments with various widths to reduce the trace&#39;s resistance. Trace resistance can also be a function of trace length. Generally, the longer the conductive trace, the higher the resistance. In this example, conductive traces  102 - a ,  102 - f  are the longest traces, conductive traces  102 - e ,  102 - j  are the shortest traces, and the other conductive traces have lengths therebetween. Since different trace lengths can result in different resistances and hence different transmission rates (among other undesirable conditions), the widths of the conductive traces  102  can be formed to substantially reduce or eliminate the differences in resistance between the traces. In this example, the segment widths in each trace can be formed to be different from the segment widths in another trace based on how much resistance difference needs to be reduced or eliminated. The trace widths can also be formed to make optimal use of the width of the border area  120  in accordance with the number of traces present at any location along the length of the border area. Accordingly, the trace widths can be formed to reduce the trace&#39;s resistance, minimize resistance differences between traces, and optimize border area space for the traces and any other electrical requirements. 
     As such, looking at the right-side border area  120 , at location A where only one conductive trace  102 - a  is present, the trace width can be formed to essentially fill the border area space and reduce the trace&#39;s resistance. At location B, two conductive traces  102 - a ,  102 - b  are present, so the widths of the two traces can be formed to optimize border area space between the two traces while reducing each trace&#39;s resistance and resistance differences between the traces. At location C, three conductive traces  102 - a ,  102 - b ,  102 - c  are present, so the widths of the three traces can be formed to optimize border area space between the three traces and to reduce each trace&#39;s resistance and resistance differences between the traces. At location D where four conductive traces  102 - a ,  102 - b ,  102 - c ,  102 - d  are present, the trace widths can be formed to optimize border area space between the four traces and to reduce each trace&#39;s resistance and resistance differences between the traces. At location E, all five conductive traces  102 - a ,  102 - b ,  102 - c ,  102 - d ,  102 - e  are present, so the widths can be formed to optimize border area space between the five traces and to reduce each trace&#39;s resistance and resistance differences between the traces. The result can be a staggered stair-step configuration of the conductive traces  102 . 
     In this stair-step configuration example of  FIG. 1 , conductive trace  102 - a  can have five segments (one at each location A through E) in which one or more of the segments have different widths. For example, the width at location A can be widest, the width at adjacent location B can be somewhat narrower, the width at adjacent location C can be even narrower, the width at adjacent location D can be narrower still, and the width at adjacent location E can be narrowest, resulting in a stair-step configuration for trace  102 - a . Conductive trace  102 - b  can have four segments (one at each location B through E) in which one or more of the segments have different widths, resulting in its stair-step configuration. Conductive trace  102 - c  can have three segments (one at each location C through E) in which one or more of the segments have different widths, forming its stair-step configuration. Conductive trace  102 - d  can have two segments (one at each location D and E) in which the two segments can have different widths in the stair-step configuration. The same configuration can be applicable for conductive traces  102 - f  through  102 - j.    
     Moreover, in this stair-step configuration example of  FIG. 1 , at location B, the widths of the segments for conductive traces  102 - b ,  102 - a  can be different. At location C, one or more of the widths of the segments for conductive traces  102 - c ,  102 - b ,  102 - c  can be different. At location D, one or more of the widths of the segments for conductive traces  102 - d ,  102 - c ,  102 - b ,  102 - a  can be different. At location E, one or more of the widths of the segments for conductive traces  102 - e ,  102 - d ,  102 - c ,  102 - b ,  102 - a  can be different. The same configuration can be applicable for conductive traces  102 - f  through  102 - j.    
     As a result, in some embodiments, the average widths (i.e., the average of the segment widths) of each trace  102  on one side of the border area  120  can be different. Whereas, each pair of conductive traces  102  coupled to the same location on opposite sides of active area  110  can have the same or similar average width. Additionally, each pair can have the same or similar corresponding individual segment widths. 
     For the conductive traces that span multiple locations, e.g., traces  102 - a ,  102 - b ,  102 - c ,  102 - d ,  102 - f ,  102 - g ,  102 - h ,  102 - i , the widths of the trace segments at all the other locations can be taken into account when setting a segment width at a particular location to ensure that the trace&#39;s resistance is reduced to an optimal or preferable level. For example, conductive trace  102 - a  spans all five locations A through E. As such, to ensure that the trace&#39;s resistance is reduced to an optimal or preferable level, when determining the segment width at location E, the previously determined segment widths at locations A through D can be used to assess what segment width at location E would result in the optimal or preferred resistance. 
     Determining appropriate trace segment widths to be formed at each location can be an iterative process, particularly when there are multiple electrical requirements to be met, e.g., to minimize a trace&#39;s resistance, while minimizing resistance differences between traces, while optimizing border area space. As such, there can be tradeoffs between how low the trace resistance can be, how many of the traces can have matching or near matching resistances, and how little of the border area space can be used. Ideally, a goal can be to find the maximum resistance among the traces within the width constraints of the border area and then determine widths of the other traces to be at or below that resistance within the width constraints of the border area. In some embodiments, an optimization algorithm can be used to balance these (and any other) electrical requirements and calculate optimal or preferable segment widths for each trace at each location. These calculated trace segment widths can then be formed in the border areas of the device. 
     Optimizing the border area space does not necessarily require that all the border area be filled by the trace widths. Rather, in some embodiments, trace widths can be narrower than the border area optimum so as to avoid parasitic coupling with proximate components in the active area. Or in some embodiments, larger spacing between the active area and the traces can be made to avoid the parasitic coupling. 
     In this example of  FIG. 1 , the conductive traces  102  are shown in the border area  120  on both sides of the active area  110 . However, it is to be understood that the conductive traces  102  can be in the border area on only one side of the active area  110 . That way, electrical signals can be transmitted to and from the active area  110  on one side in associated with the performing operation. 
     Also, each active area location has a conductive trace coupled thereto. However, it is to be understood that other coupling are also possible. For example, the conductive traces  102  can be interleaved on both sides of the active area  110 , such that some conductive traces  102  can couple at locations A, C, and E in the border area  120  on one side of the active area  110  and other conductive traces can couple at locations B and D in the border area on the other side of the active area. That way, more border space can be available for widening the traces. The interleaved conductive traces  102  on both sides can have the stair-step configuration and can form widths to reduce trace resistance and to optimize border area space, as previously described. 
       FIG. 2  illustrates a close up view of the border routing of the conductive traces of  FIG. 1  according to various embodiments. In the example of  FIG. 2 , at location E, the segment widths w 1 , w 2 , w 3 , w 4 , w 5  (not drawn to scale) of the conductive traces  102  can be formed as previously described. In some embodiments, the widths can be different based what&#39;s needed to reduce the trace&#39;s resistance. For example, the shortest trace  102 - e  can form a narrower width w 1  to overcome a smaller trace resistance. The longest trace  102 - a  can also form a narrower width w 5  because much of the trace&#39;s resistance reduction has been accounted for in the trace widths at other locations A-D. Whereas trace  102 - d  can have a wider width w 2  than trace  102 - e  to overcome a larger trace resistance. In alternate embodiments, the widths can be the same. At location D, the segment widths w 6 , w 7 , w 8 , w 9  (not drawn to scale) of the conductive traces  102  can also be formed as previously described. In some embodiments, the widths can be different based on what&#39;s needed to reduce the trace&#39;s resistance. In alternate embodiments, the widths can be the same. For those traces that span locations D and E, their widths in the two locations can be the same or different based on what&#39;s needed to reduce the trace&#39;s resistance. For example, trace  102 - d  can have either different or same widths w 2 , w 6 . 
       FIGS. 3 through 7  illustrate exemplary devices having border routing of conductive traces according to various embodiments. In the example of  FIG. 3 , touch screen  300  can have border routing of common electrode voltage (Vcom) lines  302  for driving active area  310  according to various embodiments. The Vcom line  302  can have similar structures to conductive traces  102  of  FIG. 1 . The active area  310  of the touch screen  300  can include multiple rows  324  of integrated touch-display pixels. Each Vcom line  302  can transmit a voltage from Vcom supply  330  to a corresponding row  324  of pixels to stimulate the pixels to sense a touching or hovering object at the active area  310 . As a consequence of reducing resistance in the border traces, this border routing can substantially reduce or eliminate crosstalk in sensed touch or hover signals in the touch screen  300  caused by stray display signals undesirably coupling with the Vcom lines  302  while sensing the touch or hover. 
     In the example of  FIG. 4 , touch sensor panel  400  can have border routing of stimulation lines  402  for driving touch sensing area  410  according to various embodiments. The stimulation lines  402  can have similar structures to conductive traces  102  of  FIG. 1 . The touch sensing area  410  can include multiple rows  424  of touch pixels. Each stimulation line  402  can transmit a stimulation signal from stimulation circuitry  430  to a corresponding row  424  of touch pixels to stimulate the pixels to sense a touching or hovering object at the touch sensing area  410 . Here, the stimulation lines  402  can form in the border area  420  on one side of the touch sensing area  410 . This border routing can substantially reduce or eliminate undesirable parasitic capacitance and/or resistance that can adversely affect the sensed touch or hover signals. 
     In some embodiments, the touch sensor panel  400  can be disposed on a display to form a touch screen. The panel  400  can have similar border routing of the stimulation lines  402  to drive the panel. In addition to reducing capacitance and resistance, this border routing can also substantially reduce or eliminate crosstalk caused by the display in sensed touch or hover signals. 
     In the example of  FIG. 5 , display  500  can have border routing of AC driven Vcom lines  502  for driving display area  510  according to various embodiments. The AC Vcom lines  502  can have similar structures to conductive traces  102  of  FIG. 1 . The display area  510  can include multiple rows  524  of display pixels. Each AC Vcom line  502  can transmit an AC voltage from Vcom supply  530  to drive the pixels to display graphics and/or text information. This border routing can effectively replace a thick conductive trace surrounding the display area in traditional AC Vcom displays used to ensure that the applied voltage is uniform across the display area. As a result, the border routing can optimize border area space as well as ensure the uniformity of the applied voltage. 
     In the example of  FIG. 6 , one chip display  600  can have border routing of gate signal lines  602  for driving display area  610  according to various embodiments. The signal lines  602  can have similar structures to conductive traces  102  of  FIG. 1 . The display area  610  can include multiple gate lines  635  in display pixels to drive the pixels to display graphics and/or text information. Each gate signal line  602  can transmit a gate signal from display driver  630  to drive the pixels. Here, the gate signal lines  602  can form in the border area  620  on one side of the display area  610 . This border routing can optimize border area space as well as reduce the signal lines&#39; resistance. 
     In the example of  FIG. 7 , display  700  can have border routing of gate driver control lines  702  for driving gate drivers  740  according to various embodiments. The control lines  702  can have similar structures to conductive traces  102  of  FIG. 1 . The gate drivers  740  can drive gate lines  735  in display pixels to drive the pixels to display graphics and/or text information. Each gate driver  740  can be coupled to a corresponding gate line  735 . Printed circuit board (PCB)  730  can transmit signals along control lines  702  to control the gate drivers  740  according to the display requirements. Here, the control lines  702  can form in the border area  720  on one side of the display area  710 . This border routing can optimize border area space as well as reduce the control lines&#39; resistance. 
     It is to be understood that border routing is not limited to the devices of  FIG. 3 through 7 , but can include any devices having border area space constraints and/or conductive trace resistance needs according to various embodiments. 
     As described previously, trace resistance can be a function of trace length, where the longer the trace, the higher the resistance. In  FIG. 1 , the disparity between the lengths of conductive traces  102 - e  and  102 - a  is significant such that it can be difficult to substantially match the resistances of the two traces (if indeed such a match is an electrical requirement of the device).  FIG. 8  illustrates a close up view of an exemplary border routing of the conductive traces of  FIG. 1  that addresses this issue. In the example of  FIG. 8 , conductive trace  102 - e  can have extra length (extensions to the traces having one or more bends) in the border area above the active area  110  to increase its length and thereby its resistance closer to that of the other traces. Conductive traces  102 - d  and  102 - c , the next shorter traces, can similarly have extra length (though not as much as trace  102 - e ) in the border area above the active area  110  to increase its resistance closer to that of the other traces. Conductive traces  102 - a  and  102 - b , the longer traces, can omit extra length since their resistance can more likely be the highest of the traces. Connector  850  can connect the traces  102  to signal processing circuitry (not shown). 
       FIGS. 9 a  through 9 c    illustrate exemplary stackups of conductive traces that can have border routing according to various embodiments. The thickness and material makeup of the conductive traces can be varied to meet the electrical requirements of the device. In the example of  FIG. 9 a   , a single layer of conductive material having a thickness T can be used, for example, for shorter traces to match longer traces&#39; resistance. In the example of  FIG. 9 b   , a single layer of conductive material having a thickness t can be used, for example, for longer traces to reduce the traces&#39; resistance. Alternatively, a single layer of material with higher resistivity can be used in some instances and a single layer of material with lower resistivity can be used in other instance. In the example of  FIG. 9 c   , a multi-layer stackup having different materials having higher resistivity, lower resistivity, or both can be used as an alternative to adjusting the thickness of the trace. Example trace materials include Molybdenum/Niobium (Mo/Nb), which has higher resistivity, and Aluminum/Neodymium (Al/Nd), which has lower resistivity. 
       FIG. 10  illustrates exemplary mobile telephone  1000  that can include touch sensor panel  1024  and display device  1036 , the touch sensor panel and/or the display device including conductive traces formed in their border areas according to various embodiments. 
       FIG. 11  illustrates exemplary digital media player  1100  that can include touch sensor panel  1124  and display device  1136 , the touch sensor panel and/or the display device including conductive traces formed in their border areas according to various embodiments. 
       FIG. 12  illustrates exemplary personal computer  1200  that can include trackpad  1224  and display  1236 , the trackpad and/or the display including conductive traces formed in their border areas according to various embodiments. 
     The mobile telephone, media player, and personal computer of  FIGS. 10 through 12  can be more compact and have improved performance with conductive trace border routing according to various embodiments. 
     Although embodiments have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the various embodiments as defined by the appended claims.

Metadata:
Filing Date: 20160922
Publication Date: 20171003
Grant Date: 20171003
Priority Date: 20101015
Inventors: LYON BENJAMIN B.
CHANG SHIH-CHANG
GRUNTHANER MARTIN PAUL
Assignee: APPLE INC
CPC Classifications: [{"code": "H05K1/0242", "inventive": true, "first": true, "tree": "[]"}, {"code": "H05K2201/09272", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K1/0265", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/0412", "inventive": true, "first": false, "tree": "[]"}, {"code": "Y10T29/49155", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K2201/0784", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K2201/09727", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/2092", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F3/0416", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F2203/04108", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K1/0242", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/04164", "inventive": true, "first": true, "tree": "[]"}, {"code": "H05K2201/0784", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K1/0265", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/04164", "inventive": true, "first": true, "tree": "[]"}, {"code": "Y10T29/49155", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K2201/09727", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F3/0412", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/2092", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K2201/09272", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F2203/04108", "inventive": false, "first": false, "tree": "[]"}, {"code": "Y10T29/49155", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K2201/0784", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F3/0412", "inventive": true, "first": false, "tree": "[]"}, {"code": "H05K2201/09727", "inventive": false, "first": false, "tree": "[]"}, {"code": "H05K1/0265", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 45933723