PATENT DOCUMENT

Publication Number: US-10263032-B2
Application Number: US-201615056752-A
Country: US
Kind Code: B2

Title: Photodiode with different electric potential regions for image sensors

Abstract:
An image sensor pixel is disclosed. The pixel may include a photodiode having a first region with a first potential and a second region with a second, higher potential, with the second region being offset in depth from the first region in a semiconductor chip. A storage node may be positioned at substantially the same depth as the second region of the photodiode. A storage gate may be operable to transfer charge between the photodiode and the storage node.

Claims:
What is claimed is: 
     
       1. An image sensor pixel comprising:
 a photosensitive region formed along a surface of a semiconductor chip; 
 a storage node below and at least partially overlapping with the photosensitive region; and 
 a second region configured to transfer charge from the photosensitive region to the storage node; 
 wherein: 
 the photosensitive region is doped with a first concentration of a dopant; and 
 the second region is doped with a second concentration of the dopant that is greater than the first concentration. 
 
     
     
       2. The image sensor pixel of  claim 1 , wherein the storage node is positioned entirely beneath the photosensitive region. 
     
     
       3. The image sensor pixel of  claim 1 , further comprising a floating diffusion node configured to receive a charge from the storage node. 
     
     
       4. The image sensor pixel of  claim 3 , wherein:
 the floating diffusion node is coupled to the storage node by a transfer gate that is configured to reset the storage node when activated; and 
 the storage node is coupled to the photosensitive region by a storage gate operable to selectively transfer charge from the photosensitive region to the storage node. 
 
     
     
       5. The image sensor pixel of  claim 3 , wherein:
 the surface is a first surface of the semiconductor chip; 
 the storage node is formed along a second surface of the semiconductor chip opposite to the first surface; and 
 the floating diffusion node is positioned proximate to the second surface of the semiconductor chip. 
 
     
     
       6. The image sensor pixel of  claim 3 , wherein the floating diffusion node is positioned on a separate chip that is distinct from the semiconductor chip. 
     
     
       7. The image sensor pixel of  claim 1 , further comprising a shielding region configured between the photosensitive region and the storage node. 
     
     
       8. An image sensor comprising:
 a photodiode having a photosensitive first region formed along a first surface of a semiconductor chip and a second region formed below a portion of the first region and extending to proximate a second surface opposite to the first surface of the semiconductor chip; 
 a storage node formed in the semiconductor chip at a depth below and at least partially overlapping with the first region; and 
 a storage gate coupled to a second surface of the semiconductor chip opposite to the first surface and configured to pump a charge from the second region to the storage node; 
 wherein: 
 the first region is doped with a first concentration of a dopant; and 
 the second region is doped with a second concentration of the dopant, the second concentration being greater than the first concentration. 
 
     
     
       9. The image sensor of  claim 8 , wherein the storage gate is configured to selectively increase a potential of the second region in response to an applied voltage. 
     
     
       10. The image sensor of  claim 8 , wherein a first inherent potential of the first region is approximately equal to a second inherent potential of the second region. 
     
     
       11. The image sensor of  claim 8 , wherein the storage node is bifurcated into two regions having different levels of doping. 
     
     
       12. The image sensor of  claim 8 , wherein the surface is a first surface of the semiconductor chip; and
 the storage node is pinned to the second surface. 
 
     
     
       13. The image sensor of  claim 12 , wherein:
 pinning the storage gate creates a virtual barrier for charge entering from the storage gate until an applied voltage to the storage gate is reduced. 
 
     
     
       14. The image sensor of  claim 8 , wherein the second region is not pinned to the second surface of the semiconductor chip. 
     
     
       15. The image sensor of  claim 8 , wherein:
 the storage node is a first storage node; 
 the depth of the first storage node is a first depth; 
 the storage gate is first storage gate; and 
 the image sensor further comprises:
 a second storage node formed in the semiconductor chip at a second depth below and at least partially overlapping with the first region; and 
 a second storage gate positioned on the second surface of the semiconductor chip and configured to pump a charge from the second region to the second storage node. 
 
 
     
     
       16. The image sensor of  claim 15 , wherein the second storage node is located opposite to the first storage node with respect to the second region. 
     
     
       17. An image pixel comprising:
 a photodiode having a photosensitive first region positioned along a first surface of a semiconductor chip and a second region positioned below a portion of the first region; and 
 a storage node positioned proximate to a second surface of the semiconductor chip opposite to the first surface and at least partially overlapping the first region of the photodiode, 
 wherein the storage node is bifurcated into a first region having a first doping level and a second region having a second doping level that is different than the first doping level. 
 
     
     
       18. The image pixel of  claim 17 , wherein the storage node is coupled to the photodiode by a storage gate that is configured to pump a charge from the photodiode to the storage node in response to an applied voltage. 
     
     
       19. The image pixel of  claim 17 , wherein the bifurcated storage node is pinned to the second surface and forms a virtual barrier that resists charge from entering the storage node until the applied voltage is reduced. 
     
     
       20. The image pixel of  claim 17 , further comprising:
 a floating diffusion node that is configured to receive a charge from the storage node; and 
 a transfer gate coupling the storage node to the floating diffusion node and configured to reset the storage mode when activated.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 13/783,536, filed Mar. 4, 2013, entitled “Photodiode with Different Electric Potential Regions for Image Sensors”, which is incorporated by reference in its entirety as if fully disclosed herein. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to image sensors, and, more specifically, to a photodiode with different electric potential regions for use in an image sensor 
     BACKGROUND 
     Many widely-used image sensors include global-shutter pixels because of their high efficiency and lack of a blur as compared to rolling-shutter pixels. Global shutter pixels typically include a storage node, separate from the photodiode region, where charge generated during a previous integration frame can be stored and subsequently read out. All of the pixels in a global shutter image sensor typically transfer charge generated in their respective photodiodes to their respective storage nodes ‘globally,’ which eliminates the blur caused by the row-by-row exposure and readout in rolling shutter pixels. The global shutter storage nodes can be read out when convenient, such as while the photodiode is integrating charge for a subsequent frame. 
     The storage node in global shutter pixels is usually located on the same surface of a semiconductor wafer as the photodiode region, and thus typically needs to be shielded in order to maintain the integrity of the charge stored in the storage node. Also, positioning the storage node on the same surface of a semiconductor wafer as the photodiode reduces the amount of surface area of the photodiode that can be exposed to light, and hence reduces the sensitivity of the pixel. 
     SUMMARY 
     One example of the present disclosure may take the form of an image sensor pixel. The image sensor pixel may include a photodiode having a first region with a first potential and a second region with a second, higher potential. The second region may be offset in depth from the first region in a semiconductor chip. A storage node may be positioned at substantially the same depth as the second region of the photodiode, and a storage gate may be operable to selectively transfer charge from the photodiode to the storage node. 
     Another example of the disclosure may take the form of a method of operating an image sensor pixel. The method may include integrating charge in a first region of a photodiode, and funneling charge from the first region of the photodiode to a second region of the photodiode responsive to a potential difference between the first and second regions. The method may also include transferring charge from the second region of the photodiode to a storage node positioned at least partially beneath the first region of the photodiode. 
     Another example of the disclosure may take the form of a method of manufacturing an image sensor pixel. The method may include forming a storage node and a first region of a photodiode on a first surface of a silicon wafer. The method may also include forming a second region of the photodiode on a second surface of the silicon wafer, the second region of the photodiode having a lower concentration of doping than the first region, and the second region of the photodiode at least partially covering the storage node formed on the first surface of the silicon wafer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a front perspective view of an electronic device including one or more cameras. 
         FIG. 1B  is a rear perspective view of the electronic device of  FIG. 1A . 
         FIG. 2  is a simplified block diagram of the electronic device of  FIG. 1A . 
         FIG. 3  is a simplified schematic cross-section view of the electronic device of  FIG. 1A  taken along line  3 - 3  in  FIG. 1A . 
         FIG. 4A  is a simplified diagram of an image sensor architecture for a camera of the electronic device. 
         FIG. 4B  is an enlarged view of a pixel architecture of  FIG. 4A  illustrating a single pixel. 
         FIG. 5  is a simplified schematic view of a pixel cell having a global shutter configuration. 
         FIG. 6A  is a simplified schematic cross-section view of one embodiment of an image sensor pixel. 
         FIG. 6B  is a simplified potential profile of the image sensor pixel shown in  FIG. 6A . 
         FIGS. 7A through 11B  illustrate the operation of the image sensor pixel shown in  FIG. 6A . 
         FIGS. 12A and 12B  illustrate one embodiment of steps for manufacturing the image sensor pixel shown in  FIG. 6A . 
         FIG. 13  is a simplified schematic cross-section view of another embodiment of an image sensor pixel. 
         FIG. 14  is a simplified schematic cross-section view of another embodiment of an image sensor pixel. 
         FIG. 15  is a simplified schematic cross-section view of yet another embodiment of an image sensor pixel. 
     
    
    
     SPECIFICATION 
     Overview 
     In some embodiments disclosed herein, apparatuses and methods for transferring charge from one region of a photodiode to another region of the photodiode in an image sensor are disclosed. The charge may be funneled from a first region to a second region due to different electric potentials in the respective first and second regions, with charge generally flowing to the region with the higher potential. Having two or more regions of a photodiode on a single semiconductor chip may allow for an image pixel to be formed on two sides of the semiconductor chip, with the charge funneling phenomenon being used to transfer charge from one side of the chip (e.g., a backside illuminated photodiode) to another side of the chip (e.g., with transfer transistors and circuitry), thus taking advantage of both sides of the semiconductor chip and increasing the efficiency and size of the pixels without increasing the absolute size of the overall image sensor. 
     Turning now to the figures, an image sensor and an illustrative electronic device for incorporating the image sensor will be discussed in more detail.  FIG. 1A  is a front elevation view of an electronic device  100  including one or more image sensors.  FIG. 1B  is a rear elevation view of the electronic device  100 . The electronic device  100  may include any or all of a first camera  102 , a second camera  104 , an enclosure  106 , a display  110 , and an input/output button  108 . The electronic device  100  may be substantially any type of electronic or computing device, such as, but not limited to, a computer, a laptop, a tablet, a smart phone, a digital camera, a printer, a scanner, a copier, or the like. The electronic device  100  may also include one or more internal components (not shown) typical of a computing or electronic device, such as, but not limited to, one or more processors, memory components, network interfaces, and so on. Examples of such internal components will be discussed with respect to  FIG. 2 . 
     As shown in  FIG. 1 , the enclosure  106  may form an outer surface and protective case for the internal components of the electronic device  100  and may at least partially surround the display  110 . The enclosure  106  may be formed of one or more components operably connected together, such as a front piece and a back piece, or may be formed of a single piece operably connected to the display  110 . 
     The input member  108  (which may be a switch, button, capacitive sensor, or other input mechanism) allows a user to interact with the electronic device  100 . For example, the input member  108  may be a button or switch to alter the volume, return to a home screen, and the like. The electronic device  100  may include one or more input members  108  and/or output members, and each member may have a single input or output function or multiple input/output functions. 
     The display  110  may be operably connected to the electronic device  100  or may be communicatively coupled thereto. The display  110  may provide a visual output for the electronic device  100  and/or may function to receive user inputs to the electronic device  100 . For example, the display  110  may be a multi-touch capacitive sensing screen that may detect one or more user inputs. 
     The electronic device  100  may also include a number of internal components.  FIG. 2  is a simplified block diagram of the electronic device  100 . The electronic device  100  may also include one or more processors  114 , a storage or memory component  116 , an input/output interface  118 , a power source  120 , and one or more sensors  122 , each will be discussed in turn below. 
     The processor  114  may control operation of the electronic device  100 . The processor  114  may be in communication, either directly or indirectly, with substantially all of the components of the electronic device  100 . For example, one or more system buses  124  or other communication mechanisms may provide communication between the processor  114 , the cameras  102 ,  104 , the display  110 , the input member  108 , the sensors  122 , and so on. The processor  114  may be any electronic device cable of processing, receiving, and/or transmitting instructions. For example, the processor  114  may be a microprocessor or a microcomputer. As described herein, the term “processor” is meant to encompass a single processor or processing unit, multiple processors, or multiple processing units, or other suitably configured computing element(s). 
     The memory  116  may store electronic data that may be utilized by the electronic device  100 . For example, the memory  116  may store electrical data or content e.g., audio files, video files, document files, and so on, corresponding to various applications. The memory  116  may be, for example, non-volatile storage, a magnetic storage medium, optical storage medium, magneto-optical storage medium, read only memory, random access memory, erasable programmable memory, or flash memory. 
     The input/output interface  118  may receive data from a user or one or more other electronic devices. Additionally, the input/output interface  118  may facilitate transmission of data to a user or to other electronic devices. For example, in embodiments where the electronic device  100  is a phone, the input/output interface  118  may be used to receive data from a network, or may be used to send and transmit electronic signals via a wireless or wired connection (Internet, WiFi, Bluetooth, and Ethernet being a few examples). In some embodiments, the input/output interface  118  may support multiple network or communication mechanisms. For example, the network/communication interface  118  may pair with another device over a Bluetooth network to transfer signals to the other device, while simultaneously receiving data from a WiFi or other network. 
     The power source  120  may be substantially any device capable of providing energy to the electronic device  100 . For example, the power source  120  may be a battery, a connection cable that may be configured to connect the electronic device  100  to another power source such as a wall outlet, or the like. 
     The sensors  122  may include substantially any type of sensor. For example, the electronic device  100  may include one or more audio sensors (e.g., microphones), light sensors (e.g., ambient light sensors), gyroscopes, accelerometers, or the like. The sensors  122  may be used to provide data to the processor  114 , which may be used to enhance or vary functions of the electronic device  100 . 
     With reference again to  FIGS. 1A and 1B , the electronic device  100  may also include one or more cameras  102 ,  104  and optionally a flash  112  or light source for the cameras  102 ,  104 .  FIG. 3  is a simplified cross-section view of the first camera  102 , taken along line  3 - 3  in  FIG. 1A . Although  FIG. 3  illustrates the first camera  102 , it should be noted that the second camera  104  may be substantially similar to the first camera  102 . In some embodiments, one camera may include a global shutter configured image sensor and one camera may include a rolling shutter configured image sensor. In other examples, one camera may have an image sensor with a higher resolution than the other. Likewise, it should be appreciated that the structure shown in  FIG. 3  is but one possible structure for either of the first and second cameras. 
     With reference to  FIG. 3 , the cameras  102 ,  104  may include a lens  126  in optical communication with an image sensor  130 . The lens  126  may be operably connected to the enclosure  106  and positioned above the image sensor  130 . The lens  126  may direct or transmit light  128  within its field of view onto a photodiode (discussed in more detail below) of the image sensor  130 . The image sensor  130  may convert light  128  into electrical signals that may represent the light from the captured scene. In other words, the image sensor  130  captures the light  128  optically transmitted via the lens  126  into electrical signals. 
     Image Sensor Architecture 
     An illustrative architecture for the image sensor  130  will now be discussed in more detail.  FIG. 4A  is a simplified schematic of one possible architecture for the image sensor  130 .  FIG. 4B  is an enlarged view of a pixel of the pixel architecture of  FIG. 4A .  FIG. 5  is a simplified schematic view of the pixel of  FIG. 4A . With reference to  FIGS. 4A-5 , the electronic device  100  may include an image processing component having a pixel architecture defining one or more pixels  136  and/or groups of pixel cells  138  (e.g., groups of pixels  136  grouped together to form a Bayer pixel or other set of pixels). The pixel architecture  134  may be in communication with a column select  140  through one or more column output lines  146  and a row select  144  through one or more row select lines  148 . 
     The row select  144  and/or the column select  140  may be in communication with an image processor  142 . The image processor  142  may process data from the pixels  136  and provide that data to the processor  114  and/or other components of the electronic device  100 . It should be noted that in some embodiments, the image processor  142  may be incorporated into the processor  114  or separate therefrom. The row select  144  may selectively activate a particular pixel  136  or group of pixels, such as all of the pixels  136  on a certain row. The column select  140  may selectively receive the data output from select pixels  136  or groups of pixels  136  (e.g., all of the pixels with a particular column). 
     With reference to the simplified schematic of one embodiment of a pixel  136  illustrated in  FIG. 5 , each pixel  136  may include a photodiode  154 . The photodiode  154  may be in optical communication with the lens  126  to receive light transmitted therethrough. The photodiode  154  may absorb light and convert the absorbed light into an electrical signal. The photodiode  154  may be an electron-based photodiode or a hole-based photodiode. Additionally, it should be noted that the term “photodiode,” as used herein, is meant to encompass substantially any type of photon or light detecting component, such as a photogate or other photo-sensitive region. 
     The photodiode  154  may be coupled to a storage node SN  192  through a storage gate SG  190 . The storage node  192  may store charge from the photodiode  154  to allow a global shutter operation, and may in some examples be electrically and/or optically shielded so as to prevent stray charge and/or light from corrupting the contents of the storage node  192 . The storage node  192  may be coupled to a floating diffusion node FD  163  through a transfer gate TX  158 . The floating diffusion node  163  is provided as the gate input to a source follower gate SF  160 . A row select gate  162  and the source follower gate  160  may be coupled to a reference voltage source (Vdd) node  166 . The row select gate  162  may further be coupled to a row select line (e.g.,  148  in  FIG. 4B ) for the pixel  136 . The control circuitry for the pixel  136  may additionally or alternatively include one or more other gates. For example, an anti-blooming gate  194  may be in communication with the photodiode  154  to drain excess charge from the photodiode  154 —such as when the photodiode  154  is not integrating charge. 
     In some embodiments, the photodiode  154  and the gates  194 ,  190 ,  158 ,  156 ,  160 ,  162  of the pixel  136  may all be positioned on a single semiconductor chip or wafer, whereas in other embodiments, some components of the pixel  136  may be on one semiconductor chip with other components on a second chip. For example, the photodiode  154 , the storage gate  190 , the storage node  192  may be positioned on one chip, while the floating diffusion node  163 , reset gate  156 , and so forth positioned on another chip, with the transfer transistor  158  vertically extending between the two chips. As another example, the photodiode  154 , along with the storage gate  190 , the transfer gate  158 , the source follower gate  160 , the reset gate  156 , and the row select gate  162  may be positioned on one chip, with further readout circuitry positioned on another chip. In general, the components of the pixel  136  may be spread across one or a plurality of chips. 
     In operation, when one of the cameras  102 ,  104  is actuated to capture an image, the reference voltage  166  is applied to the reset gate  156 , the transfer gate  158 , and the storage gate  190  in order to deplete charge from the photodiode  154 . In some embodiments, the cameras  102 ,  104  may not include a shutter over the lens  126 , and so the image sensor  130  may be constantly exposed to light. In these embodiments, the photodiode  154  may need to be reset or depleted before a desired image is to be captured. In other embodiments, an anti-blooming gate  194  may be used for a similar purpose. Once the charge from the photodiode  154  has been depleted, the storage gate  190 , the transfer gate  158 , and the reset gate  156  may be turned off, isolating the photodiode  154 . The photodiode  154  may then begin collecting light transmitted to the image sensor  130  from the lens  126  and integrating charge derived therefrom. As the photodiode  154  receives light, it starts to collect charge generated by the incident photons. The charge remains in the photodiode  154  because the storage gate  190  connecting the photodiode  154  to the storage node  192  is turned off, as is the anti-blooming gate  194 . 
     Once integration is complete and the photodiode  154  has collected light  128  from the lens  126 , the reset gate  156  may be turned on to reset the floating diffusion node  163  and/or the transfer gate  158  may be turned on to reset the storage node  192 . The storage gate  190  may then be activated and the charge from the photodiode  154  may be transmitted to the storage node  192 . The charge from the photodiode  154  may be held at the storage node  192  until the pixel  136  is ready to be read out. In the global shutter operation, each row within the pixel architecture  134  may be reset and exposed (i.e., integrate charge generated by light transmitted through the lens  126 ) at substantially the same time. Each pixel  136  may simultaneously transfer the charge from the photodiode  154  to a storage node, and then each pixel  136  may be read out row by row in some embodiments. When the pixel  136  is to be read out row by row, the transfer gate  158  may be activated to transfer the charge from the storage node  192  to the floating diffusion node  163 . Once the charge is stored in the floating diffusion node  163 , the row select gate  162  may be activated, and the SF gate  160  amplifies the charge in the floating diffusion node  163  and provides a signal indicative thereof through the row select gate  162 . 
     Pixel Structure 
     With reference now to  FIG. 6A , a simplified schematic cross section for one embodiment of a pixel  136  is shown. The pixel  136  includes a photodiode  154  with at least two regions  154   a ,  154   b . The two regions  154   a ,  154   b  are coupled together but have different electric potentials. The first region  154   a  has a first electric potential, and the second region  154   b  has a second electric potential, with the second electrical potential being greater than the first. As described herein, the electric potential of a region may refer to the potential of the region before and/or after the region is depleted during operation, as described above. 
     As described in more detail below with reference to  FIGS. 12A and 12B , the electric potential of the regions  154   a ,  154   b  may be different because the regions  154   a ,  154   b  were doped differently during manufacture of the pixel  136 , thereby causing more or fewer ionized atoms to be present in the regions  154   a ,  154   b  compared to one other. For example, the first region  154   a  may have been very lightly doped (shown as “n- -” in  FIG. 6A ), whereas the second region  154   b  may have been lightly doped (shown as “n-” in  FIG. 6A ). Alternatively, or additionally, the first region  154   a  may have been doped with one type of implant, and the second region  154   b  may have been doped with a different type of implant, for example an implant with a different energy. Alternatively, or additionally, the first and second regions  154   a ,  154   b  may have had different thermal treatments applied. 
     The second region  154   b  of the photodiode  154  may be offset in depth from the first region  154   a  of the photodiode  154   a  within a single semiconductor chip  170 , one example of which is illustrated in  FIG. 6A . The first region  154   a  may have a larger cross-section than the second region  154   b , and the electric potential of the second region  154   b  may be higher than the electric potential of the first region  154   a . In this manner, as described below, charge that is generated in the first region  154   a  may be funneled to the second region  154   b  because of the potential difference between the two regions  154   a ,  154   b.    
     The thickness (in depth) of the two regions  154   a ,  154   b  of the photodiode  154  may vary among different embodiments. In one embodiment, the first region  154   a  may be substantially thicker than the second region  154   b . In other embodiments, the second region  154   b  may be thicker than the first region  154   a . In one particular embodiment, the thickness of the first region  154   a  may be determined by the expected depth at which most or all incident light will be converted into electrical charge within the photodiode  154 . In other words, in one embodiment, the first region  154   a  may be engineered so that few, if any, photons are not converted into electron-hole pairs within the first region  154   a , and, consequently, so that few, if any, photons proceed to the storage node  192 . Alternatively, or in addition to having a thick first region  154   a , a shielding layer  182 ,  183  may be used in some embodiments, as described below. 
     In some embodiments, the photodiode  154  may include only two regions  154   a ,  154   b , whereas in other embodiments, the photodiode  154  may include more than two regions. For example, the photodiode may include a transition region (not shown in  FIG. 6A ) between the first and second regions, with the electric potential of the transition region gradually increasing. The transition region may be formed naturally as a result of the doping and implantation manufacturing processes, or may be deliberately formed. In other embodiments, however, the doping concentration, and thus the potential, of the two regions  154   a ,  154   b  may be stepped, or may transition abruptly from one concentration/potential to the other concentration/potential. 
     As illustrated in  FIG. 6A , in some embodiments, the photodiode  154  may substantially extend between a first surface  172  and a second surface  174  of a semiconductor chip  170 , with the first region  154   a  of the photodiode  154  positioned proximate the first surface  172  and the second region  154   b  of the photodiode  154  positioned proximate the second surface  174  of the semiconductor chip  170 . The first surface  172  of the semiconductor chip  170  may be the “backside”  172  of the chip  170 , and the second surface  174  of the semiconductor chip  170  may be the “frontside”  174  of the chip  170 . As described below, this may allow the entire first side  172  of the semiconductor chip  170  for pixel  136  to be used for illumination of the photodiode  154  (specifically, the first region  154   a  of the photodiode  154 ), while the second surface  174  of the semiconductor chip  170  can be used for transferring charge to the storage node  192  and to the floating diffusion node  163 . In this manner, no storage node or charge transfer circuitry may be present on the first surface  172  of the semiconductor chip  170  such that nearly all of the first surface  172  of the semiconductor chip  170  can be used for photodiodes  154  for various pixels  136 , thus increasing the sensitivity of the pixels  136  as compared to prior art pixels with charge storage nodes and charge transfer circuitry on the same surface as the photodiode. In other examples, however, the photodiodes  154  may not fill the entire first surface  172  of the semiconductor chip  170  so that other circuitry or nodes can be present on the first surface  172  of the semiconductor chip  170 . 
     In some but not all embodiments, the photodiode  154  may be pinned to the first and/or second surfaces  172 ,  174  of the semiconductor chip  170  (illustrated by the shallow p+ regions on the surfaces of the photodiode  154  in  FIG. 6A ). Pinning one or both surfaces  172 ,  174  of the photodiode  154  may reduce dark current, and thus improve signal to noise ratios in some embodiments. 
     Referring still to  FIG. 6A , the pixel  136  also includes a storage node  192 , at least a portion of which may be positioned at substantially the same depth in the semiconductor chip  170  as at least a portion of the second region  154   b  of the photodiode  154 , and may be positioned proximate the second surface  174  of semiconductor chip  170 . The storage node  192  may be positioned at least partially beneath the first region  154   a  of the photodiode  154 . In some embodiments, the storage node  192  is positioned entirely beneath the first region  154   a  of the photodiode  154  so that the first region  154   a  effectively shields the storage node  192  from light incident on the back surface  172  of the semiconductor chip  170 . This positioning may allow for high shutter efficiency for the pixel  136 . 
     The storage node  192  may have an electric potential that is higher than the second region  154   b  of the photodiode  154 , so that charge that accumulates in the second region of the photodiode  154   b  can be transferred to the storage node  192  when the storage gate  190  is activated. The storage node  192  may have a higher potential than the second region  154   b  of the photodiode  154  because, for example, the storage node  192  was doped with a higher concentration of dopant (shown as “n” in  FIG. 6A ) during manufacturing as compared with the second region  154   b.    
     The storage node  192  may in some embodiments be less thick (in depth) than, as deep as (in depth), or more thick (in depth) than the second region  154   b  of the photodiode  154  in different embodiments. In embodiments where the thickness in depth of the second region  154   b  of the photodiode  154  is less than the thickness in depth of the storage node  192 , charge may be transferred from the second region  154   b  of the photodiode  154  to the storage node  192  during operation, as described in more detail below. In some embodiments, the storage node  192  may be pinned to one surface  174  of the semiconductor chip  170 , for example, the same surface  174  of the semiconductor chip  170  to which the second region  154   b  of the photodiode  154  is pinned. 
     One or more storage gates  190  may be operable to transfer charge from the photodiode  154  to the storage node  192 . With reference to  FIG. 6A , the storage gate  190  may be formed on the second surface  174  of the semiconductor chip  170  and may be coupled between the second region  154   b  of the photodiode  154  and the storage node  192 . The storage gate  190  may thus be configured to form a channel between the photodiode  154  and the storage node  192  responsive to an applied voltage, with charge being transferable over the formed channel. Also, the pixel  136  may include a floating diffusion node  163 , and a transfer gate  158  coupling the storage node  192  to the floating diffusion node  163 , the operation of which is described above. 
     In some embodiments, the pixel  136  may include one or more shielded regions  182 . With reference to  FIG. 6A , one shielded region  182  may be an electrical shield, and may be configured to shield the storage node  192  from charge that is generated in the first region  154   a  of the photodiode  154 . The shielded region  182  may, for example, be a layer that is p-doped. 
     In some examples, the shielded region  182  may laterally extend the entire width and length of the storage node  192  in order to shield the storage node  192  from light incident from the first region  154   a  of the photodiode  154  (i.e., that was not converted to electron-hole pairs in the photodiode). In another example, the shielded region may also or alternatively extend in depth between the second region  154   b  of the photodiode  154  and the storage node  192 . Also, in those examples where a floating diffusion node  163  is proximate the second surface  174  of the semiconductor chip  170 , the shielded region  182  may extend partially or fully over the floating diffusion node  163 . 
     With reference now to the potential profile  186  illustrated in  FIG. 6B , representative of the electric potential of the pixel  136  in  FIG. 6A  along dotted line  185  in  FIG. 6A , the relative electric potentials of the first and second photodiode regions  154   a ,  154   b , the storage node  192 , and the floating diffusion node  163  are shown. As illustrated, the electric potential for the second region  154   b  of the photodiode  154  is greater than the electric potential of the first region  154   a . Also, the electric potential of the storage node  192  is greater than the electric potential of the second region  154   b  of the photodiode  154 , and the electric potential of the floating diffusion node  163  is greater than the electric potential of the storage node  192 . In this manner, and as described now with reference to  FIGS. 7A through 11B , charge generated in the first region  154   a  of the photodiode  154  from incident photons may be transferred to the floating diffusion node  163  upon the proper signaling of the storage and transfer gates  190 ,  158 . 
     Pixel Operation 
     In  FIG. 7A  and the corresponding potential profile  186  of the pixel  136  in  FIG. 7B , the pixel  136  is in integration mode and electron-hole pairs are generated in the first region  154   a  of the photodiode  154  as a result of incident light. As also illustrated in the corresponding potential profile  186  in  FIG. 7B , the charge carriers (electrons here) initially are located in the first region  154   a  of the photodiode  154 . Of course, in some examples, some charge may be generated in the second region  154   b  of the photodiode as well (e.g., for photons that are not absorbed in the first region  154   a . In any event, because of the potential difference between the first and second regions  154   a ,  154   b  of the photodiode  154 , the charge from the first region  154   a  is funneled or swept to the second region  154   b  soon after it is generated, as illustrated by  FIGS. 8A and 8B . Because the potential of the second region  154   b  is greater than the potential of the first region  154   a , most of the charge generated in the photodiode  154  will be stored in the second region  154   b  of the photodiode  154 . 
     After integration is complete, or even during integration in some embodiments, the storage gate  190  may be activated (e.g., by providing a high voltage to its gate terminal), which may cause a channel to form proximate the second surface  174  between the second region  154   b  of the photodiode  154  and the storage node  192 . As illustrated in  FIGS. 9A and 9B , activating the storage gate  190  may cause the charge stored in the second region  154   b  of the photodiode to be transferred through the channel formed by the storage gate  190  to the storage node  192 . As discussed above, in global shutter pixels  136 , the integration and transfer of generated charge from the photodiode  154  to the storage node  192  may occur at substantially the same time for all pixels  136  in an image sensor. 
     After the charge has been transferred to the storage node  192 , the storage gate  190  is deactivated, and the charge is isolated in the storage node  192  as illustrated in  FIGS. 10A and 10B . Because the storage node  192  is positioned at least partially beneath the first region  154   a  of the photodiode  154 , the storage node  192  may be electrically and/or optically shielded from charge or photons from the photodiode  154 , so that the charge stored in the storage node  192  across an image sensor can be read out one row and column at a time, without incurring the blurring and noise typically associated with a rolling shutter pixel architecture. As illustrated in  FIGS. 11A and 11B , the charge stored in the storage node  192  may be transferred to a floating diffusion node  163  by activating a transfer gate  158 . In some examples, correlated double sampling (CDS) may be used because the storage node  192  and/or the floating diffusion node  163  may be sampled both before and after charge is stored therein. 
     Pixel Manufacturing 
     With reference now to  FIGS. 12A and 12B , one embodiment of manufacturing the pixel  136  illustrated in  FIG. 6A  will now be described. In  FIG. 12A , the second surface  174  (e.g., the front side) of the semiconductor chip  170  is processed by forming the second region  154   b  of the photodiode  154 , the storage node  192 , and, in some embodiments, forming the shielding region  182 , the floating diffusion node  163 , the storage gate  190 , and the transfer gate  158 . These components of the pixel  136  may be formed using conventional semiconductor device lithographic and implantation processes. In some examples, the second region  154   b  and the storage node  192  may be formed using the same type of dopant, such as an n-type dopant. The concentration of the dopant used to form the second region  154   b , however, may be less than the concentration of the dopant used to form the storage node  192  so that, as described above, when the storage gate  190  is activated, charge will flow from the second region  154   b  to the storage node  192 . In other examples, the second region  154   b  and the storage node  192  may be formed using different types of dopants, with similar or different concentrations, such that the potential of the storage node  192  is greater than the second region  154   b  during operation of the pixel  136 . In still other examples, voltages or other techniques may be used to increase the potential of the second region  154   b  relative to the potential of the storage node  192 . 
     After the second surface  174  has been processed, the first surface  172  of the semiconductor chip  170  may be processed by forming the first region  154   a  of the photodiode  154 . The first region  154   a  of the photodiode  154  may be formed such that it at least partially overlaps with the second region  154   b  in depth so that charge generated in the first region  154   a  may be funneled to the second region  154   b . Also, in some embodiments, the second surface may be processing using blanket implants, since the second regions  154   b  of the pixels  136  may substantially define the pixels  136 . Using blanket implants may allow one or more lithographic or other semiconductor device processing steps to be skipped when processing the first surface  172 , thereby reducing manufacturing and processing costs. 
     Although the pixel  136  has been described in  FIGS. 12A and 12B  as being manufactured by processing the second surface  174  before processing the first surface  172 , in another embodiment, the first surface  172  is processed before the second surface  174 . In still other embodiments, the first or second surfaces  172 ,  174  may be only partially processed before proceeding to the other, or may be processed at substantially the same time. Also, as illustrated in  FIGS. 12A and 12B , one or more portions of the first and second surfaces  172 ,  174  may be pinned by forming a shallow p+ region in, for example, both surfaces of the photodiode  154  and the sole exposed surface of the storage node  192 . 
     Additional Pixel Structures 
     With reference to  FIG. 13 , a pixel  136  is shown that is substantially similar to the pixel  136  shown in  FIG. 6A , except that an additional shielding layer  183  may be used. The shielding layer  183  may be an optical shield, and may be used in addition to or in place of the electrical shield  182  described with reference to  FIG. 6A . The optical shielding layer  183  may include a light reflective material (e.g., a shiny metal) that reflects any light that is not converted into charge in the first region  154   a  of the photodiode  154  so that the light does not corrupt the charge stored in the storage node  192 . The optical shielding layer  183  may be formed during manufacturing by, for example, depositing the material and epitaxially growing semiconductor material around the optical shielding layer  183 , form which the other components of the pixel  136  may subsequently be formed. In those embodiments where an optical shielding layer  183  is used, the first region  154   a  of the photodiode  154  may be thinner than in those embodiments without an optical shielding layer  183  because there may be less of a chance of light corrupting the charge stored in the storage node  192 . 
     In  FIG. 14 , another embodiment of a pixel  136  is shown, in which the pixel  136  includes a plurality of storage nodes  192   a ,  192   b . In general, the pixel  136  may include any number of storage nodes (e.g., 1, 2, 3, 4, 5, 6, etc.). In some embodiments, a plurality of storage nodes such as the storage nodes  192   a ,  192   b  illustrated in  FIG. 14  may be used simultaneously to store charge (e.g., they together may be equivalent to the single storage node  192  illustrated in  FIG. 6A ), whereas in other embodiments, the plurality of storage nodes may be used sequentially to store charge corresponding to different frames of data. For example, one storage node  192   a  may be used to store charge from a first frame of the image sensor, and the other storage node  192   b  may be used to store charge from a second frame of the image sensor. Such sequential use of a plurality of storage nodes  192   a ,  192   b  may allow for various image sensor techniques to be used, including for example high-dynamic range (HDR) imaging, pixel sharing, buffering, burst-mode readout, and so forth. As illustrated in  FIG. 14 , for each storage node  192   a ,  192   b , the pixel  136  may include a corresponding storage gate  190   a ,  190   b , transfer gates  158   a ,  158   b , floating diffusion nodes  163   a ,  163   b , shielding layers  182   a ,  182   b , and so forth. However, in other embodiments (not shown in  FIG. 14 ), multiple storage nodes  192   a ,  192   b  may be coupled to and transfer charge to a common floating diffusion node. 
     In  FIG. 15 , yet another embodiment of an image sensor pixel  136  is shown. In  FIG. 15 , the storage gate  190  is coupled to the second region  154   b  of the photodiode  154  (as opposed to the surface  174  of the semiconductor chip  170  between the second region  154   b  and the storage node  192 , as in  FIG. 6A ) and may be configured to selectively increase the potential of the second region  154   b  responsive to an applied voltage. In this configuration, the inherent potential of the second region  154   b  of the photodiode  154  may or may not be greater than the potential of the first region  154   a , but, in any event, the storage gate  190  may pump any charge generated in the first region  154   a  towards the second surface  174  of the semiconductor chip  170  so that it can be swept into the storage node  192 . As illustrated in  FIG. 15 , the storage node  192  may be bifurcated into two differently doped regions, and may also be pinned, such that a virtual barrier is created for charge until the voltage applied to the storage gate  190  decreases in order to allow the charge to flow into the storage node  192 . In this embodiment, the second region  154   b  of the photodiode  154  may not be pinned to the second surface  174 . In still another embodiment (not shown in the figures), and as briefly mentioned above, a charge pumping gate, similar to the gate  190  in  FIG. 15 , may be used to alter the potential of one or both of the first and/or second regions  154   a ,  154   b  of the photodiode  154  illustrated in  FIG. 6A  so that charge is funneled from the first region  154   a  to the second region  154   b  during integration. 
     Conclusion 
     The foregoing description has broad application. For example, while examples disclosed herein may focus on particular architectures of image sensors (e.g., photodiode, global shutter, CMOS sensors, etc.), it should be appreciated that the concepts disclosed herein may equally apply to substantially any other type of image sensor with or without appropriate modifications as would be appreciated by one skilled in the art of image sensors. Moreover, although certain examples have been described with reference to particular dopants (e.g., a storage node  192  in  FIG. 6A  that is doped with n-type material), it will be understood that other dopants are also within the scope of this disclosure and the appended claims. For example, referring back to  FIG. 6A , the storage node  192  may be doped with p-type dopant in an n-type substrate. 
     Furthermore, the various embodiments described herein may find application in many different implementations. For example, although the funneling of charge has been described with reference to two regions  154   a ,  154   b  of a photodiode  154 , in other embodiments, charge may be transferred between two regions of a storage node, or between a storage node and another type of node using different regions with different potentials. 
     Accordingly, the discussion of any embodiment is meant only to be exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples.

Metadata:
Filing Date: 20160229
Publication Date: 20190416
Grant Date: 20190416
Priority Date: 20130304
Inventors: WAN, CHUNG CHUN
Assignee: APPLE INC
CPC Classifications: [{"code": "H04N23/54", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N5/2253", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/14643", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L27/14623", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/14612", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/044", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L27/14609", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/14603", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/1464", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/1461", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/8057", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/8037", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/803", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/802", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/199", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/18", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/199", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/8057", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/8037", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10F39/8033", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10F39/8033", "inventive": true, "first": true, "tree": "[]"}, {"code": "H04N25/77", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/044", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F3/044", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 51420497