PATENT DOCUMENT

Publication Number: US-11204636-B2
Application Number: US-201916519347-A
Country: US
Kind Code: B2

Title: Systems and methods for coherent power management

Abstract:
In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Claims:
What is claimed is: 
     
       1. A system comprising:
 a power-managed load comprising a processor; 
 a power management unit coupled to the power-managed load and configured to supply power to the power-managed load; 
 a plurality of circuits wherein:
 respective circuits of the plurality of circuits implement different power management mechanisms; 
 the different power management mechanisms affect the same power-managed load; 
 the plurality of circuits operate in different ones of a plurality of time domains and the plurality of circuits operate concurrently and independently, wherein a time characteristic corresponding to a respective time domain of the plurality of time domains differs from the time characteristic of other ones of the plurality of time domains; and 
 
 a control circuit configured to coordinate the power management mechanisms implemented by the plurality of circuits when the power management mechanisms are reacting to a same variation in the power to the power-managed load. 
 
     
     
       2. The system as recited in  claim 1  wherein the power-managed load comprises one or more integrated circuits. 
     
     
       3. The system as recited in  claim 1  wherein the power-managed load comprises one or more processors. 
     
     
       4. The system as recited in  claim 1  wherein a first power management mechanism of the plurality of power management mechanisms is a fixed phase mode in which the power management unit is configured to limit a number of enabled phases of a voltage regulator in the power management unit to a fixed number. 
     
     
       5. The system as recited in  claim 1  wherein a first power management mechanism of the plurality of power management mechanisms is a mode in which the power management unit is configured to disable power to the power-managed load and the power-managed load is configured to operate on energy stored in capacitors coupled between a power supply input to the power-managed load and ground. 
     
     
       6. The system as recited in  claim 1  wherein a first power management mechanism of the plurality of power management mechanisms is a dynamic load line mode in which a load line of the power management unit is adjusted during operation based on a state of the power-managed load. 
     
     
       7. The system as recited in  claim 1  wherein the time characteristic is a bandwidth. 
     
     
       8. The system as recited in  claim 1  wherein the time characteristic is a latency. 
     
     
       9. The system as recited in  claim 1  wherein the time characteristics for the plurality of time domains differ from each other by one or more orders of magnitude. 
     
     
       10. The system as recited in  claim 1  wherein the time characteristic corresponding to a first time domain of the plurality of time domains in which a first circuit of the plurality of circuits operates is an indication of how quickly the first circuit responds to inputs to generate compensation outputs. 
     
     
       11. A method comprising:
 controlling power to a power-managed load using a plurality of circuits, wherein respective circuits of the plurality of circuits implement different power management mechanisms that affect the power-managed load, and wherein the plurality of circuits operate in different ones of a plurality of time domains and the plurality of circuits operate concurrently and independently, wherein a time characteristic corresponding to a respective time domain of the plurality of time domains differs from the time characteristic of other ones of the plurality of time domains; and 
 coordinating operation of the plurality of circuits when the plurality of circuits are reacting to a same variation in the power to the power-managed load. 
 
     
     
       12. The method as recited in  claim 11  wherein time characteristics associated with the time domains differ by one or more orders of magnitude. 
     
     
       13. The method as recited in  claim 11  wherein the time characteristic corresponding to a first time domain of the plurality of time domains in which a first circuit of the plurality of circuits operates is an indication of how quickly the first circuit responds to inputs to generate compensation outputs. 
     
     
       14. The method as recited in  claim 11  wherein the power-managed load comprises one or more processors. 
     
     
       15. A system comprising:
 a power-managed load; 
 a plurality of circuits coupled to the power-managed load, wherein:
 respective circuits of the plurality of circuits implement different power management mechanisms; 
 the different power management mechanisms affect the same power-managed load; 
 the plurality of circuits operate in different ones of a plurality of time domains and the plurality of circuits operate concurrently and independently, wherein a time characteristic corresponding to a respective time domain of the plurality of time domains differs from the time characteristic of other ones of the plurality of time domains and indicates how quickly a respective circuit of the plurality of circuits operating in the respective time domain reacts to inputs to produce compensation outputs; and 
 
 a control circuit coupled to the plurality of circuits and configured to coordinate the power management mechanisms implemented by the plurality of circuits when the power management mechanisms are reacting to a same variation in the power to the power-managed load. 
 
     
     
       16. The system as recited in  claim 15  wherein the power-managed load comprises one or more integrated circuits. 
     
     
       17. The system as recited in  claim 15  wherein the power-managed load comprises one or more processors. 
     
     
       18. The system as recited in  claim 15  wherein the time characteristic is a bandwidth. 
     
     
       19. The system as recited in  claim 15  wherein the time characteristic is a latency. 
     
     
       20. The system as recited in  claim 15  wherein the time characteristics for the plurality of time domains differ from each other by one or more orders of magnitude.

Description:
This application is a continuation of U.S. patent application Ser. No. 15/430,699, filed on Feb. 13, 2017 and now U.S. Pat. No. 10,423,209. The above application is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Technical Field 
     Embodiments described herein are related to power management in electronic systems and, more particularly, to coherently managing multiple power management circuits included in the system. 
     Description of the Related Art 
     Electronic systems implement a variety of power management mechanisms in an attempt to optimize the balance of power consumed and performance achieved. The mechanisms include high speed, high bandwidth mechanisms that are logically close to the load being power managed. For example, the high speed, high bandwidth mechanisms can be integrated on the same integrated circuit as the load or logically close to the load, such as on an interface to the load. The mechanism also include lower speed, lower bandwidth mechanisms that are logically farther from the load (e.g. nearer the power supply). Generally, the power management mechanisms are not operated in a feedback loop and are independent of each other. Thus, there is no guarantee that the mechanisms will work well together. In fact, the mechanisms may work at cross-purposes at times. 
     For example, the currents and the rate-of-change of currents (di/dt) are reaching sufficiently large values, and throttle mechanisms are going to be needed to limit the electrical effects at different time-scales. Coordination between these mechanisms can be important to prevent stability issues and excitation of additional noise in the system. 
     Another consequence of the larger currents and di/dt&#39;s is that electrically the performance of various processors such as the central processing units (CPUs) and graphics processing units (GPUs) is being affected due to voltage guardband and droop. If the electrical behavior of the power delivery is not controlled, then the guardband will continue to increase without abatement. 
     Additionally, the amortization of power within the system can be rather complex. For example, if one is charging and discharging the bus capacitors continually by turning off and on the loads and the sources, significant power can be saved in the system by keeping certain systems on and waiting for the optimal point to turn them off and on. Larger and larger deviations in the electrical behavior will be expected on both the CPU and GPU power rails moving forward. 
     SUMMARY 
     In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism for the coordinated, coherent use of power are described. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG. 1  is a block diagram of a high level view of one embodiment of a system including a coherent power management system (CPMS). 
         FIG. 2  is a block diagram of one embodiment of the system including the CPMS illustrated as a set of credit state machines, telemetry circuits, and throttle circuits. 
         FIG. 3  is a block diagram of one embodiment of the system including the CPMS with specific compensation circuits and detector circuits. 
         FIG. 4  is a block diagram of one embodiment of a state machine for a fixed phase compensation circuit. 
         FIG. 5  is a block diagram of one embodiment of a state machine for a coasting compensation circuit. 
         FIG. 6  is a block diagram of one embodiment of a state machine for a dynamic load line compensation circuit. 
         FIG. 7  is a block diagram of one embodiment of a system. 
         FIG. 8  is a block diagram of one embodiment of a computer accessible storage medium. 
     
    
    
     While embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to. 
     Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “clock circuit configured to generate an output clock signal” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., power is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. The hardware circuits may include any combination of combinatorial logic circuitry, clocked storage devices such as flops, registers, latches, etc., finite state machines, memory such as static random access memory or embedded dynamic random access memory, custom designed circuitry, analog circuitry, programmable logic arrays, etc. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” 
     The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function. After appropriate programming, the FPGA may then be configured to perform that function. 
     Reciting in the appended claims a unit/circuit/component or other structure that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) interpretation for that claim element. Accordingly, none of the claims in this application as filed are intended to be interpreted as having means-plus-function elements. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct. 
     In an embodiment, hardware circuits in accordance with this disclosure may be implemented by coding the description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized against a library of cells designed for a given integrated circuit fabrication technology, and may be modified for timing, power, and other reasons to result in a final design database that may be transmitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof may also be custom-designed in a schematic editor and captured into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and may further include other circuit elements (e.g. passive elements such as capacitors, resistors, inductors, etc.) and interconnect between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized to a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in the FPGA. 
     As used herein, the term “based on” or “dependent on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.” 
     This specification includes references to various embodiments, to indicate that the present disclosure is not intended to refer to one particular implementation, but rather a range of embodiments that fall within the spirit of the present disclosure, including the appended claims. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The coherent power management system (CPMS) described herein may provide power management coordination across multiple power management mechanisms that may operate on different time scales (e.g. they may have different bandwidths or latencies). That is, a given power management mechanism may have a certain latency to respond to events in the system. The various power management mechanisms may have been designed independently and operate independently, in the absence of CPMS. Accordingly, CPMS is included to coordinate the efforts of the power management mechanisms. 
     For example, if a first power management mechanism is already in operation to handle an event, other power management mechanisms may be held off or their action may be reduced to account for the operation of the first power management mechanism. If one power management mechanism is about to power down a component but another power management mechanism indicates upcoming activity, the power down may be delayed/cancelled to avoid powering down and shortly thereafter powering up again (wasting energy). While these examples are not exhaustive, they illustrate how energy may be wasted in uncoordinated power management mechanisms. CPMS may attempt to balance the power management and performance of the system, attempting to maximize the performance achieved per unit of energy expended. 
     In some cases, a slower-acting (lower bandwidth, higher latency) power management mechanism may detect an event earlier in time than a faster-acting (higher bandwidth, lower latency) mechanism by monitoring different parameters and/or by detecting trends (e.g. trajectories) in the change of the parameter rather than detecting a threshold crossing. Combinations of power management mechanisms may be used to detect such trends/trajectories as well. Faster-acting mechanisms may detect trends/trajectories. While the various monitors and compensations circuits may operate at different time scales, they may be monitoring/compensating power delivery to the same load. For example, the load may be one or more processors, such as one or more central processing units (CPUs) and/or one or more graphics processing units (GPUs). 
     CPMS may generally be implemented for any power-managed load. An example of an integrated circuit having processors is discussed in more detail below, but any electrical load may be used (e.g. integrated circuits without processors, various other electrical components, processors alone on an integrated circuit, etc.). 
     Turning now to  FIG. 1 , a block diagram of one embodiment of a system including an integrated circuit (IC)  10 , a power management unit (PMU)  12 , and circuitry implementing coherent power management in the system is shown. The embodiment of  FIG. 1  illustrates the coherent power management circuits at a high level, including transfer function circuits  14 A- 14 D and compensation circuits  16 A- 16 D. The IC  10  includes transfer function circuit  14 A and compensation circuit  16 A, and further includes one or more processors. For example, the processors may include one or more CPUs  18 A- 18 N and/or one or more GPUs  20 A- 20 M. Other embodiments may include other general purpose processors or special purpose processors as well. The CPUs  18 A- 18 N and GPUs  20 A- 20 M are coupled to the transfer function circuit  14 A and the compensation circuit  16 A. The transfer function circuits  14 A- 14 C are coupled to each other, and each transfer function circuit  14 A- 14 C is coupled to a respective circuit  22 A- 22 C which combines the output of the transfer function circuit  14 A- 14 C with the output of a compensation circuit  16 B- 16 D to provide input to a compensation circuit  16 A- 16 C as shown in  FIG. 1 . The output of the transfer function circuit  14 C is coupled to the PMU  12 , which is coupled to the transfer function circuit  14 D. The transfer function circuit  14 D is coupled to the compensation circuit  16 D. 
     The transfer function circuits  14 A- 14 D may be configured to monitor various electrical parameters and/or other environmental parameters in the system and may be configured to generate controls for corresponding compensation circuits  16 A- 16 D. The electrical parameters may include voltage and current, for example. Other environmental parameters may include, for example, temperature, activity levels in the load (e.g. CPU usage, CPU usage of certain instructions, GPU usage, etc.), etc. Each transfer function circuit  14 A- 14 D may be operable at a given time window or bandwidth. Different time windows/bandwidths may differ from each other by at least an order of magnitude, in various embodiments. The time windows/bandwidths may be in part a function of the nature of the circuitry (e.g. high frequency filtering, loop stability criteria, etc.) and the parameters being sensed. In an embodiment, the transfer function circuit  14 A may have the highest bandwidth/shortest time window/shortest latency and the transfer function circuits  14 B- 14 D may have increasingly lower bandwidths/longer time windows/longer latencies. 
     The compensation circuits  16 A- 16 D may implement corrective action in response to the inputs from the transfer function circuits  14 A- 14 D and further in response to communications from other compensation circuits  16 A- 16 D acting in response to other transfer function circuits  14 A- 14 D. In some cases, a lesser amount of compensation may be provided by a given compensation circuit  16 A- 16 D if other compensation circuits  16 A- 16 D are already in operation (even if they are slower-acting circuits). 
     The corrective actions (compensations) implemented by the compensation circuits  16 A- 16 D may vary. For example, the compensation circuits  16 A- 16 D may include throttle circuits of various types. Generally, a throttler attempts to limit activities in the load in some fashion. Throttling can be a logical action (e.g. reducing instruction throughput in a processor my limiting issuance of otherwise ready-to-execute instructions, clock gating, etc.) or a physical action (e.g. reducing the clock frequency of the clocks in the load, removing clock pulses from a clock to effectively reduce the frequency, etc.). The corrective actions may also include attempts to counter the event (e.g. increasing the energy in the system by providing more current from the PMU  12 , increasing the voltage to offset a voltage droop, etc.). 
     The PMU  12  may include one or more voltage regulators configured to supply power to the IC  10  and/or other components of the system. The voltage regulators may have any design and features. For example, multiple phases of buck regulators may be implemented, where the amount of current that may be provided with good regulation of the voltage (minimal droop) is proportional to the number of phases that are on. The number of phases that are turned on at a given point in time may be dependent on the power states of the processors in the IC  10  and/or various events detected by the transfer function circuits  14 A- 14 D. 
     The IC  10  may be any integrated circuit in various embodiments. For example, the IC  10  may be a processor chip including one or more CPUs  18 A- 18 N and/or one or more GPUs  20 A- 20 M. The IC  10  may be a system on a chip (SOC) including one or more processors and one or more peripheral circuits (e.g. a memory controller coupled to a memory in a given system, bridges to input/output interfaces of various types, audio peripherals, video peripherals, etc.). In some embodiments, the IC  10  may be a fixed function IC without processors. 
     The CPUs  18 A- 18 N may be any general purpose processors implementing any instruction set. Any microarchitectural features may be implemented (e.g. in-order, out of order, scalar, superscalar, pipelined, speculative execution, etc.). Similarly, the GPUs  20 A- 20 M may be any type of graphics processor and may implement any graphics instruction set. Any microarchitectural features may be employed. 
     CPMS may in particular be focused on coordinating power management systems for providing power to the processors in the integrated circuit  10  (e.g. the CPUs  18 A- 18 N and/or the GPUs  20 A- 20 M). The processors may have larger dynamic load changes (e.g. current consumptions) than other circuitry in the integrated circuit  10  (e.g. peripherals in an SOC embodiment). In other embodiments, CPMS may also coordinate power management systems for the IC  10  as a whole, or any portions of the IC  10 , as desired. 
     It is noted that the number of transfer function circuits  14 A- 14 D and/or the number of compensation circuits  16 A- 16 D may vary in various embodiments. The numbers of such circuits may be more or fewer than those shown in  FIG. 1 . More or fewer such circuits may be integrated into the IC  10  or included external to the IC  10 . 
     Turning next to  FIG. 2 , a block diagram of one embodiment of a system including CPMS is shown in greater detail. The IC  10  is shown, including the CPUs  18 A- 18 N and the GPUs  20 A- 20 M. The IC  10  also includes a CPMS control circuit  30  and a throttle circuit  32 A. The system further includes throttle circuits  32 B- 32 D, telemetry circuits  36 A- 36 C, and credit circuits  34 A- 34 C. The CPMS control circuit  30  is coupled to the telemetry circuits  36 A- 36 C and the credit circuits  34 A- 34 C. 
     The vertical dashed lines in  FIG. 2  divide the components into K states (or K windows) K 1  to K 4 . The bandwidth/latency of the components of CPMS in each K state are represented by the times associated with the K states (less than 50 nanoseconds for K 1 , less than 1 microsecond for K 2 , less than 100 microseconds for K 3 , and less than 1 millisecond for K 4 ). The times for each K state are exemplary, and other embodiments may have other times associated with K states and more or fewer K states. The difference between a given K state and the next slower (or next faster) K state may be one or more orders of magnitude in various embodiments. The credit circuits  34 A- 34 C, telemetry circuits  36 A- 36 C, and throttle circuits  32 B- 32 D within a given K state are coupled together. 
     Each K state (or time domain) has an associated time characteristic, which may be an indicator of how quickly circuitry in the K state may react to inputs to produce compensation outputs. The time characteristic may be expressed as a bandwidth, a latency, a clock period, or any other measure of time. 
     The throttle circuits  32 A- 32 D may implement various throttling mechanisms, such as those described above with regard to  FIG. 1 . Thus, the throttle circuits  32 A- 32 D may be examples of compensation circuits  16 A- 16 D in  FIG. 1 . As discussed in more detail below, the telemetry circuits  36 A- 36 C and corresponding credit circuits  34 A- 34 C may be examples of transfer function circuits  14 A- 14 D. 
     The telemetry circuits  36 A- 36 C may measure various parameters in the system (voltage, current, temperature, etc.) to detect events for which corrective action may be indicated. The telemetry circuits  36 A- 36 C may communicate with credit circuits  34 A- 34 C, which may exchange credits with each other indicating detected events and corrective actions being taken by other K states. Thus, the credits may help prevent over compensating for events that are detected by multiple telemetry circuits  36 A- 36 C. For example, if the telemetry circuit  36 C detects an event and initiates corrective action via throttle circuit  32 D, the credit circuit  34 C may issue credits to reflect the corrective action. If another telemetry circuit (e.g. telemetry circuit  36 A) detects the same event or a parameter change that is related to the same event, the credits communicated by the credit circuit  34 C to the credit circuit  34 A may prevent a corrective action from the throttle circuit  32 B or may reduce the throttling performed by the throttle circuit  32 B, since the throttle circuit  32 D is performing corrective action (even if the effect of the corrective action isn&#39;t visible in the K 2  state yet because of the latency of the K 4  state). 
     The CPMS control circuit  30  may coordinate between the credit circuits  34 A- 34 C and telemetry circuits  36 A- 36 C. For example, the CPMS control circuit  30  may convert credits issued by one of the credit circuits  34 A- 34 C to credits for the other credit circuits  34 A- 34 C. For example, the credits may be distributed to different credit circuits based on which corresponding telemetry circuits  36 A- 36 C are likely to detect the same event or a parameter change related to the same event. The credits may be distributed based on which corrective actions are more likely to complement the corrective action taken by the initially-activated throttle circuit  32 A- 32 D, etc. 
     Viewed in another way, the combination of a given telemetry circuit  36 A- 36 C, a corresponding credit circuit  34 A- 34 C, and the CPMS control circuit  30  may be form a control loop (dotted ovals  38 A and  38 B for the K 2  state and the K 4  state, respectively). The CPMS control circuit  30  may be responsible for providing feedback in each control loop based on activities in the other control loops. 
       FIG. 3  is a block diagram of an embodiment of the system including CPMS, shown in greater detail. In the embodiment of  FIG. 3 , the IC  10  includes the CPUs  18 A- 18 N and the GPUs  20 A- 20 M. Additionally, the IC  10  includes clock dither/power estimator (PwrEst) circuit  40 , an undervoltage detector circuit (UVD)  42 , and CPMS control circuit  30 A. The CPMS control circuit  30  of  FIG. 2  may be distributed in this embodiment with the CPMS control circuit  30 A in the IC  10 , and CPMS control circuits  30 B and  30 E in the K 2  state; CPMS control circuits  30 C and  30 F in the K 3  state; and CPMS control circuits  30 D and  30 G in the K 4  state. The telemetry circuits  36 A- 36 C include a current monitor (Imon)/debug control (DbgCtl) circuit  43 , voltage comparator circuit  44 , and thermal control (ThermCtl) circuit  46 . The throttle circuits  32 A- 32 D may include the clock dither/PwrEst circuit  40 , clock control (ClockCtl) circuit  48 , performance control (PerfCtl) circuit  50 , and temperature control (TempCtl) circuit  52 . It is noted that some of the circuits  42 ,  43 ,  44 ,  46 ,  48 ,  50 ,  52 , and  30 B- 30 G may be included in the IC  10  even though the operate in different K states than the K 1  state. 
     The UVD circuit  43  may be configured to detect undervoltage events near the CPUs  18 A- 18 N/GPUs  20 A- 20 M on the IC  10 . An undervoltage event may be a voltage droop below a certain threshold or at a certain rate, indicating that the current load of the CPUs  18 A- 18 N/GPUs  20 A- 20 N may be exceeding the capability of the power distribution network on the IC  10  and/or the PMU  12 . 
     The Imon/DbgCtl circuit  42  may detect currents above a certain threshold (or above a certain level over a period of time, and/or may detect various logic states in the system that may indicate events to be compensated. The voltage comparator  44  may compare the external supply voltage from the PMU  12  to one or more thresholds programmed into the system. The ThermCtl circuit  46  may detect temperatures that exceed a certain threshold or thresholds. 
     The clock dither/PwrEst circuit  40  may dither the clock to reduce effective clock frequency temporarily in response to events, and may digitally estimate the power consumed in the processors of the IC to cause throttling of high power portions of the processors. The ClockCtl circuit  48  may be configured to slowly reduce the clock frequency as the supply voltage magnitude droops. The PerfCtl circuit  50  may be configured to ensure that power consumption of the system as a whole does not exceed a certain level. The TempCtl circuit  52  may respond to thermal events by rapidly shutting down processors in the IC  10 . 
       FIGS. 4 to 6  illustrate certain examples of power management mechanisms that may be employed in various embodiments of CPMS. The examples are not intended to be limiting, as there may be numerous other mechanisms implemented in addition to or in place of these examples. 
       FIG. 4  is a state machine  60  illustrating one embodiment of fixed phase compensation mechanism. When, for example, the CPUs  18 A- 18 N and/or the GPUs  20 A- 20 M are operating in low power modes (low power supply voltage magnitude and low clock frequency), the maximum current that the PMU  12  may be required to deliver may be limited by the fact that the low power mode is associated with a lower maximum current. In an embodiment, a fixed number of phases of voltage converters in the PMU  12  may be sufficient to supply the current, as well as current needs of other devices in a system with the IC  10 . The number of phases may be one, or may be more than one, but may be less than the maximum number of phases in the PMU  12 . Because other devices in the system may power on and may temporarily present a load that would cause the PMU  12  to enable additional phases, the fixed phase compensation mechanism may prevent such enabling and thus conserve power. The additional phases may not be needed because the CPU/GPU power state may ensure that enough current is available for the other device within the current that may be provided by the already-enabled phase(s). The state machine  60  may be part of the CPMS control circuit  30 A, in an embodiment, or may be implemented in a distributed fashion over one or more CPMS control circuits  30 A- 30 G, or may be implemented wholly outside the IC  10 , in various embodiments. 
     The CPMS control circuit  30 A may receive an indication from a power manager in the IC  10  (not shown) that at least tracks power states in the IC  10  and may, in some embodiments, control the power states. The indication may describe a change in the power state of one or more CPUs/GPUs. The state machine may be in a power state check (PState Chk) state  62 . In response to the indication, the state machine may transaction to a current maximum check (I Max Chk) state  64 , in which the CPMS control circuit  30 A may determine if the maximum current that may be drawn by the CPUs/GPUs in the new power state is low enough to be supplied by the PMU  12  in fixed phase mode. For example, the CPMS control circuit  30 A may have a lookup table programmed with power states and corresponding maximum current limits. If the currents are not serviceable in fixed phase mode, the state machine may return to the PState chk state  62 . On the other hand, if the currents are serviceable in fixed phase mode, the CPMS control circuit  30 A may transmit a fixed phase command to the PMU  12  to cause the PMU  12  to operate in fixed phase mode (Fixed Phase Cmd state  66 ). In an embodiment, the fixed phase command may cause the PMU  12  to operate in pulse frequency modulation (PFM) mode rather than burst continuous current mode (CCM). If the mode is being “retired” (e.g. a new power state is about to be entered) (Retire State  68 ), the CPMS control circuit  30 A may transmit an exit command (Exit state  70 ) to the PMU  12  and then return to the PState Chk state  62 . 
       FIG. 5  is a state machine  80  illustrating one embodiment of a coasting compensation mechanism. The state machine  80  may be part of the CPMS control circuit  30 A, in an embodiment, or may be implemented in a distributed fashion over one or more CPMS control circuits  30 A- 30 G, or may be implemented wholly outside the IC  10 , in various embodiments. 
     Coast mode may be a low power mode that may shut down (or “turn off”) the PMU  12  output rail for a pre-determined time and may allow load (e.g. the IC  10 , or more particularly the CPUs and/or GPUs) to operate on the stored energy in the capacitance in and near the load. For example, an IC  10  is often surrounded by “decoupling capacitance” that is connected between power rail and ground rail. The capacitance is charged when the power rail is actively driven to a voltage level by the PMU  12 , and supplies current when noise events or other activities results in instantaneous variations in the load current. In low power modes for the CPUs/GPUs, the active power drain may be known with a reasonable degree of certainty. In some low power modes (e.g. sleep modes), there may be no activity in load. In such circumstances, the PMU  12  may disable the power rail and allow the system to use the stored charge. The rate of discharge may be known for a given capacitance and low power mode, and thus the maximum length of the time period that coast mode may be active is known and thus the maximum time that the coast mode may last before re-enabling the PMU  12  to provide more charge to the power rail. Generally, a power rail may be disabled if the PMU is not actively providing charge (e.g. current) to keep the rail at a certain voltage while the load consumes the current. The rail is enabled if the PMU is actively providing charge. 
     The CPMS control circuit  30 A may receive an enter coast indication when a CPU/GPU enters a state in which coast mode may be used (e.g. a power state low enough that the energy consumption is low and known with a certain degree of circuitry, or a sleep state in which activity in the CPU/GPU stops). Based on the state of the CPUs/GPUs and the energy available in the system (state  82 ), the CPMS control circuit  30 A may determine whether or not there is enough energy available to enter coast mode. If not, the state machine  80  may remain in state  82  and the coast mode may not be entered. 
     Calculating available energy and determining if coast mode is to be entered may be performed in various ways. For example, the CPMS control circuit  30 A may measure the average load current and voltage, and compute the average energy consumption per unit time. Alternatively, the average energy consumption for various states of the CPU/GPU may be provided in a table or other storage to be read by the CPMS control circuit  30 A. After determining the energy consumption rates, determining the current available energy (based on capacitance and voltage), and determining the workload duration and margins from the consumption rate and available energy, the CPMS control circuit  30 A may send a command to the clock control circuit  48  ( FIG. 3 ) to track the voltage drift and adjust the clock based on the voltage drift (state  84 ). The clock control circuit  48  may acknowledge, and the CPMS control circuit  30 A may send a command to the PMU  12  to enter coast mode for a particular rail (state  86 ). The PMU may tri-state the rail (disabling the rail) and the output bridges, temporarily shutting down. The voltage may be monitored by the CPMS control circuit  30 A at the load as the frequency slowly scales (by the clock control circuit  48 ) with the voltage to maintain timing margins. At some point (e.g. after the maximum duration has expired, or in response to an attempt to increase the power state of a CPU/GPU), the state machine may retire the coast mode (state  88 ). The CPMS control circuit  30 A may signal the PMU  12  to start back up in PFM mode to maintain the retention voltage for the load (state  90 ). The CPMS control circuit  30 A may disable coast mode and the PMU  12  may await a command to adjust the voltage for the next on-coming power state to run the next workload. 
       FIG. 6  is a state machine  100  for one embodiment of a dynamic load line compensation circuit. The state machine  80  may be part of the CPMS control circuit  30 A, in an embodiment, or may be implemented in a distributed fashion over one or more CPMS control circuits  30 A- 30 G, or may be implemented wholly outside the IC  10 , in various embodiments. 
     A dynamic load line mechanism may be a dynamic shift in the load line of a PMU  12  between power states and/or within a power state to optimize power savings for the system. It is based on the fact that the maximum current has been computed within a given power state and that the voltage regulator may shift from one load line to the next to maintain lower power in the system. 
     Usually, a load line and voltage guard band is fixed for a given power state. In many cases, the system has one load line and the voltage guard band is fixed for a given power state (but may change between power states). However, with a dynamic load line, CPMS may compute two things in the system. First, the CPMS control circuit  30 A may compute the correct load line for a given power state and cause the shallowest load line (lowest slope) to be used within that power state if it is not already computed and adjusted. Second, if a workload trace has been logged for a given workload, the CPMS control circuit  30 A may check the trace log and compute the shallowest load line for this workload. That is, if the workload trace has a maximum droop spec based on previous information, the CPMS control circuit  30 A may compute the shallowest load line that will meet the spec and send a command to adjust the load line to lower the power is consumed in the system. 
     Workload tracing may be a mechanism in which CPMS identifies a given workload (e.g. a task, an app, a thread from a task etc.) and traces the power management-related events that occur during performance of that workload. The trace may be used in a subsequent execution of the same workload to predict events that may need to be managed in the subsequent execution. 
     In the state machine  100 , an indication that a power state is changing may cause the CPMS control circuit  30 A to determine if the load line may be adjusted (state  102 ). If so, the CPMS control circuit  30 A may transmit a load line adjust command to the PMU  12  (state  104 ). If there is a trace, and the trace check indicates that the load line is ok (state  106 ), the CPMS control circuit  30 A may wait for either a change in power state or other retirement cause to exit the adjusted load line (state  108 ) and may transmit an exit command to the PMU  12  (indicating that it may return to a default load line or that a new load line command may be coming) (state  110 ). 
       FIG. 7  is a block diagram of one embodiment of a system  150 . In the illustrated embodiment, the system  150  includes at least one instance of an integrated circuit (IC)  10  coupled to one or more peripherals  154  and an external memory  158 . The PMU  12  is provided which supplies the supply voltages to the IC  10  as well as one or more supply voltages to the memory  158  and/or the peripherals  154 . 
     The peripherals  154  may include any desired circuitry, depending on the type of system  150 . For example, in one embodiment, the system  150  may be a computing device (e.g., personal computer, laptop computer, etc.), a mobile device (e.g., personal digital assistant (PDA), smart phone, tablet, etc.). In various embodiments of the system  150 , the peripherals  154  may include devices for various types of wireless communication, such as wife, Bluetooth, cellular, global positioning system, etc. The peripherals  154  may also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals  154  may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system  150  may be any type of computing system (e.g. desktop personal computer, laptop, workstation, net top etc.). 
     The external memory  158  may include any type of memory. For example, the external memory  158  may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM, low power versions of the DDR DRAM (e.g. LPDDR, mDDR, etc.), etc. The DRAMs  12 A- 12 B may be any type of such DRAM as listed above. The external memory  158  may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the external memory  158  may include one or more memory devices that are mounted on the IC  10  in a chip-on-chip or package-on-package implementation. 
       FIG. 8  is a block diagram of one embodiment of a computer accessible storage medium  160  storing an electronic description of the IC  10  (reference numeral  162 ) is shown. The description may further include other components such as the portions of the CPMS that may be outside the IC  10  in some embodiments. Generally speaking, a computer accessible storage medium may include any storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium may include storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media may further include volatile or non-volatile memory media such as RAM (e.g. synchronous dynamic RAM (SDRAM), Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, or Flash memory. The storage media may be physically included within the computer to which the storage media provides instructions/data. Alternatively, the storage media may be connected to the computer. For example, the storage media may be connected to the computer over a network or wireless link, such as network attached storage. The storage media may be connected through a peripheral interface such as the Universal Serial Bus (USB). Generally, the computer accessible storage medium  160  may store data in a non-transitory manner, where non-transitory in this context may refer to not transmitting the instructions/data on a signal. For example, non-transitory storage may be volatile (and may lose the stored instructions/data in response to a power down) or non-volatile. 
     Generally, the electronic description  162  stored on the computer accessible storage medium  160  may be a database which can be read by a program and used, directly or indirectly, to fabricate the hardware comprising the IC  10  and/or other components of the system. For example, the description may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist comprises a set of gates which also represent the functionality of the hardware comprising the IC  10 . The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the IC  10 . Alternatively, the description  162  on the computer accessible storage medium  300  may be the netlist (with or without the synthesis library) or the data set, as desired. 
     While the computer accessible storage medium  160  stores a description  162  of the IC  10 , other embodiments may store a description  162  of any portion of the IC  10  and/or any portion of the system. 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Metadata:
Filing Date: 20190723
Publication Date: 20211221
Grant Date: 20211221
Priority Date: 20170213
Inventors: DIBENE, II, JOSEPH T.
SODHI, INDER M.
COX, KEITH
WILLIAMS, III, GERARD R.
Assignee: APPLE INC
CPC Classifications: [{"code": "G06F1/3203", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F1/3203", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3206", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3203", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3206", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F1/3203", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 61386918