PATENT DOCUMENT

Publication Number: US-12204155-B2
Application Number: US-202217850828-A
Country: US
Kind Code: B2

Title: Chip-to-chip optical coupling for photonic integrated circuits

Abstract:
A photonic integrated circuit including multiple elements formed by different processes onto separate chips can be manufactured by defining, via photolithography processes for example, complementary geometries onto each separate chip. Thereafter, the complementary geometries can be aligned and engaged, thereby optically and mechanically intercoupling the several chips to define a single photonic integrated circuit.

Claims:
What is claimed is: 
     
       1. A photonic integrated circuit comprising:
 a first chip defining a first surface and comprising:
 a first surface feature extending from the first surface and having a first triangular cross-sectional profile extending along a first direction and defining a first conductive surface; 
 a second surface feature extending from the first surface and having a second triangular cross-sectional profile extending along a second direction different from the first direction and defining a second conductive surface; and 
 a first photonic circuit element disposed on the first chip and defining an optical axis; and 
 
 a second chip defining a second surface and comprising:
 a third surface feature defined into the second surface and engaged with the first surface feature; 
 a first conductive layer disposed over the third surface feature and conductively coupled to the first conductive surface; 
 a fourth surface feature defined into the second surface and engaged with the second surface feature; 
 a second conductive layer disposed over the fourth surface feature and conductively coupled to the second conductive surface; and 
 a second photonic circuit element disposed on the second chip, aligned with the optical axis, and optically coupled to the first photonic circuit element. 
 
 
     
     
       2. The photonic integrated circuit of  claim 1 , wherein the first chip and the second chip are formed from silicon. 
     
     
       3. The photonic integrated circuit of  claim 1 , wherein:
 the third surface feature has a third triangular cross-sectional profile smaller than the first triangular cross-sectional profile. 
 
     
     
       4. The photonic integrated circuit of  claim 1 , wherein the third surface feature has a rectilinear cross-sectional profile oriented along the first direction. 
     
     
       5. The photonic integrated circuit of  claim 1 , wherein the first photonic circuit element comprises a laser light emitting element. 
     
     
       6. The photonic integrated circuit of  claim 5 , wherein the second photonic circuit element comprises a waveguide. 
     
     
       7. A method of manufacturing a photonic integrated circuit, the method comprising:
 forming a first channel having a first triangular cross-sectional profile into a first chip comprising a first photonic circuit element; 
 forming a second channel into the first chip, the second channel having a second triangular cross-sectional profile at a perpendicular angle relative to the first triangular cross-sectional profile of the first channel; 
 disposing a first conductive layer over the first channel; 
 disposing a second conductive layer over the second channel; 
 forming a first protrusion from a second chip comprising a second photonic circuit element; 
 forming a second protrusion from the second chip, the second protrusion offset by the angle from the first protrusion; 
 disposing a third conductive layer over the first protrusion; 
 disposing a fourth conductive layer over the second protrusion; and 
 aligning the first photonic circuit element with the second photonic circuit element by aligning the first chip with the second chip such that:
 the first protrusion extends into the first channel; 
 the second protrusion extends into the second channel; 
 the first conductive layer conductively couples to the third conductive layer; and 
 the second conductive layer conductively couples to the fourth conductive layer. 
 
 
     
     
       8. The method of  claim 7 , wherein the first channel is formed, at least in part, by a photolithography process. 
     
     
       9. The method of  claim 8 , wherein the second channel is formed, at least in part, by the photolithography process. 
     
     
       10. The method of  claim 8 , wherein the photolithography process comprises an anisotropic etch or a directional etch. 
     
     
       11. The method of  claim 8 , wherein the first protrusion and the second protrusion are formed, at least in part, by the photolithography process. 
     
     
       12. The method of  claim 7 , wherein the first channel and the first protrusion have complementary geometry. 
     
     
       13. The method of  claim 7 , wherein the second channel and the second protrusion have complementary geometry. 
     
     
       14. A photonic integrated circuit comprising:
 a first chip defining a first surface and comprising:
 a first channel defined into the first surface and having a first triangular cross-sectional profile and defining a first conductive surface; 
 a second channel defined into the first surface and perpendicular to the first channel and having a second triangular cross-sectional profile perpendicular to the first triangular cross-sectional profile and defining a second conductive surface; and 
 a first photonic circuit element disposed on the first chip; and 
 
 a second chip defining a second surface and comprising:
 a first protrusion extending from the second surface, engaging the first channel and conductively coupling to the first conductive surface; 
 a second protrusion extending from the second surface, engaging the second channel and conductively coupling to the second conductive surface; 
 a second photonic circuit element disposed on the second chip and optically coupled to the first photonic circuit element as a result of engagement between the first and second channels and the first and second protrusions, respectively. 
 
 
     
     
       15. The photonic integrated circuit of  claim 14 , wherein the first chip is mechanically coupled to the second chip.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a nonprovisional of, and claims the benefit under 35 U.S.C. § 119(e) of, U.S. Provisional Patent Application No. 63/247,992 filed on Sep. 24, 2021, and entitled “Chip-to-Chip Optical Coupling for Photonic Integrated Circuits,” the contents of which are incorporated by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     Embodiments described herein relate to photonic integrated circuits and, in particular, to systems and methods providing accurate and precise alignment when optically intercoupling photonic circuits defined on separate chips. 
     BACKGROUND 
     A photonic integrated circuit can include multiple circuit elements, each formed by different manufacturing processes. Some manufacturing processes are incompatible, so in some cases, a circuit element formed in a first process may be optically and/or mechanically coupled to a second circuit element formed separately in a second process. For example, a laser element formed onto a substrate may be mechanically and optically coupled to a waveguide formed in a separate process onto a different substrate. 
     However, in many cases, precise mechanical alignment between different components is required for high quality optical coupling between different photonic circuit elements. Precise alignment of small-scale components is difficult, time-consuming, and expensive to achieve. 
     SUMMARY 
     Embodiments described herein reference systems and methods for effective precise and accurate lateral and vertical alignment between elements (and in particular optical axes of optical elements) of different chips, each comprising at least one photonic element of a photonic circuit. In one example, an input/output facet of a first waveguide formed/defined on a first chip may be optically coupled to an input/output facet of a second waveguide formed/defined on a second chip. In such constructions, precise mutual alignment of the input/output facets, in all axes, may be required for optimal optical coupling between the first waveguide and the second waveguide. 
     More generally, as known to a person of skill in the art, different photonic elements may be manufactured in different conditions and/or with different processes. Some such processes may be incompatible with one another. For example, temperatures required to anneal a silicon waveguide may be incompatible with semiconductor elements, conductive layers, and/or functional layers of a photodiode or light emitting element, such as a laser. As a result, a photonic integrated circuit that requires multiple discrete photonic elements may require mechanical assembly of different parts, manufactured using different processes. 
     In such examples, embodiments described herein define multidimensional alignment guides by leveraging highly repeatable and highly accurate photolithography operations. More specifically, two chips—each having defined respectively thereon at least one photonic circuit element—can be precisely aligned with one another (and optically intercoupled; optical axes of different elements can be precisely aligned) by defining, from each chip, at least one alignment guide also referred to herein as a “surface feature.” Surface features of each chip can be defined to complement one another; a surface feature that extends proud of a surface of one chip may be configured to engage with and extend into a surface feature that extends into a surface of a second chip. 
     For example, some embodiments described herein reference a photonic integrated circuit formed by bonding two separate chips together. A first substrate can have defined thereon a first photonic element and a second substrate can have defined thereon a second photonic circuit element. Each of the chips can include respective surface features configured to engage with corresponding surface features of the opposite substrate. For example, the first substrate may include two channels, oriented at different angles that are configured to engage with two protrusion of the other substrate oriented in the same manner. As a result of these and other described constructions, the two chips can be accurately mechanically aligned, thereby optically intercoupling (aligning optical axes) the first photonic element with the second photonic element. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Reference will now be made to representative embodiments illustrated in the accompanying figures. It should be understood that the following descriptions are not intended to limit this disclosure to one included embodiment. To the contrary, the disclosure provided herein is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the described embodiments, and as defined by the appended claims. 
         FIGS.  1 A- 1 B  depict a simplified cross-section diagram of an operation of aligning two photonic circuit chips by leveraging complementary geometry, such as described herein. 
         FIGS.  2 A- 2 D  depict example views of a substrate as described herein that can be formed with a set of surface features that may be leveraged with complementary geometry of a second substrate to precisely align with that substrate, such as described herein. 
         FIG.  3    depicts a simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
         FIG.  4    depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
         FIG.  5    depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
         FIG.  6    depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
         FIGS.  7 A- 7 C  depict progressive relative alignments of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
         FIG.  8    is a flowchart depicting example operations of a method of aligning chips, such as described herein. 
     
    
    
     The use of the same or similar reference numerals in different figures indicates similar, related, or identical items. 
     The use of cross-hatching or shading in the accompanying figures is generally provided to clarify the boundaries between adjacent elements and also to facilitate legibility of the figures. Accordingly, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, element proportions, element dimensions, commonalities of similarly illustrated elements, or any other characteristic, attribute, or property for any element illustrated in the accompanying figures. 
     Additionally, it should be understood that the proportions and dimensions (either relative or absolute) of the various features and elements (and collections and groupings thereof) and the boundaries, separations, and positional relationships presented therebetween, are provided in the accompanying figures merely to facilitate an understanding of the various embodiments described herein and, accordingly, may not necessarily be presented or illustrated to scale, and are not intended to indicate any preference or requirement for an illustrated embodiment to the exclusion of embodiments described with reference thereto. 
     DETAILED DESCRIPTION 
     Embodiments described herein are directed to systems and methods for defining photonic integrated circuits. A photonic integrated circuit, as described herein, can be architected for any suitable computational, imaging, information transfer, or other purpose. As known to a person of skill in the art, a photonic integrated circuit can include a number of elements, including, but not limited to, lasers, photodiodes, interferometers, waveguides, lenses, polarization filters, polarizers, couplers, and so on. 
     In many cases, a photonic circuit element may be manufactured using a process specific to that photonic circuit element. For example, manufacturing processes necessary to define a light source (such as a laser) are necessarily different from manufacturing processes necessary to define a silicon or silicon nitride waveguide. Continuing the example, metallic and/or conductive layers of the laser may be incompatible with temperatures necessary to anneal the silicon waveguide. Manufacturing temperature is merely one example incompatibility; it may be appreciated that many different photonic circuit element manufacturing processes may include one or more operations that are incompatible with one another. 
     To account for manufacturing incompatibilities, among other reasons, it is often the case that a photonic integrated circuit includes components that are separately manufactured on different chips and, thereafter, assembled together. In many cases, such manufacturing/assembly techniques are referred to as “flip-chip” designs in which one chip is positioned over as second chip and coupled thereto to define a single circuit. 
     However, conventional flip-chip techniques require mechanical relative alignment between chips, which may be particularly challenging for small-scale chips, such as those that may include a limited number of photonic integrated circuit elements. As a result, conventional flip-chip manufacturing requires high alignment tolerance. For photonic integrated circuits, high alignment tolerances may not be suitable for reliably, repeatably, and precisely optically coupling together two or more singulated chips, each including one or more phonic integrated circuits. 
     For example, among other issues, flip-chip bonding of two chips can introduce lateral and/or vertical misalignment of certain circuit elements. As one non-limiting example, standoffs or posts that attach and/or offset flip-chip bonded chips set Z-axis (e.g., vertical) alignment but do not assist in X-Y (e.g., lateral) alignment. Further, the vertical alignment guiding as provided by standoffs or posts of conventional methods may only provide vertical alignment accuracy or precision within manufacturing tolerances of the standoffs or posts. 
     For photonic circuits, relative misalignment of chips may be particularly problematic. For example, in conventional flip-chip implementations in which a first chip includes a first waveguide and a second chip includes a second waveguide, relative three dimensional alignment between the first and second waveguides cannot be ensured. In particular, lateral misalignment may lead to loss of light transmitted from the first waveguide to the second waveguide, and thus to power loss for the overall photonic integrated circuit. The same is true, although often to a lesser extent, for vertical misalignment between chips and their component waveguides. 
     To account for these and other drawbacks of conventional flip-chip manufacturing techniques, embodiments described herein reference systems and methods for leveraging photolithography (and similar high-precision manufacturing techniques) to define complementary geometry on different chips to be coupled via a flip-chip methodology. The complementary geometry can be used as an alignment guide for two or three dimensions of relative alignment. As a result of systems and methods described herein, two or more chips including complementary geometry can be relatively aligned with the same accuracy and precision as the photolithography process that was leveraged to define the complementary geometry on each chip. As used herein the phrase “complementary geometry” refers generally to tongue-in-groove mating structures; one structure typically extends proud of a surface and another structure typically defines a cavity extending into a different surface. Complementary structures can have the same cross-sectional profile or different cross-sectional profiles. 
     For example, a first substrate can be used as a base substrate to form a light source that provides optical power to a photonic integrated circuit, collectively defining a first chip. The photonic integrated circuit and/or the light source can be optically coupled to other photonic circuit elements disposed on the base substrate. For example, the light source may be optically coupled to a waveguide that defines an input/output facet. 
     A second substrate can be used as a base substrate to form a waveguide configured to direct light emitted from the light source (e.g., via the first waveguide) to another circuit element of the same photonic integrated circuit, collectively defining a second chip. As noted above, process steps required to manufacture a light source may be thermally incompatible with process steps required to manufacture an annealed waveguide on the second substrate. As a result, the light source, the first waveguide, and the first substrate (the first chip) may be manufactured separately from the second waveguide and the second substrate (the second chip). In this example embodiment, during manufacturing of the light source, one or more surface features can be formed on, formed into, and/or defined from the first substrate during a photolithography process also used to define one or more features of the light source itself. As a result, a single photolithographic process defines positioning of both the light source and each individual surface feature. 
     Similarly, the waveguide of this example can be manufactured on the second substrate. A photolithography process leveraged to define geometry of the waveguide can be also used to define two or more surface features on the second substrate that complement the surface features of the first substrate. In a more general phrasing, a single manufacturing step can be used to define multiple functional elements on a chip, including channels or protrusion that may, in later manufacturing steps (following singulation, in some examples) be used for alignment guiding purposes as described herein. These operations may be selected in certain embodiments so that size and shape of different structures formed onto and/or into different substrates can be defined with the precision of a single photolithography step. 
     As a result of this construction, the surface features of each chip can be used as interlocking/intercoupling/mating alignment guides that, when engaged, provide precise threedimensional alignment of the light source and an input facet of the optical waveguide. 
     Surface features as described herein can be formed in a number of suitable ways. For example, in some embodiments, an anisotropic etch process may be used to define a linear channel and/or a linear protrusion, each having a cross-sectional profile having a rectangular shape. In other cases, a directional etch process may be used to define a channel with a triangular cross-sectional profile and, correspondingly, a protrusion having a triangular cross-sectional profile each extending for a distance in a linear manner. In other cases, a protrusion may have a rectangular cross-section, whereas a channel corresponding to the protrusion may have a triangular profile; each can extend along a linear path. In other cases, a linear path may not be required; curved paths may be possible in some examples. In these examples, protruding surface features can be configured to interlock with a corresponding, and complementary channel surface feature. In another phrasing, an embossed surface feature can be configured to engage with a debossed surface feature. 
     In many embodiments, multiple surface features are formed onto (or into, or disposed on, or formed from) a single chip so as to constrain motion and/or position of that chip in multiple dimensions when the chip is positioned relative to another chip having complementary geometry. For example, a first channel defined into a substrate surface can be oriented along a first axis and a second channel defined into the same substrate surface can be oriented along a second axis perpendicular to the first axis. In other cases, two or more channels can overlap, so as to define a cross-shape, an L-shape, or an X-shape. Many configurations are possible. 
     In some embodiments, debossed surface features may have a different cross-sectional profile geometry than complementary embossed surface features. For example, a channel with a triangular cross-sectional profile (e.g., formed with a directional etch process) may be wider than a complementary protrusion that also has a triangular cross-sectional profile. In other cases, a protrusion may have a rectangular cross-sectional profile, and may be configured to align within a channel having a triangular cross-sectional profile. 
     In some cases, multiple channels can be aligned in parallel, with different depth, length, or cross-sectional profile geometry. Rectilinear channels may not be required; channels can bow, arch, or otherwise curve or have multiple differently-oriented discrete portions. In some examples, channels of different size can be used to progressively align two chips together. In other cases, a channel may not have a single width and may instead be constructed with a tapered width that can be used to guide alignment of a second substrate toward a narrow end of the channel. 
     These foregoing and other embodiments are discussed below with reference to  FIGS.  1 A- 8   . However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanation only and should not be construed as limiting. 
       FIGS.  1 A- 1 B  depict a simplified cross-section diagram of an operation of aligning two photonic circuit chips by leveraging complementary geometry, such as described herein. 
     In particular,  FIG.  1 A  depicts a diagram of a portion of a photonic integrated circuit  100  that is defined at least in part by two chips that can be assembled and intercoupled by leveraging a flip-chip technique, as described herein. In particular, a first chip  102  can serve as a base substrate over which a second chip  104  can be positioned. 
     The first chip  102  and the second chip  104  can each include different photonic circuit elements that may require precise multi-axis alignment. More specifically, the photonic circuit elements of each chip may require precise alignment along an X axis (e.g., from right to left of  FIG.  1 A ), along a Y axis (e.g., into or out of  FIG.  1 A ), and along a Z axis (e.g., from top to bottom of  FIG.  1 A ). In this example, the X and Y axes can define a surface plane of the first chip  102  and the Z axis can extend through a thickness of the first chip  102 . Misalignment of the two photonic circuit elements may result in substantial optical power loss and/or low coupling efficiency which, in turn, can affect and degrade performance of the photonic integrated circuit  100 . 
     As with other embodiments described herein, the first chip  102  and the second chip  104  each are formed with complementary geometry that, when mutually engaged, precisely aligns the first chip  102  with the second chip  104 . 
     For example, in some embodiments, the second chip  104  can include a light source intended to be optically coupled to a waveguide defined on or through the first chip  102 . This is merely one example; it may be appreciated that either chip can include one or more passive or active optical elements or photonic elements or semiconductor circuit elements that, in turn may be configured to align with a corresponding optical coupling or conductive coupling of the other chip. For simplicity of description, the embodiments that follow reference intercoupled chips that include a single photonic circuit element coupling to a single photonic circuit element, but it may be appreciated that this is merely one example, and that other architectures and implementations can leverage embodiments described herein. 
     In this example, the second chip  104  includes a base substrate  106  over which at least a portion of a photonic integrated circuit element  108  may be formed (e.g., a light source). In some cases, the base substrate  106  is formed form silicon (e.g., bulk silicon) although this may not be required of all embodiments. 
     The second chip  104  can also define at least two protrusions, identified as the protrusions  110  and  112 . In this example, the protrusions  110  and  112  are show as extending from a surface of the photonic integrated element  108 , but this may not be required of all embodiments. For example, in some cases, the protrusions  110 ,  112  can be formed from a surface of the base substrate  106 . In further cases, one or more protrusions and/or one or more channels may be formed on, disposed on, or otherwise formed from the same base substrate of the same chip. More specifically, a single chip can include both protrusions and channels configured to mate with corresponding protrusions and channels of another chip. 
     The protrusions  110 ,  112  are shown with identical cross-sectional profiles, but this may not be required of all embodiments. For example, in some cases, the protrusion  110  may be shorter along the Z-axis than the protrusion  112 , the protrusion  110  may be deeper along the Z-axis than the protrusion  112 . In other cases, the protrusion  110  may have a circular cross section/profile, whereas the protrusion  112  may have a triangular or otherwise polygonal cross section. A person of skill in the art may readily appreciate that any suitable arrangement and geometry of the protrusions  110 ,  112  may be used. 
     The first chip  102 , similar to the second chip  104 , can include a base substrate  114 . The base substrate  114  may be formed from silicon, although this is not required of all embodiments. 
     The base substrate  114  can have formed (or disposed, placed, and so on) thereon at least a portion of a photonic circuit element  116  (e.g., a waveguide). As noted above, the photonic circuit element  116  may be configured to precisely align with the photonic circuit element  108  when the second chip  104  is positioned over and aligned with the first chip  102 . More specifically, an optical axis (light emitting axis, input facet, output facet, and so on) of the photonic circuit element  116  may be configured to precisely align with the photonic circuit element  108 . In one example construction, the photonic circuit element  116  may be a first waveguide and the second photonic circuit element  108  may be a second waveguide. 
     To effect such alignment, the base substrate  114  includes at least two channels, identified as the channels  118  and  120 . In this example, the channels  118  and  120  are show as extending from a surface of the base substrate  114 , but this may not be required of all embodiments. For example, in some cases, the protrusions  110 ,  112  can be formed from a surface of the photonic integrated circuit element  116 . 
     As may be appreciated by a person of skill in the art, the channels  118 ,  120  and the protrusions  110 ,  112  can be formed with complementary geometry such that when the second chip  104  is positioned over the first chip  102 , and the second chip  104  is advanced in the XY plane, the protrusions  110 ,  112  can become engaged with the channels  118 ,  120  and the triangular geometry of the channels  118 ,  120  can guide the protrusion  110 ,  112  to a specific Z position, thereby precisely aligning the photonic circuit element  116  and the photonic circuit element  108 . More broadly, the dual alignment channel geometry illustrated in  FIGS.  1 A and  1 B  provides for alignment along all three primary axes, namely the X-axis, the Y-axis and the Z-axis. 
     These foregoing embodiments depicted in  FIGS.  1 A- 1 B  and the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of aligning two chips to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof. 
     Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings. 
     For example,  FIGS.  2 A- 2 D  depict example views of a chip as described herein that can be formed with a set of surface features that may be leveraged with complementary geometry of corresponding surface features of a second chip to precisely align with that chip, such as described herein. 
     For example,  FIG.  2 A  depicts a view of a chip  200  that includes a base layer  202  onto which one or more features can be formed that, in turn, can define at least a portion of a photonic integrated circuit, such as described herein. For example, the chip can include an elevated portion  204  that supports a waveguide  206  that can define an input/output edge facet configured to optically and/or mechanically couple to an input/output edge facet of another waveguide formed/defined on a separate substrate. 
     Adjacent to or otherwise separated from the elevated portion  204 , can be defined two or more surface features, identified as the surface feature  208  and the surface feature  210 . The surface feature  208  and/or the surface feature  210  can be formed into or out of an upper surface of the base layer  202 . More generally, the surface feature  208  and/or the surface feature  210  may be embossed features or debossed features; the surface feature  208  and/or the surface feature  210  may define one or more channels or may define one or more protrusions. 
     The surface feature  208  and/or the surface feature  210  can exhibit any suitable cross-sectional profile or geometry. In the illustrated example, the surface feature  208  and/or the surface feature  210  each have a triangular cross-sectional profile that may be formed via photolithographically-masked directional etch or anisotropic etch processes. This is merely one example cross-sectional profile; in other examples, a surface feature as described herein can be formed to have any suitable shape. 
     In the illustrated example, the surface feature  208  and the surface feature  210  have a generally rectilinear shape, and are arranged in parallel to one another. This is not required of all embodiments, for example in  FIG.  2 B , the surface feature  210  may be oriented at an angle perpendicular to the surface feature  210 . 
     In the examples illustrated in  FIGS.  2 A- 2 B , the surface feature  208  and the surface feature  210  are shown as the only two surface features defined onto the chip  200 ; this is not required of all embodiments. For example, as shown in  FIG.  2 C , more than two surface features can be defined. More particularly, in this example, a third surface feature  212  is defined between the surface feature  208  and the surface feature  210 . 
     In the examples illustrated in  FIGS.  2 A- 2 C , each surface feature—whether embossed or debossed from a surface or layer of the chip  200  is shown as having the same size and cross-sectional profile. This is not required of all embodiments. For example, as shown in  FIG.  2 D , the surface feature  208  and the surface feature  210  may have different sizes and/or may be arranged at an oblique angle relative to one another. In this example, the surface feature  210  is depicted has larger than the surface feature  208 , which in turn is oriented at a non-parallel, non-perpendicular, oblique angle relative to the surface feature  210 . 
     Each of the example embodiments depicted in  FIGS.  2 A- 2 D  illustrate example possible geometries of surface features that may be formed into a chip, such as the first chip  102  or the second chip  104  of  FIGS.  1 A- 1 B . More generally, for these embodiments show in  FIGS.  2 A- 2 D , it may be appreciated that a similar pattern to that which is shown can be formed into a second chip or chip in order that the chip  200  can be coupled to and precisely aligned with the other chip. 
     These foregoing embodiments depicted in  FIGS.  2 A- 2 D  and the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of defining and/or positioning surface features onto a chip for aligning that chip with another chip having complementary geometry to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof. 
     Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings. 
     For example, in many embodiments, a surface feature extending proud of a surface configured to mate with and/or interface with a surface feature defining a channel may have different cross-sectional profiles. For example,  FIG.  3    depicts a simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
     In this embodiment, a photonic integrated circuit  300  can be formed by mating a first chip  302  with a second chip  304 . The first chip includes a first circuit element  306  (e.g., waveguide, light source, splitter, delay line, Bragg reflector, other reflectors, mode field converters, and so on) may be aligned with a second circuit element  308  of the second chip  304  when surface features of the first and second chips are engaged. 
     More particularly, in the illustrated embodiment, the first chip  302  includes a surface feature  310  and a surface feature  312 , each having a rectangular cross-section. Correspondingly, the second chip  304  includes a surface feature  314  and a surface feature  316 , each having a triangular cross-section. In this example, the surface feature  310  may be configured to mate with and/or engage with the surface feature  314  and the surface feature  312  may be configured to mate with and/or engage with the surface feature  316 . 
     In other cases, protrusions can have a triangular cross-sectional profile and channels, as described herein, can have a different cross-sectional profile. For example,  FIG.  4    depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
     In this embodiment, a photonic integrated circuit  400  can be formed by mating a first chip  402  with a second chip  404 . The first chip includes a first circuit element  406  that may be aligned with a second circuit element  408  of the second chip  404  when surface features of the first and second chips are engaged. 
     More particularly, in the illustrated embodiment, the first chip  402  includes a surface feature  410  and a surface feature  412 , each having a triangular cross-section. Correspondingly, the second chip  404  includes a surface feature  414  and a surface feature  416 , each having a rectangular cross-section. In this example, the surface feature  410  may be configured to mate with and/or engage with the surface feature  414  and the surface feature  412  may be configured to mate with and/or engage with the surface feature  416 . 
     In yet further examples, mating of surface features as described herein can serve a functional purpose, in addition to a mechanical and/or alignment purpose. For example,  FIG.  5    depicts a simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. 
     In this embodiment, a photonic integrated circuit  500  can be formed by mating and conductively coupling a first chip  502  with a second chip  504 . More particularly, in the illustrated embodiment, the first chip  502  includes a surface feature  506  which may be a solder ball or other conductive surface. The first chip may also include a surface feature  508 , which may also be a solder ball or other conductive surface. Each of the surface features  506 ,  508  can have a circular or curved cross-section, but this is not required of all embodiments. 
     As with other embodiments described herein, the second chip  504  includes a surface feature  512  and a surface feature  514 , each having a triangular cross-section. In this example, the surface feature  508  may be configured to mate with and/or engage with the surface feature  512  and the surface feature  506  may be configured to mate with and/or engage with the surface feature  514 . In this embodiment, the conductive surface features of each chip (which can extend into the surface features  512 ,  514 ) can form a conductive coupling between the chips, electrically coupling semiconductor circuitry defined thereon or therein. In addition, as with other embodiments described herein, the surface features may provide for precise alignment of photonic integrated circuit elements, such as an element  516  of the first chip and an element  518  of the second chip. 
     These foregoing embodiments depicted in  FIGS.  2 A- 5    and the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of defining and/or positioning surface features onto a chip for aligning that chip with another chip having complementary geometry to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof. 
     Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings. 
     Accordingly, more generally and broadly, it may be appreciated that photonic circuit elements formed on different chips can be aligned and/or mechanically, optically, and/or electrically coupled to one another. 
     It may be appreciated that complementary geometry defined in part by photonic circuit element manufacturing operations can be defined in any number of suitable ways. In some examples, different channels and corresponding protrusions can intersect. In some cases, channels and protrusions can be disposed parallel to one another and perpendicular to an optical axis of a photonic component of one phonic integrated circuit defined on a chip. In other cases, a single chip can include at least one channel feature and at least one protruding feature. 
     In some cases, a channel can have a tapering geometry to encourage particular alignment by sliding a protruding feature into the tapering channel. In this manner, optical components formed onto, into, or otherwise disposed on each respective chip can be aligned so as to share a common optical axis. In other cases, channels may have keyed depth so that optical alignment will only be achieved if particular protrusions are aligned with particular channels. 
     In yet further examples, an alignment structure as described herein can be used to align both a semiconductor circuit and a photonic circuit, each formed onto and/or defined onto respective chips. For example,  FIG.  6    depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. In this example, a photonic integrated circuit  600  includes a first chip  602  disposed over a second chip  604 . The first chip  602  and the second chip  604  are aligned in part by complementary geometry, as described herein. More specifically, a photonic circuit element  606   a  of the first chip  602  can be aligned with a second photonic circuit element  606   b  of the second chip  604 . 
     As with other embodiments described herein, the alignment can be effected by mating and/or engagement of surface features of the first chip  602  and the second chip  604 . In particular, the first chip  602  can include a protrusion  608  that mates with a channel  610  of the second chip  604 . In addition, the first chip  602  can include a second protrusion  614  that mates with a channel  612  of the second chip  604 . 
     In addition to optical coupling between the photonic circuit element  606   a  and the photonic circuit element  606   b , the first chip  602  and the second chip  604  can be conductively coupled in one or more suitable locations to conductively intercouple silicon circuitry, either digital or analog, of the respective chips. For example, solder balls  616  can conductively couple conductive pads or traces of the first chip  602  with a circuit or circuit element  618  of the second chip  604 . More specifically the solder balls  616  can facilitate one or more electrical connections between the first chip  602  and the second chip  604 ; in some cases, the solder balls may be reflowed or otherwise melted in a manufacturing step in order to conductively and mechanically couple the first and second chips to one another. 
     It may be appreciated, more generally and broadly, that other constructions of a multi-chip architecture as described herein can emit light and/or receive light in any suitable position or location; in some cases, the circuit element  618  can be configured to emit light or receive light, for example. 
     These foregoing embodiments depicted in  FIGS.  2 A- 6    and the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of defining and/or positioning surface features onto a chip for aligning that chip with another chip having complementary geometry to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof. 
     Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings. 
     For example, generally and broadly, it may be appreciated that any structure as shown in these figures and/or described herein can be formed onto any suitable base substrate. After complementary features are defined on separate chips, at least one of the chips may be flipped and/or otherwise positioned onto a second chip, after which an alignment between the two chips may be guided through three dimensions. 
     In other cases, a channel as described herein may be both embossed and debossed. For example, regions around a channel can be etched away such that the channel is defined at least in part by sidewalls that extend proud of a substrate surface. 
       FIG.  7 A  depicts a first stage of defining a bonded flip-chip structure, as described herein. In particular, a set of separately manufactured chips  700  may include a first chip  702  and a second chip  704 . The first chip, as with other embodiments described herein can include a first surface feature  706  and a second surface feature  708 , each of which extend from a surface of the first chip  702 . In a complementary manner, the second chip  704  can include a first surface feature  710  and a second surface feature  712  that are respectively configured to mate with and engage with the first surface feature  706  and the second surface feature  708 . As a result of this set of complementary geometries, the first chip  702  can be flipped/inverted onto the second chip  704  so as to effect precise alignment (lateral and vertical) between a first photonic circuit element  716  defined on the first chip  702  and a second photonic circuit element  718  defined on the second chip  704 , such as shown in  FIG.  7 B . After inversion of the first chip  702  onto the second chip  704 , the first chip  704  may be mechanically guided (e.g., via pick and place machine, manually, by vibration, and so on) such that the respective surface feature of each chip are engaged, such as shown in  FIG.  7 C . 
       FIG.  8    is a flowchart depicting example operations of a method of aligning chips, such as described herein. In this embodiment, the method  800  includes operation  802  at which a chip is selected. Thereafter, at operation  804 , two or more alignment features can be formed into or onto the chip. Finally, at operation  806 , the chip can be aligned with corresponding features of another chip, and the two chips can be affixed to one another in a suitable manner. 
     As used herein, the phrase “at least one of” preceding a series of items, with the term “and” or “or” to separate any of the items, modifies the list as a whole, rather than each member of the list. The phrase “at least one of” does not require selection of at least one of each item listed; rather, the phrase allows a meaning that includes at a minimum one of any of the items, and/or at a minimum one of any combination of the items, and/or at a minimum one of each of the items. By way of example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; any combination of A, B, and C; and/or one or more of each of A, B, and C. Similarly, it may be appreciated that an order of elements presented for a conjunctive or disjunctive list provided herein should not be construed as limiting the disclosure to only that order provided. 
     One may appreciate that although many embodiments are disclosed above, that the operations and steps presented with respect to methods and techniques described herein are meant as exemplary and accordingly are not exhaustive. One may further appreciate that alternate step order or fewer or additional operations may be required or desired for particular embodiments. 
     Although the disclosure above is described in terms of various exemplary embodiments and implementations, it should be understood that the various features, aspects and functionality described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment with which they are described, but instead can be applied, alone or in various combinations, to one or more of the some embodiments of the invention, whether or not such embodiments are described and whether or not such features are presented as being a part of a described embodiment. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments but is instead defined by the claims herein presented.

Metadata:
Filing Date: 20220627
Publication Date: 20250121
Grant Date: 20250121
Priority Date: 20210924
Inventors: WITMER, JEREMY D.
BISMUTO, ALFREDO
HILL, Jeffrey T.
SUH, JUNKYO
YILMAZ, Yigit O.
Assignee: APPLE INC
CPC Classifications: [{"code": "G02B6/4232", "inventive": false, "first": false, "tree": "[]"}, {"code": "G02B6/423", "inventive": true, "first": true, "tree": "[]"}, {"code": "G02B6/423", "inventive": true, "first": true, "tree": "[]"}, {"code": "G02B6/423", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 85706031