PATENT DOCUMENT

Publication Number: US-10797125-B2
Application Number: US-201815985485-A
Country: US
Kind Code: B2

Title: Electronic device having display circuitry with rounded corners

Abstract:
A display may have display driver circuitry. Signal routing lines may supply multiplexed signals from the display driver circuitry to demultiplexer circuitry. The demultiplexer circuitry may provide corresponding demultiplexed signals to the pixels over signal routing lines. The demultiplexer circuitry may have demultiplexer circuit blocks such as 1:N demultiplexer circuit blocks. Each of the demultiplexer circuit blocks may have the same area and layout. The demultiplexer circuit blocks may run across the width of the display. A first portion of the demultiplexer circuit blocks may extend in a straight line parallel to an edge of the active area. A second portion of the demultiplexer circuit blocks may be arranged in a staircase pattern that angles away from the first portion of demultiplexer circuit blocks.

Claims:
What is claimed is: 
     
       1. A display, comprising;
 pixels configured to form an active area with rounded corners that displays images; 
 display driver circuitry; and 
 demultiplexer circuitry between the display driver circuitry and the pixels, wherein the display driver circuitry conveys signals to the demultiplexer circuitry to display the images and wherein the demultiplexer circuitry has a first portion with first demultiplexers that extend along a first dimension and a second portion with second demultiplexers that extend in a staircase pattern along a second dimension that is oriented at a non-zero angle with respect to the first dimension. 
 
     
     
       2. The display defined in  claim 1  further comprising first and second routing lines, wherein the first routing lines fan out from the display driver circuitry and are configured to provide the signals from the display driver circuitry to the demultiplexer circuitry. 
     
     
       3. The display defined in  claim 2  wherein the second routing lines fan out from the demultiplexer circuitry, wherein the demultiplexer circuitry is configured to demultiplex the signals from the display driver circuitry, and wherein the second routing lines are configured to provide the demultiplexed signals from the demultiplexer circuitry to the pixels. 
     
     
       4. The display defined in  claim 1  wherein the pixels comprise organic light-emitting diode display pixels. 
     
     
       5. The display defined in  claim 1  wherein the non-zero angle has a value of 0.5-10°. 
     
     
       6. The display defined in  claim 5  wherein the first and second demultiplexers are 1:N demultiplexers and wherein N has a value of 2-5. 
     
     
       7. The display defined in  claim 1  wherein the each of the first demultiplexers and each of the second demultiplexers is a 1:3 demultiplexer. 
     
     
       8. The display defined in  claim 1  wherein the first demultiplexers have a first size, wherein the second demultiplexers have a second size, and wherein the first size and the second size are equal. 
     
     
       9. A display, comprising:
 pixels configured to form an active area that displays images; 
 demultiplexer circuitry having a first set of demultiplexer circuit blocks that extend in a straight line along an edge of the active area and having a second set of demultiplexer circuit blocks arranged in a staircase pattern, wherein the second set of demultiplexer circuit blocks is not parallel to the first set of demultiplexer circuit blocks; and 
 signal lines configured to route demultiplexed signals from the demultiplexer circuitry to the pixels. 
 
     
     
       10. The display defined in  claim 9  further comprising routing lines that route multiplexed signals to the demultiplexer circuitry from at least one integrated circuit. 
     
     
       11. The display defined in  claim 10  wherein the integrated circuit comprises a display driver integrated circuit. 
     
     
       12. The display defined in  claim 11  wherein the first demultiplexer circuit blocks each have a first area, wherein the second demultiplexer circuit blocks each have a second area, and wherein the first area and the second area are equal. 
     
     
       13. The display defined in  claim 12  wherein the active area has at least one rounded corner.

Description:
This application claims the benefit of provisional patent application No. 62/552,288, filed Aug. 30, 2017, which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     This relates generally to electronic devices and, more particularly, to electronic devices with displays. 
     Electronic devices often include displays. For example, devices such as cellular telephones, tablet computers, laptop computers, wristwatch devices, and other devices may have displays. 
     It can be challenging to incorporate displays into electronic devices. Space is often at a premium, particularly in portable devices. If care it not taken, more area may be consumed by display circuitry than desired. 
     SUMMARY 
     An electronic device may have a housing and a display in the housing. An array of pixels may form an active display area that displays images for a user. The display may have an inactive area that contains display driver circuitry and other structures that do not display images. Display driver circuitry may be formed in the inactive area. The display driver circuitry may include one or more display driver integrated circuits. Signal routing lines may supply multiplexed signals such as multiplexed data signals from the display driver circuitry to demultiplexer circuitry. 
     The demultiplexer circuitry may provide corresponding demultiplexed signals to the pixels in the active area over signal routing lines. The demultiplexer circuitry may have demultiplexer circuit blocks. Each of the demultiplexer circuit blocks may have the same area and layout. The demultiplexer circuit blocks may run in a strip across the width of the display. A first set of the demultiplexer circuit blocks may extend in a straight line parallel to an edge of the active area. A second set of the demultiplexer circuit blocks may be arranged in a staircase pattern forming a line that angles away from the line of the first set of demultiplexer circuit blocks. This arrangement may help relieve signal routing line crowing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view of an illustrative electronic device in accordance with an embodiment. 
         FIG. 2  is a circuit diagram of a portion of an array of pixels in a display in accordance with an embodiment. 
         FIG. 3  is a top view of a portion of a display showing an illustrative layout for demultiplexer circuitry and signal lines in an inactive display region and a portion of an associated active display area with rounded corners in accordance with an embodiment. 
         FIG. 4  is a circuit layout diagram showing how some of the demultiplexer circuit blocks in the demultiplexer circuitry may be arranged in a staircase pattern in accordance with an embodiment. 
         FIG. 5  is a top view of a portion of a display in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     An electronic device such as electronic device  10  of  FIG. 1  may have a display. Electronic device  10  may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wrist-watch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user&#39;s head, or other wearable or miniature device, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, equipment that implements the functionality of two or more of these devices, or other electronic equipment. In the illustrative configuration of  FIG. 1 , device  10  is a portable device such as a cellular telephone, media player, tablet computer, or other portable computing device. Other configurations may be used for device  10  if desired. The example of  FIG. 1  is merely illustrative. 
     Device  10  may include a display such as display  14 . Display  14  may be mounted in a housing such as housing  12 . Housing  12 , which may sometimes be referred to as an enclosure or case, may be formed of plastic, glass, ceramics, fiber composites, metal (e.g., stainless steel, aluminum, etc.), other suitable materials, or a combination of any two or more of these materials. Housing  12  may be formed using a unibody configuration in which some or all of housing  12  is machined or molded as a single structure or may be formed using multiple structures (e.g., an internal frame structure, one or more structures that form exterior housing surfaces, etc.). 
     Display  14  may be a touch screen display that incorporates a layer of conductive capacitive touch sensor electrodes or other touch sensor components (e.g., resistive touch sensor components, acoustic touch sensor components, force-based touch sensor components, light-based touch sensor components, etc.) or may be a display that is not touch-sensitive. Capacitive touch screen electrodes may be formed from an array of indium tin oxide pads or other transparent conductive structures. 
     Display  14  may include an array of pixels  18 . Pixels  18  may be arranged in rows and columns in an array that covers most or all of the front face of device  10  (as an example). The array of pixels  18  in device  10  may display images for a user and may therefore sometimes be referred to the active area of display  14 . The active area of display  14  may have a rectangular shape with rounded (curved) corners or other suitable shape and may, if desired, be bordered along one or more edges by an inactive border region (e.g., a portion of display  14  that is free of pixels  18  and that does not emit light). In the illustrative configuration of  FIG. 1 , display  14  has rounded corners  14 R to accommodate rounded corners  12 R of housing  12 . 
     A display cover layer (e.g., a transparent layer of glass, plastic, or other material with rounded corners) may overlap the active area and the inactive area of display  14 . The portion of the display cover layer overlapping pixels  18  of the active area may be free of masking materials to allow users to view images being displayed by the pixels. The portion of the display cover layer that overlaps the inactive area may have an internal coating layer of opaque masking material (e.g., black ink, white ink, gray ink, ink of non-neutral colors, etc.) to help hide display circuitry (integrated circuits, signal lines, etc.) and other inactive area structures from view by a user. 
     Display system  14  may be a liquid crystal display with liquid crystal display pixels, an organic light-emitting diode display with organic light-emitting diode pixels, a display having an array of crystalline semiconductor light-emitting diode dies, and/or displays based on other display technologies. As shown in  FIG. 2 , each pixel  18  may include circuitry such as transistor(s)  20 . Transistors  20  may be, for example, thin-film transistors that are fabricated on a display substrate. Transistors  20  may be used in forming pixel circuitry in each pixel  18 . For example, in a light-emitting diode display such as an organic light-emitting diode display, each pixel  18  may include an organic light-emitting diode such as diode  22  that is controlled by corresponding thin-film transistor pixel circuitry formed from one or more transistors  20 . The pixel circuitry of each pixel  18  may be configured to receive data on signal lines such a data lines D. One or more control lines G (sometimes referred to as scan lines, emission enable lines, gate lines, etc.) may be used in providing each pixel  18  with control signals. The control signals may be used to control the loading of data into pixels  18 . A common set of gate lines G may span each row of pixels  18  and a common data line D may span each column of pixels  18  and/or other arrangements may be used for routing the data and gate lines in display  14 . In some configurations, data lines (and/or gates lines) may run horizontally and/or data lines (and/or gate lines) may include both horizontal and/or vertical sections. In the configuration of  FIG. 2 , data lines D run vertically and at least parts of gate lines G run horizontally. Other arrangements may be used for the gate and data lines in display  14 , if desired. The configuration of  FIG. 2  is merely illustrative. 
     As shown in  FIG. 3 , display  14  may include an active area such as active area AA and an inactive area such as inactive area IA. Active area AA has pixels  18  and is configured to display images for a user. Inactive area IA contains display driver circuitry and does not contain pixels. 
     One or more display driver integrated circuits such as display driver integrated circuit  24  may receive image data from control circuitry such as a microprocessor or other content source in device  10 . To display images associated with this image data, display driver circuitry such as display driver integrated circuit  24  may supply data and control signals to pixels  18  (e.g., using signal lines such as data lines D and gate lines G of  FIG. 2 ). The contacts (pads) of integrated circuit  24  may be bonded to signal traces on a substrate associated with display  14  in regions such as illustrative bond pad region  26  (e.g., using solder bonds). Gap  34  in region  26  may be used for registration marks (fiducials), panel identification information, and other information. 
     Signal routing lines  28  may be used to route (“fan out”) the signals from the bond pads in regions  26  to demultiplexer circuitry  30 . Demultiplexer circuitry  30  may perform signal demultiplexing operations (e.g., data demultiplexing). For example, demultiplexer circuitry  30  may contain a strip of 1:N demultiplexers that extends across the width of display  14 . The value of N may be at least 2, at least 3, 2-5, 2-4, 2-10, less than 5, or other suitable value. In one illustrative configuration, the value of N is 3. Using demultiplexer circuitry  30 , M signals on M routing lines  28 ) may be demultiplexed to produced N*M signals on N*M corresponding signal routing lines  32 . Signal routing lines  32  may be used to route (fan out) the demultiplexer output signals that demultiplexer circuitry  30  provides at its output to pixels  18  in active area AA. 
     In general, display  14  may have any suitable number of pixels, gate lines G, and data lines D, etc. With one illustrative configuration, integrated circuit  24  has about 900 bonding pads for providing about 900 corresponding data signals (e.g., data signals that have not yet been demultiplexed and that are therefore sometimes referred to as multiplexed data signals), demultiplexer circuitry  30  has about 900 corresponding inputs associated with 900 respective 1:3 demultiplexers (sometimes referred to as demultiplexer blocks or demultiplexer circuit blocks). Demultiplexer circuitry  30  demultiplexes the 900 multiplexed data signals and supplies about 2700 corresponding data line signals (sometimes referred to as demultiplexed signals or demultiplexed data line signals) on 2700 corresponding outputs. Data routing lines  32  include about 2700 lines to route the demultiplexed data signals from the outputs of demultiplexer circuitry  30  (e.g., the outputs of the 900 demultiplexer circuits in circuitry  30 ) to about 2700 corresponding vertical data lines D in display  14  (e.g., a data line D corresponding to each column of pixels  18 , etc.). Other amounts of demultiplexing and different fan-out arrangements may be used, if desired. 
     To avoid creating signal routing line bottlenecks (signal line crowding) in routing lines  32  in regions  32 BT on the left and right sides of inactive area IA of display  14 , demultiplexer circuit blocks  30 A in demultiplexer circuitry  30  may be arranged in a staircase pattern. Demultiplexer circuit blocks  30 B in demultiplexer circuitry  30  may extend horizontally in a straight line running parallel to the straight lower edge of active area AA and parallel to the X dimension of  FIG. 3 , whereas demultiplexer circuit blocks  20 A in demultiplexer circuitry  20  may extend in a line that runs diagonally along longitudinal axes X′. Dimensions X and X′ may be oriented at a non-zero angle with respect to each other. 
     As shown in  FIG. 4 , for example, demultiplexer circuit blocks  30 A may each be offset vertically by a vertical distance H 2  (e.g., 0.1 microns to 10 microns, at least 0.05 microns, at least 0.2 microns, at least 0.5 microns, at least 2 microns, at least 5 microns, less than 20 microns, or other suitable amount). With this arrangement, demultiplexer circuit blocks  30 A extend in a line along a dimension (axis) X′ that is oriented at a non-zero angle B with respect to horizontal dimension (axis) X (e.g., the dimension along which demultiplexer circuit blocks  30 B extend in a line). The angle made between the dimension along which blocks  30 A extend and the dimension along which blocks  30 B extend may be 0.1-10°, 0.5-10°, at least 0.5°, at least 1°, at least 2°, at least 3°, less than 9°, less than 7°, etc. Each circuit block  30 A may have transistors that are configured to form switches that selectively route the input of that block  30 A (IN) to one of three outputs (OUT 1 , OUT 2 , or OUT 3 ) in response to control signals from display driver circuitry integrated circuit  24 . In this way, signal bits B 1 , B 2 , B 3  B 4 , . . . on input line IN can be routed in sequence so that B 1  is presented on OUT 1 , B 2  is presented on OUT 2 , B 3  is presented on OUT 3 , B 4  is presented on OUT 1 , etc. Because signals are multiplexed between display driver integrated circuit  24  and demultiplexer circuitry  30 , a reduced number of signal lines are needed in signal routing lines  28 . 
     As shown in  FIG. 5 , because the set of demultiplexer circuit blocks (1:N demultiplexers)  30 A extends along an axis X′ that is oriented at a non-zero angle B with respect to the horizontal axis (X axis) that runs parallel to lower edge  18 E of active area AA along which the set of demultiplexer circuit blocks  30 B extends, there is more room for the signal routing lines (see, e.g., lines  32 L) in regions  32 BT than would be possible if X′ were oriented horizontally. This allows height H 1  of the region occupied by signal routing lines  28  to be reduced and allows the height H 3  of inactive area IA (i.e., the lower inactive border of display  14 ) to be reduced. The angle A between axis X′ and routing lines such as line  28 L at the left and right edges of signal routing lines  28  also is increased (becomes less shallow) as a result of the presence of the tilt (staircase) configuration of demultiplexer circuit blocks  30 A. This allows the width W of display driver integrated circuitry  24  (e.g., the display driver integrated circuit and bond pad region(s)  26  of  FIG. 3 ) to be reduced (e.g., with a corresponding increase in its height perpendicular to its width) without exceeding design rule constraints on signal routing  28 . The use of the tilted line of demultiplexer circuit blocks  30 A also reduces the signal routing bottleneck that would otherwise be present at region  32 BT and allows height H 1  of routing lines  32  to be reduced. Demultiplexer circuit blocks  30 A and  30 B may, if desired, each be formed using a common (shared) layout so that the size of blocks  30 B (e.g., the area consumed on the substrate of display  14 ) is the same as the size of blocks  30 A. 
     The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Metadata:
Filing Date: 20180521
Publication Date: 20201006
Grant Date: 20201006
Priority Date: 20170830
Inventors: YU, CHENG-HO
JAMSHIDI ROUDBARI, ABBAS
YEH, SHIN-HUNG
LEE, SUNGKI
CHANG, TING-KUO
CHEN, YU CHENG
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G3/2092", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3225", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/0297", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0297", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L51/5237", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/0297", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/2092", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/3276", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L27/323", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3225", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/40", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K50/84", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/2092", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10K59/40", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10K59/87", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 65437996