PATENT DOCUMENT

Publication Number: US-11404337-B2
Application Number: US-201916729094-A
Country: US
Kind Code: B2

Title: Scalable extreme large size substrate integration

Abstract:
Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

Claims:
What is claimed is: 
     
       1. An electronic package comprising:
 a package substrate; 
 an organic interposer is bonded to the package substrate within an opening in a solder mask layer formed on top of a build-up structure of the package substrate, wherein a bottom side of the organic interposer is bonded to the package substrate with a conductive film to electrically connect a plurality of contact pads of the organic interposer to a corresponding plurality of landing pads of the package substrate; and 
 one or more dies bonded to a top side of the organic interposer; 
 wherein the conductive film comprises an array of pins or is an anisotropic conductive film. 
 
     
     
       2. The electronic package of  claim 1 , wherein the organic interposer comprises a plurality of metal redistribution lines and a plurality of polymer dielectric layers. 
     
     
       3. The electronic package of  claim 1 , wherein the conductive film comprises the array of pins. 
     
     
       4. The electronic package of  claim 3 , wherein the pins in the array of pins are separated by a pin pitch of less than 100 microns, wherein the pin pitch is less than a minimum contact pad pitch of the plurality of contact pads of the interposer. 
     
     
       5. The electronic package of  claim 1 , wherein the conductive film is the anisotropic conductive film. 
     
     
       6. The electronic package of  claim 1 , wherein the package substrate is laterally surrounded by a molding compound layer. 
     
     
       7. The electronic package of  claim 1 , further comprising a plurality of solder bumps on a bottom side of the package substrate, wherein the package substrate comprises a cored substrate. 
     
     
       8. An electronic package comprising:
 a package substrate; 
 a thin film organic interposer bonded to the package substrate with a conductive film spanning between the laterally opposite edges of the thin film organic interposer to electrically connect the plurality of bottom side contact pads of the thin film organic interposer to a corresponding plurality of landing pads of the package substrate; 
 wherein the package substrate is wider than the conductive film and the thin film organic interposer; and 
 one or more dies bonded to the plurality of top side landing pads on a top side of the thin film organic interposer; 
 wherein the conductive film comprises an array of pins or is an anisotropic conductive film. 
 
     
     
       9. The electronic package of  claim 8 , wherein the thin film organic interposer is comprised primary of a plurality of metal redistribution lines, a plurality of dielectric layers, vias, a plurality of top side landing pads, and a plurality of bottom side contact pads. 
     
     
       10. The electronic package of  claim 9 , wherein the plurality of dielectric layers comprises a plurality of polymer dielectric layers. 
     
     
       11. The electronic package of  claim 10 , wherein the plurality of dielectric layers comprises a lower rigid layer. 
     
     
       12. The electronic package of  claim 8 , wherein the thin film organic interposer comprise a plurality of metal redistribution lines and plurality of laminate polymer dielectric layers. 
     
     
       13. The electronic package of  claim 8 , wherein the conductive film comprises the array of pins. 
     
     
       14. The electronic package of  claim 13 , wherein the pins in the array of pins are separated by a pin pitch of less than 100 microns, wherein the pin pitch is less than a minimum contact pad pitch of the plurality of contact pads of the interposer. 
     
     
       15. The electronic package of  claim 8 , wherein the conductive film is the anisotropic conductive film. 
     
     
       16. The electronic package of  claim 8 , wherein the package substrate is laterally surrounded by a molding compound layer. 
     
     
       17. The electronic package of  claim 8 , further comprising a plurality of solder bumps on a bottom side of the package substrate, wherein the package substrate comprises a cored substrate.

Description:
BACKGROUND 
     Field 
     Embodiments described herein relate to electronic packaging, and more particularly to solderless interposer connections. 
     Background Information 
     Substrate yield, layer count and performance are some of the concerns associated with high performance computing applications. Various 2.XD like packaging solutions have been developed to address these concerns in which an interposer is located between a package substrate and one or more dies mounted on the interposer. The interposer may include finer line widths than is possible with traditional package substrate formation, such as cored substrate. Interposers can be constructed of different materials depending upon application, including silicon, glass, and organic. 
     SUMMARY 
     Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. In an embodiment, a method of forming an electronic package includes placing a plurality of package substrates on a carrier substrate, optionally encapsulating the plurality of package substrates in a molding compound layer, solderlessly connecting a plurality of organic interposers to the plurality of package substrates, and mounting one or more dies on each interposer. 
     In an embodiment, the interposer is stacked on the package substrate and joined with a conductive film. For example, an electronic package may include a package substrate, a bottom side of an interposer bonded to the package substrate with a conductive film to electrically connect a plurality of contact pads of the interposer to a corresponding plurality of landing pads of the package substrate, and one or more dies bonded to a top side of the interposer. In an embodiment the interposer is stacked on the package substrate during a reconstitution sequence. 
     In an embodiment the interposer is formed on the package substrate during a reconstitution sequence. In an embodiment, and electronic package includes a package substrate and an interposer on the package substrate. A dielectric film can be between the package substrate and the interposer, with a plurality of conductive columns extending through the dielectric film to directly connect a plurality of contact pads of the interposer to a corresponding plurality of landing pads of the package substrate. One or more dies may be bonded to a top side of the interposer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic cross-sectional side view illustration of an electronic package including an interposer connected to a package substrate with a conductive film in accordance with an embodiment. 
         FIG. 1B  is a close-up schematic cross-sectional side view illustration of an embedded pin array conductive film in accordance with an embodiment. 
         FIG. 1C  is a close-up schematic cross-sectional side view illustration of an anisotropic conductive film in accordance with an embodiment. 
         FIG. 2  is a schematic cross-sectional side view illustration of an electronic package including an interposer formed on a package substrate in accordance with an embodiment. 
         FIG. 3  is a flow chart illustrating a processing sequence for forming an electronic package with solderless connection of an interposer to a package substrate in accordance with an embodiment. 
         FIGS. 4A-4D  are schematic cross-sectional side view illustrations of a sequence of forming an electronic package including an interposer connected to a package substrate with a conductive film in accordance with an embodiment. 
         FIGS. 5A-5B  are schematic cross-sectional side view illustrations of a sequence of connecting an interposer to a package substrate with a plurality of conductive pillars formed during a substrate reconstitution process in accordance with an embodiment. 
         FIGS. 6A-6B  are schematic cross-sectional side view illustrations of a sequence of forming an interposer on a plurality of conductive pillars of a package substrate in accordance with an embodiment. 
         FIG. 7  is a schematic cross-sectional side view illustration of an interposer formed directly on a package substrate in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments describe electronic packages and methods of fabrication which include solderless connection of an interposer to a package substrate. In accordance with some embodiments the interposer is an organic interposer. For example, the organic interposer may include a plurality of metal interconnect lines and a plurality of polymer dielectric layers. Organic interposers may provide a more cost-sensitive integration option compared to more conventional silicon or glass interposers. In accordance with embodiments, the organic interposers are connected to the package substrate using a solderless connection. For example, this may be with a conductive film, such as an anisotropic conductive film (ACF) or an embedded pin array film. Solderless connection can also be achieved by formation of the organic interposers in a layer-by-layer process directly on the package substrates during a substrate reconstitution process. Solderless connection may avoid issues associated with solder, including joint yield and reliability, size scalability, pitch scalability, and power integrity performance. 
     In an embodiment, an electronic package includes a package substrate, a bottom side of an (e.g. organic) interposer bonded to the package substrate with a conductive film to electrically connect a plurality of contact pads of the interposer to a corresponding plurality of landing pads of the package substrate, and one or more dies bonded to a top side of the interposer. 
     In an embodiment, an electronic package includes a package substrate, an interposer on the package substrate, and one or more dies bonded to a top side of the interposer. A dielectric film may be located between the package substrate and the interposer with plurality of conductive columns extending through the dielectric film to directly connect a plurality of contact pads of the interposer to a corresponding plurality of landing pads of the package substrate. In an embodiment, a plurality of contact pads of the interposer is formed directly on a plurality of landing pads of the package substrate. 
     In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. 
     The terms “over”, “to”, “between”, and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers. 
     Referring now to  FIG. 1A  a schematic cross-sectional side view illustration is provided of an electronic package  100  including an interposer  102  connected to a package substrate  202  with a conductive film  120  in accordance with an embodiment. As illustrated, the electronic package  100  includes a package substrate  202 , and a bottom side  112  of an interposer  102  bonded to the package substrate  202  with a conductive film  120  to electrically connect a plurality of contact pads  110  of the interposer  102  to a corresponding plurality of landing pads  212  of the package substrate  202 . One or more dies  130  are bonded to a top side  114  of the interposer  102 . For example, the dies  130  may be bonded to a plurality of landing pads  116  of the interposer  102  with a plurality of solder bumps  132 . 
     The interposer  102  in accordance with embodiments may be an organic interposer. For example, such an organic interposer  102  can include a plurality of metal redistribution lines  104  and a plurality of polymer dielectric layers  106 . The metal redistribution lines  104  can be connected by vias  105 . The interposer  102  may be formed using a layer-by-layer thin film processing sequence, such as lamination of the polymer dielectric layers  106 , followed by patterning and deposition of the metal redistribution lines  104  and vias  105 . The interposer  102  may optionally include a rigid layer  108  to provide structural integrity to the interposer  102 . Vias  105  may also be formed through the rigid layer  108 . In an embodiment, rigid layer  108  is thicker than the individual organic dielectric layers  106 . Rigid layer  108  may be formed of the same or different material than the dielectric layers  106 . 
     The package substrate  202  may be a variety of substrates including traditional substrates such as ABF (Ajinomoto Build-up Film), metal or metal core substrates, silicon core substrates, ceramics, polymers, FR-2 (a phenolic paper impregnated with resin), FR-4 (a woven fiberglass impregnate with resin), etc. The package substrate  202  may be rigid or flexible. The particular embodiment illustrated in  FIG. 1A  includes a cored package substrate  202 , though this is exemplary, and embodiments are not so limited. As shown, the package substrate  202  may optionally include a core  232  including vias  234  connected a top build-up structure  210  and a bottom build-up structure  220 . Core  232  may be formed of a variety of insulating or electrically conductive materials to provide rigidity. When the core is formed of an electrically conductive material vias  234  may be insulated from the core  232  with an insulation layer  236 . 
     The build-up structures  210 ,  220  may both include metal redistribution lines  214 ,  224 , vias  215 ,  225  and dielectric layers  216 ,  226 . A top surface  203  of the package substrate  202  may be the top surface of the top build-up structure  210  any may include landing pads  212 . Contact pads  218  may be on a bottom side of the bottom build-up structure  220 . As shown, a solder mask layer  242  may be formed on top of the top build-up structure  210  and patterned to form an opening to receive the interposer  102 . A solder mask layer  244  can be formed on the bottom surface of the bottom build-up structure  220  and patterned to expose contact pads  218 , which may include solder bumps  250  applied thereto for bonding to a circuit board, etc. 
     The package substrate  202  in accordance with embodiments may optionally be embedded in a molding compound layer  240 , which laterally surrounds side edges  201  of the package substrate  202 . Encapsulation with the molding compound layer  240  may be attributed to reconstitution during the assembly process in which a plurality of package substrates  202  are molded to form a reconstituted substrate prior to addition of the interposers and dies. 
     The conductive film  120  in accordance with embodiments may be formed using various solutions. In an embodiment, the conductive film  120  is an embedded pin array. As illustrated in the close-up schematic cross-sectional side view illustration of  FIG. 1B , an embedded pin array conductive film may include an array of pins  122  (e.g. copper pins) embedded in a matrix  124  (e.g. adhesive insulator). The pins  122  in the array of pins may be separated by a pin pitch (e.g. less than 100 microns) that is less than a minimum contact pad pitch between the plurality of contact pads  110  of the interposer. In an embodiment, a matching ratio includes 2-4 pins per contact pad  110 . Similar ratios can be maintained with landing pads  212 . In an embodiment, the conductive film  120  is an anisotropic conductive film (ACF). As illustrated in the close-up schematic cross-sectional side view illustration of  FIG. 1C , and ACF may include conductive particles  126  embedded in a matrix  124  to create electrical connection between the determined locations (e.g. the contact pads  110  of the interposer  102  and landing pads  212  of the package substrate  202 . 
     Referring now to  FIG. 2 , rather than placing the interposer  102  onto the package substrate  202  and joining with an intermediate conductive film  120 , the interposer  102  can be formed on the package substrate  202  for example, during a reconstitution process in a layer-by-layer fashion. In the particular embodiment illustrated in  FIG. 2 , an electronic package  100  includes a package substrate  202 , an (e.g. organic) interposer  102  on the package substrate  202 , and a dielectric film  302  between the package substrate  202  and the interposer  102  with a plurality of conductive columns  304  extending through the dielectric film  302  to directly connect a plurality of contact pads  110  of the interposer  102  to a corresponding plurality of landing pads  212  of the package substrate  202 . One or more dies  130  are then bonded to a top side of the interposer  102 . As previously described the interposer  102  can be an organic interposer including a plurality of metal redistribution lines  214  and a plurality of polymer dielectric layers  216 . Depending upon fabrication technique the dielectric film  302  may have the same width or be wider than the package substrate  202 . For example, the dielectric film  302  may have the same width as the package substrate  202  when the dielectric film  302  and conductive columns  304  are formed as part of the package substrate prior to reconstitution ( FIGS. 6A-6B ), while the dielectric film  302  may be wider than the package substrate when the dielectric film  302  and conductive columns  304  are formed during a reconstitution process ( FIGS. 5A-5B ). In accordance with embodiments, the package substrate  202  may be laterally surrounded by a molding compound layer  240 . 
       FIG. 3  is a flow chart illustrating a processing sequence for forming an electronic package  100  with solderless connection of an interposer  102  to a package substrate  202  in accordance with an embodiment. At operation  3010  a plurality of package substrates  202  are placed on a carrier substrate. The package substrates can then optionally be encapsulated in a molding compound layer  240  at operation  3020 . This encapsulation may be part of a wafer reconstitution process. However, the encapsulation with a molding compound layer  240  is optional. For example, embodiments similar to  FIG. 1  can be fabricated with or without the molding compound layer  240 . Encapsulation with the molding compound layer  240  may be needed for embodiments similar to  FIG. 2  where the deposition and patterning operations are performed to fabricate the interposers  102  over the package substrates  202 . At operation  3030  a plurality of interposers  102  are connected to the plurality of package substrates  202  with solderless connections, for example, with conductive films  120  similar to  FIG. 1 , or a deposition (e.g. including thin film deposition or lamination techniques) and patterning sequence similar to  FIG. 2 . One or more dies  130  are then mounted on the interposers  102  at operation  3040 . 
     In one aspect, the processing sequences in accordance with embodiments are die-last sequences. This allows for the integration of known good dies onto known good substrates (e.g. including the interposers and package substrates). Such a die-last approach allows completion and testing of the lower cost integrated interposers and package substrates, prior to mounting the more expensive dies. Furthermore, integration organic interposers can further reduce cost relative to silicon or glass interposers. 
       FIGS. 4A-4D  are schematic cross-sectional side view illustrations of a sequence of forming an electronic package  100  similar to  FIG. 1A  including an interposer  102  connected to a package substrate  202  with a conductive film  120  in accordance with an embodiment. As shown in FIG.  4 A, at operation  3010  a plurality of package substrates  202  are placed on a carrier substrate  400 . Carrier substrate may be a variety of substrates to provide rigid support during subsequent fabrication including metal, glass, silicon, etc. and provide compatibility with subsequent process equipment utilized. The package substrates  202  can then optionally be encapsulated in a molding compound layer  240  at operation  3020  as shown in  FIG. 4B , followed by solderless connection of a plurality of interposers  102  are connected to the plurality of package substrates  202  at operation  3030 . In the particular embodiment illustrated solderless connection is made with a plurality of individual conductive films  120  which can be mounted on the package substrates  202  along with the interposers  102  using pick and place tools and joined with application of heat and pressure. A plurality of dies  130  can then be mounted onto the interposers  102  at operation  3040 , for example using pick and place tools and bonding with solder joints. Individual electronic packages  100  can then be singulated and separated from the carrier substrate  400  as shown in  FIG. 4D , followed by placement of solder bumps  250  resulting in electronic packages similar to that of the embodiment illustrate in  FIG. 1A . 
     Referring now to  FIGS. 5A-5B , schematic cross-sectional side view illustrations are provided of a sequence of connecting an interposer  102  to a package substrate  202  with a plurality of conductive pillars  304  formed during a substrate reconstitution process in accordance with an embodiment. In particular  FIG. 5A  illustrates a close-up of operations  3010 - 3020  in which the plurality of package substrates  202  are placed onto the carrier substrate  400  and then encapsulated within a molding compound layer  240 . In this particular processing sequence variation, a plurality of conductive columns  304  are formed on the package substrates  202 , which are now part of a reconstituted substrate structure. Dielectric film  302  may be formed laterally around the conductive columns  304 , or alternatively the conductive columns  304  are formed within openings in the dielectric film  302 . For example, conductive columns  304  (e.g. including copper) may be formed on landing pads  212  using a plating technique. As shown in  FIG. 5B , the interposers  102  are then formed over the package substrates  202  at operation  3030 , followed by singulation  3040  as previously described to result in an electronic package similar to that illustrated in  FIG. 2 . In the resultant structure a plurality of conductive columns  304  may extend through the dielectric film  302  to directly connect a plurality of contact pads  110  of the interposer  102  to a corresponding plurality of landing pads  212  of the package substrate  202 . Referring to  FIG. 5B , structural distinctions may exist compared to the embodiment illustrated in  FIG. 2 . For example, the dielectric film  302  is wider than the package substrate  202 . As shown, a lateral edge  301  of the dielectric film may extend to the package edge, while the lateral edge  201  of the package substrate  202  is laterally surrounded by the molding compound layer  240 . As shown, dielectric layers from the interposer  102  can also extend to the package edge. 
       FIGS. 6A-6B  are schematic cross-sectional side view illustrations of a sequence of forming an interposer  102  on a plurality of conductive pillars  304  of a package substrate  202  in accordance with an embodiment.  FIGS. 6A-6B  are similar to those of  FIGS. 5A-5B , with one difference being that the conductive pillars  304  are pre-formed as part of the fabrication sequence of the package substrate  202 . Thus, at operation  3010  placement of the package substrates  202  onto the carrier substrate  400  includes the conductive pillars  304 . The dielectric layer  302  may optionally be included at this stage, or included prior to the formation of the interposers  102  at operation  3030 . In an embodiment, the resultant electronic package formed using the sequence of  FIGS. 6A-6B  may be similar to that of  FIG. 2 . As such, the lateral edges  301  of the dielectric layer  302  and lateral edges  201  of the package substrates  202  may be the same. 
     Referring now to  FIG. 7 , a schematic cross-sectional side view illustration is provided of another process variation in which an interposer  102  is formed directly on a package substrate  202  in accordance with an embodiment. In such an embodiment, the interposer  102  is formed after encapsulation with the molding compound layer  240 . For example, this may include a film assisted molding technique in which a protective film is formed over the package substrates  202  during molding, then removed to expose the landing pads  212 . Contact pads  110  of the interposer  102  can then be formed directly on the landing pads  212  of the package substrates  202  during fabrication of the interposers  102 . 
     In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming an electronic package with solderless organic interposer to package substrate connection. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.

Metadata:
Filing Date: 20191227
Publication Date: 20220802
Grant Date: 20220802
Priority Date: 20191227
Inventors: HU, KUNZHONG
ZHONG, CHONGHUA
LU, Jiongxin
ZHAI, JUN
Assignee: APPLE INC
CPC Classifications: [{"code": "H01L2224/16225", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L2221/68345", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L23/28", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L25/0655", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L2221/68359", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L23/145", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L23/3128", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L2021/60022", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L23/5383", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L23/145", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L23/5385", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/6835", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L23/49816", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L23/488", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L24/14", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/565", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L25/0655", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L24/94", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L25/0655", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2021/60022", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L23/28", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L23/488", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L23/145", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L24/14", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L24/94", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L21/565", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 76547750