PATENT DOCUMENT

Publication Number: US-8838825-B2
Application Number: US-201113170101-A
Country: US
Kind Code: B2

Title: Synchronized transmission of audio and video data from a computer to a client via an interface

Abstract:
A method for controlling data transmission between a computer and a video client via an interface, the method comprising: the computer polling the interface a first time to determine the size of the buffer on the interface; receiving a first buffer size value from the interface; sending a plurality of frames of video and audio data to the buffer on the interface such that a delay period exists between the sending of each frame; the computer polling the interface a second time to determine buffer size after the frames are sent to the interface; receiving a second buffer size value from the interface; and modifying the amount of time between the transmission of frames.

Claims:
What is claimed is: 
     
       1. In an interface of a computerized device between a computer and a video client, a method of performing data transmission flow control, the method comprising:
 receiving a stream of input data from the video client according to a first format; 
 converting the received input data to scanned lines of video data; 
 generating frames and vertical blanking intervals based on the scanned lines; and 
 for each generated vertical blanking interval, transmitting one of the frames from the interface of the computerized device to the computer, wherein the computer synchronizes with the video data by determining a vertical blanking frequency from a frequency of frames received from the interface, 
 wherein the computerized device and the computer share an external clock for synchronizing data transmission. 
 
     
     
       2. The method of  claim 1 , wherein the frame additionally comprises audio data. 
     
     
       3. The method of  claim 1 , wherein the frame of data is National Television System Committee (NTSC) compliant. 
     
     
       4. The method of  claim 1 , wherein the size of at least one frame of said plurality of frames varies to accommodate various data sizes. 
     
     
       5. The method of  claim 1 , wherein the frames of data are of a predetermined size. 
     
     
       6. The method of  claim 1 , wherein the first format comprises one or more analog signals. 
     
     
       7. The method of  claim 6 , wherein the first format comprises one or more digital signals. 
     
     
       8. The method of  claim 7 , wherein the digital signals are compressed. 
     
     
       9. A computer readable apparatus having a non-transitory computer readable storage medium containing instructions which, when executed by a computerized device:
 responsive to receiving a stream of input data according to a first format, converting the received input data to scanned lines of video data; 
 generating frames and vertical blanking intervals based on the scanned lines; and 
 for each generated vertical blanking interval, transmitting one of the frames from an interface of the computerized device to a first device, wherein the first device synchronizes with the video data by determining a vertical blanking frequency from a frequency of frames received from the interface, 
 wherein the computerized device and the first device share an external clock for synchronizing data transmission. 
 
     
     
       10. The computer readable apparatus of  claim 9 , wherein the generated frames are associated with one or more audio data. 
     
     
       11. The computer readable apparatus of  claim 9 , wherein the first format is compressed. 
     
     
       12. A computer readable apparatus having a non-transitory computer readable storage medium containing instructions which, when executed by a computerized device:
 responsive to receiving data frames from a peer device, according to a first format comprising one or more video data and one or more vertical blanking intervals, determine a frequency of receipt of vertical blanking intervals based on a frequency of the received data frames; 
 for each vertical blanking interval, display a corresponding video data; and 
 synchronize to the peer device, based at least in part on the determined frequency of vertical blanking intervals, 
 wherein the computerized device and the peer device share an external clock for synchronizing data transmission. 
 
     
     
       13. The apparatus of  claim 12 , wherein the first format comprises one or more video data and one or more audio data. 
     
     
       14. The apparatus of  claim 12 , wherein the data frames accommodate various video formats. 
     
     
       15. The apparatus of  claim 12 , wherein the data frames have a fixed size. 
     
     
       16. The apparatus of  claim 12 , wherein the first format comprises a plurality of scan lines. 
     
     
       17. The apparatus of  claim 12 , wherein the first format comprises a compressed digital signal.

Description:
PRIORITY APPLICATIONS 
     This application is a continuation of and claims priority to U.S. patent application Ser. No. 12/079,832 filed Mar. 28, 2008 and issued as U.S. Pat. No. 7,970,926 on Jun. 28, 2011, entitled “SYNCHRONIZED TRANSMISSION OF AUDIO AND VIDEO DATA FROM A COMPUTER TO A CLIENT VIA AN INTERFACE”, which claims priority to U.S. patent application Ser. No. 10/746,283 filed Dec. 23, 2003 and issued as U.S. Pat. No. 7,353,284 on Apr. 1, 2008 entitled “SYNCHRONIZED TRANSMISSION OF AUDIO AND VIDEO DATA FROM A COMPUTER TO A CLIENT VIA AN INTERFACE”, which claims priority to U.S. Provisional Patent Application Ser. No. 60/478,336 of the same title filed Jun. 13, 2003, each of the foregoing incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates broadly to devices in communication over a network. Specifically, the present invention relates to data flow management between devices transmitting and receiving data at different transmission rates. More specifically, the present invention relates to controlling data flow through a buffer by monitoring the buffer and adjusting data transmission based on buffer conditions. 
     BACKGROUND OF THE INVENTION 
     A “bus” is a collection of signals interconnecting two or more electrical devices that permits one device to transmit information to one or more other devices. There are many different types of busses used in computers and computer-related products. Examples include the Peripheral Component Interconnect (“PCI”) bus, the Industry Standard Architecture (“ISA”) bus and Universal Serial Bus (“USB”), to name a few. The operation of a bus is usually defined by a standard which specifies various concerns such as the electrical characteristics of the bus, how data is to be transmitted over the bus, how requests for data are acknowledged, and the like. Using a bus to perform an activity, such as transmitting data, requesting data, etc., is generally called running a “cycle.” Standardizing a bus protocol helps to ensure effective communication between devices connected to the bus, even if such devices are made by different manufacturers. Any company wishing to make and sell a device to be used on a particular bus, provides that device with an interface unique to the bus to which the device will connect. Designing a device to particular bus standard ensures that device will be able to communicate properly with all other devices connected to the same bus, even if such other devices are made by different manufacturers. Thus, for example, an internal fax/modem (ie., internal to a personal computer) designed for operation on a PCI bus will be able to transmit and receive data to and from other devices on the PCI bus, even if each device on the PCI bus is made by a different manufacturer. 
     Currently, there is a market push to incorporate various types of consumer electronic equipment with a bus interface that permits such equipment to be connected to other equipment with a corresponding bus interface. For example, digital cameras, digital video recorders, digital video disks (“DVDs”), printers are becoming available with an IEEE 1394 bus interface. The IEEE (“Institute of Electrical and Electronics Engineers”) 1394 bus, for example, permits a digital camera to be connected to a printer or computer so that an image acquired by the camera can be printed on the printer or stored electronically in the computer. Further, digital televisions can be coupled to a computer or computer network via an IEEE 1394 bus. 
     However, many devices exist without any sort of IEEE 1394 interface. This presents a problem as such devices are unable to be to be connected with other devices as described above. There is a heartfelt need to overcome this problem to provide connectivity to devices that otherwise cannot be connected to a IEEE 1394 bus. 
     SUMMARY OF THE INVENTION 
     The present invention controls the transmission of data from a computer to a video client via an interface device that buffers the data frames sent and communicates to the computer and the video client using different protocols. In an embodiment, the present invention provides a method of performing data transmission flow control by polling the interface a first time to determine the size of the buffer on the interface; receiving a first buffer size value from the interface; sending a plurality of frames of video and audio data to the buffer on the interface such that a delay period exists between the sending of each frame; polling the interface a second time to determine buffer size after the frames are sent to the interface; and receiving a second buffer size value from the interface. If the second buffer size value is larger than the optimal size, and larger than the first buffer size value, then the delay period between transmission of frames from the computer to the interface is increased. 
     In another embodiment, the present invention provides a method of performing data transmission flow control, by polling the interface a first time to determine the size of the buffer on the interface; receiving a first buffer size value from the interface; sending a plurality of frames of video and audio data to the buffer on the interface such that a delay period exists between the sending of each frame; polling the interface a second time to determine buffer size after the frames are sent to the interface; and receiving a second buffer size value from the interface. 
     If the second buffer size value is smaller than optimal size, and smaller than the first buffer size value, then the delay period between transmission of frames from the computer to the interface is decreased. 
     Many other features and advantages of the present invention will be realized by reading the following detailed description, when considered in conjunction with the accompanying drawings, in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates in block diagram form major components used in connection with embodiments of the present invention; 
         FIG. 2  illustrates the format of a frame in accordance with embodiments of the present invention; 
         FIGS. 3A and 3B  illustrate the format of the first data packet and following data packet, respectively; 
         FIGS. 4A and 4B  illustrate the organization of video data within data packets in accordance with the embodiments of the present invention; 
         FIGS. 5A and 5B  illustrate the organization of audio data within data packets in accordance with the embodiments of the present invention; 
         FIGS. 6 and 7  illustrate elements of a header included in the frame in accordance with embodiments of the present invention; 
         FIG. 8  illustrates a collection of packets that combine to form a frame in accordance with embodiments of the present invention; 
         FIGS. 9A-9D  illustrates an alternative embodiment of the present invention in which variations of SDTI frames are used in accordance with embodiments of the present invention; 
         FIG. 9E  illustrates an alternative embodiment in which the transmitter divides the SDTI stream across multiple channels; 
         FIG. 10  illustrates in flow chart form acts performed to provide external clocking between a computer and a hardware interface in accordance with embodiments of the present invention; 
         FIG. 11  illustrates the register memory map for the interface device in accordance with embodiments of the present invention; 
         FIG. 12  illustrates organization of A/V global registers contained within the interface of the present invention; 
         FIG. 13  illustrates organization of global status registers contained within the interface device of the present invention; 
         FIG. 14  illustrates the isochronous control register contained in the interface device of the present invention; 
         FIG. 15  illustrates the organization of the flow control register contained in the interface device of the present invention; and 
         FIG. 16  illustrates the organization of the isochronous channel register contained in the interface device of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Directing attention to  FIG. 1 , there is shown in block diagram form components connected to transmit audio and video data between a computer  100  and client  102 , connected by bus  104  to interface  106 . Computer  100  in the preferred embodiment is a computing device capable of processing and video and audio data and displaying it in a recognizable form to a user. Such devices include desktop, laptop, and palmtop computers. Client  102  as referred to herein is a video consumer or video producer, and includes such devices as digital cameras, and video storage devices, such as linear and random access devices. Bus  104 , as referred to herein, includes a physical connection between computer  100  and interface  106 , as well as the serial protocol adhered to by devices communicating over bus  104 . In the preferred embodiment, bus  104  utilizes the IEEE 1394 serial bus protocol known as Firewire. Interface  106  accepts from client  102  both analog and digital inputs, and converts the input to scanned lines that can be used by an audio/video player executed on computer  100 . In an alternative embodiment, interface  106  accepts from client  102  a digital compressed/uncompressed signal and transmits the entire signal or subsets of that signal. In an embodiment, interface  106  divides the input into frames  108  them over bus  104  to computer  100 . 
     The format of frame  108  is illustrated in  FIG. 2 . Frame  108  includes a frame header  110 , video block  112 , audio block  114 , and optionally an audio header  116 . Audio data in audio block  114  is sampled with respect to the video data in video block  112 . The audio sample count per frame varies in accordance with the number defined in the ANSI/SMPTE 272M specification, incorporated herein by reference in its entirety. The audio sample count cadence is necessary to divide the integer number of samples per second across the NTSC frame rate (29.97 fps). Similarly, the size of frame  108  can vary to accommodate various video formats such as PAL or NTSC, and 8 or 10 bit video data, and audio formats such as 48 Khz and 96 Khz 16 and 24 bit etc. Similarly, the frame size of compressed data can vary to accommodate the compressed format. In an embodiment, video block  112  and audio block or compressed block are of a predetermined size, to make parsing frame  108  simple and requiring little processing overhead by applications such as direct memory access programs. In the event that not all of video block  112  or audio block  114  is not completely full of data, the remaining portions of blocks  112 ,  114  can be filled with zeros. In one embodiment, data contained in video block  112  and audio block  114  is not compressed, further reducing processing overhead on interface  106 , as well as processing overhead required by decompression programs running on computer  100 . 
     Interface  106 , upon converting the input received from client  102  and converting it to scan lines and organizing it into frames  108 , sends a frame at each vertical blanking interval to provide synchronization with computer  100 . Computer  100  can derive the vertical blanking interval from the frequency of frames received and synchronize itself with the audio and video data of the incoming frames  108  received from interface  106 . In this manner, processing resources are preserved, as there is no need to perform synchronization on each frame as it is received, thus providing higher quality performance of audio and video display on computer  100 . 
       FIGS. 3A and 3B  illustrate the format of the first data packet and following data packet, respectively. 
       FIGS. 4A and 4B  illustrate the organization of video data within data packets.  FIGS. 5A and 5B  illustrate the organization of audio data within data packets. 
       FIG. 6  illustrates the contents of frame header  110 . Included are format flags  130 , which indicate how many bits per sample, SMPTE time code  132 , incrementing frame counter  134 , audio cycle count  136 , audio sample count  138 , channel count  140 , block size byte count  142 , audio format flags  144 , and video format flags  146 . Audio sample count  138  indicates a number of samples, which is in accordance with a cadence. The value in audio cycle count  136  indicates location within the cadence. A cadence of frames form a cycling pattern. In an alternative embodiment, some of the contents of frame header  110  can be moved or copied to optional audio header  116 . An alternative view of frame header  110  is shown in  FIG. 7 , showing byte count, data length, and a frame bit. 
     As illustrated in  FIG. 8 , frame  108  is constructed from a plurality of packets  150  of a predetermined size. Associated with each packet is an 1394 isochronous packet header. Data transmission in accordance with the present invention takes advantage of a synchronization bit to find the beginning of a frame. The first packet in frame  108  is marked with the synchronization bit. This allows the stream of data to be identified by computer  100  as it is received, further reducing processing overhead by allowing computer  100  to synchronize the flow of frames received from interface  106 . 
     In an alternative embodiment of the present invention, frames adhering to the serial digital interface (SDI) standard can be utilized as illustrated in  FIGS. 9A through 9E . In these embodiments, bus  104  adheres to the IEEE 1394B serial bus protocol to accommodate data rate restrictions set forth by the SDI standard. As described above, interface  106  forms frames from received input by creating scanned lines, performing deinterlacing, packetizing, and creating fixed-size SDTI frames of audio and video data. Various modifications can be made to SDTI frames, depending on the processing resources available on computer  100 , interface  106 , client  102 , or other device. As described above, the transmission of SDTI frames sent over bus  104  are synchronized to the vertical blanking interval of the accepted signal. 
     As shown in  FIG. 9A , SDTI frame  160  generally has two components: vertical blanking portion  162  and horizontal retrace  164 . Alternatively, in another embodiment ( FIG. 9B ), SDI frame header  166 , a header having a synchronization bit and a frame count, is added to SDTI frame  160  for further synchronization and fault detection purposes, such as recovering from data lost in transmission or the occurrence of a bus reset. In this embodiment, a frame count synchronization bit is included in SDTI frame header  166  and SDTI frame header  166  is synchronized with vertical blanking portion  162 . For example, in an application where interface  106  is unable to read compressed data, or excessive upgrades to interface  106  would be required, SDTI frame  160  can be transmitted to computer  100 , where processing on the SDTI stream is performed by software in a non-realtime manner. Alternatively, as shown in  FIG. 9C , SDTI frame  160  can be constructed without horizontal retrace  164  to further reduce processing overhead. An SDTI frame constructed without a horizontal retrace but having header  166 , can also be utilized in an embodiment, as shown in  FIG. 9D . In yet another embodiment, as shown in  FIG. 9E , the SDTI frame can be split between multiple channels and also include SDTI frame header  166 . In this embodiment, the transmitter splits the SDTI stream in half, with half of the lines being transmitted across channel A, the other half being transmitted across channel B. An attached header for each partial frame can be used to assist in re-combining frame data. 
     In another aspect of the present invention, external clocking can be utilized to synchronize data transmission between computer  100 , interface  106  and client  102 . In an embodiment, client  102  includes a high-quality reference clock  180  ( FIG. 1 ) that can be used to synchronize clock  182  on interface  106  and prevent overflow of buffer  184  on interface  106 . In this embodiment, the value of reference clock  180  on client  102  is derived on interface  106  from the frequency at which data is transmitted from computer  102  to interface  106 . To perform flow control, cycles are skipped between transmission of frames. A skipped cycle increases the amount of time between transmissions of frames, to slow the data rate of the frame transmission. Directing attention to  FIG. 10 , at reference numeral  200 , computer polls interface  106  to read the size of buffer  184 . While for exemplary purposes the buffer is referred to in terms such as “bigger” and “smaller,” it is to be understood that in the case of a fixed-size buffer bigger and smaller refer to fullness of the buffer. At reference numeral  202 , computer  100  then sends a plurality of frames to interface  106 . At reference numeral  204 , computer  100  again polls interface  106  to determine the size of buffer  184 . If buffer  184  has grown in size from the last poll of its size (decision reference numeral  206 ), control proceeds to reference numeral  208 , where computer  100  increases the delay between frames it is sending to interface  106 . In an embodiment, the delay between frames sent is 125 milliseconds. In another embodiment a fractional delay is attained by modulating the delay over a number of frames. For instance if a delay between frames of 2.5 times 1.25 microseconds is required, alternating frame delays of 2 and 3 cycles (of 125 microseconds) are interspersed. Control then returns to reference numeral  202 , where the frames are sent to interface  106  with the additional delay between frames. However, returning to decision reference numeral  206 , if buffer  184  has not grown in size since the last polling of its size, control transitions to decision reference numeral  210 . At decision reference numeral  210 , if buffer  206  has decreased in size, control transitions to reference numeral  212 , where the delay between frames sent from computer  100  to interface  106  is decreased. In an embodiment, the amount of this decrease is also 125 Ms. Control then transitions to reference numeral  202 , where the frames are sent from computer  100  to interface  106  with the reduced delay between frames. Returning to decision reference numeral  210 , if the size of buffer  184  has not reduced since the last polling of the size of buffer  184 , then no adjustment to the delay between frames is necessary, and control transitions to reference numeral  202 . 
     Interface  106  includes a serial unit  300  for enabling communication across bus  104 . Serial unit  300  includes a unit directory  302  as shown in Table 1. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Name 
                 Key 
                 Value 
               
               
                   
                   
               
             
            
               
                   
                 Unit_Spec_ID 
                 0x12 
                 0x000a27 
               
               
                   
                 Unit_SW_Version 
                 0x13 
                 0x000022 
               
               
                   
                 Unit_Register_Location 
                 0x54 
                 Csr_offset to registers 
               
               
                   
                 Unit_Signals_Supported 
                 0x55 
                 Supported RS232 signals 
               
               
                   
                   
               
            
           
         
       
     
     The Unit_Spec_ID value specifies the organization responsible for the architectural definition of serial unit  300 . The Unit_SW_Version value, in combination with Unit_Spec_ID value, specifies the software interface of the unit. The Unit_Register_location value specifies the offset in the target device&#39;s initial address space of the serial unit registers. The Unit_Signals_Supported value specifies which RS-232 signals are supported, as shown in the Table 2. If this entry is omitted from the serial unit directory  302 , then none of these signals are supported. 
     
       
         
           
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Field 
                 Bit 
                 Description 
               
               
                   
               
             
            
               
                 Ready to Send (RTS) 
                 0 
                 Set if RTS/RFR is supported 
               
               
                 Clear to Send (CTS) 
                 1 
                 Set if CTS is supported 
               
               
                 Data Set ready (DSR) 
                 2 
                 Set if DSR is supported 
               
               
                 Data Transmit Ready 
                 3 
                 Set if DTR is supported 
               
               
                 (DTR) 
               
               
                 Ring Indicator (RI) 
                 4 
                 Set if RI supported 
               
               
                 Carrier (CAR) 
                 5 
                 Set if CAR/DCD is supported 
               
               
                 Reserved 
                 [31 . . . 6] 
                 Reserved 
               
               
                   
               
            
           
         
       
     
     Also included in serial unit  300  is a serial unit register map  304  that references registers contained in serial unit  300 . The organization of serial unit register map  304  is shown in Table 3. 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 3 
               
               
                   
               
               
                 Hex 
                   
                   
                   
                   
               
               
                 Offset 
                 Name 
                 Access 
                 Size (quads) 
                 Value 
               
               
                   
               
             
            
               
                 0x0 
                 Login 
                 W 
                 2 
                 Address of initiator&#39;s 
               
               
                   
                   
                   
                   
                 serial registers 
               
               
                 0x8 
                 Logout 
                 W 
                 1 
                 Any value 
               
               
                 0xc 
                 Reconnect 
                 W 
                 1 
                 Initiator&#39;s node ID 
               
               
                 0x10 
                 TxFIFO 
                 R 
                 1 
                 Size in bytes of Tx FIFO 
               
               
                   
                 Size 
               
               
                 0x14 
                 RxFIFO 
                 R 
                 1 
                 Size in bytes of Rx FIFO 
               
               
                   
                 Size 
               
               
                 0x18 
                 Status 
                 R 
                 1 
                 CTS/DSR/RI/CAR 
               
               
                 0x1c 
                 Control 
                 W 
                 1 
                 DTR/RTS 
               
               
                 0x20 
                 Flush 
                 W 
                 1 
                 Any value 
               
               
                   
                 TxFIFO 
               
               
                 0x24 
                 Flush 
                 W 
                 1 
                 Any value 
               
               
                   
                 RxFIFO 
               
               
                 0x28 
                 Send Break 
                 W 
                 1 
                 Any value 
               
               
                 0x2c 
                 Set Baud 
                 W 
                 1 
                 Baud rate 300-&gt;230400 
               
               
                   
                 Rate 
               
               
                 0x30 
                 Set Char 
                 W 
                 1 
                 7 or 8 bit characters 
               
               
                   
                 Size 
               
               
                 0x34 
                 Set Stop 
                 W 
                 1 
                 1, 1.5 or 2 bits 
               
               
                   
                 Size 
               
               
                 0x38 
                 Set Parity 
                 W 
                 1 
                 None, odd or even parity 
               
               
                 0x3c 
                 Set Flow 
                 W 
                 1 
                 None, RTS/CTS or 
               
               
                   
                 Control 
                   
                   
                 Xon/Xoff 
               
               
                 0x40 
                 Reserved 
                 — 
                 4 
                 Reserved 
               
               
                 0x50 
                 Send Data 
                 W 
                 TxFIFO size 
                 Bytes to transmit 
               
               
                   
               
            
           
         
       
     
     Serial unit register map  304  references a login register. A device attempting to communicate with serial unit  300 , is referred to herein as an initiator. For example, an initiator can be computer  100 , or other nodes connected on a network via a high-speed serial bus and in communication with interface  106 . The initiator writes the 64 bit address of the base of its serial register map to the login register to log into serial unit  300 . If another initiator is already logged in, serial unit  300  returns a conflict error response message. The high 32 bits of the address are written to the Login address, the lower 32 bits to Login+4. The serial unit register map also references a logout register. The initiator writes any value to this register to log out of the serial unit. After every bus reset the initiator must write its (possibly changed) nodeID to the reconnect register. If the initiator fails to do so within one second after the bus reset it is automatically logged out. The 16-bit nodeID is written to the bottom 16 bits of this register, the top 16 bits should be written as zero. A read of the TxFIFOSize register returns the size in bytes of the serial unit&#39;s transmit FIFO. A read of the RxFIFOSize register returns the size in bytes of serial unit  300 &#39;s receive FIFO. A read of the status register returns the current state of CTS/DSR/RI/CAR (if supported). The status register is organized as shown in Table 4. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 4 
               
               
                   
                   
               
               
                   
                 Field 
                 Bit 
                 Description 
               
               
                   
                   
               
             
            
               
                   
                 CTS 
                 0 
                 1 if CTS is high, else 0 
               
               
                   
                 DSR 
                 1 
                 1 if DSR is high, else 0 
               
               
                   
                 RI 
                 2 
                 1 if RI is high, else 0 
               
               
                   
                 CAR 
                 3 
                 1 if CAR is high, else 0 
               
               
                   
                 Reserved 
                 [31 . . . 4] 
                 Always 0 
               
               
                   
                   
               
            
           
         
       
     
     A write to the control register sets the state of DTR and RTS (if supported). The organization of the control register is shown in Table 5. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 5 
               
               
                   
                   
               
               
                   
                 Field 
                 Bit 
                 Description 
               
               
                   
                   
               
             
            
               
                   
                 RTS 
                 0 
                 If 1 set RTS high, else set RTS 
               
               
                   
                   
                   
                 low 
               
               
                   
                 DTR 
                 1 
                 If 1 set DTR high, else set DTR 
               
               
                   
                   
                   
                 low 
               
               
                   
                 Reserved 
                 [31 . . . 2] 
                 Always 0 
               
               
                   
                   
               
            
           
         
       
     
     A write of any value to the FlushTxFIFO register causes serial unit  300  to flush its transmit FIFO, discarding any bytes currently in it. A write of any value to the FlushRxFIFO register causes the serial unit to flush its receive FIFO, discarding any bytes currently in it. A write of any value to the send break register causes serial unit  300  to set a break condition on its serial port, after transmitting the current contents of the TxFIFO. A write to the set baud rate register sets serial unit  300 &#39;s serial port&#39;s baud rate. The set baud rate register is organized as shown in Table 6. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 6 
               
               
                   
                   
               
               
                   
                 Value written 
                 Baud Rate 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 0 
                 300 
               
               
                   
                 1 
                 600 
               
               
                   
                 2 
                 1200 
               
               
                   
                 3 
                 2400 
               
               
                   
                 4 
                 4800 
               
               
                   
                 5 
                 9600 
               
               
                   
                 6 
                 19200 
               
               
                   
                 7 
                 38400 
               
               
                   
                 8 
                 57600 
               
               
                   
                 9 
                 115200 
               
               
                   
                 10 
                 230400 
               
               
                   
                   
               
            
           
         
       
     
     The set char size register sets the bit size of the characters sent and received. The organization of the set char size register is shown in Table 7. 7 bit characters are padded to 8 bits by adding a pad bit as the most significant bit. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 7 
               
               
                   
                   
               
               
                   
                 Value written 
                 Character bit size 
               
               
                   
                   
               
             
            
               
                   
                 0 
                 7 bits 
               
               
                   
                 1 
                 8 bits 
               
               
                   
                   
               
            
           
         
       
     
     The set stop size register designates the number of stop bits. The set stop size register is organized as shown in Table 8. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 8 
               
               
                   
                   
               
               
                   
                 Value written 
                 Stop bits 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 0 
                 1 
                 bit 
               
               
                   
                 1 
                 1.5 
                 bits 
               
               
                   
                 2 
                 2 
                 bits 
               
               
                   
                   
               
            
           
         
       
     
     The set parity register sets the serial port parity. The organization of the set parity register is shown in Table 9. 
     
       
         
           
               
               
             
               
                 TABLE 9 
               
               
                   
               
               
                 Value written 
                 Parity 
               
               
                   
               
             
            
               
                 0 
                 No Parity bit 
               
               
                 1 
                 Even parity 
               
               
                 2 
                 Odd parity 
               
               
                   
               
            
           
         
       
     
     The set flow control register sets the type of flow control used by the serial port. The organization of the set flow register is shown in Table 10. 
     
       
         
           
               
               
             
               
                 TABLE 10 
               
               
                   
               
               
                 Value written 
                 Flow Control 
               
               
                   
               
             
            
               
                 0 
                 None 
               
               
                 1 
                 CTS/RTS 
               
               
                 2 
                 XOn/Xoff 
               
               
                   
               
            
           
         
       
     
     The send data register is used when the initiator sends block write requests to this register to write characters into the transmit FIFO. Block writes must not be larger than the transmit FIFO size specified by the TxFIFOSize register. If there isn&#39;t enough room in the Tx FIFO for the whole block write, then a conflict error response message is returned and no characters are copied into the FIFO. 
     Also included in serial unit  300  is an initiator register map having a plurality of registers, organized as shown in Table 11. 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 11 
               
               
                   
               
               
                 Hex 
                   
                   
                   
                   
               
               
                 Offset 
                 Name 
                 Access 
                 Size (quads) 
                 Value 
               
               
                   
               
             
            
               
                 0x0 
                 Break 
                 W 
                 1 
                 Any value 
               
               
                 0x4 
                 Framing Error 
                 W 
                 1 
                 Received 
               
               
                   
                   
                   
                   
                 character 
               
               
                 0x8 
                 Parity Error 
                 W 
                 1 
                 Received 
               
               
                   
                   
                   
                   
                 character 
               
               
                 0xc 
                 RxFIFO 
                 W 
                 1 
                 Any value 
               
               
                   
                 overflow 
               
               
                 0x10 
                 Status change 
                 W 
                 1 
                 CTS/DSR/RI/CAR 
               
               
                 0x14 
                 Reserved 
                 — 
                 3 
                 Reserved 
               
               
                 0x20 
                 Received Data 
                 W 
                 RxFIFO size 
                 Bytes received 
               
               
                   
               
            
           
         
       
     
     When serial unit  300  detects a break condition on its serial port, it writes an arbitrary value to this register. When serial unit  300  detects a framing error on its serial port, it writes the received character to the framing register. When serial unit  300  detects a parity error on its serial port, it writes the received character to the parity error register. When serial unit  300 &#39;s receive FIFO overflows, serial unit  300  writes an arbitrary value to the RxFIFO overflow register. When serial unit  300  detects a change in state of any of CTS/DSR/RI/CAR it writes to the status change register indicating the new serial port signal state. The organization of the status register is shown in table 12. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 12 
               
               
                   
                   
               
               
                   
                 Field 
                 Bit 
                 Description 
               
               
                   
                   
               
             
            
               
                   
                 CTS 
                 0 
                 1 if CTS is high, else 0 
               
               
                   
                 DSR 
                 1 
                 1 if DSR is high, else 0 
               
               
                   
                 RI 
                 2 
                 1 if RI is high, else 0 
               
               
                   
                 CAR 
                 3 
                 1 if CAR is high, else 0 
               
               
                   
                 Reserved 
                 [31 . . . 4] 
                 Always 0 
               
               
                   
                   
               
            
           
         
       
     
     When serial unit  300  receives characters from its serial port it writes the received characters to the received data register with a block write transaction. It never writes more bytes than the receive FIFO size specified by the RxFIFOSize register. If the initiator cannot receive all the characters sent it responds with a conflict error response message and receives none of the characters sent. 
       FIG. 11  illustrates the register memory map for the interface device in accordance with embodiments of the present invention.  FIG. 12  illustrates organization of A/V global registers contained within the interface of the present invention.  FIG. 13  illustrates organization of global status registers contained within the interface device of the present invention.  FIG. 14  illustrates the isochronous control register contained in the interface device of the present invention.  FIG. 15  illustrates the organization of the flow control register contained in the interface device of the present invention.  FIG. 16  illustrates the organization of the isochronous channel register contained in the interface device of the present invention. 
     In another embodiment of the present invention, a synthesized vertical blanking signal is derived by polling a vertical blanking register on interface  106 . The vertical blanking signal invokes code to programs running on computer  100 . In, an embodiment, timing information may also be provided to programs running on computer  100 , either in combination with the invoked code or instead of the invoked code. In an embodiment of the invention, interface  106  contains a register that holds a counter indicating current progress in the frame, from which the next vertical retrace can be extrapolated or otherwise derived. By deriving boundaries on frame transmission, other data that is within the frame and synchronized to the occurrence of a vertical blanking interval can be located and accessed, such as for sampling operations. Additionally, an embodiment of the present invention derives frame boundaries for locating data that is coincident with the vertical blanking interval but includes no information about the vertical blanking In an embodiment, the present invention is used to obtain data that is valid for a period after the occurrence of a video blanking interval, such as a time code contained within the frame, can be read, and used in various processing applications. In an embodiment, computer  100  can then schedule an interrupt to fire at this extrapolated time, thus sending out a frame.

Metadata:
Filing Date: 20110627
Publication Date: 20140916
Grant Date: 20140916
Priority Date: 20030613
Inventors: AGNOLI GIOVANNI M.
ABT JOHN O.
BOWMAN SAMUEL R.
DELWICHE JAMES A.
DILLON JEFFREY C.
YANOWITZ ANDREW
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G2370/025", "inventive": false, "first": false, "tree": "[]"}, {"code": "H04L47/30", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N19/152", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F3/14", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N21/43632", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2350/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2370/10", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2350/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2370/10", "inventive": false, "first": false, "tree": "[]"}, {"code": "H04N21/43632", "inventive": true, "first": true, "tree": "[]"}, {"code": "H04N21/64707", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N21/4113", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N21/4113", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2370/025", "inventive": false, "first": false, "tree": "[]"}, {"code": "H04N21/64707", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F3/14", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04L47/30", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N19/152", "inventive": false, "first": false, "tree": "[]"}, {"code": "H04N21/64707", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04L47/30", "inventive": true, "first": false, "tree": "[]"}, {"code": "H04N21/4113", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2370/025", "inventive": false, "first": false, "tree": "[]"}, {"code": "H04N21/43632", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F3/14", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2370/10", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2350/00", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 33514221