PATENT DOCUMENT

Publication Number: US-10297712-B2
Application Number: US-201414312554-A
Country: US
Kind Code: B2

Title: Micro LED display

Abstract:
A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Claims:
What is claimed is: 
     
       1. A display substrate comprising:
 a plurality of separate micro LED devices bonded to a corresponding plurality of separate driver contacts; and 
 a common contact line formed of a transparent material directly over and in electrical contact with a top surface of each of the plurality of separate micro LED devices, wherein each of the plurality of separate micro LED devices comprises:
 a p-n diode including:
 a bottom surface directly beneath the top surface; 
 a p-doped layer; 
 an n-doped layer; and 
 a quantum well layer between the n-doped layer and the p-doped layer; 
 wherein the p-n diode is less than 3 μm thick and less than 10 μm wide; and 
 
 a lower metallization layer including a top surface and a bottom surface, wherein the top surface of the lower metallization layer is underneath the bottom surface of the p-n diode, and the bottom surface of the lower metallization layer is directly over and bonded to a corresponding driver contact; 
 wherein a maximum thickness between the top surface of the p-n diode and the bottom surface of the lower metallization layer is less than 5 μm. 
 
 
     
     
       2. The display substrate of  claim 1 , wherein the common contact line comprises indium tin oxide. 
     
     
       3. The display substrate of  claim 1 , further comprising a plurality of separate bonding layers, wherein each lower metallization layer is bonded to a corresponding driver contact with a corresponding bonding layer. 
     
     
       4. The display substrate of  claim 3 , wherein each bonding layer comprises indium. 
     
     
       5. The display substrate of  claim 1 , wherein each p-n diode has a square configuration with tapered corners. 
     
     
       6. The display substrate of  claim 1 , further comprising a plurality of dielectric barrier layers, wherein each dielectric barrier layer spans sidewalls of a corresponding p-n diode. 
     
     
       7. The display substrate of  claim 6 , wherein each dielectric barrier layer covers the quantum well layer of a corresponding p-n diode. 
     
     
       8. The display substrate of  claim 7 , wherein common contact line is on each dielectric barrier layer, such that each dielectric barrier layer electrically insulates a corresponding quantum well from the common contact line. 
     
     
       9. The display substrate of  claim 8 , wherein the plurality of separate micro LED devices are arranged in a pixel group. 
     
     
       10. The display substrate of  claim 9 , wherein the pixel group includes a red-emitting micro LED device, a green-emitting micro LED device, and a blue-emitting micro LED device. 
     
     
       11. The display substrate of  claim 1 , wherein the p-doped layer is thinner than the n-doped layer. 
     
     
       12. The display substrate of  claim 1 , wherein the p-n diode comprises an inorganic II-VI or III-V semiconductor. 
     
     
       13. The display substrate of  claim 1 , wherein the top and bottom surface of each p-n diode are concentric. 
     
     
       14. The display substrate of  claim 13 , wherein the top and bottom surface of each p-n diode are parallel. 
     
     
       15. The display substrate of  claim 14 , wherein the top surface of each p-n diode is planar. 
     
     
       16. The display substrate of  claim 15 , wherein the bottom surface of each p-n diode is wider than a corresponding lower metallization layer. 
     
     
       17. The display substrate of  claim 13 , wherein the bottom surface of each p-n diode is wider than a corresponding lower metallization layer. 
     
     
       18. The display substrate of  claim 1 , wherein the plurality of separate micro LED devices are arranged in a pixel group. 
     
     
       19. The display substrate of  claim 1 , wherein the plurality of separate micro LED devices are arranged in a pixel group. 
     
     
       20. The display substrate of  claim 19 , wherein the pixel group includes micro LED devices that are designed to emit different colors.

Description:
RELATED APPLICATIONS 
     This application is a continuation application of co-pending U.S. patent application Ser. No. 13/372,258, filed Feb. 13, 2012, which claims the benefit of priority from U.S. Provisional Patent Application Ser. No. 61/561,706 filed on Nov. 18, 2011 and U.S. Provisional Patent Application Ser. No. 61/594,919 filed on Feb. 3, 2012, the full disclosures of which are incorporated herein by reference. 
    
    
     FIELD 
     The present invention relates to micro semiconductor devices. More particularly embodiments of the present invention relate to a method of forming an array of micro devices such as light emitting diodes (LEDs) for transfer to a different substrate. 
     BACKGROUND INFORMATION 
     Light emitting diodes (LEDs) based upon gallium nitride (GaN) are expected to be used in future high-efficiency lighting applications, replacing incandescent and fluorescent lighting lamps. Current GaN-based LED devices are prepared by heteroepitaxial growth techniques on foreign substrate materials. A typical wafer level LED device structure may include a lower n-doped GaN layer formed over a sapphire growth substrate, a single quantum well (SQW) or multiple quantum well (MWQ), and an upper p-doped GaN layer. 
     In one implementation, the wafer level LED device structure is patterned into an array of mesas on the sapphire growth substrate by etching through the upper p-doped GaN layer, quantum well layer, and into the n-doped GaN layer. An upper p-electrode is formed on the top p-doped GaN surfaces of the array of mesas, and an n-electrode is formed on a portion of the n-doped GaN layer which is in contact with the array of mesas. The mesa LED devices remain on the sapphire growth substrate in the final product. 
     In another implementation, the wafer level LED device structure is transferred from the growth substrate to an acceptor substrate such as silicon, which has the advantage of being more easily diced to form individual chips than a GaN/sapphire composite structure. In this implementation, the wafer level LED device structure is permanently bonded to the acceptor (silicon) substrate with a permanent bonding layer. For example, the p-electrode formed on the p-doped GaN surfaces of the array of mesas can be bonded to the acceptor (silicon) substrate with a permanent bonding layer. The sapphire growth substrate is then removed to expose the inverted wafer level LED device structure, which is then thinned to expose the array of mesas. N-contacts are then made with the exposed n-doped GaN, and p-contacts are made on the silicon surface which is in electrical contact with the p-electrode. The mesa LED devices remain on the acceptor substrate in the final product. The GaN/silicon composite can also be diced to form individual chips. 
     SUMMARY OF THE INVENTION 
     A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with metal redistribution lines. In an embodiment, a micro LED structure includes a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer formed on a substrate. The metallization layer may include one or more layers. For example, the metallization layer may include an electrode layer and a barrier layer between the electrode layer and the bonding layer. The micro p-n diode and metallization layer may each have a top surface, a bottom surface and sidewalls. In an embodiment, the bottom surface of the micro p-n diode is wider than the top surface of the micro p-n diode, and the sidewalls are tapered outwardly from top to bottom. The top surface of the micro p-n diode may also be wider than the bottom surface of the p-n diode, or approximately the same width. In an embodiment, the bottom surface of the micro p-n diode is wider than the top surface of the metallization layer. The bottom surface of the micro p-n diode may also be wider than the top surface of the metallization layer, or approximately the same width as the top surface of the metallization layer. 
     A conformal dielectric barrier layer may optionally be formed over the micro p-n diode and other exposed surfaces. The conformal dielectric barrier layer may be thinner than the micro p-n diode, metallization layer and optionally the bonding layer so that the conformal dielectric barrier layer forms an outline of the topography it is formed on. In an embodiment, the conformal dielectric barrier layer spans sidewalls of the micro p-n diode, and may cover a quantum well layer in the micro p-n diode. The conformal dielectric barrier layer may also partially span the bottom surface of the micro p-n diode, as well as span sidewalls of the metallization layer. In some embodiments, the conformal dielectric barrier layer also spans sidewalls of a patterned bonding layer. A contact opening may be formed in the conformal dielectric barrier layer exposing the top surface of the micro p-n diode. The contact opening can have a width which is greater than, less than, or approximately the same width as the top surface of the micro p-n diode. In one embodiment, the contact opening has a width which is less than the width of the top surface of the micro p-n diode, and the conformal dielectric barrier layer forms a lip around the edges of the top surface of the micro p-n diode. 
     In some embodiments the bonding layer may be formed of a material which has a liquidus temperature or melting temperature below approximately 350° C., or more specifically below approximately 200° C. For example, the bonding layer may include indium, tin or a thermoplastic polymer such as polyethylene or polypropylene. The bonding layer may be laterally continuous across the substrate, or may also be formed in laterally separate locations. For example, a laterally separate location of the bonding layer may have a width which is less than or approximately the same width as the bottom surface of the micro p-n diode or metallization layer. 
     In an embodiment, a micro LED array includes a plurality of locations of a bonding layer on a carrier substrate, and a corresponding plurality of micro LED structures on the plurality of locations of the bonding layer. Each micro LED structure includes a micro p-n diode and a metallization layer with the metallization layer between the micro p-n diode and a respective location of the bonding layer. A conformal dielectric barrier layer can be deposited on the micro LED array on the substrate, with the conformal dielectric barrier layer spanning sidewalls of each micro p-n diode. The conformal dielectric barrier layer may also partially span the bottom surface of each micro p-n diode, and sidewalls of each metallization layer. A plurality of contact openings may be formed in the conformal dielectric barrier layer exposing a top surface of each micro p-n diode in which each contact opening has a width which may be greater than, less than, or approximately the same width as the top surface of each corresponding micro p-n diode. 
     The plurality of locations of the bonding layer may or may not be laterally separate from one another. In some embodiments, the plurality of locations of the bonding layer are laterally separate and the conformal dielectric barrier layer spans sidewalls of each of the plurality of laterally separate locations of the bonding layer. In some embodiments, the substrate includes a respective plurality of pillars on which the plurality of locations of the bonding layer are formed. For example, each micro p-n diode may include a bottom surface which is either approximately the same width as a top surface of a respective pillar or wider than the top surface of f the respective pillar. The pillars may also have a height which is greater than a respective thickness of the locations of the bonding layer. In an embodiment, the respective height is at least twice the respective thickness. 
     A micro LED structure and micro LED array may be formed utilizing existing heterogeneous growth technologies. In an embodiment a p-n diode layer and metallization layer are transferred from a growth substrate to a carrier substrate. In accordance with embodiments of the invention, the p-n diode layer and the metallization layer may be patterned prior to or after transfer to the carrier substrate. Transferring the p-n diode layer and the metallization layer to the carrier substrate may include bonding the metallization layer to a bonding layer on the carrier substrate. For example, the bonding layer may have a liquidus temperature or melting temperature below approximately 350° C., or more specifically below 200° C. For example, the bonding layer may be formed of indium or an indium alloy. After patterning the p-n diode layer and the metallization layer to form a plurality of separate micro p-n diodes and a plurality of separate locations of the metallization layer a conformal dielectric barrier layer is formed spanning the sidewalls of the plurality of separate micro p-n diodes. The conformal dielectric barrier layer may form an outline of the topography onto which it is formed, and may be thinner than the micro p-n diodes and the metallization layer. For example, the conformal dielectric barrier layer may be formed by atomic layer deposition (ALD). The conformal dielectric barrier layer may also be formed on a portion of the bottom surface of each separate micro p-n diode. 
     In an embodiment, the p-n diode layer and a patterned metallization layer including a plurality of separate locations of the metallization layer on the p-n diode layer are transferred from the growth substrate to the carrier substrate. The p-n diode layer may be partially patterned prior to transferring from the growth substrate to the carrier substrate, to form micro mesas separated by trenches in the p-n diode layer. In an embodiment, a plurality of pillars are formed on the carrier substrate prior to transferring the p-n diode layer and patterned metallization layer to the carrier substrate. The bonding layer may be formed over the plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the patterned metallization layer to the carrier substrate. 
     In an embodiment, the metallization layer is patterned to form a plurality of separate locations of the metallization layer after transferring the metallization layer and the p-n diode layer from the growth substrate to the carrier substrate. In such an embodiment, the p-n diode layer is patterned to form a plurality of separate micro p-n diodes, followed by patterning the metallization layer. Patterning of the metallization layer may include etching the metallization layer until a maximum width of the plurality of separate locations of the metallization layer are less than a width of the bottom surface of each of the plurality of separate micro p-n diodes. In an embodiment, the bonding layer is patterned after transferring the p-n diode layer and the metallization layer form the growth substrate to the carrier substrate. For example, the bonding layer can be etched until a maximum width of the plurality of separate locations of the bonding layer are less than a width of a bottom surface of each of the plurality of separate micro p-n diodes. A plurality of pillars can also be formed on the carrier substrate prior to transferring the p-n diode layer and the metallization layer from the growth substrate to the carrier substrate. The bonding layer may be formed over the plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the patterned metallization layer to the carrier substrate. 
     Once formed, the micro LED structure and micro LED array can be picked up and transferred to a receiving substrate. A transfer head can be positioned over the carrier substrate having an array of micro LED structures disposed thereon, and an operation is performed to create a phase change in the bonding layer for at least one of the micro LED structures. For example, the operation may be heating the bonding layer above a liquidus temperature or melting temperature of the bonding layer, or altering a crystal phase of the bonding layer. The at least one micro LED structure including the micro p-n diode and the metallization layer, and optionally a portion of the bonding layer for the at least one of the micro LED structures may be picked up with a transfer head and placed on a receiving substrate. If a conformal dielectric barrier layer has already been formed, a portion of the conformal dielectric barrier layer may also be picked up with the micro p-n diode and the metallization layer. Alternatively, a conformal dielectric barrier layer can be formed over the micro LED structure, or plurality of micro LED structures, after being placed on the receiving substrate. 
     In an embodiment, the conformal dielectric barrier layer spans a portion of the bottom surface of the micro p-n diode, spans sidewalls of the metallization layer, and spans across a portion of the bonding layer adjacent the metallization layer. The conformal dielectric barrier layer may be cleaved after contacting the micro LED structure with the transfer head and/or creating the phase change in the bonding layer, which may be prior to picking up the micro p-n diode and the metallization layer with the transfer head. For example, cleaving the conformal dielectric barrier layer may include transferring a pressure from the transfer head to the conformal dielectric barrier layer and/or heating the bonding layer above a liquidus temperature of the bonding layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a cross-sectional side view illustration of a bulk LED substrate in accordance with an embodiment of the invention. 
         FIG. 1B  is a cross-sectional side view illustration of a patterned metallization layer in accordance with an embodiment of the invention. 
         FIG. 1C  is a cross-sectional side view illustration of a patterned p-n diode layer in accordance with an embodiment of the invention. 
         FIGS. 2A-2E  are cross-sectional side view illustrations of a carrier substrate with bonding layer in accordance with an embodiment of the invention. 
         FIG. 3  is a cross-sectional side view illustration of bonding a growth substrate and carrier substrate together in accordance with an embodiment of the invention. 
         FIG. 4  is a cross-sectional side view illustration of various possible structures after bonding the growth substrate and carrier substrate together in accordance with an embodiment of the invention. 
         FIG. 5  is a cross-sectional side view illustration of the growth substrate removed from the bonded structure in accordance with an embodiment of the invention. 
         FIG. 6  is a cross-sectional side view illustration of a thinned-down p-n diode layer in accordance with an embodiment of the invention. 
         FIG. 7  is a cross-sectional side view illustration of etching p-n diode layer to form micro p-n diodes in accordance with an embodiment of the invention. 
         FIG. 7 ′- 7 ″ are a cross-sectional side view illustrations etching layers in accordance with an embodiment of the invention. 
         FIG. 8  is a cross-sectional side view illustration of various micro LED structures in accordance with an embodiment of the invention. 
         FIGS. 9-9 ′ are cross-sectional side view illustrations of the formation of contact openings in a micro LED array in accordance with an embodiment of the invention. 
         FIGS. 10-10 ″ are cross-sectional side view illustrations of the formation of contact openings in a micro LED array in accordance with an embodiment of the invention. 
         FIGS. 11A-11C  are cross sectional side view illustrations of a wicked up bonding layer in accordance with an embodiment of the invention. 
         FIGS. 12A-12B  include top and cross-sectional side view illustrations of a carrier wafer and array of micro LED structures including micro p-n diodes in accordance with an embodiment of the invention. 
         FIG. 13  is an illustration of a method of picking up and transferring a micro LED structure from a carrier substrate to a receiving substrate in accordance with an embodiment of the invention. 
         FIG. 14  is a cross-sectional side view illustration of a transfer head picking up a micro LED structure from a carrier substrate in accordance with an embodiment of the invention. 
         FIG. 15  is a cross-sectional side view illustration of a bipolar micro device transfer head in accordance with an embodiment of the invention. 
         FIG. 16  is a cross-sectional side view illustration of a receiving substrate with a plurality of micro LEDs in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the present invention describe micro semiconductor devices and a method of forming an array of micro semiconductor devices such as micro light emitting diodes (LEDs) for transfer to a receiving substrate. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with metal redistribution lines. While embodiments of the present invention are described with specific regard to micro LEDs comprising p-n diodes, it is to be appreciated that embodiments of the invention are not so limited and that certain embodiments may also be applicable to other micro semiconductor devices which are designed in such a way so as to perform in a controlled fashion a predetermined electronic function (e.g. diode, transistor, integrated circuit) or photonic function (LED, laser). 
     In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to “one embodiment,” “an embodiment” or the like means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in one embodiment,” “in an embodiment” or the like in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. 
     The terms “spanning,” “over,” “to,” “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “spanning,” “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers. 
     The terms “micro” device, “micro” p-n diode or “micro” LED structure as used herein may refer to the descriptive size of certain devices or structures in accordance with embodiments of the invention. As used herein, the terms “micro” devices or structures are meant to refer to the scale of 1 to 100 μm. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller size scales. 
     In one aspect, embodiments of the invention describe a method of processing a bulk LED substrate into an array of micro LED structures which are poised for pick up and transfer to a receiving substrate. In this manner, it is possible to integrate and assemble micro LED structures into heterogeneously integrated systems. The micro LED structures can be picked up and transferred individually, in groups, or as the entire array. Thus, the micro LED structures in the array of micro LED structures are poised for pick up and transfer to a receiving substrate such as display substrate of any size ranging from micro displays to large area displays, and at high transfer rates. In some embodiments, arrays of micro LED structures which are poised for pick up are described as having a 10 μm by 10 μm pitch, or 5 μm by 5 μm pitch. At these densities a 6 inch substrate, for example, can accommodate approximately 165 million micro LED structures with a 10 μm by 10 μm pitch, or approximately 660 million micro LED structures with a 5 μm by 5 μm pitch. Thus, a high density of pre-fabricated micro devices with a specific functionality may be produced in a manner in which they are poised for pick up and transfer to a receiving substrate. The techniques described herein are not limited to micro LED structures, and may also be used in the manufacture of other micro devices. 
     In another aspect, embodiments of the invention describe a micro LED structure and micro LED array in which each micro p-n diode is formed over a respective location of a bonding layer. The respective locations of the bonding layer may or may not be laterally separate locations. An operation may be performed on a respective location of the bonding layer corresponding to a micro LED during the micro LED pick up process in which the respective location of the bonding layer undergoes a phase change which assists in the pick up process. For example, the respective location of the bonding layer may change from solid to liquid in response to a temperature cycle. In the liquid state the respective location of the bonding layer may retain the micro p-n diode in place on a carrier substrate through surface tension forces, while also providing a medium from which the micro p-n diode is readily releasable. In addition, the liquid state may act as a cushion or shock absorber to absorb forces exerted by a transfer head if a transfer head makes contact with the micro LED structure during the pick up process. In this manner, the liquid state may compensate for non-uniformities in the topography in the micro LED array or transfer head array by smoothing out over the underlying surface in response to compressive forces exerted by a transfer head. In other embodiments, the respective location of the bonding layer may not undergo a complete phase transformation. For example, the respective location of the bonding layer may become substantially more malleable in response to a temperature cycle while partially remaining in the solid state. In another embodiment, the respective location of the bonding layer may undergo a crystal phase transformation in response to an operation, such as a temperature cycle. 
     Referring now to  FIG. 1 , a semiconductor device layer  110  may be formed on a substrate  101 . In an embodiment, semiconductor device layer  110  may include one or more layers and is designed in such a way so as to perform in a controlled fashion a predetermined electronic function (e.g. diode, transistor, integrated circuit) or photonic function (LED, laser). It is to be appreciated that while semiconductor device layer  110  may be designed in such a way so as to perform in a controlled fashion in a predetermined function, that the semiconductor device layer  110  may not be fully functionalized. For example, contacts such as an anode or cathode may not yet be formed. In the interest of conciseness and to not obscure embodiments of the invention, the following description is made with regard to semiconductor device layer  110  as a p-n diode layer  110  grown on a growth substrate  101  in accordance with conventional heterogeneous growth conditions. 
     The p-n diode layer  110  may include a compound semiconductor having a bandgap corresponding to a specific region in the spectrum. For example, the p-n diode layer  110  may include one or more layers based on II-VI materials (e.g. ZnSe) or III-V nitride materials (e.g. GaN, AlN, InN, and their alloys). Growth substrate  101  may include any suitable substrate such as, but not limited to, silicon, SiC, GaAs, GaN and sapphire (Al 2 O 3 ). 
     In a particular embodiment, growth substrate  101  is sapphire, and the p-n diode layer  110  is formed of GaN. Despite the fact that sapphire has a larger lattice constant and thermal expansion coefficient mismatch with respect to GaN, sapphire is reasonably low cost, widely available and its transparency is compatible with excimer laser-based lift-off (LLO) techniques. In another embodiment, another material such as SiC may be used as the growth substrate  101  for a GaN p-n diode layer  110 . Like sapphire, SiC substrates may be transparent. Several growth techniques may be used for growth of p-n diode layer  110  such as metalorganic chemical vapor deposition (MOCVD). GaN, for example, can be grown by simultaneously introducing trimethylgallium (TMGa) and ammonia (NH 3 ) precursors into a reaction chamber with the sapphire growth substrate  101  being heated to an elevated temperature such as 800° C. to 1,000° C. In the particular embodiment illustrated in  FIG. 1A , p-n diode layer  110  may include a bulk GaN layer  112 , an n-doped layer  114 , a quantum well  116  and p-doped layer  118 . The bulk GaN layer  112  may be n-doped due to silicon or oxygen contamination, or intentionally doped with a donor such as silicon. N-doped GaN layer  114  may likewise be doped with a donor such as silicon, while p-doped layer  118  may be doped with an acceptor such as magnesium. A variety of alternative p-n diode configurations may be utilized to form p-n diode layer  110 . Likewise, a variety of single quantum well (SQW) or multiple quantum well (MQW) configurations may be utilized to form quantum well  116 . In addition, various buffer layers may be included as appropriate. In one embodiment, the sapphire growth substrate  101  has a thickness of approximately 200 μm, bulk GaN layer  112  has a thickness of approximately 5 μm, n-doped layer  114  has a thickness of approximately 0.1 μm-3 μm, quantum well layer  116  has a thickness less than approximately 0.3 μm and p-doped layer  118  has a thickness of approximately 0.1 μm-1 μm. 
     A metallization layer  120  may then be formed over the p-n diode layer  110 . As illustrated in  FIG. 1A , metallization layer  120  may include an electrode layer  122  and optionally a barrier layer  124 , though other layers may be included. In an embodiment, metallization layer has a thickness of approximately 0.1 μm-2 μm. Electrode layer  122  may make ohmic contact to the p-doped GaN layer  118 , and may be formed of a high work-function metal such as Ni, Au, Ag, Pd and Pt. In an embodiment, electrode layer  122  may be reflective to light emission. In another embodiment, electrode layer  122  may also be transparent to light emission. Transparency may be accomplished by making the electrode layer very thin to minimize light absorption. Barrier layer  124  may optionally be included in the metallization layer  120  to prevent diffusion of impurities into the p-n diode  110 . For example, barrier layer  124  may include, but is not limited to, Pd, Pt, Ni, Ta, Ti and TiW. In certain embodiments, barrier layer  124  may prevent the diffusion of components from the bonding layer into the p-n diode layer  110 . 
     In accordance with certain embodiments of the invention, p-n diode layer  110  and metallization layer  120  are grown on a growth substrate  101  and subsequently transferred to a carrier substrate  201 , such as one illustrated in  FIGS. 2A-2E  and described in more detail in the following description. As described in more detail in the following figures and description, the metallization layer  120  and p-n diode layer  110  can be patterned prior to transfer to a carrier substrate  201 . The carrier substrate  201  and bonding layer  210  may also be patterned prior to transfer of the p-n diode layer  110  and metallization layer  120  to the carrier substrate  201 . Accordingly, embodiments of the invention may be implemented in a multitude of variations during formation of an array of micro LEDs for subsequent transfer to a receiving substrate. 
     Referring now to  FIG. 1B  metallization layer  120  may be patterned prior to transfer to a carrier substrate  201 . In an embodiment, the structure of  FIG. 1B  may be achieved by forming a patterned photoresist layer over the p-n diode layer  110  followed by deposition of the metallization layer  120 . The photoresist layer is then lifted off (along with the portion of the metallization layer on the photoresist layer) leaving behind the laterally separate locations of metallization layer  120  illustrated in  FIG. 1B . In certain embodiments, the pitch of the laterally separate locations of metallization layer  120  may be 5 μm, 10 μm, or larger corresponding to the pitch of the array of micro LEDs. For example, a 5 μm pitch may be formed of 3 μm wide laterally separate locations of metallization layer  120  separated by a 2 μm spacing. A 10 μm pitch may be formed of 8 μm wide separate locations of metallization layer  120  separated by a 2 μm spacing. Though, these dimensions are meant to be exemplary and embodiments of the invention are not so limited. In some embodiments, the width of the laterally separate locations of metallization layer  120  is less than or equal to the width of the bottom surface of the array of micro p-n diodes  150  as discussed in further detail in the following description and figures. 
     Referring now to  FIG. 1C  patterning of the metallization layer  120  may be followed by patterning of p-n diode layer  110 . In an embodiment, the structure of  FIG. 1C  may be achieved by forming a second patterned photoresist layer over the laterally separate locations of metallization layer  120  and an etchant is applied to etch the p-n diode layer  110  to etch trenches  134  and form a plurality of micro mesas  130 . Referring again to the enlarged section of p-n diode layer  110  in FIG.  1 A, in an embodiment, etching is performed to etch trenches through the p-doped layer  118 , quantum well  116 , and into the n-doped layer  114  or bulk layer  112 . Etching of the GaN p-n diode layer  110  can be performed utilizing dry plasma etching techniques such as reactive ion etching (RIE), electro-cyclotron resonance (ECR), inductively coupled plasma reactive ion etching ICP-RIE, and chemically assisted ion-beam etching (CAIBE). The etch chemistries may be halogen-based, containing species such as Cl 2 , BCl 3  or SiCl 4 . In the particular embodiment illustrated in  FIG. 1C , micro mesas  130  may have tapered sidewalls  132  up to 15 degrees. For example, RIE with a chlorine-based etch chemistry may be utilized. Alternatively, the sidewalls may be vertical. For example, ICP-RIE which a chlorine-based etch chemistry may be utilized to obtain vertical sidewalls. 
     In certain embodiments, the pitch of the micro mesas  130  may be 5 μm, 10 μm, or larger. For example, a micro mesa  130  array with a 5 μm pitch may be formed of 3 μm wide micro mesas separated by a 2 μm spacing. A micro mesa  130  array with a 10 μm pitch may be formed of 8 μm wide micro mesas separated by a 2 μm spacing. Though, these dimensions are meant to be exemplary and embodiments of the invention are not so limited. 
       FIGS. 2A-2E  are cross-sectional side view illustrations of various embodiments of a carrier substrate  201  with bonding layer  210  for bonding to the metallization layer  120  on growth substrate  101 .  FIG. 2A  illustrates a carrier substrate  201  and bonding layer  210  which are not patterned prior to bonding.  FIGS. 2B-2D  illustrate a carrier substrate  201  which has been patterned to form a plurality of posts  202  having sidewalls  204  and separated by trenches  206 . Posts  202  may have a maximum width which is equal to or less than a width of the micro p-n diodes  135 ,  150 , as will become more apparent in the following description and figures. In an embodiment, the trench posts  202  are at least twice as tall as a thickness of the bonding layer  210 . In an embodiment, bonding layer  210  may have a thickness of approximately 0.1 μm-2 μm, and trench posts have a height of at least 0.2 μm-4 μm. In the particular embodiment illustrated in  FIG. 2B , a conformal bonding layer  210  is formed over the posts  202 , and on the sidewalls  204  and within trenches  206 . In the particular embodiment illustrated in  FIG. 2C , bonding layer  210  is anisotropically deposited so that it is formed only on the top surface of posts  202  and within the trenches  206 , without a significant amount being deposited on the sidewalls  204 . In the particular embodiment illustrated in  FIG. 2D , bonding layer  210  is formed only on the top surface of posts  202 . Such a configuration may be formed by patterning the posts  202  and bonding layer  210  with the same patterned photoresist. In the particular embodiment illustrated in  FIG. 2E , the laterally separate locations of the bonding layer  210  may be formed with a photoresist lift off technique in which a blanket layer of the bonding layer is deposited over a patterned photoresist layer, which is then lifted off (along with the portion of the bonding layer on the photoresist layer) leaving behind the laterally separate locations of the bonding layer  210  illustrated in  FIG. 2E , though other processing techniques may be used. 
     As described above with regard to  FIGS. 2B-2E  and  FIGS. 1B-1C , certain embodiments of the invention include laterally separate locations of the metallization layer  120  and/or laterally separate locations of the bonding layer  210 . With regard to  FIG. 2B , in which a conformal bonding layer  210  is formed over the posts  202 , and on the sidewalls  204  and within trenches  206 , the particular locations of the bonding layer on top of the posts  202  are laterally separated by the trenches  206 . Thus, even though the conformal bonding layer  210  is continuous, the locations of the bonding layer  210  on top of the posts  202  are laterally separate locations. Likewise, the individual discrete locations of the bonding layer  210  in  FIG. 2E  are laterally separated by the space between them. Where posts  202  exist, the relationship of the bonding layer  210  thickness to post  202  height may factor into the lateral separation of the locations of the bonding layer  210 . 
     Bonding layer  210  may be formed from a variety of suitable materials. Bonding layer may be formed from a material which is capable of adhering a micro LED structure to a carrier substrate. In an embodiment, bonding layer  210  may undergo a phase change in response to an operation such as change in temperature. In an embodiment, bonding layer may be removable as a result of the phase change. In an embodiment, bonding layer may be remeltable or reflowable. In an embodiment, the bonding layer may have a liquidus temperature or melting temperature below approximately 350° C., or more specifically below approximately 200° C. At such temperatures the bonding layer may undergo a phase change without substantially affecting the other components of the micro LED structure. For example, the bonding layer may be formed of a metal or metal alloy, or of a thermoplastic polymer which is removable. In an embodiment, the bonding layer may be conductive. For example, where the bonding layer undergoes a phase change from solid to liquid in response to a change in temperature a portion of the bonding layer may remain on the micro LED structure during the pick up operation as described in more detail the following description. In such an embodiment, it may be beneficial that the bonding layer is formed of a conductive material so that it does not adversely affect the micro LED structure when it is subsequently transferred to a receiving substrate. In this case, the portion of conductive bonding layer remaining on the micro LED structure during the transfer operation may aid in bonding the micro LED structure to a conductive pad on the receiving substrate. 
     Solders may be suitable materials for bonding layer  210  since many are generally ductile materials in their solid state and exhibit favorable wetting with semiconductor and metal surfaces. A typical alloy melts not a single temperature, but over a temperature range. Thus, solder alloys are often characterized by a liquidus temperature corresponding to the lowest temperature at which the alloy remains liquid, and a solidus temperature corresponding to the highest temperature at which the alloy remains solid. An exemplary list of low melting solder materials which may be utilized with embodiments of the invention are provided in Table 1. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Liquidus  
                 Solidus  
               
               
                   
                 Chemical composition 
                 Temperature (° C.) 
                 Temperature (° C.) 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 100 In 
                 156.7 
                 156.7 
               
               
                   
                 66.3In33.7Bi 
                 72 
                 72 
               
               
                   
                 51In32.5Bi16.5Sn 
                 60 
                 60 
               
               
                   
                 57Bi26In17Sn 
                 79 
                 79 
               
               
                   
                 54.02Bi29.68In16.3Sn 
                 81 
                 81 
               
               
                   
                 67Bi33In 
                 109 
                 109 
               
               
                   
                 50In50Sn 
                 125 
                 118 
               
               
                   
                 52Sn48In 
                 131 
                 118 
               
               
                   
                 58Bi42Sn 
                 138 
                 138 
               
               
                   
                 97In3Ag 
                 143 
                 143 
               
               
                   
                 58Sn42In 
                 145 
                 118 
               
               
                   
                 99.3In0.7Ga 
                 150 
                 150 
               
               
                   
                 95In5Bi 
                 150 
                 125 
               
               
                   
                 99.4In0.6Ga 
                 152 
                 152 
               
               
                   
                 99.6In0.4Ga 
                 153 
                 153 
               
               
                   
                 99.5In0.5Ga 
                 154 
                 154 
               
               
                   
                 60Sn40Bi 
                 170 
                 138 
               
               
                   
                 100Sn 
                 232 
                 232 
               
               
                   
                 95Sn5Sb 
                 240 
                 235 
               
               
                   
                   
               
            
           
         
       
     
     An exemplary list thermoplastic polymers which may be utilized with embodiments of the invention are provided in Table 2. 
     
       
         
           
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Polymer 
                 Melting Temperature (° C.) 
               
               
                   
               
             
            
               
                 Acrylic (PMMA) 
                 130-140 
               
               
                 Polyoxymethylene (POM or Acetal) 
                 166 
               
               
                 Polybutylene terephthalate (PBT) 
                 160 
               
               
                 Polycaprolactone (PCL) 
                 62 
               
               
                 Polyethylene terephthalate (PET) 
                 260 
               
               
                 Polycarbonate (PC) 
                 267 
               
               
                 Polyester 
                 260 
               
               
                 Polyethylene (PE) 
                 105-130 
               
               
                 Polyetheretherketone (PEEK) 
                 343 
               
               
                 Polylactic acid (PLA) 
                 50-80 
               
               
                 Polypropylene (PP) 
                 160 
               
               
                 Polystyrene (PS) 
                 240 
               
               
                 Polyvinylidene chloride (PVDC) 
                 185 
               
               
                   
               
            
           
         
       
     
     In accordance with embodiments of the invention, bonding layer  210  is formed with a uniform thickness and may be deposited by a variety of suitable methods depending upon the particular composition. For example, solder compositions may be sputtered, deposited by electron beam (E-beam) evaporation, or plated with a seed layer to obtain a uniform thickness. 
     Posts  202  may be formed from a variety of materials and techniques. In an embodiment, posts  202  may be formed integrally with carrier substrate  201  by patterning the carrier substrate  201  by an etching or embossing process. For example, carrier substrate  201  may be a silicon substrate with integrally formed posts  202 . In another embodiment, posts can be formed on top of carrier substrate  201 . For example, posts  202  may be formed by a plate up and photoresist lift off technique. Posts can be formed from any suitable material including semiconductors, metals, polymers, dielectrics, etc. 
     Referring now to  FIG. 3 , the growth substrate  101  and carrier substrate  201  may be bonded together under heat and/or pressure. It is to be appreciated that while  FIG. 3  illustrates the bonding of the patterned structure of  FIG. 1B  with the unpatterned structure of  FIG. 2A , that any combination of  FIGS. 1A-1C  and  FIGS. 2A-2E  are contemplated in accordance with embodiments of the invention. In addition, while it has been described that bonding layer  210  is formed on the carrier substrate  201  prior to bonding, it is also possible that the bonding layer  210  is formed on the metallization layer  120  of the growth substrate  101  prior to bonding. For example, bonding layer  210  could be formed over metallization layer  120 , and patterned with metallization layer  120  during formation of the laterally separate locations of metallization layer illustrated in  FIG. 1B . While not illustrated, depending upon the particular arrangement and composition of layers in formed on the substrates to be bonded together, an oxidation resistant film may be formed on the top surface of either or both substrates to prevent oxidation prior to bonding. For example, in one embodiment, a thin gold film can be deposited on either or both of the exposed surface of metallization layer  120  and bonding layer  210 . During bonding of the substrates illustrated in  FIG. 3 , the bonding layer  210  may partially soak up the gold film resulting in a gold alloy at the bonding interface between the substrates. 
       FIG. 4  is a cross-sectional side view illustration of various non-limiting possible structures after bonding the growth substrate  101  and carrier substrate  201 . The particular combinations of substrates are described in Table 3. For example, the particular embodiment illustrated in Example 4A represents the bonding of the carrier substrate illustrated in  FIG. 2D  to the growth substrate illustrated in  FIG. 1C . 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
                 Ex. 
               
               
                   
                 4A 
                 4B 
                 4C 
                 4D 
                 4E 
                 4F 
                 4G 
                 4H 
                 4I 
                 4J 
                 4K 
                 4L 
                 4M 
                 4N 
                 4O 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
            
               
                 Carrier 
                 2D 
                 2C 
                 2B 
                 2D 
                 2C 
                 2B 
                 2A 
                 2E 
                 2A 
                 2E 
                 2D 
                 2C 
                 2B 
                 2A 
                 2E 
               
               
                 Substrate 
               
               
                 (2A-2D) 
               
               
                 Growth 
                 1C 
                 1C 
                 1C 
                 1A 
                 1A 
                 1A 
                 1A 
                 1A 
                 1C 
                 1C 
                 1B 
                 1B 
                 1B 
                 1B 
                 1B 
               
               
                 Substrate 
               
               
                 (1B) 
               
               
                   
               
            
           
         
       
     
     As described above, the structures of many of the examples can also be created by forming the bonding layer  210  on the growth substrate, followed by bonding the growth substrate  101  to the carrier substrate  201 . For example, example 4O, can also be created by patterning bonding layer  210  and metallization layer  210  on growth substrate  101 , following by bonding the growth substrate  101  to carrier substrate  201 . 
     Referring now to  FIG. 5 , the growth substrate  101  has been removed from the bonded structure. Growth substrate  101  may be removed by a suitable method such as chemical etching or an excimer laser-based lift-off (LLO) if the growth substrate is transparent. In an embodiment, LLO of a GaN p-n diode layer  110  from a transparent sapphire growth substrate  101  is accomplished by irradiating the  101 / 110  layer interface through the transparent sapphire growth substrate  101  with a short pulse (e.g. tens of nanoseconds) from an ultraviolet laser such as a Nd-YAG laser or KrF excimer laser. Absorption in the GaN p-n diode layer  110  at the interface results in localized heating of the interface resulting in decomposition at the interfacial GaN to liquid Ga metal and nitrogen gas. Once the desired are has been irradiated, the transparent sapphire growth substrate  101  can be removed by remelting the Ga on a hotplate. 
     Referring now to  FIG. 6 , the p-n diode layer  110  is thinned down to a desirable thickness. Referring back to the enlarged p-n diode layer  110  in  FIG. 1A , a predetermined amount of the bulk GaN layer  112  (which may be n-type) or a portion of the n-type GaN layer  114  are removed so that an operable p-n diode remains after thinning. Depending upon the underlying structure, the thinning process may be performed utilizing suitable techniques such as polishing, wet etching or dry etching. For example, a combination of polish and/or timed etch to a desired thickness may be performed. In circumstances where there are underlying patterned structures such as pillars or micro mesas, a timed etch to a desired thickness may be performed in order to avoid damaging the patterned structures. As shown in Examples 6A, 6B, 6C, 6I and 6J where the p-n diode layers  110  were pre-patterned to form micro mesas  130 , they are now free-standing micro p-n diodes  135 . 
     If either of the growth substrate  101  or carrier substrate  201  structures were not pre-patterned or only partially pre-patterned prior to bonding, then additional patterning may be performed after the p-n diode layer  110  thinning illustrated in  FIG. 6 . As illustrated in  FIG. 7  a patterned mask layer  140  may be formed over the unpatterned p-n diode layer  110  for etching of p-n diode layer  110  to form free standing micro p-n diodes  150 . Mask layer  140  may be formed from photoresist or a variety of materials such as metal (e.g. chromium, nickel) or dielectric (silicon nitride, silicon oxide) which are more resistant to the GaN etching conditions than is photoresist. Etching of the GaN p-n diode layer  110  can be performed utilizing dry plasma etching techniques such as reactive ion etching (RIE), electro-cyclotron resonance (ECR), inductively coupled plasma reactive ion etching (ICP-RIE), and chemically assisted ion-beam etching (CAIBE). The etch chemistries may be halogen-based, containing species such as Cl 2 , BCl 3  or SiCl 4 . 
     In the particular embodiment illustrated in  FIG. 7 , micro p-n diodes  150  may have outwardly tapered sidewalls  153  (from top to bottom of the micro p-n diodes  150 ) up to 15 degrees. For example, RIE with a chlorine-based etch chemistry may be utilized. Alternatively, the sidewalls  153  may be vertical. For example, ICP-RIE which a chlorine-based etch chemistry may be utilized to obtain vertical sidewalls. As will become apparent in the description of  FIG. 16 , outwardly tapered sidewalls may be advantageous in some embodiments when forming a common contact over a series of micro LED structures which have been picked up and transferred to a receiving substrate. In certain embodiments, the pitch between the micro p-n diodes  150  may be 5 μm, 10 μm, or larger. For example, a micro p-n diode  150  array with a 5 μm pitch may be formed of 3 μm wide micro p-n diodes separated by a 2 μm spacing. A micro p-n diode  150  array with a 10 μm pitch may be formed of 8 μm wide micro p-n diodes separated by a 2 μm spacing. 
     Referring now to  FIGS. 7 ′- 7 ″, etching may optionally be continued on metallization layer  120  and/or bonding layer  210  utilizing suitable etching chemistries based upon the particular materials in metallization layer  120  and bonding layer  210 . In certain embodiments illustrated in  FIG. 7 ′, anisotropic etching with a dry etching chemistry can be utilized to etch metallization layer  120  and/or bonding layer  210  so that the layers  120 ,  210  have a width matching the overlying lower surface of the micro p-n diode  150 . In certain embodiments illustrated in  FIG. 7 ″, wet etching may be utilized to “undercut” the metallization layer  120  and/or bonding layer  210  underneath the overlying lower surface of the micro p-n diode  150  as illustrated in Examples 7″D-7″H. While not specifically illustrated, it is understood that etching could also be performed to “undercut” the underlying layers  120 ,  210  underneath micro p-n diodes  135 . 
     Upon completion of etching processes for the micro p-n diodes, metallization layer or bonding layer, the mask layer  140  may be removed, for example by using a selective etching technique, resulting the micro LED array illustrated in  FIG. 8 . As illustrated, the micro LED array includes a carrier substrate  201 , a plurality of locations of a bonding layer  210  (which may or may not be laterally separate) on the carrier substrate, and a respective plurality of separate micro p-n diodes  135 ,  150  over the plurality of locations of the bonding layer  210 . A plurality of separate locations of metallization layer  120  are formed between the respective plurality of separate micro p-n diodes  135 ,  150  and the plurality of locations of the bonding layer  210 . In some embodiments, the carrier substrate includes a respective plurality of pillars  202  on which the plurality of laterally separate locations of the bonding layer  210  are formed, as illustrated in Examples 8A-8F and Examples 8K-8M. 
     In some embodiments, the micro p-n diodes  150  (as well as micro p-n diodes  135 ) include a top surface  152  and a bottom surface  151 , and the metallization layer  120  includes a top surface  121  and a bottom surface, and the bottom surface  151  of the micro p-n diode  150  (as well as micro p-n diodes  135 ) is wider than the top surface  121  of the metallization layer  120 . 
     In some embodiments, the plurality of micro p-n diodes  135 ,  150  each include a bottom surface  151  which has approximately the same width as a top surface  203  of each of the respective plurality of pillars  202 . In other embodiments, the plurality of micro p-n diodes  135 ,  150  each include a bottom surface  151  which is wider than a top surface  203  of each of the respective plurality of pillars  202 . The relationship of the micro p-n diode  135 ,  150  bottom width and underlying pillar  202  top surface may affect the pick up process. For example, if the bonding layer  210  exhibits a phase change from solid to liquid during the pick up process then the micro p-n diode  135 ,  150  is essentially floating on a liquid layer. Surface tension forces in the liquid bonding layer  210  may retain the micro p-n diode  135 ,  150  in place on top of the pillar  202 . In particular, surface tension forces associated with the edges of the top surface of the pillar  202  may further assist in maintaining the micro p-n diode  135 ,  150  in place where the pillar  202  top surface width is less than or approximately equal to the p-n diode  135 ,  150  bottom width. 
     In some embodiments, the plurality of micro p-n diodes  135 ,  150  are positioned over an unpatterned bonding layer  210 . For example, as illustrated in Example 6I and Example 8N, the bonding layer  210  may be a uniform layer on the carrier substrate and the corresponding plurality of locations of the bonding layer  210  are not laterally separate from each other. In other embodiments, the plurality of micro p-n diodes  135 ,  150  are positioned over a pattered bonding layer  210 . For example, as illustrated in Examples 8A-8M and Example 8O, the patterned bonding layer may include a plurality of laterally separate locations of the bonding layer  210 . In an embodiment, the plurality of micro p-n diodes  135 ,  150  each include a bottom surface  151  which has approximately the same or greater width than a corresponding top surface  211  for a plurality of laterally separate locations of the bonding layer  210 . 
     As previously described the bonding layer may absorb compression forces associated with contacting the micro LED structure with a transfer head during the pick up process. As a result, the bonding layer may absorb the compressive forces and bulge out laterally. Where each micro LED structure is patterned to have a small separation distance, of 2 μm for example, the amount of bonding layer laterally protruding from each micro LED structure should be minimized so as to not interfere with an adjacent micro LED structure during the pick up process. In certain embodiments where trenches  206  are present between posts  202 , the trenches may act as bonding layer reservoirs into which molten bonding layer may flow without interfering with an adjacent micro LED structure. 
     In some embodiments, the micro LED structures or array of micro LED structures of  FIG. 8  (as well as the micro LED structures of  FIG. 6  Example 6I, and  FIG. 7  Examples 7′D-7′I after removal of layer  140 ) are poised for pick up and transfer to a receiving substrate, for example with a transfer head  300  described in more detail with regard to  FIGS. 14-16 . In other embodiments, a thin conformal dielectric barrier layer may be formed of an array of any of the micro p-n diodes  135 ,  150  prior to pick up and transfer to a receiving substrate. Referring now to  FIGS. 9-9 ′, a thin conformal dielectric barrier layer  160  may be formed over an array of any of the micro p-n diodes  150  of  FIGS. 7-7 ″. In one embodiment, the thin conformal dielectric barrier layer  160  may protect against charge arcing between adjacent micro p-n diodes  150  during the pick up process, and thereby protect against adjacent micro p-n diodes  150  from sticking together during the pick up process. The thin conformal dielectric barrier layer  160  may also protect the sidewalls  153 , quantum well layer  116  and bottom surface  151 , of the micro p-n diodes  150  from contamination which could affect the integrity of the micro p-n diodes  150 . For example, the thin conformal dielectric barrier layer  160  can function as a physical barrier to wicking of the bonding layer material  210  up the sidewalls and quantum layer  116  of the micro p-n diodes  150  as described in more detail with regard to  FIGS. 11A-11C  in the following description. The thin conformal dielectric barrier layer  160  may also insulate the micro p-n diodes  150  once placed on a receiving substrate. In an embodiment, the thin conformal dielectric barrier layer  160  is approximately 50-600 angstroms thick aluminum oxide (Al2O3). Conformal dielectric barrier layer  160  may be deposited by a variety of suitable techniques such as, but not limited to, atomic layer deposition (ALD). 
     The thin conformal dielectric layer and contact openings can be formed using a mask layer lift off technique. Referring to  FIGS. 9-9 ′, the mask layer  140  illustrated in  FIG. 7  for patterning the micro p-n diode  150  can also be used in a lift off technique for forming the thin conformal dielectric barrier layer  160  and contact opening  162 . The thin conformal dielectric barrier layer  160  may be formed over an array of any of the micro p-n diodes  150  of  FIG. 7 ,  FIG. 7 ′ or  FIG. 7 ″ and is conformal to and spans across exposed surfaces of the mask layer  140 , and sidewalls  153  and the bottom surface  151  of the p-n diode  150 . The conformal dielectric barrier layer  160  may also span across exposed surfaces of metallization layer  120 , bonding layer  210 , as well as the carrier substrate and posts  202 , if present. The mask layer  140  is then removed, lifting off the portion of the thin conformal dielectric barrier layer  160  formed thereon resulting in the structure illustrated in  FIG. 9 ′ including contact openings  162 . In the particular embodiment illustrated in  FIG. 9 ′, the conformal dielectric barrier layer  160  is not formed on the top surface  152  of the micro p-n diodes  150 . 
     Referring to  FIGS. 10-10 ″ the thin conformal dielectric layer can also be formed over the array of micro p-n diodes  135 ,  150  of  FIG. 8  (as well as the micro LED structures of  FIG. 6  Example 6I, and  FIG. 7  Examples 7′D-7′I after removal of layer  140 ) followed by patterning to create contact openings  162 . As illustrated in  FIG. 9 , the thin conformal dielectric barrier layer  160  may be formed over an array of any of the micro p-n diodes  150  and is conformal to and spans across the exposed top surface and sidewalls of the p-n diodes  150 . The dielectric barrier layer  160  may also span across the exposed bottom surface  151  of the p-n diodes  135 ,  150  and surfaces of metallization layer  120 , bonding layer  210 , as well as the carrier substrate  201  and posts  202 , if present. A blanket photoresist layer may then be formed over the p-n diode array and carrier substrate  201 , and then patterned to form openings over each micro p-n diode  135 ,  150 . The thin conformal dielectric barrier layer  160  may then be etched to form contact openings  162  on the top surface of each micro p-n diode  135 ,  150 . Contact openings  162  are illustrated in  FIGS. 10 ′- 10 ″ after removal of the patterned photoresist. As illustrated in  FIG. 10 ′, contact openings  162  may have a slightly smaller width than the top surface of the micro p-n diodes  135 ,  150 . The difference in width may be a result of adjusting for an alignment tolerance in patterning the photoresist. As a result, the conformal dielectric barrier layer  160  may form a lip around the top surface and sidewalls of the micro p-n diodes  135 ,  150 . As illustrated in  FIG. 10 ″, contact openings  162  may have a slightly larger width than the top surface of the micro p-n diodes  135 ,  150 . In the embodiment illustrated in  FIG. 10 ″ the contact openings  162  expose the top surfaces of the micro p-n diodes  150  and an upper portion of the sidewalls of the micro p-n diodes  150 , while the dielectric barrier layer  160  covers and insulates the quantum well layers  116 . 
     Referring now to  FIGS. 11A-11C , in accordance with some embodiments of the invention it is possible that an amount of bonding layer  210  wicks up along the side surfaces of the metallization layer  120  and along the bottom surface  151  of the p-n diode layer  110  during the bonding operation illustrated in  FIG. 3 . Referring to  FIG. 11B , it is possible that after forming the micro p-n diodes  150 , that the amount bonding layer  210  which has wicked up could potentially continue its migration along the sidewalls  153  of the micro p-n diode  150  during subsequent processing. Continued migration toward the quantum well layer  116  could interfere with the operation of the micro p-n diode  150 . Referring now to  FIG. 11C , in accordance with embodiments of the invention, the conformal dielectric barrier layer  160  may function as a physical barrier to protect the sidewalls  153  and quantum well layer  116  of the micro p-n diodes  150  from contamination by the bonding layer material  210  during subsequent temperature cycles (particularly at temperatures above the liquidus or melting temperature of the bonding layer material  210 ) such as during picking up the micro device from the carrier substrate, and releasing the micro device onto the receiving substrate. While  FIGS. 11A-11C  have been illustrated and described with reference to micro p-n diodes  150 , it is also contemplated that it is possible that an amount of bonding layer  210  could wick up and continue its migration along the sidewalls of micro mesas  130  used to form micro p-n diodes  135  during the bonding operation illustrated in  FIG. 3 . Conformal dielectric barrier layer  160  may similarly function as a physical barrier to protect the sidewalls and quantum well layer  116  of the micro p-n diodes  135  from contamination by the bonding layer material  210 . 
       FIGS. 12A-12B  include top and cross-sectional side view illustrations of a carrier substrate  201  and array of micro LED structures in accordance with an embodiment of the invention. In the particular embodiments illustrated, the arrays are produced from micro LED structures of Example 10′N including micro p-n diode  150 . However, it is to be appreciated that  FIGS. 12A-12B  are meant to be exemplary, and that the array of micro LED structures can be formed from any of the micro LED structures previously described. In the embodiment illustrated in  FIG. 12A , each individual micro p-n diode  150  is illustrated as a pair of concentric circles having different diameters or widths corresponding the different widths of the top and bottom surfaces of the micro p-n diode  150 , and the corresponding tapered sidewalls spanning between the top and bottom surfaces. In the embodiment illustrated in  FIG. 12B , each individual micro p-n diode  150  is illustrated as a pair of concentric squares with tapered or rounded corners, with each square having a different width corresponding to the different widths of the top and bottom surfaces of the micro p-n diode  150 , and the corresponding tapered sidewalls spanning from the top and bottom surfaces. However, embodiments of the invention do not require tapered sidewalls, and the top and bottom surfaces of the micro p-n diode  150  may have the same diameter, or width, and vertical sidewalls. As illustrated in  FIGS. 12A-12B  the array of micro LED structures is described as having a pitch (P), spacing (S) between each micro LED structure and maximum width (W) of each micro LED structure. In order for clarity and conciseness, only x-dimensions are illustrated by the dotted lines in the top view illustration, though it is understood that similar y-dimensions may exist, and may have the same or different dimensional values. In the particular embodiments illustrated in  FIGS. 12A-12B , the x- and y-dimensional values are identical in the top view illustration. In one embodiment, the array of micro LED structures may have a pitch (P) of 10 μm, with each micro LED structure having a spacing (S) of 2 μm and maximum width (W) of 8 μm. In another embodiment, the array of micro LED structures may have a pitch (P) of 5 μm, with each micro LED structure having a spacing (S) of 2 μm and maximum width (W) of 3 μm. However, embodiments of the invention are not limited to these specific dimensions, and any suitable dimension may be utilized. 
     An embodiment of a method of transferring a micro LED structure to a receiving substrate is described in  FIG. 13 . In such an embodiment a carrier substrate is provided having an array of micro LED structures disposed thereon. As described above, each micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer on the carrier substrate. A conformal dielectric barrier layer may optionally span sidewalls of the micro p-n diode. The conformal dielectric barrier layer may additionally span a portion of the bottom surface of the micro p-n diode, as well as sidewalls of the metallization layer, and bonding layer if present. Then at operation  1310  a phase change is created in the bonding layer for at least one of the micro LED structures. For example, the phase change may be associated with heating the bonding layer above a melting temperature or liquidus temperature of a material forming the bonding layer or altering a crystal phase of a material forming the bonding layer. The micro p-n diode and metallization layer, optionally a portion of the conformal dielectric barrier layer for at least one of the micro LED structures, and optionally a portion of bonding layer  210  may then be picked up with a transfer head in operation  1320  and then placed on a receiving substrate in operation  1330 . 
     A general illustration of operation  1320  in accordance with an embodiment is provided in  FIG. 14  in which a transfer head  300  picks up a micro p-n diode, metallization layer, a portion of the conformal dielectric barrier layer for at least one of the micro LED structures, and a portion of bonding layer  210 . In the particular embodiment illustrated a conformal dielectric barrier layer has been formed, however, in other embodiments a conformal dielectric barrier layer may not be present. In some embodiments a portion of bonding layer  210 , such as approximately half, may be lifted off with the micro LED structure. While a specific micro LED structure including micro p-n diode  150  is illustrated, it is understood than any of the micro LED structures including any of the micro p-n diodes  150  described herein may be picked up. In addition, while the embodiment illustrated in  FIG. 14  shows a transfer head  300  picking up a single micro LED structure, transfer head  300  may pick up a group of micro LED structures in other embodiments. 
     Still referring to  FIG. 14 , in the particular embodiment illustrated the bottom surface of the micro p-n diode  150  is wider than the top surface of the metallization layer  120 , and the conformal dielectric barrier layer  160  spans the sidewalls of the micro p-n diode  150 , a portion of the bottom surface of the micro p-n diode  150  and sidewalls of the metallization layer  120 . This may also apply for micro p-n diodes  135 . In one aspect, the portion of the conformal dielectric barrier layer  160  wrapping underneath the micro p-n diode  135 ,  150  protects the conformal dielectric barrier layer  160  on the sidewalls of the micro p-n diode  150  from chipping or breaking during the pick up operation with the transfer head  300 . Stress points may be created in the conformal dielectric barrier layer  160  adjacent the metallization layer  120  or bonding layer  210 , particularly at corners and locations with sharp angles. Upon contacting the micro LED structure with the transfer head  300  and/or creating the phase change in the bonding layer, these stress points become natural break points in the conformal dielectric barrier layer  160  at which the conformal dielectric layer can be cleaved. In an embodiment, the conformal dielectric barrier layer  160  is cleaved at the natural break points after contacting the micro LED structure with the transfer head and/or creating the phase change in the bonding layer, which may be prior to or during picking up the micro p-n diode and the metallization layer. As previously described, in the liquid state the bonding layer may smooth out over the underlying structure in response to compressive forces associated with contacting the micro LED structure with the transfer head. In an embodiment, after contacting the micro LED structure with the transfer head, the transfer head is rubbed across a top surface of the micro LED structure prior to creating the phase change in the bonding layer. Rubbing may dislodge any particles which may be present on the contacting surface of either of the transfer head or micro LED structure. Rubbing may also transfer pressure to the conformal dielectric barrier layer. Thus, both transferring a pressure from the transfer head  300  to the conformal dielectric barrier layer  160  and heating the bonding layer above a liquidus temperature of the bonding layer can contribute to cleaving the conformal dielectric barrier layer  160  at a location underneath the micro p-n diode  135 ,  150  and may preserve the integrity of the micro LED structure and quantum well layer. In an embodiment, the bottom surface of the micro p-n diode  135 ,  150  is wider than the top surface of the metallization layer  120  to the extent that there is room for the conformal dielectric barrier layer  160  to be formed on the bottom surface of the micro p-n diode  135 ,  150  and create break points, though this distance may also be determined by lithographic tolerances. In an embodiment, a 0.25 μm to 1 μm distance on each side of the micro p-n diode  135 ,  150  accommodates a 50 angstrom to 600 angstrom thick conformal dielectric barrier layer  160 . 
     A variety of suitable transfer heads can be utilized to aid in the pick up and placement operations  1320 ,  1330  in accordance with embodiments of the invention. For example, the transfer head  300  may exert a pick up pressure on the micro LED structure in accordance with vacuum, magnetic, adhesive, or electrostatic principles in order to pick up the micro LED structure. 
       FIG. 15  is a cross-sectional side view illustration of a bipolar micro device transfer head which operates according to electrostatic principles in order to pick up the micro LED structure in accordance with an embodiment of the invention. As illustrated, the micro device transfer head  300  may include a base substrate  302 , a mesa structure  304  including a top surface  308  and sidewalls  306 , an optional passivation layer  310  formed over the mesa structure  304  and including a top surface  309  and sidewalls  307 , a pair of electrodes  316 A,  316 B formed over the mesa structure  304  (and optional passivation layer  310 ) and a dielectric layer  320  with a top surface  321  covering the electrodes  316 A,  316 B. Base substrate  302  may be formed from a variety of materials such as silicon, ceramics and polymers which are capable of providing structural support. In an embodiment, base substrate has a conductivity between 10 3  and 10 18  ohm-cm. Base substrate  302  may additionally include wiring (not shown) to connect the micro device transfer heads  300  to the working electronics of an electrostatic gripper assembly. 
       FIG. 16  is an illustration of a receiving substrate  400  onto which a plurality of micro LED structures have been placed in accordance with an embodiment of the invention. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors, or a substrate with metal redistribution lines. In the particular embodiment illustrated, each micro LED structure may be placed over a driver contact  410 . A common contact line  420  may then be formed over the series of micro p-n diodes  135 ,  150 . As illustrated, the tapered sidewalls of the micro p-n diodes  135 ,  150  may provide a topography which facilitates the formation of a continuous contact line. In an embodiment, the common contact line  420  can be formed over a series of red-emitting, green-emitting or blue-emitting micro LEDs. In certain embodiments, the common contact line  420  will be formed from a transparent contact materials such as indium tin oxide (ITO). In one embodiment, the plurality of micro LEDs may be arranged into pixel groups of three including a red-emitting micro LED, green-emitting micro LED, and a blue-emitting micro LED. 
     Still referring to  FIG. 16 , a close up illustration of a p-n diode  135 ,  150  is provided in accordance with an embodiment of the invention. In one embodiment, the p-n diode  135 ,  150  may include a top n-doped layer  114  with a thickness of approximately 0.1 μm-3 μm, quantum well layer  116  (which may be SQW or MQW) with a thickness less than approximately 0.3 μm, and lower p-doped layer  118  with thickness of approximately 0.1 μm-1 μm. In an embodiment, top n-doped layer  114  may be 0.1 μm-6 μm thick (which may include or replace bulk layer  112  previously described). In a specific embodiment, p-n diodes  135 ,  150  may be less than 3 μm thick, and less than 10 μm wide. 
     In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming an array of micro LED structures which are poised for pick up and transfer to a receiving substrate. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.

Metadata:
Filing Date: 20140623
Publication Date: 20190521
Grant Date: 20190521
Priority Date: 20111118
Inventors: BIBL, ANDREAS
HIGGINSON, JOHN A.
LAW, HUNG-FAI STEPHEN
HU, HSIN-HUA
Assignee: APPLE INC
CPC Classifications: [{"code": "H01L2224/95", "inventive": false, "first": false, "tree": "[]"}, {"code": "F21V7/00", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2224/95", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L21/677", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L33/04", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L27/15", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L33/28", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L2224/95", "inventive": false, "first": false, "tree": "[]"}, {"code": "F21V7/00", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L33/06", "inventive": true, "first": true, "tree": "[]"}, {"code": "H01L33/30", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L33/20", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L33/0079", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L29/0684", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L25/0753", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10D62/124", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/819", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10H29/10", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/824", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/823", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/811", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/018", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10H20/812", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10H20/819", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10H20/819", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10H20/80", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10H20/018", "inventive": true, "first": true, "tree": "[]"}, {"code": "H10H20/018", "inventive": true, "first": true, "tree": "[]"}]
Family ID: 48094811