PATENT DOCUMENT

Publication Number: US-11087670-B2
Application Number: US-201815895248-A
Country: US
Kind Code: B2

Title: Electronic device display with monitoring circuitry utilizing a crack detection resistor

Abstract:
An electronic device may have a flexible display such as an organic light-emitting diode display. A strain sensing resistor may be formed on a bent tail portion of the flexible display to gather strain measurements. Resistance measurement circuitry in a display driver integrated circuit may make resistance measurements on the strain sensing resistor and a temperature compensation resistor to measure strain. A crack detection line may be formed from an elongated pair of traces that are coupled at their ends to form a loop. The crack detection line may run along a peripheral edge of the flexible display. Crack detection circuitry may monitor the resistance of the crack detection line to detect cracks. The crack detection circuitry may include switches that adjust the length of the crack detection line and thereby allow resistances to be measured for different segments of the line.

Claims:
What is claimed is: 
     
       1. A display system, comprising:
 a flexible display having pixels; 
 a crack detection resistor that runs along a peripheral edge of the flexible display, wherein the crack detection resistor has parallel first and second lines along the peripheral edge and has a plurality of bridging resistances located at respective locations along the peripheral edge of the flexible display, wherein the crack detection resistor has first and second ends with first and second respective terminals, wherein each of the bridging resistances is coupled between the first line and the second line, wherein each of a first plurality of the bridging resistances has a first resistance and is coupled between the first and second lines along a first side of the pixels and wherein each of a second plurality of the bridging resistances is coupled between the first and second lines along a second side of the pixels and has a second resistance that is different than the first resistance; and 
 measurement circuitry coupled to the flexible display that is configured to make measurements on the crack detection resistor to determine a location of a crack in the first and second lines of the crack detection resistor based on the first and second resistances and a change in total resistance between the first and second terminals. 
 
     
     
       2. The display system defined in  claim 1  wherein the first and second lines comprise a metal that corrodes upon exposure to moisture. 
     
     
       3. The display system defined in  claim 1  wherein the first and second lines comprise silver. 
     
     
       4. The display system defined in  claim 1  wherein the pixels comprise anodes formed from a layer of anode metal and wherein the first and second lines comprise portions of the layer of anode metal. 
     
     
       5. The display system defined in  claim 1  wherein the pixels are formed from thin-film transistor circuitry and wherein the first and second lines include lines formed from a source-drain metal layer in the thin-film transistor circuitry. 
     
     
       6. A display system, comprising:
 a flexible display having pixels and a bent tail portion that extends away from the pixels; 
 a crack detection resistor that runs along a peripheral edge of the flexible display and that extends into a central strip in the bent tail portion, wherein the crack detection resistor includes a first line with a first pair of terminals and a second line with a second pair of terminals; 
 first and second pluralities of data lines for the flexible display, wherein the central strip is interposed between the first and second pluralities of data lines; and 
 resistance measurement circuitry configured to make a first resistance measurement between the first pair of terminals to detect a presence of a crack in the first and second lines and to form a short circuit between the second pair of terminals and make a second resistance measurement to determine a location of the crack in response to detecting the crack. 
 
     
     
       7. The display system defined in  claim 6  wherein the first and second lines are parallel and are coupled by a series of bridging paths. 
     
     
       8. The display system defined in  claim 6  further comprising a display driver integrated circuit that supplies data to columns of the pixels over the first and second pluralities of data lines. 
     
     
       9. The display system defined in  claim 8  wherein the resistance measurement circuitry is in the display driver integrated circuit. 
     
     
       10. The display system defined in  claim 6  wherein the first and second lines have straight portions that run along the peripheral edge and have non-straight portions in the bent tail portion. 
     
     
       11. The display system defined in  claim 10  wherein the bent tail portion has a first width, wherein the central strip has a second width, and wherein the second width is less than 20% of the first width. 
     
     
       12. The display system defined in  claim 6  wherein the pixels are formed from thin-film transistor circuitry including at least first and second metal layers and wherein the crack detection resistor has first and second parallel lines in the central strip that are formed from the first metal layer. 
     
     
       13. The display system defined in  claim 6  wherein the pixels are formed from thin-film transistor circuitry including at least first and second metal layers and wherein the crack detection resistor has first and second lines in the central strip that are formed from portions of the first metal layer and from portions of the second metal layer. 
     
     
       14. A display system, comprising:
 a display having pixels; 
 first and second concentric paths that run along a peripheral edge of the display; and 
 a first resistance measurement circuit coupled to the first path and a second resistance measurement circuit coupled to the second path, wherein the first resistance measurement circuit is configured to make a first measurement to detect a presence of a crack in both of the first and second concentric paths when the second resistance measurement circuit is in an open circuit state, wherein the second resistance measurement circuit is decoupled from the second path in the open circuit state, and wherein the first resistance measurement circuit is configured to make a second measurement when the second resistance measurement circuit is in a closed circuit state to determine a location of the crack in response to detecting the presence of the crack. 
 
     
     
       15. The display system defined in  claim 14 , further comprising:
 resistive paths that couple the first path to the second path, wherein each resistive path couples the first path to the second path at a different respective location along the first and second paths. 
 
     
     
       16. The display system defined in  claim 15  wherein the first resistance measurement circuit measures the resistance of the first path to determine a location of a crack in the first path and the second resistance measurement circuit measures the resistance of the second path to determine a location of a crack in the second path. 
     
     
       17. The display system defined in  claim 14  wherein the first path is interposed between the second path and the pixels. 
     
     
       18. The display system defined in  claim 17  further comprising:
 a third concentric path that runs along the peripheral edge of the display, wherein the second path is interposed between the first path and the third path.

Description:
This application claims the benefit of provisional patent application No. 62/377,483, filed Aug. 19, 2016, and is a continuation-in-part of patent application Ser. No. 15/275,109, filed Sep. 23, 2016, which are hereby incorporated by reference herein in their entireties. 
    
    
     BACKGROUND 
     This relates to electronic devices, and more particularly, to electronic devices with displays. 
     Electronic devices are often provided with displays. For example, cellular telephones, computers, and wristwatch devices may have displays for presenting images to a user. 
     Displays such as organic light-emitting diode displays may have flexible substrates. This allows portions of the display to be bent. The tail of a display may, for example, be bent when mounting the display in a compact device housing. 
     Challenges can arise in providing electronic devices with bent flexible displays. If care is not taken, mishandling during fabrication or stress due to drop events may damage the display. 
     SUMMARY 
     An electronic device may have a display mounted in a housing. The display may be a flexible display such as an organic light-emitting diode display. The display may have an array of pixels and a bent tail portion. The bent tail portion may bend about a bend axis. A display driver integrated circuit may supply data to columns of the pixels using data lines that extend across the bent tail portion. The display driver circuit may be coupled to the bent tail portion through a flexible printed circuit. A gate driver circuit may supply control signals to rows of the pixels using gate lines. 
     A strain sensing resistor may be formed on the bent tail portion of the flexible display to gather strain measurements. A temperature compensation resistor may be located adjacent to the strain sensing resistor. The strain sensing resistor and temperature compensation resistor may be formed from meandering metal traces. The meandering traces of the strain sensor may run perpendicular to the bend axis. The meandering traces of the temperature compensation resistor may run parallel to the bend axis. Resistance measurement circuitry in the display driver circuit may be used to measure the resistance of the strain sensing and temperature compensation resistors. Strain measurements may be obtained by subtracting the temperature compensation resistance from the strain sensing resistance. 
     A crack detection line may be formed from an elongated pair of traces that are coupled to form a loop. The crack detection line may run along the peripheral edge of the flexible display. Crack detection circuitry in the display driver integrated circuit may monitor the resistance of the crack detection line to detect cracks. If no cracks are present, crack detection line resistance will be low. In the presence of a crack, the resistance of the crack detection line will become elevated. 
     A shift register in the gate driver circuit may be provided with switches. The switches may be positioned at various positions along the length of the crack detection line and may be selectively closed to shorten the length of the signal path in the crack detection line by various amounts. By closing the switches in sequence while simultaneously measuring the resulting resistances of the crack detection line, the resistance of each of a plurality of segments of the crack detection line can be determined. This allows the positions of cracks within the crack detection line to be identified. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional side view of an illustrative electronic device in accordance with an embodiment. 
         FIG. 2  is a top view of an illustrative flexible display with strain gauge monitoring resistors in accordance with an embodiment. 
         FIG. 3  is a top view of a portion of a flexible display with strain gauge resistors in accordance with an embodiment. 
         FIG. 4  is a cross-sectional side view of a portion of a flexible display with metal traces in accordance with an embodiment. 
         FIGS. 5, 6, and 7  are circuit diagrams illustrative strain gauge circuits in accordance with an embodiment. 
         FIG. 8  is a diagram of an illustrative display with crack detection monitoring circuitry in accordance with an embodiment. 
         FIG. 9  is a diagram of an illustrative resistance measurement circuit that may be used to detect cracks in accordance with an embodiment. 
         FIG. 10  is a diagram of an illustrative display with crack detection monitoring circuitry in accordance with an embodiment. 
         FIG. 11  is a cross-sectional side view of an illustrative display with crack detection circuitry in accordance with an embodiment. 
         FIG. 12A  is a diagram of illustrative crack monitoring circuitry in accordance with an embodiment. 
         FIGS. 12B and 12C  show illustrative capacitors for the circuitry of  FIG. 12A  in accordance with embodiments. 
         FIG. 13A  is a diagram of an illustrative display with a crack detection resistor having parallel paths that extend into a central strip in a tail portion of the display in accordance with an embodiment. 
         FIG. 13B  shows illustrative non-straight metal trace patterns that may be used for the parallel lines of the crack detection resistor in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     An electronic device such as electronic device  10  of  FIG. 1  may be provided with a flexible display having monitoring circuitry. The monitoring circuitry may include strain gauge monitoring circuitry for monitoring strain in the bent portion of a display and may include peripheral crack monitoring circuitry. The strain gauge monitoring circuitry may include strain gauge resistors on a bent portion of the flexible display and a strain gauge circuit that monitors for resistance changes arising when stress is applied to the bent portion of the flexible display. The peripheral crack monitoring circuitry may have a peripheral crack detection line formed from a loop-shaped signal path with two parallel metal traces that runs along the periphery of the active area of the display. A crack detection circuit may use resistance monitoring circuitry to measure resistance changes in one or more segments of the crack detection line that are indicative of cracking in the line and in structures elsewhere in the display. 
     Electronic device  10  may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wristwatch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user&#39;s head, or other wearable or miniature device, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, equipment that implements the functionality of two or more of these devices, or other electronic equipment. In the illustrative configuration of  FIG. 1 , device  10  is a portable device such as a wristwatch. Other configurations may be used for device  10  if desired. The example of  FIG. 1  is merely illustrative. 
     Device  10  may have a display such as display  14 . Display  14  may be mounted on the front face of device  10  in housing  12 . Housing  12 , which may sometimes be referred to as an enclosure or case, may be formed of plastic, glass, ceramics, fiber composites, metal (e.g., stainless steel, aluminum, etc.), other suitable materials, or a combination of any two or more of these materials. Housing  12  may be formed using a unibody configuration in which some or all of housing  12  is machined or molded as a single structure or may be formed using multiple structures (e.g., an internal frame structure, one or more structures that form exterior housing surfaces, etc.). Housing  12  may have metal sidewalls or sidewalls formed from other materials, 
     Display  14  may be a touch screen display that incorporates a layer of conductive capacitive touch sensor electrodes or other touch sensor components (e.g., resistive touch sensor components, acoustic touch sensor components, force-based touch sensor components, light-based touch sensor components, etc.) or may be a display that is not touch-sensitive. Capacitive touch screen electrodes may be formed from an array of indium tin oxide pads or other transparent conductive structures. 
     Display  14  may include an array of display pixels formed from liquid crystal display (LCD) components, an array of electrophoretic display pixels, an array of plasma display pixels, an array of organic light-emitting diode display pixels, an array of electrowetting display pixels, or display pixels based on other display technologies. Configurations in which display  14  includes organic-light-emitting diode structures may sometimes be described herein as an example. 
     Display  14  may have a thin flexible display layer (sometimes referred to as a pixel array, display, or flexible display) such as flexible display  22 . Flexible display  22  may be formed from thin-film circuitry (e.g., thin-film transistors, thin-film organic light-emitting diodes, etc.) on a polymer substrate such as a flexible polyimide substrate. The thin-film circuitry may be encapsulated using one or more encapsulation layers (e.g., moisture barrier layers formed from organic and/or inorganic films). A transparent protective layer such as display cover layer  20  may overlap flexible display  22 . Cover layer  20  may be formed from transparent glass, clear polymer, sapphire or other crystalline material, ceramic, or other transparent protective layer. 
     Flexible display  22  may have an array of pixels  24  (pixel array  22 A) that form an active area for displaying images. Flexible display  22  may also have an inactive tail region such as tail  22 T that is free of pixels  24 . Images may be displayed for a user in pixel array  22 A by pixels  24 . Pixels  24  may be, for example, organic light-emitting diode pixels formed on a flexible polymer substrate (e.g., a polyimide substrate) and may be formed from thin-film circuitry on the substrate. 
     Metal traces such as metal traces  30  in flexible display  22  (e.g., data lines, control lines, etc.) may couple the circuitry of pixel array  22 A with display driver circuitry such as display driver circuitry in display driver integrated circuit  42 . In the example of  FIG. 1 , circuit  42  has been mounted on flexible printed circuit  32  and flexible printed circuit  32  has been coupled to flexible display  22 . With this arrangement, display driver integrated circuit  42  may be coupled to pixel array  22 A using metal traces  36  in flexible printed circuit  32  and metal traces  30  in flexible display  22 . Metal traces  36  in flexible printed circuit  32  may be soldered to contact pads on integrated circuit  42 . Metal traces  36  and metal traces  30  may also form mating pads that are coupled together at bonds  34 . Bonds  34  may be anisotropic conductive film bonds or other conductive connections. If desired, display driver circuitry such as display driver circuitry  42  may be coupled to pixel array  22 A with other arrangements. The use of flexible printed circuit  32  to couple circuit  42  to display  22  is merely illustrative. 
     Flexible display  22  may have a bent portion such as bent portion  26  that bends about bend axis  28 . The inclusion of bent portion  26  in display  22  may help display  22  fit within housing  12 . Display driver integrated circuit  42  may be coupled to system circuitry such as components  48  on one or more additional printed circuits such as printed circuit  46 . Components  48  may include storage and processing circuitry for controlling the operation of device  10 . Components  48  may be coupled to display driver circuit  42  and display  22  using connectors  45  (e.g., board-to-board connectors). 
     The bending of display  22  may create stress for traces  30 . If mishandled during assembly or if subjected to stress from a drop event, there is a risk that traces  30  could become damaged. To help characterize the stresses to which display  22  is subjected, display  22  may be provided with strain monitoring circuitry. The strain monitoring circuitry may include, for example, strain gauge resistors on bent portion  26  of display  22 . Crack monitoring circuitry may also be included in flexible display  22  (e.g., peripheral crack detection lines may run along one or more of the edges of pixel array  22 A or other portions of display  22 ). 
     The monitoring circuitry may include resistors (strain gauge resistors, peripheral lines that have associated resistances, etc.) and circuitry for evaluating the resistances associated with the resistors. The resistors may be incorporated into sensitive portions of display  22  (e.g., bent portion  26 , the edges of pixel array  22 A, etc.). 
     The circuitry for measuring and evaluating the resistances may be formed in display driver integrated circuit  42 , in other display driver circuitry (e.g., thin-film gate driver circuitry or gate driver integrated circuits on the edges of pixel array  22 A), or may be formed using components  48 . If desired, probe pads  38  may be formed on printed circuit  32  and/or on display  22  and these probe pads may be contacted by probes associated with test equipment. The test equipment may include resistance monitoring circuitry for monitoring resistance changes in strain gauge resistors and/or crack detection line resistance changes. Test equipment may also be coupled to the circuitry of display  22  using connector  45  or other coupling techniques (e.g., to monitor strain gauge resistors and/or crack detection resistors). During testing, test equipment may use electrically controlled actuators or other equipment to automatically apply stress to display  22  (e.g., to bend display  22  in region  26 ) and/or may otherwise manipulate display  22  while gathering data from monitoring structures in display  22 . With this type of testing arrangement, the tester may, for example, direct the actuators to apply known amounts of stress to display  22  in bent portion  26  or other region of display  22  while using the strain gauge resistors or other monitoring sensors to gather corresponding measurements (e.g., strain gauge measurements). Configurations in which resistance measurement circuitry and other monitoring circuitry is incorporated into display driver integrated circuit  42  (see, e.g., resistance measurement circuitry such as circuit  44  in display driver integrated circuit  42  of  FIG. 2 ) so that strain measurements and crack detection measurements may be made during fabrication or during normal use of device  10  by a user may sometimes be described herein as an example. 
       FIG. 2  is a top view of flexible display  22  in an unbent configuration. As shown in  FIG. 2 , pixel array  22 A may include rows and columns of pixels  24 . Gate driver circuitry (e.g., thin-film gate driver circuitry running along the left and/or right edges of pixel array  22 A) may supply horizontal control signals to each row of pixels  24 . These horizontal control signals, which may sometimes be referred to as gate line signals, may be used to control switching transistor in the pixel circuits associated with pixels  24  (e.g., for data loading, threshold voltage compensation operations, etc.). During data loading operations, data signals from display driver integrated circuit  42  may be supplied to columns of pixels  24  via respective data lines D. 
     Tail portion  22 T of flexible display  22  may bend around bend axis  28 . Strain gauge monitoring structures such as strain gauge resistors R 1  and R 2  and associated strain gauge circuitry in display driver integrated circuit  42  such as resistance measurement circuit  44  may be may be used in monitoring strain in tail portion  22 T and may form a strain gauge that can gather real time strain gauge measurements. 
     The strain gauge may include one or more strain-sensing (strain-sensitive) resistors such as resistors R 1 . Resistors R 1  may contain meandering metal traces that change resistance when bent. Resistors R 1  may be placed on tail  22 T in a location that overlaps bend axis  28 , so that resistance changes in resistors R 1  due to bending of display  22  in tail region  22 T may be maximized. 
     The strain gauge may also include one or more temperature compensation strain gauge resistors such as temperature compensation resistors R 2  (sometimes referred to as reference strain gauge resistors). Resistors R 2  may have meandering metal trace that match those of resistors R 1  so that both resistors R 1  and resistors R 2  experience the same responses to changes in operating temperature. Resistors R 2  may be placed on tail  22 T at locations that do not overlap bend axis  28  and may be oriented so that the traces in resistors R 2  run perpendicular to the traces in resistors R 1 . As a result, resistors R 1  will change resistance when tail  22 T is bent about axis  28 , but resistors R 2  will not change resistance when tail  22 T is bent about axis  28 . This allows resistance measurements made with a reference resistor R 2  to be subtracted from resistance measurements made with a strain-sensing resistor R 1  to remove temperature-dependent effects from the strain gauge resistance measurements (e.g., to remove noise due to temperature fluctuations). 
     In the example of  FIG. 2 , display  22  has been provided with two sets of strain gauge resistors. A left-hand set (formed from a first strain-sensing resistor R 1  overlapping bend axis  28  and a first associated temperature compensation resistor R 2 ) may be located along the left-hand edge of tail  22 T and may measure strain along the left side of tail  22 T. A right-hand set (formed from a second strain-sensing resistors R 1  overlapping bend axis  28  and a second associated temperature compensation resistor R 2 ) may be located along the right-hand edge of tail  22 T and may measure strain along the right side of tail  22 T. By including strain measurement circuitry along both the right and left edges of tail  22 T, strain data may be gathered that is sensitive to situations in which tail  22 T is bent unevenly along the left and right of tail  22 T (e.g., situations in which tail  22 T is twisted). 
     An illustrative trace layout for resistors R 1  and R 2  is shown in  FIG. 3 . As shown in  FIG. 3 , resistors R 1  and R 2  may have meandering paths formed from metal traces or other elongated conductive lines  50 . There may be any suitable number of parallel elongated lines in each resistor (e.g., more than 5 lines, 10-100 lines, 20-50 lines, more than 20 lines, fewer than 200 lines, fewer than 150 lines, etc.). The width of the metal traces forming lines  50  may be 2-10 microns, 4-8 microns, more than 3 microns, less than 20 microns, or other suitable width. The length of the sides of each resistor may be, for example, more than 0.05 mm, more than 0.1 mm, more than 0.5 mm, less than 1 mm, or less than 2 mm, etc. Resistors R 1  and R 2  may be rectangular or may have other shapes. Lines  50  in resistor R 1  may extend perpendicular to bend axis  28  (e.g., along dimension Y which is aligned with the longitudinal axis of tail  22 T) to maximize bending of lines  50  and therefore changes in the resistance of R 1  when tail  22 T is bent. Lines  50  in temperature compensation resistor R 2  may be parallel to lines  50  in resistor R 1  or may be arranged parallel to bend axis  28  as shown in  FIG. 3  to help reduce the sensitivity of resistor R 2  to changes in the bending of tail  22 T. 
     A cross-sectional side view of a portion of tail portion  22 T of display  22  is shown in  FIG. 4 . As shown in  FIG. 4 , tail portion  22 T may have a substrate such as substrate  52 . Substrate  52  may be formed from a flexible polymer such as a layer of polyimide. Metal traces  54  may be formed on substrate  52  and may be covered with planarization layer  56 . Metal traces  58  may be formed on planarization layer  56  and may be covered with planarization layer  60 . In pixel array  22 A, metal traces  54  and  58  may be used in forming thin-film transistor structures (e.g., source-drain terminals) and signal lines. In inactive tail portion  22 T of display  22 , metal traces  54  and  58  may form control signal lines and data lines D for carrying data from display driver integrated circuit  42  to pixels  24  in pixel array  22 A. Planarization layers  56  and  60  may be formed from polymers or other suitable materials. Polymer layer  62  may serve as a neutral stress plane adjustment layer that helps move the neutral stress plane of tail  22 T into alignment with traces  54  to minimize stress-induced cracking in traces  54  when tail  22 T is bent. With this type of configuration, traces  58  may (as an example) experience more stress than traces  54  when tail  22 T is bent. Accordingly, it may be desirable to form lines  50  for resistors R 1  and R 2  from the same metal layer that is used in forming lines  58  to maximize strain gauge sensitivity. Other layers of conductive material in display  22  may be patterned to form strain gauge resistors if desired. The use of the metal layer that is used in forming traces  58  to form strain gauge resistors is merely illustrative. 
     An illustrative strain gauge circuit is shown in  FIG. 5 . Resistance measurement circuitry  44  may be formed in display driver integrated circuit  42  (as an example) and may be coupled to resistors R 1  and R 2  on tail portion  22 T using metal traces  36  in flexible printed circuit  32  and traces  30  in display  22 . Bonds  34  between the pads formed from traces  36  and  30  and the portions of traces  30  and  36  that carry signals between resistors R 1  and R 2  and circuit  44  (shown collectively as paths  70 ) may have associated resistances Rc. For accurate strain gauge measurements, resistances Rc should be subtracted out of the strain gauge resistance measurements. Resistance changes in resistor R 1  that are due to changes in temperature and not changes in strain can be measured using temperature compensation resistor R 2  and can be subtracted from the measured resistance of resistor R 1 . 
     During operation, current source  64  may apply a known current I between terminals A and B. This causes current I to flow through resistors R 1  and R 2 , which are coupled in series between terminals A and B. Voltage sensor  66  may measure the resulting voltage V 1  between terminals C and D and voltage sensor  68  may measure the resulting voltage V 2  between terminals D and E. The resistance of resistor R 1  is equal to V 1 /I and the resistance of resistor R 2  is V 2 /I. Resistances R 1  and R 2  are therefore independent of the value of resistance Rc associated with bonds  34 . The resistance values for resistors R 1  and R 2  may be determined by resistance measurement circuitry (e.g., using a processor circuit in circuitry  44 ) based on the known value of I and the measured values of V 1  and V 2 . The processor circuitry may also subtract R 2  from R 1  to isolate changes in resistance R 1  that are due to changes in the strain on resistor R 1  (e.g., bending of lines  50  about axis  28 , which can narrow lines  50  and thereby increase the resistance of lines  50 ). The measured changes in resistance R 1  due to strain may be used as strain gauge measurements that reflect the amount of strain experienced by tail portion  22 T in bend region  26 . 
     The availability of contact pads on tail portion  22 T may be limited due to the limited amount of area available on tail portion  22 T. It may therefore be desirable to couple terminals A and B to pads that are coupled to other lines in display  22  such as lines  72 . Lines  72  may be, for example, positive power supply lines (e.g., lines that carry a positive power supply voltage Vdd to pixels  24  during normal operation of display  22 ). By piggybacking the measurement signals for measuring R 1  and R 2  through these contact pads, pad count can be minimized. 
       FIG. 6  shows how lines  72  may be omitted, if desired. 
     The number of pads used to measure resistances R 1  and R 2  may, if desired, be minimized using a resistance measurement arrangement of the type shown in  FIG. 7 . With this arrangement, resistance measurement circuitry  44  may measure the resistance RM 1  between terminals P 1  and P 2  and may measure the resistance RM 2  between terminals P 2  and P 3 . Resistor R 1  or R 2  may be coupled between terminals F and G (e.g., separate circuits of the type shown in  FIG. 7  may be used for measuring R 1  and for measurement R 2 ). After measuring RM 1  and RM 2 , resistance measurement circuitry  44  can compute the value of the resistance between terminals F and G (either R 1  or R 2  depending on which strain gauge resistor is coupled between terminals F and G) by subtracting RM 2  from RM 1 . This cancels out resistance Rc so that the measured strain gauge resistance values are independent of bond resistance. 
     In addition to measuring strain in display  22 , display  22  may incorporate crack detection circuitry. With one illustrative configuration, which is shown in  FIG. 8 , a crack detection line such as crack detection line  80  may run along some or all of the peripheral edge of display  22 . Crack detection line  80  may be formed from metal (e.g., part of one of the metal layers used in forming pixels  24  such a gate metal layer, source-drain metal layer, anode metal layer, cathode metal layer, etc.). Crack detection line  80  may also be formed from semiconductor (e.g., polysilicon or semiconducting oxide) or other conductive material. Illustrative configurations in which crack detection line  80  is formed from metal traces may sometimes be described herein as an example. 
     Crack detection line  80  may have a loop shape formed from outgoing line  80 - 1 , end connection path  80 - 2 , and return line  80 - 3  (i.e., a metal trace that is parallel to the metal trace forming path  80 - 2 ). This allows line  80  to serve as a crack detection resistor. In the absence of damage to display  22 , line  80  will be free of cracks and will be characterized by a low resistance. In the event that display  22  is subjected to stress that forms cracks in pixels  24  or other display circuity, crack detection line  80 , which is subjected to the same stress, will also develop cracks. The presence of cracks in crack detection line  80  will raise the resistance of line  80 . The change in the resistance of line  80  can detected by crack detection circuitry  44  in display driver circuit  42  (or external crack detection circuitry in a tester, etc.). The crack detection circuitry can then report this result to circuit components  48  (e.g., control circuitry in device  10 ), may report this result to external equipment, or may present warnings on display  22  (as examples). 
     If desired, the crack detection circuitry for display  22  may measure the resistance of individual segments SG of line  80  such as segments SG 1 , SG 2 , . . . SGN. As shown in  FIG. 8 , the display driver circuitry of display  22  may include gate driver circuitry  90 . Gate driver circuitry  90  may receive control signals (e.g., clock signals, start and stop pulses, etc.) from display driver circuit  42  via path  92 . Gate driver circuitry  90  may contain a shift register formed from a chain of register circuits  84 . Register circuits  84  may each supply horizontal control signals (e.g., scan signals, emission enable signals, etc.) to a corresponding row of pixels  24  (e.g., signals on illustrative gate lines G). During operation, circuit  42  initiates propagation of a control pulse through the shift register. As the control pulse propagates through the shift register, each gate line G (or other set of control signals) is activated in sequence, allowing successive rows of pixels  24  to be loaded with data from data lines D. 
     Gate driver circuitry  90  (e.g., some of register circuits  84 ) may be provided with switches SW 1 , SW 2 , . . . SWN, each of which selectively creates a short between lines (parallel metal traces)  80 - 1  and  80 - 3  at a different respective location along the length of line  80 . As the control pulse propagates through the shift register, each of switches SW 1 , SW 2 , . . . SWN is activated in sequence. As each switch is closed, resistance measurement circuitry  44  may measure the resistance of line  80 . When switch SW 1  is closed, line  80  is shorted at switch SW 1  and circuit  44  measures the resistance of segment SG 1  of line  80 . When switch SW 2  is closed, line  80  is shorted at switch SW 2  and circuit  44  measures the resistance of segments SG 1  and SG 2  together. This process continues until all switches have been closed and circuit  44  measures the resistance of all segments of line  80  (i.e., the entire length of line  80  from circuit  44  to connection path  80 - 2 ). Using these resistance measurements, the resistance of each individual segment can be determined by resistance measurement circuit  44 . These resistance measurements can then be processed by the resistance measurement circuitry to determine whether the resistance of any segment is sufficiently high to reveal the presence of a crack. 
     Any suitable technique may be used by measurement circuitry  44  to measure the resistance of line  80 . For example, resistance measurement circuitry  44  may measure the resistance of line  80  by applying a known voltage to a capacitor of known capacitance C and discharging that capacitor through line  80  while incrementing a counter or otherwise timing the decay time (RC time) associated with discharging the capacitor. The RC time can then be used to extract a measured resistance value R. 
     Consider, as an example, a resistance measurement circuit such as illustrative resistance measurement circuitry  44  of  FIG. 9 . As shown in  FIG. 9 , resistance measurement circuitry  44  of display driver integrated circuit  42  may be coupled to crack detection line (resistor)  80  in display panel  22  (see, e.g., line  80  of  FIG. 8 ). Resistance measurement circuitry  44  may make measurements of the resistance of line  80  while switches  84  ( FIG. 8 ) are opened and closed so that segments of line  80  can be monitored for the presence of cracks. 
     Resistance measurement circuitry  44  may have an integrator such as integrator  100 . Integrator  100  may have a capacitor such as capacitor  104  and an operational amplifier such as operational amplifier  106 . The input of integrator  100  is coupled to line  80  and can be used to receive current that passes through reference resistor Rref or line  80  (of unknown resistance R) from reference voltage source Vref. 
     Clock  116  may supply clock signals to control logic  112  and counter  114 . The clock signals may be used to increment a count value maintained by counter  114 . When it is desired to perform a resistance measurement with integrator  100 , control logic  112  may assert a control signal that closes switch  102 . Switch  102 , which may sometimes be referred to as an integrator reset switch, is coupled across capacitor  104  and discharges capacitor  104  when closed. While discharging capacitor  104  to reset integrator  100 , control logic  112  may also clear counter  114 . 
     When making resistance measurements, control logic  112  may place resistance selection switch  108  in either a first state in which voltage Vref is coupled to integrator  100  via resistor Rref or a second state in which voltage Vref is coupled to integrator  100  via resistor (resistance) R. In the first state, a current equal to Vref/Rref flows into integrator  100 . In the second state, a current equal to Vref/R flows into integrator  100 , where R is the resistance of the currently selected segment SG of line  80  that is being measured. 
     During integration operations, switch  102  is placed in its open state and the voltage on capacitor  104  rises in proportion to the current flowing into integrator  100 . The output of amplifier  106 , which serves as the output of integrator  100 , may be supplied to a first input of comparator  110 . A second input of comparator  110  may be provided with reference voltage V 0 . Comparator  110  may compare the signals on its first and second inputs and may produce corresponding output signals at its output. 
     When the output from integrator  100  exceeds V 0 , the output of comparator  110  will change state (i.e., the output of comparator  110  will toggle). The change in state of the output of comparator  110  may be detected by control logic  112 . In response to detection of the change of state of the comparator output, control logic  112  can obtain the current count value of counter  114 . This count value is proportional to the magnitude of the current being integrated by integrator  100 . The amount of time taken to charge the integrator output to V 0  (the count value of counter  114 ) can be measured by control logic  112  in both the first state of resistor selection switch  108  (in which current Vref/Rref flows into integrator) and in the second state of resistor selection switch  108  (in which current Vref/R flows into integrator  100 ). Control logic  112  may then obtain the unknown value of resistance R from the count value obtained when switch  108  is in the first state and the count value obtained when switch  108  is in the second state. 
     Strain resistor measurements (e.g., strain data from strain sensor resistor R 1 ) and/or crack detection resistor measurements (e.g., crack detection data such as measured resistance R from line  80 ) may be gathered during testing and analyzed to determine whether design changes should be made. Strain and crack detection measurements may be gathered by a tester having test probes that are coupled to pads in display  22  or pads in flexible printed circuit  32  and/or may be gathered by a tester that obtains digital measurements from resistance measurement circuitry  44  over a digital data communications path. Strain and crack measurements may be gathered during manufacturing to detect damaged parts so that they can be repaired or replaced. If desired, strain and crack data can be gathered during normal operation of device  10 . Any suitable action may be taken in response to abnormal strain or crack data. For example, an alert may be presented on display  22  that informs a user that display  22  has been subjected to potentially damaging amounts of stress and should be serviced, historical data can be gathered (e.g., to detect whether device  10  has been dropped), and/or other actions may be taken in response to gathered strain and crack detection information. These alert techniques may also be used during testing and manufacturing. 
     As shown in  FIG. 10 , display  22  may be provided with two or more concentric rings (e.g., parallel lines formed from metal traces that make up a crack detection resistor) such as paths  80 A and  80 B. Optional paths forming bridging resistances RB 1  may be located between paths  80 A and  80 B along the left peripheral edge of display  22  and optional bridging resistances RB 2  may be located between paths  80 A and  80 B along the right peripheral edge of display  22 . One or more bridging resistances (e.g., metal trace paths) may also be formed along the upper edge of display  22 . 
     Resistance measurement circuit M 1  in resistance measurement circuitry such as resistance measurement circuit  44  may measure the resistance between terminals  122  and  124  and an optional separate measurement circuit such as circuit M 2  may be coupled between terminals  126  and  128 . If desired circuit M 2  may be omitted, bridging resistances RB 1  and RB 2  may be omitted, and path  80 A may be shorted to path  80 B using optional shorting paths  120 . There are two concentric paths in the monitoring circuit of  FIG. 10 , but additional concentric may be formed along the edge of display  22  if desired (as illustrated by dots  130 ). 
     When shorting paths  120  are present, outer peripheral crack detection path  80 B and inner peripheral crack detection path  80 A are electrically coupled. In this type of arrangement, measurement circuit M 1  may be used to simultaneously monitor paths  80 A and  80 B for changes in resistance. If no cracks are present, the resistance between terminals  122  and  124  will have a first resistance value. If a crack is present that penetrates outer path  80 B but not inner path  80 A, the first resistance value will rise to a second resistance that is larger than the first resistance. The presence of a crack that passes through outer path  80 B and inner path  80 A will create a higher third resistance between terminals  122  and  124  (e.g., an open circuit resistance). 
     In arrangements in which bridging resistances such as resistances (coupling paths) RB 1  and RB 2  are coupled between outer path  80 B and inner path  80 A, crack location information can be determined from measured resistance information. The measured resistance between nodes  122  and  124  will, for example, be different if a crack is present in path  80 B at location  132  than if the crack is present in path  80 B at location  134  (e.g., in a different segment of path  80 B). If RB 1  and RB 2  are equal, the distance of the crack along the peripheral edge of display  22  can be determined from the resistance measurement. If RB 1  and RB 2  are different, the resistance network formed from paths  80 A,  80 B, and the paths associated with resistances RB 1  and RB 2  will be asymmetric (different on the left and right). As a result, the measured resistance between nodes  122  and  124  will correspond to a unique crack location. For example, the measured resistance will be different when a crack is present at location  134  (e.g., a given distance from circuit M 1  along the left edge of display  22 ) than when a crack is present at location  136  (e.g., the same given distance from circuit M 1  along the right edge of display  22 ). 
     When shorting paths  120  are present and circuit  44  contains only measurement circuit M 1  and not circuit M 2 , the presence of a crack that passes through both paths  80 B and  80 A will create an open circuit between nodes  122  and  124 . As a result, it will not be possible to determine the location of the crack along the periphery of display  22 . To determine crack location in scenarios in which a crack passes through both outer path  80 B and inner path  80 A, circuit  44  can be provided with both measurement circuits M 1  and M 2 , as shown in  FIG. 10 . Paths  120  can be omitted. With this type of arrangement, circuit M 2  may be open circuited while circuit M 1  measures the resistance of the crack detection resistor formed by coupled lines  80 A and  80 B. In the event that a crack is present that passes through both line  80 B and line  80 A, an open circuit resistance will be detected by circuit M 1 . Measurement circuit M 2  may then be placed in a short circuit state (shorting terminals  126  and  128  together) while measurement circuit M 1  measures the resistance between terminals  126  and  128 . The presence of the short circuit formed by circuit M 2  allows peripheral path resistance to be measured by circuit M 1  even in the presence of a crack that passes through both path  80 B and  80 A. Consider, as an example, a scenario in which a crack passes through path  80 B in location  138  and passes through path  80 A in location  140 . During measurement with circuit M 1 , a loop-shaped signal path between terminals  122  and  124  will be formed. The loop-shaped path includes a first segment of path  80 A between terminal  122  and bridge path  142 , a first segment of path  80 B from path  142  to terminal  126 , a short circuit path through circuit M 2 , a second segment of path  80 B from terminal  128  to path  144 , and a second segment of path  80 A from path  144  to terminal  124 . The measured resistance of this type of path uniquely depends on the location of the crack (locations  138  and  140  in this present example) and can therefore be used to determine crack location along the edge of display  22 . 
     If desired, crack detection circuitry for display  22  may be provided with moisture intrusion sensitivity. A cross-sectional side view of an illustrative display with a moisture sensing configuration is shown in  FIG. 11 . As shown in  FIG. 11 , display  22  may contain an array of pixels  24  in active area AA. Each pixel  24  may include a light emitting diode such as diode  156 . Each diode  156  may be coupled to a transistor such as transistor  152  and other pixel control circuitry. Diodes such as diode  156  may include emissive material  158  between cathode  154  and anode  160 . 
     Anode  160  may be formed from a metal trace on surface  162  of thin-film transistor circuitry layer  150 . Layer  150  may include inorganic and/or organic dielectric layers, metal traces, one or more semiconductor layers, and/or other layers of material for forming thin-film transistor circuitry such as thin-film transistor  152 . In peripheral portions of display  22  without pixels  24  (e.g., inactive area IA), the same layer of metal that is patterned to form anodes such as anode  160  (sometimes referred to as an “anode layer”) may be used in forming peripheral paths  80 A and  80 B. Polymer  166  (e.g., a layer of photosensitive polymer patterned to form openings for emissive layer  158  for pixels  24 ) may overlap paths  80 A and  80 B. Encapsulation  164  (e.g., one or more layers of inorganic dielectric and/or organic dielectric such as polymer) may overlap display  22  and may help protect the structures of pixels  24  and thin-film transistor layer  150  from exposure to moisture and other environmental contaminants. 
     In the presence of a crack along the edge of display  22 , moisture may intrude into display  22  (e.g., past encapsulation layer  164  and layer  166 , thereby reaching paths  80 A and  80 B. Paths  80 A and  80 B may be formed from metal traces that degrade and become less conductive when exposed to moisture or other environmental contaminants. For example, paths  80 A and  80 B may be formed from a metal such as silver that oxidizes and/or otherwise corrodes and becomes more resistive when exposed to the environment (e.g., air and/or moisture). In the illustrative configuration of  FIG. 11 , paths  80 A and  80 B are formed above layer  150  near to encapsulation  164 , so paths  80 A and  80 B will be sensitive to degradation in encapsulation  164 . Paths  80 A and/or  80 B may also be formed from metal traces in thin-film transistor circuitry layer  150  (e.g., metal traces patterned in a source-drain metal layer). By monitoring the resistance of paths  80 A and/or  80 B over time, the presence of moisture in display  22  may be detected and suitable action taken. If desired, moisture monitoring paths such as paths  80 A and  80 B may also be used to monitor for the presence of cracks that form open circuits, as described in connection with  FIG. 10 . 
     Another illustrative peripheral monitoring circuit arrangement is shown in  FIGS. 12A, 12B, and 12C . With this type of arrangement, display  22  may have measurement circuit  44  that includes a resistance measurement circuit M 1  and a capacitance measurement circuit C 1 . One terminal of circuit M 1  and one terminal of circuit C 1  may be coupled to outer path  80 B and an opposing terminal of circuit M 1  and an opposing terminal of circuit C 1  may be coupled to inner path  80 A. Paths  80 A and  80 B may serve as first and second respective capacitor electrodes. Optional discrete capacitor structures such as capacitor C can be placed in a series of locations along the periphery of display  22 . Each capacitor C may, for example, have interdigitated fingers as shown in  FIG. 12B  or may have upper and lower overlapping electrodes as shown in  FIG. 12C  (e.g., electrodes that overlap in a direction perpendicular to the surface of the display). Dielectric (e.g., polymer  166  and/or polymer and/or inorganic dielectric in layer  150  of  FIG. 11 ) may be interposed between paths  80 A and  80 B. When moisture is present, the moisture will alter the dielectric constant of the dielectric between paths  80 A and  80 B. The resulting change in capacitance between paths  80 A and  80 B can be monitored by circuit C 1  and used to detect moisture intrusion. Moisture may also alter the resistance through the dielectric from path  80 B to  80 A, which can be monitored using circuit M 1 . 
     In addition to or instead of using circuits M 1  and C 1  to measure for degradation due to environmental contaminants, measurements from circuits M 1  and C 1  can be used to detect cracks. Consider, as an example, a scenario in which a crack is present in path  80 B at location  172 . This crack will electrically isolate portion  170  of path  80 B from the rest of path  80 B. As a result, the resistance measured by circuit M 1  between paths  80 B and  80 A through the dielectric separating paths  80 B and  80 A will rise in proportion to the shortened length of path  80 B. For example, if the length of path  80 B is cut in half by the presence of a crack, the measured resistance will double. At the same time, the measured capacitance between paths  80 B and  80 A will increase as the length of path  80 B is reduced (e.g., the capacitance measured by circuit C 1  will decrease in proportion to the decrease in length of path  80 B). Measured resistance and/or capacitance can therefore be used to determine the location of the crack. 
     As shown in  FIG. 13A , paths  80 A and  80 B may, if desired, be located centrally within tail portion  22 T of display  22 . For example, in a scenario in which tail  22 T has a total width W 2 , paths  80 A and  80 B may be located within a central strip of width W 1 , where W 1  is less than 50% of W 2 , less than 20% of W 2 , is less than 10% of W 2 , or is another suitable fraction of W 2 . The traces that form paths  80 A and  80 B in tail  22 T may be straight or may have a non-straight shape such as a serpentine shape or other meandering path shape to help resist cracking when tail  22 T is bent. For example, paths  80 A and  80 B may be formed from chains with circular links, elliptical links, butterfly patterns, single or double serpentine path shapes and/or other crack-resistant shapes. These path patterns may also be used in forming data lines D.  FIG. 13B  is a diagram showing illustrative chain-shaped meandering metal traces for forming paths  80 B and  80 A in tail  22 T. Other non-straight line shapes may be used for the metal traces forming paths  80 B and  80 A, if desired. 
     By placing paths  80 B and  80 A in the center of tail  22 T as shown in  FIG. 13A , paths  80 B and  80 A will be sensitive to damage to display  22  that is caused by dropping device  10  on its lower edge. Corner impacts can be detected using strain gauges located on either side of paths  80 A and  80 B (see, e.g., resistors R 1  and R 2  of  FIG. 2 ). The strain gauges may, however, exhibit reduced sensitivity to lower edge impacts. Potential damage to display  22  from lower edge impacts can, however, be measured by using circuitry  44  to monitor paths such as paths  80 B and  80 A in the center of tail  22 T, as shown in  FIG. 13A . 
     Paths  80 A and  80 B may all be formed in a first source-drain metal layer in thin-film transistor circuitry layer  150  of  FIG. 11 , may all be formed in a different second source-drain metal layer in layer  150 , or may include two lines formed in the first source-drain metal layer and two lines formed in the second source-drain metal layer (as examples). Tail  22 T may include a polymer coating layer (sometimes referred to as a neutral stress plane adjustment layer) that helps place a neutral stress plane of tail  22 T close to the metal traces on tail  22 T to reduce stress-induced cracks. For example, the neutral stress plane of tail  22 T may be located within a substrate layer in tail  22 T. The first source-drain metal layer may be located between the substrate of tail  22 T and the neutral stress plane adjustment layer. The second source-drain metal layer may be interposed between the first source-drain metal layer and the neutral stress plane adjustment layer. With this type of arrangement, the second source-drain metal layer may be located farther from the neutral stress plane in the substrate of tail  22 T than the first source-drain metal layer. As a result, placing all four of the lines for paths  80 A and  80 B in tail  22 T in the second source-drain metal layer may make paths  80 A and  80 B more sensitive to cracks in the bend in tail  22 T than placing all four of these lines in the first source-drain metal layer. 
     The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Metadata:
Filing Date: 20180213
Publication Date: 20210810
Grant Date: 20210810
Priority Date: 20160819
Inventors: MANDLIK, PRASHANT
LALGUDI VISWESWARAN, BHADRINARAYANA
AHMED, IZHAR Z
ZHANG, ZHEN
TSAI, TSUNG-TING
BYUN, KI YEOL
CHEN, YU CHENG
LEE, SUNGKI
HAJIROSTAM, MOHAMMAD
ALOUSI, SINAN
Assignee: APPLE INC
CPC Classifications: [{"code": "G09G3/3266", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2380/02", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0286", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C19/28", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/035", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G3/3677", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2330/12", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C19/28", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2310/0286", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/0426", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/32", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/3266", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/035", "inventive": true, "first": true, "tree": "[]"}, {"code": "G01L1/2281", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3677", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2330/12", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/043", "inventive": false, "first": false, "tree": "[]"}, {"code": "G01L1/2281", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2300/043", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G2330/12", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L27/3276", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2310/0286", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3677", "inventive": true, "first": false, "tree": "[]"}, {"code": "H01L51/0031", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G2380/02", "inventive": false, "first": false, "tree": "[]"}, {"code": "G01L1/2281", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L51/0097", "inventive": false, "first": false, "tree": "[]"}, {"code": "G09G3/3266", "inventive": true, "first": false, "tree": "[]"}, {"code": "G09G3/32", "inventive": true, "first": true, "tree": "[]"}, {"code": "G09G2300/043", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C19/28", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L2251/5338", "inventive": false, "first": false, "tree": "[]"}, {"code": "H01L27/3225", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K2102/311", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K71/70", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K77/111", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K2102/311", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K77/111", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "H10K71/70", "inventive": true, "first": false, "tree": "[]"}, {"code": "H10K59/131", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 62562501