PATENT DOCUMENT

Publication Number: US-8949684-B1
Application Number: US-55158309-A
Country: US
Kind Code: B1

Title: Segmented data storage

Abstract:
A method for data storage includes assigning in a memory that includes one or more storage devices a first storage area for storage of user data, and a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data. Input data is processed to produce redundancy data, and the input data is stored in the first storage area using at least one first write command. The redundancy data is stored in the second storage area using at least one second write command, separate from the first write command.

Claims:
The invention claimed is: 
     
       1. A method for data storage, comprising:
 estimating reliability of one or more multi-level memory cells in a memory, wherein the estimating the reliability includes determining a number of program and erase cycles that have been performed on the one or more multi-level memory cells; 
 partitioning the memory into a first storage area and a second storage area dependent upon the estimated reliability; 
 processing input data to produce first redundancy data and second redundancy data, wherein the second redundancy data incudes a larger number of redundancy bits than the first redundancy data; 
 storing the input data and the first redundancy data in the first storage area, wherein storing the input data includes mapping bit values of the input data to programming levels in a binary order; 
 storing the second redundancy data in the second storage area; and 
 evaluating a criterion with respect to the stored input data, and, responsively to the criterion, selecting to perform one of:
 reconstructing the input data irrespective of the second redundancy data stored in the second storage area by reading the input data from the first storage area; and 
 reading the second redundancy data from the second storage area and reconstructing the input data responsively to the second redundancy data; 
 
 wherein reconstructing the input data responsively to the second redundancy data comprises reusing readout data from a first page of the stored input data in a reading of a second page of the stored input data. 
 
     
     
       2. The method according to  claim 1 , wherein the criterion comprises a success of an attempt to reconstruct the input data by reading the input data and the first redundancy data from the first storage area irrespective of the second redundancy data stored in the second storage area. 
     
     
       3. The method according to  claim 1 , wherein processing the input data to produce the first redundancy data and the second redundancy data comprises encoding the input data using first and second Error Correction Codes (ECC) to produce respective first and second sets of parity bits, wherein storing the input data and the first redundancy data comprises storing the first set of the parity bits in the first storage area, and wherein storing the second redundancy data comprises storing the second set of the parity bits in the second storage area. 
     
     
       4. The method according to  claim 3 , wherein reconstructing the input data irrespective of the second redundancy data comprises reading the first set of the parity bits from the first storage area and decoding the first ECC, and wherein reconstructing the input data responsively to the second redundancy data comprises reading the second set of the parity bits from the second storage area and decoding the second ECC. 
     
     
       5. The method according to  claim 1 , wherein evaluating the criterion comprises assessing a time period that elapsed since the input data was stored. 
     
     
       6. The method according to  claim 1 , wherein evaluating the criterion comprises assessing a wear level of memory cells holding the input data. 
     
     
       7. The method according to  claim 1 , wherein reading the input data and the first redundancy data comprises accessing the first storage area, and wherein reading the second redundancy data comprises accessing the second storage area. 
     
     
       8. The method according to  claim 1 , wherein each multi-level memory cell is configured to store at least a first bit and a second bit, and wherein reading the first redundancy data comprises reading the first bit using one or more first read thresholds and reading the second bit using one or more second read thresholds, such that at least a common read threshold is common to the first and second read thresholds, and correcting at least one error in reading the second bit with respect to the common read threshold based on the read first bit. 
     
     
       9. The method according to  claim 1 , wherein storing the input data and the first redundancy data in the first storage area comprises programming at least one multi-level memory cell included in the first storage area dependent upon the input data and the first redundancy data using a first storage configuration; and wherein storing the second redundancy data in the second storage area comprises programming at least one multi-level analog memory cell included in the second storage area dependent upon the second redundancy data using the first storage configuration; and the method further comprising detecting that shut-off of electrical power to the memory is imminent, and re-programming the at least one multi-level memory cell included in the first storage area and the at least one multi-level memory cell included in the second storage area using a second storage configuration. 
     
     
       10. The method according to  claim 1 , wherein the memory includes at least first and second storage devices implemented using first and second different storage media types, wherein the first storage area is assigned in the first storage device, and wherein the second storage area is assigned in the second storage device. 
     
     
       11. An apparatus for data storage, comprising:
 an interface, which is coupled to communicate with a memory; and 
 circuitry coupled to the memory, wherein the circuitry is configured to: 
 estimate reliability of one or more multi-level memory cells in the memory, wherein to estimate the reliability of the one or more multi-level memory cells in the memory, the circuitry is further configured to determine a number of program and erase cycles that have been performed on the one or more multi-level memory cells; 
 partitioning the memory into a first storage area and a second storage area dependent upon the estimated reliability; 
 process input data to produce first redundancy data and second redundancy data, wherein the second redundancy data includes a larger number of redundancy bits than the first redundancy data; 
 store the input data and the first redundancy data in the first storage area; 
 wherein to store the input data the circuitry is further configured to map bit values of the input data to programming levels in a binary order; 
 store the second redundancy data in the second storage area; and 
 evaluate a criterion with respect to the stored input data, and, responsively to the criterion, selecting to perform one of:
 reconstruct the input data irrespective of the second redundancy data stored in the second storage area by reading the input data from the first storage area; and 
 read the second redundancy data from the second storage area and reconstructing the input data responsively to the second redundancy data; 
 
 wherein to reconstruct the input data responsively to the read second redundancy data the circuitry is further configured to reuse readout data from a first page of the stored input data in a reading of a second page of the stored input data. 
 
     
     
       12. The apparatus according to  claim 11 , wherein the criterion comprises a success of an attempt to reconstruct the input data by reading the input data and the first redundancy data from the first storage area irrespective of the second redundancy data stored in the second storage area. 
     
     
       13. The apparatus according to  claim 11 , wherein to process the input data to produce the first redundancy data and the second redundancy data, the circuitry is further configured to encode the input data using first and second Error Correction Codes (ECC) to produce respective first and second sets of parity bits, and to store the first set of the parity bits in the first storage area and to store the second set of the parity bits in the second storage area. 
     
     
       14. The apparatus according to  claim 13 , wherein the circuitry is further configured to reconstruct the input data irrespective of the second redundancy data by reading the first set of the parity bits from the first storage area and decoding the first ECC, and to reconstruct the input data responsively to the second redundancy data by reading the second set of the parity bits from the second storage area and decoding the second ECC. 
     
     
       15. The apparatus according to  claim 11 , wherein the circuitry is further configured to evaluate the criterion by assessing a time period that elapsed since the input data was stored. 
     
     
       16. The apparatus according to  claim 11 , wherein the circuitry is further configured to evaluate the criterion by assessing a wear level of the one or more multi-level memory cells holding the input data. 
     
     
       17. The apparatus according to  claim 11 , wherein to store the input data in the first storage area the circuitry is further configured to store the input data and the first redundancy data in the first storage area using at least one first write command, and wherein to store the second redundancy data in the second storage area the circuitry is further configured to store the second redundancy data in the second storage area using at least one second write command, different from the first write command. 
     
     
       18. The apparatus according to  claim 11 , wherein each multi-level memory cell is configured to store at least a first bit and a second bit, and wherein the circuitry is configured to read the first bit using one or more first read thresholds, to read the second bit using one or more second read thresholds such that at least a common read threshold is common to the first and second read thresholds, and to correct at least one error in reading the second bit with respect to the common read threshold based on the read first bit. 
     
     
       19. The apparatus according to  claim 11 , wherein to store the input data and the first redundancy data in the first storage area, the circuitry is further configured to program at least one multi-level memory cell included in the first storage area dependent on the input data and the first redundancy data using a first storage configuration; and wherein to store the second redundancy data in the second storage area, the circuitry is further configured to program at least one multi-level memory included in the second storage area dependent upon the second redundancy data using the first storage configuration; and wherein the circuitry is further configured to detect that shut-off of electrical power to the memory is imminent, and to re-program the at least one multi-level memory cell of the first storage area and the at least one multi-level memory cell of the second storage area using a second storage configuration responsive to the detection of the shut-off. 
     
     
       20. The apparatus according to  claim 11 , wherein the memory includes at least first and second storage devices implemented using first and second different storage media types, and wherein the circuitry is configured to assign the first storage area in the first storage device and to assign the second storage area in the second storage device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Application 61/093,613, filed Sep. 2, 2008, U.S. Provisional Patent Application 61/105,819, filed Oct. 16, 2008, U.S. Provisional Patent Application 61/120,968, filed Dec. 9, 2008, and U.S. Provisional Patent Application 61/141,866, filed Dec. 31, 2008, whose disclosures are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to data storage, and particularly to segmented storage of data and redundancy information. 
     BACKGROUND OF THE INVENTION 
     Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume either of two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels. 
     Data that is stored in memory is sometimes encoded with an Error Correction Code (ECC) in order to reduce the likelihood of read errors. For example, Goodman and Sayano describe a number of on-chip coding techniques for the protection of Random Access Memory (RAM) devices, which use multi-level storage cells, in “On-Chip ECC for Multi-Level Random Access Memories,” Proceedings of the 1989 IEEE/CAM Information Theory Workshop, Jun. 25-29, 1989, Ithaca, N.Y., which is incorporated herein by reference. As another example, U.S. Pat. No. 6,212,654, whose disclosure is incorporated herein by reference, describes methods for storing data in an analog memory device using coded modulation techniques. Other ECC schemes for multilevel memory devices are described in U.S. Pat. No. 6,469,931, whose disclosure is incorporated herein by reference. 
     U.S. Patent Application Publication 2004/0083333, whose disclosure is incorporated herein by reference, describes techniques for using different ECC algorithms to encode and to decode contents of blocks within a non-volatile memory. U.S. Patent Application Publication 2004/0083334, whose disclosure is incorporated herein by reference, describes techniques for encoding data associated with a page by dividing the page into segments and separately encoding the segments using extended ECC calculations. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a method for data storage, including: 
     in a memory that includes one or more storage devices, assigning a first storage area for storage of user data, and a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data; 
     processing input data to produce redundancy data; 
     storing the input data in the first storage area using at least one first write command; and 
     storing the redundancy data in the second storage area using at least one second write command, separate from the first write command. 
     In some embodiments, the method includes evaluating a criterion with respect to the stored input data, and, responsively to the criterion, selecting to perform one of: 
     reconstructing the input data irrespective of the redundancy data stored in the second storage area by reading the input data from the first storage area; and 
     reading the redundancy data from the second storage area and reconstructing the input data responsively to the read redundancy data. 
     In a disclosed embodiment, the criterion includes a success of an attempt to reconstruct the input data by reading the input data from the first storage area irrespective of the redundancy data stored in the second storage area. In an embodiment, processing the input data includes encoding the input data with an Error Correction Code (ECC) to produce parity bits, storing the redundancy data includes storing the parity bits in the second storage area, and reconstructing the input data responsively to the redundancy data includes decoding the ECC. 
     In another embodiment, processing the input data includes encoding the input data using first and second Error Correction Codes (ECC) to produce respective first and second sets of parity bits, storing the input data includes storing the first set of the parity bits in the first storage area, and storing the redundancy data includes storing the second set of the parity bits in the second storage area. In an embodiment, reconstructing the input data irrespective of the redundancy data includes reading the first set of the redundancy bits from the first storage area and decoding the first ECC, and reconstructing the input data responsively to the read redundancy data includes reading the second set of the redundancy bits from the second storage area and decoding the second ECC. 
     In another embodiment, evaluating the criterion includes assessing a time period that elapsed since the input data was stored. Additionally or alternatively, evaluating the criterion includes assessing a wear level of memory cells holding the input data. In an embodiment, reading the input data includes accessing the first storage area using at least one first read command, and reading the redundancy data includes accessing the second storage area using at least one second read command, different from the first read command. In yet another embodiment, the memory includes multi-level analog memory cells, each storing at least first and second bits, and reading the redundancy data includes reading the first bits using one or more first read thresholds and reading the second bits using one or more second read thresholds, such that at least a common read threshold is common to the first and second read thresholds, and correcting at least one error in reading the second bits with respect to the common read threshold based on the read first bits. 
     In some embodiments, assigning the second storage area includes evaluating a criterion with respect to the memory, and modifying a size of the second storage area responsively to the criterion. Evaluating the criterion may include assessing a storage reliability of memory cells in the first storage area. In an embodiment, the method includes storing the redundancy data in the second storage area responsively to detecting that shut-off of electrical power to the memory is imminent. In another embodiment, the memory includes at least first and second storage devices implemented using first and second different storage media types, the first storage area is assigned in the first storage device, and the second storage area is assigned in the second storage device. 
     There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage, including: 
     an interface, which is coupled to communicate with a memory that includes one or more storage devices; and 
     circuitry, which is configured to assign in the memory a first storage area for storage of user data, to assign in the memory a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data, to process input data to produce redundancy data, to store the input data in the first storage area using at least one first write command, and to store the redundancy data in the second storage area using at least one second write command, separate from the first write command. 
     There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage, including: 
     a memory including one or more storage devices; and 
     circuitry, which is configured to assign in the memory a first storage area for storage of user data, to assign in the memory a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data, to process input data to produce redundancy data, to store the input data in the first storage area using at least one first write command, and to store the redundancy data in the second storage area using at least one second write command, separate from the first write command. 
     The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention; 
         FIG. 2  is a block diagram that schematically illustrates a Solid-State Disk (SSD) system, in accordance with an embodiment of the present invention. 
         FIGS. 3 and 4  are flow charts that schematically illustrate methods for data storage and retrieval, in accordance with embodiments of the present invention; 
         FIG. 5  is a diagram showing memories partitioned into data storage, redundancy storage and over-provisioning areas, in accordance with an embodiment of the present invention; 
         FIG. 6  is a flow chart that schematically illustrates a method for allocating redundancy storage space, in accordance with an embodiment of the present invention; 
         FIG. 7  is a flow chart that schematically illustrates a method for data storage in the presence of power shut-down, in accordance with an embodiment of the present invention; and 
         FIG. 8  is a graph showing threshold voltage distributions in groups of analog memory cells, in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Overview 
     Embodiments of the present invention that are described hereinbelow provide methods and systems for improving the reliability, latency, cost-effectiveness and operational flexibility of data storage and retrieval. These embodiments refer mainly to Solid-State Disk (SSD) systems, but the disclosed techniques are similarly applicable to various other memory systems and applications. 
     In some embodiments, a memory is partitioned into a data storage area and a redundancy storage area, separate from one another. The data storage area is used for storing user data, while the redundancy storage area is used for storing redundancy information (e.g., ECC parity bits) related to the user data. Typically, the data storage area and the redundancy storage area are located in different regions of the memory, typically in different physical pages or blocks, or even on different memory devices. In particular, the data storage area and the redundancy storage area are accessed by separate memory access commands (such as read, write and erase commands). When input data is accepted for storage in the memory, the input data is processed to produce redundancy data. The input data is stored in the data storage area and the redundancy data is stored in the redundancy storage area, typically using separate write commands. 
     Typically, when the input data is to be retrieved from the memory, an attempt is first made to reconstruct the data from the contents of the data storage area, without reading or using the redundancy data stored in the redundancy storage area. If the initial attempt fails, the redundancy data is read from the redundancy storage area. The input data is then reconstructed using both the data read from the data storage area and the redundancy data read from the redundancy storage area. The initial attempt to reconstruct the data without reading the redundancy data may be skipped, for example, if it is known that the memory cells that store the user data are heavily-cycled or have not been refreshed for a long period of time. 
     In some embodiments, some redundancy bits are stored in the data storage area in addition to the input data. Other redundancy bits are stored, as described above, in the redundancy storage area. For example, the input data may be encoded with two different ECCs, with the parity bits of the first ECC stored in the data storage area, and the parity bits of the second ECC (which is typically stronger) stored in the redundancy storage area. In these embodiments, an attempt is initially made to decode the first ECC (whose parity bits are read together with the input data from the data storage area). If this first decoding attempt fails, the parity bits of the second ECC are read from the redundancy storage area and the second ECC is decoded. 
     When using the methods and systems described herein, the vast majority of user data is usually read successfully using only the information stored in the data storage area. The additional redundancy information is reverted to only on the rare occasion that the information in the data storage area is severely distorted. The higher latency and computational power associated with reading and decoding the redundancy information is incurred only when actually needed. Thus, the methods and systems described herein enable data readout at low latency without compromising data storage reliability. 
     System Description 
       FIG. 1  is a block diagram that schematically illustrates a memory system  20 , in accordance with an embodiment of the present invention. System  20  stores data in a memory  24 , which comprises one or more storage devices. In the embodiments described herein, memory  24  comprises one or more non-volatile Flash memory devices. In alternative embodiments, however, the storage devices of memory  24  may comprise any other suitable type of memory device, such as NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory—PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells. Additionally or alternatively to non-volatile solid-state memory devices, the storage devices of memory  24  may comprise volatile memory devices such as various types of Random Access Memory (RAM), as well as magnetic storage devices such as Hard Disk Drives (HDD). The different types of storage devices are also referred to herein as different storage media. Generally, memory  24  may comprise one or more storage devices, which may be of the same storage medium or of different media types. 
     System  20  comprises a memory controller  28 , which accepts data from a host  32  and stores it in memory  24 , and retrieves data from the memory and provides it to the host. Memory controller  28  comprises a host interface  36  for communicating with host  32 , a memory interface  40  for communicating with memory  24 , and a processor  44  that processes the stored and retrieved data. In some embodiments, controller  28  encodes the stored data with an Error Correction Code (ECC). In these embodiments, controller  28  comprises an ECC unit  48 , which encodes the data before stored in memory  24  and decodes the ECC of data retrieved from the memory. Any suitable type of ECC, such as Bose-Chaudhuri-Hocquenghem (BCH) or Reed-Solomon (RS) codes can be used. 
     Memory controller  28  assigns a data storage area  52  and a redundancy storage area  56  in memory  24 . Data storage area  52  is used for storing user data  60 , i.e., data that is accepted for storage from host  32 . Redundancy storage area  56 , on the other hand, is used for storing redundancy information  64  that is related to the user data. The term “redundancy information” is used to describe any kind of information, which increases the likelihood of successfully reconstructing the stored user data. Redundancy information may comprise, for example, ECC parity bits that are produced by ECC unit  48 . Alternatively, the redundancy information may comprise a Cyclic Redundancy Check (CRC), checksum or any other suitable type of redundancy information. (In some embodiments, some redundancy information is also stored in data storage area  52  along with the user data, as will be explained further below.) 
     The data storage area and the redundancy storage area are typically assigned in separate locations in memory  24 , i.e., in different memory pages or blocks of a given storage device, or in different storage devices. In some embodiments, the data storage area can be assigned in a storage device of a given storage medium, and the redundancy storage area in a storage device of a different storage medium. For example, the data storage area may be assigned in a storage medium that is optimized for speed, such as fast MLC memory. The redundancy storage area may be assigned in a storage medium that is optimized for reliability such as SLC memory, or in a storage medium that is optimized for low cost such as MLC memory. In an example implementation, the data storage area may reside in Flash memory while the redundancy storage area resides in a DRAM device or in a RAM drive. Each of the data storage area and the redundancy storage area may comprise a single contiguous storage region, or it may be divided into multiple non-contiguous regions in one or more of the storage devices of memory  24 . 
     Typically, the data storage area and the redundancy storage area are accessed (read, written and/or erased) using separate memory access commands. The commands may differ in form (e.g., when the data storage and redundancy storage areas are assigned in different storage media), or only in address values (e.g., when the data storage and redundancy storage areas are assigned in different regions of the same memory device). 
     In the description that follows, system  20  comprises a Solid-State Disk (SSD) system that stores data for a host computer. In alternative embodiments, however, system  20  may be used in any other suitable application and with any other suitable host, such as in computing devices, cellular phones or other communication terminals, removable memory modules such as Disk-On-Key (DOK) devices, Secure Digital (SD) cards, Multi-Media Cards (MMC) and embedded MMC (eMMC), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved. 
       FIG. 2  is a block diagram that schematically illustrates an SSD system  70 , in accordance with an embodiment of the present invention. System  70  can be viewed as an example implementation of system  20  of  FIG. 1  above. System  70  accepts data for storage from a host  74  and stores it in memory, and retrieves data from memory and provides it to the host. System  70  comprises multiple memory devices  78 , each comprising multiple analog memory cells. In the present example, devices  78  comprise non-volatile NAND Flash devices, although any other suitable memory type, such as the memory types described above, can also be used. Each memory device  78  may comprise a packaged device or an unpackaged semiconductor chip or die. A typical SSD may comprise on the order of thirty-two devices, each providing a storage space of 4096 MB. Alternatively, however, system  70  may comprise any suitable number of memory devices of any desired type and size. Although the system configuration of  FIG. 2  comprises multiple memory devices, the methods and systems described herein can also be used in systems having only a single memory device. 
     System  70  comprises an SSD controller  82 , which accepts data from host  74  and stores it in memory devices  78 , and retrieves data from the memory devices and provides it to the host. SSD controller  82  comprises a host interface  86  for communicating with host  74 , a memory interface  90  for communicating with memory devices  78 , and a processor  94  that processes the stored and retrieved data. In particular, processor  94  assigns a data storage area and a redundancy storage area in memory devices  78 , and carries out the data storage methods described herein using these separate areas. In some embodiments, controller  94  encodes the stored data with an ECC. In these embodiments, controller  82  comprises an ECC unit  98 , which encodes the data before stored in devices  78  and decodes the ECC of data retrieved from devices  78 . 
     Each memory device  78  comprises a memory cell array  106 . The memory array comprises multiple analog memory cells  110 . In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Any suitable type of analog memory cells, such as the types listed above, can be used. In the present example, each memory device  78  comprises a non-volatile memory of NAND Flash cells. 
     The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages (i.e., as is well-known in the art, the gate voltage at which the memory cell begins to conduct), the methods and systems described herein may be used with any other suitable kind of storage values. 
     System  70  stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values into the cell. 
     Each memory device  78  comprises a reading/writing (R/W) unit  102 , which accepts data for storage from SSD controller  82 , converts the data into analog storage values and writes them into memory cells  110  of that memory device. When reading data out of array  106 , R/W unit  102  typically converts the storage values of memory cells  110  into digital samples having a resolution of one or more bits, and provides the digital samples to controller  82 . Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W unit can erase a group of cells  110  by applying one or more negative erasure pulses to the cells. 
     Memory controller  28  in  FIG. 1  and/or SSD controller  82  in  FIG. 2 , and in particular processors  44  and/or  94 , may be implemented in hardware. Alternatively, controller and/or  82  may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements. In some embodiments, processor  44  and/or  94  comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory. 
     The configurations of  FIGS. 1 and 2  are exemplary system configurations, which are shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figures for clarity. 
     In the exemplary system configuration shown in  FIG. 2 , memory devices  78  and SSD controller  82  are implemented as separate Integrated Circuits (ICs). In alternative embodiments, however, the memory and the controller (memory  24  and controller  28 , or memory devices  78  and controller  82 ) may be integrated on separate semiconductor dies in a single Multi-Chip 
     Package (MCP) or System on Chip (SoC), and may be interconnected by an internal bus. Further alternatively, some or all of the controller circuitry may reside on the same die on which one or more of the memory devices are disposed. Further alternatively, some or all of the functionality of the controller can be implemented in software and carried out by a processor or other element of the host system. In some embodiments, the host and the controller may be fabricated on the same die, or on separate dies in the same device package. 
     In an example configuration, memory cells  110  in a given array  106  are arranged in multiple rows and columns. The memory cells in each row are connected by word lines, and the memory cells in each column are connected by bit lines. The memory array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In a typical implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row. 
     Erasing of cells is usually carried out in blocks that contain multiple pages. Typical memory devices may comprise several thousand erasure blocks. In a typical two-bit-per-cell MLC device, each erasure block is on the order of thirty-two word lines, each comprising several thousand cells. Each word line of such a device is often partitioned into four pages (odd/even order cells, least/most significant bit of the cells). Three-bit-per cell devices having thirty-two word lines per erasure block would have 192 pages per erasure block, and four-bit-per-cell devices would have 256 pages per block. Alternatively, other block sizes and configurations can also be used. Some memory devices comprise two or more separate memory cell arrays, often referred to as planes. Since each plane has a certain “busy” period between successive write operations, data can be written alternately to the different planes in order to increase programming speed. 
     Data Storage and Retrieval in Data Storage Area and Redundancy Storage Area 
     Storing user data in one area and redundancy data in another area is advantageous for several reasons. For example, in many cases the user data can be reconstructed successfully without fetching or using the redundancy information at all. When the user data and redundancy information are stored separately and read by separate read commands, it is often sufficient to read only the data storage area in order to retrieve the user data. The average number of read commands is thus reduced considerably, along with the latency and computational complexity associated with reading and decoding the redundancy information. An example method that uses this principle is shown in  FIG. 3  below. 
     Moreover, separate storage of user data and redundancy information may be advantageous even if the redundancy information is read and used unconditionally. For example, the data structure in some memory devices (e.g., page size) limits the ability to encode the user data with high-redundancy (e.g., low-rate) ECC. Since most memory devices have a fixed page size, the efficiency of using variable-rate ECC is often limited. Storing the redundancy information in a separate area enables the use of high-redundancy ECC and efficient utilization of memory space. In some cases, storage of user data and redundancy information has different performance requirements, which are better met by different storage media. Separated storage enables storing each of the user data and the redundancy information in a storage medium that best matches its specific requirements. 
       FIG. 3  is a flow chart that schematically illustrates a method for data storage and retrieval, in accordance with an embodiment of the present invention. Although the method description refers to system  20  of  FIG. 1  above, the method may be applied to any other suitable system configuration, such as SSD system  70  of  FIG. 2 . 
     The method of  FIG. 3  begins with memory controller  28  assigning data storage area  52  and redundancy storage area  56  in memory  24 , at a partitioning step  120 . At some point in time, memory controller  28  accepts certain input data for storage, at an input step  124 . The input data comprises data bits. The memory controller encodes the data bits of the input data with an ECC, using ECC unit  48 , at an encoding step  128 . The ECC encoding operation produces parity bits, also referred to as redundancy bits. The memory controller stores the data bits in data storage area  52 , and the redundancy bits in redundancy storage area  56 , at a storage step  132 . The controller typically stores the data bits using one or more write commands that address the data storage area, and the redundancy bits using one or more other write commands that address the redundancy storage area. 
     At a certain point in time, memory controller  28  accepts from host  32  a request to retrieve the input data, at a retrieval request step  136 . In response to the request, the memory controller reads the data bits of the input data from data storage area  52 , and the corresponding redundancy bits from redundancy storage area  56 , at a readout step  140 . The controller typically reads the data bits using one or more read commands that address the data storage area, and the redundancy bits using one or more other read commands that address the redundancy storage area. 
     ECC unit  48  of memory controller  28  processes the retrieved data bits and redundancy bits so as to decode the ECC, at an ECC decoding step  144 . The decoding operation reconstructs the input data. The memory controller outputs the reconstructed data to the host, at an output step  148 . 
       FIG. 4  is a flow chart that schematically illustrates another method for data storage and retrieval, in accordance with an alternative embodiment of the present invention. Although the method description refers to system  20  of  FIG. 1  above, the method may be applied to any other suitable system configuration, such as SSD system  70  of  FIG. 2 . 
     The method of  FIG. 4  begins with ECC unit  48  of memory controller  28  encoding the data bits of certain input data with two alternative ECCs denoted ECC1 and ECC2, at a dual encoding step  150 . Typically, ECC2 is stronger (e.g., has a lower code rate) than ECC1, and as a result produces a larger number of redundancy bits for a given set of data bits. 
     The memory controller stores the data bits and the redundancy bits of ECC1 in data storage area  52 , at a first storage step  154 . The memory controller stores the redundancy bits of ECC2 in redundancy storage area  56 , at a second storage step  158 . Typically, the memory controller carries out step  154  using one or more write commands that address the data storage area, and step  158  using one or more other write commands that address the redundancy storage area. 
     The memory controller accepts a request to retrieve the data in question, at a readout request step  162 . In response to the request, the memory controller first attempts to reconstruct the data using only the information stored in the data storage area (i.e., based on ECC1). The memory controller reads the data bits and the redundancy bits of ECC1 from the data storage area, at a first readout step  166 . ECC unit  48  attempts to decode ECC1, at an ECC1 decoding step  170 . If the attempt to decode ECC1 is successful, the memory controller outputs the reconstructed data to the host, at a data output step  176 , and the method terminates. 
     Otherwise, i.e., if the attempt to decode ECC1 fails, the memory controller reads the redundancy bits of ECC2 from redundancy storage area  56 , at a second readout step  178 . ECC unit  48  then decodes ECC2, at an ECC2 decoding step  182 . Since ECC2 is stronger than ECC1, ECC2 decoding is likely to succeed even though ECC1 decoding (step  170 ) has failed. Memory controller  28  then outputs the reconstructed data to the host, at step  176 . 
     In the method of  FIG. 4 , the memory controller accesses the redundancy storage area selectively, only when the data cannot be reconstructed based on the information stored in the data storage area. This feature, as explained above, significantly reduces the average number of read operations carried out by the memory controller. As a result, the average read latency is considerably lower. Since ECC2 typically comprises a low-rate code, its decoding is often a computationally-intensive and time-consuming task, and therefore the reduction in read latency achieved by the method of  FIG. 4  is particularly important. 
     Another feature of the method of  FIG. 4  is that some redundancy information is stored in the data storage area in addition to the data bits. This technique increases the likelihood of succeeding to reconstruct the data in the initial attempt (i.e., without reverting to the redundancy storage area). On the other hand, this technique increases the average read latency, because ECC1 is decoded in any readout operation. Since ECC1 is typically selected to be a relatively high-rate code (which produces a relatively small number of parity bits), the latency increase is usually tolerable. 
     Note that in some embodiments, the redundancy storage area can be accessed selectively (i.e., only upon failure to reconstruct the data using the data storage area) even if no redundancy information is stored in the data storage area. 
     Alternatively to using ECC1, the memory controller may store other forms of redundancy information in the data storage area. For example, the memory controller may compute an error detection code (e.g., a Cyclic Redundancy Check (CRC) or checksum) over the data bits, and store the result in the data storage area. When reading the data, the memory controller may evaluate the error detection code in order to decide whether or not to revert to the redundancy storage area. 
     The example of  FIG. 4  describes two levels of redundancy, namely ECC1 and ECC2. Alternatively, however, the memory controller may apply three or more levels of redundancy, each stored and retrieved separately. In these embodiments, the memory controller gradually increases the level of redundancy if the previous attempt fails. 
     In the description above, the second decoding attempt (step  182 ) uses the redundancy bits stored in the redundancy storage area, and not the redundancy bits stored in the data storage area. In alternative embodiments, however, the second decoding attempt may consider the redundancy bits stored both in the redundancy storage area and in the data storage area. This technique is sometimes referred to as incremental encoding. Some aspects of incremental encoding are addressed in U.S. Patent Application Publication 2008/0282106, which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference. 
     Variable-Size Redundancy Storage Area 
     In some embodiments, memory controller  28  modifies the size of the redundancy storage area dynamically over the lifetime of memory  24 . The memory controller may adjust the size of the redundancy storage area based on any suitable criterion related to the memory, such as based on the estimated storage reliability of the memory cells in the data storage area. The memory controller may estimate the storage reliability, for example, depending on the number of programming and erasure cycles the cells have gone through. This estimate is based on the assumption that fresh memory cells have higher storage reliability than heavily-cycled memory cells. 
     As another example, when the system is subject to long power shut-off periods, memory controller  28  may increase the size of the redundancy storage area and apply sufficient redundancy to maintain data reliably during power shut-off. When power shut-off periods are not anticipated, a smaller redundancy storage area may be sufficient. The size of the redundancy storage area can also be adjusted depending on whether advance notification of power shut-off is available. As yet another example, the storage reliability in memory  24  may be user-configurable or otherwise pre-specified. In such cases, the memory controller may adjust the size of the redundancy storage area (and the amount of redundancy) to match the specified reliability level, thus effectively trading memory space for reliability. Additionally or alternatively, any other suitable criteria can be used to set the size of the redundancy storage area. 
       FIG. 5  is a diagram showing memory arrays partitioned into data storage, redundancy storage and Over-Provisioning (OP) areas, in accordance with an embodiment of the present invention. In the example of  FIG. 5 , a memory  180 A is partitioned (statically or dynamically) into a data storage area  184 A, a redundancy storage area  188 A and an OP area  192 A. A memory  180 B is partitioned into a data storage area  184 B, a redundancy storage area  188 B and an OP area  192 B. Memory  180 A represents a situation in which the memory cells are relatively fresh, i.e., have gone through a relatively small number of programming and erasure cycles. Memory  180 B represents a situation in which the memory cells are heavily cycled, i.e., have gone through a relatively large number of programming and erasure cycles. Memories  180 A and  180 B may correspond to different groups of memory cells. Alternatively, Memory  180 B may correspond to the same group of memory cells as memory  180 A, but at a later point in time. 
     The functions of the data storage areas ( 184 A and  184 B) and the redundancy storage areas ( 188 A and  188 B) have been described above. The OP areas ( 192 A and  192 B) are typically used as dynamic cache memories, for performing random (i.e., non-sequential) write operations more efficiently. 
     When the memory cells are relatively fresh, reliable storage can be achieved using a modest amount of redundancy information. The memory controller thus sets the size of redundancy storage area  188 A accordingly. When the memory cells become heavily-cycled, their storage reliability deteriorates, and additional redundancy may be needed in order to maintain reliable storage. Therefore, the memory controller sets the size of redundancy storage area  188 B to be larger than the size of area  188 A. In the present example, increasing the size of the redundancy storage area comes at the expense of reducing the size of the OP area, i.e., at the expense of degraded random write performance. 
       FIG. 6  is a flow chart that schematically illustrates a method for allocating redundancy storage space, in accordance with an embodiment of the present invention. The method begins with memory controller  28  estimating the storage reliability of a group of memory cells, at a reliability estimation step  200 . For example, the memory controller may estimate the storage reliability based on the number of programming and erasure cycles applied to the memory cells. The memory controller sets the ECC redundancy (e.g., the ECC code rate) based on the estimated storage reliability, at a redundancy setting step  204 . The memory controller then sets the size of the redundancy storage area based on the ECC redundancy level, at a redundancy area setting step  208 . 
     Some aspects of estimating the storage reliability of memory cells and of using variable redundancy levels are addressed in U.S. patent application Ser. No. 12/063,544, entitled “Memory Device with Adaptive Capacity,” which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference. 
     Data Storage in the Presence of Power Shut-Off Events 
     In some data storage applications, system  20  experiences power shut-off events. Power shut-offs are common, for example, in removable storage devices that accept electrical power from a host, such as SSD systems (e.g., system  70  in  FIG. 2 ), Disk-On-Keys (DOK) and removable memory cards. A device of this sort experiences power shut-off whenever it is disconnected from the host. Power shut-off periods have a detrimental effect on the storage reliability of analog memory cells, because the storage values of some memory cells may undergo considerable distortion by the time electrical power is restored. This distortion may cause significant performance degradation. 
     In some embodiments of the present invention, system  20  identifies that power shut-off is imminent, such as by accepting an indication from the host. Upon detecting that power shut-down is imminent, the memory controller re-programs at least some of the data in the memory using a different storage configuration, which is more robust to long retention periods. For example, the robust storage configuration may use an ECC having higher redundancy than the ECC used for normal storage. Some aspects of data storage in the presence of power shut-down events are addressed in detail in U.S. patent application Ser. No. 12/551,567, entitled “Reliable Data Storage in Analog Memory Cells Subjected to Long Retention Periods,” filed Sep. 1, 2009, which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference. 
     In some embodiments, the memory controller stores the redundancy bits of the ECC, which is used in the normal storage configuration, in the data storage area. The redundancy bits of the higher-redundancy ECC, which is used in the robust storage configuration, are stored in the redundancy storage area. Using this technique, the normal storage configuration has relatively low read latency. 
       FIG. 7  is a flow chart that schematically illustrates a method for data storage in the presence of power shut-down, in accordance with an embodiment of the present invention. The method begins with the memory controller storing data in the memory using the normal storage configuration, at a normal storage step  210 . The memory controller checks whether power shut-down is imminent, at a checking step  214 . If no power shut-down is expected, the method loops back to step  210  above. 
     Otherwise, i.e., upon detecting that power shut-down is imminent, the memory controller re-programs at least some of the data using the robust storage configuration, at a robust re-programming step  218 . The robust storage configuration uses an ECC whose code rate is lower than the ECC used in the normal storage configuration. When re-programming the data, the memory controller stores the redundancy bits of the lower-rate ECC in the redundancy storage area. 
     Segmented Data Storage in Memory Devices Having Binary Bit Mapping 
     As explained above, analog memory cell devices (e.g., Flash devices) store data in analog memory cells by writing analog storage values into the cells. The range of storage values (e.g., charge levels or threshold voltages) is divided into intervals that represent possible data values. Each such interval is referred to as a programming state or programming level. R/W unit  102  ( FIG. 2 ) programs a given memory cell to store a certain data value by writing a storage value that falls in the range corresponding to that data value. The R/W unit typically reads a given memory cell by comparing its storage value to one or more read thresholds, which are usually positioned in the boundary regions between adjacent programming levels. 
     In multi-level memory cell devices, each memory cell stores two or more data bits, and each programming level corresponds to a particular value combination of these two or more bits. When using four-level memory cells, for example, each memory cell stores two data bits. The bits are commonly referred to as a Least Significant Bit (LSB) and a Most Significant Bit (MSB), although this terminology is arbitrary and any other suitable terminology can also be used. In some embodiments, the memory controller stores multiple memory pages in a group of multi-level memory cells (e.g., the cells in a given word line), such that different bits store different pages. In four-level cells, for example, the memory controller may store a certain memory page in the cell LSBs and another page in the cell MSBs. Each bit (page) is read using a respective set of one or more read thresholds. 
     Multi-level memory devices may differ from one another in the way bit values are mapped to programming levels. Two common mapping schemes are Gray mapping and binary mapping. In Gray mapping, adjacent programming levels differ from one another by only one bit value. Since most read errors occur between adjacent programming levels, Gray mapping ensures that each error event affects only a single bit, and therefore reduces the overall error probability. In binary mapping, bit values are mapped to programming levels in an ascending or descending binary order. As a result, some error events between adjacent programming levels affect more than a single bit. Thus, binary mapping is usually inferior to Gray mapping in terms of read error performance. 
       FIG. 8  is a graph showing Gray mapping and binary mapping of bit values to programming levels, in accordance with an embodiment of the present invention. The example of  FIG. 8  refers to four-level MLC, each storing two data bits. A graph  220  at the top of the figure shows the threshold voltage distribution in a group of memory cells that are programmed using Gray mapping. A graph  224  at the bottom of the figure shows the threshold voltage distribution in a group of memory cells that are programmed using binary mapping. 
     When using Gray mapping (graph  220 ), four programming levels  228 A . . .  228 D represent the bit value combinations “11”, “10”, “00” and “01”, respectively. (In this example, the left-hand-side bit denotes the LSB and the right-hand-side bit denotes the MSB.) As can be seen in the figure, adjacent programming levels differ from one another by only one bit value. In order to read the LSBs of these cells, R/W unit uses an LSB read threshold  232 , positioned between levels  228 B and  228 C. The MSBs are read using two MSB read thresholds  236 , positioned between levels  228 A and  228 B and between levels  228 C and  228 D. Note that in Gray mapping, no read threshold is common to the LSB and MSB. 
     When using binary mapping (graph  224 ), four programming levels  240 A . . .  240 D represent the bit value combinations “11”, “10”, “01” and “00”, respectively. In this scheme, the R/W unit reads the LSB using an LSB read threshold positioned between levels  240 B and  240 C. The MSB is read using three MSB read thresholds  236 , positioned between levels  240 A and  240 B, between levels  240 B and  240 C, and between levels  240 C and  240 D. In the binary mapping scheme, error events between programming levels  240 B and  240 C (i.e., erroneously deciding that a cell that was programmed to level  240 B belongs to level  240 C, or vice versa) causes both an LSB error and an MSB error. Therefore, the error performance of this scheme is inferior to the Gray mapping scheme. Note also that in the binary scheme there is some commonality between the LSB and MSB read threshold. In the example of graph  224 , the read threshold between programming levels  240 B and  240 C (referred to as “the middle read threshold”) is common to both LSB and MSB readout. 
     In some embodiments, when using memory devices that use binary mapping, the memory controller compensates for the inferior error performance by re-using information from the readout of one bit (page) in the readout of another bit (page). Information re-use across different bits (pages) is possible because of the commonality between read thresholds. 
     Consider, for example, the binary mapping scheme of graph  224 . Assume that the LSB page was decoded successfully (after error correction). Typically, some of the read LSB values were erroneous but were corrected by the ECC. Erroneous LSB readout is caused by a storage value falling on the wrong side of the middle read threshold (i.e., by a cell that belongs to level  240 C but whose threshold voltage fell below the middle read threshold, or by a cell that belongs to level  240 B but whose threshold voltage fell above the middle read threshold). The memory controller can identify the memory cells in which the LSB was read incorrectly, since these errors were corrected by the ECC. 
     Since the middle read threshold is common to both LSB and MSB readout, a memory cell in which the LSB was read incorrectly also corresponds to an MSB error. Therefore, in some embodiments, the memory controller identifies the memory cells in which the LSB was read incorrectly, and flips (reverses) the MSB value of these memory cells. Assuming the MSB errors are distributed uniformly among the three MSB read thresholds, this flipping operation corrects approximately a third of the MSB errors. 
     As can be appreciated, the re-using information from one page in the readout of another page involves additional computations and incurs additional latency. In some embodiments, the memory controller may invoke this re-use mechanism only when reverting to the redundancy storage area, i.e., only if an initial attempt to reconstruct the data based on the data storage area (without re-use across different pages) fails. 
     The example embodiments shown in  FIG. 8  correspond to four-level memory cells. In alternative embodiments, however, the disclosed technique can be applied in memory cells storing any other suitable number of programming levels, such as eight-level or sixteen-level memory cells. 
     Conditional Use of the Redundancy Storage Area Based on Cell Refreshing Ad Other Criteria 
     In some embodiments, the memory controller refreshes the data in the memory cells, on a periodic basis or otherwise. Refreshing a group of memory cells (e.g., a block) typically involves copying the data stored in the memory cells to another storage location (e.g., to another block). Occasional cell refreshing avoids long retention periods, in which the cell storage values may drift considerably and cause read errors. Refreshing schemes for analog memory cells are described, for example, in U.S. Pat. Nos. 6,731,557 and 7,397,697, whose disclosures are incorporated herein by reference. 
     In some embodiments, the memory controller may hold information as to the refreshing status of different memory cells or cell groups (e.g., blocks). The memory controller may use this information to decide whether or not to access and use the redundancy information stored in the redundancy storage area. For example, the memory controller may decide to reconstruct certain user data based on both the data storage area and the redundancy storage area if the memory cells that store this data (in the data storage area) have not been refreshed for longer than a predefined time period. 
     In particular, if the memory controller concludes that the memory cells that store certain data were not refreshed for a long time period (i.e., that a long time period has elapsed since the data was stored or re-programmed), it may decide to skip any initial attempt to reconstruct the data based on only the data storage area. This feature assumes that such an initial attempt is likely to fail because the memory cells in question are not sufficiently fresh. 
     Additionally or alternatively, the memory controller may decide whether or not to fetch and use the redundancy information stored in the redundancy storage area based on any other suitable criterion, such as based on the estimated cell wear level (e.g., the number of programming and erasure cycles that the cells have gone through). 
     It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Metadata:
Filing Date: 20090901
Publication Date: 20150203
Grant Date: 20150203
Priority Date: 20080902
Inventors: SHALVI OFIR
ROTBARD BARAK
GOLOV OREN
ANHOLT MICHA
PERLMUTTER URI
Assignee: APPLE INC
CPC Classifications: [{"code": "G06F11/1012", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F11/1072", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/3404", "inventive": true, "first": true, "tree": "[]"}, {"code": "G11C2029/0411", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C16/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C2029/4402", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C2029/4402", "inventive": false, "first": false, "tree": "[]"}, {"code": "G11C5/005", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C2029/0411", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F11/1072", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/3404", "inventive": true, "first": true, "tree": "[]"}, {"code": "G11C5/005", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F11/1012", "inventive": true, "first": false, "tree": "[]"}, {"code": "G11C16/00", "inventive": false, "first": false, "tree": "[]"}]
Family ID: 52395867