PATENT DOCUMENT

Publication Number: US-11989640-B2
Application Number: US-202217991373-A
Country: US
Kind Code: B2

Title: Scalable neural network processing engine

Abstract:
Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

Claims:
What is claimed is: 
     
       1. A neural processor circuit, comprising:
 a plurality of neural engine circuits that are each configured for selective activation, each of the neural engine circuits configured to perform convolution operations on input data and kernel coefficients to generate output data, at least two of the neural engine circuits each comprising a plurality of multiply-add (MAD) circuits; 
 a neural task manager circuit configured to provide configuration data to the neural engine circuits to activate or deactivate one or more of the neural engine circuits for a task; 
 a kernel direct memory access (DMA) circuit configured to send kernel data to activated neural engine circuits of the neural engine circuits; and 
 a data buffer having a scalable size that is based on a number of the activated neural engine circuits. 
 
     
     
       2. The neural processor circuit of  claim 1 , wherein the data buffer is shared among the plurality of neural engine circuits, the data buffer in communication with a memory external to the neural processor circuit, the data buffer configured to store the input data from the memory for sending to the neural engine circuits and the output data received from different post-processors of the neural engine circuits. 
     
     
       3. The neural processor circuit of  claim 2 , wherein the data buffer is further configured to allocate memory space for storing the input data and the output data responsive to receiving the configuration data from the neural task manager circuit. 
     
     
       4. The neural processor circuit of  claim 3 , wherein the neural processor circuit includes a buffer DMA coupled to the memory and the data buffer, the buffer DMA configured to retrieve the input data from the memory and provide the input data to the memory space of the data buffer according to the configuration data. 
     
     
       5. The neural processor circuit of  claim 2 , wherein the kernel DMA circuit is further configured to allocate memory space for storing the kernel data responsive to receiving the configuration data from the neural task manager circuit. 
     
     
       6. The neural processor circuit of  claim 2 , further comprising a processor coupled to the memory, the processor configured to generate the configuration data defining tasks that instantiate one or more neural networks. 
     
     
       7. The neural processor circuit of  claim 2 , wherein each of the plurality of neural engines circuits operates in a power saving mode when deactivated. 
     
     
       8. The neural processor circuit of  claim 1 , wherein the neural task manager circuit is further configured to store tasks in a task queue based on a task list. 
     
     
       9. The neural processor circuit of  claim 8 , wherein the neural processor circuit operates in a power saving mode when deactivated. 
     
     
       10. A method for processing input data, comprising:
 selectively activating a plurality of neural engine circuits of a neural processor circuit, each of the neural engine circuits configured to perform convolution operations on input data and kernel coefficients to generate output data, at least two of the neural engine circuits each comprising a plurality of multiply-add (MAD) circuits; 
 providing configuration data to the neural engine circuits to activate or deactivate one or more of the neural engine circuits for a task; 
 and 
 sending kernel data to activated neural engine circuits of the neural engine circuits; and 
 storing the input data in a data buffer of the neural processor circuit, wherein the data buffer has a scalable size that is based on a number of the activated neural engine circuits. 
 
     
     
       11. The method of  claim 10 , further comprising receiving the output data from different post-processors of the neural engine circuits. 
     
     
       12. The method of  claim 10 , further comprising allocating memory space of the data buffer for storing the input data and the output data responsive to the configuration data. 
     
     
       13. The method of  claim 12 , further comprising retrieving the input data from a memory and providing the input data to the memory space of the data buffer according to the configuration data. 
     
     
       14. The method of  claim 10 , further comprising:
 allocating memory space of a kernel direct memory access (DMA) circuit for storing the kernel data responsive to the configuration data; and 
 storing the kernel data in the kernel DMA circuit. 
 
     
     
       15. The method of  claim 10 , further comprising generating the configuration data defining tasks that instantiate one or more neural networks. 
     
     
       16. The method of  claim 10 , wherein each of the plurality of neural engines circuits operates in a power saving mode when deactivated. 
     
     
       17. The method of  claim 10 , further comprising providing the configuration data to the neural processor circuit to activate or deactivate the neural processor circuit for a task. 
     
     
       18. The method of  claim 17 , wherein the neural processor circuit operates in a power saving mode when deactivated. 
     
     
       19. An integrated circuit (IC) system comprising a neural processor circuit, the neural processor circuit comprising:
 a plurality of neural engine circuits that are each configured for selective activation, each of the neural engine circuits configured to perform convolution operations on input data and kernel coefficients to generate output data, at least two of the neural engine circuits each comprising a plurality of multiply-add (MAD); 
 a neural task manager circuit configured to provide configuration data to the neural engine circuits to activate or deactivate one or more of the neural engine circuits for a task; 
 a kernel direct memory access (DMA) circuit configured to send kernel data to activated neural engine circuits of the neural engine circuits; and 
 a data buffer having a scalable size that is based on a number of the activated neural engine circuits. 
 
     
     
       20. The IC system of  claim 19 , wherein the data buffer is shared among the plurality of neural engine circuits, the data buffer in communication with a memory external to the neural processor circuit, the data buffer configured to store the input data from the memory for sending to the neural engine circuits and the output data received from different post-processors of the neural engine circuits.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application of U.S. patent application Ser. No. 15/971,882 filed on May 4, 2018, which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field of the Disclosure 
     The present disclosure relates to a circuit for implementing a neural network and more specifically to scalable processing of neural network tasks. 
     2. Description of the Related Arts 
     An artificial neural network (ANN) is a computing system or model that uses a collection of connected nodes to process input data. The ANN is typically organized into layers where different layers perform different types of transformation on their input. Extensions or variants of ANN such as convolution neural network (CNN), deep neural networks (DNN), recurrent neural networks (RNN) and deep belief networks (DBN) have come to receive much attention. These computing systems or models often involve extensive computing operations including multiplication and accumulation. For example, CNN is a class of machine learning technique that primarily uses convolution between input data and kernel data, which can be decomposed into multiplication and accumulation operations. 
     Depending on the types of input data and operations to be performed, these machine learning systems or models can be configured differently. Such varying configuration would include, for example, pre-processing operations, number of channels in input data, kernel data to be used, non-linear function to be applied to convolution result, and applying of various post processing operations. Using a central processing unit (CPU) and its main memory to instantiate and execute machine learning systems or models of various configuration is relatively easy because such systems or models can be instantiated with mere updates to code. However, relying solely on the CPU for various operations of these machine learning systems or models would consume significant bandwidth of a central processing unit (CPU) as well as increase the overall power consumption. 
     SUMMARY 
     Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit may include multiple engine circuits that are selectively activated or deactivated to support parallel processing of input data according to configuration data that programs the neural processor circuit to instantiate or implement a neural network. The neural processor circuit includes a plurality of neural engine circuits, a data buffer, and a kernel extract circuit. The neural engine circuits are selectively activated, and each of the neural engine circuits are configured to perform convolution operations on input data and kernel coefficients to generate output data. The data buffer is between the plurality of neural engine circuits and a memory external to the neural processor circuit. The data buffer stores the input data from the memory for sending to the neural engine circuits and the output data received from the neural engine circuits. The kernel extract circuit receives kernel data from the memory external to the neural processor circuit, and sends a corresponding kernel coefficient extracted from the kernel data to neural engine circuits selected for activation. 
     In some embodiments, a neural task manager circuit configured to provide configuration data to the neural engine circuits to activate or deactivate one or more of the neural engine circuits for a task. 
     In some embodiments, the data buffer allocates memory space for storing the input data and the output data responsive to receiving the configuration data from the neural task manager circuit. 
     In some embodiments, the kernel extract circuit allocates memory space for storing the kernel data responsive to receiving the configuration data from the neural task manager. 
     In some embodiments, the neural task manager circuit configured to provide configuration data to the neural processor circuit to activate or deactivate the neural processor circuit for a task. An electronic device may include multiple neural processor circuits that are selectively activated or deactivated. 
     In some embodiments, a plurality of neural engine circuits of a neural processor circuit are selectively activated. Each of the neural engine circuits is configured to perform convolution operations on input data and kernel coefficients to generate output data. The input data is stored in a data buffer of the neural engine circuit for sending to the neural engine circuits and the output data received from the neural engine circuits. A corresponding kernel coefficient extracted from kernel data is sent to neural engine circuits selected for activation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a high-level diagram of an electronic device, according to one embodiment 
         FIG.  2    is a block diagram illustrating components in the electronic device, according to one embodiment. 
         FIG.  3    is a block diagram illustrating a neural processor circuit, according to one embodiment. 
         FIG.  4    is a block diagram of a neural engine in the neural processor circuit, according to one embodiment. 
         FIG.  5    is a conceptual diagram illustrating loops for processing input data at the neural processor circuit, according to one embodiment. 
         FIG.  6    is a conceptual diagram illustrating segmenting the input data into slices, tiles and work units, according to one embodiment. 
         FIG.  7    is a diagram illustrating programming of rasterizers in components of the neural processor circuit, according to one embodiment. 
         FIG.  8    is a flowchart illustrating a method of processing input data in a neural processor circuit, according to one embodiment. 
         FIG.  9    is a schematic block diagram illustrating a neural network represented by a task list of tasks, according to one embodiment. 
         FIG.  10    is a block diagram illustrating a neural task manager, according to one embodiment. 
         FIG.  11    is a diagram illustrating retrieval of task descriptors using a task queue, according to one embodiment. 
         FIG.  12    is a diagram illustrating a task descriptor, according to one embodiment. 
         FIG.  13    is a block diagram illustrating a fetch queue and a configuration queue of a neural task manager, according to one embodiment. 
         FIG.  14    is a flowchart illustrating a method of managing tasks in a neural processor circuit, according to one embodiment. 
         FIG.  15    is a block diagram illustrating multiple neural processor circuits in an electronic device, according to one embodiment. 
         FIG.  16    is a block diagram illustrating a kernel extract circuit of a neural engine, according to one embodiment. 
         FIG.  17    is a flowchart illustrating a method of processing input data with a scalable neural processor circuit, according to one embodiment 
     
    
    
     The figures depict, and the detail description describes, various non-limiting embodiments for purposes of illustration only. 
     DETAILED DESCRIPTION 
     Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, the described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments. 
     Embodiments of the present disclosure relate to a scalable neural processor circuit that includes a plurality of neural engines that can be selectively activated to instantiate neural networks. For a processing cycle, a data buffer of the neural processor circuit (e.g., coupled to a system memory and the first and second neural engine circuits) provides input data to each of the neural engine circuits that are active. Each of the active neural engine circuits may apply different kernel coefficients to the input data to generate different output data. The size of the data buffer and kernel memories that store kernel data may also be modified. 
     Exemplary Electronic Device 
     Embodiments of electronic devices, user interfaces for such devices, and associated processes for using such devices are described. In some embodiments, the device is a portable communications device, such as a mobile telephone, that also contains other functions, such as personal digital assistant (PDA) and/or music player functions. Exemplary embodiments of portable multifunction devices include, without limitation, the iPhone®, iPod Touch®, Apple Watch®, and iPad® devices from Apple Inc. of Cupertino, California Other portable electronic devices, such as wearables, laptops or tablet computers, are optionally used. In some embodiments, the device is not a portable communications device, but is a desktop computer or other computing device that is not designed for portable use. In some embodiments, the disclosed electronic device may include a touch sensitive surface (e.g., a touch screen display and/or a touch pad). An example electronic device described below in conjunction with  FIG.  1    (e.g., device  100 ) may include a touch-sensitive surface for receiving user input. The electronic device may also include one or more other physical user-interface devices, such as a physical keyboard, a mouse and/or a joystick. 
     Figure ( FIG.  1    is a high-level diagram of an electronic device  100 , according to one embodiment. Device  100  may include one or more physical buttons, such as a “home” or menu button  104 . Menu button  104  is, for example, used to navigate to any application in a set of applications that are executed on device  100 . In some embodiments, menu button  104  includes a fingerprint sensor that identifies a fingerprint on menu button  104 . The fingerprint sensor may be used to determine whether a finger on menu button  104  has a fingerprint that matches a fingerprint stored for unlocking device  100 . Alternatively, in some embodiments, menu button  104  is implemented as a soft key in a graphical user interface (GUI) displayed on a touch screen. 
     In some embodiments, device  100  includes touch screen  150 , menu button  104 , push button  106  for powering the device on/off and locking the device, volume adjustment buttons  108 , Subscriber Identity Module (SIM) card slot  110 , head set jack  112 , and docking/charging external port  124 . Push button  106  may be used to turn the power on/off on the device by depressing the button and holding the button in the depressed state for a predefined time interval; to lock the device by depressing the button and releasing the button before the predefined time interval has elapsed; and/or to unlock the device or initiate an unlock process. In an alternative embodiment, device  100  also accepts verbal input for activation or deactivation of some functions through microphone  113 . The device  100  includes various components including, but not limited to, a memory (which may include one or more computer readable storage mediums), a memory controller, one or more central processing units (CPUs), a peripherals interface, an RF circuitry, an audio circuitry, speaker  111 , microphone  113 , input/output (I/O) subsystem, and other input or control devices. Device  100  may include one or more image sensors  164 , one or more proximity sensors  166 , and one or more accelerometers  168 . The device  100  may include components not shown in  FIG.  1   . 
     Device  100  is only one example of an electronic device, and device  100  may have more or fewer components than listed above, some of which may be combined into a components or have a different configuration or arrangement. The various components of device  100  listed above are embodied in hardware, software, firmware or a combination thereof, including one or more signal processing and/or application specific integrated circuits (ASICs). 
       FIG.  2    is a block diagram illustrating components in device  100 , according to one embodiment. Device  100  may perform various operations including image processing. For this and other purposes, the device  100  may include, among other components, image sensor  202 , system-on-a chip (SOC) component  204 , system memory  230 , persistent storage (e.g., flash memory)  228 , motion (orientation) sensor  234 , and display  216 . The components as illustrated in  FIG.  2    are merely illustrative. For example, device  100  may include other components (such as speaker or microphone) that are not illustrated in  FIG.  2   . Further, some components (such as motion sensor  234 ) may be omitted from device  100 . 
     Image sensor  202  is a component for capturing image data and may be embodied, for example, as a complementary metal-oxide-semiconductor (CMOS) active-pixel sensor a camera, video camera, or other devices. Image sensor  202  generates raw image data that is sent to SOC component  204  for further processing. In some embodiments, the image data processed by SOC component  204  is displayed on display  216 , stored in system memory  230 , persistent storage  228  or sent to a remote computing device via network connection. The raw image data generated by image sensor  202  may be in a Bayer color kernel array (CFA) pattern (hereinafter also referred to as “Bayer pattern”). 
     Motion sensor  234  is a component or a set of components for sensing motion of device  100 . Motion sensor  234  may generate sensor signals indicative of orientation and/or acceleration of device  100 . The sensor signals are sent to SOC component  204  for various operations such as turning on device  100  or rotating images displayed on display  216 . 
     Display  216  is a component for displaying images as generated by SOC component  204 . Display  216  may include, for example, liquid crystal display (LCD) device or an organic light emitting diode (OLED) device. Based on data received from SOC component  204 , display  216  may display various images, such as menus, selected operating parameters, images captured by image sensor  202  and processed by SOC component  204 , and/or other information received from a user interface of device  100  (not shown). 
     System memory  230  is a component for storing instructions for execution by SOC component  204  and for storing data processed by SOC component  204 . System memory  230  may be embodied as any type of memory including, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) RAMBUS DRAM (RDRAM), static RAM (SRAM) or a combination thereof. In some embodiments, system memory  230  may store pixel data or other image data or statistics in various formats. 
     Persistent storage  228  is a component for storing data in a non-volatile manner. Persistent storage  228  retains data even when power is not available. Persistent storage  228  may be embodied as read-only memory (ROM), flash memory or other non-volatile random access memory devices. 
     SOC component  204  is embodied as one or more integrated circuit (IC) chip and performs various data processing processes. SOC component  204  may include, among other subcomponents, image signal processor (ISP)  206 , a central processor unit (CPU)  208 , a network interface  210 , sensor interface  212 , display controller  214 , neural processor circuit  218 , graphics processor (GPU)  220 , memory controller  222 , video encoder  224 , storage controller  226 , and bus  232  connecting these subcomponents. SOC component  204  may include more or fewer subcomponents than those shown in  FIG.  2   . 
     ISP  206  is hardware that performs various stages of an image processing pipeline. In some embodiments, ISP  206  may receive raw image data from image sensor  202 , and process the raw image data into a form that is usable by other subcomponents of SOC component  204  or components of device  100 . ISP  206  may perform various image-manipulation operations such as image translation operations, horizontal and vertical scaling, color space conversion and/or image stabilization transformations, as described below in detail with reference to  FIG.  3   . 
     CPU  208  may be embodied using any suitable instruction set architecture, and may be configured to execute instructions defined in that instruction set architecture. CPU  208  may be general-purpose or embedded processors using any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, RISC, ARM or MIPS ISAs, or any other suitable ISA. Although a single CPU is illustrated in  FIG.  2   , SOC component  204  may include multiple CPUs. In multiprocessor systems, each of the CPUs may commonly, but not necessarily, implement the same ISA. 
     Graphics processing unit (GPU)  220  is graphics processing circuitry for performing graphical data. For example, GPU  220  may render objects to be displayed into a frame buffer (e.g., one that includes pixel data for an entire frame). GPU  220  may include one or more graphics processors that may execute graphics software to perform a part or all of the graphics operation, or hardware acceleration of certain graphics operations. 
     Neural processor circuit  218  is a circuit that performs various machine learning operations based on computations including multiplication, addition and accumulation. Such computations may be arranged to perform, for example, convolution of input data and kernel data. Neural processor circuit  218  is a configurable circuit that performs these operations in a fast and power-efficient manner while relieving CPU  208  of resource-intensive operations associated with neural network operations. Neural processor circuit  218  may receive the input data from sensor interface  212 , the image signal processor  206 , system memory  230  or other sources such as network interface  210  or GPU  220 . The output of neural processor circuit  218  may be provided to various components of device  100  such as the image signal processor  206 , system memory  230  or CPU  208  for various operations. The structure and operation of neural processor circuit  218  is described below in detail with reference to  FIG.  3   . 
     Network interface  210  is a subcomponent that enables data to be exchanged between devices  100  and other devices via one or more networks (e.g., carrier or agent devices). For example, video or other image data may be received from other devices via network interface  210  and be stored in system memory  230  for subsequent processing (e.g., via a back-end interface to image signal processor  206 , such as discussed below in  FIG.  3   ) and display. The networks may include, but are not limited to, Local Area Networks (LANs) (e.g., an Ethernet or corporate network) and Wide Area Networks (WANs). The image data received via network interface  210  may undergo image processing processes by ISP  206 . 
     Sensor interface  212  is circuitry for interfacing with motion sensor  234 . Sensor interface  212  receives sensor information from motion sensor  234  and processes the sensor information to determine the orientation or movement of the device  100 . 
     Display controller  214  is circuitry for sending image data to be displayed on display  216 . Display controller  214  receives the image data from ISP  206 , CPU  208 , graphic processor or system memory  230  and processes the image data into a format suitable for display on display  216 . 
     Memory controller  222  is circuitry for communicating with system memory  230 . Memory controller  222  may read data from system memory  230  for processing by ISP  206 , CPU  208 , GPU  220  or other subcomponents of SOC component  204 . Memory controller  222  may also write data to system memory  230  received from various subcomponents of SOC component  204 . 
     Video encoder  224  is hardware, software, firmware or a combination thereof for encoding video data into a format suitable for storing in persistent storage  128  or for passing the data to network interface  210  for transmission over a network to another device. 
     In some embodiments, one or more subcomponents of SOC component  204  or some functionality of these subcomponents may be performed by software components executed on ISP  206 , CPU  208  or GPU  220 . Such software components may be stored in system memory  230 , persistent storage  228  or another device communicating with device  100  via network interface  210 . 
     Image data or video data may flow through various data paths within SOC component  204 . In one example, raw image data may be generated from the image sensor  202  and processed by ISP  206 , and then sent to system memory  230  via bus  232  and memory controller  222 . After the image data is stored in system memory  230 , it may be accessed by video encoder  224  for encoding or by display  116  for displaying via bus  232 . 
     Example Neural Processor Circuit 
     Neural processor circuit  218  is a configurable circuit that performs neural network operations on the input data based at least on kernel data  340 . For this purpose, neural processor circuit  218  may include, among other components, neural task manager  310 , a plurality of neural engines  314 A through  314 N (hereinafter collectively referred as “neural engines  314 ” and individually also referred to as “neural engine  314 ”), kernel direct memory access (DMA)  324 , data buffer  318  and buffer DMA  320 . Neural processor circuit  218  may include other components not illustrated in  FIG.  3   . 
     Each of neural engines  314  performs computing operations for neural network operations in parallel. Depending on the load of operation, entire set of neural engines  314  may be operated or only a subset of the neural engines  314  may be operated while the remaining neural engines  314  are placed in a power save mode to conserve power. Each of neural engines  314  includes components for storing one or more kernels, for performing multiply-accumulate operations, and for post-processing to generate an output data  328 , as described below in detail with reference to  FIG.  4   . One example of a neural network operation is a convolution operation. 
     Neural task manager  310  manages the overall operation of neural processor circuit  218 . Neural task manager  310  may receive a task list from a compiler executed by CPU  208 , store tasks in its task queues, choose a task to perform, and send instructions to other components of the neural processor circuit  218  for performing the chosen task. Neural task manager  310  may also perform switching of tasks on detection of events such as receiving instructions from CPU  208 . In one or more embodiments, the neural task manager  310  sends rasterizer information to the components of the neural processor circuit  218  to enable each of the components to track, retrieve or process appropriate portions of the input data and kernel data, as described below in detail with reference to  FIGS.  5  through  7   . Although neural task manager  310  is illustrated in  FIG.  3    as part of neural processor circuit  218 , neural task manager  310  may be a component outside the neural processor circuit  218 . 
     Kernel DMA  324  is a read circuit that fetches kernel data from a source (e.g., system memory  230 ) and sends kernel data  326 A through  326 N to each of the neural engines  314 . Kernel data represents information from which kernel elements can be extracted. In one embodiment, the kernel data may be in a compressed format which is decompressed at each of neural engines  314 . Although kernel data provided to each of neural engines  314  may be the same in some instances, the kernel data provided to each of neural engines  314  is different in most instances. 
     Data buffer  318  is a temporary storage for storing data associated with the neural network operations. In one embodiment, data buffer  318  is embodied as a memory that can be accessed by all of the neural engines  314 . Data buffer  318  may store input data  322 A through  322 N for feeding to corresponding neural engines  314 A through  314 N, as well as output from each of neural engines  314 A through  314 N for feeding back into neural engines  314  or sending to a target circuit (e.g., system memory  230 ). The operations of data buffer  318  and other components of the neural processor circuit  218  are coordinated so that the input data and intermediate data stored in the data buffer  318  is reused across multiple operations at the neural engines  314 , and thereby reduce data transfer to and from system memory  230 . Data buffer  318  may be operated in a broadcast mode where input data of all input channels are fed to all neural engines  314  or in a unicast mode where input data of a subset of input channels are fed to each neural engine  314 . 
     The input data  322  stored in data buffer  318  can be part of, among others, image data, histogram of oriented gradients (HOG) data, audio data, meta data, output data  328  of a previous cycle of the neural engine  314 , and other processed data received from other components of the SOC component  204 . 
     Buffer DMA  320  includes a read circuit that receives a portion (e.g., tile) of the input data from a source (e.g., system memory  230 ) for storing in data buffer  318 , and a write circuit that forwards data from data buffer  318  to a target (e.g., system memory). 
     Example Neural Engine Architecture 
       FIG.  4    is a block diagram of the neural engine  314 , according to one embodiment. The neural engine  314  performs various operations to facilitate neural network operations such as convolution, spatial pooling and local response normalization. The neural engine  314  receives the input data  322 , performs multiply-accumulate operations (e.g., convolution operations) on the input data  322  based on stored kernel data, performs further post-processing operations on the result of the multiply-accumulate operations, and generates the output data  328 . The input data  322  and/or the output data  328  of the neural engine  314  may be of a single channel or multiple channels. 
     Neural engine  314  may include, among other components, input buffer circuit  402 , computation core  416 , neural engine (NE) control  418 , kernel extract circuit  432 , accumulators  414  and output circuit  424 . Neural engine  314  may include further components not illustrated in  FIG.  4   . 
     Input buffer circuit  402  is a circuit that stores a portion of the input data  322  as it is received from the data buffer  318  and sends an appropriate portion  408  of input data for a current task or process loop to computation core  416  for processing. Input buffer circuit  402  includes a shifter  410  that shifts read locations of input buffer circuit  402  to change the portion  408  of input data sent to computation core  416 . By changing portions of input data provided to the computation core  416  via shifting, neural engine  314  can perform multiply-accumulate for different portions of input data based on fewer number of read operations. In one or more embodiments, the input data  322  includes data of difference convolution groups and/or input channels. 
     Kernel extract circuit  432  is a circuit that receives kernel data  326  from kernel DMA  324  and extracts kernel coefficients  422 . In one embodiment, the kernel extract circuit  432  references a look up table (LUT) and uses a mask to reconstruct a kernel from compressed kernel data  326 . The mask indicates locations in the reconstructed kernel to be padded with zero and remaining locations to be filled with numbers. The kernel coefficients  422  of the reconstructed kernel are sent to computation core  416  to populate register in multiply-add (MAD) circuits of computation core  416 . In other embodiments, the kernel extract circuit  432  receives kernel data in an uncompressed format and the kernel coefficients are determined without referencing a LUT or using a mask. 
     Computation core  416  is a programmable circuit that performs computation operations. For this purpose, the computation core  416  may include MAD circuits MAD 0  through MADN and a post-processor  428 . Each of MAD circuits MAD 0  through MADN may store an input value in the portion  408  of the input data and a corresponding kernel coefficient in the kernel coefficients  422 . The input value and the corresponding kernel coefficient are multiplied in each of MAD circuits to generate a processed value  412 . 
     Accumulator  414  is a memory circuit that receives and stores processed values  412  from MAD circuits. The processed values stored in accumulator  414  may be sent back as feedback information  419  for further multiply and add operations at MAD circuits or sent to post-processor  428  for post-processing. Accumulator  414  in combination with MAD circuits form a multiply-accumulator (MAC)  404 . In one or more embodiments, accumulator  414  may have subunits where each subunit sends data to different components of neural engine  314 . For example, during a processing cycle, data stored in a first subunit of accumulator  414  is sent to MAC circuit while data stored in a second subunit of accumulator  414  is sent to post-processor  428 . 
     Post-processor  428  is a circuit that performs further processing of values  412  received from accumulator  414 . The post-processor  428  may perform operations including, but not limited to, applying nonlinear functions (e.g., Rectified Linear Unit (ReLU)), normalized cross-correlation (NCC), merging the results of performing neural operations on 8-bit data into 16-bit data, and local response normalization (LRN). The result of such operations is output from the post-processor  428  as processed values  417  to output circuit  424 . 
     NE control  418  controls operations of other components of the neural engine  314  based on the operation modes and parameters of neural processor circuit  218 . Depending on different modes of operation (e.g., group convolution mode or non-group convolution mode) or parameters (e.g., the number of input channels and the number of output channels), neural engine  314  may operate on different input data in different sequences, return different values from accumulator  414  to MAC circuits, and perform different types of post-processing operations at post processor  428 . To configure components of the neural engine  314  to operate in a desired manner, the NE control  418  sends a control signal to components of the neural engine. NE control  418  may also include rasterizer  430  that tracks the current task or process loop being processed at neural engine  314 , as described below in detail with reference to  FIG.  5  through  7   . 
     Output circuit  424  receives processed values  417  from the post-processor  428  and interfaces with data buffer  318  to store processed values  417  in data buffer  318 . For this purpose, output circuit  424  may send out as output data  328  in a sequence or a format that is different from the sequence or format in which the processed values  417  are processed in post-processor  428 . 
     The components in the neural engine  314  may be configured during a configuration period by the NE control  418  and the neural task manager  310 . For this purpose, the neural task manager  310  sends configuration information to the neural engine  314  during the configuration period. The configurable parameters and modes may include, but are not limited to, mapping between input data elements and kernel elements, the number of input channels, the number of output channels, performing of output strides, and enabling/selection of post-processing operations at the post processor  428 . 
     Operation of Segmenting of Data for Processing at Neural Processor Circuit 
     Input data is typically split into smaller pieces of data for parallel processing at multiple neural engines  314 . Often multiple cycles of operations are performed to generate output for a task associated with a neural network. A compiler executed by CPU  208  analyzes the hierarchy and nodes of the neural network and determines how the input data is to be segmented based on the hardware constraints of the neural processor circuit  218 . One of functions of the compiler is to determine how input data is to be split into smaller data units for processing at the neural engines  314 , and how the processing is to be iterated in loops to produce the result for tasks. 
       FIG.  5    is a conceptual diagram illustrating loops for processing the input data at neural processor circuit  218 , according to one embodiment. The outermost loop represents processing for a convolution group, if group convolution involving multiple convolution group is used. Group convolutions are convolutions where input data of the input channels in each group are used only for generating output data of output channels of each group but are not used for generating output data for output channels of other groups. Hence, each group of the group convolution can be treated as a separate convolution operation. 
     In the loop for each convolution group is a processing loop for a slice of the input data. The entire input data for a convolution operation is segmented into multiple strips of slices in an overlapping manner, as shown in  FIG.  6   . The overlapping portions  602 ,  604 ,  606  are parts of the input data that are overfetched in two adjacent slices to provide spatial support for a corresponding kernel. The second outermost loop performs convolution operation for each slice in the input data. Within the loop for a slice is a processing loop for a tile of the slice. Each slice is segmented into a plurality of tiles, as shown in  FIG.  6   . The overlapping portions  608 ,  610 ,  612 ,  614  are parts of the input data in slice  4  that are overfetched in two adjacent tiles to provide spatial support for a corresponding kernel. The rightmost tile will typically have a width smaller than other tiles of the slice. In one embodiment, input data for each tile is loaded onto data buffer  318  in a read cycle and reused for operations in processing loops for the tile. In the processing loop for the tile is a processing loop for a work unit. Each tile is segmented into multiple work units as shown in  FIG.  6   . A work unit is a portion of the input data having a size that produces output values that fit into accumulator  414  of neural engine  314  during a single cycle of the computation core  416 . Although the shape of each work unit is shown as a horizontal strip in  FIG.  6   , the shape of the work unit can be different depending on the shape and size of the tile. The work units also have overlapping parts that represent overfetched data to provide support for a corresponding kernel. Especially, work units for the last tile of a slice may have a shape of a vertical strip if the tile is tall. In one or more embodiments, the size of each work unit is 256 bytes. In such embodiments, for example, work units be shaped to one of 16×16, 32×8, 64×4, 128×2 or 256×1 dimension. 
     For each work unit, an internal processing loop may be provided for an output channel group (OCG). The number of output channels produced for a given work unit by a single cycle of the computation core  416  is referred to as an OCG. Depending on operation modes, each neural engine  314  may process output data of different numbers of output channels (e.g., 8 channels, 32 channels) for a single load of input data into its input buffer circuit  402 . 
     For each output channel group, an internal processing loop may be provided for an input channel (Cin). If an input stride is implemented to skip certain input data, loops for sub-input channels (Sub-Cin) may be provided within the processing loop for the input channel (Cin). 
     For each input channel or each sub-input channel, internal loops are provided for processing horizontal spatial support for a kernel and the vertical support within each horizontal spatial support. The spatial support refers to the input data for convolution with the kernel, and includes overfetched input data for performing convolution at the edges of the input data. 
     Overfetch refers to fetching additional input data in current slice, tile or work unit so that proper dimension of input data can be provided for convolution with a kernel. In one or more embodiments, overfetch is performed vertically between slices to obtain additional rows of input data (shown as overlapping portions  602 ,  604 ,  606  in  FIG.  6   ), horizontally between tiles to obtain additional columns of input data (shown as overlapping portions  608 ,  610 ,  612 ,  614  in  FIG.  6   ), and vertically between work units within a tile to obtain additional rows of input data. 
     For each spatial support for the kernel, an internal processing loop for an output channel (OC) is provided to generate output data for each output channel (Cout). In cases where output stride implements a spatial upsampling, an additional inner loop for processing each sub-output channel is provided. Loading of kernel coefficients and MAC operations are performed within the loop for the output channel (OC) or sub-output channel if an output stride is implemented, to generate output data for the output channel (OC) or sub-output channel. 
     The nested loop structure of  FIG.  5    is merely illustrative. Loops may be omitted, added or structured differently depending on various factors. For example, if only a single convolution group is used, the outermost loop may be removed. Further, the loop structure for the horizontal spatial support and the vertical spatial support may be reversed. 
     In one or more embodiments, the operations associated dividing the input space into smaller units and processing these smaller units as described above with reference to  FIGS.  5  and  6    are performed by rasterizers  714 ,  718 ,  720 ,  722  in various components of neural processor circuit  218 . A rasterizer is a circuit in various components of neural processor circuit  218  that keeps track of the segment of the input/output data (e.g., group, work unit, input channel, output channel) and instructs the components of neural processor circuit for proper handling of the segment of the input data. For example, rasterizer  720  in buffer DMA  320  tracks tiles and slices received from system memory  230  while rasterizer  718  in data buffer  318  broadcasts in sequence work units for processing by the neural engines  314 . Rasterizer  722  in kernel DMA  322  determines which kernels are to be received and distributed to neural engines  314 , while rasterizers  714  in neural engines  314  operate shifters  410  in input buffer circuits  402  to forward correct portions  408  of input data to MAC  404 , and send the finished output data  328  to the data buffer  318 . 
       FIG.  7    is a diagram illustrating programming of rasterizers  714 ,  718 ,  720 ,  722  in components  314 ,  318 ,  320 ,  322  of the neural processor circuit  218 , according to one embodiment. To perform their functions, each of rasterizers  714 ,  718 ,  720 ,  722  receives task information  710  (e.g., configuration data) indicating how the input data and/or kernel data are to be segmented and to be handled by each component of the neural processor circuit  218 . The task information includes information about particulars of the current layer (e.g., dimensions of input and output data, dimension of an associated kernel, types of padding at the boundaries of input data). Rasterizers  714 ,  718 ,  720 , and  722  may also receive constraints on their operations (e.g., whether to allow or disallow tile width over a threshold). 
     By providing rasterizers in different components of neural processor circuit  218 , overhead in data transmitted between the components of the neural processor circuit  218  may be reduced. If a single central rasterizer is provided to control different components of the neural processor circuit  218 , kernel data, input data, and output data transmitted between the components may be needed in these data to identify associated position in the loops of the task such as convolution group, tile, slice, work unit, input channel and output channel. By using distributed rasterizers, no separate metadata is needed to transmit the kernel data, input data and output data among components of the neural processor circuit  218 . 
     Example Process at Neural Engine Architecture 
       FIG.  8    is a flowchart illustrating a method of processing input data in neural processor circuit  218 , according to one embodiment. The method may include different and/or additional steps, or the steps may be in different orders. 
     After neural task manager  310  programs rasterizers  714 ,  718 ,  720 ,  722 , the process of operating buffer DMA  320  is initiated by rasterizer  720  instructing  804  buffer DMA  320  to cause buffer DMA  320  to receive a tile of input data from system memory  230 . The tile received by buffer DMA  320  is stored  806  in data buffer  318 . 
     Rasterizer  718  in data buffer  318  then instructs  808  data buffer  318  to send a work unit to one or more neural engines  314 . The work unit is then stored in input buffer circuits  402  of the one or more neural engines  314 . 
     In one or more embodiments, input buffer circuit  402  selects  816  a portion of work unit to be sent to MAC  404  to perform multiply-accumulate operation. Then MAC  404  performs  820  multiply-accumulate operations on the selected portion of the work unit using a corresponding kernel. Then it is determined  824  if the entire work unit is processed at one or more neural engines  314 . If not, the selected portion of the work unit is shifted  828  by shifter  410  and returns to perform  820  another round of multiply-accumulate operations. 
     If it is determined  824  that the entire work unit was processed, then it proceeds to determine  832  if all work units in the tile was processed. If not, then the process proceeds  836  to the next work unit by having data buffer  318  send  808  a next work unit to one or more neural engines  314 , and repeats the subsequent processes. 
     If it is determined  832  that all work units in the tile was processed by the neural engines  314 , the process proceeds to determine  840  whether all tiles for the input data were processed. If not, the process proceeds  844  to a next tile by having rasterizer  720  instructs  804  buffer DMA  320  to receive a next tile from system memory  230  and repeats the subsequent processes. 
     If it is determined  840  that all tiles of the input data are processed, then the process ends for the current input data. Then, the process may be repeated to process the next input data or proceed to the next task. 
     Embodiments of the process as described above with reference to  FIG.  8    are merely illustrative. Further loops may be embodied, as described above with reference to  FIG.  5   . Moreover, sequence of the process may be modified or omitted. 
     A neural network may include network layers or sub-layers that are instantiated or implemented as a series of tasks executed by the neural processor circuit  218 .  FIG.  9    is a schematic block diagram illustrating a neural network  900  represented by a list  904  of tasks, according to one embodiment. The neural network  900  includes network layers (or sub-layers) including convolution layers C1, C2, C3 (including sub-layers C3 00 , C3 10 , C3 11 , C3 20 , and C3 21 ), C5, and C6, and pooling layers P2 and P4. The neural network  900  is an example of a neural network architecture that may be instantiated by the neural processor circuit  218 . That is, when the neural network  900  is converted into the task list  904  to become executable by the neural processor circuit  218 . Other types of neural network architectures with different types of network layers or orders of network layers may also be instantiated by the neural processor circuit  218 . 
     The neural network  900  is converted, such as by the CPU  208 , to the task list  904 . The task list  904  includes a linear link-list defining a sequence of tasks including task C1, task C2+P2, task C3 00 +P4, task C3 10 , task C3 11 +P4, task C3 20 , task C3 21 +P4, task C5 a , task C5 b , and task C6. Each task is associated with a task descriptor that defines a configuration of the neural processor circuit  218  to execute the task. Each task may correspond with a single network layer of the neural network  900 , a portion of a network layer of the neural network  900 , or multiple network layers of the neural network  900 . For example, the task C1 corresponds with a single network layer C1, the task C2+P2 corresponds with multiple network layers C2 and P2, and the tasks C5 a  and C5 b  each correspond with a portion of the network layer C5. The neural processor circuit  218  instantiates the neural network  900  by executing the tasks of the task list  904  under the control of the neural task manager  310 . 
       FIG.  10    is a block diagram illustrating the neural task manager  310 , according to one embodiment. The neural task manager  310  manages the execution of tasks for one or more neural networks  900  by the neural processor circuit  218 . The neural task manager  310  may include, among other components, a task arbiter  1002 , task queues  1004 A through  1004 N (hereinafter collectively referred as “task queues  1004 ” and individually also referred to as “task queue  1004 ”), a task manager direct memory access (DMA)  1006 , a fetch queue  1008 , and a configuration queue  1010 . The neural task manager  310  may include other components not illustrated in  FIG.  10   . 
     The task arbiter  1002  is a circuit or a combination of circuit and firmware that selects tasks from the task queues  1004  for execution by the neural processor circuit  218 . The task arbiter  1002  dequeues tasks from the task queues  1004 , and places tasks in the configuration queue  1010 . While a task is in a configuration queue, it is committed to execution and the neural processor circuit performs a prefetch for input data and kernel data before the task is executed by other components of the neural processor circuit  218 . For example, the task arbiter  1002  may perform fixed-priority arbitration between multiple task queues  1004 , and select the task from the task queues  1004  with the highest priority for retrieval of a task descriptor  1012  from the system memory  230  by the task manager DMA  1006 . 
     The neural task manager  310  may include one or more task queues  1004 . Each task queue  1004  is coupled to the CPU  208  and the task arbiter  1002 . Each task queue  1004  receives from the CPU  208  a reference to a task list  904  of tasks that when executed by the neural processor circuit  218  instantiates a neural network  900 . The reference stored in each task queue  1004  may include a set of pointers and counters pointing to the task list  904  of the task descriptors  1012  in the system memory  230 . Each task queue  1004  may be further associated with a priority parameter that defines the relative priority of the task queues  1004 . The task descriptor  1012  of a task specifies a configuration of the neural processor circuit  218  for executing the task. 
     The task manager DMA  1006  is coupled to task arbiter  1002 , the system memory  230 , and the fetch queue  1008 . The task manager DMA  1006  includes a read circuit that receives task descriptors  1012  of tasks from a source (e.g., system memory  230 ) for storing in the fetch queue  1008 . For example, the task arbiter  1002  selects a task queue  1004  according to the priorities of the task queues  1004 , and uses the task list  904  referenced by the selected task queue  1004  to control the task manager DMA  1006  to select the task descriptor  1012  of a task. 
     The fetch queue  1008  is a single entry queue that stores a task descriptor  1012  of a task that is pending to commit for execution. The fetch queue  1008  is coupled to the task manager DMA  1006  to receive the task descriptor  1012  from the system memory  230 , and provides the task descriptor  1012  to the configuration queue  1010 , or the configuration data  1014  extracted from the task descriptor  1012  to the configuration queue  1010 . 
     The configuration queue  1010  holds configuration data  1014  of multiple tasks that have been committed for execution. When a task is in the configuration queue  1010 , the kernel DMA  324  may fetch kernel data from the system memory  230  to store in the kernel extract circuit  432  of neural engines  314 , and the buffer DMA  320  may fetch input data from the system memory  230  to store in the data buffer  318 . To execute the task, the kernel extract circuit  432  provides the prefetched kernel data to the MAC  404  of the neural engine  314 , and the data buffer  318  provides the prefetched input data to the MAC  404  of the neural engine  314 . In some embodiments, the configuration queue  1010  may include multiple queues that holds configuration data  1014  extracted from the committed task descriptors  1012 . As discussed in greater detail in connection with  FIG.  13   , the configuration queue  1010  is further coupled to other components of the neural processor circuit  218  to configure the neural processor circuit  218  according to the configuration data  1014 . 
       FIG.  11    is a diagram illustrating retrieval of task descriptors  1012  using a task queue  1004 , according to one embodiment. The task queue  1004  includes a reference, such as a set of pointers, to the task descriptors  1012 A through  1012 N stored in the system memory  230 . To that end, the task queue  1004  may include a memory storing a head parameter  1102 , a network identifier (ID)  1104 , a base address index  1106 , a tail parameter  1108 , a count parameter  1110 , and a priority parameter  1112 . The head parameter  1102  is a pointer to a location of the system memory  230  storing the task descriptor  1012 A at the head of the task queue  1004 . The network ID  1104  identifies the neural network  900  of the task descriptor  1012  at the head of the task queue  1004 , and the base address index  1106  is an index to a base-address table  1114  tagged with the network ID  1104  of the task descriptor  1012 A at the head of the task queue  1004 . The count parameter  1110  defines the number of task descriptors  1012  in the task queue  1004 . The priority parameter  1112  defines the priority of the task queue  1004 , which is used by the task arbiter  1002  to select between multiple task queues  1004 . 
     When a particular task queue  1004  is selected (e.g., according to the priority parameter  1112 ), the task arbiter  1002  references the head parameter  1102 , the network ID  1104 , the base address index  1106 , and the base address table  1114  to retrieve a task descriptor  1012  from the system memory  230 , and places the task descriptor  1012  into the fetch queue  1008  to initiate commitment of the task for execution. In each configuration period, the task arbiter  1002  may continue to place a task descriptor  1012  into the fetch queue  1008  according to the order of tasks defined by the task list  904  of the task queue  1004 , such as by retrieving the next task descriptor  1012 B, and so forth. 
       FIG.  12    is a diagram illustrating a task descriptor  1012 , according to one embodiment. The task arbiter  1002  places the task descriptor  1012  in the fetch queue  1008  from system memory  230 , which is then transferred to the configuration queue  1010 . The highest priority (e.g., first in) task descriptor  1012  in the configuration queue  1010  is used to configure the neural processor circuit  218  for execution during the configuration period. The task descriptor  1012  includes configuration data  1014  including a task descriptor header  1202  and address data  1204 A through  1204 N (hereinafter referred as “address data  1204 ”). The task descriptor header  1202  includes configuration data  1014  that configures various operations of the neural task manager  310 , including operations related to task selection and task switching. For example, the task descriptor header  1202  may be parsed by the task arbiter  1002  to extract configuration data  1014  that programs the neural task manager  310  and other components of the neural processing circuit  218 . The task descriptor header  1202  may include a task identifier (ID)  1206  that identifies the task, a neural network identifier (ID)  1208  that identifies a neural network  900  instantiated by the task, a task switch parameter  1210  defining whether the neural task manager  310  should initiate a task switch (e.g., to execute a task of a different task queue  1004 ) after execution of the task, an input surface parameter  1212  defining whether the input data for the task should be retrieved from the system memory  230  or the data buffer  318 , an output surface parameter  1214  defining whether the output data of the task should be stored in the system memory  230  or the data buffer  318 , various (e.g., base address) pointers  1216  to facilitate the programming of the neural processor circuit  218 , and one or more debug/exception parameters  1218  that control event, exception, or debug logging. 
     Each instance of address data  1204 A through  1204 N (collectively or individually referred to as “address data  1204 ”) defines an address and data payload pair used to program the components of the neural processor circuit  218 . The data payload may include input data and kernel data used to execute the task. For example, each instance of address data  1204  includes register data defining the data payload, a register address defining a destination memory location of the neural processing circuit  218  for receiving the register data, and a register count defining a number of consecutive memory locations (e.g., registers) to be written with the register data. In some embodiments, the register address is combined with the base address stored in the header  1202  to define the full address of each memory location. If the task descriptor  1116  is generated at compile time, then the actual run time addresses may not be known. The base address table  1114  is used avoid duplicating or updating all task descriptors with dynamically assigned addresses. 
       FIG.  13    is a block diagram illustrating the fetch queue  1008  and configuration queue  1010 , according to one embodiment. The configuration queue  1010  is coupled to the fetch queue  1008 , which is coupled to the system memory  230  via the task manager DMA  1006 . The configuration queue  1010  is further coupled to the rasterizer  714  of one or more neural engines  314 , the rasterizer  718  of the data buffer  318 , the rasterizer  720  of the buffer DMA  320 , and the rasterizer  722  of the kernel DMA  322 . The fetch queue  1008  stores a task descriptor  1012  (e.g., including the task descriptor header  1202  and the address data  1204 A through  1204 N) for a task that is pending and not committed to execution. The fetch queue  1008  reduces the latency of reading the next task descriptor  1012  into the configuration queue  1010  from the system memory  230 . The fetch queue  1008  stores the highest priority task descriptor  1012  as determined by the task arbiter  1002 . The task arbiter  1002  may replace the task descriptor  1012  stored in the fetch queue  1008  if a higher priority task descriptor  1012  has been has been enqueued (e.g., from a higher priority task queue  1004 ). The task descriptor  1012  in the fetch queue  1008  does not initiate an input data or kernel prefetch, and does not affect task queue priorities, pointers, or counters. As such, a task descriptor  1012  in the fetch queue  1008  may be readily replaced by a higher priority task descriptor  1012  by writing the higher priority task descriptor  1012  into the fetch queue  1008 . When a task descriptor  1012  stored in the configuration queue  1010  is executed by the neural processor circuit  218 , the task descriptor  1012  stored in the fetch queue  1008  is transferred to the configuration queue  1010 , and another task descriptor  1012  of a subsequent task may be stored in the fetch queue  1008 . 
     The configuration queue  1010  stores task descriptors  1012  of tasks committed for execution by the neural processor circuit  218 . In some embodiments, the configuration queue  1010  includes multiple separate queues  1310  that each store a portion of the configuration data  1014  (including configuration data  1014 A through  1014 E) extracted from the task descriptor  1012 . Furthermore, the queues  1310  are each coupled to a respective component of the neural processor circuit  218  for programming the component with the configuration data  1014 . Through operation of the configuration queue  1010 , the neural task manager  310  programs the rasterizers  714 ,  718 ,  720 ,  722  to perform the functionality discussed above in  FIGS.  7  and  8   . For example, a queue  1310 A is coupled to the rasterizers  714  of the neural engines  314  to provide configuration data  1014 A that controls the operations of the shifters  410  in the input buffer circuits  402  to forward correct portions  408  of input data to MAC  404 , and send the finished output data  328  to the data buffer  318 . The queue  1310 B is coupled to the rasterizer  718  of the data buffer  318  to provide configuration data  1014 B that controls the broadcasting of input data (e.g., work units) by the data buffer  318  for processing by the neural engines  314 . The queue  1310 C is a read queue that is coupled to the rasterizer  720  of the buffer DMA  320  to provide configuration data  1014 C that controls the buffer DMA  320  to retrieve input data (e.g., a tile) from system memory  230  and store the input data in the data buffer  318 . The queue  1310 D is a write queue that is coupled to the rasterizer  720  of the buffer DMA  320  to provide configuration data  1014 D that controls the buffer DMA  320  to store output data in the system memory  230 . The queue  1310 E is coupled to the rasterizer  722  of the kernel DMA  322  to provide configuration data  1014 E that controls which kernels are to be received and distributed to neural engines  314 . In some embodiments, a task descriptor  1012  or configuration data  1014  stored in the configuration queue  1010  cannot be replaced and will be executed in a first in, first out (FIFO) order. 
     Example Process at Neural Task Manager Architecture 
       FIG.  14    is a flowchart illustrating a method of managing tasks in the neural processor circuit  218 , according to one embodiment. The method may include different and/or additional steps, or the steps may be in different orders. 
     The CPU  208  generates  1402  a task list  904  of task descriptors  1012  of tasks that when executed by the neural processor circuit  218  instantiates a neural network  900 . For example, the CPU  208  may receive input data for a machine learning operation from the image sensor  202 , the system memory  230 , the persistent storage  228 , the network interface  210 , or some other components. The machine learning operation may include an inferencing operation, or a training operation. The neural network  900  may include kernel data and a neural network architecture including network layers. The input data is applied to the neural network  900  to perform the machine learning operation. The kernel data and network layers of the neural network  900  may be computed in a machine learning training process. The CPU  208  performs a compile operation (offline or on-the-fly) to turn a neural network description  900  into a linked list of ask descriptors  1012  referred to herein as the task  904 . Each task is defined by a task descriptor  1012 , and when executed by the neural processor circuit  218  instantiates a single network layer, multiple network layers, or a portion of a network layer. Each task descriptor  1012  of a task includes configuration data  1014 , such as the task descriptor header  1202  and the address data  1204  defining neural processor circuit  218  address and data payload pairs. The data payload may include the kernel data of the neural network  900  and the input data. The configuration data  1014  further includes instructions that configure operation of the rasterizers  714 ,  718 ,  720 , and  722  to execute the task. 
     The CPU  208  stores  1404  the task list  904  of task descriptors  1012  in the system memory  230 . In some embodiments, the CPU  208  or another CPU external to the electronic device  100  generates the task descriptors  1012  and stores the task descriptors  1012  in the persistent storage  228  or some other non-volatile memory. The task descriptors  1012  are loaded along with the kernel data and input data in the system memory  230  for use by the neural processor circuit  218 . The CPU  208  may be coupled to the system memory  230  via the bus  232  and the memory controller  222 . 
     The task list  904  may include a set of pointers that reference the locations of the task descriptors  1012  in the system memory  230 . Furthermore, the CPU  208  may update parameters of the task descriptors  1102  such as memory addresses or the network ID. For example, the task list  904  may include a head parameter  1102  and a tail parameter  1108  respectively defining a beginning register address and an end register addresses of the system memory  230  where multiple tasks descriptors  1012  are stored. In some embodiments, the references to the register addresses in the task list  904  may be partial addresses, and a base address table  1114  is used to define the full reference addresses to the system memory  230 . In some embodiments, the CPU  208  may patch absolute addresses as necessary. The CPU  208  may further configure the neural processor circuit  218  by setting its base address registers. 
     The task arbiter  1002  of the neural task manager  310  enqueues  1406  the task list  904  for execution by the neural processor circuit  218 . For example, the neural task manager  310  includes multiple task queues  1004 A through  1004 N. The task queues  1004  may each store a reference to a task list  904 . Furthermore, the task queues  1004  are prioritized for execution according to the priority parameters  1112  of the task lists  904  referenced by the task queues  1004 . 
     In some embodiments, the CPU  208  performs a general configuration of the neural processor circuit  218  to execute the task. The CPU  208  may further start the neural processor circuit  218  if the neural processor circuit  218  is not already running. 
     The task arbiter  1002  selects  1408  a task queue with highest priority for execution. For example, the task arbiter  1002  in each programming period selects a task queue  1004  based a comparison of priority parameters of the task queues  1004  or the task lists  904  of the task queues  1004 , and executes tasks from the task list  904  from the highest priority task queue  1004 . 
     The neural processor circuit  218  executes  1410  a task from the selected task queue. For example, the neural processor circuit  218  performs the method of  FIG.  8    to execute the task. The configuration queue  1010  of the neural task manager  310  may provide the configuration data  1014  (or task information  710 ) to the rasterizers  714 ,  718 ,  720 ,  722  of the neural processor circuit  218  to program the neural processor circuit  218  to execute the task, as shown in  FIG.  7   . Furthermore, the execution of the task may include processing of the prefetched kernel data and input data while the task was in the configuration queue  1010 . The execution of each task may include multiple processing loops for handling the input data as shown in  FIGS.  5  and  6   . The task arbiter  1002  may dequeue the task from the configuration queue  1010  after execution of the task. 
     In some embodiments, to execute the task, the task arbiter  1002  controls the task manager DMA  1006  to retrieve the task descriptor  1012  of the task of the task list  904 , and store the task descriptor  1012  in the fetch queue  1008 . After execution of a previously committed task, the task arbiter  1002  may dequeue the executed task by removing the task descriptor or configuration data of the task from the configuration queue  1010 . The task descriptor  1012  or extracted configuration data  1014  of the current task is then placed in the configuration queue  1010  from the fetch queue  1008 . When the task is in the configuration queue  1010 , the neural processor circuit  218  may initiate a prefetch operation by the kernel DMA  324  for kernel data from the system memory  230  to the kernel extract circuit  432 , and a prefetch operation by the buffer DMA  320  for input data from the system memory  230  to the data buffer  318 . 
     If a different task queue has a higher priority, a task switch to the task queue with the higher priority may be performed when possible. To perform a task switch (e.g., to another machine learning operation), the task arbiter  1002  replaces a task in the fetch queue  1008  with another task descriptor referenced in a different task queue  1004 . The task arbiter  1002  may resume the interrupted machine learning operation defined by the task list  904  after completion of the task switch by storing the replaced task into the fetch queue  1008 . 
     In some embodiments, the CPU  208  determines  1408  a priority parameter  1110  of the task list  904  to select a task queue. The priority parameter  1110  defines the priority of the tasks of the machine learning operation relative to other tasks of other machine learning operations executed by the neural processor circuit  218 . The CPU  208  may facilitate the execution of multiple machine learning operations. The machine learning operations may be different, such as by using different input data or different neural network architectures and kernel data. The CPU  208  may determine the priority parameter of the task list  904  programmatically, or based on user input. The task descriptor  1012  referenced by the task queue  1004  with the highest priority may be selected for execution. The priority of a task queue is either determined by the CPU  208 , Of dynamically by information from a previously executed task descriptor. 
     The task arbiter  1002  determines  1412  whether all tasks of the task list  904  have been executed. If a task of the task list  904  has not been executed, the process returns to step  1410 , where the task arbiter  1002  executes the unexecuted task of the task list  904 . 
     If each task of the task list  904  has been executed, the task arbiter  1002  removes  1414  the task list  904  from the task queue  1004 . In another example, a reference to a task descriptor  1012  of a task may be removed from the task queue  1004  subsequent to execution of the task. The process may end. In another example, the process may return to  1402 , where the CPU  208  may continue to generate task descriptors of tasks for other machine learning operations. In that sense, the process may be repeated to place tasks into task queues for execution of machine learning operations by the neural processor circuit  218  according to specified task priorities. 
     Scalable Neural Engines 
     Various components of the electronic device  100  and the neural processor circuit  218  may be scalable to facilitate parallel processing of machine learning operations. Configuration data for tasks may define the selective usage of hardware components. 
     The neural engines  314  of a neural processor circuit  218  may be selectively activated or deactivated for particular tasks. With reference to  FIG.  3   , for example, the neural processor circuit  218  includes the neural engines  314 A through  314 N. In some examples, the neural processor circuit  218  may include two, eight, or sixteen neural engines  314 . Each of the neural engines  314  is coupled to the data buffer  318 . In some embodiments, the data buffer  318  broadcasts the same input data to each activated neural engines  314  in a processing cycle. In the processing cycle, each of the neural engines apply different or the same kernel coefficients to the input data to generate different output values. For example, output data from different neural engines  314  in a processing cycle may include output data associated with different channels. One or more neural engines  314  of the neural processor circuit  218  may be deactivated for the processing cycle. Deactivation may result in the neural engine  314  being turned off or placed in a power saving mode (e.g., using less power than when activated). 
     In some embodiments, the data buffer  318  stores a tile of input data, and provides a work unit of the tile, or a portion of a work unit of the tile, to the neural engines  314  in a processing cycle. The neural engines  314  may apply different kernel coefficients so that different operations on the work unit of the tile may be processed in parallel by multiple neural engines  314 . As such, the number of processing cycles used to process input data by a neural processor circuit  218  can be decreased by using additional neural engines  314  in the neural processor circuit  218 . In another example, a neural engine  314  may be deactivated if not used in processing a task to reduce power consumption. 
     Scalable Neural Processor Circuits 
     An electronic device may include different numbers of neural processor circuits  218 , with each neural processor circuit  218  being selectively activated or deactivated for particular tasks.  FIG.  15    is a block diagram illustrating multiple neural processor circuits  218  in an electronic device  1500 , according to one embodiment. The electronic device  1500  includes the bus  232 , the CPU  208 , the system memory  230 , and may further include other components of the electronic device  100  as discussed above in connection with  FIG.  2   . The electronic device  1500  further includes a neural interconnect circuit  1502  coupled to the system memory  230  and neural processor circuits  218 A through  218 N. 
     The neural interconnect circuit  1502  includes a neural interconnect buffer direct memory access (DMA)  1504  and a neural interconnect data buffer  1506 . The neural interconnect buffer DMA  1504  retrieves configuration data for tasks from the system memory  230  and stores the configuration data in the neural interconnect data buffer  1506 . The neural interconnect data buffer  1506  is coupled to the buffer DMAs  320  and the data buffers  318  of each of the neural processor circuits  218 A through  218 N. The neural interconnect data buffer  1506  distributes configuration data to neural processor circuits  218 A through  218 N, such as one or more of the neural processor circuits  218 A through  218 N which are selectively activated for processing tasks. 
     In some embodiments, the neural interconnect data buffer  1506  stores a slice or work group of input data, and provides different tiles of a slice to one or more of the neural processor circuits  218 A through  218 N. The data buffers  318  of different neural processor circuits  218  may store a different tile. Each data buffer  318  of a neural processor circuit  218  may provide a work unit or a portion of a work unit of the tile stored in the data buffer  318  to each of the neural engines  314  of the neural processor circuits  218  in a processing cycle. The neural processor circuits  314  may use different input data or different kernel coefficients so that different operations on different tiles may be processed in parallel by multiple neural processor circuits  218 . In some embodiments, multiple neural processor circuits  218  may be used to process the different tasks of a neural network in parallel. In some embodiments, different neural processor circuits  218  may process tasks for different neural networks in parallel. 
     The number of processing cycles used to process input data by an electronic device  1500  can be decreased by using additional neural processor circuits  218 . If fewer than all of the neural processor circuits  218  of an electronic device are committed to task processing, one or more neural processor circuits  218  may operate in a power saving mode or be turned off while one or more other neural processor circuits  218  processes input data. 
     In some embodiments, multiple neural processor circuits  218  may each be coupled to the system memory  230 . For example, the data buffers  318  of each neural processor circuit  218  may retrieve configuration data, input data, and kernel data directly from the system memory  230 . Here, the neural interconnect circuit  1502  may be omitted from the electronic device. 
     In some embodiments, barriers may be used to support multiple neural processor circuits  218  to avoid data hazards. Data hazards occur when input data or kernel coefficients haven&#39;t arrived in the neural interconnect data buffer  1506  or system memory  230  when a neural processor circuit  218  tries to consume it. Examples of data hazards may include (1) kernel prefetch from system memory  230  to the neural interconnect data buffer  1506  followed by the neural processor circuit  218  consuming the kernel coefficients, (2) input data load from the system memory  230  to the neural interconnect data buffer  1506  followed by the neural processor circuit  218  consuming the input data, (3) neural processor circuit  218  producing output data followed by a different neural processor circuit consuming the output data as input data, (4) neural processor circuit  218  producing output data followed by the same neural processor circuit  218  consuming the output data as kernel coefficients, or (5) a neural engine  314  producing data output data followed by a neural processor circuit  218  consuming the output data. 
     In some embodiments, prefetching is performed for kernel data or kernel coefficients from system memory  230  into the neural interconnect data buffer  1506 . The neural interconnect buffer DMA  1504  needs to complete the transfer of coefficients of a given kernel before the neural processor circuit  218  consumes it. In case the neural processor circuit  218  is faster than the data transfer by the neural interconnect buffer DMA  1504 , to avoid the data hazard, the CPU  220  may configure upfront a breakpoint register inside the neural task manager  310  which stops the execution of the neural processor circuit  218  directly after a provided task II) has been reached. The breakpoint register contains this task ID bit field and an enable bit. When the neural interconnect buffer DMA  1504  completes a configurable amount of kernel coefficients, it sends an interrupt to the CPU  220  which then updates the breakpoint register to the task ID of the most recently transferred kernel coefficients. If the data transfer by the neural interconnect buffer DMA  1504  is ahead of the kernel read from the neural processor circuit  218 , everything is fine and the neural processor circuit  218  keeps running. In case the neural processor circuit  218  is faster than the data transfer by the neural interconnect buffer DMA  1504 , the neural processor circuit  218  will reach the breakpoint and stops until the neural interconnect buffer DMA  1504  has completed and the CPU  220  re-activates the neural engine  314  of the neural processor circuit  218 . 
     In the case of (4) neural processor circuit  218  producing output data followed by the same neural processor circuit  218  consuming the output data as kernel coefficients, the compiler provides the depending task ID in the task descriptor of the consuming task. The neural processor circuit  218  then avoids the hazard in hardware by making sure that the current task will not execute before the task with the depending task II) finishes execution including all DMA writes. 
     In some embodiments, a neural processor circuit  218  or other component of the electronic device  100  (e.g., CPU  220 , ISP  206 , etc.) may include a memory scale and rotate (MSR) circuit. The MSR circuit crops input patches of variable size from an input image and scales the input image to a different resolution before the input image as input data the neural processor circuit  218 . For example, the neural processor circuit  218  may instantiate a neural network that performs object detection by providing bounding boxes of potential objects of different sizes. The MSR circuit then crops these objects and scales it to the same size such that another consuming neural network performing object classification can classify these objects. 
     In some embodiments, a neural processor circuit  218  may be located in the CPU  208 , the GPU  220 , the image signal processor  206 , or other component of the electronic device  100 . The neural processor circuit  218  in another component may operate as discussed herein for a neural processor circuit  218 . For example, a neural processor circuit  218  may operate with a neural processor circuit in the CPU  208 , the GPU  220 , or the image signal processor  206  to process different tiles of a slice of input data, or otherwise process input data in parallel. 
     In some embodiments, multiple neural processor circuits  218  can either run separate neural networks, or speed up the execution of a single neural network by using the compiler to slice a network spatially (width or height), channel-wise and/or into separate branches so that these slices can be scheduled across neural processor circuits  218 . 
     Scalable Data Buffer and Kernel Extract Circuit 
     The size of the data buffer  318  of each neural processor circuit  218  may be scalable according to the number of activated neural engines  314  that are activated for a task. For example, a portion of the memory space of the data buffer  318  may be allocated to storing input data and kernel data for each neural engine  314  that is activated for performing a task. Furthermore, the total size of the data buffer  318  may correspond with the number of neural engines  314  in the neural processor circuit  218 , and the size of the MAC circuit  404  of each neural engine  314 . In some embodiments, the data buffer  318  is sufficiently sized to store the input data for a tile including work units that are broadcast to each of the neural engines  314  for each processing cycle, the kernel data to be applied to the work units in each processing cycle, and any other configuration data for each processing cycle (e.g., instructions for rasterizers). The data buffer  318  may also be sufficiently sized to store output data generated by the MAC circuits  404  of the neural engines  314  from the input data and kernel data. The output data may replace the input data for a previous processing cycle in the data buffer  318 , or may be stored in a different location of the data buffer  318 . In that sense, the size of the data buffer  318  or allocation of data to the data buffer  318  may vary to provide scalability of neural engine  314  use in a neural processor circuit  218 . 
     The size of the kernel extract circuit  432  of each neural engine  314  may be scalable to support different types of neural operations with input data. Furthermore, a kernel extract circuit  432  of a neural engine  314  may be selectively activated or deactivated with the neural engine  314 .  FIG.  16    is a block diagram illustrating a kernel extract circuit  432  of a neural engine  314 , according to one embodiment. The kernel extract circuit  432  is a component of a neural processor circuit  218 , and includes a kernel memory  1604  and a kernel decompress circuit  1606 . The kernel memory  1604  receives the kernel data  326  from the kernel DMA  324  of the neural processor circuit  218 , and stores the kernel data  326 . The kernel decompress circuit  1606  generates the kernel coefficients  422  using the kernel data  326 , and provides the kernel coefficients  422  to the MAC circuit  404  of the neural processor circuit  218 . The kernel decompress circuit  1606  converts the kernel data  326  in a compressed format into the kernel coefficients  422 . The size of the kernel memory  1604 , or the allocation of data to the kernel memory  1604 , may vary to support scalable kernel sizes. 
     In some embodiments, the number of MAD circuits in the MAC  404  of the neural engine  314  may also be scaled to support the kernel size. For example, the number of MAD circuits located or activated in a neural engine  314  may correspond with the number of kernel coefficients  422  to facilitate processing of each of the kernel coefficients  422  provided to the MAD circuits MAD 0  through MADN in a processing cycle. 
     In some embodiments, each neural engine  314  includes X number of MAD circuits. As such, N neural engines  314  in a neural processor circuit  218  provides for up to N*X operations in each processing cycle. Furthermore, M neural processor circuits  218  in an electronic device provides for up to N*M*X operations in each processing cycle. In an example, an electronic device may include a single neural processor circuit  218  (M=1) each having eight neural engines  314  (N=8) with each neural engine  314  including 256 MAD circuits (X=256) to provide for up to 2,048 operations in each processing cycle. In another example, an electronic device may include a two neural processor circuit  218  (M=2) each having sixteen neural engines  314  (N=16) with each neural engine  314  including 256 MAD circuits (X=256) to provide for up to 8,192 operations in each processing cycle. 
     In addition to the components of the electronic device  100 / 1500  and neural processing circuit  218  being scalable, various fabrics, buses, and/or interfaces that connect these components may also be scalable in size to facilitate data transfers between the components. 
     Example Scalable Process at Neural Processor Architecture 
       FIG.  17    is a flowchart illustrating a method of processing input data with a scalable neural processor circuit, according to one embodiment. The method may include different and/or additional steps, or the steps may be in different orders. 
     The CPU  208  generates  1702  configuration data of tasks according to computing resources of an electronic device. The configuration data may define the activation and deactivation of components such as neural processor circuits  218  and neural engines  318  for the task. The configuration data may also define allocation of input data into memory space of data buffers  318  of activated neural processor circuits, and allocation of kernel data into memory space of kernel memories  1604  of activated neural engines  314 . 
     The configuration data for each task may be defined by a task descriptor  1012 . The CPU  208  performs a compile operation to generate task descriptors  1012  of the tasks based on input data and the network layers of a neural network  900 , and the available computing resources. The configuration data may include the address data  1204  defining neural processor circuit  218  address and data payload pairs for input data and kernel data. In some embodiments, the CPU  208  generates configuration data of tasks for multiple neural networks that are implemented in parallel. The tasks for each neural network may be generated in a separate compile operation. 
     As discussed above, the configuration data may be generated based on the resources of the electronic device and neural processor circuit(s)  218 . For example, the CPU  208  may optimize the processing of the network layers of the neural network into tasks according to the computing resources of the electronic device including the number of neural processor circuits  218 , the number of neural engines  314  in the neural processor circuits  218 , the size of the data buffers  318  of the neural processor circuits, the number of MAD circuits in the neural engines  314 , and the size of the kernel extract circuits  432  in the neural engines  314 . The configuration data may define behavior of rasterizers to control how kernel data and input data is provided to the data buffer  318  of each activated neural processor circuit  218 . For each neural processor circuit  218 , the configuration data may define how portions of the input data and kernel coefficients extracted from the kernel data are provided to each activated neural engine  314  of the neural processor circuit  218 . If a neural processor circuit  218  or neural engine  314  is not used for a task, the configuration data may specify a deactivation of the unused component. 
     The system memory  230  stores  1704  the configuration data of the tasks. For example, the CPU  208  provides the configuration data of the tasks to the system memory  230 . Furthermore, the CPU  208  may enqueue task lists in task queues  1004  of a neural task manager  310 . 
     In some embodiments, the system memory  230  stores multiple tiles of input data. For example, the system memory  230  may store input data for a convolution group, each convolution group including multiple slices, and each slice including the multiple tiles. In some embodiments, the system memory  230  stores multiple tiles belonging to different convolution groups or different neural networks. 
     The buffer DMA  320  of a neural processor circuit  218  retrieves  1706  input data from the system memory  230  to the data buffer  318  of the neural processor circuit  218 , and the kernel DMA  324  of the neural processor circuit  218  retrieves  1706  kernel data from the system memory  230  to the buffer extract circuit  432 . For example, when the configuration data for a task is placed in the configuration queue  1010  of the neural task manager  310  of a neural processor circuit  218 , the buffer DMA  320  and kernel DMA  324  performs a prefetch for the input data and kernel data, respectively. The prefetch results in the input data being stored in the data buffer  318  and the kernel data being stored in the kernel extract circuits  432  of each neural engine  314  prior to the processing cycle for the input data and the kernel data. The size of the data buffer  318  or the kernel extract circuit  432  (e.g., the kernel memory  1604 ) may be selected to support the utilization of the neural engines  314  in the neural processor circuit  218 , and a subset of the available memory space may be allocated according to the configuration data and the activation and deactivation of the neural engines  314 . 
     In some embodiments, multiple activated neural processor circuits  218  perform the step  1706  in parallel. The buffer DMA  320  of each neural processor circuit  218  may retrieve one of the multiple tiles of input data stored in the system memory  230  according to the configuration data. Furthermore, the kernel DMA  324  of each neural processor circuit  218  retrieves kernel data to be processed with the input data retrieved by the buffer DMA  320  of the neural processor circuit  218 . 
     In some embodiments, one or more neural processor circuits  218  may be deactivated when not used in a processing cycle. The deactivation may include placing a neural processor circuit  218  in a power saving mode or powering off the neural processor circuit  218 . Here, the deactivated neural processor circuit  218  does not retrieve input data or kernel data from the system memory  230 . 
     The data buffer  318  of the neural processor circuit  218  provides  1708  a portion of the input data stored in the data buffer  318  to MAC circuits  404  of the neural engines  314  of the neural processor circuit  218 , and the kernel extract circuit  432  of the neural processor circuit  218  provides  1708  kernel coefficients generated from the kernel data to the MAC circuits  404  of the neural engines  314  of the neural processor circuit  218 . The neural engines  314  that receive the input data and kernel data may be activated neural engines  314 . One or more neural engines  314  of the neural processor circuit  218  may be deactivated, such as by being placed in a power saving mode or powered off, when not used in a processing cycle. 
     The portion of input data provided to each of the activated neural engines  314  of the neural processor circuit  218  may include a work unit of the tile of input data stored in the data buffer  318  of the neural processor circuit  218 . In some embodiments, the activated neural engines  314  of the neural processor circuit  218  receives the same (e.g., work unit or portion of a work unit) input data, and applies different kernel coefficients to the input data in a processing cycle. Multiple neural processor circuits  218  may perform step  1708  in parallel so that the neural processor circuits  218  process different input data in the processing cycle. In the same processing cycle, multiple neural engines  314  of a neural processor circuit  218  may be tasked with applying different kernel coefficients to the same input data. Here, multiple neural engines  314  may operate in parallel to generate different channels of output data in the processing cycle. In a subsequent processing cycle, the input data provided to the neural engines  314  may be different, or the kernel data used by the neural engines  314  may be different, or both. 
     The neural engines  314  of the neural processor circuit  218  generate  1710  output data using the portion of input data and the kernel coefficients. For example, each neural processing circuit  218  may generate different output data in a processing cycle based on the input data and kernel data provided to the MAC circuits  404  of the activated neural engines  314  in the processing cycle. 
     In some embodiments, the neural engines  314  perform multiple processing cycles to implement loops for processing the input data as shown in  FIGS.  5  through  8   . For example, the neural engine  314  of a neural processor circuit  218  may process different work units of a tile of input data in different processing cycles. In another example, different neural processor circuits  218  may process different tiles of a common slice of input data in a processing cycle. In another example, different neural processor circuits  218  may process different neural networks in a processing cycle, such as different tiles of different input data. 
     The neural engines  314  of the neural processor circuit  218  store  1712  the output data in the data buffer  318  of the neural processor circuit  218 . After performing one or more processing cycles, the output data from each neural engine  314  of the neural processor circuit  218  is stored in the data buffer  318  of the neural processor circuit  218 . 
     The neural task manager  310  determines  1714  for the neural processor circuit  218  whether the output data stored in the data buffer  318  of the neural processor circuit  218  is input data for a subsequent task executed by the neural processor circuit  218 . The determination may be based on the configuration data for the task, such as the output surface parameter  1214  of the task descriptor  1012  of the task. 
     If the output data stored in the data buffer  318  is input data for a subsequent task, the method returns to  1408 , where the input data and corresponding kernel coefficients are provided to MAC circuits  404  of the neural engines  314  of the neural processor circuit  218 . In the subsequent task, different components such as neural processor circuits  218  or neural engines  314  may be selectively activated or deactivated according to the configuration data of the subsequent. 
     If the output data stored in the data buffer  318  is not input data for the subsequent task, the buffer DMA  320  of the neural processor circuit  218  stores the output data from the data buffer  318  to the system memory  230 . The method may end. 
     In some embodiments, the neural processor circuit  218  may perform a prefetch operation in the processing cycle that generates the output data for subsequent input data from the system memory  230  to be processed by the neural processor circuit  218  in a subsequent processing cycle. 
     In some embodiments, the output data from a first neural processor circuit  218  is used as input data for a second neural processor circuit  218 . For example, the output data from the first neural processor circuit  218  may be stored in the system memory  230 , and the system memory  230  may provide the output data to the second neural processor circuit  218  as input data. 
     The steps  1706  through  1716  may be performed by multiple neural processor circuits  218  of the electronic device, such as in parallel to improve the speed of machine learning operations executed by the electronic device. The output data from each neural processor circuit  218  may be collected by the neural interconnect data buffer  1506  or the system memory  230 . Depending on the configuration data of tasks, the output data may be provided to one or more neural processor circuits  218  as input data for a subsequent processing cycle. 
     While particular embodiments and applications have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope of the present disclosure.

Metadata:
Filing Date: 20221121
Publication Date: 20240521
Grant Date: 20240521
Priority Date: 20180504
Inventors: NORDEN, ERIK
FISHEL, LIRAN
PARK, SUNG HEE
SHIN, JAEWON
MILLS, CHRISTOPHER L.
LEE, SEUNGJIN
MUJICA, FERNANDO A.
Assignee: APPLE INC
CPC Classifications: [{"code": "G06N3/063", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06N3/0464", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06N3/04", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06N3/08", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06N3/063", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06N3/063", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06N3/04", "inventive": true, "first": true, "tree": "[]"}, {"code": "G06N3/045", "inventive": true, "first": false, "tree": "[]"}, {"code": "Y02D10/00", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06N3/08", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06N3/045", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F13/28", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06F2213/28", "inventive": false, "first": false, "tree": "[]"}, {"code": "G06F1/3296", "inventive": true, "first": false, "tree": "[]"}, {"code": "G06N3/08", "inventive": true, "first": false, "tree": "[]"}]
Family ID: 66248700