The goal of this lab assignment is to extend the LC-3b simulator you wrote in Lab 3 to handle virtual memory. You will augment the existing LC-3b microarchitecture with facilities for virtual to physical address translation. You will also provide microarchitectural support for page fault exceptions and change the protection exception from lab #3 to be based on access mode in the PTE.
In Lab 4, the address space of the LC-3b is divided into pages of 512 locations. The LC-3b virtual address space has 128 pages, while physical memory has 32 frames. Virtual pages 0-23, which are reserved for the operating system, will be mapped to frames 0-23 and will always be resident in physical memory. Frames 24-31 are available for swapping virtual pages of user programs. There are two modes of operation: supervisor and user. Virtual pages 0-23 cannot be accessed unless the LC-3b is in supervisor mode. Since user programs operate in user mode, they cannot access those pages. Thus the user virtual memory space is 104 pages (pages 24-127).
A file holding an LC-3b program that gets loaded into virtual page 9 (x1200). This will be the interrupt service routine.
The simulator will start executing the LC-3b program loaded in page 24. The timer interrupt from lab #3 will occur only once, at cycle 300. The interrupt handler will be modified to clear the reference bits of all page table entries. If the page accessed by a user program is not valid (not in physical memory), then a page fault exception will occur. If the user program accesses a page that can only be accessed in supervisor mode, a protection exception will occur. You are supposed to provide microarchitectural support for detecting and handling these exceptions. The exception service routine you will write should simply halt the machine.
This shell code has the capability of loading the page table into memory. You will need to copy and paste the code you wrote for Lab #3 into this new shell code.
The first parameter is the microcode file as before. The second parameter is the page table in LC-3b machine language. Note that since the page table is in physical memory, the first line of this file should have a physical address. For all the program files, (including the interrupt & exception handlers) which are in virtual memory, the first line should have a virtual address.
The page table should be placed at the beginning of frame 8 of physical memory. A page table entry (PTE) contains only 9 bits of information, but for convenience, it is represented in a full 16 bit word. Thus one page table entry occupies two memory locations. The format of each page table entry is as follows:
During the execution of instructions, your microcode will have to convert virtual addresses to physical addresses, as well as modify PTE's when necessary. To make address translation possible, we have added more structures to the datapath. We have added these registers: Page Table Base Register (PTBR) and Virtual Address Register (VA). The PTBR points to the first entry of the page table in physical memory. It's used to access a particular PTE during translation. To read from this register onto the bus, you should assert the GatePTBR signal. The VA register is a temporary register to hold the current address under translation. To read the VA register onto the bus and to write to the VA register from the bus, you should assert the GateVA and LD.VA control signals respectively.
Assume that at the beginning of each address translation phase the virtual address is located in the MAR, and if the operation is a write, a source register holds the data to be written. Address translation consists of the following steps:
If the page accessed by a user program is not valid (not in physical memory), then a page fault exception will occur. The exception vector for page fault exception is x02. You will also write the exception service routine for the page fault. This routine should start at memory location x1400. For the purposes of this assignment, the exception service routine will simply halt the machine. However, don't rely on this. We can test your simulator by replacing your exception routine with our routine which returns from the exception handler using the RTI instruction instead of halting the machine. Upon return from the exception handler, the instruction that caused the exception should be re-executed.
Protection exceptions occur only when the machine is in user mode, and a memory page whose PTE protection bit is set to 0 is accessed. The memory access that causes a protection exception should not be allowed to complete. Exception vector for the protection exception is x04. The exception handler for the protection exception is located starting at x1600. This routine should halt the machine. However, as with the page fault exception, do not assume that the machine will always be halted after a protection exception occurs.
The user program in page 24 should do the following: calculate the sum of the first 20 bytes stored in the memory locations beginning with xC000 (notice this is on page 96). This sum should then be stored at xC014. Then the program should jump to the address pointed to by this sum. Page 96 contains data to be used by the program on page 24. The following numbers should be stored there:
Dump the memory locations containing the page table entries once before the 300th cycle, once after the ISR is done, and finally after the protection exception halts the execution of the program (you should get a page fault protection exception after the jump). Also, dump memory location x3814 (corresponding to which virtual address?) and the current registers after the protection exception.
The user stack should start at address 0xFE00 and the supervisor stack should start at virtual address 0x3000.
If you were unable to finish lab #3 and are hence starting from lab #2, please make a note of this in the readme. You will be unable to simulate the page fault exception, protection exception and timer interrupt if the requirements of lab #3 are not done.