Intel 8080
功能 > 指令集

| 操作码> 7 | 操作码> 6 | 操作码> 5 | 操作码> 4 | 操作码> 3 | 操作码> 2 | 操作码> 1 | 操作码> 0 | 操作数> b2 | 操作数> b3 | 助记符 | 周期数 | 描述 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | — | NOP | 4 | No operation |
| 0 | 0 | RP | RP | 0 | 0 | 0 | 1 | datlo | dathi | LXI rp,data | 10 | RP ← data |
| 0 | 0 | RP | RP | 0 | 0 | 1 | 0 | — | — | STAX rp | 7 | (RP) ← A [BC or DE only] |
| 0 | 0 | RP | RP | 0 | 0 | 1 | 1 | — | — | INX rp | 5 | RP ← RP + 1 |
| 0 | 0 | DDD | DDD | DDD | 1 | 0 | 0 | — | — | INR ddd | 5/10 | DDD ← DDD + 1 |
| 0 | 0 | DDD | DDD | DDD | 1 | 0 | 1 | — | — | DCR ddd | 5/10 | DDD ← DDD - 1 |
| 0 | 0 | DDD | DDD | DDD | 1 | 1 | 0 | data | — | MVI ddd,data | 7/10 | DDD ← data |
| 0 | 0 | RP | RP | 1 | 0 | 0 | 1 | — | — | DAD rp | 10 | HL ← HL + RP |
| 0 | 0 | RP | RP | 1 | 0 | 1 | 0 | — | — | LDAX rp | 7 | A ← (RP) [BC or DE only] |
| 0 | 0 | RP | RP | 1 | 0 | 1 | 1 | — | — | DCX rp | 5 | RP ← RP - 1 |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | RLC | 4 | A1-7 ← A0-6; A0 ← Cy ← A7 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | RRC | 4 | A0-6 ← A1-7; A7 ← Cy ← A0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | RAL | 4 | A1-7 ← A0-6; Cy ← A7; A0 ← Cy |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | RAR | 4 | A0-6 ← A1-7; Cy ← A0; A7 ← Cy |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | addlo | addhi | SHLD add | 16 | (add) ← HL |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | DAA | 4 | If A0-3 > 9 OR AC = 1 then A ← A + 6; then if A4-7 > 9 OR Cy = 1 then A ← A + 0x60 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | addlo | addhi | LHLD add | 16 | HL ← (add) |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | CMA | 4 | A ← ¬A |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | addlo | addhi | STA add | 13 | (add) ← A |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | — | — | STC | 4 | Cy ← 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | addlo | addhi | LDA add | 13 | A ← (add) |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | CMC | 4 | Cy ← ¬Cy |
| 0 | 1 | DDD | DDD | DDD | SSS | SSS | SSS | — | — | MOV ddd,sss | 5/7 | DDD ← SSS |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | HLT | 7 | Halt |
| 1 | 0 | ALU | ALU | ALU | SSS | SSS | SSS | — | — | ADD ADC SUB SBB ANA XRA ORA CMP sss | 4/7 | A ← A [ALU operation] SSS |
| 1 | 1 | CC | CC | CC | 0 | 0 | 0 | — | — | Rcc | 5/11 | If cc true, PC ← (SP), SP ← SP + 2 |
| 1 | 1 | RP | RP | 0 | 0 | 0 | 1 | — | — | POP rp | 10 | RP ← (SP), SP ← SP + 2 |
| 1 | 1 | CC | CC | CC | 0 | 1 | 0 | addlo | addhi | Jcc add | 10 | If cc true, PC ← add |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | addlo | addhi | JMP add | 10 | PC ← add |
| 1 | 1 | CC | CC | CC | 1 | 0 | 0 | addlo | addhi | Ccc add | 11/17 | If cc true, SP ← SP - 2, (SP) ← PC, PC ← add |
| 1 | 1 | RP | RP | 0 | 1 | 0 | 1 | — | — | PUSH rp | 11 | SP ← SP - 2, (SP) ← RP |
| 1 | 1 | ALU | ALU | ALU | 1 | 1 | 0 | data | — | ADI ACI SUI SBI ANI XRI ORI CPI data | 7 | A ← A [ALU operation] data |
| 1 | 1 | N | N | N | 1 | 1 | 1 | — | — | RST n | 11 | SP ← SP - 2, (SP) ← PC, PC ← N x 8 |
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | — | RET | 10 | PC ← (SP), SP ← SP + 2 |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | addlo | addhi | CALL add | 17 | SP ← SP - 2, (SP) ← PC, PC ← add |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | port | — | OUT port | 10 | Port ← A |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | port | — | IN port | 10 | A ← Port |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | — | — | XTHL | 18 | HL ↔ (SP) |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | — | — | PCHL | 5 | PC ← HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | — | — | XCHG | 4 | HL ↔ DE |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | — | — | DI | 4 | Disable interrupts |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | — | — | SPHL | 5 | SP ← HL |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | — | — | EI | 4 | Enable interrupts |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | 助记符 | 周期数 | 描述 |

| SSS DDD | SSS DDD | SSS DDD | SSS DDD | SSS DDD | 2 | 1 | 0 | CC | CC | ALU | RP |  |
| B | B | B | B | B | 0 | 0 | 0 | NZ | NZ | ADD ADI (A ← A + arg) | BC |  |
| C | C | C | C | C | 0 | 0 | 1 | Z | Z | ADC ACI (A ← A + arg + Cy) | DE |  |
| D | D | D | D | D | 0 | 1 | 0 | NC | NC | SUB SUI (A ← A - arg) | HL |  |
| E | E | E | E | E | 0 | 1 | 1 | C | C | SBB SBI (A ← A - arg - Cy) | SP or PSW |  |
| H | H | H | H | H | 1 | 0 | 0 | PO | PO | ANA ANI (A ← A ∧ arg) |  |  |
| L | L | L | L | L | 1 | 0 | 1 | PE | PE | XRA XRI (A ← A ⊻ arg) |  |  |
| M | M | M | M | M | 1 | 1 | 0 | P | P | ORA ORI (A ← A ∨ arg) |  |  |
| A | A | A | A | A | 1 | 1 | 1 | N | N | CMP CPI (A - arg) |  |  |
| SSS DDD | SSS DDD | SSS DDD | SSS DDD | SSS DDD | 2 | 1 | 0 | CC | CC | ALU |  |  |