三維晶片
注釋

↑  B. Black, D. Nelson, C. Webb, and N. Samra, "3D Processing Technology and Its Impact on iA32 Microprocessors", in Proc. of Int. Conf. on Computer Design, pp. 316-318, 2004.
1 2  S. Borkar, "3D integration for energy efficient system design", in Proc. Design Autom. Conf., 2011, pp. 214–219.
↑  Seguin, Steve. "World's First Stacked 3D Processor Created". September 16, 2008
↑  .   [2012-10-29]. （原始内容存档于2021-03-08）.
↑  3D-MAPS project webpage at Georgia Tech .   [2012-04-02]. （原始内容存档于2015-03-08）.
↑  D.Y. Chen, W. Chiou, M.F. Chen, T. Wang, K. Ching, H. Tu, W.J. Wu, C. Yu, K. Yang, H.B. Chang, M. Tseng, C.W. Hsiao, Y.J. Lu, H.P. Hu, Y.C. Lin, C. Hsu, W. Shue, C. Yu. .   [2021-08-09]. （原始内容存档于2021-11-22）.
↑  Real World Technologies. "3D Integration: A Revolution in Design". May 2, 2007. http://realworldtech.com/page.cfm?ArticleID=RWT050207213241&p=6 （页面存档备份，存于）
↑  Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/ （页面存档备份，存于）,
↑  Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/1/ （页面存档备份，存于）
↑  Xiangyu Dong and Yuan Xie, "System-level Cost Analysis and Design Exploration for 3D ICs", Proc. of Asia and South Pacific Design Automation Conference, 2009, .   [2010-05-20]. （原始内容存档于2010-04-24）.
↑  "3D IC Technology Delivers The Total Package" .   [2011-01-27]. （原始内容存档于2010-10-31）.  Electronic Design July 02, 2010
↑  James J-Q Lu, Ken Rose, & Susan Vitkavage "3D Integration: Why, What, Who, When?" .   [2008-01-22]. （原始内容存档于2008-02-12）.  Future Fab Intl. Volume 23, 2007
↑  William J. Dally, "Future Directions for On-Chip Interconnection Networks" page 17, http://www.ece.ucdavis.edu/~ocin06/talks/dally.pdf （页面存档备份，存于） Computer Systems Laboratory Stanford University, 2006
↑  Johnson, R Colin. "3-D chip stacks standardized". July 10, 2008. http://www.eetimes.com/electronics-news/4077835/3-D-chip-stacks-standardized （页面存档备份，存于）
↑  "3D-ICs and Integrated Circuit Security" http://www.tezzaron.com/about/papers/3D-ICs_and_Integrated_Circuit_Security.pdf （页面存档备份，存于） Tezzaron Semiconductor, 2008
↑  Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee. "An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth". In Proceedings of the 16th International Symposium on High-Performance Computer Architecture, pp.429-440, Bangalore, India, January, 2010.
↑  "Predicting the Performance of a 3D Processor-Memory Chip Stack" Jacob, P., McDonald, J.F. et al.Design & Test of Computers, IEEE
Volume 22, Issue 6, Nov.–Dec. 2005 Page(s):540–547
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1 2  Hsien-Hsin S. Lee and Krishnendu Chakrabarty, "Test challenges for 3D integrated circuits", IEEE Design and Test of Computers, Special issue on 3D IC Design and Test, vol. 26, no. 5, pp. 26–35, Sep/Oct 2009
↑  http://www.eetasia.com/ART_8800485666_480300_NT_fcb98510.HTM （页面存档备份，存于） "EDA's big three unready for 3D chip packaging". EE Times Asia, October 25, 2007]
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↑  .   [2012-10-29]. （原始内容存档于2014-05-17）.
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↑  .   [2011-01-27]. （原始内容存档于2011-03-14）.  "Si, glass interposers for 3D packaging: analysts' takes". Advanced Packaging August 10, 2010]
1 2 3 4  D. H. Kim, S. Mukhopadhyay, S. K. Lim, "Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs", in Proc. of Int. Workshop Sys.-Level Interconn. Pred., 2009, pp. 85–92.
↑  J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2D Blocks into 3D Chips", in Proc. of the Int. Symp. on Physical Design, pp. 81-88, 2011
↑  S. Garg, D. Marculescu, "3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs", in Proc. Int. Symp. Quality Electron. Des., 2009, pp. 147–155
↑  L. K. Scheffer, "CAD implications of new interconnect technologies", in Proc. Design Autom. Conf., 2007, pp. 576–581.
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