No - it's the massive investment in tooling.

I see comments like these all the time about 'open source bitstream generators' and whatnot. If you have a very simple, regular architecture, then P&R (place & route) is relatively simple, and has been done (there is an open-source bitstream generator for the Lattice iCE40 chips, see http://www.clifford.at/icestorm/). This line from that page in particular:
"It has a very minimalistic architecture with a very regular structure. "

For anything close to a modern FPGA, the P&R is only the start of the problem - timing is the next big one. Having a large design not meet timing can be a nightmare, but the tools take delay (extracted from the design) into account for routing, so you'd have to add that; also, I think the amount of effort to get the "hard macros"/specialized in-silicon blocks configured correctly would be amazing. You'll notice that even in the iceSTORM project, PLL's and timing analysis are not yet implemented. I use the Xilinx Zynqs at work, and they contain high speed serdes, dual-core ARM processors, and a boatload of other items.

There are large teams who are employed full-time, and frequently get their Masters/PhD with a specialty in VLSI/EDA, developing these algorithms, testing them extensively, and then implementing them. With the money someone like Xilinx brings to the table, they can pick those individuals out from school directly.

It isn't a CPU, and it never will be. I'm amazed at what free software can do, but I just don't think a team without substantial financial backing and extreme expertise could ever even approach the problem.

All of this is without even considering errata that might exist for the FPGAs, or security features at the silicon level - items which will become different immediately after a free solution is announced. Why? There's zero incentive for Xilinx to allow a free software competitor, and they have the IC designers - BOOM! The next generation adds something goofy that means a team would have to decap a chip, and start probing it. Also, said team has to be able to probe something at 28nm or below. The freaking optics for that kind of work start to get expensive by themselves, let alone the lab you need with floating tables and microsteppers (depending). A team might have to install a special floor to even get the kind of mechanical precision necessary - let that sink in. Who the hell has the money for that? I'll tell you who - other nations. We've used the security features on FPGAs (from Actel and Xilinx both) to prevent another NATION from figuring out our algorithms. The goal is to make it so costly to reverse-engineer as to make development of your own entire system seem like a saner approach.

No. There will never be an open-source bitstream generator for a modern FPGA for the same reason the Apollo project required a nation's financial backing - SpaceX can get to LEO (Low Earth Orbit). They just don't have the money, time, or manpower to get people to the moon. And if they did, they still wouldn't be "free software" - I guess a better comparison than SpaceX would be Copenhagen Suborbitals.(https://en.wikipedia.org/wiki/Copenhagen_Suborbitals)

TL;DR - No, there will never be a free software bitstream generator for any kind of modern FPGA, for a multiplicity of reasons.

EDIT: If anyone is interested in trying to do a free software FPGA, you'd have to design it from scratch and try to be a fabless semiconductor company. 1 seat of the EDA tools for IC design (on a modern node) vary - but at the last place I worked they used Mentor Calibre, and I think it was somewhere between 50/100k? It would be fun to design one on an older process, but it would be laughably expensive, slow, and power hungry compared to more modern FPGAs. Bonus though: it will have better TID (total incident dose) radiation hardness, although it wouldn't be a serious contender unless you implemented scrubbing/error detection or a unique rad-hard transistor setup (then you'd need to pay to have it sent to a reactor and tested, which is a PITA - trust me).