I've used CLaSH over most of the pass year to do all my Verilog assignments (CS major doing EE electives), and also contributed a bit to the project, so figure I'd offer some insight.

For all you saying "but sequential is the hard part". Yes functional programming is most clearly a smash-hit with combinatorial circuits, but CLaSH shines with sequential circuits too. Basically, time-varying nets are represented as infinite streams where the nth element is the value at the nth cycle. Registers are basically `cons`, they just "delay" the stream by one cycle, tacking on the initial value in front. To make complex sequential code you just "tie the knot" around the streams with `letrec`s -- which actually corresponds to exactly what the feedback loop looks like on the schematic. [Anyone that's done FRP should recognize this ideom.] In this way CLaSH is both more high-level and more low level than Verilog/VHDL: clocks nets are derived automatically, but feed back loops are explicit.

Now if you are an electrical engineer, subsisting one tedious task (routing clocks) for another (programming without "blocking assignment") might seem like no net gain. But us functional programmers are fluent at working with such fix-points, and abstracting both what we tie together an the knot-tying itself. The Moore and Mealy combinatorial are the tip of the iceberg -- examples that we hope will be more accessible to electrical engineers unfamiliar with functional programming.

For all you saying that "the hard part isn't working with the HDL at all, but lower level concerns like timing, layout, etc", I have two things.

First you are acting like HDL writing is not on the "critical path" of your development process, and thus of no concern. Well that's not just true--you can't have one engineer do HDL writing, one do layout, and one engineer do testing completely independently because there are some basic data dependencies here that linearized the development workflow. It may not be the component with the "most delay" but it's still on that critical path, and thus improving it will yield at least some speedup to some extent. Automatic layout and timing analysis is great too, but unless you have a massive amount of computing power at your disposal, AFIAK you can't get very far, so improving the HDL side of things might be the /best/ you can do.

Second, there is the development cost of finding all your bugs with low-level tools. Yes timing analysis is essential, but it's not great in diagnosing the underlying problem. If you have lots of code that, well, isn't very aesthetically pleasing, and you do all your debugging on FPGA or with timing analysis, I suppose just about all bugs look like timing issues. With CLaSH:

- You have far less code, and it's more high-level, so just reading looking for errors it is more productive.
- You can try out your code on the repl, seeing providing a stream of inputs and getting a stream of output. High level state machine errors (do you really nail this the first time with verilog?) are easily caught this way.
- Because you have more opportunities to modularize your code, you have more opportunities to test components in isolation. Unit tests vs. System tests--y'all know the deal. The former is no panacea, but obviously it makes complete code/path coverage way more tractable computationally.
- QuickCheck. I generate programs, run my single-cycle and pipeline processor for n cycles, see if they both halted and compare register/mem stage, otherwise throw out the test. I /suppose/ you could do this with C-augmented testbenches, but it would be way, way, way more code and effort. QuichCheck worked so well that I never wrote a test bench.
- EVENTUALLY, with idris or [faking it with] dependent Haskell prove your circuit correct up to the synchronous model CLaSH is built around.

In practice I can say I honestly wrote and debugged programs all from GHCi (the Haskell REPL, so very much in software land), and saw them work first time on the FPGA. Where this didn't happen was usually do to a black boxes, like megfunctions and other components on the dev board. Obviously my Haskell testing is of no use if I model them wrong in CLaSH.

Finally, it would be dishonest and misleading to not mention CLaSH's downsides. CLaSH is designed assuming your circuit is totally synchronous (or purely combinatorial, but that's the trivial case). I don't know often this comes up in the real world, but in interfacing with the components on the dead board, I often had to do things that violated rigidly synchronous circuit design --- inverting my clock to get a second 180-degree-off clock domain, asynchronous communication with SRAM. [CLaSH supports multiple clock domains, but only knows about their relative frequency, not phase.] You can often still describe these circuit in CLaSH, but because it violates its synchronous model, it won't understand them and neither will your Haskell-land testing infrastructure. Basically you loose the benefits that made CLaSH great in the first place. Fundamentally, I think true fixing these cases means designing a lower-level "asynchronous CLaSH" that both normal CLaSH and these cases can elaborate to. Trying to tack them on as special cases to CLaSH and it's synchronous modle won't fly.

But all is not lost, if you can contain the model-violation to one bit of code and give it kosher synchronous interface, you are all good. Write some Haskell to simulate what it does (need not be even in the subset CLaSH can understand), and make a Verilog/VHDL black box. CLaSH doesn't help you with that module, but that module doesn't pollute the rest of your program either. Most real-world designs are by and large synchronous, unless the world has been lying to me. So the quarantined modules would never form a significant part of your program.

That about wraps it up, ...hope somebody's still reading this thread after writing all that.