This doesn't really match my understanding of things, this is what I'm familiar with.

IC design software is too loose a term. Most, if not all, integrated circuits are designed these days using a hardware description language (VHDL and Verilog being most popular) and those languages/files have exactly the same level of source code control that any source code does, git, mercurial, CVS, etc. They are just text files, they have a build and a test processes.

Further integrated circuits can be collaboratively designed, look at FPGACPU.org as an interesting example.

This one is really hard to wrap my head around:

CLAIM: There is an absurdly high level of unsalable designs.

EVIDENCE: This occurs because there's no customer feedback loop and you can't predict the direction of the IC market.

Bad chip designs exist for the same reason that bad software exists, some people just produce bad designs. I think you were trying to argue that there are good designs that didn't get produced, but that is true for any design.

So that said lets talk about what is hard.

It is hard for me, as an individual, to get a wafer start at a fab. It is hard for me as an individual to generate masks for a specific process.

It is hard for me, as an individual, to get the circuit parameters for a particular process and so that I can do both a good layout and can tweak my masks for good yield.

It is hard for me, as an individual, to get my processed wafers diced, tested, and packaged.

Historically, getting all of those things done to convert a working chip design from simulation to testable parts, has been a few million dollars. And at the end of those millions one has (wafer size / die size ) * layout efficency * process yield * testing yield number of parts. These are divided up into one or more 'bins' (if they are still usable at different frequencies or voltages). And when I divide that number of chips by the amount of money I've spent, I've got a price per chip that has to be something the market will be willing to pay.

That is both a lot of hoops, and sitting down for betting one round costs a few million.

So what, exactly, is efabless.com de-risking? Unlike circuit boards, you can't easily put several different IC designs on the same chip and expect a fixed yield across them (sort of the OSHPark model). You can do what some folks have done which is buy "excess" capacity on older generation fabs (like Atmel's) and get a discount because you're helping them keep things running, but its still quite expensive.

The cost of failure in IC design is nearly zero. Once you've done the simulations you've just burned CPU cycles up to that point. If the process is well characterized there is exactly zero reason for a chip you produce to not work when it comes out the other end. A long time friend from my Intel days remarked that it used to be news if a chip worked the first time, now it is news if it doesn't work the first time you bake it.

I can see a challenge that low run rate chips are too expensive for the market they are trying to serve (which is why FPGAs have been growing in leaps and bounds). The original solution, ASICs which are less space efficient than bespoke designs are great for taking an FPGA design into production. So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you get even more traction you plug in the process design library and do layout for a specific process. Where does efabless fit into that?