Grumble grumble. Professional here, and I really do not like this article.

There are a lot of things getting mixed up here: ground planes for EMC, ground planes for electrical performance, ground planes for DFM/etching, and ground planes as "fashion".

First off, let's just say that meeting radiated EMC ("47 CFR Part 15" according to the article, equivalent to CISPR 22/32 in Europe) is a bloody good idea. Yes, the testing labs are "a bit of a racket". But does anyone else remember the days when turning on the vacuum cleaner would knock out the TV? That wasn't great. And we have a whole lot more electronics in the world today. A world without Part 15/CISPR is an ugly world indeed.

Four-layer boards are cheap. Really cheap. They may be double the cost, but you're doubling pennies here. In fact, just checking in with one common low-volume supplier, they're not doubling: the price for 200mm × 100mm boards with good specs goes from $9.34 each in quantity 10 to... $10.59. For prototypes, that's basically a rounding error. Perhaps even literally a rounding error. So don't complain about the cost of four-layer boards anymore, it isn't 2004.

Internal ground fill layers are what people usually mean when talking about "ground planes". They have three key properties:

1. They are very easy to do and are very tolerant of mistakes. You don't have to calculate return current paths, you don't have to size and locate return current traces, you don't have to gum up your routing. You just dedicate the layer and it works, and it keeps working if you have to make changes later.

2. They help shield internal layers further down in the stack from radiating. This is usually minor, but for nasty digital stuff or high-power electronics, can be useful.

3. They develop inter-plane capacitance with nearby power layers, if inter-layer dielectrics are small. This is critical to maintaining power distribution network performance at high frequencies (>100s of MHz). This stuff is very, very important to make high-speed digital logic work well. Of course, it's only one link in the chain (GHz stuff gets handled on-package or even on-die; <100MHz is the job of on-board capacitors until you get into power supply dynamics in the kHz and below). This is the "increasing shunt capacitance" mentioned in the article. Yes, it can be bad news for analog stuff, but this is both very rare and the sort of problem where anyone who can do that kind of difficult analog design has the skill to punch a hole in the plane where it's needed.

There is also a manufacturing issue where the manufacturers find it easiest to have approximately balanced amounts of copper on opposite layers of a board. Copper pours are one solution to this. Copper thieving pads are another. This is important but easy to manage, and vendors are good at it.

So all of the above applies to internal layer copper fills. None of it is "fashion": there are good reasons to do it, the extra layers are cheap these days, and it's an easy and robust way to design things. Fills on external layers are a different matter; they're kind of stupid in a lot of cases. Unless you're doing a two-layer design, or a 4-layer that kind of ends up behaving like a 2-layer (this happens sometimes when stuff is very tight), the external fills are pretty worthless. I wrote more about this ages ago over here: https://www.eevblog.com/forum/eda/altium-article-on-never-us... This is the only real thing I'd agree with the article on.

There's a lot of stuff going on here, and I don't think this article does a very good job keeping it straight. If you take one thing away from all of this, it should probably be that internal copper planes are pretty great, and what happens on the outside of the board isn't so important.