I am the designer of this project, and would like to thank magicalhippo who originally posted here about my work, I appreciate that my work can reach more people in that hopefully some might enjoy seeing and possibly even building it.
This reply is for people here interested in the design, who feel a certain nostalgia because I noticed there were some questions which I feel I would like to comment on to make a few things more clear, for interested users here.

I started out doing Z80 stuff since the 90s, and did a Z80 PC mainboard. It got me interested in also designing an XT system to learn from this and possibly it could benefit a later revision Z80 system because that was my favorite CPU. I did that until I found that the XT design was sufficiently user friendly and complete. The original XT schematics were relatively complete in terms of the schematics. I have seen some bare PCBs of my design being sold of my XT on a Russian website, which I was happy to see because I hope that anyone enthousiastic, feeling nostalgic about the XT machine and able to do so could have the chance to also build one. Usually you get 5 pieces from for example JLCPCB so there will be some excess boards left over. All the mainboards are not easy and require some skill level and understanding in order to be able to debug any timing related issues. It could be interesting for students for a school project.

Next I decided to look at the AT which is a completely different machine, and yet shared many similarities. The big appeal of the AT to me was the fact that the IBM team involved had the great foresight to make the 16 bit AT completely hardware and software compatible to the 8 bit XT machine. When you study the complete design, you can find that this is not a trivial matter and goes deeply into the core of the technology in order to be able to really have true backward compatibility. In doing this, the PC/AT paved the way for the industry standard to successfully evolve from it. The 16 bit 286 is limited but it deserves respect and served its role in giving humanity the PC technology. The clone builders then took off with the standard which has in it's core kept the original 5170 functionality inside it. It's pretty amazing for this machine to have survive in so many iterations of PC technology! To me this is a level of legendary invention by IBM and particularly thanks to Don Estridge.

The 5170 is a severely limited machine because it consists of a lot of TTL circuits which are vulnerable to timing problems and difficult to scale up in that configuration. The 5170 and similar TTL chipset boards are vulnerable and error prone in my experience, I tested 4 of these old boards and they all had some issues. In order to get the functionality I needed, I had to say goodbye to the TTL graveyard approach and venture into programmable logic. Initially I didn't want to do this because it's not open, but when I recreated more circuits hidden in the PAL chip U87, the scale of the whole design started to grow beyond what I am comfortable with integrating into a single mainboard, and being able to include some useful integrated I/O. The design files are shared so technically it's also openly known technology just in a programmable form. The CPLD chips are a little large, however they have the advantage of through hole sockets being possible. This makes the design more accessible for people who don't like SMD. There is a LAN chip on the board but it should be left out, my tests were not great, it seems to cause stability issues in the system so I took the chip off again. My design does support the 80287 math coprocessor, I have tested this. Please keep in mind, this was literally my first prototype PCB concept of an AT design, and took me more than a year to develop. Before my work, the AT design was only partially known openly to the world. You can see some MAME files and some previous failed attempts to reverse engineer the U87 PAL. A big and important part was hidden inside PAL chip U87, which is now openly known in a functional schematic finally. Without knowing the logic inside U87, there is no chance to fully know the system and how it works. After the 5170 it's mostly all chipset based AT PCs and these chipsets are not known.

After I had replicated a functional 5170, the next goal was clock speed above the original 8MHz. I progressed into 16MHz and then targeted to replace the 82284 and 82288 control chips inside the existing system controller CPLD. This required some level of rewiring finally to patch in an oscillator IC for the new clock signal. A lot of the development work I have done so far is the same as what chipset developers have done before. So I could learn and understand the issues they had faced before in order to get to higher clock speeds and reduce the design in size. Simply replicating the logic in a CPLD comes with a lot of timing related challenges and issues which I have had to overcome in my development.

Please note, the original 5170 used a S-BUS or system bus. Directly behind this bus on the mainboard is the M-BUS or memory bus. So in principle it's possible to move the M-BUS onto a card into the ISA slot which is what I have done. Also note, the ISA bus is simply a CPU/system bus and has no real clock operation. It's only limited looking at the system as a whole in terms of how fast the entire system is able to operate. And that limit is not 8MHz. It's much higher, at least 18 to 20MHz, depending on the configuration. My design was originally intended to be a recreation of the 5170, however it turned out to have much bigger potential far beyond that design thanks to the CPLD chips. My design is not DRAM based, it's SRAM based. So no CAS/RAS involved and no refresh. I removed all refresh functions which are not needed and to some extent free up the CPU for a few more useful cycles per second.

The next step I am working on now is a combined 286/486 system which can swap the CPU. The 486 function will be at some level in 32 bit so it is planned to support all the faster DX2 and DX4 CPUs which evolved. I will use BGA FPGA chips which have much higher integration capability and higher clock rating. This design is in the same spirit as the first revision prototype, to redo the development which was done in the 90s, however I am using more modern technology which was not available at the time. However it's about the technology at its core to be openly known and published finally, and not being lost in time because of original machines dying off. Doing this design can preserve the historic technology in a reproducable form, it's fun to me and also allows to explore the further limits and efficiency of these CPUs, hopefully the FPGAs used will be able to do this in previously unseen levels. I will be using some modern RAM like DDR or such and let the FPGA control it and interface to the legacy CPU. That's the idea. Imagine running a 486 with the full memory in the same speed as cache chips. I don't know if that's possible but I will attempt it. For more details, check out the VCF thread. The new 286/486 development follows in the same thread which started with my 286 PC/AT design. In GitHub there are separate projects published for each of my design iterations.