summary of instruction set from skimming:

encoding:

- fixed-width 32-bit instruction set;

- the instruction encoding is a little odd, with 5 formats* (or more?) and the opcode split into two parts with a couple of register numbers between them, but nothing like the bizarreness of risc-v;

- 16-bit immediates orthogonally available for all integer arithmetic and bitwise instructions (not just, say, addi);

* 3-reg (incl. base+scaled-index, jmp, lots of other things), 10-bit-imm, 16-bit-imm (which arguably includes bb0/bb1/bcnd), crs/crd, base+imm

integer:

- 31 32-bit gprs plus a zero register;

- r31 is conventionally the stack pointer, but there are no push, pop, load-multiple, store-multiple, preincrement, predecrement, postincrement, or postdecrement facilities, so there are no special hardware privileges for a stack pointer register to potentially have;

- strangely, there are separate signed and unsigned add and subtract, which suggests that it's not two's-complement. that would be tooo bizarre for 01988 but i can't find any clarification anywhere. maybe it just affects how carries are handled?

- there is an integer divide instruction, two actually;

- though it doesn't have an arm-like optional barrel shift on operand 2, it does have a pdp-8-like optional bit inversion on it;

- they remembered to include the extract- and set-bit-field instructions the arm forgot which were added in thumb(2?), and they even have fancy things like ffs and ffc, and due to the bit inversion option it even supports abjunction (and-not), or-not, and xnor;

- in fact, the extract- and set-bit-field instruction can even read the offset and width from a register (they don't have to be immediate);

- and shift-right and shift-left are special cases of them;

- the manual suggests tricks with the add instruction and the zero register to manipulate the carry bit, but i don't see suggestions for how to emulate mov, which is odd;

memory:

- load-store architecture;

- apparently no halfword or even byte load or store instructions, but the ld and st instructions have a type field which allows them to do signed and unsigned halfword and byte loads and stores, orthogonally, and even doubleword loads and stores;

- if you set the b.o. bit in the psr (cr1), your loads and stores are little-endian, which i guess motorola thought smelled bad;

- only two addressing modes (base+unsigned-immediate and base+scale×index-register, but they count the second one twice) which is a lot less than arm but still more than risc-v; they claim seven but that's because they're double-counting base+scaled-index and also counting their jump target types;

- there's a lea instruction (lea) but it's not super-powerful because it only does those two modes, and the scale only goes up to 8;

- unaligned access is not implemented, not even 4-byte-aligned access for doublewords, but there's an option to truncate the address instead of trapping (maybe useful for pointer tagging);

- there's an external line to tell the mmu whether it's in supervisor or user mode, plus a bit in load/store instructions to tell supervisor-mode code to access user memory, so plausibly they could use separate memory mappings, though i don't know if the actual mmu they shipped does this;

- there's apparently no instruction cache flush instruction, so i suspect the (off-chip) caches had to implement a very expensive i386-like memory model;

control flow:

- there's a delay slot on branches, but a bit to turn it off;

- there is no condition code register, but there are compare instructions, which store their results in a gpr. it also has some compare-and-branch instructions like risc-v, some which trap to supervisor mode and some which branch pc-relative by a signed 18-bit offset (bb0, bb1, bcnd), but no branch-if-greater-than style instructions with two source registers;

- nevertheless, the psr has a carry bit in it, which you can use with .ci or .co suffixes on arithmetic, just no carry-conditional branch instructions;

- the call instruction (bsr/jsr) uses a link register (r1) instead of a stack;

etc.:

- built-in one-issue-per-cycle ieee-754 fpu, including gradual underflow, both signaling and non-signaling nans, and both 64- and 32-bit floats, but without transcendentals or even square root;

- no obvious way for a kernel to avoid saving fpu state when context-switching from a task that didn't use it;

- i don't think you can read or write the psr in user mode, so it's standardly virtualizable, but that also means you can't switch byte orders or misaligned access handling style in user mode;

- however, you can set the fpcr in user mode, so you can change the rounding mode for your interval arithmetic library;

- their only atomic instruction for smp synchronization is xmem, exchange register with memory, which is a bit weak (though not as bad as the 68000, which iirc only had test-and-set);

- the suggested calling convention has 13 call-clobbered registers (8 for parameters);

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