The worst part is that MCM doesn't even solve this problem, actually in some ways it makes it worse. MCM solves yield not wafer cost - people conflate the two into a single die cost number but they're actually two distinct things really.

Take RDNA3 as an example. Even if you get 100% yields, you need a significant amount of additional area in the product. N31 is over 500mm2 of area even if it's yielded as a 308mm2 chiplet and six 38mm2 chiplets. Even if all of those yield at 100% you can't make it not be 500mm2 of area, and you have to pay for that.

And because MCM imposes some performance overheads that have to be compensated for, and because of the innate nature of the additional PHYs taking up area, the actual total area is larger than a monolithic chip. This is an offsetting factor in the comparison to monolithic, yes monolithic yields lower but it also needs less actual silicon too, and that pushes yields back up a touch and pushes wafer cost down a touch.

Comparisons between products are always inexact, and NVIDIA is on a slightly different node (a customized version of N4/N5P called 4N) but it's the same general family (AMD is on N5P) and 7900XTX is using 531mm2 total to compete with the 4080 which uses only 378mm2 - so we are talking about potentially a 40% area overhead for MCM, which is significant in terms of increased wafer cost even if the yields are higher.

Even if you assume RDNA3 missed expectations and "should" have performed somewhat better... we are still probably talking about a >20% area advantage for monolithic products.

https://en.wikipedia.org/wiki/List_of_AMD_graphics_processin...

https://en.wikipedia.org/wiki/List_of_Nvidia_graphics_proces...

(and, note that rumors have swirled recently that N4 and N5P are actually the same thing, they have the same density and library. Reportedly, both TSMC and Samsung faked their N4 and 4LPX libraries for marketing reasons and pushed the "true" node off, in the same way that TSMC kinda pushed off the real N3 into N3E (e for enhanced) and called the shitty version N3B (b for bad) instead... so N4 vs N5P for the basis of the 4N custom nodelet may not actually be a meaningful distinction after all, lol. And RDNA3 and Ada may actually be on the same parent node as a result.)

https://www.reddit.com/r/hardware/comments/145e9ft/tsmc_n4_i... (actual tweet seems to be removed?)

Anyway, it is the same thing in CPUs too - yes, the CCD/IO die approach is great, but, it also does use a lot more silicon than a monolithic chip would for an equivalent design. Epyc has 8 or 16 chiplets of N5P and another giant chiplet of N6 for the IO die. That's a lot of total area, and wafer costs continue to increase.

The other place it bites is in GPU dies too. PHYs don't shrink, and there are de-facto "minimums" of 4 PHYs per GPU (of any performance) imposed by actual raw bandwidth requirements and the need for 8GB of VRAM (current max is 2GB/16gbit per module unless you go clamshell, which drives up cost a ton). Every time you shrink, the wafer cost of that fixed, non-shrinkable PHY area goes up by 25% or 50%, even if you yield that area at 100%, and the performance does not increase accordingly. This is what's been eating up the gains in the low-end dGPU market, and this is the reason AMD chose not to shrink RX 7600 / Navi33 to N5P with the rest of the lineup and left it on N6 instead.

Thermals are the elephant in the room with stacking and wafer costs are the elephant in the room with MCM and PHYs. Yes, yields are better, but it doesn't mean the wafers are free either.