> I've been underwhelmed by all previous FPGAs, but maybe they didn't count. Maybe this is something new that finally manifests the original vision of what FPGAs could be.

It sounds like you're frustrated with hardware manufacturers for a slight against supporting your use case. But I think that on closer inspection, you're really frustrated with economics, physics, and the nature of the universe.

It's part of the nature of semiconductor manufacturing that manufacturing a custom ASIC (or massively-general-purpose IC?) especially a large and complex one, is going to be very expensive. There are huge non-recurring costs that can get amortized over each unit, plus economies of scale that kick in, when your masks can be used for production runs of thousands or millions of chips. It's not 10x more expensive than it should be so they can make 90% profit when you compare it per unit of silicon area against the millions of Zen3 chiplets that AMD has sold, it's 10x more expensive because it has fixed costs and they're only going to sell a few thousand of them.

As a result of that, you want to spend as little as possible to make a product that's usable by as many people as possible. If a thousand companies can use this FPGA with flash/EEPROM/fuses that have relatively low write endurance, but it's more expensive and difficult (or eliminates thousands of use cases!) to use SRAM with huge write endurance for settings that will typically be written once and, on dev units, a few dozen to a few hundred times, that's not an intentional poison pill sabotaging your career but just reasonable economics and good sense. Plus, if you're trying to recover NRE, an obvious avenue for recovery of some of those funds that you spend writing the software is to make the software proprietary so you can sell Vivado licenses to each of those customers.

On a 2-dimensional planar die, you can add a few layers, but you can't change the mathematics of graph theory to get 3D or 4D or infinite connectivity. Interconnect is just plain expensive. It's always going to be an engineering tradeoff between power dissipation and speed, so they make a best guess as to where the most applications will need interconnect, and build that. The fundamental software gates that are used to build them are always going to be slower than dedicated hardware gates, because it takes additional transistors to run a signal through them. That's why memories, ALUs, CPU cores, and peripherals on an FPGA SOC are hard-coded into the chip. They're hardcoded in ways that allow you to flexibly make use of them with custom logic, but they're burned into the die because that's better performance for their users.

You can't physically call into being a few cubic nanometers of doped silicon to form a new gate when you downlonew bitstream to an FPGA - and putting P or N doped silicon in just the right spot is critical to designing a chip, so how in the world do FPGAs actually work? They cheat, instead of building actual logic gates they just move charges to build the same truth-table out of generic SRAM-based look-up table, which means working at a layer of abstraction several steps ad a up the stack. The idealized, oversimplified, conceptual model of an FPGA as identical to a mask-programmable integrated circuit, except field-programmable, doesn't exist.