The gap has remained pretty consistent since Pascal/Vega. NVIDIA is roughly 20-30% ahead "architectural lead" (which I think is roughly approximated by perf-per-transistor perhaps with some wiggle room for node-quality and featureset, eg RDNA2 lacks tensors and has much slower RT etc). That can mean smaller dies/lower cost, or it can mean lower clocks/higher efficiency from a similar-sized die, or in the case of Ampere/Turing, older nodes+bigger dies at lower cost. Now that they've snapped back to TSMC N5 family (it's a custom 4N node, not to be confused with N4, and it's not clear whether the basis for 4N is N4 or N5P, but both N4 and N5P are N5 family) this has reappeared as performance wins and higher efficiency.

NVIDIA used older nodes on Ampere/Turing while AMD moved ahead to TSMC N7. NVIDIA is just so far ahead architecturally that they can roughly match AMD's efficiency despite a full-node gap in technology and going against (specifically) the best node in the industry.

The older node let them reduce costs, which is part of the reason why AMD has been perceived as reluctant to play the price wars during Turing/Ampere. NVIDIA was playing with older cheap nodes and AMD was basically using the best, most expensive node available just to compete (not even significantly beat), and a GPU needs a nice big chunk of it that could easily be several high-margin CPU dies instead. Nobody is ever going to publicly attribute a positive intent to NVIDIA ever, but, Ampere and Turing were an earnest effort to keep the cost down for consumers. 2080 Ti was the same $999 MSRP as the first GK110 card 10+ years ago. 3080 was so exquisitely priced that AMD sighed and dragged their feet and finally marked theirs 50 bucks less and threw in the towel and didn't barely produce it for the first year. 3060 Ti should have been the next RX 480 level value-proposition that keeps mainstream gamers happy for the next 5 years. Mining ruined everything - yet again.

The two negative consequences of this were efficiency and top-end performance. Samsung 8nm is a 10+ node, basically a full node behind TSMC N7, and obviously that has perf/w consequences. NVIDIA's architectural advantage mostly held them over but they still slid in a little under RDNA2's efficiency, when if they'd been on N7 themselves they could have easily been 20%+ more efficient. And it resulted in huge dies, because the perf/mm2 is much worse on a 10+ than on N7. So they didn't really have a top-end - a 3090 is really more comparable to what they could have gotten out of a full-die x104 on N7, but 754mm2 is as big as they could go on Samsung 8. That is part of why the 4090 towers above the rest of the lineup in a way the 3090 didn't. 30-series didn't really have a high-end part, they had "castoffs" (full dies) from the mainstream-enthusiast part that happened to have a little extra headroom.

A little bit of product strategy - you put your cutdowns at the high-value points of your lineup. GTX 970 and 980 Ti being cutdowns, 1080 Ti being a cutdown, etc. In CPUs, that's where AMD puts the 3600 and 3900X, and Intel puts the 5820K, etc. With Ampere, NVIDIA went as big as possible, then put the 3080 as being the GA102 cutdown, to make it a great value. Same for 3060 Ti. And the 3090 and the 3070 are the bloopers that result from the full-die chips being more expensive. But with the AD102 die being 754mm2 already (fucking enormous), that's as good as they could do on Samsung 8nm, so they kind of abandoned the true top-end stuff.

That was the strategy on 8nm - big dies on a shitty node, and make the 3080 a cutdown to take advantage of it. And on Turing it was the 2080 Ti (because 12FFN was the same node as Pascal was on, it's a 16nm with no optical shrink just the "your mom sized" reticle limit) plus pushing some of those "non-raster" performance-scaling approaches like DLSS.

They also needed to bring in a custom memory tech (GDDR6X is NVIDIA-exclusive) to keep costs down - Samsung 8nm has terrible SRAM density compared to TSMC N7 so the "infinity cache" strategy is off the table (or at least you'd need to stack it, and the packaging step drives up costs a lot too). 512b buses are tough to route these days and a lot of people don't think it's possible anymore with tighter integrity requirements (again, maybe it'd be possible with fanout packaging which, quelle surprise, drives up costs). But PAM4 lets you move a lot more data per clock edge using basically the same IC form-factor. The only real alternative would have been HBM2 which would also have driven up costs. So NVIDIA traded a custom memory tech to allow them to use a shitty node that they could get cheaply and produce these massive, fairly low-clocked dies on what amounts to an overgrown smartphone node, all in the name of cost reduction and bending MSRPs downwards ($399 3060 Ti, $699 3080). And miners royally fucked it all up, yet again.

But anyway to go back to the original point - this gap has always existed, AMD just appeared competitive because they were using a better, more expensive node, and they took it on the chin in margins as a result. And now that NVIDIA has moved back to a leading node (very leading in fact) the gap has reappeared. People just didn't want to do the math on comparing products across two nodes and realize the gap was always there, but people like me have been saying something along the lines of "RDNA1 isn't all that great considering it's N7 vs 16nm and NVIDIA still is slightly ahead on perf/w" and "RDNA2 is moving forward but it's still barely beating NVIDIA even though they're using a garbage Samsung 10+ node" quite frequently and we got shouted down.

I agree that it seems like RDNA3 missed somewhere though. The efficiency gains are massively lower than what AMD promised in their earlier slides, the performance seems disappointing. Maybe our expectations were just mis-calibrated, and maybe the marketing slides were just cooked, but it does seem like it missed some target by 20-30% and nobody external knows what the specific reason is.